MCU name: RL78/F13(ROM:128KB)
Chip name: R5F10BLG

Module | Macro | Sub | Setting | Status
Clock Generator |  |  |  | Used
| CGC |  |  | Used
|  |  | PIOR00 / TI00 | P17
|  |  | PIOR01 / TI01 | P30
|  |  | PIOR02 / TI02 | P16
|  |  | PIOR03 / TI03 | P125
|  |  | PIOR04 / TI04 | P13
|  |  | PIOR05 / TI05 | P15
|  |  | PIOR06 / TI06 | P14
|  |  | PIOR07 / TI07 | P120
|  |  | PIOR10 / TO00 | P17
|  |  | PIOR11 / TO01 | P30
|  |  | PIOR12 / TO02 | P16
|  |  | PIOR13 / TO03 | P125
|  |  | PIOR14 / TO04 | P13
|  |  | PIOR15 / TO05 | P15
|  |  | PIOR16 / TO06 | P14
|  |  | PIOR17 / TO07 | P120
|  |  | PIOR40 / RXD0/SI00/SDA00 | P16
|  |  | PIOR40 / TXD0/SO00 | P15
|  |  | PIOR40 / _SCK00/SCL00 | P17
|  |  | PIOR40 / _SSI00 | P30
|  |  | PIOR41 / SO01 | P120
|  |  | PIOR41 / SI01 | P13
|  |  | PIOR41 / _SCK01 | P14
|  |  | PIOR41 / _SSI01 | P125
|  |  | PIOR41 / SCL01 | P14
|  |  | PIOR41 / SDA01 | P13
|  |  | PIOR42 / RXD1/SI10 | P11
|  |  | PIOR42 / TXD1/SO10 | P12
|  |  | PIOR42 / _SCK10 | P10
|  |  | PIOR42 / _SSI10 | -
|  |  | PIOR42 / SCL10 | P10
|  |  | PIOR42 / SDA10 | P11
|  |  | PIOR43 / SO11 | P72
|  |  | PIOR43 / SI11 | P70
|  |  | PIOR43 / _SCK11 | P71
|  |  | PIOR43 / _SSI11 | P73
|  |  | PIOR43 / SCL11 | P71
|  |  | PIOR43 / SDA11 | P70
|  |  | PIOR44 / LTxD0 | P13
|  |  | PIOR44 / LRxD0 | P14
|  |  | PIOR46 / CTxD0 | P10
|  |  | PIOR46 / CRxD0 | P11
|  |  | PIOR50 / KR0 | P70
|  |  | PIOR50 / KR1 | P71
|  |  | PIOR50 / KR2 | P72
|  |  | PIOR50 / KR3 | P73
|  |  | PIOR50 / KR4 | P74
|  |  | PIOR50 / KR5 | P75
|  |  | PIOR50 / KR6 | P76
|  |  | PIOR50 / KR7 | P77
|  |  | PIOR52 / INTP2 | P30
|  |  | PIOR53 / INTP3 | P17
|  |  | PIOR70 / TRDCLK0/TRDIOA0 | P13
|  |  | PIOR71 / TRDIOB0 | P125
|  |  | PIOR73 / TRDIOD0 | P120
|  |  | Operation mode setting | High speed main mode 4.0 (V) ¡Ü VDD ¡Ü 5.5 (V)
|  |  | Main system clock (fMAIN) setting | High-speed system clock (fMX)
|  |  | fIH operation | Unused
|  |  | fMX operation | Used
|  |  | High-speed system clock setting | X1 oscillation (fX)
|  |  | fMX frequency | 8(MHz)
|  |  | Stable time | 32768 (2^18/fX)(¦Ìs)
|  |  | fPLL operation | Used
|  |  | fPLL frequency | 32(MHz)
|  |  | Lockup wait counter | 64 (2^9/fMAIN)(¦Ìs)
|  |  | PLL output for main system clock (fMP) setting | 32 (fPLL)(MHz)
|  |  | fSUB operation | Unused
|  |  | Internal low-speed oscillation clock (fIL) setting | 15(kHz)
|  |  | Low speed on-chip oscillator clock (fSL) setting | 15 (fIL)(kHz)
|  |  | WDT operation clock (fWDT) setting | 15(kHz)
|  |  | RTC operation clock | 65.57 (fMX/122)(kHz)
|  |  | Timer RD operation clock | 32000 (fCLK)(kHz)
|  |  | CPU and peripheral clock (fCLK) | 32000 (fMP)(kHz)
|  |  | On-chip debug operation setting | Used
|  |  | RRM function setting | Used
|  |  | Trace function setting | Used
|  |  | Hot plug-in function setting | Unused
|  |  | Security ID setting | Used
|  |  | Security ID | 0x00000000000000000000
|  |  | Security ID authentication failure setting | Erase flash memory data
|  |  | Output the function for confirming reset source | Used
|  |  | RESOUT pin setting | P130 used as port pin
|  |  | Illegal memory access detection function setting | Unused
|  |  | RAM guard function setting | Unused
|  |  | Port register guard function setting | Unused
|  |  | Interrupt register guard function setting | Unused
|  |  | Chip state control register guard function setting | Unused
|  |  | Detection of 1 bit error detection interrupt (INTRAM) | Unused
|  |  | CPU stack pointer monitor function setting | Unused
|  |  | Clock monitor function setting | Unused
|  |  | Data flash access control setting | Disables data flash access
Port |  |  |  | Used
| PORT |  |  | Used
|  | P00 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P12 |  |
|  |  | Mode | Out
|  |  | N-ch | Unused
|  |  | output value | 0
|  | P15 |  |
|  |  | Mode | Out
|  |  | N-ch | Unused
|  |  | output value | 0
|  | P16 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P17 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P31 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P32 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  | P50 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P51 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P52 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P60 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P63 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P70 |  |
|  |  | Mode | Out
|  |  | N-ch | Unused
|  |  | output value | 0
|  | P71 |  |
|  |  | Mode | Out
|  |  | N-ch | Unused
|  |  | output value | 0
|  | P72 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  | P73 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P74 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  | P75 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P76 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P77 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P90 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P91 |  |
|  |  | Mode | In
|  | P92 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P93 |  |
|  |  | Mode | In
|  | P95 |  |
|  |  | Mode | In
|  | P96 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P125 |  |
|  |  | Mode | In
|  |  | Pull-up | Unused
|  |  | Schmitt1 buffer | Used
|  | P130 |  |
|  |  | Mode | Out
|  |  | output value | 0
|  | P140 |  |
|  |  | Mode | Out
|  |  | output value | 0
Interrupt |  |  |  | Unused
Serial |  |  |  | Unused
A/D Converter |  |  |  | Used
| ADC |  |  | Used
|  |  | A/D convertor operation setting | Used
|  |  | Comparator operation setting | Stop
|  |  | Resolution setting | 10 bits
|  |  | VREF(+) setting | VDD
|  |  | VREF(-) setting | VSS
|  |  | Trigger mode setting | Software trigger mode
|  |  | Operation mode setting | One-shot select mode
|  |  | ANI0 - ANI15 analog input selection | ANI0 - ANI9
|  |  | ANI24 - ANI26 analog input selection | ANI27, ANI28, ANI29, ANI30
|  |  | A/D channel selection | ANI0
|  |  | Conversion time mode | Normal 1
|  |  | Conversion time | 4.75 (152/fCLK)(¦Ìs)
|  |  | Conversion result upper/lower bound value setting | Generates an interrupt request (INTAD) when ADLL ¡Ü ADCRH ¡Ü ADUL
|  |  | Upper bound (ADUL) value | 255
|  |  | Lower bound (ADLL) value | 0
|  |  | Use A/D interrupt (INTAD) | Unused
Timer |  |  |  | Used
| TAU0 |  |  | Used
|  | Channel0 |  |
|  |  | Channel 0 | PWM output (master)
|  |  | Cycle value | 200¦Ìs, (Actual value: 200)
|  |  | End of timer channel 0 count, generate an interrupt (INTTM00) | Unused
|  |  | Duty value | 0(%), (Actual value: 0%)
|  |  | Initial output value | 0
|  |  | Output level | Active-high
|  |  | Output delay time | No delay
|  |  | Slow mode | Unused
|  |  | End of timer channel 1 count, generate an interrupt (INTTM01) | Unused
|  | Channel1 |  |
|  |  | Channel 1 | PWM output (slave)
|  | Channel2 |  |
|  |  | Channel 2 | Interval timer
|  |  | Interval value (16 bits) | 1ms, (Actual value: 1)
|  |  | Generates INTTM02 when counting is started | Unused
|  |  | End of timer channel 2 count, generate an interrupt (INTTM02) | Used
|  |  | Priority (INTTM02) | Low
| TAU1 |  |  | Unused
| TMRJ0 |  |  | Unused
| TMRD0 |  |  | Unused
| TMRD1 |  |  | Unused
Watchdog Timer |  |  |  | Used
| WDT |  |  | Used
|  |  | Watchdog timer operation setting | Used
|  |  | Operation in HALT/STOP/SNOOZE mode setting | Enabled
|  |  | Overflow time | 4369.07 (2^16/fWDT)(ms)
|  |  | Window open period | 100(%)
|  |  | Enable interval interrupt when 75% + 1/2fIL of overflow time (INTWDTI) | Used
|  |  | Priority | Low
Real-time Clock |  |  |  | Unused
Data Transfer Controller |  |  |  | Unused
Clock Output/Buzzer Output |  |  |  | Unused
Voltage Detector |  |  |  | Unused