From c9428891ade732b6da3ca20d99c86cd7a5844c3d Mon Sep 17 00:00:00 2001 From: sunbeam Date: Mon, 23 Dec 2024 11:04:44 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E7=89=88?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .cproject | 157 + .cwGeneratedFileSetLog | 8 + .gitignore | 1 + .project | 25 + ...com.freescale.core.ide.cdt.toolchain.prefs | 25 + ....freescale.core.ide.newprojectwizard.prefs | 2 + .settings/org.eclipse.core.resources.prefs | 2 + .vscode/launch.json | 7 + .vscode/settings.json | 9 + .vscode/tasks.json | 28 + LIN_Stack/bsp/SCI/lin_isr.c | 1133 ++ LIN_Stack/bsp/SCI/lin_lld_sci.c | 3307 +++++ LIN_Stack/bsp/SCI/lin_lld_sci.h | 811 ++ LIN_Stack/bsp/SCI/lin_lld_timesrv.c | 423 + LIN_Stack/bsp/SCI/lin_lld_timesrv.h | 130 + LIN_Stack/bsp/SCI/lin_reg.h | 991 ++ LIN_Stack/coreapi/lin_common_api.c | 246 + LIN_Stack/coreapi/lin_common_proto.c | 1601 +++ LIN_Stack/coreapi/lin_j2602_api.c | 50 + LIN_Stack/coreapi/lin_j2602_proto.c | 210 + LIN_Stack/coreapi/lin_lin21_api.c | 33 + LIN_Stack/coreapi/lin_lin21_proto.c | 300 + LIN_Stack/diagnostic/lin_diagnostic_service.c | 689 + LIN_Stack/include/lin_common_api.h | 301 + LIN_Stack/include/lin_common_proto.h | 804 ++ LIN_Stack/include/lin_commontl_api.h | 868 ++ LIN_Stack/include/lin_commontl_proto.h | 576 + LIN_Stack/include/lin_diagnostic_service.h | 293 + LIN_Stack/include/lin_j2602_api.h | 72 + LIN_Stack/include/lin_j2602_proto.h | 144 + LIN_Stack/include/lin_j2602tl_api.h | 122 + LIN_Stack/include/lin_lin21_api.h | 35 + LIN_Stack/include/lin_lin21_proto.h | 247 + LIN_Stack/include/lin_lin21tl_api.h | 321 + LIN_Stack/lowlevel/lin.c | 1152 ++ LIN_Stack/lowlevel/lin.h | 1822 +++ LIN_Stack/mainpage.h | 340 + LIN_Stack/transport/lin_commontl_api.c | 1359 ++ LIN_Stack/transport/lin_commontl_proto.c | 2085 +++ LIN_Stack/transport/lin_j2602tl_api.c | 146 + LIN_Stack/transport/lin_lin21tl_api.c | 425 + Lib/mc9s12zvl32.c | 314 + Project_Headers/derivative.h | 155 + Project_Headers/diagnostic_service_slave.h | 24 + Project_Headers/mc9s12zvl32.h | 11137 ++++++++++++++++ Project_Settings/Linker_Files/mc9s12zvl32.prm | 51 + Project_Settings/Startup_Code/starts12z.c | 102 + ReferencedRSESystems.xml | 100 + Sources/AD1.c | 203 + Sources/AD1.h | 51 + Sources/Button.c | 171 + Sources/Button.h | 19 + Sources/CPU.c | 190 + Sources/CPU.h | 19 + Sources/DMK-BC316-77.c | 346 + Sources/DMK-BC316-77.h | 71 + Sources/PWM1.c | 204 + Sources/PWM1.h | 168 + Sources/TI1.c | 40 + Sources/TI1.h | 8 + Sources/WDog1.c | 142 + Sources/WDog1.h | 145 + Sources/diagnostic/diagnostic_DID.c | 143 + Sources/diagnostic/diagnostic_DID.h | 47 + Sources/diagnostic/diagnostic_service_slave.c | 453 + Sources/diagnostic/diagnostic_service_slave.h | 57 + Sources/main.c | 33 + lin_cfg/LDF_DMK-BC316-77.ldf | 169 + lin_cfg/NPF_DMK-BC316-77.npf | 49 + lin_cfg/lin_cfg.c | 226 + lin_cfg/lin_cfg.h | 1415 ++ lin_cfg/lin_hw_cfg.h | 92 + 72 files changed, 37644 insertions(+) create mode 100644 .cproject create mode 100644 .cwGeneratedFileSetLog create mode 100644 .gitignore create mode 100644 .project create mode 100644 .settings/com.freescale.core.ide.cdt.toolchain.prefs create mode 100644 .settings/com.freescale.core.ide.newprojectwizard.prefs create mode 100644 .settings/org.eclipse.core.resources.prefs create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 .vscode/tasks.json create mode 100644 LIN_Stack/bsp/SCI/lin_isr.c create mode 100644 LIN_Stack/bsp/SCI/lin_lld_sci.c create mode 100644 LIN_Stack/bsp/SCI/lin_lld_sci.h create mode 100644 LIN_Stack/bsp/SCI/lin_lld_timesrv.c create mode 100644 LIN_Stack/bsp/SCI/lin_lld_timesrv.h create mode 100644 LIN_Stack/bsp/SCI/lin_reg.h create mode 100644 LIN_Stack/coreapi/lin_common_api.c create mode 100644 LIN_Stack/coreapi/lin_common_proto.c create mode 100644 LIN_Stack/coreapi/lin_j2602_api.c create mode 100644 LIN_Stack/coreapi/lin_j2602_proto.c create mode 100644 LIN_Stack/coreapi/lin_lin21_api.c create mode 100644 LIN_Stack/coreapi/lin_lin21_proto.c create mode 100644 LIN_Stack/diagnostic/lin_diagnostic_service.c create mode 100644 LIN_Stack/include/lin_common_api.h create mode 100644 LIN_Stack/include/lin_common_proto.h create mode 100644 LIN_Stack/include/lin_commontl_api.h create mode 100644 LIN_Stack/include/lin_commontl_proto.h create mode 100644 LIN_Stack/include/lin_diagnostic_service.h create mode 100644 LIN_Stack/include/lin_j2602_api.h create mode 100644 LIN_Stack/include/lin_j2602_proto.h create mode 100644 LIN_Stack/include/lin_j2602tl_api.h create mode 100644 LIN_Stack/include/lin_lin21_api.h create mode 100644 LIN_Stack/include/lin_lin21_proto.h create mode 100644 LIN_Stack/include/lin_lin21tl_api.h create mode 100644 LIN_Stack/lowlevel/lin.c create mode 100644 LIN_Stack/lowlevel/lin.h create mode 100644 LIN_Stack/mainpage.h create mode 100644 LIN_Stack/transport/lin_commontl_api.c create mode 100644 LIN_Stack/transport/lin_commontl_proto.c create mode 100644 LIN_Stack/transport/lin_j2602tl_api.c create mode 100644 LIN_Stack/transport/lin_lin21tl_api.c create mode 100644 Lib/mc9s12zvl32.c create mode 100644 Project_Headers/derivative.h create mode 100644 Project_Headers/diagnostic_service_slave.h create mode 100644 Project_Headers/mc9s12zvl32.h create mode 100644 Project_Settings/Linker_Files/mc9s12zvl32.prm create mode 100644 Project_Settings/Startup_Code/starts12z.c create mode 100644 ReferencedRSESystems.xml create mode 100644 Sources/AD1.c create mode 100644 Sources/AD1.h create mode 100644 Sources/Button.c create mode 100644 Sources/Button.h create mode 100644 Sources/CPU.c create mode 100644 Sources/CPU.h create mode 100644 Sources/DMK-BC316-77.c create mode 100644 Sources/DMK-BC316-77.h create mode 100644 Sources/PWM1.c create mode 100644 Sources/PWM1.h create mode 100644 Sources/TI1.c create mode 100644 Sources/TI1.h create mode 100644 Sources/WDog1.c create mode 100644 Sources/WDog1.h create mode 100644 Sources/diagnostic/diagnostic_DID.c create mode 100644 Sources/diagnostic/diagnostic_DID.h create mode 100644 Sources/diagnostic/diagnostic_service_slave.c create mode 100644 Sources/diagnostic/diagnostic_service_slave.h create mode 100644 Sources/main.c create mode 100644 lin_cfg/LDF_DMK-BC316-77.ldf create mode 100644 lin_cfg/NPF_DMK-BC316-77.npf create mode 100644 lin_cfg/lin_cfg.c create mode 100644 lin_cfg/lin_cfg.h create mode 100644 lin_cfg/lin_hw_cfg.h diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..0c1b2e3 --- /dev/null +++ b/.cproject @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.cwGeneratedFileSetLog b/.cwGeneratedFileSetLog new file mode 100644 index 0000000..6b5f2b9 --- /dev/null +++ b/.cwGeneratedFileSetLog @@ -0,0 +1,8 @@ +Sources/main.c +Project_Settings/Linker_Files/mc9s12zvl32.prm +Project_Settings/Startup_Code/starts12z.c +Project_Headers/derivative.h +Project_Headers/mc9s12zvl32.h +Lib/mc9s12zvl32.c +.settings/com.freescale.core.ide.newprojectwizard.prefs +ReferencedRSESystems.xml diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..2ab2dd8 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/FLASH diff --git a/.project b/.project new file mode 100644 index 0000000..3f75096 --- /dev/null +++ b/.project @@ -0,0 +1,25 @@ + + + DMK-EBO-77A-SW0312 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/com.freescale.core.ide.cdt.toolchain.prefs b/.settings/com.freescale.core.ide.cdt.toolchain.prefs new file mode 100644 index 0000000..ed89937 --- /dev/null +++ b/.settings/com.freescale.core.ide.cdt.toolchain.prefs @@ -0,0 +1,25 @@ +eclipse.preferences.version=1 +hotfix/arm.cdt.toolchain.ErrorParserHotFix=true +hotfix/arm.cdt.toolchain.UIElementValueTypeUpdate=true +hotfix/class\ com.freescale.core.ide.cdt.toolchain.ProjectErrorParserHotFix=true +hotfix/class\ com.freescale.core.ide.cdt.toolchain.QuotePathsHotFix=true +hotfix/class\ com.freescale.core.ide.cdt.toolchain.ToolOptionsUpdateHotFix=true +hotfix/class\ com.freescale.core.ide.cdt.toolchain.UiElementValueTypeHotFix=true +hotfix/coldfire.cdt.toolchain.UIElementValueTypeUpdate=true +hotfix/com.freescale.arm.cdt.toolchain=true +hotfix/com.freescale.arm.cdt.toolchain.ToolOptionsUpdate.fileAndProgram_v1=true +hotfix/com.freescale.coldfire.cdt.gcc.toolchain=true +hotfix/com.freescale.coldfire.cdt.toolchain=true +hotfix/com.freescale.coldfire.toolchain.ToolOptionsUpdate.fileAndProgram_v1=true +hotfix/com.freescale.core.ide.util.pbhotfix=true +hotfix/com.freescale.dsc.cdt.toolchain=true +hotfix/com.freescale.hc08.cdt.toolchain=true +hotfix/com.freescale.hc08.cdt.toolchain.FixCommandLinePatternHotFix=true +hotfix/com.freescale.hc08.cdt.toolchain.hc08.cdt.toolchain.UIElementValueTypeUpdate=true +hotfix/com.freescale.ppc.cdt.toolchain=true +hotfix/com.freescale.ppc.toolchain.ToolOptionsUpdate.fileAndProgram_v1=true +hotfix/com.freescale.ppc.toolchain.UIElementValueTypeUpdate.toSymbolFiles=true +hotfix/com.freescale.s12z.cdt.toolchain=true +hotfix/com.freescale.s12z.cdt.toolchain.LibOptionsHotFix=true +hotfix/dsc.cdt.toolchain.UIElementValueTypeUpdate=true +hotfix/s12z.cdt.toolchain.UIElementValueTypeUpdate=true diff --git a/.settings/com.freescale.core.ide.newprojectwizard.prefs b/.settings/com.freescale.core.ide.newprojectwizard.prefs new file mode 100644 index 0000000..cb39b54 --- /dev/null +++ b/.settings/com.freescale.core.ide.newprojectwizard.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +versionGenerated/versionGenerated=1.10.1.FSL_mcu105_5051 diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..c37489c --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding//LIN_Stack/bsp/SCI/lin_lld_sci.c=UTF-8 diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..f980ab9 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,7 @@ +{ + // 使用 IntelliSense 了解相关属性。 + // 悬停以查看现有属性的描述。 + // 欲了解更多信息，请访问: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..0c13b29 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + "editor.renderLineHighlight": "all", + "files.associations": { + "lin_diagnostic_service.h": "c", + "lin_commontl_proto.h": "c", + "lin.h": "c", + "derivative.h": "c" + } +} \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..96998c2 --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,28 @@ +{ + "tasks": [ + { + "type": "cppbuild", + "label": "C/C++: gcc.exe 生成活动文件", + "command": "D:\\MinGW-w64\\mingw64\\bin\\gcc.exe", + "args": [ + "-fdiagnostics-color=always", + "-g", + "${file}", + "-o", + "${fileDirname}\\${fileBasenameNoExtension}.exe" + ], + "options": { + "cwd": "${fileDirname}" + }, + "problemMatcher": [ + "$gcc" + ], + "group": { + "kind": "build", + "isDefault": true + }, + "detail": "调试器生成的任务。" + } + ], + "version": "2.0.0" +} \ No newline at end of file diff --git a/LIN_Stack/bsp/SCI/lin_isr.c b/LIN_Stack/bsp/SCI/lin_isr.c new file mode 100644 index 0000000..463e71f --- /dev/null +++ b/LIN_Stack/bsp/SCI/lin_isr.c @@ -0,0 +1,1133 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup SCI_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file bsp/SCI/lin_isr.c +* +* @author FPT Software +* +* @brief Interrupt service routine used in LIN driver +* +******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * 20101027 v1.0 First version + * 20111005 v1.1 Updated hardware support, multi timers + * 20111121 v1.2 Updated interrupt service routine for 9S12J637 + * 20140728 v1.3 Add AUTOBAUD feature + * + *****************************************************************************/ +#include "lin_hw_cfg.h" +#include "lin_lld_timesrv.h" +#include "lin_lld_sci.h" + +#if AUTOBAUD == 1 /* AUTOBAUD feature applicible for S12Z MCU family*/ +#include "lin_lld_autobaud.h" + +extern l_u16 lin_max_frame_res_timeout_val_autobaud[8]; +volatile l_bool stop_flag = 0; +l_u16 dTbit[5] = {0}; + +#endif /* End (1==AUTOBAUD) */ + + +#if defined(_MC9S12I32_H) +#include "analog_die_reg.h" + +volatile unsigned char sci_isr_flag = 0; +volatile unsigned char j = 0; +volatile unsigned char i=0; +volatile unsigned char ivr = 0; +volatile unsigned char scis = 0; +volatile unsigned char isrhi =0; +volatile unsigned char isrlo = 0; + +#pragma CODE_SEG NON_BANKED + +interrupt void D2D_ISR(void) +{ + ivr = IVR; + isrhi = ISRhi; + isrlo = ISRlo; + scis = SCIS1; + + if(isrhi&0x01) + { + sci_isr_flag = 1; + scis = SCIS1; + + lin_lld_sci_rx_isr(); + /* remove interrupt flag */ + SCIS1 = scis; + } + else if(isrlo&0x40) + { + lin_lld_sci_err_isr(); + } + else if (isrlo&0x10) + { + lin_lld_sci_timeout(); + /* Write 1 to TFLG1 C3F to clear C3F flag*/ + TFLG1 |= 0x08; + } +} + +#pragma CODE_SEG DEFAULT + +#elif defined (_MC9S12I128_H) +#include "mm912j637.h" + +#pragma CODE_SEG NON_BANKED + +void _D2DERR(void); /* 0xFFF4 D2DI Error Interrupt */ +void _D2D(void); /* 0xFFF2 D2DI External Error Interrupt */ + +#pragma TRAP_PROC +void _dummyISR( void ) +{ + /* endless loop */ + for(;;); +} + +#pragma TRAP_PROC +void _D2D(void) +{ + volatile l_u8 reg_temp = 0x00; + reg_temp = INT_VECT; + switch (reg_temp) + { + case 0x04: + _TFLG1.Bits.C0F = 1; + break; + + case 0x07: + _TFLG1.Bits.C3F = 1; + lin_lld_timer_isr(); + break; + + case 0x9: + lin_lld_sci_err_isr(); + break; + + case 0xB: + lin_lld_sci_rx_isr(); + break; + + default: + break; + } +} + +#pragma CODE_SEG DEFAULT + +#elif defined (_MM9Z1J638_H) +#include "mm9z1j638.h" + +interrupt _D2D(void); + +interrupt _D2D(void) +{ + volatile l_u8 reg_temp = 0x00; + reg_temp = B_INT_VECT; + switch (reg_temp) + { + case 0x04: + B_TFLG1_C0F = 1; + break; + + case 0x07: + B_TFLG1_C3F = 1; + lin_lld_timer_isr(); + break; + + case 0x9: + #if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_err_isr(); + #else + lin_lld_sci_err_isr(SCI0); + #endif + break; + + case 0xB: + #if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_rx_isr(); + #else + lin_lld_sci_rx_isr(SCI0); + #endif + break; + + default: + break; + } +} + +#pragma CODE_SEG DEFAULT + +#else + +/** +* @def ISR(ivn, x) +* Call function x with interrupt vector number is ivn +*/ +#define ISR(ivn, x) interrupt ivn void x(void) + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +/* Change vector number define */ +#if (NUM_OF_SCI_CHANNEL == 1) && (!defined(_MC9S12GN32_H)) && (!defined(_MC9S12ZVMA_H)) +#define VectorNumber_Vsci0 VectorNumber_Vsci +#define SCI0_INT SCI_INT +#endif /* End (NUM_OF_SCI_CHANNEL == 1) && !defined(_MC9S12GN32_H) */ +/* End Change vector number define */ +#if ((!defined(_MC9S12ZVML128_H)) && (!defined(_MC9S12ZVL32_H))&&(!defined(_MC9S12ZVML31_H))) +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Define a specific segment to store the code */ +#endif /*End if ((!defined(_MC9S12ZVML128_H)) && (!defined(_MC9S12ZVL32_H))&&(!defined(_MC9S12ZVML31_H)))*/ + +#if _SCI0_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci0, SCI0_INT) +* @brief interrupt service routine for SCI0 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +void SCI0_INT(void); +ISR(VectorNumber_Vsci0, SCI0_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI0_ == 1) */ + +#if _SCI1_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci1, SCI1_INT) +* @brief interrupt service routine for SCI1 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI1 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1, SCI1_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI1); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI1_ == 1) */ + +#if _SCI2_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci2, SCI2_INT) +* @brief interrupt service routine for SCI2 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI2 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci2, SCI2_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI2); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI2_ == 1) */ + +#if _SCI3_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci3, SCI3_INT) +* @brief interrupt service routine for SCI3 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI3 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci3, SCI3_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI3); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI3_ == 1)*/ + +#if _SCI4_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci4, SCI4_INT) +* @brief interrupt service routine for SCI4 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI4 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci4, SCI4_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI4); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI4_ ==1) */ + +#if _SCI5_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ISR(VectorNumber_Vsci5, SCI5_INT) +* @brief interrupt service routine for SCI5 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI5 receiver +* +* @see #lin_lld_sci_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci5, SCI5_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_isr(); +#else + lin_lld_sci_isr(SCI5); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (_SCI5_ == 1) */ +#endif /* End (SCI_VERSION == SCI_V5) */ + +#if (SCI_VERSION == SCI_V4) +/* Change vectorNumber define */ +#if (NUM_OF_SCI_CHANNEL == 1) + +#define VectorNumber_Vsci1tx VectorNumber_Vscitx +#define VectorNumber_Vsci1rx VectorNumber_Vscirx +#define VectorNumber_Vsci1err VectorNumber_Vscierr + +#endif +/* End Change vectorNumber define */ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Define a specific segment to store the code */ + +#if _SCI0_ == 1 +#if defined(_MC9S08RN60_H) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_TX_INT (void) +* @brief interrupt service routine for SCI0 transmiter +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 transmiter +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci0tx, SCI0_TX_INT) +{ +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_RX_INT(void) +* @brief interrupt service routine for SCI0 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 receiver +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci0rx, SCI0_RX_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_rx_isr(); +#else + lin_lld_sci_rx_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_ERR_INT( void ) +* @brief interrupt service routine for SCI0 error +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 error +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci0err, SCI0_ERR_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_err_isr(); +#else + lin_lld_sci_err_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#else +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_TX_INT (void) +* @brief interrupt service routine for SCI0 transmiter +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 transmiter +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1tx, SCI1_TX_INT) +{ + +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_RX_INT(void) +* @brief interrupt service routine for SCI0 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 receiver +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1rx, SCI1_RX_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_rx_isr(); +#else + lin_lld_sci_rx_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI1_ERR_INT( void ) +* @brief interrupt service routine for SCI0 error +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 error +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1err, SCI1_ERR_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_err_isr(); +#else + lin_lld_sci_err_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* defined(_MC9S08RN60_H) */ +#endif /* End _SCI0_ == 1 */ + + +#if _SCI1_ == 1 +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI2_TX_INT (void) +* @brief interrupt service routine for SCI1 transmiter +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI1 transmiter +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci2tx, SCI2_TX_INT) +{ + +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI2_RX_INT (void) +* @brief interrupt service routine for SCI1 receiver +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI1 receiver +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci2rx, SCI2_RX_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_rx_isr(); +#else + lin_lld_sci_rx_isr(SCI1); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI2_ERR_INT (void) +* @brief interrupt service routine for SCI1 error +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI1 error +* +* @see #lin_lld_sci_rx_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci2err, SCI2_ERR_INT) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_sci_err_isr(); +#else + lin_lld_sci_err_isr(SCI1); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End _SCI1_ == 1 */ +#endif /* End (SCI_VERSION == SCI_V4) */ + +#if (SCI_VERSION == SCI_V2) +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Define a specific segment to store the code */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI_RX_INT (void ) +* @brief interrupt service routine for SCI0 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 +* +* @see #lin_lld_xgate_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1rx, SCI_RX_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_rx_isr(); +#else + lin_lld_sci_rx_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void SCI_ERR_INT(void) +* @brief interrupt service routine for SCI0 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for SCI0 +* +* @see #lin_lld_xgate_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vsci1err, SCI_ERR_INT) +{ +#if (LIN_MODE == _SLAVE_MODE_) + lin_lld_sci_err_isr(); +#else + lin_lld_sci_err_isr(SCI0); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} +#endif /* End (SCI_VERSION == SCI_V2) */ + + +#if (_MCU_ == _S12X_) +#ifdef MULTI_TIMER_MODE +#if (_PIT0_ == 1) +ISR(VectorNumber_Vpit0, PIT0_TIMER_ISR) +{ + lin_lld_timer_isr(PIT0_INDEX); + __asm + { + MOVB #$01,PITTF + } +} +#endif /* (_PIT0_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT1_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT1 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT1 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT1_ == 1) +/****CONGTH****/ +ISR(VectorNumber_Vpit1, PIT1_TIMER_ISR) +{ + lin_lld_timer_isr(PIT1_INDEX); + __asm + { + MOVB #$02,PITTF + } +} +#endif /* (_PIT1_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT2_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT2 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT2 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT2_ == 1) +ISR(VectorNumber_Vpit2, PIT2_TIMER_ISR) +{ + lin_lld_timer_isr(PIT2_INDEX); + __asm + { + MOVB #$04,PITTF + } +} +#endif /* (_PIT2_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT3_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT3 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT3 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT3_ == 1) +ISR(VectorNumber_Vpit3, PIT3_TIMER_ISR) +{ + lin_lld_timer_isr(PIT3_INDEX); + __asm + { + MOVB #$08,PITTF + } +} +#endif /* (_PIT3_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT4_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT4 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT4 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT4_ == 1) +/****CONGTH****/ +ISR(VectorNumber_Vpit4, PIT4_TIMER_ISR) +{ + lin_lld_timer_isr(PIT4_INDEX); + __asm + { + MOVB #$10,PITTF + } +} +#endif /* End (_PIT4_ == 1) */ + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT5_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT5 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT5 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ + +#if (_PIT5_ == 1) +/****CONGTH****/ +ISR(VectorNumber_Vpit5, PIT5_TIMER_ISR) +{ + lin_lld_timer_isr(PIT5_INDEX); + __asm + { + MOVB #$20,PITTF + } +} +#endif /* End (_PIT6_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT6_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT6 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT6 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT6_ == 1) +/****CONGTH****/ +ISR(VectorNumber_Vpit6, PIT6_TIMER_ISR) +{ + lin_lld_timer_isr(PIT6_INDEX); + __asm + { + MOVB #$40,PITTF + } +} +#endif /* End (_PIT6_ == 1) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT7_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT7 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT7 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (_PIT7_ == 1) +/****CONGTH****/ +ISR(VectorNumber_Vpit7, PIT7_TIMER_ISR) +{ + lin_lld_timer_isr(PIT7_INDEX); + __asm + { + MOVB #$80,PITTF + } +} +#endif /* End (_PIT7_ == 1) */ + +#else /* Else MULTI_TIMER_MODE */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void PIT0_TIMER_ISR (void) +* @brief interrupt interrupt service routine for PIT0 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for PIT0 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vpit0, PIT0_TIMER_ISR) +{ + lin_lld_timer_isr(); + PITTF_PTF0 = 1; +} + +#endif /* End MULTI_TIMER_MODE */ +#endif /* End (_MCU_ == _S12X_) */ + +#if (_MCU_ == _S12_) +#if defined(_MC9S12XHY256_H) || defined(_MC9S12HY64_H) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TIM0CH7_TIMER_ISR (void) +* @brief interrupt interrupt service routine for TIM0 +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for TIM0 +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vtim0ch7, TIM0CH7_TIMER_ISR) +{ + lin_lld_timer_isr(); + /* Reset interrupt request flag */ + TIM0_TFLG1 = 128; +} +#endif /* End for 9S12XHY256 and 9S12HY64 */ + +#if defined(_MC9S12P128_H) || defined(_MC9S12XS128_H) || defined(_MC9S12XS256_H) || defined(_MC9S12G128_H) || defined(_MC9S12G240_H) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TIM0_TIMER_ISR (void) +* @brief interrupt interrupt service routine for TIM timer +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for TIM timer +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vtimch7, TIM0_TIMER_ISR) +{ + lin_lld_timer_isr(); + TFLG1_C7F = 1; +} +#endif /* End for 9S12P128, 9S12XS128, 9S12XS256 and 9S12G128 */ + +#if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H)) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TIM0_TIMER_ISR (void) +* @brief interrupt interrupt service routine for TIM timer +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for TIM timer +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vtimch0, TIM_TIMER_ISR) +{ + lin_lld_timer_isr(); + /* Write 1 to TFLG1 C0F bit to clear this C0F flag*/ + TFLG1 = TFLG1_C0F_MASK; + TC0 = (TC0 + ((MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD) ) & 0xFFFF; +} + +#endif /* End if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H)) */ + +#if defined(_MC9S12GN32_H) || defined(_MC9S12G64_H) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TIM0_TIMER_ISR (void) +* @brief interrupt interrupt service routine for TIM timer +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for TIM timer +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +ISR(VectorNumber_Vtimch0, TIM_TIMER_ISR) +{ + lin_lld_timer_isr(); + /* Write 1 to TFLG1 C0F bit to clear this C0F flag*/ + TFLG1 = TFLG1_C0F_MASK; + TC0 = (TC0 + ((MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD) ) & 0xFFFF; +} + +#endif /* End defined(_MC9S12GN32_H) || defined(_MC9S12G64_H) */ + +#if ( defined(_MC9S12ZVL32_H) || defined(_MC9S12ZVL128_H) || \ +defined(_MC9S12ZVMA_H) || defined(_MC9S12ZVMB_H)) +#if (_SCI0_) + +void LinPhy_ISR(void); +ISR(VectorNumber_Vlinphy0, LinPhy_ISR) +{ + if(LP0IF_LPOCIF == 1) + { + LP0IF_LPOCIF = 1; + } +} +#endif /* END SCI0 */ +#endif /* END ifdef _MC9S12ZVL32_H */ + +#if (defined(_MC9S12ZVML128_H) || defined(_MC9S12ZVL32_H)||defined(_MC9S12ZVHY64_H)||defined(_MC9S12ZVH128_H)\ + ||defined(_MC9S12ZVML31_H)||defined(_MC9S12ZVMC256_H)||defined(_MC9S12ZVL128_H) ||defined(_MC9S12ZVMB_H)) +void TIMchan2_ISR(void); +ISR(VectorNumber_Vtim0ch2, TIMchan2_ISR) +{ + lin_lld_timer_isr(); + /* Write 1 to TFLG1 C2F bit to clear this C2F flag*/ + TIM0TFLG1 = TIM0TFLG1_C2F_MASK; + TIM0TC2 = (TIM0TC2 + ((MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD) ) & 0xFFFF; +} +#endif /* End if (defined(_MC9S12ZVML128_H) || defined(_MC9S12ZVL32_H)||defined(_MC9S12ZVHY64_H)||defined(_MC9S12ZVH128_H)||defined(_MC9S12ZVML31_H)) */ +#if (defined(_MC9S12ZVC64_H)) +ISR(VectorNumber_Vtim1ch2, TIMchan2_ISR) +{ + lin_lld_timer_isr(); + /* Write 1 to TFLG1 C2F bit to clear this C2F flag*/ + TIM0TFLG1 = TIM0TFLG1_C2F_MASK; + TIM1TC2 = (TIM1TC2 + ((MCU_BUS_FREQ/500000)*TIME_BASE_PERIOD) ) & 0xFFFF; +} +#endif + +#if (defined(_MC9S12ZVMA_H)||defined(_MC9S12VRP64_H)||defined(_MC9S12VRP48_H)) +void TIM1chan0_ISR(void); +ISR(VectorNumber_Vtim1ch0, TIM1chan0_ISR) +{ + lin_lld_timer_isr(); + /* Write 1 to TFLG1 C0F bit to clear this C0F flag*/ + TIM1TFLG1 = TIM1TFLG1_C0F_MASK; + TIM1TC0 = (TIM1TC0 + ((MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD) ) & 0xFFFF; +} +#endif /* End if (defined(_MC9S12ZVMA_H))||defined(_MC9S12VRP64_H)||defined(_MC9S12VRP48_H)) */ + + +#if (AUTOBAUD == 1) +void TIM_Input_capture_ISR(void); +void AutobaudTimerValEval(void) +{ + l_u8 i; + + /* Clear interrupt flag */ + CLEAR_TIMER_CHANNEL_INTERRUPT_FLAG; + + if ((0 == stop_flag) && (autobaud_tmr_capture_index < 5)) + { + + autobaud_tmr_capture[autobaud_tmr_capture_index]=TIMER_CNT_REG; + /* Calculate 2xTbit time for the second and later capture */ + if (autobaud_tmr_capture_index > 0) + { + i = autobaud_tmr_capture_index - 1; + dTbit[i] = autobaud_tmr_capture[i+1] - autobaud_tmr_capture[i]; + /* Check if 2xTbit time satisfy valid conditions: + * 1. The following 2xTbit must be +/-14% of the 2xTbit right before it + * 2. And it is in the acceptable ranges of master baud rate of 19200 bps or 9600 bps + */ + if ((dTbit[i] < DBIT_DURATION_MIN_19200) || + ((dTbit[i] > DBIT_DURATION_MAX_19200) && (dTbit[i] < DBIT_DURATION_MIN_9600)) || + (dTbit[i] > DBIT_DURATION_MAX_9600)) + { + stop_flag = 1; + /* do not capture */ + TIMER_CONTROL_EDG = 0; + TIMER_INT_ENA = 0; + lin_goto_idle_state(); + return; + }else + { + if (i > 0) + { + if ((dTbit[i] < ((100 - BIT_RATE_TOLERANCE_UNSYNC) * (dTbit[i-1] / 100))) || (dTbit[i] > ((100 + BIT_RATE_TOLERANCE_UNSYNC) * (dTbit[i-1] / 100)))) + { + stop_flag = 2; + /* do not capture */ + TIMER_CONTROL_EDG = 0; + TIMER_INT_ENA = 0; + lin_goto_idle_state(); + return; + } + } + } + } + autobaud_tmr_capture_index ++; + } + /* Adjust the baud rate if there is no error in SYNC BYTE */ + if ((autobaud_tmr_capture_index > 4) && (stop_flag == 0)) + { + if (dTbit[i] >= DBIT_DURATION_MIN_9600) + { + autobaud_current = 9600; + }else + { + autobaud_current = 19200; + } + lin_lld_sci_init_autobaud(autobaud_current); + /* Disable interrupt from timer channel */ + TIMER_CONTROL_EDG = 0; + TIMER_INT_ENA = 0; + } + return; +} + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TIM_Input_capture_ISR (void) +* @brief timer interrupt service routine for AUTOBAUD feature +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt interrupt service routine for TIM timer +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if (defined(_MC9S12ZVML128_H)||defined(_MC9S12ZVML31_H) ||defined(_MC9S12ZVL32_H)\ + ||defined(_MC9S12ZVL128_H)||defined(_MC9S12ZVMC256_H) || defined(_MC9S12ZVMB_H)) +ISR(VectorNumber_Vtim0ch3, TIM_Input_capture_ISR) +{ + AutobaudTimerValEval(); +} +#endif +/* End if (defined(_MC9S12ZVML128_H)||defined(_MC9S12ZVML31_H)||defined(_MC9S12ZVL32_H) */ +/* ||defined(_MC9S12ZVL128_H)||defined(_MC9S12ZVMC256_H) || defined(_MC9S12ZVMB_H)) */ + +#if (defined(_MC9S12ZVH128_H)) +ISR(VectorNumber_Vtim1ch0, TIM_Input_capture_ISR) +{ + AutobaudTimerValEval(); +} +#endif /* End (defined(_MC9S12ZVH128_H)*/ + +#if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H)) +ISR(VectorNumber_Vtimch3, TIM_Input_capture_ISR) +{ + AutobaudTimerValEval(); +} +#endif /* End if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H))*/ + +#if (defined(_MC9S12ZVMA_H)||defined(_MC9S12VRP64_H)||defined(_MC9S12VRP48_H)) +ISR(VectorNumber_Vtim1ch1, TIM_Input_capture_ISR) +{ + AutobaudTimerValEval(); +} +#endif /* End if (defined(_MC9S12ZVMA_H))*/ + +#endif /* End (AUTOBAUD == 1)*/ + +#endif /* End (_MCU_ == _S12_) */ + +#if (_MCU_ == _S08_) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void TPM1_TIMER_ISR(void) +* @brief interrupt service routine for TPM1/ FTM timer +* +* @return #void +* +* @SDD_ID N/A +* @endif +* +* @details +* interrupt service routine for TPM1/ FTM timer +* +* @see #lin_lld_timer_isr +*//*END*----------------------------------------------------------------------*/ +#if defined(_MC9S08RN60_H) + +ISR(VectorNumber_Vmtim0, TPM1_TIMER_ISR) +{ + /* CH0F = 0 */ + MTIM0_SC &= ~MTIM0_SC_TOF_MASK; + lin_lld_timer_isr(); +} +#else +ISR(VectorNumber_Vtpm1ch0, TPM1_TIMER_ISR) +{ + /* CH0F = 0 */ + TPM1C0SC &= ~TPM1C0SC_CH0F_MASK; + lin_lld_timer_isr(); +} +#endif /* End defined(_MC9S08RN60_H)*/ +#endif /* End (_MCU_ == _S08_) */ + +#if ((!defined(_MC9S12ZVML128_H))&&(!defined(_MC9S12ZVML31_H))) +#pragma CODE_SEG DEFAULT /* Return to default code segment */ +#endif /* End if ((!defined(_MC9S12ZVML128_H))&&(!defined(_MC9S12ZVML31_H))) */ + +#endif /* End defined(_MC9S12I32_H) */ +/** +* @} +*/ + + + diff --git a/LIN_Stack/bsp/SCI/lin_lld_sci.c b/LIN_Stack/bsp/SCI/lin_lld_sci.c new file mode 100644 index 0000000..d245109 --- /dev/null +++ b/LIN_Stack/bsp/SCI/lin_lld_sci.c @@ -0,0 +1,3307 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup SCI_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file bsp/SCI/lin_lld_sci.c +* +* @author FPT Software +* +* @brief SCI for LIN network +* +******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * 20101027 v1.0 First version + * 20111005 v1.1 Updated hardware support, multi timers + * + *****************************************************************************/ +#include "derivative.h" +#include "DMK-BC316-77.h" +#include "lin_lld_sci.h" +#include "lin_hw_cfg.h" +#include "lin_common_proto.h" +#include "lin_lld_timesrv.h" +#include "lin_cfg.h" + +#if (!defined(_MC9S12ZVML128_H) && !defined(_MC9S12ZVML31_H)) +#pragma MESSAGE DISABLE C4800 /* Disable warning message with ID C4800 */ +#endif /* End if (!defined(_MC9S12ZVML128_H) && !defined(_MC9S12ZVML31_H)) */ + +#if (LIN_MODE == _SLAVE_MODE_) +#if (SCI_VERSION == SCI_V4 && __RESYN_EN==1) +#include "lin_lld_resyn.h" +#define Active_Edge_Rx_Disable() pSCI->scibdh.byte &= ~SCIBDH_RXEDGIE_MASK +#define Active_Edge_Rx_Enable() pSCI->scibdh.byte |= SCIBDH_RXEDGIE_MASK +#endif /* End (SCI_VERSION == SCI_V4 && __RESYN_EN==1) */ + +#if (AUTOBAUD == 1) +#include "lin_lld_autobaud.h" +extern l_u16 lin_max_frame_res_timeout_val_autobaud[8]; +#endif /* End (1==AUTOBAUD) */ + +/***** Globle variable data *****/ + +/* pSCI func ifc checksum_mode state l_status cnt_byte *ptr current_pid *response_buffer + pid_out tbit frame_timeout_cnt res_frame_timeout_cnt idle_timeout_cnt */ +#if (SCI_VERSION != SCI_V5) +/** +* @var static l_bool func +*/ +static l_bool func = 0; +#endif /* End (SCI_VERSION != SCI_V5) */ + +/** +* @var static tSCI *pSCI +*/ +static tSCI *pSCI = (tSCI*)SCI_ADDR; + +/** +* @var static l_u8 ifc +*/ +static l_u8 ifc = 0xFF; + +/** +* @var static l_u8 state +*/ +static l_u8 state = UNINIT; + +/** +* @var static lin_status l_status +*/ +static lin_status l_status; + +/** +* @var static l_u8 cnt_byte +*/ +static l_u8 cnt_byte = 0; + +/** +* @var static l_u8 *ptr +*/ +static l_u8 *ptr = 0; + +/** +* @var static l_u8 current_id +*/ +static l_u8 current_id = 0x00; + +/** +* @var static l_u8 *response_buffer +*/ +static l_u8 *response_buffer = 0; + +/** +* @var static l_u8 pid +*/ +static l_u8 pid = 0x80; + +/** +* @var static l_u16 tbit +*/ +static l_u16 tbit = 0; + +/** +* @var static l_u16 frame_timeout_cnt +*/ +static l_u16 frame_timeout_cnt = 0; + +/** +* @var static l_u16 res_frame_timeout_cnt +*/ +static l_u16 res_frame_timeout_cnt = 0; + +/** +* @var static l_u16 idle_timeout_cnt +*/ +static l_u16 idle_timeout_cnt = 0; + +#if (SCI_VERSION == SCI_V4) +/* Globle variable for resyn */ +#if (__RESYN_EN) +volatile static l_u8 resyn_flag = 0x00; +extern l_u16 timer_value; + +#endif /* End Enable resych */ +#endif /* End (SCI_VERSION == SCI_V4) */ + +extern const l_u16 lin_max_frame_res_timeout_val[8]; +#if (SCI_VERSION != SCI_V2) +extern l_u8 lin_lld_response_buffer[10]; +#endif /* End (SCI_VERSION != SCI_V2) */ + +//user define +extern unsigned char InitButtonCode; +/***** LOW-LEVEL API *****/ + +void lin_lld_sci_init +( + /* [IN] LIN interface name*/ + l_ifc_handle iii +) +{ +#if (SCI_VERSION == SCI_V2) + /* Config */ + ifc=(l_u8)iii; + response_buffer=lin_lld_response_buffer; + /* Set SCI is Master or Slave */ + tbit=(l_u16)(1000000/LIN_BAUD_RATE); + + /* Initialize SCI */ + /* Set baud rate */ + pSCI->scibdh.byte = ((MCU_BUS_FREQ/LIN_BAUD_RATE/16)>>8)&0x1F; + pSCI->scibdl.byte = (MCU_BUS_FREQ/LIN_BAUD_RATE/16)&0xFF; + + /* Enable use of 13bit breaks and SCI frame for LIN */ + pSCI->scicr1.byte = 0x00; /* one start bit, eight data bits, one stop bit */ + pSCI->scicr2.byte = ((SCICR2_TE_MASK | SCICR2_RE_MASK) | SCICR2_RIE_MASK); + pSCI->scicr3.byte |= SCICR3_FEIE_MASK; /* Enable Frame Error interrupt */ + + /* Enter IDLE state */ + lin_goto_idle_state(); +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + l_u16 tmp; + /* Resyn initialization */ +#if (__RESYN_EN == 1) /* enable/disable Resyn module */ + initTrimSaturation(); + TPM_CH2_init(); +#endif /* enable/disable Resyn module */ + /* Config */ + ifc=(l_u8)iii; + response_buffer=lin_lld_response_buffer; + /* Set SCI is Master or Slave */ + tbit=(1000000/LIN_BAUD_RATE); + + /* Initialize SCI */ + /* Set baud rate */ + tmp = MCU_BUS_FREQ/LIN_BAUD_RATE/16; + pSCI->scibdh.byte = (tmp>>8)&0x1F; + pSCI->scibdl.byte = tmp&0xFF; + + /* Enable use of 13bit breaks and SCI frame for LIN */ + /* one start bit, eight data bits, one stop bit */ + pSCI->scicr1.byte = 0x00; + pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + /* clear LIN Break Detection flag */ + pSCI->scisr2.byte |= (SCISR2_LBKDIF_MASK | SCISR2_BRK13_MASK | SCISR2_LBKDE_MASK); + /* Enable Frame Error interrupt */ + pSCI->scicr3.byte |= SCICR3_FEIE_MASK; + /* enable LIN Break Detection interrupt */ + pSCI->scibdh.byte |= SCIBDH_LBKDIE_MASK; + /* Receive data not inverted */ + pSCI->scisr2.bit.rxinv = 0; + /* Enter IDLE state */ + lin_goto_idle_state(); +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V5) + l_u16 tmp; + /* Config */ + ifc=(l_u8)iii; + response_buffer=lin_lld_response_buffer; + /* Set SCI is Master or Slave */ + tbit=(1000000/LIN_BAUD_RATE); + + /* Initialize SCI */ + /* Set baud rate */ + pSCI->scisr2.byte = 0x00; + tmp = MCU_BUS_FREQ/LIN_BAUD_RATE/16; + pSCI->scibdh.byte = (l_u8)(tmp>>8); + pSCI->scibdl.byte = tmp&0xff; + + /* Enable SCI in wait mode and enable bit count after stop bit */ + pSCI->scicr1.byte = SCICR1_ILT_MASK; + /* Enable use of 13bit breaks and SCI frame for LIN */ + pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); + /* Enable mismatch error detection */ + pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + /* Enable tranceiver interrupt */ + pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + + /* Enter IDLE state */ + lin_goto_idle_state(); +#endif /* End (SCI_VERSION == SCI_V5) */ + +#if (SCI_VERSION == SCI_V6) + l_u16 tmp; +#if ( defined(_MC9S12ZVL32_H) || defined(_MC9S12ZVL128_H) || \ + defined(_MC9S12ZVMA_H) || defined(_MC9S12ZVMB_H)) + #if (_SCI0_) + /* Set up for LIN PHY */ + /* Enable LIN PHY*/ + LP0CR_LPE = 1; + /* Turn on lin transmitter overcurrent interrupt */ + LP0IE_LPOCIE = 1; + #endif /* END SCI0 */ +#endif /* END ifdef _MC9S12ZVL32_H */ +#if (defined(_MC9S12VR64_H) || defined(_MC9S12VR32_H) || defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H)) + #if (_SCI0_) + /* Set up for LIN PHY */ + /* Enable LIN PHY*/ + LPCR_LPE = 1; + /* Turn on lin transmitter overcurrent interrupt */ + LPIE_LPOCIE = 1; + #endif /* END SCI0 */ +#endif /* END if defined(_MC9S12VR64_H) || defined(_MC9S12VR32_H) || defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H) */ + /* Config */ + ifc=(l_u8)iii; + response_buffer=lin_lld_response_buffer; + /* Set SCI is Master or Slave */ + tbit=(1000000/LIN_BAUD_RATE); + + /* Initialize SCI */ + /* Set baud rate */ + pSCI->scisr2.byte = 0x00; +#if (AUTOBAUD == 1) + /* driver shall init slave with baudrate = 19200. Then it detect LIN Bus baudrate, then adjust accordingly */ + tmp = MCU_BUS_FREQ/19200; +#else + tmp = MCU_BUS_FREQ/LIN_BAUD_RATE; +#endif + pSCI->scibdh.byte = (l_u8)(tmp>>8); + pSCI->scibdl.byte = (l_u8)tmp&0xff; + + /* Enable SCI in wait mode and enable bit count after stop bit */ + pSCI->scicr1.byte = SCICR1_ILT_MASK; + /* Enable use of 13bit breaks and SCI frame for LIN */ + pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); +#if (AUTOBAUD == 1) + /* Enable break detect flags */ + pSCI->sciacr1.byte = SCIACR1_BKDIE_MASK; + /* Enable break detect circuit */ + pSCI->sciacr2.byte = SCIACR2_BKDFE_MASK; +#else + /* Enable mismatch error detection */ + pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + //pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + pSCI->sciacr1.byte = (SCIACR1_RXEDGIE_MASK | SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK);//SCIACR1_RXEDGIE_MASK + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); +#endif + /* Enable transceiver interrupt */ + pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + /* Dummy read */ + (void)pSCI->scisr1.byte; + + + /****************************** + *** x. AUTOBAUD + *******************************/ + +#if (AUTOBAUD == 1) + autobaud_init(); +#endif /* End AUTOBAUD */ + /* Enter IDLE state */ + lin_goto_idle_state(); +#endif /* End (SCI_VERSION == SCI_V6) */ +} /* End of function lin_lld_sci_init( l_ifc_handle iii ) */ + + +#if (AUTOBAUD == 1) +volatile l_u8 baudrate_adjusted_flag = 0; +void lin_lld_sci_init_autobaud (l_u16 baudrate) +{ + l_u16 tmp; + l_u8 i = 0; + /* Set up for LIN PHY */ +#if ( defined(_MC9S12ZVL32_H) || defined(_MC9S12ZVL128_H) || \ + defined(_MC9S12ZVMA_H) || defined(_MC9S12ZVMB_H)) + /* Enable LIN PHY*/ + LP0CR_LPE = 1; +#endif /* END ifdef _MC9S12ZVL32_H */ + response_buffer=lin_lld_response_buffer; + + /* Set SCI is Master or Slave */ + tbit=(1000000/baudrate); + /* Initialize SCI */ + /* Set baud rate */ + pSCI->scisr2.byte = 0x00; + tmp = (MCU_BUS_FREQ/baudrate); + /*Change AMAP to 0 to access SCI_BDH, SCI_BDL*/ + pSCI->scisr2.byte &= ~SCISR2_AMAP_MASK; + /*Set new baudrate*/ + pSCI->scibdh.byte = (l_u8)(tmp>>8); + pSCI->scibdl.byte = tmp&0xff; + + /* Enable SCI in wait mode and enable bit count after stop bit */ + pSCI->scicr1.byte = SCICR1_ILT_MASK; + /* Enable use of 13bit breaks and SCI frame for LIN */ + pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); + /* Enable mismatch error detection */ + pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + /* Enable tranceiver interrupt */ + pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + autobaud_current=baudrate; + /* Ignore first frame if node was sleeping before receiving */ + /* Enter Receive PID state */ + if (RECV_SYN == state) + { + state = RECV_PID; + } + /* Set flag to indicate that baud rate was adjusted*/ + baudrate_adjusted_flag = 1; + + for (i=0; i<8; i++) + { + lin_max_frame_res_timeout_val_autobaud[i] = lin_calc_max_res_timeout_cnt(autobaud_current, i+1); + } + + frame_timeout_cnt =lin_max_frame_res_timeout_val_autobaud[7]; + +} /* End of function lin_lld_sci_init( l_ifc_handle iii ) */ +#endif /* AUTOBAUD Init */ + +void lin_lld_sci_deinit () +{ + state=UNINIT; + lin_lld_sci_int_disable(); +} + + +void lin_lld_sci_tx_wake_up () +{ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + l_u8 sci_flag_sr1; + if((state == IDLE) || (state == SLEEP_MODE)) + { + sci_flag_sr1 = pSCI->scisr1.byte; + /* Send wake signal byte=0x80 */ + pSCI->scid.byte = SCID_R7_T7_MASK; + /* Set Lin state to idle */ + lin_goto_idle_state(); + } +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + if((state == IDLE) || (state == SLEEP_MODE)) + { + /* Send wake signal byte=0x80 */ + pSCI->scidrl.byte = SCIDRH_R8_MASK; + /* Set Lin state to idle */ + lin_goto_idle_state(); + } +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_tx_wake_up() */ + + +void lin_lld_sci_int_enable() +{ +#if (SCI_VERSION == SCI_V2) + /* Can't enable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + /* Enable SCI Channel*/ + pSCI->scicr2.byte |= (SCICR2_RE_MASK | SCICR2_RIE_MASK); +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + /* Can't enable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + + /* Enable SCI Channel*/ + pSCI->scicr2.byte |= (SCICR2_RE_MASK | SCICR2_RIE_MASK); + /* Enable timeout interrupt 0 channel */ + +#if ((!defined(_MC9S12I32_H)) && (!defined(_MC9S12I128_H)) && (!defined(_MM9Z1J638_H)) && (!defined(_MC9S08RN60_H))) + TPM1C0SC = 0x50; +#endif /* End defined(_MC9S12I32_H) */ +#endif /* End (SCI_VERSION == SCI_V4) */ + + /*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + /* Can't enable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + /* Enable SCI Channel*/ + pSCI->scicr2.byte |= (SCICR2_RE_MASK | SCICR2_RIE_MASK); + /* Enable Timeout */ +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_int_enable() */ + + +void lin_lld_sci_int_disable () +{ +#if (SCI_VERSION == SCI_V2) + /* Can't disable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + + while(state != IDLE) {} + /* Disable SCI Channel*/ + pSCI->scicr2.byte &= ~(SCICR2_RE_MASK | SCICR2_RIE_MASK); +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + /* Can't disable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + + while(state != IDLE) {} + /* Disable SCI Channel*/ + pSCI->scicr2.byte &= ~(SCICR2_RE_MASK | SCICR2_RIE_MASK); + /* Disable timeout interrupt 0 channel */ + +#if ((!defined(_MC9S12I32_H)) && (!defined(_MC9S12I128_H)) && (!defined(_MM9Z1J638_H)) && (!defined(_MC9S08RN60_H))) + TPM1C0SC = 0x00; +#endif /* if not defined(_MC9S12I128_H) */ +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + /* Can't disable in interrupt context */ + if((state == PROC_CALLBACK) || (state==UNINIT) || (state==SLEEP_MODE)) + { + return; + } + + while(state != IDLE) {} + /* Disable SCI Channel*/ + pSCI->scicr2.byte &= ~(SCICR2_RE_MASK | SCICR2_RIE_MASK); +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_int_disable() */ + +void lin_lld_sci_ignore_response () +{ + lin_goto_idle_state(); +} + +void lin_lld_sci_set_low_power_mode () +{ + /* Configure Hw code */ + /* Set Lin status = receiving data*/ + state=SLEEP_MODE; +} + +void lin_lld_sci_rx_response +( + /* [IN] Length of response data expect to wait */ + l_u8 msg_length +) +{ + /* Put response length and pointer of response buffer into descriptor */ + *(response_buffer)=msg_length; + cnt_byte=0; + ptr=response_buffer; + /* Set Lin status = receiving data*/ + state=RECV_DATA; +} + +void lin_lld_sci_tx_response () +{ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + /* calculate checksum */ + response_buffer[*(response_buffer)+1] = lin_checksum(response_buffer, pid); + cnt_byte=1; + /* Send First byte */ + pSCI->scid.byte = response_buffer[1]; + /* Set LIN Status */ + state = SEND_DATA; +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + /* calculate checksum */ + response_buffer[*(response_buffer)+1] = lin_checksum(response_buffer, pid ); + cnt_byte=1; + /* Send First byte */ + pSCI->scidrl.byte = response_buffer[1]; + /* Set LIN Status */ + state = SEND_DATA; +#endif /* End (SCI_VERSION == SCI_V5) */ + +} /* End function lin_lld_sci_tx_response() */ + + +l_u8 lin_lld_sci_get_status () +{ + return l_status.byte; +} + + +l_u8 lin_lld_sci_get_state() +{ + return state; +} + + +void lin_lld_sci_timeout () +{ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if (LD_CHECK_N_CR_TIMEOUT == tl_check_timeout_type) + { + if(0 == --tl_check_timeout) + { + /* update status of transport layer */ + tl_service_status = LD_SERVICE_ERROR; + tl_receive_msg_status = LD_N_CR_TIMEOUT; + tl_rx_msg_status = LD_N_CR_TIMEOUT; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_diag_state = LD_DIAG_IDLE; + } + } + + if (LD_CHECK_N_AS_TIMEOUT == tl_check_timeout_type) + { + if(0 == --tl_check_timeout) + { + /* update status of transport layer */ + tl_service_status = LD_SERVICE_ERROR; + tl_tx_msg_status = LD_N_AS_TIMEOUT; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_diag_state = LD_DIAG_IDLE; + } + } +#else + /* Single Frame */ + if (LD_CHECK_N_AS_TIMEOUT == tl_check_timeout_type) + { + if(0 == --tl_check_timeout) + { /* update status of transport layer */ + tl_service_status = LD_SERVICE_ERROR; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } + } +#endif /* END (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +#if (SCI_VERSION == SCI_V2) + switch(state) + { + case IDLE: + if(idle_timeout_cnt==0) + { + /* Set LIN mode to sleep mode */ + lin_goto_sleep_flg = 1; + /* trigger callback */ + CALLBACK_HANDLER(ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0x00); + /* goback to IDLE, reset max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + /* Set state to sleep mode */ + state = SLEEP_MODE; + } + else + { + idle_timeout_cnt--; + } + break; + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == frame_timeout_cnt) + { + lin_goto_idle_state(); + } + else + { + frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(res_frame_timeout_cnt == 0) + { + if(cnt_byte > 0) + { + /* set lin status: error_in_response */ + l_status.byte |= LIN_STA_ERROR_RESP; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_NODATA_TIMEOUT, 0x00); + } + lin_goto_idle_state(); + } + else + { + res_frame_timeout_cnt--; + } + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + switch(state) + { + case IDLE: + if(idle_timeout_cnt==0) + { + /* Set LIN mode to sleep mode */ + lin_goto_sleep_flg = 1; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0xFF); + /* goback to IDLE, reset max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + /* disable LIN break detect interrupt */ + pSCI->scisr2.bit.lbkde = 0; + /* Set state to sleep mode */ + state = SLEEP_MODE; + } + else + { + idle_timeout_cnt--; + } + break; + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == frame_timeout_cnt) + { + lin_goto_idle_state(); + } + else + { + frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(0 == res_frame_timeout_cnt) + { + if(cnt_byte) + { + /* set lin status: error_in_response */ + l_status.byte |= LIN_STA_ERROR_RESP; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_NODATA_TIMEOUT, current_id); + } + lin_goto_idle_state(); + } + else + { + res_frame_timeout_cnt--; + } + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V4) */ + + /*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + switch(state) + { + case IDLE: + if(idle_timeout_cnt==0) + { + /* Set LIN mode to sleep mode */ + lin_goto_sleep_flg = 1; + + NO_DATA_Sleep=1; //~{e( ?~}?~{?9~}?~{=f?f5<~}?~{ o??~} + + /* trigger callback */ + CALLBACK_HANDLER(ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0xFF); + /* goback to IDLE, reset max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + /* Set state to sleep mode */ + state = SLEEP_MODE; + } + else + { + idle_timeout_cnt--; + } + break; + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == frame_timeout_cnt) + { + lin_goto_idle_state(); + } + else + { + frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(0 == res_frame_timeout_cnt) + { + if(cnt_byte > 0) + { + + /* set lin status: error_in_response */ + l_status.byte |= LIN_STA_ERROR_RESP; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_NODATA_TIMEOUT, current_id); + } + lin_goto_idle_state(); + } + else + { + res_frame_timeout_cnt--; + } + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_timeout() */ + +/*** INTERNAL FUNTIONS ***/ + +void lin_goto_idle_state () +{ +#if (SCI_VERSION == SCI_V2) + /* set lin status: ~bus_activity */ + l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + state=IDLE; +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + /* set lin status: ~bus_activity */ + l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + state=IDLE; + /* Enable LBK detect */ + pSCI->scisr2.bit.lbkde = 1; +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + /* set lin status: ~bus_activity */ + l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + state=IDLE; +#if (AUTOBAUD == 1) + /* if baud rate was not adjusted successfully*/ + if (baudrate_adjusted_flag < 1) + { + /* Enable SCI interface*/ + /* Enable SCI in wait mode and enable bit count after stop bit */ + pSCI->scicr1.byte = SCICR1_ILT_MASK; + /* Enable use of 13bit breaks and SCI frame for LIN */ + pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); + /* Enable mismatch error detection */ + pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + /* Enable tranceiver interrupt */ + pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + + } +#endif +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_goto_idle_state() */ + +#if (SCI_VERSION != SCI_V5) +void lin_lld_sci_err_isr () +{ +#if (SCI_VERSION == SCI_V2) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + sci_flag_sr1 = pSCI->scisr1.byte; + tmp_byte = pSCI->scid.byte; + /****************************** + *** 1. BREAK DETECTED + *******************************/ + if(0x00 == tmp_byte) + { + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == state) + { + lin_goto_idle_state(); + return; + } + /* reset lin status */ + l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + frame_timeout_cnt = lin_max_frame_res_timeout_val[7]; + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + state=RECV_SYN; + return; + } + /****************************** + *** 3. FRAME ERROR DETECTED + *******************************/ + else + { + /* set lin status: error_in_response, framing_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* trigger callback */ + if((state == RECV_DATA)||(state == SEND_DATA)||(state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_FRAME_ERR, current_id); + } + lin_goto_idle_state(); + } +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + sci_flag_sr1 = pSCI->scisr1.byte; + tmp_byte = pSCI->scid.byte; + + if((sci_flag_sr1 & SCISR1_FE_MASK)||(sci_flag_sr1 & SCISR1_PF_MASK)) + { + if(sci_flag_sr1 & SCISR1_FE_MASK) + { + + /* set lin status: error_in_response, framing_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* trigger callback */ + if((state == RECV_DATA)||(state == SEND_DATA)||(state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_FRAME_ERR, current_id); + } + lin_goto_idle_state(); + } + if(sci_flag_sr1 & SCISR1_PF_MASK) + { + /* set lin status: error_in_response, framing_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_PARITY_ERR); + /* trigger callback */ + if((state == RECV_DATA)||(state == SEND_DATA)||(state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_CHECKSUM_ERR, current_id); + } + lin_goto_idle_state(); + } + } +#endif /* End (SCI_VERSION == SCI_V4) */ +} /* End function lin_lld_sci_err_isr() */ + + +void lin_lld_sci_rx_isr () +{ +#if (SCI_VERSION == SCI_V2) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + sci_flag_sr1 = pSCI->scisr1.byte; + tmp_byte = pSCI->scid.byte; + /* Set max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_RDRF_MASK)) + { + switch(state) + { + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55 == tmp_byte) + { + state=RECV_PID; + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + /* checkparity and extrait PID */ + current_id = lin_process_parity(tmp_byte, CHECK_PARITY); + pid = tmp_byte; + if(current_id !=0xFF) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_OK, current_id); + /* Set Maximum response frame timeout */ + res_frame_timeout_cnt = lin_max_frame_res_timeout_val[*(response_buffer) - 1]; + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* set lin status: parity_error */ + l_status.byte |= LIN_STA_PARITY_ERR; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_ERR, 0x00); + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + ptr++; + *(ptr)=tmp_byte; + /* Check bytes received fully */ + if(cnt_byte==(response_buffer[0])) + { + /* checksum checking */ + if(lin_checksum(response_buffer, pid)==tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* set lin status: successful_transfer */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_RX_COMPLETED, current_id); + if (SLEEP_MODE != state) + { + lin_goto_idle_state(); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* set lin status: error_in_response, checksum_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_CHECKSUM_ERR, current_id); + lin_goto_idle_state(); + } + } + cnt_byte++; + break; + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + /* Check for READBACK error */ + if (0U == (sci_flag_sr1 & SCISR1_TC_MASK)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + lin_goto_idle_state(); + break; + } + else + { + if (tmp_byte != response_buffer[cnt_byte]) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + lin_goto_idle_state(); + break; + } + } + + if(cnt_byte <= (response_buffer[0])) + { + /* Send data bytes and checksum */ + cnt_byte++; + pSCI->scid.byte = response_buffer[cnt_byte]; + } + else + { + /* TX transfer complete */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_TX_COMPLETED, current_id); + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + if ((tmp_byte == 0xF0) || (tmp_byte == 0xE0) || (tmp_byte == 0xC0) || (tmp_byte == 0x80) || (tmp_byte == 0x00)) + { + /* Set idle timeout again */ + lin_goto_idle_state(); + } + break; + default: + break; + } + } +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + l_u8 sci_flag_sr1; + l_u8 sci_flag_sr2; + l_u8 tmp_byte; + /* Set max idle timeout */ + idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + + /****************************** + *** 1. BREAK DETECTED + *******************************/ + /* if the lbkdif is set */ + sci_flag_sr2 = pSCI->scisr2.byte ; + + if((sci_flag_sr2 & SCISR2_RXEDGIF_MASK) && (!(sci_flag_sr2 & SCISR2_LBKDIF_MASK))) + { + /* Clear flag */ + pSCI->scisr2.bit.rxedgif = 1; + #if (__RESYN_EN == 1) + /* Resynchronization */ + if (resyn_flag & START_RESYN_MASK ) + { + /* start timer */ + TPM_CH2_enable(); + } + + if (resyn_flag) + { + /* increase falling_edge_num */ + resyn_flag <<= 1; + /* Store RESYN_FLAG for test */ + } + else /* if resyn_flag == STOP_RESYN_MASK */ + { + /* Disable Active Edge interrupt */ + pSCI->scibdh.byte &= ~SCIBDH_RXEDGIE_MASK; + } + + if (resyn_flag & FIN_RESYN_MASK) + { + /* store timer */ + TPM_CH2_store(); + /* Store timer value for test */ + } + #else /* if __RESYN_EN == 0 */ + pSCI->scibdh.byte &= ~SCIBDH_RXEDGIE_MASK; /* Disable rx edged detection */ + #endif + /* End Resynchronization */ + + if (SLEEP_MODE == state) + { + lin_goto_idle_state(); + lin_goto_sleep_flg = 0; + } + + /* Enable Break interrupt */ + pSCI->scibdh.byte |= SCIBDH_LBKDIE_MASK ; + + /* Receive data not inverted */ + pSCI->scisr2.bit.rxinv = 0; + /* check state of node is SLEEP_MODE */ + return; + } + + if(sci_flag_sr2 & SCISR2_LBKDIF_MASK) + { + /* Clear flag */ + pSCI->scisr2.bit.lbkdif = 1; + /* Enable Active Edge interrupt */ + pSCI->scibdh.byte |= SCIBDH_RXEDGIE_MASK; + /* Disable Break interrupt */ + pSCI->scibdh.byte &= ~SCIBDH_LBKDIE_MASK ; + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == state) + { + lin_goto_idle_state(); + return; + } + /* reset lin status */ + l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + frame_timeout_cnt = lin_max_frame_res_timeout_val[7]; + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + /* Start resyn */ + #if (__RESYN_EN == 1) + resyn_flag = START_RESYN_MASK; + #endif + /* Enable Active Edge interrupt */ + pSCI->scibdh.byte |= 0x40 ; /* SCIBDH_RXEDGIE_MASK; */ + + state=RECV_SYN; + /* Disable LBK detect */ + pSCI->scisr2.bit.lbkde = 0; + return; + } + else + { + sci_flag_sr1 = pSCI->scisr1.byte; + tmp_byte = pSCI->scid.byte; + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_RDRF_MASK)) + { + switch(state) + { + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55 == tmp_byte) + { + state=RECV_PID; + #if (__RESYN_EN == 1) + /* Update new trim value */ + if (resyn_flag & FIN_RESYN_MASK) + { + compTrimCorrection(); + ApplyTrimReg(); + } + resyn_flag = STOP_RESYN_MASK; + #endif + + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + /* checkparity and extrait PID */ + current_id=lin_process_parity(tmp_byte, CHECK_PARITY); + /* Keep the PID */ + pid = tmp_byte; + if(current_id !=0xFF) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_OK, current_id); + /* Set Maximum response frame timeout */ + res_frame_timeout_cnt = lin_max_frame_res_timeout_val[*(response_buffer) - 1]; + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* set lin status: parity_error */ + l_status.byte |= LIN_STA_PARITY_ERR; + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_ERR, 0xFF); + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + ptr++; + *(ptr)=tmp_byte; + /* Check bytes received fully */ + if(cnt_byte==(response_buffer[0])) + { + /* checksum checking */ + if(lin_checksum(response_buffer, pid)==tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* set lin status: successful_transfer */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_RX_COMPLETED, current_id); + if (SLEEP_MODE != state) + { + lin_goto_idle_state(); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* set lin status: error_in_response, checksum_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_CHECKSUM_ERR, current_id); + lin_goto_idle_state(); + } + } + cnt_byte++; + break; + + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + /* Check for READBACK error */ + if (0==(sci_flag_sr1&SCISR1_TC_MASK)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + lin_goto_idle_state(); + break; + } + else + { + if (tmp_byte != response_buffer[cnt_byte]) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + lin_goto_idle_state(); + break; + } + } + + if(cnt_byte <= (response_buffer[0])) + { + /* Send data bytes and checksum */ + cnt_byte++; + pSCI->scid.byte = response_buffer[cnt_byte]; + } + else + { + /* TX transfer complete */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_TX_COMPLETED, current_id); + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + if ((tmp_byte == 0xF0) || (tmp_byte == 0xE0) || (tmp_byte == 0xC0) || (tmp_byte == 0x80) || (tmp_byte == 0x00)) + { + /* Set idle timeout again */ + lin_goto_idle_state(); + /* Enable LIN break detect interrupt */ + pSCI->scisr2.bit.lbkde = 1; + } + break; + default: + break; + } + } + } +#endif /* End (SCI_VERSION == SCI_V4) */ +} /* End function lin_lld_sci_rx_isr() */ +#endif /* End(SCI_VERSION != SCI_V5)*/ + +l_u8 MFS_RollingCounter=0; +l_u8 MFS_CheckSum=0; + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +void lin_lld_sci_isr () +{ + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + l_u16 i; + + sci_flag_sr1 = pSCI->scisr1.byte; + /* Set max idle timeout */ + idle_timeout_cnt = _MAX_IDLE_TIMEOUT_; + + if(FLAG_GO_TO_Sleep==1) + { + PWM1_Init(); + Sig_LI0_DI_KL_58xs_run=0; + V_12_Ctrl=1; + AD1_Init(); + AD1_Start(); + l_ifc_init(LI0); + } + + M_ASK_S_Sleep=0; + NO_DATA_Sleep=0; + FLAG_GO_TO_Sleep=0; + + + /****************************** + *** 1. BREAK DETECTED + *******************************/ + if(0 != (pSCI->sciasr1.byte & SCIASR1_BKDIF_MASK)) + { + /* Clear the error flag */ + pSCI->sciasr1.byte |= SCIASR1_BKDIF_MASK; + + /* Reset lin status */ + l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + #if (AUTOBAUD == 1) + frame_timeout_cnt = lin_max_frame_res_timeout_val_autobaud[7]; + if (baudrate_adjusted_flag == 0) + { + /* Disable SCI receiver interface*/ + pSCI->scicr2.byte &= ~( SCICR2_RE_MASK | SCICR2_RIE_MASK); + pSCI->sciacr2.byte &= ~(SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + pSCI->sciacr1.byte &= ~(SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + autobaud_tmr_capture_index = 0; + /* Capture only on failing edges */ + stop_flag = 0; + TIMER_CONTROL_EDG = 2U; + TIMER_INT_ENA = 1; + } + + #else + frame_timeout_cnt = lin_max_frame_res_timeout_val[7]; + #endif /* End (AUTOBAUD == 1)*/ + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == state) + { + lin_goto_idle_state(); + return; + } + + /* Handle error */ + if((RECV_DATA == state) || (SEND_DATA == state) || (SEND_DATA_COMPLETED == state)) + { + /* Read dummy data to clear FE flags */ + tmp_byte = pSCI->scidrl.byte; + /* Set lin status: error_in_response, framing_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_FRAME_ERR, current_id); + } + + state = RECV_SYN; + return; + } + /****************************** + *** 2. BIT ERROR DETECTED + *******************************/ + else + { + if( 0 != (pSCI->sciasr1.byte&SCIASR1_BERRIF_MASK)) + { + pSCI->sciasr1.byte |= SCIASR1_BERRIF_MASK; + /* set lin status: error_in_response, readback_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_READBACK_ERR); + if((state == SEND_DATA) || (state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); +#if (LIN_PROTOCOL == PROTOCOL_J2602) + /* if Bit error occurs when a logic 0 is accepted as stop bit, then this case causes Framing error too*/ + /*In this case, wait for about 20 for loops, so that SCI hardware have enough time to set Framing error flag*/ + for (i=0; i<200; i++); + /* Check if Framing error flag is set */ + if(0 != (pSCI->scisr1.byte&SCISR1_FE_MASK)) + { + return; + } +#endif + } +#if (AUTOBAUD == 1) + /*Clear bit error if arise in worst case for first bit error due to baud rate evaluation */ + if (baudrate_adjusted_flag < 2) + { + return; + } + else lin_goto_idle_state(); +#else + lin_goto_idle_state(); +#endif + + return; + } + } + /****************************** + *** 3. FRAME ERROR DETECTED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_FE_MASK)) + { + /* Clear FE flags */ + pSCI->scisr1.byte |= SCISR1_FE_MASK; + tmp_byte = pSCI->scidrl.byte; + /* set lin status: error_in_response, framing_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* trigger callback */ + if((state == RECV_DATA)||(state == SEND_DATA) || (state == SEND_DATA_COMPLETED) ) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_FRAME_ERR, current_id); + } + lin_goto_idle_state(); + } + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + else if(0U != (sci_flag_sr1 & SCISR1_RDRF_MASK)) + { + tmp_byte = pSCI->scidrl.byte; + switch(state) + { + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55 == tmp_byte) + { + state = RECV_PID; + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + /* checkparity and extrait PID */ + pid=tmp_byte; + current_id = lin_process_parity(tmp_byte,CHECK_PARITY); + if(current_id != 0xFFU) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + if(current_id == 0x0E) + { + InitButtonCode = 0; + } + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_OK, current_id); + /* Set Maximum response frame timeout */ + #if (AUTOBAUD == 1) + if (baudrate_adjusted_flag == 1U) + { + baudrate_adjusted_flag = 2U; + /*Clear bit error if arise in worst case for first bit error due to baud rate evaluation */ + pSCI->sciasr1.byte |= SCIASR1_BERRIF_MASK; + } + res_frame_timeout_cnt = lin_max_frame_res_timeout_val_autobaud[*(response_buffer) - 1]; + #else + res_frame_timeout_cnt = lin_max_frame_res_timeout_val[*(response_buffer) - 1]; + #endif /* End (AUTOBAUD == 1)*/ + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* set lin status: parity_error */ + l_status.byte |= LIN_STA_PARITY_ERR; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_PID_ERR, 0xFFU); + lin_goto_idle_state(); + } + break; + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + ptr++; + *(ptr) = tmp_byte; + /* Check bytes received fully */ + if(cnt_byte==(response_buffer[0])) + { + /* checksum checking */ + if(lin_checksum(response_buffer, pid) == tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* set lin status: successful_transfer */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_RX_COMPLETED, current_id); + if (SLEEP_MODE != state) + { + lin_goto_idle_state(); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* set lin status: error_in_response, checksum_error */ + l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_CHECKSUM_ERR, current_id); + lin_goto_idle_state(); + + } + lin_pFrameBuf[6] = l_status.byte; + } + cnt_byte++; + break; + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + if(current_id==0x0E) + { + if(cnt_byte==1) + { + MFS_RollingCounter++; + if(MFS_RollingCounter==16) + { + MFS_RollingCounter=0; + } + l_u8_wr_LI0_MFL_Zaehler(MFS_RollingCounter); + } + } + + if (0 == (sci_flag_sr1&SCISR1_TC_MASK )) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + state = PROC_CALLBACK; + lin_goto_idle_state(); + break; + } + + if(cnt_byte==(response_buffer[0])) + { + /* Send checksum byte */ + pSCI->scidrl.byte = response_buffer[cnt_byte+1]; + state= SEND_DATA_COMPLETED; + } + else + { + /* Send byte next */ + cnt_byte++; + pSCI->scidrl.byte = response_buffer[cnt_byte]; + } + break; + /****************************** + *** 4.7 SLAVE: Sending data compeleted + *******************************/ + case SEND_DATA_COMPLETED: + /*******************************************/ + /*** TX Buffer Empty - Checksum Sent ***/ + /*******************************************/ + if (0U == (sci_flag_sr1&SCISR1_TC_MASK)) + { + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_READBACK_ERR, current_id); + state = PROC_CALLBACK; + lin_goto_idle_state(); + break; + } + /* set lin status: successful_transfer */ + l_status.byte |= LIN_STA_SUCC_TRANSFER; + state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)ifc, LIN_LLD_TX_COMPLETED, current_id); + lin_goto_idle_state(); + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + /* if receive a wakeup signal*/ + if ((tmp_byte == 0xFFU) || (tmp_byte == 0xFEU) || (tmp_byte == 0xFCU) || (tmp_byte == 0xF8U) || (tmp_byte == 0xF0U)|| (tmp_byte == 0xE0U)|| (tmp_byte == 0xC0U)|| (tmp_byte == 0x80U)|| (tmp_byte == 0x00U)) + { + /* Set lin bus to idle state */ + lin_goto_idle_state(); + } + break; + default: + break; + } + } + pSCI->sciasr1.byte |=0x80;// + /****************************** + *** 5. OVERRUN ERROR DETECTED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_OR_MASK)) + { + /* Read SCIDRL Register to clear OR flag*/ + tmp_byte = pSCI->scidrl.byte; + lin_goto_idle_state(); + } + +} /* End function lin_lld_sci_isr() */ +#endif /* End (SCI_VERSION == SCI_V5) */ + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + +/*--------------------------------------------------------------------*/ + +#if (LIN_MODE == _MASTER_MODE_) +/***** Globle variable data *****/ + +extern lin_node lin_node_descrs[NUM_OF_SCI_CHANNEL]; +extern const l_u16 lin_max_frame_res_timeout_val[LIN_NUM_OF_IFCS][8]; + +#ifdef MULTI_TIMER_MODE +extern const l_u16 max_idle_timeout[LIN_NUM_OF_IFCS]; +#endif /* End MULTI_TIMER_MODE */ +/***** LOW-LEVEL API *****/ + +void lin_lld_sci_init +( + /* [IN] sci channel name */ + sci_channel_name channel, + /* [IN] LIN interface name*/ + l_ifc_handle iii +) +{ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + lin_node *lnode_p; + tSCI* _pSCI; + lin_configuration *lconf_p; + + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + lconf_p = (lin_configuration *)&lin_ifc_configuration[iii]; + + /* Config */ + lnode_p->ifc=(l_u8)iii; + lnode_p->response_buffer=lconf_p->response_buffer; + /* Set SCI is Master or Slave */ + lnode_p->func=(l_bool)lconf_p->function; + lnode_p->tbit=(l_u16)(1000000/lconf_p->baud_rate); + + /* Initialize SCI */ + /* Set baud rate */ + _pSCI->scibdh.byte = ((MCU_BUS_FREQ/lconf_p->baud_rate/16)>>8)&0x1F; + _pSCI->scibdl.byte = (MCU_BUS_FREQ/lconf_p->baud_rate/16)&0xFF; + + /* Enable use of 13bit breaks and SCI frame for LIN */ + /* one start bit, eight data bits, one stop bit */ + _pSCI->scicr1.byte = 0x00; + _pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK); + +#if (SCI_VERSION == SCI_V2) + /* clear LIN Break Detection flag and set BRK13 bit */ + _pSCI->scisr2.byte |= SCISR2_BRK13_MASK; + /* enable RX complete interrupt */ + _pSCI->scicr2.byte |= SCICR2_RIE_MASK; + /* Enable Frame Error interrupt */ + _pSCI->scicr3.byte |= SCICR3_FEIE_MASK; +#endif /* End (SCI_VERSION == SCI_V2)*/ + +#if (SCI_VERSION == SCI_V4) + _pSCI->scisr2.byte |= (SCISR2_LBKDIF_MASK | SCISR2_BRK13_MASK | SCISR2_LBKDE_MASK); /* clear LIN Break Detection flag */ + /* enable RX complete interrupt */ + _pSCI->scicr2.byte |= SCICR2_RIE_MASK; + /* Enable Frame Error interrupt */ + _pSCI->scicr3.byte |= SCICR3_FEIE_MASK; + /* enable LIN Break Detection interrupt */ + _pSCI->scibdh.byte |= SCIBDH_LBKDIE_MASK; +#endif /* End (SCI_VERSION == SCI_V4)*/ + + /* Enter IDLE state */ + lin_goto_idle_state(channel); +#endif /* End (SCI_VERSION != SCI_V5 && SCI_VERSION != SCI_V6) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V5) + l_u16 tmp; + lin_node *lnode_p; + tSCI* _pSCI; + lin_configuration *lconf_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + lconf_p = (lin_configuration *)&lin_ifc_configuration[iii]; + + /* Config */ + lnode_p->ifc=(l_u8)iii; + lnode_p->response_buffer=lconf_p->response_buffer; + /* Set SCI is Master or Slave */ + lnode_p->func=(l_bool)lconf_p->function; + lnode_p->tbit=(l_u16)(1000000/lconf_p->baud_rate); + + /* Initialize SCI */ + /* Set baud rate */ + _pSCI->scisr2.byte = 0x00; + tmp = (l_u16)(MCU_BUS_FREQ/lconf_p->baud_rate/16); + _pSCI->scibdh.byte = (l_u8)(tmp>>8); + _pSCI->scibdl.byte = tmp&0xff; + + /* Enable SCI in wait mode and enable bit count after stop bit */ + _pSCI->scicr1.byte = SCICR1_ILT_MASK; + /* Enable use of 13bit breaks and SCI frame for LIN */ + _pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); + /* Enable mismatch error detection */ + _pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + _pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + _pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + /* Enable tranceiver interrupt */ + _pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + + /* Enter IDLE state */ + lin_goto_idle_state(channel); +#endif /* End (SCI_VERSION != SCI_V5) */ + +#if (SCI_VERSION == SCI_V6) + l_u16 tmp; + lin_node *lnode_p; + tSCI* _pSCI; + lin_configuration *lconf_p; +#if ( defined(_MC9S12ZVL32_H) || defined(_MC9S12ZVL128_H) || \ + defined(_MC9S12ZVMA_H) || defined(_MC9S12ZVMB_H)) + #if (_SCI0_) + /* Set up for LIN PHY */ + /* Enable LIN PHY*/ + LP0CR_LPE = 1; + /* Turn on lin transmitter overcurrent interrupt */ + LP0IE_LPOCIE = 1; +#endif /* END SCI0 */ +#endif /* END ifdef _MC9S12ZVL32_H */ +#if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H)||defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H)) +#if (_SCI0_) + /* Set up for LIN PHY */ + /* Enable LIN PHY*/ + LPCR_LPE = 1; + /* Turn on lin transmitter overcurrent interrupt */ + LPIE_LPOCIE = 1; +#endif /* END SCI0 */ +#endif /* END if (defined(_MC9S12VR64_H)||defined(_MC9S12VR32_H)||defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H))*/ + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + lconf_p = (lin_configuration *)&lin_ifc_configuration[iii]; + + /* Config */ + lnode_p->ifc=(l_u8)iii; + lnode_p->response_buffer=lconf_p->response_buffer; + /* Set SCI is Master or Slave */ + lnode_p->func=(l_bool)lconf_p->function; + lnode_p->tbit=(l_u16)(1000000/lconf_p->baud_rate); + + /* Initialize SCI */ + /* Set baud rate */ + _pSCI->scisr2.byte = 0x00; + tmp = (l_u16)(MCU_BUS_FREQ/lconf_p->baud_rate); + _pSCI->scibdh.byte = (l_u8)(tmp>>8); + _pSCI->scibdl.byte = tmp&0xff; + + /* Enable SCI in wait mode and enable bit count after stop bit */ + _pSCI->scicr1.byte = SCICR1_ILT_MASK ; + /* Enable use of 13bit breaks and SCI frame for LIN */ + _pSCI->scisr2.byte = (SCISR2_AMAP_MASK | SCISR2_BRK13_MASK); + /* Enable mismatch error detection */ + _pSCI->sciasr1.byte = SCIASR1_BERRIF_MASK; + /* Enable bit error interrupt and break detect flags */ + _pSCI->sciacr1.byte = (SCIACR1_BERRIE_MASK | SCIACR1_BKDIE_MASK); + /* Enable break detect circuit and timing bit error detection at 9th time stick */ + _pSCI->sciacr2.byte = (SCIACR2_BERRM0_MASK | SCIACR2_BKDFE_MASK); + /* Enable tranceiver interrupt */ + _pSCI->scicr2.byte = (SCICR2_TE_MASK | SCICR2_RE_MASK | SCICR2_RIE_MASK); + + /* Dummy read */ + (void)_pSCI->scisr1.byte; + + /* Enter IDLE state */ + lin_goto_idle_state(channel); +#endif /* End (SCI_VERSION != SCI_V6) */ +} /* End function lin_lld_sci_init(sci_channel_name channel, l_ifc_handle iii) */ + + +void lin_lld_sci_deinit +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + lin_node *lnode_p; +#if (SCI_VERSION == SCI_V2) + lnode_p = &lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V2) */ +#if (SCI_VERSION == SCI_V4) + lnode_p = (lin_node *)&lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V4) */ + lnode_p->state=UNINIT; + lin_lld_sci_int_disable(channel); +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + lnode_p->state=UNINIT; + lin_lld_sci_int_disable(channel); +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_deinit(sci_channel_name channel) */ + + +void lin_lld_sci_tx_header +( + /* [IN] sci channel name */ + sci_channel_name channel, + /* [IN] PID to be send */ + l_u8 pid_id +) +{ + lin_node *lnode_p; +#if (SCI_VERSION == SCI_V2) + lnode_p = &lin_node_descrs[channel]; +#else + lnode_p = (lin_node *)&lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V2) */ + /* Check the SCI is Master ? */ + if(lnode_p->func) + { + return; + } + /* Make PID and put PID into the ongoing buffer */ + lnode_p->current_id = pid_id; + lnode_p->pid = lin_process_parity(pid_id, MAKE_PARITY); + /* Set LIN Status */ + lnode_p->state = SEND_BREAK; + /* Send Break*/ + lnode_p->pSCI->scicr2.byte |= SCICR2_SBK_MASK; + lnode_p->pSCI->scicr2.byte &= ~SCICR2_SBK_MASK; +} /* End function lin_lld_sci_tx_header(sci_channel_name channel, l_u8 pid_id) */ + + +void lin_lld_sci_tx_wake_up +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ +#if (SCI_VERSION == SCI_V2) + lin_node *lnode_p; + lnode_p = &lin_node_descrs[channel]; + if((lnode_p->state == IDLE) || (lnode_p->state == SLEEP_MODE)) + { + /* Send wake signal byte=0x80 */ + lnode_p->pSCI->scid.byte = 0x80; + + /* Set Lin state to idle */ + lin_goto_idle_state(channel); + } +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + lin_node *lnode_p; + l_u8 sci_flag_sr1; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + if((lnode_p->state == IDLE) || (lnode_p->state == SLEEP_MODE)) + { + sci_flag_sr1 = lnode_p->pSCI->scisr1.byte; + /* Send wake signal byte=0x80 */ + lnode_p->pSCI->scid.byte = SCID_R7_T7_MASK; + /* Set Lin state to idle */ + lin_goto_idle_state(channel); + } +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + if((lnode_p->state == IDLE) || (lnode_p->state == SLEEP_MODE)) + { + /* Send wake signal byte=0x80 */ + lnode_p->pSCI->scidrl.byte = SCIDRH_R8_MASK; + /* Set Lin state to idle */ + lin_goto_idle_state(channel); + } +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_tx_wake_up(sci_channel_name channel) */ + + +void lin_lld_sci_int_enable +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + lin_node *lnode_p; +#if (SCI_VERSION == SCI_V2) + lnode_p = &lin_node_descrs[channel]; +#else + lnode_p = (lin_node *)&lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V2) */ + + /* Can't enable in interrupt context */ + if((lnode_p->state == PROC_CALLBACK) || (lnode_p->state==UNINIT) || (lnode_p->state==SLEEP_MODE)) + { + return; + } + + /* Enable SCI Channel*/ + lnode_p->pSCI->scicr2.byte |= (SCICR2_RE_MASK | SCICR2_RIE_MASK); +} + + +void lin_lld_sci_int_disable +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + lin_node *lnode_p; +#if (SCI_VERSION == SCI_V2) + lnode_p = &lin_node_descrs[channel]; +#else + lnode_p = (lin_node *)&lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V2) */ + + /* Can't disable in interrupt context */ + if((lnode_p->state == PROC_CALLBACK) || (lnode_p->state==UNINIT) || (lnode_p->state==SLEEP_MODE)) + { + return; + } + + while(lnode_p->state != IDLE) {} + /* Disable SCI Channel*/ + lnode_p->pSCI->scicr2.byte &= ~(SCICR2_RE_MASK | SCICR2_RIE_MASK); +} + + +void lin_lld_sci_ignore_response +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + lin_goto_idle_state(channel); +} + + +void lin_lld_sci_set_low_power_mode +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + tSCI* _pSCI; + lin_node *lnode_p; + + /* Get Lin node descriptor */ + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + + /* Configure Hw code */ + + /* Set Lin status = receiving data*/ + lnode_p->state=SLEEP_MODE; +} + +void lin_lld_sci_rx_response +( + /* [IN] sci channel name */ + sci_channel_name channel, + /* [IN] Length of response data expect to wait */ + l_u8 msg_length +) +{ + lin_node *lnode_p; + + /* Get Lin node descriptor */ +#if (SCI_VERSION == SCI_V2) + lnode_p = &lin_node_descrs[channel]; +#else + lnode_p = (lin_node *)&lin_node_descrs[channel]; +#endif /* End (SCI_VERSION == SCI_V2) */ + + /* Put response length and pointer of response buffer into descriptor */ + *(lnode_p->response_buffer)=msg_length; + lnode_p->cnt_byte=0; + lnode_p->ptr=lnode_p->response_buffer; + + /* Set Lin status = receiving data*/ + lnode_p->state=RECV_DATA; +} + +void lin_lld_sci_tx_response +( + /* [IN] sci channel name */ + sci_channel_name channel) +{ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + + /* calculate checksum */ + lnode_p->response_buffer[*(lnode_p->response_buffer)+1] = lin_checksum(lnode_p->response_buffer , lnode_p->pid); + lnode_p->cnt_byte=1; + /* Send First byte */ + lnode_p->pSCI->scid.byte = lnode_p->response_buffer[1]; + /* Set LIN Status */ + lnode_p->state = SEND_DATA; + +#else + + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + + /* calculate checksum */ + lnode_p->response_buffer[*(lnode_p->response_buffer)+1] = lin_checksum(lnode_p->response_buffer , lnode_p->pid ); + lnode_p->cnt_byte=1; + /* Send First byte */ + lnode_p->pSCI->scidrl.byte = lnode_p->response_buffer[1]; + /* Set LIN Status */ + lnode_p->state = SEND_DATA; +#endif /* End (SCI_VERSION != SCI_V5) */ +} /* End function lin_lld_sci_tx_response(sci_channel_name channel) */ + + +l_u8 lin_lld_sci_get_status +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + return lnode_p->l_status.byte; +} + + +l_u8 lin_lld_sci_get_state(sci_channel_name channel) +{ + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + return lnode_p->state; +} + + +void lin_lld_sci_timeout +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + register lin_node *lnode_p; +#ifdef MULTI_TIMER_MODE + l_u8 i; +#endif /* End MULTI_TIMER_MODE */ + /* multi frame support */ + lin_configuration * conf; + lin_tl_descriptor *tl_conf; + l_ifc_handle iii; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + iii = (l_ifc_handle)lnode_p->ifc; + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if (LD_CHECK_N_CR_TIMEOUT == tl_conf->tl_check_timeout_type) + { + if(0 == --tl_conf->tl_check_timeout) + { + /* switch to normal table */ + if (_MASTER_ == conf->function) + { + *(conf->active_schedule_id) = *(conf->previous_schedule_id); + conf->schedule_start_entry[*(conf->active_schedule_id)] = 0; + } + /* update status of transport layer */ + *conf->diagnostic_mode = DIAG_NONE; + *conf->tl_service_status = LD_SERVICE_ERROR; + tl_conf->tl_receive_msg_status = LD_N_CR_TIMEOUT; + tl_conf->tl_rx_msg_status = LD_N_CR_TIMEOUT; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } + } + + if (LD_CHECK_N_AS_TIMEOUT == tl_conf->tl_check_timeout_type) + { + if(0 == --tl_conf->tl_check_timeout) + { + /* switch to normal table */ + if (_MASTER_ == conf->function) + { + *(conf->active_schedule_id) = *(conf->previous_schedule_id); + conf->schedule_start_entry[*(conf->active_schedule_id)] = 0; + } + /* update status of transport layer */ + *conf->diagnostic_mode = DIAG_NONE; + *conf->tl_service_status = LD_SERVICE_ERROR; + tl_conf->tl_tx_msg_status = LD_N_AS_TIMEOUT; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } + } +#else + if (LD_CHECK_N_AS_TIMEOUT == tl_check_timeout_type_array[iii]) + { + if(0 == --tl_check_timeout_array[iii]) + { + tl_conf->tl_service_status = LD_SERVICE_ERROR; + tl_check_timeout_type_array[iii] = LD_NO_CHECK_TIMEOUT; + } + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_)*/ + +#if (SCI_VERSION == SCI_V2) + + switch(lnode_p->state) + { + case IDLE: + if(lnode_p->idle_timeout_cnt==0) + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0xFF); + /* goback to IDLE, reset max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + } + else + { + lnode_p->idle_timeout_cnt--; + } + break; + + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == lnode_p->frame_timeout_cnt) + { + lin_goto_idle_state(channel); + } + else + { + lnode_p->frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(lnode_p->res_frame_timeout_cnt == 0) + { + if(lnode_p->cnt_byte) + { + /* set lin status: error_in_response */ + lnode_p->l_status.byte |= LIN_STA_ERROR_RESP; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_NODATA_TIMEOUT, lnode_p->current_id); + } + lin_goto_idle_state(channel); + } + else + { + lnode_p->res_frame_timeout_cnt--; + } + + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + + switch(lnode_p->state) + { + + case IDLE: + if(lnode_p->idle_timeout_cnt==0) + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0xFF); + /* goback to IDLE, reset max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + /* disable LIN break detect interrupt */ + lnode_p->pSCI->scisr2.bit.lbkde = 0; + } + else + { + lnode_p->idle_timeout_cnt--; + } + break; + + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == lnode_p->frame_timeout_cnt) + { + lin_goto_idle_state(channel); + } + else + { + lnode_p->frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(0 == lnode_p->res_frame_timeout_cnt) + { + if(lnode_p->cnt_byte) + { + /* set lin status: error_in_response */ + lnode_p->l_status.byte |= LIN_STA_ERROR_RESP; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_NODATA_TIMEOUT, lnode_p->current_id); + } + lin_goto_idle_state(channel); + } + else + { + lnode_p->res_frame_timeout_cnt--; + } + + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + + switch(lnode_p->state) + { + case IDLE: + if(lnode_p->idle_timeout_cnt==0) + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_BUS_ACTIVITY_TIMEOUT, 0xFF); + /* goback to IDLE, reset max idle timeout */ + #ifdef MULTI_TIMER_MODE + for(i=0; iidle_timeout_cnt=max_idle_timeout[i]; + break; + } + #else + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + #endif /* End (TIMER_MODE == MULTI_TIMER) */ + } + else + { + lnode_p->idle_timeout_cnt--; + } + break; + + case SEND_PID: /* Master */ + case RECV_SYN: + case RECV_PID: + case SEND_DATA: + case SEND_DATA_COMPLETED: + /* timeout send has occurred - change state of the node and inform core */ + if(0 == lnode_p->frame_timeout_cnt) + { + lin_goto_idle_state(channel); + } + else + { + lnode_p->frame_timeout_cnt--; + } + break; + case RECV_DATA: + /* timeout receive has occurred - change state of the node and inform core */ + if(0 == lnode_p->res_frame_timeout_cnt) + { + if(lnode_p->cnt_byte) + { + /* set lin status: error_in_response */ + lnode_p->l_status.byte |= LIN_STA_ERROR_RESP; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_NODATA_TIMEOUT, lnode_p->current_id); + } + lin_goto_idle_state(channel); + } + else + { + lnode_p->res_frame_timeout_cnt--; + } + break; + case PROC_CALLBACK: + break; + default: + break; + } +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_lld_sci_timeout(sci_channel_name channel) */ + +/*** INTERNAL FUNTIONS ***/ + + +void lin_goto_idle_state +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ +#if (SCI_VERSION == SCI_V2) + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + /* set lin status: ~bus_activity */ + lnode_p->l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + lnode_p->state=IDLE; +#endif /* End (SCI_VERSION == SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + /* set lin status: ~bus_activity */ + lnode_p->l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + lnode_p->state=IDLE; + /* Enable LBK detect */ + lnode_p->pSCI->scisr2.bit.lbkde = 1; +#endif /* End (SCI_VERSION == SCI_V4) */ + +/*--------------------------------------------------------------------*/ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) + lin_node *lnode_p; + tSCI* _pSCI; +#ifdef MULTI_TIMER_MODE + l_u8 i; +#endif /* End MULTI_TIMER_MODE */ + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + /* set lin status: ~bus_activity */ + lnode_p->l_status.byte &= ~LIN_STA_BUS_ACTIVITY; + /* Set max idle timeout */ +#ifdef MULTI_TIMER_MODE + for(i=0; iidle_timeout_cnt=max_idle_timeout[i]; + break; + } +#else + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; +#endif /* End MULTI_TIMER_MODE */ + lnode_p->state=IDLE; +#endif /* End (SCI_VERSION == SCI_V5) */ +} /* End function lin_goto_idle_state(sci_channel_name channel) */ +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) +void lin_lld_sci_err_isr +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ +#if (SCI_VERSION == SCI_V2) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + register lin_node *lnode_p; /* local pointer to the lin node descriptor */ + volatile tSCI *_pSCI; + + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + + sci_flag_sr1 = _pSCI->scisr1.byte; + tmp_byte = _pSCI->scid.byte; + /****************************** + *** 1. BREAK DETECTED + *******************************/ + if(0x00 == tmp_byte) + { + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == lnode_p->state) + { + lin_goto_idle_state(channel); + return; + } + /* Reset lin status */ + lnode_p->l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + lnode_p->frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][7]; + /****************************** + *** 1.1 MASTER NODE: Sending SYN field + *******************************/ + if(lnode_p->func == _MASTER_/* Master */) + { + lnode_p->state=SEND_PID; + /* Send syn field */ + _pSCI->scid.byte = 0x55; + } + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + else + { + lnode_p->state=RECV_SYN; + } + + return; + } + /****************************** + *** 3. FRAME ERROR DETECTED + *******************************/ + else + { + /* set lin status: error_in_response, framing_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* Trigger callback */ + if((lnode_p->state == RECV_DATA)||(lnode_p->state == SEND_DATA)||(lnode_p->state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_FRAME_ERR, lnode_p->current_id); + } + lin_goto_idle_state(channel); + } +#endif /* End (SCI_VERSION = SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + /* local pointer to the lin node descriptor */ + register lin_node *lnode_p; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + + sci_flag_sr1 = lnode_p->pSCI->scisr1.byte; + tmp_byte = lnode_p->pSCI->scid.byte; + + /****************************** + *** 3. FRAME ERROR DETECTED + *******************************/ + /* set lin status: error_in_response, framing_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* Trigger callback */ + if((lnode_p->state == RECV_DATA)||(lnode_p->state == SEND_DATA)||(lnode_p->state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_FRAME_ERR, lnode_p->current_id); + } + lin_goto_idle_state(channel); +#endif /* End (SCI_VERSION = SCI_V4) */ +} /* End function lin_lld_sci_err_isr(sci_channel_name channel) */ + +void lin_lld_sci_rx_isr +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ +#if (SCI_VERSION == SCI_V2) + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + + /* local pointer to the lin node descriptor */ + register lin_node *lnode_p; + /* pointer to the SCI peripheral */ + volatile tSCI* _pSCI; + + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + + sci_flag_sr1 = _pSCI->scisr1.byte; + tmp_byte = _pSCI->scid.byte; + /* Set max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_RDRF_MASK)) + { + switch(lnode_p->state) + { + /****************************** + *** 4.1 MASTER: Sending PID of frame + *******************************/ + case SEND_PID: + lnode_p->state=RECV_PID; + /* Send PID byte */ + _pSCI->scid.byte = lnode_p->pid; + break; + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55U == tmp_byte) + { + lnode_p->state=RECV_PID; + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(channel); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + if(lnode_p->func == _MASTER_) /*Master*/ + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer) - 1]; + } + else /* Slave node */ + { + /* checkparity and extrait PID */ + lnode_p->current_id= lin_process_parity(tmp_byte, CHECK_PARITY); + lnode_p->pid = tmp_byte; + if(lnode_p->current_id != 0xFFU) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer) - 1]; + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* set lin status: parity_error */ + lnode_p->l_status.byte |= LIN_STA_PARITY_ERR; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_ERR, 0x00); + lin_goto_idle_state(channel); + } + } + break; + + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + lnode_p->ptr++; + *(lnode_p->ptr)=tmp_byte; + /* Check bytes received fully */ + if(lnode_p->cnt_byte==(lnode_p->response_buffer[0])) + { + /* checksum checking */ + if(lin_checksum(lnode_p->response_buffer, lnode_p->pid)==tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* set lin status: successful_transfer */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_RX_COMPLETED, lnode_p->current_id); + if (SLEEP_MODE != lnode_p->state) + { + lin_goto_idle_state(channel); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* set lin status: error_in_response, checksum_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_CHECKSUM_ERR, lnode_p->current_id); + lin_goto_idle_state(channel); + } + } + lnode_p->cnt_byte++; + break; + + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + /* Check for READBACK error */ + if (0==(sci_flag_sr1&SCISR1_TC_MASK)) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lin_goto_idle_state(channel); + break; + } + else + { + if (tmp_byte != lnode_p->response_buffer[lnode_p->cnt_byte]) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lin_goto_idle_state(channel); + break; + } + } + + if(lnode_p->cnt_byte <= (lnode_p->response_buffer[0])) + { + /* Send data bytes and checksum */ + lnode_p->cnt_byte++; + _pSCI->scid.byte = lnode_p->response_buffer[lnode_p->cnt_byte]; + } + else + { + /* TX transfer complete */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_TX_COMPLETED, lnode_p->current_id); + lin_goto_idle_state(channel); + } + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + if ((tmp_byte == 0xF0U) || (tmp_byte == 0xE0U) || (tmp_byte == 0xC0U) || (tmp_byte == 0x80U) || (tmp_byte == 0x00U)) + { + /* Set idle timeout again */ + lin_goto_idle_state(channel); + } + break; + default: + break; + } + } +#endif /* End (SCI_VERSION = SCI_V2) */ + +/*--------------------------------------------------------------------*/ + +#if (SCI_VERSION == SCI_V4) + l_u8 sci_flag_sr1; + l_u8 sci_flag_sr2; + l_u8 tmp_byte; + + register lin_node *lnode_p; /* local pointer to the lin node descriptor */ + volatile tSCI* _pSCI; + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + + sci_flag_sr2 = _pSCI->scisr2.byte ; + /* Set max idle timeout */ + lnode_p->idle_timeout_cnt=_MAX_IDLE_TIMEOUT_; + + if((sci_flag_sr2 & SCISR2_RXEDGIF_MASK) && (!(sci_flag_sr2 & SCISR2_LBKDIF_MASK))) + { + /* Clear flag */ + _pSCI->scisr2.bit.rxedgif = 1; + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == lnode_p->state) + { + lin_goto_idle_state(channel); + } + + /* Enable Break interrupt */ + _pSCI->scibdh.byte |= SCIBDH_LBKDIE_MASK ; + /* Disable Active Edge interrupt */ + _pSCI->scibdh.byte &= ~SCIBDH_RXEDGIE_MASK; + + /* Receive data not inverted */ + _pSCI->scisr2.bit.rxinv = 0; + return; + } + + /* Check LBK flag */ + if (1 == _pSCI->scisr2.bit.lbkdif) + { + /* Clear flag */ + _pSCI->scisr2.bit.lbkdif = 1; + /* Enable Active Edge interrupt */ + _pSCI->scibdh.byte |= SCIBDH_RXEDGIE_MASK; + /* Disable Break interrupt */ + _pSCI->scibdh.byte &= ~SCIBDH_LBKDIE_MASK ; + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == lnode_p->state) + { + lin_goto_idle_state(channel); + return; + } + /* Reset lin status */ + lnode_p->l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + lnode_p->frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][7]; + /****************************** + *** 1.1 MASTER NODE: Sending SYN field + *******************************/ + if(lnode_p->func == 0/* Master */) + { + lnode_p->state=SEND_PID; + /* Send syn field */ + _pSCI->scid.byte = 0x55; + } + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + else + { + lnode_p->state=RECV_SYN; + } + /* Disable LBK interrupt */ + _pSCI->scisr2.bit.lbkde = 0; + return; + } + else + { + sci_flag_sr1 = lnode_p->pSCI->scisr1.byte; + tmp_byte = lnode_p->pSCI->scid.byte; + + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_RDRF_MASK)) + { + + switch(lnode_p->state) + { + /****************************** + *** 4.1 MASTER: Sending PID of frame + *******************************/ + case SEND_PID: + lnode_p->state=RECV_PID; + /* Send PID byte */ + _pSCI->scid.byte = lnode_p->pid; + break; + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55 == tmp_byte) + { + lnode_p->state=RECV_PID; + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(channel); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + if(!lnode_p->func) /*Master*/ + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer) - 1]; + } + else /* Slave node */ + { + /* checkparity and extrait PID */ + lnode_p->current_id= lin_process_parity(tmp_byte, CHECK_PARITY); + /* Keep the PID */ + lnode_p->pid = tmp_byte; + if(lnode_p->current_id !=0xFF) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer) - 1]; + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* Set lin status: parity_error */ + lnode_p->l_status.byte |= LIN_STA_PARITY_ERR; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_ERR, 0xFF); + lin_goto_idle_state(channel); + } + } + break; + + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + lnode_p->ptr++; + *(lnode_p->ptr)=tmp_byte; + /* Check bytes received fully */ + if(lnode_p->cnt_byte==(lnode_p->response_buffer[0])) + { + /* Checksum checking */ + if(lin_checksum(lnode_p->response_buffer, lnode_p->pid)==tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* Set lin status: successful_transfer */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_RX_COMPLETED, lnode_p->current_id); + if (SLEEP_MODE != lnode_p->state) + { + lin_goto_idle_state(channel); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* Set lin status: error_in_response, checksum_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_CHECKSUM_ERR, lnode_p->current_id); + + lin_goto_idle_state(channel); + } + } + lnode_p->cnt_byte++; + break; + + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + /* Check for READBACK error */ + if (0==(sci_flag_sr1&SCISR1_TC_MASK)) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lin_goto_idle_state(channel); + break; + } + else + { + if (tmp_byte != lnode_p->response_buffer[lnode_p->cnt_byte]) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lin_goto_idle_state(channel); + break; + } + } + + if(lnode_p->cnt_byte <= (lnode_p->response_buffer[0])) + { + /* Send data bytes and checksum */ + lnode_p->cnt_byte++; + _pSCI->scid.byte = lnode_p->response_buffer[lnode_p->cnt_byte]; + } + else + { + /* TX transfer complete */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_TX_COMPLETED, lnode_p->current_id); + lin_goto_idle_state(channel); + } + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + if ((tmp_byte == 0xF0U) || (tmp_byte == 0xE0U) || (tmp_byte == 0xC0U) || (tmp_byte == 0x80U) || (tmp_byte == 0x00U)) + { + /* Set idle timeout again */ + lin_goto_idle_state(channel); + /* Disable LIN break detect interrupt */ + _pSCI->scisr2.bit.lbkde = 1; + } + break; + default: + break; + } + } + } +#endif /* End (SCI_VERSION = SCI_V4) */ +} /* End function lin_lld_sci_rx_isr(sci_channel_name channel) */ +#endif /* End((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) */ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +void lin_lld_sci_isr +( + /* [IN] sci channel name */ + sci_channel_name channel +) +{ + l_u8 sci_flag_sr1; + l_u8 tmp_byte; + l_u8 i; + + /* Local pointer to the lin node descriptor */ + register lin_node *lnode_p; + /* Pointer to the SCI peripheral */ + volatile tSCI* _pSCI; + + lnode_p = (lin_node *)&lin_node_descrs[channel]; + _pSCI = lnode_p->pSCI; + + sci_flag_sr1 = _pSCI->scisr1.byte; + + /* Set max idle timeout */ + #ifdef MULTI_TIMER_MODE + for(i = 0; i < LIN_NUM_OF_IFCS; i++) + if (channel == lin_virtual_ifc[i]) + { + lnode_p->idle_timeout_cnt = max_idle_timeout[i]; + break; + } + #else + lnode_p->idle_timeout_cnt = _MAX_IDLE_TIMEOUT_; + #endif /* MULTI_TIMER_MODE */ + + /****************************** + *** 1. BREAK DETECTED + *******************************/ + if(0 != (_pSCI->sciasr1.byte&SCIASR1_BKDIF_MASK)) + { + /* Clear the error flag */ + _pSCI->sciasr1.byte |=SCIASR1_BKDIF_MASK; + /* check state of node is SLEEP_MODE */ + if (SLEEP_MODE == lnode_p->state) + { + lin_goto_idle_state(channel); + return; + } + + /* Handle error */ + if((RECV_DATA == lnode_p->state) || (SEND_DATA == lnode_p->state) || (SEND_DATA_COMPLETED == lnode_p->state)) + { + /* Read dummy data to clear FE flags */ + tmp_byte = _pSCI->scidrl.byte; + /* Set lin status: error_in_response, framing_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_FRAME_ERR, lnode_p->current_id); + } + + /* Reset lin status */ + lnode_p->l_status.byte = LIN_STA_BUS_ACTIVITY; + /* Set max frame timeout */ + lnode_p->frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][7]; + /****************************** + *** 1.1 MASTER NODE: Sending SYN field + *******************************/ + if(lnode_p->func == 0/* Master */) + { + lnode_p->state=SEND_PID; + /* Send syn field */ + _pSCI->scidrl.byte = 0x55; + } + /****************************** + *** 1.2 SLAVE NODE: Wait for SYN + *******************************/ + else + { + lnode_p->state=RECV_SYN; + } + return; + } + /****************************** + *** 2. BIT ERROR DETECTED + *******************************/ + else if(0 != (_pSCI->sciasr1.byte&SCIASR1_BERRIF_MASK)) + { + _pSCI->sciasr1.byte |= SCIASR1_BERRIF_MASK; + /* set lin status: error_in_response, readback_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_READBACK_ERR); + if((lnode_p->state == SEND_DATA)||(lnode_p->state == SEND_DATA_COMPLETED)) + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + /* If Bit error occurs when a logic 0 is accepted as stop bit, then this case causes Framing error too*/ + /* In this case, wait for about 20 for loops, so that SCI hardware have enough time to set Framing error flag*/ + for (i=0; i<200; i++); + /* Check if Framing error flag is set */ + if(0 != (_pSCI->scisr1.byte&SCISR1_FE_MASK)) + { + return; + } + } + lin_goto_idle_state(channel); + return; + } + + /****************************** + *** 3. FRAME ERROR DETECTED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_FE_MASK)) + { + /* Clear FE flags */ + _pSCI->scisr1.byte |= SCISR1_FE_MASK; + tmp_byte = _pSCI->scidrl.byte; + /* Set lin status: error_in_response, framing_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_FRAME_ERR); + /* Trigger callback */ + if((lnode_p->state == RECV_DATA)||(lnode_p->state == SEND_DATA) || (lnode_p->state == SEND_DATA_COMPLETED)) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_FRAME_ERR, lnode_p->current_id); + } + lin_goto_idle_state(channel); + } + /****************************** + *** 4. BYTE RECIEVED + *******************************/ + else if(0 != (sci_flag_sr1&SCISR1_RDRF_MASK)) + { + tmp_byte = _pSCI->scidrl.byte; + switch(lnode_p->state) + { + /****************************** + *** 4.1 MASTER: Sending PID of frame + *******************************/ + case SEND_PID: + lnode_p->state=RECV_PID; + /* Send PID byte */ + _pSCI->scidrl.byte = lnode_p->pid; + break; + /****************************** + *** 4.2 SLAVE: Receiving SYN byte + *******************************/ + case RECV_SYN: + if (0x55 == tmp_byte) + { + lnode_p->state=RECV_PID; + } + else + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + #endif /* End of (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_goto_idle_state(channel); + } + break; + /****************************** + *** 4.3 SLAVE: Receiving PID + *******************************/ + case RECV_PID: + if(!lnode_p->func) /*Master*/ + { + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer)-1]; + } + else /* Slave node */ + { + /* Checkparity and extrait PID */ + lnode_p->pid=tmp_byte; + lnode_p->current_id = lin_process_parity(tmp_byte,CHECK_PARITY); + if(lnode_p->current_id !=0xFF) + { + /*****************************************/ + /*** ID received correctly - parity OK ***/ + /*****************************************/ + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_OK, lnode_p->current_id); + /* Set Maximum response frame timeout */ + lnode_p->res_frame_timeout_cnt = lin_max_frame_res_timeout_val[lnode_p->ifc][*(lnode_p->response_buffer)-1]; + } + else + { + /*****************************************/ + /*** ID Parity Error ***/ + /*****************************************/ + /* Set lin status: parity_error */ + lnode_p->l_status.byte |= LIN_STA_PARITY_ERR; + /* Crigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_PID_ERR, 0xFF); + lin_goto_idle_state(channel); + } + } + break; + + /****************************** + *** 4.4 SLAVE: Receiving data + *******************************/ + case RECV_DATA: + lnode_p->ptr++; + *(lnode_p->ptr)=tmp_byte; + /* Check bytes received fully */ + if(lnode_p->cnt_byte==(lnode_p->response_buffer[0])) + { + /* Checksum checking */ + if(lin_checksum(lnode_p->response_buffer, lnode_p->pid)==tmp_byte) + { + /*******************************************/ + /*** RX Buffer Full - Checksum OK ***/ + /*******************************************/ + /* Set lin status: successful_transfer */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_RX_COMPLETED, lnode_p->current_id); + + if (SLEEP_MODE != lnode_p->state) + { + lin_goto_idle_state(channel); + } + } + else + { + /*******************************************/ + /*** RX Buffer Full - Checksum ERROR ***/ + /*******************************************/ + /* set lin status: error_in_response, checksum_error */ + lnode_p->l_status.byte |= (LIN_STA_ERROR_RESP|LIN_STA_CHECKSUM_ERR); + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_CHECKSUM_ERR, lnode_p->current_id); + + lin_goto_idle_state(channel); + } + } + lnode_p->cnt_byte++; + break; + + /****************************** + *** 4.5 SLAVE: Sending data + *******************************/ + case SEND_DATA: + if (0 == (sci_flag_sr1&SCISR1_TC_MASK )) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lnode_p->state = PROC_CALLBACK; + lin_goto_idle_state(channel); + break; + } + if(lnode_p->cnt_byte==(lnode_p->response_buffer[0])) + { + /* Send checksum byte */ + _pSCI->scidrl.byte = lnode_p->response_buffer[lnode_p->cnt_byte+1]; + lnode_p->state= SEND_DATA_COMPLETED; + } + else + { + /* Send byte next */ + lnode_p->cnt_byte++; + _pSCI->scidrl.byte = lnode_p->response_buffer[lnode_p->cnt_byte]; + } + break; + /****************************** + *** 4.7 SLAVE: Sending data compeleted + *******************************/ + case SEND_DATA_COMPLETED: + /*******************************************/ + /*** TX Buffer Empty - Checksum Sent ***/ + /*******************************************/ + if (0 == (sci_flag_sr1&SCISR1_TC_MASK )) + { + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_READBACK_ERR, lnode_p->current_id); + lnode_p->state = PROC_CALLBACK; + lin_goto_idle_state(channel); + break; + } + /* set lin status: successful_transfer */ + lnode_p->l_status.byte |= LIN_STA_SUCC_TRANSFER; + lnode_p->state = PROC_CALLBACK; + /* Trigger callback */ + CALLBACK_HANDLER((l_ifc_handle)lnode_p->ifc, LIN_LLD_TX_COMPLETED, lnode_p->current_id); + lin_goto_idle_state(channel); + break; + /****************************** + *** 4.8 SLAVE: Low power mode + *******************************/ + case SLEEP_MODE: + if ((tmp_byte == 0xFFU) || (tmp_byte == 0xFEU) || (tmp_byte == 0xFCU) || (tmp_byte == 0xF8U) || (tmp_byte == 0xF0U)|| (tmp_byte == 0xE0U)|| (tmp_byte == 0xC0U)|| (tmp_byte == 0x80U)|| (tmp_byte == 0x00U)) + { + /* Set idle timeout again */ + lin_goto_idle_state(channel); + } + break; + default: + break; + } + } + + /****************************** + *** 5. OVERRUN ERROR DETECTED + *******************************/ + if(0 != (sci_flag_sr1&SCISR1_OR_MASK)) + { + /* Read SCIDRL Register to clear OR flag*/ + tmp_byte = _pSCI->scidrl.byte; + lin_goto_idle_state(channel); + } + +} /* End function lin_lld_sci_isr(sci_channel_name channel) */ +#endif /* End (SCI_VERSION = SCI_V5) */ + +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/** +* @} +*/ + diff --git a/LIN_Stack/bsp/SCI/lin_lld_sci.h b/LIN_Stack/bsp/SCI/lin_lld_sci.h new file mode 100644 index 0000000..3f6a8c7 --- /dev/null +++ b/LIN_Stack/bsp/SCI/lin_lld_sci.h @@ -0,0 +1,811 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup SCI_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file bsp/SCI/lin_lld_sci.h +* +* @author FPT Software +* +* @brief SCI for LIN network +* +******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * 20101027 v1.0 First version + * 20111005 v1.1 Updated hardware support, multi timers + * + *****************************************************************************/ + +#ifndef __LIN_LLD_SCI +#define __LIN_LLD_SCI + +/* MODULE LIN_LLD_SCI. */ + +#include "lin_reg.h" +#include "lin_cfg.h" +#include "lin.h" + +#ifndef SCI_VERSION +#error "SCI_VERSION is not defined in lin_hw_cfg.h" +#endif + +/*** MARCOS ***/ +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +#define LIN_LLD_SCI_MCU_RESET { COPCTL = 0x01; ARMCOP = 0x00;} /**< MCU reset */ +#endif /* End (SCI_VERSION == SCI_V5) */ + +/* Define _MC9S12ZVMB_H for all MCU of MC9S12ZVMB Family */ +#if (defined(_MC9S12ZVMB48_H) || defined(_MC9S12ZVMBA48_H) || defined(_MC9S12ZVMB64_H) || defined(_MC9S12ZVMBA64_H)) +#define _MC9S12ZVMB_H +#endif /* End (defined(_MC9S12ZVMB48_H) || defined(_MC9S12ZVMBA48_H) || defined(_MC9S12ZVMB64_H) || defined(_MC9S12ZVMBA64_H))*/ + +/* Define _MC9S12ZVMA_H for all MCU of MC9S12ZVMB Family*/ +#if (defined(_MC9S12ZVMA32_H) || defined(_MC9S12ZVMAL32_H) || defined(_MC9S12ZVMA16_H) || defined(_MC9S12ZVMAL16_H)) +#define _MC9S12ZVMA_H +#endif /* End defined(_MC9S12ZVMA32_H) || defined(_MC9S12ZVMAL32_H) || defined(_MC9S12ZVMA16_H) || defined(_MC9S12ZVMAL16_H) */ + +/* Lin status bit mask */ +#define LIN_STA_SUCC_TRANSFER 1 /**< LIN status bit mask: success transfer */ +#define LIN_STA_ERROR_RESP 2 /**< LIN status bit mask: error in response */ +#define LIN_STA_BUS_ACTIVITY 4 /**< LIN status bit mask: bus activity */ +#define LIN_STA_FRAME_ERR 8 /**< LIN status bit mask: frame error */ +#define LIN_STA_CHECKSUM_ERR 16 /**< LIN status bit mask: checksum error */ +#define LIN_STA_READBACK_ERR 32 /**< LIN status bit mask: readback error */ +#define LIN_STA_PARITY_ERR 64 /**< LIN status bit mask: parity error */ +#define LIN_STA_RESET 128 /**< LIN status bit mask: reset */ + + +#if (LIN_MODE == _SLAVE_MODE_) +/* Low-level API prototype */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_init(l_ifc_handle iii) +* @brief SCI v5 init +* +* @param iii [IN] lin interface handle +* +* @SDD_ID LIN_SDD_168 +* @endif +* +* @return #void +* +* @local_var +* -# #l_u16 temp +* +* +* @details Init SCI for LIN network +* +* +* @see #lin_goto_idle_state +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_init(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_deinit() +* @brief SCI deinit +* +* @SDD_ID LIN_SDD_169 +* @endif +* +* @return #void +* +* @details +* Deinit SCI for LIN network +*//*END*----------------------------------------------------------------------*/ + +#if (AUTOBAUD == 1) +void lin_lld_sci_init_autobaud(l_u16 baudrate); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_deinit() +* @brief SCI deinit +* +* @SDD_ID LIN_SDD_169 +* @endif +* +* @return #void +* +* @details +* Deinit SCI for LIN network +*//*END*----------------------------------------------------------------------*/ +#endif + +void lin_lld_sci_deinit(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_tx_wake_up() +* @brief This function requests to send wake up signal via SCI channel +* +* +* @SDD_ID LIN_SDD_170 +* @endif +* +* @return #void +* +* +* @details +* This function requests to send wake up signal via SCI channel +* Send 4Tbit to 64 Tbit +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_tx_wake_up(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_int_enable() +* @brief This function enables SCI Interrupt +* +* @SDD_ID LIN_SDD_171 +* @endif +* +* @return #void +* +* @details +* This function enables SCI Interrupt +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_int_enable(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_int_disable() +* @brief This function disables SCI Interrupt +* +* @SDD_ID LIN_SDD_172 +* @endif +* +* @return #void +* +* @details +* This function disables SCI Interrupt +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_int_disable(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_ignore_response() +* @brief Set low level ignore flag lin_lld_ignore_flag +* +* @SDD_ID LIN_SDD_173 +* @endif +* +* @return #void +* +* @details +* Set low level ignore flag lin_lld_ignore_flag +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_ignore_response(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_set_low_power_mode() +* @brief Request to enter low power mode in SCI Driver +* +* @SDD_ID LIN_SDD_174 +* @endif +* +* @return #void +* +* @details +* Request to enter low power mode in SCI Driver +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_set_low_power_mode(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_rx_response(l_u8 msg_length) +* +* @param msg_length IN length of response data expect to wait +* +* @brief This function requests to receive response data of LIN frame via SCI channel +* +* @SDD_ID LIN_SDD_175 +* @endif +* +* @return #void +* +* @details +* This function requests to receive response data of LIN frame via SCI channel +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_rx_response(l_u8 msg_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_tx_response() +* +* @brief This function requests to send first data and set lin_lld_state to SEND_DATA +* +* @SDD_ID LIN_SDD_179 +* @endif +* +* @return #void +* +* +* @details +* This function requests to send first data and set lin_lld_state to SEND_DATA +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_tx_response(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_sci_get_status() +* +* @brief Get LIN status ( return lin_status ) +* +* @SDD_ID LIN_SDD_180 +* @endif +* +* @return #l_u8 +* +* @details +* Get LIN status ( return lin_status ) +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_sci_get_status(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_sci_get_state() +* +* @brief This function is to get state of Low level layer +* +* @SDD_ID LIN_SDD_181 +* @endif +* +* @return #l_u8 +* +* @details +* This function is to get state of Low level layer +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_sci_get_state(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_timeout() +* +* @brief This function is called in period Tbit in order to check timeout for IDLE and MAXFRAME +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @return #void +* +* @details +* This function is called in period Tbit in order to check timeout for IDLE and MAXFRAME +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_timeout(void); + + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_err_isr ( ) +* @brief SCI Interrupt service routine that handles SCI Error +* +* @return #void +* +* @SDD_ID LIN_SDD_187 +* @endif +* +* @local_var +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 tmp_byte +* +* @static_global_var +* -# #pSCI +* -# #l_status +* -# #state +* -# #l_ifc_handle +* -# #current_id +* -# #ifc +* +* @details +* SCI Interrupt service routine that handles SCI Error +* +* @see #lin_goto_idle_state +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_err_isr(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_rx_isr ( ) +* @brief SCI Interrupt service routine that handles RX LIN Communication +* +* @return #void +* +* @SDD_ID LIN_SDD_188 +* @endif +* +* @local_var +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 sci_flag_sr2 +* -# #l_u8 tmp_byte +* +* @static_global_var +* -# #pSCI +* -# #l_status +* -# #frame_timeout_cnt +* -# #lin_max_frame_res_timeout_val +* -# #current_id +* -# #ifc +* -# #l_ifc_handle +* -# #response_buffer +* +* @details +* SCI Interrupt service routine that handles RX LIN Communication +* +* @see #lin_checksum +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_rx_isr(void); +#else + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_isr() +* +* @brief SCI Interrupt service routine that handles LIN Communication +* +* @SDD_ID LIN_SDD_189 +* @endif +* +* @return #void +* +* @local_var +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 tmp_byte +* +* @details +* SCI Interrupt service routine that handles LIN Communication +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_isr(void); + +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*** INTERNAL FUNCTIONS ***/ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_goto_idle_state() +* +* @brief Enter IDLE state +* +* @SDD_ID LIN_SDD_182 +* @endif +* +* @return #void +* +* @details +* Enter IDLE state +*//*END*----------------------------------------------------------------------*/ +void lin_goto_idle_state(void); + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + +#if LIN_MODE == _MASTER_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_init(sci_channel_name channel, l_ifc_handle iii) +* +* @param channel IN sci channel name +* @param iii IN LIN interface name +* +* @brief SCI Init +* +* @SDD_ID LIN_SDD_97 +* @endif +* +* @return #void +* +* @local_var +* -# #l_u16 *tmp +* -# #lin_node *lnode_p +* -# #lin_configuration *lconf_p +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see lin_goto_idle_state +* +* @details +* This function is inited SCI for LIN network +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_init(sci_channel_name channel, l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_deinit(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief SCI deinit +* +* @SDD_ID LIN_SDD_98 +* @endif +* +* @return #void +* +* +* @static_global_var +* -# #lin_node +* -# #lnode_p +* +* @see lin_lld_sci_int_disable +* @see lin_node_descrs +* +* @details +* This function is deinited SCI +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_deinit(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_tx_header(sci_channel_name channel, l_u8 pid_id) +* +* @param channel IN sci channel name +* @param pid_id IN PID to be send +* +* @brief This function requests to send header of LIN frame via SCI channel +* +* @SDD_ID LIN_SDD_99 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* +* @see lin_process_parity +* @see lin_node_descrs +* +* @details +* This function requests to send header of LIN frame via SCI channel +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_tx_header(sci_channel_name channel, l_u8 pid_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_tx_wake_up(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief This function requests to send wake up signal via SCI channel. +* +* @SDD_ID LIN_SDD_100 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @see lin_goto_idle_state +* +* @details +* This function requests to send wake up signal via SCI channel. +* Send 4Tbit to 64 Tbit +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_tx_wake_up(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_int_enable(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief This function enables SCI Interrupt +* +* @SDD_ID LIN_SDD_101 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* +* @details +* This function enables SCI Interrupt +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_int_enable(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_int_disable(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief This function disables SCI Interrupt +* +* @SDD_ID LIN_SDD_102 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* +* @details +* This function disables SCI Interrupt +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_int_disable(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_ignore_response(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief Set low level ignore flag lin_lld_ignore_flag +* +* @SDD_ID LIN_SDD_103 +* @endif +* +* @return #void +* +* @see lin_goto_idle_state +* +* @details +* Set low level ignore flag lin_lld_ignore_flag +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_ignore_response(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_set_low_power_mode(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief Request to enter low power mode in SCI Driver +* +* @SDD_ID LIN_SDD_104 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* Request to enter low power mode in SCI Driver +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_set_low_power_mode(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_rx_response(sci_channel_name channel, l_u8 msg_length) +* +* @param channel IN sci channel name +* @param msg_length IN length of response data expect to wait +* +* @brief This function requests to receive response data of LIN frame via SCI channel +* +* @SDD_ID LIN_SDD_105 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* This function requests to receive response data of LIN frame via SCI channel +*//*END*----------------------------------------------------------------------*/ + +void lin_lld_sci_rx_response(sci_channel_name channel,l_u8 msg_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_tx_response(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief This function requests to send first data and set lin_lld_state to SEND_DATA +* +* @SDD_ID LIN_SDD_109 +* @endif +* +* @return #void +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* This function requests to send first data and set lin_lld_state to SEND_DATA +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_tx_response(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_sci_get_status(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief Get LIN status ( return lin_status ) +* +* @SDD_ID LIN_SDD_110 +* @endif +* +* @return #l_u8 +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* Get LIN status ( return lin_status ) +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_sci_get_status(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_sci_get_state(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief Get LIN state ( return state ) +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @return #l_u8 +* +* @local_var +* -# #lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* Get LIN state ( return state ) +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_sci_get_state(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_timeout(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief This function is called in period Tbit in order to check timeout for IDLE and MAXFRAME +* +* @SDD_ID LIN_SDD_111 +* @endif +* +* @return #void +* +* @local_var +* -# #register lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* This function is called in period Tbit in order to check timeout for IDLE and MAXFRAME +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_timeout(sci_channel_name channel); + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_err_isr ( sci_channel_name channel) +* @brief SCI Interrupt service routine that handles SCI Error +* +* @param channel [IN] sci channel name +* +* @return #void +* +* @SDD_ID LIN_SDD_115 +* @endif +* +* @local_var +* -# #lin_node *lnode_p +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 tmp_byte +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* SCI Interrupt service routine that handles SCI Error +* +* @see #lin_goto_idle_state +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_err_isr(sci_channel_name channel); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_rx_isr ( sci_channel_name channel) +* @brief SCI Interrupt service routine that handles RX LIN Communication +* +* @param channel [IN] sci channel name +* +* @return #void +* +* @SDD_ID LIN_SDD_116 +* @endif +* +* @local_var +* -# #register lin_node *lnode_p +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 sci_flag_sr2 +* -# #l_u8 tmp_byte +* +* @static_global_var +* -# #lin_node_descrs +* -# #lin_max_frame_res_timeout_val +* +* @details +* SCI Interrupt service routine that handles RX LIN Communication +* +* @see #lin_goto_idle_state +* @see #lin_process_parity +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_rx_isr(sci_channel_name channel); +#else + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_sci_isr(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief SCI Interrupt service routine that handles LIN Communication +* +* @SDD_ID LIN_SDD_117 +* @endif +* +* @return #void +* +* @local_var +* -# #l_u8 sci_flag_sr1 +* -# #l_u8 tmp_byte +* -# #register lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @see #lin_goto_idle_state +* @see #lin_checksum +* @see #lin_process_parity +* +* @details +* SCI Interrupt service routine that handles LIN Communication +*//*END*----------------------------------------------------------------------*/ +void lin_lld_sci_isr(sci_channel_name channel); +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_goto_idle_state(sci_channel_name channel) +* +* @param channel IN sci channel name +* +* @brief Enter IDLE state +* +* @SDD_ID LIN_SDD_112 +* @endif +* +* @return #void +* +* @local_var +* -# #register lin_node *lnode_p +* +* @static_global_var +* -# #lin_node_descrs +* +* @details +* Enter IDLE state +*//*END*----------------------------------------------------------------------*/ +void lin_goto_idle_state(sci_channel_name channel); +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#endif /* ifndef _LIN_LLD_SCI */ + +/** +* @} +*/ diff --git a/LIN_Stack/bsp/SCI/lin_lld_timesrv.c b/LIN_Stack/bsp/SCI/lin_lld_timesrv.c new file mode 100644 index 0000000..5abd8d9 --- /dev/null +++ b/LIN_Stack/bsp/SCI/lin_lld_timesrv.c @@ -0,0 +1,423 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup SCI_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file bsp/SCI/lin_lld_timesrv.c +* +* @author FPT Software +* +* @brief Timer for S08, S12, S12X +* +******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * 20101027 v1.0 First version + * 20111005 v1.1 Updated hardware support + * 20111121 v1.2 Updated timer config for J637 + * + *****************************************************************************/ + +#include "lin_lld_timesrv.h" +#include "lin_lld_sci.h" +#include "lin_common_proto.h" +#include "lin_hw_cfg.h" + +#if defined(_MC9S12I32_H) +#include "analog_die_reg.h" +#endif /* End defined(_MC9S12I32_H) */ + +#if defined (_MC9S12I128_H) +#include "mm912j637.h" +#endif /* End defined(_MC9S12I128_H) */ + +#if (LIN_MODE == _MASTER_MODE_) +extern const lin_hardware_name lin_virtual_ifc[LIN_NUM_OF_IFCS]; +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#ifdef MULTI_TIMER_MODE +extern const l_u16 time_base_period[LIN_NUM_OF_IFCS]; +#endif /* End MULTI_TIMER_MODE */ + +#if (_MCU_ == _S12X_) +void lin_lld_timer_S12X_init (void) +{ + +#ifdef MULTI_TIMER_MODE + + /* Init PIT timer */ + PITTF = 0x00; + PITCE = 0x00; + PITINTE = 0x00; + /* Configures the PIT (Periodic Interrupt Timer) to generate a periodic interrupt of 500us */ + /* (Interrupt on channel 0) */ + + /*** USING PIT Chanel 0 ***/ +#if (_PIT0_ == 1) + PITTF_PTF0 = 1; + PITCE_PCE0 = 1; + PITINTE_PINTE0 = 1; + /* Baudrate register loading */ + PITLD0 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT0_INDEX])); +#endif /* (_PIT0_ == 1) */ + + /*** USING PIT Chanel 1 ***/ +#if (_PIT1_ == 1) + PITTF_PTF1 = 1; + PITCE_PCE1 = 1; + PITINTE_PINTE1 = 1; + /* Baudrate register loading*/ + PITLD1 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT1_INDEX])); +#endif /* (_PIT1_ == 1) */ + + /*** USING PIT Chanel 2 ***/ +#if (_PIT2_ == 1) + PITTF_PTF2 = 1; + PITCE_PCE2 = 1; + PITINTE_PINTE2 = 1; + /* Baudrate register loading*/ + PITLD2 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT2_INDEX])); +#endif /* (_PIT2_ == 1) */ + + /*** USING PIT Chanel 3 ***/ +#if (_PIT3_ == 1) + PITTF_PTF3 = 1; + PITCE_PCE3 = 1; + PITINTE_PINTE3 = 1; + /* Baudrate register loading */ + PITLD3 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT3_INDEX])); +#endif /* (_PIT3_ == 1) */ + + /*** USING PIT Chanel 4 ***/ +#if (_PIT4_ == 1) + PITTF_PTF4 = 1; + PITCE_PCE4 = 1; + PITINTE_PINTE4 = 1; + /* Baudrate register loading */ + PITLD4 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT4_INDEX])); +#endif /* (_PIT4_ == 1) */ + + /*** USING PIT Chanel 5 ***/ +#if (_PIT5_ == 1) + PITTF_PTF5 = 1; + PITCE_PCE5 = 1; + PITINTE_PINTE5 = 1; + /* Baudrate register loading*/ + PITLD5 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT5_INDEX])); +#endif /* (_PIT5_ == 1) */ + + /*** USING PIT Chanel 2 ***/ +#if (_PIT6_ == 1) + PITTF_PTF6 = 1; + PITCE_PCE6 = 1; + PITINTE_PINTE6 = 1; + /* Baudrate register loading*/ + PITLD6 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT6_INDEX])); +#endif /* (_PIT6_ == 1) */ + + /*** USING PIT Chanel 7 ***/ +#if (_PIT7_ == 1) + PITTF_PTF7 = 1; + PITCE_PCE7 = 1; + PITINTE_PINTE7 = 1; + /* Baudrate register loading */ + PITLD7 = (l_u16)((MCU_BUS_FREQ/1000000)*(time_base_period[PIT7_INDEX])); +#endif /* (_PIT7_ == 1) */ + + PITMTLD0=0x00; + /* Enable PIT Module */ + PITCFLMT = 0xA0; + +#else /* Else MULTI_TIMER_MODE */ + /* Init PIT0 timer for single timer mode */ + PITTF = 0x00; + PITCE = 0x00; + PITINTE = 0x00; + /* Configures the PIT (Periodic Interrupt Timer) to generate a periodic interrupt of 500us */ + /* (Interrupt on channel 0) */ + + /*** USING PIT Chanel 0 ***/ + PITTF_PTF0 = 1; + PITCE_PCE0 = 1; + PITINTE_PINTE0 = 1; + /* TIME_BASE_PERIOD micro seconds with Fbus = MCU_BUS_FREQ Mhz*/ + PITLD0 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + PITMTLD0=0x00; + + /* Enable PIT Module */ + PITCFLMT = 0xA0; +#endif /* End MULTI_TIMER_MODE */ +} + + +#endif /* End (_MCU_ == _S12X_) */ + +/* ----------------------------------------------------------------- */ + +#if (_MCU_ == _S12_) +void lin_lld_timer_S12_init (void) +{ +#if defined(_MC9S12I32_H) + l_u16 temp; + /* Init timer for MM912F634 apply for 9S12I32 MCU */ + /* Initialize TIM timer */ + /* Timer functions normally */ + TSCR1 = 0x00; + /* Output Compare Select Timer 3 */ + TIOS = 8; + /* Define an output associated OC3 */ + TCTL1 = 192; + /* Enable toggle output compare pin */ + TTOV = 8; + /* Enable Hardware interrupt request */ + TSCR2 = 0x88; + /* Enable tim3 */ + TIE = 8; + /* Set timer period */ + temp = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + TC3hi = (l_u8)(temp>>8); + TC3lo = (l_u8)temp; + TSCR1 = 128; + /* End define for I32 */ + +#elif defined(_MC9S12GN32_H) || defined(_MC9S12G64_H) + /* Timer functions normally */ + TSCR1 = 8; + /* Set up timer channel 0 */ + /* Timer output compare */ + TIOS = TIOS_IOS0_MASK; + /* Enable toggle output compare pin */ + TTOV = TTOV_TOV0_MASK; + /* Enable Hardware interrupt request */ + TSCR2 = 0x00; + /* Enable timer channel 0 interrupt */ + TIE = TIE_C0I_MASK; + /* Set timer period */ + TC0 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /* Enable timer */ + TSCR1 = TSCR1_TEN_MASK ; + /* End define for GN32, G64 */ + +#elif (defined(_MC9S12VR64_H) || defined(_MC9S12VR32_H)) + /* Timer functions normally */ + TSCR1 = 8; + /* Set up timer channel 3 */ + CFORC |= CFORC_FOC0_MASK; + /* Timer output compare */ + TIOS |= TIOS_IOS0_MASK; + /* Enable toggle output compare pin */ + TTOV |= TTOV_TOV0_MASK; + /* Disable Hardware interrupt request and Timer prescaler = 1 */ + TSCR2 = 0x00; + /* Enable timer channel 3 interrupt */ + TIE |= TIE_C0I_MASK; + /* Set timer period */ + TC0 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /* Enable timer */ + TSCR1 = TSCR1_TEN_MASK; + /* End (defined(_MC9S12VR64_H) || defined(_MC9S12VR32_H))*/ + +#elif defined(_MM912J637_H) + /* Disable Timer */ + TSCR1 = 0x00; + /* Timer output compare */ + TIOS = 0x08; + /* Timer disconnect from output pin */ + TCTL1 = 0x00; + /* Disable input capture */ + TCTL2 = 0x00; + /* disable toggle output compare pin */ + TTOV = 0x00; + /* Enable timer counter reset by successfull OC on channel */ + TSCR2 = 0x08; + /* Enable timer channel 3 interrupt */ + TIE = 0x08; + /* Set timer period */ + TC3 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /* Enable timer */ + TSCR1 = 0x80; + /* End define for 9S12I128 */ +#elif defined(_MM9Z1J638_H) + /* Disable Timer */ + B_TSCR1 = 0x00; + /* Timer output compare */ + B_TIOS = 0x08; + /* Timer disconnect from output pin */ + B_TCTL1 = 0x00; + /* Disable input capture */ + B_TCTL2 = 0x00; + /* disable toggle output compare pin */ + B_TTOV = 0x00; + /* Enable timer counter reset by successfull OC on channel */ + B_TSCR2 = 0x08; + /* Enable timer channel 3 interrupt */ + B_TIE = 0x08; + /* Set timer period */ + B_TC3 = MCU_BUS_FREQ/(1000000/TIME_BASE_PERIOD); + /* Enable timer */ + B_TSCR1 = 0x80; +#else + +#if defined(_MC9S12XHY256_H) || defined(_MC9S12HY64_H) +#define TSCR1 TIM0_TSCR1 +#define OCPD TIM0_OCPD +#define PACTL TIM0_PACTL +#define OC7M TIM0_OC7M +#define TIOS TIM0_TIOS +#define TCTL1 TIM0_TCTL1 +#define TTOV TIM0_TTOV +#define TSCR2 TIM0_TSCR2 +#define TFLG1 TIM0_TFLG1 +#define TIE TIM0_TIE +#define TC7 TIM0_TC7 +#endif /* End for 9S12XHY256 and 9S12HY64 */ + +#if (defined(_MC9S12ZVML128_H) || defined(_MC9S12ZVL32_H)||defined(_MC9S12ZVHY64_H)||defined(_MC9S12ZVH128_H)\ + ||defined(_MC9S12ZVML31_H)||defined(_MC9S12ZVMC256_H)||defined(_MC9S12ZVL128_H)||defined(_MC9S12ZVMB_H)) + /*Configure the timer*/ + /*Timer prescaler = 1 */ + TIM0TSCR2 = 0x00; + /*Enable Channel 2 as Output Compare */ + TIM0TIOS_IOS2 = 1; + /*Enable Channel 2 interrupt */ + TIM0TIE_C2I = 1; + TIM0TC2 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /*Disable the timer when the MCU is in freeze mode */ + TIM0TSCR1_TSFRZ = 1; + /*Enable the Timer */ + TIM0TSCR1_TEN = 1; +#else +#if (defined(_MC9S12ZVMA_H)|| defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H)) + /*Configure the timer*/ + /*Timer prescaler = 1 */ + TIM1TSCR2 = 0x00; + /*Enable Channel 0 as Output Compare */ + TIM1TIOS_IOS0 = 1; + /*Enable Channel 0 interrupt */ + TIM1TIE_C0I = 1; + TIM1TC0 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /*Disable the timer when the MCU is in freeze mode */ + TIM1TSCR1_TSFRZ = 1; + /*Enable the Timer */ + TIM1TSCR1_TEN = 1; +#else +#if defined(_MC9S12ZVC64_H) + /*Configure the timer*/ + /*Timer prescaler = 32 (6.25MHZ/32 ~ 5.12[us]) */ + TIM1TSCR2 = 0x08; + /*Enable Channel 2 as Output Compare */ + TIM1TIOS_IOS2 = 1; + /*Enable Channel 2 interrupt */ + TIM1TIE_C2I = 1; + TIM1TC2 = (MCU_BUS_FREQ/500000)*TIME_BASE_PERIOD; + /*Disable the timer when the MCU is in freeze mode */ + TIM1TSCR1_TSFRZ = 1; + /*Enable the Timer */ + TIM1TSCR1_TEN = 1; +#else + /* Initialize TIM timer */ + /* Timer functions normally */ + TSCR1 = 8; + /* Disable timer */ + OCPD = 128; + /* Clock select bits: Div. by 64 clock enabled with pin low level */ + PACTL = 12; + /* Timer output compare */ + OC7M = 128; + /* Output Compare Select Timer 7 */ + TIOS = 128; + /* Define an output associated OC7 */ + TCTL1 = 192; + /* Enable toggle output compare pin */ + TTOV = 128; + /* Enable Hardware interrupt request */ + TSCR2 = 136; + /* Enable Output Compare */ + TFLG1 = 255; + /* Enable tim7 */ + TIE = 128; + /* Set timer period */ + TC7 = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + /* Enable timer */ + TSCR1 = 128; +#endif /* End defined(_MC9S12ZVC64_H) */ +#endif /* End (defined(_MC9S12ZVMA_H)|| defined(_MC9S12VRP64_H) || defined(_MC9S12VRP48_H)) */ +#endif /* End (defined(_MC9S12ZVML128_H) || defined(_MC9S12ZVL32_H) || defined(_MC9S12ZVML31_H)) */ +#endif /* End defined(_MC9S12I32_H) */ + +} + +#endif /* End (_MCU_ == _S12_) */ + +/* ----------------------------------------------------------------- */ + +#if (_MCU_ == _S08_) +void lin_lld_timer_S08_init (void) +{ +#if defined(_MC9S08RN60_H) + /* Stop timer */ + MTIM0_SC = 0x10; + /* Initialize appropriate value to the compare/modulo/reload register */ + MTIM0_MOD = 0xFE; + /* Set pre-scaler */ + MTIM0_CLK = 0x05; + /* Reset HW Counter and run timer */ + MTIM0_SC = 0x60; +#else + /* Configures the TPM to generate a periodic interrupt of 500us */ + /* (Interrupt on channel 0) */ + /* clear prescaler and disable the timer */ + TPM1SC = 0x00; + + /* clear interrupt flag and disable interrupt channel; + channel performs output compare with not using pin */ + TPM1C0SC = 0x50; + + /* set maximum modulo value */ + TPM1C0V = TPM1MOD = (MCU_BUS_FREQ/1000000)*TIME_BASE_PERIOD; + TPM1CNTH = 0x00; + /* enable timer and select the TPM clock source*/ + TPM1SC = 0x08; +#endif /*End defined(_MC9S08RN60_H)*/ +} +#endif /* End (_MCU_ == _S08_) */ + +#ifdef MULTI_TIMER_MODE +void lin_lld_timer_isr(l_u8 index) +{ + /* Timeout for SCI channel */ + lin_lld_sci_timeout(lin_virtual_ifc[index]); + /*** Master task firing ***/ +} +#else /* Else MULTI_TIMER_MODE */ +void lin_lld_timer_isr(void) +{ +#if LIN_MODE == _MASTER_MODE_ + l_u8 i; + /* Timeout for SCI channel */ + for(i=0; i#l_u8 i +* +* @see #lin_lld_sci_timeout +* +* @details +* Timer interrupt service routine +*//*END*----------------------------------------------------------------------*/ +#ifdef MULTI_TIMER_MODE +void lin_lld_timer_isr(l_u8 index); +#else +void lin_lld_timer_isr(void); +#endif /* End MULTI_TIMER_MODE */ + +#endif /* __LIN_LLD_TIMESRV */ + +/** +* @} +*/ diff --git a/LIN_Stack/bsp/SCI/lin_reg.h b/LIN_Stack/bsp/SCI/lin_reg.h new file mode 100644 index 0000000..af34da5 --- /dev/null +++ b/LIN_Stack/bsp/SCI/lin_reg.h @@ -0,0 +1,991 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup SCI_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file bsp/SCI/lin_reg.h +* +* @author FPT Software +* +* @brief SCI register definition on S08, S12, S12X +* +******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * 20101027 v1.0 First version + * + *****************************************************************************/ + +#ifndef LIN_REG_H +#define LIN_REG_H + +#include "lin_hw_cfg.h" + +/*************************************/ +/****** Common Register struct *****/ +/*************************************/ + +/** +* @var typedef unsigned char tU08 +* unsigned 8 bits definition +*/ +typedef unsigned char tU08; /**< unsigned 8 bit definition */ + +/** +* @var typedef unsigned char tU16 +* unsigned 16 bits definition +*/ +typedef unsigned short tU16; /**< unsigned 16 bit definition */ + +/** +* @var typedef unsigned long tU32 +* unsigned 32 bits definition +*/ +typedef unsigned long tU32; /**< unsigned 32 bit definition */ + +/** +* @var typedef unsigned char tS08 +* signed 32 bits definition +*/ +typedef signed char tS08; /**< signed 8 bit definition */ + +/** +* @var typedef signed int tS16 +* signed 16 bits definition +*/ +typedef signed short tS16; /**< signed 16 bit definition */ + +/** +* @var typedef signed long tS32 +* signed 32 bits definition +*/ +typedef signed long tS32; /**< signed 32 bit definition */ + +#if (!defined(_MC9S12ZVML128_H) && !defined(_MC9S12ZVML31_H)) +#pragma MESSAGE DISABLE C1106 /**< WARNING C1106: Non-standard bitfield type */ +#endif /* End if (!defined(_MC9S12ZVML128_H) && !defined(_MC9S12ZVML31_H)) */ + +/** +* @var uREG08 tREG08 +* register 8 bits +*/ + +/** +* @union uREG08 +* register 8 bits +*/ +typedef union uREG08 /**< 8 bit register with byte and bit access*/ +{ + tU08 byte; /**< access whole register e.g. var.byte = 0xFF;*/ + struct + { + tU08 _0 :1; /**< bit 0 */ + tU08 _1 :1; /**< bit 1 */ + tU08 _2 :1; /**< bit 2 */ + tU08 _3 :1; /**< bit 3 */ + tU08 _4 :1; /**< bit 4 */ + tU08 _5 :1; /**< bit 5 */ + tU08 _6 :1; /**< bit 6 */ + tU08 _7 :1; /**< bit 7 */ + } bit; /**< access bit at a time e.g. var.bit._7 = 1; */ +} tREG08; + + +/** +* @var uREG16 tREG16 +* register 16 bits +*/ + +/** +* @union uREG16 +* register 16 bits +*/ +typedef union uREG16 /**< 16 bit register with word and byte access*/ +{ + tU16 word; /**< access whole word */ + struct + { + tREG08 msb; /**< msb byte */ + tREG08 lsb; /**< lsb byte */ + } byte; /**< access byte at a time */ +} tREG16; + +/*************************************/ +/******* SCI Register struct *******/ +/*************************************/ + +#if (SCI_VERSION == SCI_V2) +/** +* @var uSCIBDH tSCIBDH +* SCI baurate high register +*/ +/** +* @union uSCIBDH +* SCI baurate high register +*/ +typedef union uSCIBDH +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr8 :1; /**< msb baud rate select bits: bit 8 */ + tU08 sbr9 :1; /**< msb baud rate select bits: bit 9 */ + tU08 sbr10 :1; /**< msb baud rate select bits: bit 10 */ + tU08 sbr11 :1; /**< msb baud rate select bits: bit 11 */ + tU08 sbr12 :1; /**< msb baud rate select bits: bit 12 */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + } bit; /**< access register as bits */ +} tSCIBDH; +#endif /* End (SCI_VERSION == SCI_V2) */ + +#if (SCI_VERSION == SCI_V4) +/** +* @union tSCIBDH +* SCI baud rate higher byte +*/ +typedef union uSCIBDH +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr8 :1; /**< msb baud rate select bits: bit 8 */ + tU08 sbr9 :1; /**< msb baud rate select bits: bit 9 */ + tU08 sbr10 :1; /**< msb baud rate select bits: bit 10 */ + tU08 sbr11 :1; /**< msb baud rate select bits: bit 11 */ + tU08 sbr12 :1; /**< msb baud rate select bits: bit 12 */ + tU08 :1; /**< bit reserved area */ + tU08 rxegie :1; /**< RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ + tU08 lbkdie :1; /**< LIN Break Detect Interrupt Enable (for LBKDIF) */ + } bit; /**< access register as bits */ +} tSCIBDH; +#endif /* End (SCI_VERSION == SCI_V4) */ + +#if (SCI_VERSION == SCI_V5) +/** +* @var uSCIBDH tSCIBDH +*/ +/** +* @union uSCIBDH +* SCI Baud Rate Register +*/ +typedef union uSCIBDH +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr8 :1; /**< msb baud rate select bits: bit 8 */ + tU08 sbr9 :1; /**< msb baud rate select bits: bit 9 */ + tU08 sbr10 :1; /**< msb baud rate select bits: bit 10 */ + tU08 sbr11 :1; /**< msb baud rate select bits: bit 11 */ + tU08 sbr12 :1; /**< msb baud rate select bits: bit 12 */ + tU08 tnp :2; /**< transmit narrow pulse */ + tU08 iren :1; /**< IRDA enable */ + } bit; /**< access register as bits */ + struct /**< alternate bits for SCIASR1 */ + { + tU08 bkdif :1; /**< break detect interrupt flag */ + tU08 berrif :1; /**< bit error interrupt flag */ + tU08 berrv :1; /**< bit error value */ + tU08 :4; /**< bit reserved area */ + tU08 rxedgif:1; /**< receive input active edge interrupt flag */ + } abit; /**< alternate bits for SCIBDH */ +} tSCIBDH; +#endif /* End (SCI_VERSION == SCI_V5) */ + +#if (SCI_VERSION == SCI_V6) +/** +* @var uSCIBDH tSCIBDH +*/ +/** +* @union uSCIBDH +* SCI Baud Rate Register +*/ +typedef union uSCIBDH +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr8 :1; /**< msb baud rate select bits: bit 8 */ + tU08 sbr9 :1; /**< msb baud rate select bits: bit 9 */ + tU08 sbr10 :1; /**< msb baud rate select bits: bit 10 */ + tU08 sbr11 :1; /**< msb baud rate select bits: bit 11 */ + tU08 sbr12 :1; /**< msb baud rate select bits: bit 12 */ + tU08 sbr13 :1; /**< msb baud rate select bits: bit 13 */ + tU08 sbr14 :1; /**< msb baud rate select bits: bit 14 */ + tU08 sbr15 :1; /**< msb baud rate select bits: bit 15 */ + } bit; /**< access register as bits */ + struct /**< alternate bits for SCIASR1 */ + { + tU08 bkdif :1; /**< break detect interrupt flag */ + tU08 berrif :1; /**< bit error interrupt flag */ + tU08 berrv :1; /**< bit error value */ + tU08 :4; /**< bit reserved area */ + tU08 rxedgif:1; /**< receive input active edge interrupt flag */ + } abit; /**< alternate bits for SCIBDH */ +} tSCIBDH; +#endif /* End (SCI_VERSION == SCI_V6) */ + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) +/** +* @union tSCIBDL +* SCI baud rate lower byte +*/ +typedef union uSCIBDL +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr0 :1; /**< lsb baud rate select bits: bit 0 */ + tU08 sbr1 :1; /**< lsb baud rate select bits: bit 1 */ + tU08 sbr2 :1; /**< lsb baud rate select bits: bit 2 */ + tU08 sbr3 :1; /**< lsb baud rate select bits: bit 3 */ + tU08 sbr4 :1; /**< lsb baud rate select bits: bit 4 */ + tU08 sbr5 :1; /**< lsb baud rate select bits: bit 5 */ + tU08 sbr6 :1; /**< lsb baud rate select bits: bit 6 */ + tU08 sbr7 :1; /**< lsb baud rate select bits: bit 7 */ + } bit; /**< access register as bits */ +} tSCIBDL; + +#else +typedef union uSCIBDL +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbr0 :1; /**< lsb baud rate select bits: bit 0 */ + tU08 sbr1 :1; /**< lsb baud rate select bits: bit 1 */ + tU08 sbr2 :1; /**< lsb baud rate select bits: bit 2 */ + tU08 sbr3 :1; /**< lsb baud rate select bits: bit 3 */ + tU08 sbr4 :1; /**< lsb baud rate select bits: bit 4 */ + tU08 sbr5 :1; /**< lsb baud rate select bits: bit 5 */ + tU08 sbr6 :1; /**< lsb baud rate select bits: bit 6 */ + tU08 sbr7 :1; /**< lsb baud rate select bits: bit 7 */ + } bit; /**< access register as bits */ + struct + { + tU08 bkdie :1; /**< break detect interrupt enable */ + tU08 berrie :1; /**< bit error interrupt enable */ + tU08 :5; /**< bit reserved area */ + tU08 rxedgie:1; /**< receive input active edge interrupt enable */ + } abit; /**< alternate bits for SCIBDL */ +} tSCIBDL; +#endif /* End (SCI_VERSION != SCI_V5 && SCI_VERSION != SCI_V6) */ + +#if (SCI_VERSION == SCI_V6) +/** +* @var uSCICR1 tSCICR1 +*/ +/** +* @union uSCICR1 +* SCI Control Register 1 +*/ +typedef union uSCICR1 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 pt :1; /**< parity type */ + tU08 pe :1; /**< parity enable */ + tU08 ilt :1; /**< idle line type */ + tU08 wake :1; /**< wake up by address mark/idle */ + tU08 m :1; /**< mode select */ + tU08 rsrc :1; /**< receiver source */ + tU08 sciswai :1; /**< stop in wait mode */ + tU08 loops :1; /**< loop mode/single wire mode enable */ + } bit; /**< access register as bits */ + struct + { + tU08 bkdfe :1; /**< break detect feature enable */ + tU08 berrm0 :1; /**< bit error mode */ + tU08 berrm1 :1; /**< bit error mode */ + tU08 :2; /**< bit reserved area */ + tU08 tnp :2; /**< transmit narrow pulse */ + tU08 iren :1; /**< IRDA enable */ + } abit; /**< alternate bits for SCIACR1 */ +} tSCICR1; +#elif (SCI_VERSION == SCI_V5) +/** +* @var uSCICR1 tSCICR1 +*/ +/** +* @union uSCICR1 +* SCI Control Register 1 +*/ +typedef union uSCICR1 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 pt :1; /**< parity type */ + tU08 pe :1; /**< parity enable */ + tU08 ilt :1; /**< idle line type */ + tU08 wake :1; /**< wake up by address mark/idle */ + tU08 m :1; /**< mode select */ + tU08 rsrc :1; /**< receiver source */ + tU08 sciswai :1; /**< stop in wait mode */ + tU08 loops :1; /**< loop mode/single wire mode enable */ + } bit; /**< access register as bits */ + struct + { + tU08 bkdfe :1; /**< break detect feature enable */ + tU08 berrm0 :1; /**< bit error mode */ + tU08 berrm1 :1; /**< bit error mode */ + tU08 :5; /**< bit reserved area */ + } abit; /**< alternate bits for SCIACR1 */ +} tSCICR1; +#else /* SCI V2 and V4 */ +/** +* @union tSCICR1 +* SCI control register 1 +*/ +typedef union uSCICR1 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 pt :1; /**< parity type */ + tU08 pe :1; /**< parity enable */ + tU08 ilt :1; /**< idle line type */ + tU08 wake :1; /**< wake up by address mark/idle */ + tU08 m :1; /**< mode select */ + tU08 rsrc :1; /**< receiver source */ + tU08 sciswai :1; /**< stop in wait mode */ + tU08 loops :1; /**< loop mode/single wire mode enable */ + } bit; /**< access register as bits */ +} tSCICR1; +#endif /* End (SCI_VERSION == SCI_V6) */ + +/** +* @var uSCICR2 tSCICR2 +*/ +/** +* @union uSCICR2 +* * SCI Control Register 2 +*/ +typedef union uSCICR2 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 sbk :1; /**< send break character */ + tU08 rwu :1; /**< receiver wake-up control */ + tU08 re :1; /**< receiver enable */ + tU08 te :1; /**< transmitter enable */ + tU08 ilie :1; /**< idle line interrupt enable */ + tU08 rie :1; /**< receiver interrupt enable */ + tU08 tcie :1; /**< transmit complete interrupt enable */ + tU08 tie :1; /**< transmit interrupt enable */ + } bit; /**< access register as bits */ +} tSCICR2; + +/** +* @var uSCISR1 tSCISR1 +*/ +/** +* @union uSCISR1 +* SCI Status Register 1 +*/ +typedef union uSCISR1 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 pf :1; /**< parity error flag */ + tU08 fe :1; /**< framing error flag */ + tU08 nf :1; /**< noise error flag */ + tU08 orf :1; /**< overrun error flag - 'or' in specification */ + tU08 idle :1; /**< idle line detected flag */ + tU08 rdrf :1; /**< receive data register full flag */ + tU08 tc :1; /**< transmit complete flag */ + tU08 tdre :1; /**< transmit data register empty flag */ + } bit; /**< access register as bits */ +} tSCISR1; + +#if (SCI_VERSION == SCI_V2) +/** +* @var uSCISR2 tSCISR2 +* SCI status register 2 +*/ +/** +* @union uSCISR2 +* SCI status register 2 +*/ +typedef union uSCISR2 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 raf :1; /**< receiver active flag */ + tU08 :1; /**< bit reserved area */ + tU08 brk13 :1; /**< break character length */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + tU08 :1; /**< bit reserved area */ + } bit; /**< access register as bits */ +} tSCISR2; +#endif /* End (SCI_VERSION == SCI_V2) */ + +#if (SCI_VERSION == SCI_V4) +/** +* @var uSCISR2 tSCISR2 +* SCI status register 2 +*/ +/** +* @union uSCISR2 +* SCI status register 2 +*/ +typedef union uSCISR2 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 raf :1; /**< receiver active flag */ + tU08 lbkde :1; /**< LIN Break Detection Enable */ + tU08 brk13 :1; /**< Break Character Generation Length */ + tU08 rwuid :1; /**< Receive Wake Up Idle Detect */ + tU08 rxinv :1; /**< Receive Data Inversion */ + tU08 :1; /**< bit reserved area */ + tU08 rxedgif:1; /**< RxD Pin Active Edge Interrupt Flag */ + tU08 lbkdif :1; /**< LIN Break Detect Interrupt Flag */ + } bit; /**< access register as bits */ +} tSCISR2; +#endif /* End (SCI_VERSION == SCI_V4) */ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +/** +* @var uSCISR2 tSCISR2 +*/ +/** +* @union uSCISR2 +* SCI status register 2 +*/ +typedef union uSCISR2 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 raf :1; /**< receiver active flag */ + tU08 txdir :1; /**< receiver active flag */ + tU08 brk13 :1; /**< 13-bit break */ + tU08 rxpol :1; /**< receiver polarity */ + tU08 txpol :1; /**< transmitter polarity */ + tU08 :2; /**< bit reserved area */ + tU08 amap :1; /**< alternate register map */ + } bit; /**< access register as bits */ +} tSCISR2; +#endif /* End (SCI_VERSION == SCI_V5 || SCI_VERSION == SCI_V6) */ + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) +/** +* @var uSCICR3 tSCICR3 +*/ +/** +* @union uSCICR3 +* SCI control register 3 +*/ +typedef union uSCICR3 +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 peie :1; /**< Parity Error Interrupt Enable */ + tU08 feie :1; /**< Framing Error Interrupt Enable */ + tU08 neie :1; /**< Noise Error Interrupt Enable */ + tU08 orie :1; /**< Overrun Interrupt Enable */ + tU08 txinv :1; /**< Transmit Data Inversion */ + tU08 txdir :1; /**< TxD Pin Direction in Single-Wire Mode */ + tU08 t8 :1; /**< Ninth Data Bit for Transmitter */ + tU08 r8 :1; /**< Ninth Data Bit for Receiver */ + } bit; /**< access register as bits */ +} tSCICR3; + +/** +* @var uSCID tSCID +*/ +/** +* @union uSCID +* SCI data +*/ +typedef union uSCID +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 r0_t0 :1; /**< Receive/Transmit Data Bit 0 */ + tU08 r1_t1 :1; /**< Receive/Transmit Data Bit 1 */ + tU08 r2_t2 :1; /**< Receive/Transmit Data Bit 2 */ + tU08 r3_t3 :1; /**< Receive/Transmit Data Bit 3 */ + tU08 r4_t4 :1; /**< Receive/Transmit Data Bit 4 */ + tU08 r5_t5 :1; /**< Receive/Transmit Data Bit 5 */ + tU08 r6_t6 :1; /**< Receive/Transmit Data Bit 6 */ + tU08 r7_t7 :1; /**< Receive/Transmit Data Bit 7 */ + } bit; /**< access register as bits */ +} tSCID; +#else +/** +* @var uSCIDRH tSCIDRH +*/ +/** +* @union uSCIDRH +* SCI Data Register hight +*/ +typedef union uSCIDRH +{ + tU08 byte; /**< access register as byte */ + struct + { + tU08 :6; /**< not used */ + tU08 t8 :1; /**< transmit bit 8 */ + tU08 r8 :1; /**< receive bit 8 */ + } bit; /**< access register as bits */ +} tSCIDRH; +#endif /* End (SCI_VERSION != SCI_V5) */ + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) +/** +* @struct tSCI +* SCI data structure +*/ +typedef struct /**< sci datastructure */ +{ + volatile tSCIBDH scibdh; /**< sci baud rate high register */ + volatile tSCIBDL scibdl; /**< sci baud rate low register */ + volatile tSCICR1 scicr1; /**< sci control register 1 */ + volatile tSCICR2 scicr2; /**< sci control register 2 */ + volatile tSCISR1 scisr1; /**< sci status register 1 */ + volatile tSCISR2 scisr2; /**< sci status register 2 */ + volatile tSCICR3 scicr3; /**< sci control register 3 */ + volatile tSCID scid; /**< sci data register */ +} tSCI; +#else /* SCI v5 and v6 */ +/** +* @struct tSCI +* sci datastructure +*/ +typedef struct /**< sci datastructure */ +{ + volatile tSCIBDH scibdh; /**< sci baud rate high register / alternate status register */ + volatile tSCIBDL scibdl; /**< sci baud rate low register / alternate control register 1 */ + volatile tSCICR1 scicr1; /**< sci control register 1 / alternate control register 2 */ + volatile tSCICR2 scicr2; /**< sci control register 2 */ + volatile tSCISR1 scisr1; /**< sci status register 1 */ + volatile tSCISR2 scisr2; /**< sci status register 2 */ + volatile tSCIDRH scidrh; /**< sci data register high */ + volatile tREG08 scidrl; /**< sci data register low */ +} tSCI; + + +#define sciasr1 scibdh /**< SCI alternate status register */ +#define sciacr1 scibdl /**< SCI alternate control register 1 */ +#define sciacr2 scicr1 /**< SCI alternate control register 2 */ +#endif /* End (SCI_VERSION != SCI_V5) */ + +/*************************************/ +/************ SCI Bit masks **********/ +/*************************************/ + +/* SCIBH - SCI Baud Rate Register High */ +#if (defined(_MC9S08DZ128_H)|| defined(_MM9Z1J638_H)||(SCI_VERSION == SCI_V4)) +#ifndef SCIBDH_RXEDGIE_MASK +#define SCIBDH_RXEDGIE_MASK 64 /**< SCI baud rate register high bit mask: RxD input active edge interrupt enable */ +#endif /* ifndef SCIBDH_RXEDGIE_MASK */ + +#ifndef SCIBDH_LBKDIE_MASK +#define SCIBDH_LBKDIE_MASK 128 /**< SCI baud rate register high bit mask: LIN break detected interrupt enable */ +#endif /* ifndef SCIBDH_LBKDIE_MASK */ +#endif /* End (SCI_VERSION == SCI_V4) */ + + +/* SCIASR1 - SCI Alternative Status Register */ +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +#ifndef SCIASR1_BKDIF_MASK +#define SCIASR1_BKDIF_MASK 1 /**< SCI alternate status register 1 bit mask: break detect interrupt flag */ +#endif /* ifndef SCIASR1_BKDIF_MASK */ + +#ifndef SCIASR1_BERRIF_MASK +#define SCIASR1_BERRIF_MASK 2 /**< SCI alternate status register 1 bit mask: bit error interrupt flag */ +#endif /* ifndef SCIASR1_BERRIF_MASK */ + +#ifndef SCIASR1_BERRV_MASK +#define SCIASR1_BERRV_MASK 4 /**< SCI alternate status register 1 bit mask: bit error value */ +#endif /* ifndef SCIASR1_BERRV_MASK */ + +#ifndef SCIASR1_RXEDGIF_MASK +#define SCIASR1_RXEDGIF_MASK 128 /**< SCI alternate status register 1 bit mask: receive input active interrupt flag */ +#endif /* ifndef SCIASR1_RXEDGIF_MASK */ + +/* SCI0ACR1 - SCI Alternative Control Register 1 */ +#ifndef SCIACR1_BKDIE_MASK +#define SCIACR1_BKDIE_MASK 1 /**< SCI alternate control register 1 bit mask: break detect interrupt enable */ +#endif /* ifndef SCIACR1_BKDIE_MASK */ + +#ifndef SCIACR1_BERRIE_MASK +#define SCIACR1_BERRIE_MASK 2 /**< SCI alternate control register 1 bit mask: bit error interrupt enable */ +#endif /* ifndef SCIACR1_BERRIE_MASK */ + +#ifndef SCIACR1_RXEDGIE_MASK +#define SCIACR1_RXEDGIE_MASK 128 /**< SCI alternate control register 1 bit mask: receive input active edge interrupt enable */ +#endif /* ifndef SCIACR1_RXEDGIE_MASK */ +#endif /* End (SCI_VERSION == SCI_V5) */ + +/* SCICR1 - SCI Control Register 1 */ +#if (SCI_VERSION == SCI_V2) +#ifndef SCICR1_PT_MASK +#define SCICR1_PT_MASK 1 /**< SCI control register 1 bit mask: parity type*/ +#endif /* ifndef SCICR1_PT_MASK */ + +#ifndef SCICR1_PE_MASK +#define SCICR1_PE_MASK 2 /**< SCI control register 1 bit mask: parity enable*/ +#endif /* ifndef SCICR1_PE_MASK */ + +#ifndef SCICR1_ILT_MASK +#define SCICR1_ILT_MASK 4 /**< SCI control register 1 bit mask: idle line type select*/ +#endif /* ifndef SCICR1_ILT_MASK */ + +#ifndef SCICR1_WAKE_MASK +#define SCICR1_WAKE_MASK 8 /**< SCI control register 1 bit mask: receiver wakeup method select*/ +#endif /* ifndef SCICR1_WAKE_MASK */ + +#ifndef SCICR1_M_MASK +#define SCICR1_M_MASK 16 /**< SCI control register 1 bit mask: 8 bit or 9 bit mode select*/ +#endif /* ifndef SCICR1_M_MASK */ + +#ifndef SCICR1_RSTC_MASK +#define SCICR1_RSTC_MASK 32 /**< SCI control register 1 bit mask: receiver source select*/ +#endif /* ifndef SCICR1_RSTC_MASK */ + +#ifndef SCICR1_SCIWAI_MASK +#define SCICR1_SCIWAI_MASK 64 /**< SCI control register 1 bit mask: SCI stops in wait mode*/ +#endif /* ifndef SCICR1_SCIWAI_MASK */ + +#ifndef SCICR1_LOOPS_MASK +#define SCICR1_LOOPS_MASK 128 /**< SCI control register 1 bit mask: loop mode select*/ +#endif /* ifndef SCICR1_LOOPS_MASK */ + +#else +#ifndef SCICR1_PT_MASK +#define SCICR1_PT_MASK 1 /**< SCI control register 1 bit mask: parity type*/ +#endif /* ifndef SCICR1_PT_MASK */ + +#ifndef SCICR1_PE_MASK +#define SCICR1_PE_MASK 2 /**< SCI control register 1 bit mask: parity enable*/ +#endif /* ifndef SCICR1_PE_MASK */ + +#ifndef SCICR1_ILT_MASK +#define SCICR1_ILT_MASK 4 /**< SCI control register 1 bit mask: idle line type select*/ +#endif /* ifndef SCICR1_ILT_MASK */ + +#ifndef SCICR1_WAKE_MASK +#define SCICR1_WAKE_MASK 8 /**< SCI control register 1 bit mask: receiver wakeup method select*/ +#endif /* ifndef SCICR1_WAKE_MASK */ + +#ifndef SCICR1_M_MASK +#define SCICR1_M_MASK 16 /**< SCI control register 1 bit mask: 8 bit or 9 bit mode select*/ +#endif /* ifndef SCICR1_M_MASK */ + +#ifndef SCICR1_RSRC_MASK +#define SCICR1_RSRC_MASK 32 /**< SCI control register 1 bit mask: receiver source select*/ +#endif /* ifndef SCICR1_RSRC_MASK */ + +#ifndef SCICR1_SCISWAI_MASK +#define SCICR1_SCISWAI_MASK 64 /**< SCI control register 1 bit mask: SCI stops in wait mode*/ +#endif /* ifndef SCICR1_SCISWAI_MASK */ + +#ifndef SCICR1_LOOPS_MASK +#define SCICR1_LOOPS_MASK 128 /**< SCI control register 1 bit mask: loop mode select*/ +#endif /* ifndef SCICR1_LOOPS_MASK */ +#endif /* End (SCI_VERSION == SCI_V2) */ + + +/* SCIACR2 - SCI Alternative Control Register 2 */ +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +#ifndef SCIACR2_BKDFE_MASK +#define SCIACR2_BKDFE_MASK 1 /**< SCI alternate control register 2: break detect feature enable */ +#endif /* ifndef SCIACR2_BKDFE_MASK */ + +#ifndef SCIACR2_BERRM0_MASK +#define SCIACR2_BERRM0_MASK 2 /**< SCI alternate control register 2: bit error mode 0 */ +#endif /* ifndef SCIACR2_BERRM0_MASK */ + +#ifndef SCIACR2_BERRM1_MASK +#define SCIACR2_BERRM1_MASK 4 /**< SCI alternate control register 2: bit error mode 1 */ +#endif /* ifndef SCIACR2_BERRM1_MASK */ + +#ifndef SCIACR2_BERRM_MASK +#define SCIACR2_BERRM_MASK 6 /**< SCI alternate control register 2: bit error mode bit 0 and 1 is set */ +#endif /* ifndef SCIACR2_BERRM_MASK */ + +#ifndef SCIACR2_BERRM_BITNUM +#define SCIACR2_BERRM_BITNUM 1 /**< SCI alternate control register 2: bit num */ +#endif /* ifndef SCIACR2_BERRM_BITNUM */ +#endif /* End (SCI_VERSION == SCI_V5) */ + +/* SCICR2 - SCI Control Register 2 */ +#ifndef SCICR2_SBK_MASK +#define SCICR2_SBK_MASK 1 /**< SCI control register 2 bit mask: send break */ +#endif /* ifndef SCICR2_SBK_MASK */ + +#ifndef SCICR2_RWU_MASK +#define SCICR2_RWU_MASK 2 /**< SCI control register 2 bit mask: receiver wakeup control */ +#endif /* ifndef SCICR2_RWU_MASK */ + +#ifndef SCICR2_RE_MASK +#define SCICR2_RE_MASK 4 /**< SCI control register 2 bit mask: receiver enable */ +#endif /* ifndef SCICR2_RE_MASK */ + +#ifndef SCICR2_TE_MASK +#define SCICR2_TE_MASK 8 /**< SCI control register 2 bit mask: transmitter enable */ +#endif /* ifndef SCICR2_TE_MASK */ + +#ifndef SCICR2_ILIE_MASK +#define SCICR2_ILIE_MASK 16 /**< SCI control register 2 bit mask: idle line interrupt enable*/ +#endif /* ifndef SCICR2_ILIE_MASK */ + +#ifndef SCICR2_RIE_MASK +#define SCICR2_RIE_MASK 32 /**< SCI control register 2 bit mask: receiver interrupt enable */ +#endif /* ifndef SCICR2_RIE_MASK */ + +#ifndef SCICR2_TCIE_MASK +#define SCICR2_TCIE_MASK 64 /**< SCI control register 2 bit mask: transmission complete interrupt enable */ +#endif /* ifndef SCICR2_TCIE_MASK */ + +#ifndef SCICR2_TIE_MASK +#define SCICR2_TIE_MASK 128 /**< SCI control register 2 bit mask: transmit interrupt enable */ +#endif /* ifndef SCICR2_TIE_MASK */ + +/* SCISR1 - SCI Status Register */ +#ifndef SCISR1_PF_MASK +#define SCISR1_PF_MASK 1 /**< SCI status register 1 bit mask: parity error flag */ +#endif /* ifndef SCISR1_PF_MASK */ + +#ifndef SCISR1_FE_MASK +#define SCISR1_FE_MASK 2 /**< SCI status register 1 bit mask: framing error flag */ +#endif /* ifndef SCISR1_FE_MASK */ + +#ifndef SCISR1_NF_MASK +#define SCISR1_NF_MASK 4 /**< SCI status register 1 bit mask: noise flag */ +#endif /* ifndef SCISR1_NF_MASK */ + +#ifndef SCISR1_OR_MASK +#define SCISR1_OR_MASK 8 /**< SCI status register 1 bit mask: receiver overrun flag */ +#endif /* ifndef SCISR1_OR_MASK */ + +#ifndef SCISR1_IDLE_MASK +#define SCISR1_IDLE_MASK 16 /**< SCI status register 1 bit mask: idle line flag */ +#endif /* ifndef SCISR1_IDLE_MASK */ + +#ifndef SCISR1_RDRF_MASK +#define SCISR1_RDRF_MASK 32 /**< SCI status register 1 bit mask: receive data register full flag */ +#endif /* ifndef SCISR1_RDRF_MASK */ + +#ifndef SCISR1_TC_MASK +#define SCISR1_TC_MASK 64 /**< SCI status register 1 bit mask: transmission complete flag*/ +#endif /* ifndef SCISR1_TC_MASK */ + +#ifndef SCISR1_TDRE_MASK +#define SCISR1_TDRE_MASK 128 /**< SCI status register 1 bit mask: transmit data register empty flag */ +#endif /* ifndef SCISR1_TDRE_MASK */ + +/* SCISR2 - SCI Status Register 2 */ + +#if (SCI_VERSION == SCI_V2) +#ifndef SCISR2_RAF_MASK +#define SCISR2_RAF_MASK 1 /**< SCI status register 2 bit mask: receiver active flag */ +#endif /* ifndef SCISR2_RAF_MASK */ + +#ifndef SCISR2_BRK13_MASK +#define SCISR2_BRK13_MASK 4 /**< SCI status register 2 bit mask: break character length */ +#endif /* ifndef SCISR2_BRK13_MASK */ +#endif /* End (SCI_VERSION == SCI_V2) */ + +#if (SCI_VERSION == SCI_V4) +#ifndef SCISR2_RAF_MASK +#define SCISR2_RAF_MASK 1 /**< SCI status register 2 bit mask: receiver active flag */ +#endif /* ifndef SCISR2_RAF_MASK */ + +#ifndef SCISR2_LBKDE_MASK +#define SCISR2_LBKDE_MASK 2 /**< SCI status register 2 bit mask: LIN break detection enable */ +#endif /* ifndef SCISR2_LBKDE_MASK */ + +#ifndef SCISR2_BRK13_MASK +#define SCISR2_BRK13_MASK 4 /**< SCI status register 2 bit mask: break character length */ +#endif /* ifndef SCISR2_BRK13_MASK */ + +#ifndef SCISR2_RWUID_MASK +#define SCISR2_RWUID_MASK 8 /**< SCI status register 2 bit mask: receive wakeup idle detect */ +#endif /* ifndef SCISR2_RWUID_MASK */ + +#ifndef SCISR2_RXINV_MASK +#define SCISR2_RXINV_MASK 16 /**< SCI status register 2 bit mask: receive data inversion */ +#endif /* ifndef SCISR2_RXINV_MASK */ + +#ifndef SCISR2_RXEDGIF_MASK +#define SCISR2_RXEDGIF_MASK 64 /**< SCI status register 2 bit mask: RxD pin active edge interrupt flag */ +#endif /* ifndef SCISR2_RXEDGIF_MASK */ + +#ifndef SCISR2_LBKDIF_MASK +#define SCISR2_LBKDIF_MASK 128 /**< SCI status register 2 bit mask: LIN break detect interrupt flag */ +#endif /* ifndef SCISR2_LBKDIF_MASK */ + +#endif /* End (SCI_VERSION == SCI_V4) */ + +#if ((SCI_VERSION == SCI_V5) || (SCI_VERSION == SCI_V6)) +#ifndef SCISR2_RAF_MASK +#define SCISR2_RAF_MASK 1 /**< SCI status register 2 bit mask: receiver active flag */ +#endif /* ifndef SCISR2_RAF_MASK */ + +#ifndef SCISR2_TXDIR_MASK +#define SCISR2_TXDIR_MASK 2 /**< SCI status register 2 bit mask: transmitter pin data direction in single-wire mode */ +#endif /* ifndef SCISR2_TXDIR_MASK */ + +#ifndef SCISR2_BRK13_MASK +#define SCISR2_BRK13_MASK 4 /**< SCI status register 2 bit mask: break character length */ +#endif /* ifndef SCISR2_BRK13_MASK */ + +#ifndef SCISR2_RXPOL_MASK +#define SCISR2_RXPOL_MASK 8 /**< SCI status register 2 bit mask: receive polarity */ +#endif /* ifndef SCISR2_RXPOL_MASK */ + +#ifndef SCISR2_TXPOL_MASK +#define SCISR2_TXPOL_MASK 16 /**< SCI status register 2 bit mask: transmit polarity */ +#endif /* ifndef SCISR2_TXPOL_MASK */ + +#ifndef SCISR2_AMAP_MASK +#define SCISR2_AMAP_MASK 128 /**< SCI status register 2 bit mask: transmit map */ +#endif /* ifndef SCISR2_AMAP_MASK */ + +#endif /* End (SCI_VERSION == SCI_V5) */ + +#if ((SCI_VERSION != SCI_V5) && (SCI_VERSION != SCI_V6)) +/* SCICR3 - SCI Control Register 3 */ +#ifndef SCICR3_PEIE_MASK +#define SCICR3_PEIE_MASK 1 /**< SCI control register 3 bit mask: parity error interrupt enable */ +#endif /* ifndef SCICR3_PEIE_MASK */ + +#ifndef SCICR3_FEIE_MASK +#define SCICR3_FEIE_MASK 2 /**< SCI control register 3 bit mask: framing error interrupt enable */ +#endif /* ifndef SCICR3_FEIE_MASK */ + +#ifndef SCICR3_NEIE_MASK +#define SCICR3_NEIE_MASK 4 /**< SCI control register 3 bit mask: noise error interrupt enable */ +#endif /* ifndef SCICR3_NEIE_MASK */ + +#ifndef SCICR3_ORIE_MASK +#define SCICR3_ORIE_MASK 8 /**< SCI control register 3 bit mask: overrun interrupt enable */ +#endif /* ifndef SCICR3_ORIE_MASK */ + +#ifndef SCICR3_TXINV_MASK +#define SCICR3_TXINV_MASK 16 /**< SCI control register 3 bit mask: transmit data inversion */ +#endif /* ifndef SCICR3_TXINV_MASK */ + +#ifndef SCICR3_TXDIR_MASK +#define SCICR3_TXDIR_MASK 32 /**< SCI control register 3 bit mask: TxD pin direction in single-wire mode */ +#endif /* ifndef SCICR3_TXDIR_MASK */ + +#ifndef SCICR3_T8_MASK +#define SCICR3_T8_MASK 64 /**< SCI control register 3 bit mask: Ninth data bit for transmitter */ +#endif /* ifndef SCICR3_T8_MASK */ + +#ifndef SCICR3_R8_MASK +#define SCICR3_R8_MASK 128 /**< SCI control register 3 bit mask: ninth data bit for receiver */ +#endif /* ifndef SCICR3_R8_MASK */ + +/* SCID - SCI Data Register */ +#if (defined(_MC9S08DZ128_H)|| defined(_MM9Z1J638_H)||(SCI_VERSION == SCI_V4)) +#ifndef SCID_R0_T0_MASK +#define SCID_R0_T0_MASK 1 /**< SCI data register bit mask: bit 0 */ +#endif /* ifndef SCID_R0_T0_MASK */ + +#ifndef SCID_R1_T1_MASK +#define SCID_R1_T1_MASK 2 /**< SCI data register bit mask: bit 1 */ +#endif /* ifndef SCID_R1_T1_MASK */ + +#ifndef SCID_R2_T2_MASK +#define SCID_R2_T2_MASK 4 /**< SCI data register bit mask: bit 2 */ +#endif /* ifndef SCID_R2_T2_MASK */ + +#ifndef SCID_R3_T3_MASK +#define SCID_R3_T3_MASK 8 /**< SCI data register bit mask: bit 3 */ +#endif /* ifndef SCID_R3_T3_MASK */ + +#ifndef SCID_R4_T4_MASK +#define SCID_R4_T4_MASK 16 /**< SCI data register bit mask: bit 4 */ +#endif /* ifndef SCID_R4_T4_MASK */ + +#ifndef SCID_R5_T5_MASK +#define SCID_R5_T5_MASK 32 /**< SCI data register bit mask: bit 5 */ +#endif /* ifndef SCID_R5_T5_MASK */ + +#ifndef SCID_R6_T6_MASK +#define SCID_R6_T6_MASK 64 /**< SCI data register bit mask: bit 6 */ +#endif /* ifndef SCID_R6_T6_MASK */ + +#ifndef SCID_R7_T7_MASK +#define SCID_R7_T7_MASK 128 /**< SCI data register bit mask: bit 7 */ +#endif /* ifndef SCID_R7_T7_MASK */ +#endif /* End (!defined(_MC9S08SG32_H))*/ + +#else + +/* SCI Data Register High */ +#ifndef SCIDRH_T8_MASK +#define SCIDRH_T8_MASK 64 /**< SCI data register high bit mask: transmit bit 8 */ +#endif /* ifndef SCIDRH_T8_MASK */ +#ifndef SCIDRH_R8_MASK +#define SCIDRH_R8_MASK 128 /**< SCI data register high bit mask: receive bit 8 */ +#endif /* ifndef SCIDRH_R8_MASK */ + +/* SCI Data Register Low */ +#ifndef SCIDRL_R0_T0_MASK +#define SCIDRL_R0_T0_MASK 1 /**< SCI data register low bit mask: bit 0 */ +#endif /* ifndef SCIDRL_R0_T0_MASK */ + +#ifndef SCIDRL_R1_T1_MASK +#define SCIDRL_R1_T1_MASK 2 /**< SCI data register low bit mask: bit 1 */ +#endif /* ifndef SCIDRL_R1_T1_MASK */ + +#ifndef SCIDRL_R2_T2_MASK +#define SCIDRL_R2_T2_MASK 4 /**< SCI data register low bit mask: bit 2 */ +#endif /* ifndef SCIDRL_R2_T2_MASK */ + +#ifndef SCIDRL_R3_T3_MASK +#define SCIDRL_R3_T3_MASK 8 /**< SCI data register low bit mask: bit 3 */ +#endif /* ifndef SCIDRL_R3_T3_MASK */ + +#ifndef SCIDRL_R4_T4_MASK +#define SCIDRL_R4_T4_MASK 16 /**< SCI data register low bit mask: bit 4 */ +#endif /* ifndef SCIDRL_R4_T4_MASK */ + +#ifndef SCIDRL_R5_T5_MASK +#define SCIDRL_R5_T5_MASK 32 /**< SCI data register low bit mask: bit 5 */ +#endif /* ifndef SCIDRL_R5_T5_MASK */ + +#ifndef SCIDRL_R6_T6_MASK +#define SCIDRL_R6_T6_MASK 64 /**< SCI data register low bit mask: bit 6 */ +#endif /* ifndef SCIDRL_R6_T6_MASK */ + +#ifndef SCIDRL_R7_T7_MASK +#define SCIDRL_R7_T7_MASK 128 /**< SCI data register low bit mask: bit 7 */ +#endif /* ifndef SCIDRL_R7_T7_MASK */ + +#endif /* End (SCI_VERSION != SCI_V5) */ +#endif /* Lin register */ + +/** +* @} +*/ diff --git a/LIN_Stack/coreapi/lin_common_api.c b/LIN_Stack/coreapi/lin_common_api.c new file mode 100644 index 0000000..a368326 --- /dev/null +++ b/LIN_Stack/coreapi/lin_common_api.c @@ -0,0 +1,246 @@ +/****************************************************************************** +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +*****************************************************************************/ + +/** @addtogroup common_core_api_group +* @{ */ + +/**************************************************************************//** +* +* @file lin_common_api.c +* +* @author FPT Software +* +* @brief Common LIN API functions +* +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +/** @} */ + +#include "lin_common_api.h" +#include "lin_common_proto.h" +#include "lin.h" + +#if (XGATE_SUPPORT == 1) +#include "lin_lld_xgate.h" +#endif /* End (XGATE_SUPPORT == 1) */ + +/* -------------------------------FUNCTION COMMON --------------------------- */ +/** @addtogroup driver_cluster_group +* @{ */ +l_bool l_sys_init () +{ +#if XGATE_SUPPORT == 1 + lin_lld_setup_xgate(); +#endif /* End (XGATE_SUPPORT == 1) */ + lin_lld_timer_init(); + return 0; +} /* end of l_sys_init() */ +/** @} */ + +#if LIN_MODE == _MASTER_MODE_ +/** @addtogroup schedule_management_group +* @{ */ +void l_sch_set +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] schedule table for interface */ + l_schedule_handle schedule_iii, + /* [IN] entry to be set */ + l_u8 entry +) +{ + lin_configuration const *conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + if ((conf->function == _MASTER_) && (schedule_iii < LIN_NUM_OF_SCHD_TBL)) + { + /* Check if input entry is in range from 0 to N = (Number of frame slots) */ + if (entry <= conf->schedule_tbl[schedule_iii].num_slots) + { + /* save the new schedule which is activated after the */ + /* current schedule reaches its next schedule entry point */ + *(conf->previous_schedule_id) = *(conf->active_schedule_id); + /* Insert new schedule at that point of the current schdule */ + *(conf->active_schedule_id) = (l_u8)schedule_iii; + /* if entry is 0 or 1 the new schedule table will be started from the beginning. */ + if (entry == 0U) + { + /* Set entry equal to 1 */ + entry = 1U; + } + /* Assign the start entry of new schedule table by argument entry */ + conf->schedule_start_entry[schedule_iii] = entry - 1; + } + } +} /* end of l_sch_set() */ + +l_u8 l_sch_tick +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + return lin_tick_callback_handler(iii); +} /* end of l_sch_tick() */ +/** @} */ +#endif /* End LIN_MODE == _MASTER_MODE_ */ + +/** @addtogroup interface_management_group +* @{ */ +l_bool l_ifc_init +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ +#if LIN_MODE == _SLAVE_MODE_ + return lin_lld_init(); +#else + return lin_lld_init(iii); +#endif /* End LIN_MODE == _SLAVE_MODE_ */ +} /* end of l_ifc_init() */ + +void l_ifc_goto_sleep +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + /* If node is master node */ +#if LIN_MODE == _MASTER_MODE_ + /* Get current configuration */ + lin_configuration const *conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Set active schedule as GOTO_SLEEP_SCHEDULE */ + l_sch_set(iii, (l_schedule_handle)(conf->schedule_start + 1), 0); + +#endif /* End LIN_MODE == _MASTER_MODE_ */ +} /* end of l_ifc_goto_sleep() */ + +void l_ifc_wake_up +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_tx_wake_up(); +#else + /* Send wakeup signal */ + lin_lld_tx_wake_up(iii); + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} /* end of l_ifc_wake_up() */ + +void l_ifc_rx +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + +} /* end of l_ifc_rx() */ + +void l_ifc_tx +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + +} /* end of l_ifc_tx() */ + +void l_ifc_aux +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + +} /* end of l_ifc_aux() */ +l_u16 l_ifc_read_status +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + static l_u16 tmp_word_status; +#if LIN_MODE == _SLAVE_MODE_ + tmp_word_status = lin_word_status.word; + /* Clear Word status */ + lin_word_status.word = 0; + /* Clear Save configuration flag value */ + lin_save_configuration_flg = 0; + /* Clear Successful transfer */ + lin_successful_transfer = 0; + /* Clear Error in response */ + lin_error_in_response = 0; + /* Clear Goto sleep flag */ + lin_goto_sleep_flg = 0; + /* Clear Current pid */ + lin_current_pid = 0x00; +#else + lin_configuration const *conf; + conf = &lin_ifc_configuration[iii]; + tmp_word_status = *((l_u16*)(conf->word_status)); + /* Read-reset call; meaning that after the call has returned, + the status word is set to 0 */ + /* Clear word status */ + *((l_u16*)(conf->word_status)) = 0; + /* Clear save configuration flag value */ + lin_save_configuration_flg[iii] = 0; + /* Clear Successful transfer */ + *(conf->successful_transfer)= 0; + /* Clear Error in response */ + *(conf->error_in_response)= 0; + /* Clear Goto sleep flag */ + *(conf->goto_sleep_flg) = 0; + /* Clear Current pid */ + *(conf->current_pid) = 0x00; +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + + return (tmp_word_status); +} /* end of l_ifc_read_status() */ +/** @} */ + +/** @addtogroup call_out_group +* @{ */ +l_u16 l_sys_irq_disable +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ +#if LIN_MODE == _SLAVE_MODE_ + return lin_lld_int_disable(); +#else + return lin_lld_int_disable(iii); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} /* end of l_sys_irq_disable() */ + +void l_sys_irq_restore +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ +#if LIN_MODE == _SLAVE_MODE_ + lin_lld_int_enable(); +#else + lin_lld_int_enable(iii); +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +} /* end of l_sys_irq_restore() */ +/** @} */ diff --git a/LIN_Stack/coreapi/lin_common_proto.c b/LIN_Stack/coreapi/lin_common_proto.c new file mode 100644 index 0000000..f7ae8ed --- /dev/null +++ b/LIN_Stack/coreapi/lin_common_proto.c @@ -0,0 +1,1601 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup common_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_common_proto.c +* +* @author FPT Software +* +* @brief Common LIN protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ +#include "derivative.h" +#include "lin.h" +#include "lin_common_proto.h" +#include "lin_lin21_proto.h" +#include "lin_j2602_proto.h" +#include "lin_common_api.h" +/* Unuse for GPIO */ +#if ( _LIN_GPIO_ == 0 ) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) +#include "lin_commontl_proto.h" +#include "lin_lin21tl_api.h" +#include "lin_j2602tl_api.h" +#endif /* End ( _LIN_GPIO_ == 0 ) && !defined(_MC9S08SC4_H) */ + + +/* ---------------------------- For 1 interface ----------------------------------- */ +#if LIN_MODE == _SLAVE_MODE_ +/** + * @var l_u8 frame_signal_error + * frame or signal error + */ +l_u8 frame_signal_error; + +/* Global variables */ +/** + * @var l_u8 frame_index + * index of frame in frames table + */ +l_u8 frame_index; + + +void lin_pid_response_callback_handler +( + /* [IN] event id */ + lin_lld_event_id event_id, + /* [IN] PID to process */ + l_u8 pid +) +{ + if (LIN_LLD_PID_OK == event_id) + { + lin_process_pid(pid); + } + else if (LIN_LLD_TX_COMPLETED == event_id) + { + lin_update_tx(pid); + } + else if (LIN_LLD_RX_COMPLETED == event_id) + { + lin_update_rx(pid); + } +#if !defined(MCU_SKEAZN84) /* Not cover for KEA8 platform */ + else if (LIN_LLD_BUS_ACTIVITY_TIMEOUT == event_id) + { + lin_bus_activity_timeout(pid); + } + else + { + lin_handle_error(event_id, pid); + } +#endif /*!defined(MCU_SKEAZN84) */ +} /* end of lin_pid_response_callback_handler() */ + + +void lin_process_pid +( + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u8 action; + const lin_frame_struct *lin_frame_ptr; + + #if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) && !defined(MCU_SKEAZN84) + l_u8 volatile associate_frame; + l_u16 flag_offset; + l_u8 flag_size; + l_u8 i; + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + /* get frame index */ + frame_index = lin_get_frame_index(pid); + if (0xFF == frame_index) + { + action = 0; + } + else + { + action = 1; + lin_frame_ptr = &(lin_frame_tbl[frame_index]); + /* PID belongs to this node, then check type of frame */ + #if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) && !defined(MCU_SKEAZN84) + if (LIN_FRM_EVNT == lin_frame_ptr->frm_type) + { + associate_frame = (l_u8)(*(lin_frame_ptr->frame_data)); + flag_offset = lin_frame_tbl[associate_frame].flag_offset; + flag_size = lin_frame_tbl[associate_frame].flag_size; + action = 0; + /* Update transmit flags */ + for (i = 0U; i < flag_size; i++) + { + if (lin_flag_handle_tbl[flag_offset++] != 0xFFU) + { + /* Frame is updated */ + /* Get the PID of the associated unconditional frame */ + pid = lin_configuration_RAM[1 + *(lin_frame_ptr->frame_data)]; + /* Get the frame index in lin_frame_tbl[] */ + frame_index = lin_get_frame_index(pid); + /* Create frame response */ + lin_make_res_evnt_frame(pid); + /* Set response */ + action = 2; + } + } + } + else + { + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + if (LIN_RES_PUB == lin_frame_ptr->frm_response) + { + if (LIN_FRM_UNCD == lin_frame_ptr->frm_type) + { + lin_process_uncd_frame(pid, MAKE_UNCONDITIONAL_FRAME); + action = 2; + } + /* Unuse for GPIO */ + #if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) + else + { + if (0 == tl_slaveresp_cnt) + { + action = 0; + } + else + { + if (tl_service_status != LD_SERVICE_ERROR) + { + lin_make_res_diag_frame(); + tl_slaveresp_cnt--; + action = 2; + } + else + { + /*ignore */ + action = 0; + } + } + } + #endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ + } + #if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) && !defined(MCU_SKEAZN84) + } + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + } + /* Ignore diagnostic frame when interface is GPIO */ +#if (_LIN_GPIO_ == 1) + if (pid == 0x3C || pid == 0x3D) + { + action = 0; + } +#endif /* End (_LIN_GPIO_ == 1) */ + switch (action) + { + case 1: + /* Receive response */ + lin_lld_rx_response(lin_frame_ptr->frm_len); + break; + case 2: + /* Set response */ + lin_lld_set_response(lin_frame_ptr->frm_len); + break; + default: + /* ignore response */ + lin_lld_ignore_response(); + break; + } +} + +void lin_update_rx +( + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u16 flag_offset; + l_u8 flag_size, i; + flag_offset = lin_frame_tbl[frame_index].flag_offset; + flag_size = lin_frame_tbl[frame_index].flag_size; + + /* Set successful transfer */ + lin_successful_transfer = 1; + /* PID belongs to this node, then check type of frame */ + if (LIN_FRM_UNCD == lin_frame_tbl[frame_index].frm_type) + { + lin_process_uncd_frame(pid, UPDATE_UNCONDITIONAL_FRAME); + } + /* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) + else if (LIN_FRM_DIAG == lin_frame_tbl[frame_index].frm_type) + { + lin_update_rx_diag_frame(); + } +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ + /* Update rx frame flag */ + lin_frame_flag_tbl[frame_index] = 1; + /* Update rx frame flags */ + for (i = 0; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset++] = 0xFF; + } + + /* update word status */ +#if !defined(MCU_SKEAZN84) +#if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_word_status_lin21 (pid); +#else + lin_update_word_status_j2602 (LIN_LLD_RX_COMPLETED, pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ +#endif /* !defined(MCU_SKEAZN84) */ +} + +void lin_update_tx +( + /* [IN] PID to process */ + l_u8 pid +) +{ +#if (LIN_PROTOCOL == PROTOCOL_J2602) + l_u8 i; + l_u16 byte_offset_temp; + l_u8 bit_offset_temp; +#else + /* Check signal error */ + l_signal_handle *ptr; + ptr = (l_signal_handle *)lin_frame_tbl[frame_index].frame_data; +#endif/* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + /* Set successful transfer */ + lin_successful_transfer = 1; + /* Update again in case event triggered frame. The frame index has been modified */ + frame_index = lin_get_frame_index(pid); + /* Update transmit flags */ + lin_update_tx_flags(frame_index); + lin_frame_flag_tbl[frame_index] = 1; + + /* Update word status */ +#if (LIN_PROTOCOL == PROTOCOL_21) + #if !defined(MCU_SKEAZN84) /* Not cover for KEA8 platform */ + /* Check frame contain the response_error signal or not */ + if (ptr != 0) + { + if (*ptr == response_error) + { + /* Clear error signal in frame data buffer */ + lin_error_in_response = 0; + lin_update_err_signal(frame_index); + } + } + lin_update_word_status_lin21 (pid); + #endif /*!defined(MCU_SKEAZN84) */ +#else + #if (LIN_PROTOCOL == PROTOCOL_J2602) + if (0x3D != pid) + { + lin_error_in_response = 0; + /* Set error signal equal to error in response */ + for (i = 0; i < num_frame_have_esignal; i++) + { + /* Get pointer to Byte and bit offset values in each frame that contains the error signal */ + byte_offset_temp = lin_response_error_byte_offset[i]; + bit_offset_temp = lin_response_error_bit_offset[i]; + /* Set error signal equal to error in response */ + lin_pFrameBuf[byte_offset_temp] = (l_u8)(lin_pFrameBuf[byte_offset_temp] & (~(0x07U << bit_offset_temp))); + } + } + #else + #if !defined(MCU_SKEAZN84) /* Not cover for KEA8 platform */ + /* Check frame contain the response_error signal or not */ + if (ptr != 0) + { + if (*ptr == response_error) + { + /* Clear error signal in frame data buffer */ + lin_error_in_response = 0; + lin_update_err_signal(frame_index); + } + } + #endif /*!defined(MCU_SKEAZN84) */ + #endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_update_word_status_j2602 (LIN_LLD_TX_COMPLETED, pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if (0x3D == pid) + { + /* process message */ + tl_tx_msg_size--; + if (0 == tl_tx_msg_size) + { + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_tx_msg_status = LD_COMPLETED; + tl_service_status = LD_SERVICE_IDLE; + tl_diag_state = LD_DIAG_IDLE; + } + else + { + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + tl_diag_state = LD_DIAG_TX_PHY; + } + } +#else /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#if ( _LIN_GPIO_ == 0 ) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) + if (0x3D == pid) + { + if (0 == tl_slaveresp_cnt) + { + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_check_timeout = N_MAX_TIMEOUT_CNT; + } + } +#endif +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ +} + +#if !defined(MCU_SKEAZN84) /* Not cover for KEA8 platform */ +void lin_handle_error +( + /* [IN] event id */ + lin_lld_event_id event_id, + /* [IN] PID to process */ + l_u8 pid +) +{ + frame_index = lin_get_frame_index(pid); + switch (event_id) + { + /* PID error */ + case LIN_LLD_PID_ERR: + /* do nothing here */ + break; + /* Frame error */ + case LIN_LLD_FRAME_ERR: + case LIN_LLD_CHECKSUM_ERR: + case LIN_LLD_READBACK_ERR: + case LIN_LLD_NODATA_TIMEOUT: + if (LIN_FRM_EVNT != lin_frame_tbl[frame_index].frm_type) + { + /* Set response error */ + lin_error_in_response = 1; + } + + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if (0x3C == pid) + { + tl_receive_msg_status = LD_FAILED; + tl_rx_msg_status = LD_FAILED; + lin_tl_rx_queue.queue_status = LD_RECEIVE_ERROR; + tl_slaveresp_cnt = 0; + tl_diag_state = LD_DIAG_IDLE; + } + else if (0x3D == pid) + { + tl_tx_msg_status = LD_FAILED; + lin_tl_tx_queue.queue_status = LD_TRANSMIT_ERROR; + tl_diag_state = LD_DIAG_IDLE; + } + tl_service_status = LD_SERVICE_ERROR; + #else /* Single frame support */ + #if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) + if (0x3C == pid) + { + tl_slaveresp_cnt = 0; + } + #endif /* (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + break; + default: + break; + } + /* Update word status */ +#if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_err_signal(frame_index); + lin_update_word_status_lin21 (pid); +#else + #if (LIN_PROTOCOL == PROTOCOL_J2602) + lin_update_status_byte(event_id); + #else + lin_update_err_signal(frame_index); + #endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_update_word_status_j2602 (event_id, pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + +} + +void lin_bus_activity_timeout +( + /* [IN] PID to process */ + l_u8 pid +) +{ +#if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_word_status_lin21 (pid); +#else + lin_update_word_status_j2602 (LIN_LLD_BUS_ACTIVITY_TIMEOUT, pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + /* Change to low power mode */ + lin_lld_set_low_power_mode(); +} +#endif /* !defined(MCU_SKEAZN84) */ +void lin_update_tx_flags +( + /* [IN] index of frame */ + l_u8 frm_id +) +{ + l_u16 flag_offset; + l_u8 flag_size, i; + l_u8 associate_frame; + + /* Update event triggered flags */ + if (LIN_FRM_EVNT == lin_frame_tbl[frm_id].frm_type) + { + associate_frame = (l_u8)(*(lin_frame_tbl[frame_index].frame_data)); + flag_offset = lin_frame_tbl[associate_frame].flag_offset; + flag_size = lin_frame_tbl[associate_frame].flag_size; + /* Update transmit flags */ + for (i = 0U; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset] = 0xFFU; + flag_offset++; + } + } + /* Find the signal id associated with frame */ + else if (LIN_FRM_DIAG != lin_frame_tbl[frm_id].frm_type) + { + flag_offset = lin_frame_tbl[frm_id].flag_offset; + flag_size = lin_frame_tbl[frm_id].flag_size; + for (i = 0; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset++] = 0xFF; + } + } +} + +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) +void lin_update_rx_diag_frame +( +) +{ + /* Check goto sleep */ + if (0x00 == lin_lld_response_buffer[1]) + { + lin_goto_sleep_flg = 1; + + M_ASK_S_Sleep=1; + + lin_lld_set_low_power_mode(); + return; + } + /* TL support */ + /* Single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + /* Copy response to diagnostic PDU in TL */ + lin_tl_put_pdu(); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + /* Process PDU income */ + lin_tl_handler(); +} + +void lin_make_res_diag_frame +( + +) +{ + /* get data from tx queue to response buffer */ + lin_tl_get_pdu(); +} +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) */ +l_u8 lin_get_frame_index +( + /* [IN] PID of frame */ + l_u8 pid +) +{ + l_u8 i; + for (i = LIN_NUM_OF_FRMS; 0 < i; i--) + { + if (lin_configuration_RAM[i] == pid) + { + return (i - 1); + } + } + return 0xFF; +} + +void lin_process_uncd_frame +( + /* [IN] PID to process */ + l_u8 pid, + /* [IN] make or update */ + l_u8 type +) +{ + l_u16 frame_byte_offset; + l_u8 flag, i; + /* Set frame length */ + lin_lld_response_buffer[0] = lin_frame_tbl[frame_index].frm_len; + frame_byte_offset = lin_frame_tbl[frame_index].frm_offset; + + if (MAKE_UNCONDITIONAL_FRAME == type) + { + /* get data from lin frame buffer */ + flag = lin_frame_updating_flag_tbl[frame_index]; + + for (i = 1; i < lin_lld_response_buffer[0]+1; i++, frame_byte_offset++) + { + if(flag & (1<<(i-1))) + { + lin_lld_response_buffer[i] = buffer_backup_data[i-1]; + } + else + { + lin_lld_response_buffer[i] = lin_pFrameBuf[frame_byte_offset]; + } + } + } + else + { + for (i = 1; i < lin_lld_response_buffer[0]+1; i++, frame_byte_offset++) + { + lin_pFrameBuf[frame_byte_offset] = lin_lld_response_buffer[i]; + } + } +} +#endif /* End of (LIN_MODE == _SLAVE_MODE_) */ + +/* ----------------------------------------------------------------------- */ +#if LIN_MODE == _MASTER_MODE_ + +extern l_u8 etf_collision_flag[LIN_NUM_OF_IFCS]; +/** + * @var l_u8 frame_signal_error + * frame or signal error + */ +l_u8 frame_signal_error[LIN_NUM_OF_IFCS]; + +#ifdef MULTI_TIMER_MODE +extern const l_u16 max_tl_timeout_counter[LIN_NUM_OF_IFCS]; +#endif /* End MULTI_TIMER_MODE */ + +void lin_pid_response_callback_handler +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] event id */ + lin_lld_event_id event_id, + /* [IN] PID to process */ + l_u8 pid +) +{ + if (LIN_LLD_PID_OK == event_id) + { + lin_process_pid(iii, pid); + } + else if (LIN_LLD_TX_COMPLETED == event_id) + { + lin_update_tx(iii, pid); + } + else if (LIN_LLD_RX_COMPLETED == event_id) + { + lin_update_rx(iii, pid); + } + else if (LIN_LLD_BUS_ACTIVITY_TIMEOUT == event_id) + { + lin_bus_activity_timeout(iii, pid); + } + else + { + lin_handle_error(iii, event_id, pid); + } +} + +l_u8 lin_tick_callback_handler +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + lin_schedule_struct *sch; + l_u8 *current_entry; + l_u8 frame_index; + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + l_u8 *cur_pid; + l_u8 *_active_schedule_id; + l_bool send_master_request_header_flag = 0; + l_u8 i; + l_u8 retVal = 0U; + lin_tl_queue *current_pdu; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + tl_conf = conf->tl_desc; + /* Get active_schedule_id */ + _active_schedule_id = conf->active_schedule_id; + cur_pid = conf->current_pid; + + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* process diagnostic interleaved mode */ + if (*cur_pid == 0x3D && *conf->diagnostic_mode == DIAG_INTER_LEAVE_MODE && *conf->tl_diag_interleave_state == DIAG_NO_RESPONSE) + { + /* go back normal schedule table */ + *_active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*_active_schedule_id] = 0; + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + sch = (lin_schedule_struct*)&conf->schedule_tbl[*_active_schedule_id]; + current_entry = (l_u8 *)&conf->schedule_start_entry[*_active_schedule_id]; + + if (LIN_SCH_TBL_NULL != sch->sch_tbl_type) + { + /* Check if next_transmit is 0 */ + if (0 == *(conf->next_transmit_tick)) + { + /* Check protocol */ + #if (LIN_PROTOCOL == PROTOCOL_21)||(LIN_PROTOCOL == PROTOCOL_20) + if (etf_collision_flag[iii] == 1) + { + /* Call collison resolver */ + lin_collision_resolve(iii, *cur_pid) ; + /* Update active schedule table */ + sch = (lin_schedule_struct*)&conf->schedule_tbl[*_active_schedule_id]; + /* Re-calculate current entry due to change table to collision */ + current_entry = (l_u8 *)&conf->schedule_start_entry[*_active_schedule_id]; + lin_lld_clear_etf_collision_flag(iii); + } + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + + + /* Set new transmit tick */ + *(conf->next_transmit_tick) = sch->ptr_sch_data[*current_entry].delay_integer; + + /* Get frame index to send */ + frame_index = (l_u8)sch->ptr_sch_data[*current_entry].frm_id; + + if ((frame_index - conf->frame_start) < conf->num_of_frames) + { + *cur_pid = conf->configuration_RAM[frame_index - conf->frame_start + 1]; + } + + /* TL support */ + /* get PDU poiter for MasterRequest frame */ + current_pdu = (lin_tl_queue *)&(sch->ptr_sch_data[*current_entry].tl_queue_data); + + /* Single frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + /* Get TL configuration */ + /* In a normal table, send Master Request with data in the schedule*/ + if ((LIN_SCH_TBL_DIAG != sch->sch_tbl_type) && (0x3C == *cur_pid)) + { + tl_conf->tl_tx_single_pdu = current_pdu; + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* increase start entry */ + *current_entry = (* current_entry + 1); + + /* Check if it is the last entry */ + if (*current_entry >= sch->num_slots) + { + /* switch schedule table */ + lin_switch_sch_table(iii); + } + + if (LIN_FRM_SPRDC == conf->frame_tbl[frame_index].frm_type) + { + /* Sporadic frame */ + *cur_pid = lin_check_sporadic_update(iii, (l_frame_handle)frame_index); + } + + if (0xFF != *cur_pid) + { + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* In a normal table, send Master Request with data in the schedule*/ + if ((0x3C == *cur_pid) && (LIN_SCH_TBL_DIAG != sch->sch_tbl_type)) + { + for (i = 0; i < 8; i++) + { + conf->response_buffer[i+1] = (*current_pdu)[i]; + } + } + #else /* Single frame support */ + /* Transmit PID */ + if ((0x3C == *cur_pid) || (0x3D == *cur_pid)) + { + if (DIAG_INTER_LEAVE_MODE == conf->diagnostic_mode) + { + *(conf->diagnostic_frame_to_send) = (*(conf->diagnostic_frame_to_send) - 1); + } + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /*If current ID is 0x3D or other IDs except 0x3C, then send header unconditionally */ + if (0x3C != *cur_pid) + { + lin_lld_tx_header(iii, *cur_pid); + } + /* If current ID is 0x3C and the Master is running Diagnostic Master Request Schedule*/ + /*Then send 0x3C header */ + else if ((0x3C == *cur_pid) && (LIN_SCH_TBL_DIAG == sch->sch_tbl_type)) + { + lin_lld_tx_header(iii, *cur_pid); + } + /* If current ID is 0x3C and the Master is not running Diagnostic Master Request Schedule*/ + /*Then send 0x3C header only for some cases */ + else if ((0x3C == *cur_pid) && (LIN_SCH_TBL_DIAG != sch->sch_tbl_type)) + { + /* If the current entry is Master Request and has schedule data that is different from 0, then send header*/ + for (i = 0; i < 8; i++) + { + if ((*current_pdu)[i] != 0) + { + send_master_request_header_flag = 1; + } + } + /* If flag for send Master Request Header is true */ + if (send_master_request_header_flag) + { + lin_lld_tx_header(iii, *cur_pid); + } + + } + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* process diagnostic interleaved mode */ + if (*cur_pid == 0x3D && *conf->diagnostic_mode == DIAG_INTER_LEAVE_MODE) + { + *conf->tl_diag_interleave_state = DIAG_NO_RESPONSE; + if (INTERLEAVE_MAX_TIMEOUT == (tl_conf->tl_interleave_timeout_counter++)) + { + /* switch to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + /* inform service error */ + *conf->tl_service_status = LD_SERVICE_ERROR; + *conf->diagnostic_mode = DIAG_NONE; + } + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Next tick will not start a transmission */ + } + } /* End (LIN_SCH_TBL_NULL != sch->sch_tbl_type) */ + + /* Decrease next_transmit_tick */ + *(conf->next_transmit_tick) = (*(conf->next_transmit_tick) - 1); + + /* if the next call of l_sch_tick will start the transmission of the frame in the next schedule table entry */ + /* The return value will in this case be the next schedule table entry's number */ + /* counted from the beginning of the schedule table) in the schedule table */ + /* The return value will be in range 1 to N if the schedule table has N entries */ + if (0U == *(conf->next_transmit_tick)) + { + /* The return value will be in range 1 to N if the schedule table has N entries */ + if (*current_entry >= sch->num_slots) + { + /* If next entry is the first frame in the next schedule table */ + /* Then return 1*/ + retVal = 1U; + } + else + { + /* The return value will be in range 1 to N if the schedule table has N entries */ + retVal = (l_u8)(*current_entry + 1U); + } + } + } + + /* update word status */ + #if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_word_status_lin21(iii, (lin_lld_event_id)0, *cur_pid); + #else + lin_update_word_status_j2602(iii, (lin_lld_event_id)0, *cur_pid); + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + + return retVal; +} + +void lin_process_pid +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u8 action; + const lin_frame_struct *lin_frame_ptr; + l_u8 frame_index; +#if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) + l_u16 flag_offset; + l_u8 flag_size; + l_u8 i; + l_u8 volatile associate_frame; +#endif + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + frame_index = lin_get_frame_index(iii, pid); + if (0xFF == frame_index) + { + action = 0; + } + else + { + action = 1; + lin_frame_ptr = &(conf->frame_tbl[frame_index]); + /* PID belongs to this node, then check type of frame */ + switch(lin_frame_ptr->frm_type) + { + /* Unconditional frame */ + case LIN_FRM_UNCD: + if (LIN_RES_PUB == lin_frame_ptr->frm_response) + { + lin_process_uncd_frame(iii, pid, MAKE_UNCONDITIONAL_FRAME); + /* Set response */ + action = 2; + } + break; + #if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) + /* Event trigger frame */ + case LIN_FRM_EVNT: + if (_MASTER_ == conf->function) + { + /* Rx response */ + action = 1; + } + else + { + associate_frame = (l_u8)(*(((lin_associate_frame_struct*)(lin_frame_ptr->frame_data))->act_uncn_frm)); + flag_offset = conf->frame_tbl[associate_frame].flag_offset; + flag_size = conf->frame_tbl[associate_frame].flag_size; + /* Update transmit flags */ + for (i = 0U; i < flag_size; i++) + { + if (lin_flag_handle_tbl[flag_offset++] != 0xFFU) + { + /* Frame is updated */ + lin_make_res_evnt_frame(iii, conf->configuration_RAM[1 + (associate_frame)-conf->frame_start]); + /* Set response */ + action = 2; + } + } + } + break; + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + /* Diagnostic frame */ + case LIN_FRM_DIAG: + if ( LIN_RES_PUB == lin_frame_ptr->frm_response) + { + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + action = 2; + /* Master node */ + if (0x3C == pid) + { + if (DIAG_INTER_LEAVE_MODE == *conf->diagnostic_mode) + { + lin_tl_make_mreq_pdu(iii); + } + } + else + { + /* Slave mode */ + if ((tl_conf->tl_slaveresp_cnt == 0) && (0x3D == pid)) + { + action = 0; + } + else + { + /* Check error in multi frames */ + if (*conf->tl_service_status != LD_SERVICE_ERROR) + { + lin_make_res_diag_frame(iii, pid); + tl_conf->tl_slaveresp_cnt--; + } + else + { + /* Check is CF */ + /* ignore response when error */ + action = 0; + break; + } + } + } + #else /* Single frame support */ + /* TL support */ + /* Master mode */ + action = 2; + if (0x3C == pid) + { + lin_tl_make_mreq_pdu(iii, 0); + } + /* For 0x3D Identifier*/ + else + { + /* Slave mode */ + if ((tl_conf->tl_slaveresp_cnt == 0) || (tl_conf->tl_service_status == LD_SERVICE_ERROR)) + { + action = 0; + } + else + { + lin_make_res_diag_frame(iii, pid); + tl_conf->tl_slaveresp_cnt--; + } + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + } + else + { + /* Rx response */ + action = 1; + } + break; + default: + break; + } + } + switch (action) + { + case 1: + /* Receive response */ + lin_lld_rx_response(iii, lin_frame_ptr->frm_len); + break; + case 2: + /* Set response */ + lin_lld_set_response(iii, lin_frame_ptr->frm_len); + break; + default: + /* ignore response */ + lin_lld_ignore_response(iii); + break; + } +} + +void lin_update_rx +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u16 flag_offset; + l_u8 frame_index, flag_size, i, ass_pid; + + const lin_configuration *conf; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_descriptor *tl_conf; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Set successful transfer */ + *(conf->successful_transfer) = 1; + frame_index = lin_get_frame_index(iii, pid); + if (0xFF != frame_index) + { + /* This PID doesn't belong to this node */ + /* PID belongs to this node, then check type of frame */ + switch(conf->frame_tbl[frame_index].frm_type) + { + /* Unconditional frame */ + case LIN_FRM_UNCD: + lin_process_uncd_frame(iii, pid, UPDATE_UNCONDITIONAL_FRAME); + break; + /* Event trigger frame */ + case LIN_FRM_EVNT: + *(conf->error_in_response) = 0; + lin_update_rx_evnt_frame(iii, pid); + /* Recalculate frame_index by updating associate PID */ + ass_pid = lin_process_parity(conf->response_buffer[1], CHECK_PARITY); + frame_index = lin_get_frame_index(iii, ass_pid); + break; + /* Diagnostic frame */ + case LIN_FRM_DIAG: + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* process diagnostic interleaved mode */ + if (pid == 0x3D && *conf->diagnostic_mode == DIAG_INTER_LEAVE_MODE) + { + tl_conf = conf->tl_desc; + *conf->tl_diag_interleave_state = DIAG_RESPONSE; + /* do not check interleave time out counter when response receive */ + tl_conf->tl_interleave_timeout_counter = 0; + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + lin_update_rx_diag_frame(iii, pid); + break; + default: + break; + } + /* Update rx frame flag */ + lin_frame_flag_tbl[frame_index] = 1; + /* Update rx frame flags */ + flag_offset = lin_frame_tbl[frame_index].flag_offset; + flag_size = lin_frame_tbl[frame_index].flag_size; + for (i = 0; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset++] = 0xFF; + } + + /* update word status */ + if (_SLAVE_ == conf->function) + { + #if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_word_status_lin21 (iii, LIN_LLD_RX_COMPLETED, pid); + #else + lin_update_word_status_j2602 (iii, LIN_LLD_RX_COMPLETED, pid); + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + } + } +} + +void lin_update_tx +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u8 frame_index; +#if (LIN_PROTOCOL == PROTOCOL_J2602) + l_u8 i; + l_u16 *byte_offset_temp_ptr; + l_u8 *bit_offset_temp_ptr; + lin_node_attribute *node_att_ptr; +#else + /* Check signal error */ + l_signal_handle *ptr; +#endif + const lin_configuration *conf; + const lin_frame_struct *lin_frame_ptr; + + /* Multi frame support */ + lin_tl_descriptor *tl_conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Set successful transfer */ + *(conf->successful_transfer) = 1; + /* Find frame index by pid */ + frame_index = lin_get_frame_index(iii, pid); + lin_update_tx_flags(iii, frame_index); + lin_frame_flag_tbl[frame_index] = 1; + + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if ((0x3C == pid) && _MASTER_ == conf->function) + { + if(DIAG_INTER_LEAVE_MODE == *conf->diagnostic_mode) + { + /* Callback to transport layer */ + tl_process_mreq(iii); + } + if((conf->response_buffer)[1] == 0) + { + (*conf->goto_sleep_flg) = 1; + } + } + else if (_SLAVE_ == conf->function && 0x3D == pid) + { + /* process message */ + tl_conf->tl_tx_msg_size--; + if (0 == tl_conf->tl_tx_msg_size) + { + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_conf->tl_tx_msg_status = LD_COMPLETED; + *conf->tl_service_status = LD_SERVICE_IDLE; + } + else + { + + #ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; + #else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + #endif /* End MULTI_TIMER_MODE */ + tl_conf->tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + } + } +#else /* Single frame support */ + if ((0x3C == pid) && (_MASTER_ == conf->function)) + { + if (LIN_SCH_TBL_DIAG == conf->schedule_tbl[*conf->active_schedule_id].sch_tbl_type) + { + /* switch to slave response - next schedule table */ + *conf->active_schedule_id += 1; + + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + conf->tl_desc->tl_cnt_to_send = 0; + } + if((conf->response_buffer)[1] == 0) + { + (*conf->goto_sleep_flg) = 1; + } + } + else if (0x3D == pid && _SLAVE_ == conf->function) + { + if ( tl_conf->tl_slaveresp_cnt == 0) + { + /* slave response completed */ + conf->tl_desc->tl_service_status = LD_SERVICE_IDLE; + tl_check_timeout_type_array[iii] = LD_NO_CHECK_TIMEOUT; + tl_check_timeout_array[iii] = N_MAX_TIMEOUT_CNT; + } + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Update word status */ + if (_SLAVE_ == conf->function) + { +#if (LIN_PROTOCOL == PROTOCOL_21) + ptr = (l_signal_handle *)lin_frame_tbl[frame_index].frame_data; + /* Check frame contain the response_error signal or not */ + if (ptr != 0) + { + if ((*ptr) == conf->node_attribute->response_error) + { + /* Clear error signal in frame data buffer */ + *(conf->error_in_response) = 0; + lin_update_err_signal(iii, frame_index); + } + } + lin_update_word_status_lin21 (iii, LIN_LLD_TX_COMPLETED, pid); +#else + #if (LIN_PROTOCOL == PROTOCOL_J2602) + if (0x3D != pid) + { + node_att_ptr = conf->node_attribute; + *(conf->error_in_response) = 0; + for (i = 0; i < node_att_ptr->num_frame_have_esignal; i++) + { + byte_offset_temp_ptr = node_att_ptr->response_error_byte_offset_ptr + i; + bit_offset_temp_ptr = node_att_ptr->response_error_bit_offset_ptr + i; + /* Clear error signal in frame data buffer */ + lin_pFrameBuf[*byte_offset_temp_ptr] = (l_u8)(lin_pFrameBuf[*byte_offset_temp_ptr] & (~(0x07U << (*bit_offset_temp_ptr)))); + } + } + #else + ptr = (l_signal_handle *)lin_frame_tbl[frame_index].frame_data; + /* Check frame contain the response_error signal or not */ + if (ptr != 0) + { + if (*ptr == conf->node_attribute->response_error) + { + /* Clear error signal in frame data buffer */ + *(conf->error_in_response) = 0; + lin_update_err_signal(iii, frame_index); + } + } + #endif/* End of LIN_PROTOCOL == PROTOCOL_J2602 */ + lin_update_word_status_j2602 (iii, LIN_LLD_TX_COMPLETED, pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + } +} + +void lin_handle_error +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] event id */ + lin_lld_event_id event_id, + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u8 i; + l_u8 frame_index; + const lin_configuration *conf; + + conf = &(lin_ifc_configuration[iii]); + frame_index = lin_get_frame_index(iii, pid); + switch (event_id) + { + /* PID error */ + case LIN_LLD_PID_ERR: + /* do nothing here */ + break; + /* Frame error */ + case LIN_LLD_FRAME_ERR: + case LIN_LLD_CHECKSUM_ERR: + case LIN_LLD_READBACK_ERR: + case LIN_LLD_NODATA_TIMEOUT: + if (LIN_FRM_EVNT == conf->frame_tbl[frame_index].frm_type) + { + if(conf->function == _MASTER_) + { + lin_lld_set_etf_collision_flag(iii); + } + } + else + { + *(conf->error_in_response) = 1; + /* TL support */ + if ((0x3C == pid) || (0x3D == pid)) + { + /* multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_handler_error(iii, pid); + #else /* single frame support */ + lin_tl_no_response(iii); + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + } + } + break; + default: + break; + } + + /* Update word status */ + if (_SLAVE_ == conf->function) + { + #if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_err_signal(iii, frame_index); + lin_update_word_status_lin21 (iii, event_id, pid); + #else + #if (LIN_PROTOCOL == PROTOCOL_J2602) + lin_update_status_byte(iii, event_id); + #else + lin_update_err_signal(iii, frame_index); + #endif/* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + lin_update_word_status_j2602 (iii, event_id, pid); + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + } +} + +void lin_bus_activity_timeout +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid +) +{ + const lin_configuration *conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + if (_SLAVE_ == conf->function) + { + #if (LIN_PROTOCOL == PROTOCOL_21) + lin_update_word_status_lin21 (iii, LIN_LLD_BUS_ACTIVITY_TIMEOUT, pid); + #else + lin_update_word_status_j2602 (iii, LIN_LLD_BUS_ACTIVITY_TIMEOUT, pid); + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + } + /* Change to low power mode */ + lin_lld_set_low_power_mode(iii); +} + +void lin_switch_sch_table +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + /* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + l_u8 tmp_sch_id; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + const lin_configuration *conf; + l_u8 *_active_schedule_id; + l_u8 *_previous_schedule_id; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + _active_schedule_id = conf->active_schedule_id; + _previous_schedule_id = conf->previous_schedule_id; + switch(conf->schedule_tbl[*(conf->active_schedule_id)].sch_tbl_type) + { + /* Collision */ + case LIN_SCH_TBL_COLL: + /* Set active table equal to previous table */ + *_active_schedule_id = *_previous_schedule_id; + break; + /* Diagnostic schedule table */ + case LIN_SCH_TBL_DIAG: + /* single frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + if (DIAG_INTER_LEAVE_MODE == conf->diagnostic_mode) + { + /* Swap schedule table */ + /* SWAP_PTR(conf->active_schedule_id, conf->previous_schedule_id, tmp_sch_id); */ + tmp_sch_id = *_active_schedule_id; + *_active_schedule_id = *_previous_schedule_id; + *_previous_schedule_id = tmp_sch_id; + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + /* Set start entry of active schedule table to 0 */ + conf->schedule_start_entry[*_active_schedule_id] = 0; + break; + /* Normal schedule table */ + case LIN_SCH_TBL_NORM: + /* multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if (DIAG_INTER_LEAVE_MODE == *conf->diagnostic_mode) + { + *_previous_schedule_id = *_active_schedule_id; + *_active_schedule_id = conf->schedule_start+3; + } + #else /* single frame support */ + if (*(conf->diagnostic_frame_to_send) > 0 ) + { + /* Swap schedule table */ + /* SWAP_PTR(conf->active_schedule_id, conf->previous_schedule_id, tmp_sch_id); */ + tmp_sch_id = *_active_schedule_id; + *_active_schedule_id = *_previous_schedule_id; + *_previous_schedule_id = tmp_sch_id; + } + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Set start entry of active schedule table to 0 */ + conf->schedule_start_entry[*_active_schedule_id] = 0; + break; + /* Goto sleep schedule table */ + case LIN_SCH_TBL_GOTO: + /* Switch to NULL_SCHEDULE_TABLE */ + /* In the lin_sch_table, the NULL_SCHEDULE_TABLE for interface iii */ + /* is located at shedule_start */ + *_active_schedule_id = conf->schedule_start; + conf->schedule_start_entry[*_active_schedule_id] = 0; + break; + default: + break; + } +} + +l_u8 lin_check_sporadic_update +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] index of frame */ + l_frame_handle frm_id +) +{ + l_u8 associate_frame_offset = 0U; + l_u16 flag_offset = 0U; + l_u8 flag_size = 0U; + l_u8 i = 0U; + l_u8 j; + lin_associate_frame_struct *ptr; + const lin_configuration *conf; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + ptr = (lin_associate_frame_struct*)(conf->frame_tbl[frm_id].frame_data); + /* Check associate frame */ + for (j = 0; j < ptr->num_asct_uncn_pid; j++) + { + associate_frame_offset = (l_u8)ptr->act_uncn_frm[j]; + flag_offset = conf->frame_tbl[associate_frame_offset].flag_offset; + flag_size = conf->frame_tbl[associate_frame_offset].flag_size; + + for (i = 0U; i < flag_size; i++) + { + if (lin_flag_handle_tbl[flag_offset++] != 0xFFU) + { + /* Frame is updated, return the PID of associate updated frame */ + return conf->configuration_RAM[ptr->act_uncn_frm[j] - conf->frame_start+1]; + } + } + } + /* There's no updated frame */ + return 0xFF; +} + +void lin_update_tx_flags +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] index of frame */ + l_u8 frm_id +) +{ + l_u16 flag_offset; + l_u8 flag_size, i; + l_u8 associate_frame; + const lin_configuration *conf; + const lin_frame_struct *lin_frame_ptr; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + lin_frame_ptr = &(lin_frame_tbl[frm_id]); + + /* check event trigger frame and clear flag */ + if (LIN_FRM_EVNT == conf->frame_tbl[frm_id].frm_type) + { + associate_frame = (l_u8)(*(((lin_associate_frame_struct*)(lin_frame_ptr->frame_data))->act_uncn_frm)); + flag_offset = conf->frame_tbl[associate_frame].flag_offset; + flag_size = conf->frame_tbl[associate_frame].flag_size; + /* Update transmit flags */ + for (i = 0; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset] = 0xFF; + flag_offset++; + } + } + else if (LIN_FRM_DIAG != lin_frame_tbl[frm_id].frm_type) + { + flag_offset = lin_frame_tbl[frm_id].flag_offset; + flag_size = lin_frame_tbl[frm_id].flag_size; + /* Update transmit flags */ + for (i = 0; i < flag_size; i++) + { + lin_flag_handle_tbl[flag_offset++] = 0xFF; + } + } + + /* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + /* TL support */ + /* Check if Diagnostic Frame */ + else + { + lin_tl_update_tx_flag(iii); + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void lin_update_rx_diag_frame +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid +) +{ + l_u8 i, j; + const lin_configuration *conf; + + conf = &(lin_ifc_configuration[iii]); + + /* Update diagnostic signals */ + j = (pid - 0x3C) << 3; + + /* Check goto sleep */ + if (0x00 == conf->response_buffer[1]) + { + (*conf->goto_sleep_flg) = 1; + lin_lld_set_low_power_mode(iii); + return; + } + for (i = 1; i < 9; i++, j++) + { + /* Update corresponding signals */ + conf->diag_signal_tbl[j] = conf->response_buffer[i]; + } + /* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + /* TL support */ + /* Copy response to diagnostic PDU in TL */ + lin_tl_put_pdu(iii); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + /* Process PDU income */ + lin_tl_handler(iii); + +} + +void lin_make_res_diag_frame +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID of frame */ + l_u8 pid +) +{ + //const lin_configuration *conf; + /* Get current configuration */ + //conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + + lin_tl_get_pdu(iii); +} + +l_u8 lin_get_frame_index +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID of frame */ + l_u8 pid +) +{ + l_u8 i; + const lin_configuration *conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + for (i = conf->num_of_frames; 0 < i; i--) + { + if (conf->configuration_RAM[i] == pid) + { + return (i + conf->frame_start - 1); + } + } + return 0xFF; +} + +void lin_process_uncd_frame +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID to process */ + l_u8 pid, + /* [IN] make or update */ + l_u8 type +) +{ + l_u8 frame_index, *response_buffer_ptr; + l_u16 frame_byte_offset; + l_u8 flag, i; + + const lin_configuration *conf; + conf = &(lin_ifc_configuration[iii]); + + frame_index = lin_get_frame_index(iii, pid); + + if (0xFF != frame_index) + { + response_buffer_ptr = conf->response_buffer; + + /* Set frame length */ + response_buffer_ptr[0] = lin_frame_tbl[frame_index].frm_len; + frame_byte_offset = lin_frame_tbl[frame_index].frm_offset; + + if (MAKE_UNCONDITIONAL_FRAME == type) + { + /* get data from lin frame buffer */ + flag = lin_frame_updating_flag_tbl[frame_index]; + + for (i = 1; i < response_buffer_ptr[0]+1; i++, frame_byte_offset++) + { + if(flag & (1<<(i-1))) + { + response_buffer_ptr[i] = buffer_backup_data[i-1]; + } + else + { + response_buffer_ptr[i] = lin_pFrameBuf[frame_byte_offset]; + } + } + } + else + { + for (i = 1; i < response_buffer_ptr[0]+1; i++, frame_byte_offset++) + { + lin_pFrameBuf[frame_byte_offset] = response_buffer_ptr[i]; + } + } + } +} +#endif /* End of (LIN_MODE == _MASTER_MODE_) */ +/** +* @} + */ diff --git a/LIN_Stack/coreapi/lin_j2602_api.c b/LIN_Stack/coreapi/lin_j2602_api.c new file mode 100644 index 0000000..562923f --- /dev/null +++ b/LIN_Stack/coreapi/lin_j2602_api.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup J2602_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602_api.c +* +* @author FPT Software +* +* @brief J2602 LIN core API functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +#include "lin_j2602_api.h" + +l_bool l_ifc_connect +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + return 0; +} + +l_bool l_ifc_disconnect +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + return 0; +} +/** +* @} + */ diff --git a/LIN_Stack/coreapi/lin_j2602_proto.c b/LIN_Stack/coreapi/lin_j2602_proto.c new file mode 100644 index 0000000..e22e6f9 --- /dev/null +++ b/LIN_Stack/coreapi/lin_j2602_proto.c @@ -0,0 +1,210 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup J2602_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602_proto.c +* +* @author FPT Software +* +* @brief J2602 LIN protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +#include "lin_j2602_proto.h" + +/* ---------------------------- For 1 interface -----------------------------------*/ +#if LIN_MODE == _SLAVE_MODE_ +#if LIN_PROTOCOL != PROTOCOL_21 + +void lin_update_word_status_j2602 +( + /* [IN] event of Low-level driver */ + lin_lld_event_id event_id, + /* [IN] PID of frame */ + l_u8 pid +) +{ + l_u8 overrun = 0; + if((lin_word_status.word & 0x03) > 0) + { + overrun |= lin_successful_transfer | lin_error_in_response; + } + lin_word_status.word |= ((lin_error_in_response) | (lin_successful_transfer << 1) | + (overrun << 2) | (lin_goto_sleep_flg << 3)); + lin_word_status.word = (lin_word_status.word & 0x00FF) | (pid << 8); + + lin_successful_transfer = 0; +} + +void lin_update_status_byte +( + /* [IN] interface name */ + lin_lld_event_id event_id +) +{ + l_u8 i; + l_u8 signal_data; + l_u16 byte_offset_temp; + l_u8 bit_offset_temp; + l_bool set_error_signal = 0; + switch (event_id) + { + /* Parity error */ + case LIN_LLD_PID_ERR: + /* Set ID Parity Error 0x07 */ + signal_data = 0x07; + set_error_signal = 1; + break; + /* Byte Field Framing Error*/ + case LIN_LLD_FRAME_ERR: + /* Set Byte Field Framing Error 0x06 */ + signal_data = 0x06; + set_error_signal = 1; + break; + /* Checksum error */ + case LIN_LLD_CHECKSUM_ERR: + /* Set Checksum error 0x05 */ + signal_data = 0x05; + set_error_signal = 1; + break; + /* Data error */ + case LIN_LLD_READBACK_ERR: + /* Set Data error 0x04 */ + signal_data = 0x04; + set_error_signal = 1; + break; + default: + break; + } + + if (set_error_signal == 1) + { + for (i = 0; i < num_frame_have_esignal; i++) + { + /* Get pointer to Byte and bit offset values in each frame that contains the error signal */ + byte_offset_temp = lin_response_error_byte_offset[i]; + bit_offset_temp = lin_response_error_bit_offset[i]; + /* Set error signal equal to error in response */ + lin_pFrameBuf[byte_offset_temp] = (l_u8)((lin_pFrameBuf[byte_offset_temp] & (~(0x07U << bit_offset_temp))) | + (signal_data << bit_offset_temp)); + } + } +} +#endif /* End (LIN_PROTOCOL != PROTOCOL_21) */ +#endif /* End of (LIN_MODE == _SLAVE_MODE_)*/ + +/*-----------------------------------------------------------------------*/ +#if LIN_MODE == _MASTER_MODE_ + +void lin_update_word_status_j2602 +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] event of Low-level driver */ + lin_lld_event_id event_id, + /* [IN] PID of frame */ + l_u8 pid +) +{ + l_u8 err_in_res, suc_in_tras; + lin_word_status_str *word_status; + lin_configuration const *conf; + + conf = &(lin_ifc_configuration[iii]); + err_in_res = *(conf->error_in_response); + suc_in_tras = *(conf->successful_transfer); + + word_status = conf->word_status; + word_status->bit.error_in_res = err_in_res; + if((word_status->word & 0x03) > 0) + { + word_status->bit.overrun |= (err_in_res | suc_in_tras); + } + word_status->bit.successful_transfer = suc_in_tras; + word_status->bit.last_pid = pid; + word_status->bit.gotosleep = *(conf->goto_sleep_flg); + + *(conf->successful_transfer) = 0; +} + +void lin_update_status_byte +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] interface name */ + lin_lld_event_id event_id +) +{ + l_u8 i; + l_u8 signal_data; + l_u16* byte_offset_temp_ptr; + l_u8* bit_offset_temp_ptr; + lin_node_attribute *node_att_ptr; + l_bool set_error_signal = 0; + lin_configuration const *conf; + + conf = &(lin_ifc_configuration[iii]); + switch (event_id) + { + /* Parity error */ + case LIN_LLD_PID_ERR: + /* Set ID Parity Error 0x07 */ + signal_data= 0x07; + set_error_signal = 1; + break; + /* Byte Field Framing Error*/ + case LIN_LLD_FRAME_ERR: + /* Set Byte Field Framing Error 0x06 */ + signal_data = 0x06; + set_error_signal = 1; + break; + /* Checksum error */ + case LIN_LLD_CHECKSUM_ERR: + /* Set Checksum error 0x05 */ + signal_data = 0x05; + set_error_signal = 1; + break; + /* Data error */ + case LIN_LLD_READBACK_ERR: + /* Set Data error 0x04 */ + signal_data = 0x04; + set_error_signal = 1; + break; + default: + break; + } + + if (set_error_signal == 1) + { + node_att_ptr = conf->node_attribute; + for (i = 0; i < node_att_ptr->num_frame_have_esignal; i++) + { + /* Get pointer to Byte and bit offset values in each frame that contains the error signal */ + byte_offset_temp_ptr = node_att_ptr->response_error_byte_offset_ptr + i; + bit_offset_temp_ptr = node_att_ptr->response_error_bit_offset_ptr + i; + /* Set error signal equal to error in response */ + lin_pFrameBuf[*byte_offset_temp_ptr] = (l_u8)((lin_pFrameBuf[*byte_offset_temp_ptr] & (~(0x07U << (*bit_offset_temp_ptr)))) | + (signal_data << (*bit_offset_temp_ptr))); + } + } +} +#endif /* End of (LIN_MODE == _SLAVE_MODE_)*/ +/** +* @} +*/ diff --git a/LIN_Stack/coreapi/lin_lin21_api.c b/LIN_Stack/coreapi/lin_lin21_api.c new file mode 100644 index 0000000..1e44c23 --- /dev/null +++ b/LIN_Stack/coreapi/lin_lin21_api.c @@ -0,0 +1,33 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup LIN21_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_lin21_api.c +* +* @author FPT Software +* +* @brief Common LIN 2.1 API functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +#include "lin_lin21_api.h" + +/** + * @} + */ \ No newline at end of file diff --git a/LIN_Stack/coreapi/lin_lin21_proto.c b/LIN_Stack/coreapi/lin_lin21_proto.c new file mode 100644 index 0000000..483b2ad --- /dev/null +++ b/LIN_Stack/coreapi/lin_lin21_proto.c @@ -0,0 +1,300 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup LIN21_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_lin21_proto.c +* +* @author FPT Software +* +* @brief Common LIN 2.1 protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * 20111005 v1.1 Updated word status + * + *****************************************************************************/ + +#include "lin_lin21_proto.h" +#include "lin_common_proto.h" +#include "lin.h" + + +/* ---------------------------- For 1 interface ----------------------------------- */ +#if (LIN_MODE == _SLAVE_MODE_) +#if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) +#if !defined(MCU_SKEAZN84) /* Not cover for KEA8 platform */ +extern l_u8 frame_index; + + +void lin_update_word_status_lin21 +( + /* [IN] PID of frame */ + l_u8 pid +) +{ + l_u8 overrun = 0; + if((lin_word_status.word & 0x03) > 0) + { + overrun |= lin_successful_transfer | lin_error_in_response; + } + lin_word_status.word |= ((lin_error_in_response) | (lin_successful_transfer << 1) | + (overrun << 2)| + (lin_goto_sleep_flg << 3) | + (lin_save_configuration_flg << 6)); + if(pid != 0xff) + { + lin_word_status.word = (lin_word_status.word & 0x00FF) | (pid << 8); + /* Set bus activity */ + lin_word_status.word |= 1 << 4; + } + + lin_successful_transfer = 0; +} + + + +void lin_update_err_signal +( + /* [IN] index of frame */ + l_u8 frm_id +) +{ + l_u8 i; + l_u16 byte_offset_temp; + l_u8 bit_offset_temp; + /* Set error signal equal to error in response */ + if (LIN_FRM_EVNT != lin_frame_tbl[frm_id].frm_type) + { + for (i = 0; i < num_frame_have_esignal; i++) + { + byte_offset_temp = lin_response_error_byte_offset[i]; + bit_offset_temp = lin_response_error_bit_offset[i]; + lin_pFrameBuf[byte_offset_temp] = (l_u8)((lin_pFrameBuf[byte_offset_temp] & (~(1U << (bit_offset_temp)))) | + (lin_error_in_response << (bit_offset_temp))); + } + } +} +void lin_make_res_evnt_frame +( + /* [IN] PID of frame */ + l_u8 pid +) +{ + /* Create response */ + lin_process_uncd_frame(pid, MAKE_UNCONDITIONAL_FRAME); + lin_lld_response_buffer[1] = lin_process_parity(pid, MAKE_PARITY); +} + +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ +#endif /* #if !defined(MCU_SKEAZN84) */ + +#endif /* End of (LIN_MODE == _SLAVE_MODE_) */ + +/* ------------------------ FOR MULTI-INTERFACE -------------------------- */ +#if (LIN_MODE == _MASTER_MODE_) + +void lin_collision_resolve +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID of frame */ + l_u8 pid +) +{ + lin_associate_frame_struct *ptr; + l_u8 frame_index; + const lin_configuration *conf; + l_u8 *_active_schedule_id; + + conf = &(lin_ifc_configuration[iii]); + frame_index = lin_get_frame_index(iii, pid); + /* Check MASTER function */ + if (_MASTER_ == conf->function) + { + /* Find collision resolver table */ + /* Swap schedule table */ + /* Get active_schedule_id */ + _active_schedule_id = conf->active_schedule_id; + *(conf->previous_schedule_id) = *_active_schedule_id ; + + /* Set collision resolver table to active schedule */ + ptr = (lin_associate_frame_struct*)conf->frame_tbl[frame_index].frame_data; + + *_active_schedule_id = ptr->coll_resolver_id; + + conf->schedule_start_entry[*_active_schedule_id] = 0; + } +} + +void lin_update_word_status_lin21 +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] event of Low-level driver */ + lin_lld_event_id event_id, + /* [IN] PID of frame */ + l_u8 pid +) +{ + + l_u8 err_in_res, suc_in_tras, frame_index, save_config; + lin_word_status_str *word_status_ptr; + const lin_configuration *conf; + + conf = &(lin_ifc_configuration[iii]); + err_in_res = *(conf->error_in_response); + suc_in_tras = *(conf->successful_transfer); + save_config = lin_save_configuration_flg[iii]; + + word_status_ptr = conf->word_status; + if((word_status_ptr->word & 0x03) > 0) + { + word_status_ptr->bit.overrun |= err_in_res | suc_in_tras; + } + word_status_ptr->bit.error_in_res |= err_in_res; + word_status_ptr->bit.successful_transfer |= suc_in_tras; + if(pid != 0xff) + { + word_status_ptr->bit.last_pid = pid; + } + if(LIN_LLD_BUS_ACTIVITY_TIMEOUT != event_id) + { + /* Set bus activity timeout */ + word_status_ptr->bit.bus_activity = 1U; + } + + if (_MASTER_ == conf->function) + { + /* For Master node */ + word_status_ptr->bit.gotosleep = *(conf->goto_sleep_flg); + /* If is Master node, value always equal 0 */ + word_status_ptr->bit.save_conf = 0; + + frame_index = lin_get_frame_index(iii, pid); + if (0xFF == frame_index) /* This PID doesn't belong to this node */ + { + /* Error */ + return; + } + + /* PID belongs to this node, then check type of frame */ + if (LIN_SCH_TBL_COLL == conf->schedule_tbl->sch_tbl_type) + { + word_status_ptr->bit.etf_collision = 1; + } + else + { + word_status_ptr->bit.etf_collision = 0; + } + } + else + { + /* For Slave node */ + word_status_ptr->bit.gotosleep = *(conf->goto_sleep_flg); + word_status_ptr->bit.etf_collision = 0; + /* Updated save configuration value to word status */ + word_status_ptr->bit.save_conf = save_config; + word_status_ptr->bit.dummy = 0; + } +} + + +void lin_update_err_signal +( + /* [IN] interface name */ + l_ifc_handle iii, + l_u8 frm_id +) +{ + const lin_configuration *conf; + l_u8 i; + l_u16* byte_offset_temp_ptr; + l_u8* bit_offset_temp_ptr; + l_u8 err_in_res; + lin_node_attribute *node_att_ptr; + + conf = &(lin_ifc_configuration[iii]); + node_att_ptr = conf->node_attribute; + err_in_res = *(conf->error_in_response); + /* Set error signal equal to error in response */ + if (LIN_FRM_EVNT != conf->frame_tbl[frm_id].frm_type) + { + for (i = 0; i < node_att_ptr->num_frame_have_esignal; i++) + { + byte_offset_temp_ptr = &node_att_ptr->response_error_byte_offset_ptr[i]; + bit_offset_temp_ptr = &node_att_ptr->response_error_bit_offset_ptr[i]; + lin_pFrameBuf[*byte_offset_temp_ptr] = (l_u8)((lin_pFrameBuf[*byte_offset_temp_ptr] & (~(1U << (*bit_offset_temp_ptr)))) | + (err_in_res << (*bit_offset_temp_ptr))); + } + } +} + +void lin_update_rx_evnt_frame +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID of frame */ + l_u8 pid +) +{ + lin_associate_frame_struct *ptr; + l_u8 frame_index, i, ass_pid; + const lin_configuration *conf; + + conf = &(lin_ifc_configuration[iii]); + /* Get frame index of the eventrigger frame */ + frame_index = lin_get_frame_index(iii, pid); + + if (0xFF != frame_index) /* This PID doesn't belong to this node */ + { + + /* calculate PID that associated with ETF */ + ass_pid = lin_process_parity(conf->response_buffer[1], CHECK_PARITY); + ptr = (lin_associate_frame_struct*)(conf->frame_tbl[frame_index].frame_data); + + for (i = 0; i < ptr->num_asct_uncn_pid; i++ ) + { + /* First byte of response for event trigger is the PID of the associate frame */ + if (conf->configuration_RAM[ptr->act_uncn_frm[i] - conf->frame_start + 1] == ass_pid ) + { + /* Update unconditional frame */ + lin_process_uncd_frame(iii, ass_pid, UPDATE_UNCONDITIONAL_FRAME); + /* break; */ + i = ptr->num_asct_uncn_pid; + } + } + } + /* error */ + return; +} + +void lin_make_res_evnt_frame +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] PID of frame */ + l_u8 pid +) +{ + /* Create response */ + lin_process_uncd_frame(iii, pid, MAKE_UNCONDITIONAL_FRAME); + /* Set associate PID */ + lin_ifc_configuration[iii].response_buffer[1] = lin_process_parity(pid, MAKE_PARITY); +} +#endif /* End of (LIN_MODE == _MASTER_MODE_) */ +/** + * @} + */ diff --git a/LIN_Stack/diagnostic/lin_diagnostic_service.c b/LIN_Stack/diagnostic/lin_diagnostic_service.c new file mode 100644 index 0000000..7c44532 --- /dev/null +++ b/LIN_Stack/diagnostic/lin_diagnostic_service.c @@ -0,0 +1,689 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup diagnostic_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_diagnostic_service.c +* +* @author FPT Software +* +* @brief Diagnostic Service slave functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090718 v1.0 First version + * 20111005 v1.1 Updated diagnostics service + * + *****************************************************************************/ + +#include "lin_commontl_proto.h" +#include "lin_diagnostic_service.h" + +/* Define functionality */ +#ifndef MULTI_PDU_SUPPORT +#define MULTI_PDU_SUPPORT 0 /**< multi PDU support */ +#endif /* End MULTI_PDU_SUPPORT */ + +/********------------- Code supports SINGLE interface ----------------**********/ +#if LIN_MODE == _SLAVE_MODE_ +/*************************** FUNCTIONS *******************/ +/* Unuse for GPIO */ +#if ( _LIN_GPIO_ == 0 ) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) +#if LIN_PROTOCOL == PROTOCOL_21 + +void lin_diagservice_assign_frame_id() +{ + l_u16 supid, msg_id,pid,current_id; + lin_tl_pdu_data *lin_tl_pdu; +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u16 length; + l_u8 data[10]; + /* get pdu from rx queue */ + ld_receive_message(&length, data+2); + lin_tl_pdu = (lin_tl_pdu_data *)data; +#else /* Single frame support */ + lin_tl_pdu = tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + supid = (l_u16)(((*lin_tl_pdu)[4]) << 8); + supid = supid |(l_u16)((*lin_tl_pdu)[3]); + //product_id.supplier_id = supid; + + msg_id = (l_u16)(((*lin_tl_pdu)[6]) << 8); + msg_id = msg_id |(l_u16)((*lin_tl_pdu)[5]); + //product_id.function_id = fid; + + pid = (*lin_tl_pdu)[7]; + current_id = lin_process_parity(pid,CHECK_PARITY); + + if(supid==0x0B00 || supid==0x7FFF){//iav测试台架发的spid与软件定义spid，高位低位相反，目前直接写死 + if(msg_id==0x5001){ + lin_configuration_RAM[1]= current_id; + lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_FRAME_ID, POSITIVE, 0); + } + else if(msg_id==0x5000){ + lin_configuration_RAM[2]= current_id; + lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_FRAME_ID, POSITIVE, 0); + } + } +} + + +void lin_diagservice_assign_frame_id_range() +{ + l_u8 start_index; + l_s8 j, i = 7; + lin_tl_pdu_data *lin_tl_pdu; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u16 length; + l_u8 data[10]; + /* get pdu from rx queue */ + ld_receive_message(&length, data+2); + lin_tl_pdu = (lin_tl_pdu_data *)data; +#else /* Single frame support */ + lin_tl_pdu = tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Get start index in request */ + start_index = (*lin_tl_pdu)[3]; + +// for (i = 7, j = start_index+4; j > start_index; i--, j-- ) +// { +// if ((0xFF != (*lin_tl_pdu)[i]) && (j > LIN_CFG_FRAME_NUM)) +// { +// lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_FRAME_ID_RANGE, NEGATIVE, GENERAL_REJECT); +// return; +// } +// } + +// /* Store PIDs */ +// for (i = 4, j = start_index + 1; i < 8; i++, j++) +// { +// switch ((*lin_tl_pdu)[i]) +// { +// case 0x00: +// /* Unassign frame */ +// lin_configuration_RAM[j] = 0xFF; +// break; + +// case 0xFF: +// /* keep the previous assigned value of this frame */ +// break; + +// default: +// /* Calculate frame ID & Assign ID to frame */ +// lin_configuration_RAM[j] = lin_process_parity((*lin_tl_pdu)[i], CHECK_PARITY); +// break; +// } +// } /* End of for statement */ + + lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_FRAME_ID_RANGE, POSITIVE, 0); +} + +void lin_diagservice_read_by_identifier() +{ + l_u8 id; + l_u16 supid, fid; + lin_tl_pdu_data *lin_tl_pdu; + + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u16 length; + l_u8 data[10]; + /* get pdu from rx queue */ + ld_receive_message(&length, data+2); + lin_tl_pdu = (lin_tl_pdu_data *)data; +#else /* Single frame support */ + lin_tl_pdu = tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + //20200801:ȫ���ظ�����Ӧ + //lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, POSITIVE, 0); + //return; + + /* Get supplier and function indentification in request */ + supid = (l_u16)(((*lin_tl_pdu)[5]) << 8); + supid = supid |(l_u16)((*lin_tl_pdu)[4]); + + fid = (l_u16)(((*lin_tl_pdu)[7]) << 8); + fid = fid |(l_u16)((*lin_tl_pdu)[6]); + + +// /* Check Supplier ID and Function ID */ +// if (((supid != product_id.supplier_id) && (supid != LD_ANY_SUPPLIER)) || \ +// ((fid != product_id.function_id) && (fid != LD_ANY_FUNCTION))) +// { +// tl_slaveresp_cnt = 0; +// #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +// tl_service_status = LD_SERVICE_IDLE; +// #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +// return; +// } + id = (*lin_tl_pdu)[3]; + + switch (id) + { + case LIN_PRODUCT_IDENT: + if((supid==0x0B00 || supid==0x7FFF) && (fid==product_id.function_id || fid==0xFFFF))//iav测试台架发的spid与软件定义spid，高位低位相反，目前直接写死 + { + lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, POSITIVE, 0); + } + break; + case SERIAL_NUMBER: + lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, POSITIVE, 1); + break; + default: + if (id >= LIN_READ_USR_DEF_MIN && id <= LIN_READ_USR_DEF_MAX) + { + lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, POSITIVE, id); + break; + //��֪��ΪʲôҪ���� + // l_u8 data_callout[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + // l_u8 i; + // l_u8 retval = ld_read_by_id_callout(id, data_callout); + // /*If the User ID is supported, make positive response*/ + // if (retval == LD_POSITIVE_RESPONSE) + // { + // for (i =0; i <5; i++) + // { + // if (data_callout[i] != 0xFF) + // { + // lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, POSITIVE, id); + // break; + // } + // /* If all data_callout is 0xFF, then make negative response*/ + // if (i == 4) + // { + // /* Make a negative slave response PDU */ + // lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + // } + + // } + // } + // else if (retval == LD_NEGATIVE_RESPONSE) + // /*If the User ID is not supported, make negative response*/ + // { + // /* Make a negative slave response PDU */ + // lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + // } + // else if (retval == LD_ID_NO_RESPONSE) + // { + // /*Do not answer*/ + // tl_slaveresp_cnt = 0; + // #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + // tl_service_status = LD_SERVICE_IDLE; + // #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + // } + + } + else + { + /* Make a negative slave response PDU */ + lin_tl_make_slaveres_pdu(SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + } + break; + } /* End of switch */ +} + +void lin_condittional_change_nad() +{ + l_u8 id, byte, mask, invert; +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + id = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][3]; + byte = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][4]; + mask = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][5]; + invert = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][6]; +#else /* Single frame support */ + id = (*tl_current_rx_pdu_ptr)[3]; + byte = (*tl_current_rx_pdu_ptr)[4]; + mask = (*tl_current_rx_pdu_ptr)[5]; + invert = (*tl_current_rx_pdu_ptr)[6]; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Possible positive ID */ + if (id == 0) + { + if(byte>0 && byte<6) + { + /*Byte 1: Supplier ID LSB; Byte 2: Supplier ID MSB*/ + if(byte>0 && byte<3) + { + byte = product_id.supplier_id >> ((byte-1)*8); + } + /*Byte 3: Function ID LSB; Byte 4: Function ID MSB*/ + else if(byte>2 && byte<5) + { + byte = product_id.function_id >> ((byte-3)*8); + } + /* Byte 5: Variant */ + else + { + byte = product_id.variant; + } + /* Do a bitwise XOR with Invert and Do a bitwise AND with Mask */ + byte = (byte^invert)&mask; + /* If the final result is zero, then give positive response*/ + if (byte == 0) + { + lin_tl_make_slaveres_pdu(SERVICE_CONDITIONAL_CHANGE_NAD, POSITIVE, 0); + /* If the final result is zero then change the NAD to New NAD */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_configured_NAD = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][7]; + #else/* Single frame support */ + lin_configured_NAD = (*tl_current_rx_pdu_ptr)[7]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + } + } + } +} + +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ +#endif /* End ( _LIN_GPIO_ == 0 ) && !defined(_MC9S08SC4_H) */ + + +#if LIN_PROTOCOL == PROTOCOL_21 +/* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +void lin_diagsrv_functional_service(void) +{ + l_u16 length; + l_u8 data[10]; + /* get pdu from rx queue */ + ld_receive_message(&length, data); + + /* do something here */ +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + +#if LIN_PROTOCOL == PROTOCOL_J2602 +void lin_diagservice_target_reset() +{ + l_u8 *signal_data_ptr; + l_u8 nad; + lin_tl_pdu_data *lin_tl_pdu; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu = (lin_tl_pdu_data *)&lin_lld_response_buffer[1]; +#else /* Single frame support */ + lin_tl_pdu = tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Set the reset flag within the J2602 Status Byte */ + /* Set error signal equal to error in response */ + lin_pFrameBuf[response_error_byte_offset] = (lin_pFrameBuf[response_error_byte_offset] & + (~(0x07 << response_error_bit_offset))) | + (0x01 << response_error_bit_offset); + + /* Create positive response */ + + /* Get NAD of node */ + nad = (*lin_tl_pdu)[0]; + + if (LD_BROADCAST != nad) + { + lin_tl_make_slaveres_pdu(SERVICE_TARGET_RESET, POSITIVE, 0); + } + else + { + tl_slaveresp_cnt = 0; + } +} +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +/********------------ End of code for SINGLE Interface --------------**********/ + + +/********------------- Code supports Multi interface ----------------**********/ +#if LIN_MODE == _MASTER_MODE_ +/*************************** FUNCTIONS *******************/ + + +#if LIN_PROTOCOL == PROTOCOL_21 + +void lin_diagservice_assign_frame_id_range +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration* conf; + l_s8 j, i = 0; + l_u8 start_index; + l_u8 cfg_frame_num = 0; + lin_tl_pdu_data *lin_tl_pdu; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u16 length; + l_u8 NAD, data[10]; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Do actions only for slave nodes */ + if (conf->function == _SLAVE_) + { + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* receive message data */ + ld_receive_message(iii, &length, &NAD, data+2); + + lin_tl_pdu = (lin_tl_pdu_data *)data; + #else /* Single frame support */ + /* Get current PDU pointer of RX queue */ + lin_tl_pdu = (lin_tl_pdu_data *)&conf->response_buffer[1]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Get start index in request */ + start_index = (*lin_tl_pdu)[3]; + + /* Find the number of configurable frame */ + i = 1; + while (0xFFFF != (conf->configuration_ROM)[i]) + { + i++; + cfg_frame_num++; + } + /* Check request validity */ + for (i = 7, j = start_index+4; j > start_index; i--, j-- ) + { + if ((0xFF != (*lin_tl_pdu)[i]) && (j > cfg_frame_num)) + { + lin_tl_make_slaveres_pdu(iii, SERVICE_ASSIGN_FRAME_ID_RANGE, NEGATIVE, GENERAL_REJECT); + return; + } + } + + /* Store PIDs */ + for (i = 4, j = 1; i < 8; i++, j++) + { + switch ((*lin_tl_pdu)[i]) + { + case 0x00: + /* Unassign frame */ + (conf->configuration_RAM)[start_index + j] = 0xFF; + break; + + case 0xFF: + /* keep the previous assigned value of this frame */ + break; + + default: + /* Calculate frame ID and Assign ID to frame */ + (conf->configuration_RAM)[start_index + j] = lin_process_parity((*lin_tl_pdu)[i], CHECK_PARITY); + break; + } + } /* End of for statement */ + lin_tl_make_slaveres_pdu(iii, SERVICE_ASSIGN_FRAME_ID_RANGE, POSITIVE, 0); + } +} + + +void lin_diagservice_read_by_identifier +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration* conf; + const lin_node_attribute* node_conf; + lin_product_id ident; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data *lin_tl_pdu; + l_u8 id; + l_u16 supid, fid; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu_data pdu_data; + l_u16 length; + l_u8 NAD, data[10]; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL description */ + tl_conf = conf->tl_desc; + + /* Do actions only for slave nodes */ + if (conf->function == _SLAVE_) + { + /* Multi frame support */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu = (lin_tl_pdu_data *)&pdu_data; + /* receive message data */ + ld_receive_message(iii, &length, &NAD, data+2); + + lin_tl_pdu = (lin_tl_pdu_data *)data; + #else /* Single frame support */ + lin_tl_pdu = (lin_tl_pdu_data *)&conf->response_buffer[1]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Get the node attribute */ + node_conf = conf->node_attribute; + + /* Get the product identification */ + ident = node_conf->product_id; + + /* Get supplier and function indentification in request */ + supid = (l_u16)(((*lin_tl_pdu)[5]) << 8); + supid = supid |(l_u16)((*lin_tl_pdu)[4]); + + fid = (l_u16)(((*lin_tl_pdu)[7]) << 8); + fid = fid |(l_u16)((*lin_tl_pdu)[6]); + + + /* Check Supplier ID and Function ID */ + if (((supid != ident.supplier_id) && (supid != LD_ANY_SUPPLIER)) || \ + ((fid != ident.function_id) && (fid != LD_ANY_FUNCTION))) + { + tl_conf->tl_slaveresp_cnt = 0; + return; + } + + /* Get the identifier of request */ + id = (*lin_tl_pdu)[3]; + + switch (id) + { + case LIN_PRODUCT_IDENT: + lin_tl_make_slaveres_pdu(iii, SERVICE_READ_BY_IDENTIFY, POSITIVE, 0); + break; + case SERIAL_NUMBER: + lin_tl_make_slaveres_pdu(iii, SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + break; + + default: + if (id >= LIN_READ_USR_DEF_MIN && id <= LIN_READ_USR_DEF_MAX) + { + l_u8 data_callout[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + l_u8 i; + l_u8 retval = ld_read_by_id_callout(iii,id, data_callout); + /*If the User ID is supported, make positive response*/ + if (retval == LD_POSITIVE_RESPONSE) + { + for (i =0; i <5; i++) + { + if (data_callout[i] != 0xFF) + { + lin_tl_make_slaveres_pdu(iii,SERVICE_READ_BY_IDENTIFY, POSITIVE, id); + break; + } + /* If all data_callout is 0xFF, then make negative response*/ + if (i == 4) + { + /* Make a negative slave response PDU */ + lin_tl_make_slaveres_pdu(iii,SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + } + + } + } + else if (retval == LD_NEGATIVE_RESPONSE) + /*If the User ID is not supported, make negative response*/ + { + /* Make a negative slave response PDU */ + lin_tl_make_slaveres_pdu(iii,SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + } + else if (retval == LD_ID_NO_RESPONSE) + { + /*Do not answer*/ + tl_conf->tl_slaveresp_cnt = 0; + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + *conf->tl_service_status = LD_SERVICE_IDLE; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + } + } + else + { + /* Make a negative slave response PDU */ + lin_tl_make_slaveres_pdu(iii, SERVICE_READ_BY_IDENTIFY, NEGATIVE, SUBFUNCTION_NOT_SUPPORTED); + } + break; + } /* end of switch */ + } +} +/*FUNCTION********************************************************************** + * + * Function Name : lin_condittional_change_nad + * Description : + * + *END**************************************************************************/ +void lin_condittional_change_nad(l_ifc_handle iii) +{ + l_u8 id, byte, mask, invert; + const lin_configuration* conf; + lin_node_attribute* node_conf; + lin_tl_descriptor *tl_conf; +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_transport_layer_queue *rx_queue; +#else /* Single frame support */ + lin_tl_pdu_data *lin_tl_pdu; +#endif + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Do actions only for slave nodes */ + if (conf->function == _SLAVE_) + { + /* Get TL description */ + tl_conf = conf->tl_desc; + /* Get the node attribute */ + node_conf = conf->node_attribute; + + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* Get receive queue */ + rx_queue = tl_conf->tl_rx_queue; + id = rx_queue->tl_pdu[rx_queue->queue_header][3]; + byte = rx_queue->tl_pdu[rx_queue->queue_header][4]; + mask = rx_queue->tl_pdu[rx_queue->queue_header][5]; + invert = rx_queue->tl_pdu[rx_queue->queue_header][6]; + #else /* Single frame support */ + /* Get current PDU pointer of RX buffer */ + lin_tl_pdu = tl_conf->tl_current_rx_pdu_ptr; + id = (*lin_tl_pdu)[3]; + byte = (*lin_tl_pdu)[4]; + mask = (*lin_tl_pdu)[5]; + invert = (*lin_tl_pdu)[6]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Possible positive ID */ + /* Support only identifier 0 for LIN Product Identification */ + if (id == 0) + { + if(byte>0 && byte<6) + { + /*Byte 1: Supplier ID LSB; Byte 2: Supplier ID MSB*/ + if(byte>0 && byte<3) + { + byte = (node_conf->product_id).supplier_id >> ((byte-1)*8); + } + /*Byte 3: Function ID LSB; Byte 4: Function ID MSB*/ + else if(byte>2 && byte<5) + { + byte = (node_conf->product_id).function_id >> ((byte-3)*8); + } + /* Byte 5: Variant */ + else + { + byte = (node_conf->product_id).variant; + } + /* Do a bitwise XOR with Invert and Do a bitwise AND with Mask */ + byte = (byte^invert)&mask; + /* If the final result is zero, then give positive response*/ + if (byte == 0) + { + lin_tl_make_slaveres_pdu(iii,SERVICE_CONDITIONAL_CHANGE_NAD, POSITIVE, 0); + /* If the final result is zero then change the NAD to New NAD */ + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + node_conf->configured_NAD = rx_queue->tl_pdu[rx_queue->queue_header][7]; + #else/* Single frame support */ + node_conf->configured_NAD = (*lin_tl_pdu)[7]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + } + } + } + } +} +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + +#if LIN_PROTOCOL == PROTOCOL_J2602 +void lin_diagservice_target_reset +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data *pdu; + l_u8 byte_offset_temp, bit_offset_temp; + l_u8 nad; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* Get PDU from RX queue */ + + /* Get current PDU pointer of RX queue */ + pdu = (lin_tl_pdu_data *)&conf->response_buffer[1]; + + /* Set the reset flag within the J2602 Status Byte */ + byte_offset_temp = conf->node_attribute->response_error_byte_offset; + bit_offset_temp = conf->node_attribute->response_error_bit_offset; + + /* Set error signal equal to error in response */ + lin_pFrameBuf[byte_offset_temp] = (lin_pFrameBuf[byte_offset_temp] & + (~(0x07 << bit_offset_temp))) | + (0x01 << bit_offset_temp); + /* Create positive response */ + + /* Get NAD of node */ + nad = (*pdu)[0]; + + if (LD_BROADCAST != nad) + { + lin_tl_make_slaveres_pdu(iii, SERVICE_TARGET_RESET, POSITIVE, 0); + } + else + { + tl_conf->tl_slaveresp_cnt = 0; + } +} +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ +#endif /* End (LIN_MODE == _MASTER_MODE_) */ +/* ---------------- End of code for Multi Interface ----------------- */ +/** + * @} + */ diff --git a/LIN_Stack/include/lin_common_api.h b/LIN_Stack/include/lin_common_api.h new file mode 100644 index 0000000..43d4443 --- /dev/null +++ b/LIN_Stack/include/lin_common_api.h @@ -0,0 +1,301 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/** @addtogroup common_core_api_group +* @{ */ +/**************************************************************************//** +* +* @file lin_common_api.h +* +* @author FPT Software +* +* @brief Common LIN API functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +/** @} */ + +#ifndef _LIN_COMMON_API_H +#define _LIN_COMMON_API_H + +#include "lin.h" +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_bool l_sys_init ( void ) +* @brief This function performs the initialization of the LIN core +* +* @return #l_bool +* +* @SDD_ID LIN_SDD_238 +* @endif +* +* @details +* This function performs the initialization of the LIN core +* +* @see #lin_lld_setup_xgate +* @see #lin_lld_timer_init +* +* @addtogroup driver_cluster_group +*//*END*----------------------------------------------------------------------*/ +l_bool l_sys_init (void); + +/** @} */ +#if LIN_MODE == _MASTER_MODE_ +/** @addtogroup schedule_management_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_sch_set (l_ifc_handle iii, l_schedule_handle schedule_iii, l_u8 entry) +* @brief Set up the next schedule to be followed by the l_sch_tick +* +* @param iii [IN] interface name +* @param schedule_iii [IN] schedule table for interface +* @param entry [IN] entry to be set +* +* @return #void +* +* @SDD_ID LIN_SDD_249 +* @endif +* +* @local_var +* -# #lin_configuration conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Set up the next schedule to be followed by the l_sch_tick +* function for a certain interface. The new schedule will be +* activated as soon as the current schedule reaches +* its next schedule entry point +* +*//*END*----------------------------------------------------------------------*/ +void l_sch_set (l_ifc_handle iii, l_schedule_handle schedule_iii, l_u8 entry); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 l_sch_tick (l_ifc_handle iii) +* @brief follows a schedule +* +* @param iii [IN] interface name +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_250 +* @endif +* +* @details +* This function follows a schedule. When a frame becomes due, its +* transmission is initiated. When the end of the current schedule is reached, +* this function starts again at the beginning of the schedule. +* +* @see #lin_tick_callback_handler +*//*END*----------------------------------------------------------------------*/ +l_u8 l_sch_tick (l_ifc_handle iii); +/** @} */ + +/** @addtogroup interface_management_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_ifc_goto_sleep (l_ifc_handle iii) +* @brief Request slave nodes to enter bus sleep mode +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_252 +* @endif +* +* @local_var +* -# #lin_configuration conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Request slave nodes on the cluster connected to the interface to enter +* bus sleep mode by issuing one go to sleep command. +* +* @see #l_sch_set +*//*END*----------------------------------------------------------------------*/ +void l_ifc_goto_sleep (l_ifc_handle iii); +/** @} */ +#endif /* LIN_MODE == _MASTER_MODE_ */ +/** @addtogroup interface_management_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_bool l_ifc_init (l_ifc_handle iii) +* @brief Initialize the controller specified by name +* +* @param iii [IN] interface name +* +* @return #l_bool +* +* @SDD_ID LIN_SDD_251 +* @endif +* +* @details +* Initialize the controller specified by name, i.e. sets up internal +* functions such as the baud rate. The default schedule set by the l_ifc_init +* call will be the L_NULL_SCHEDULE where no frames will be sent and received. +* This is the first call a user must perform, before using any other interface +* related LIN API functions. +* The function returns zero if the initialization was successful and non-zero if failed. +* +* @see #lin_lld_init +*//*END*----------------------------------------------------------------------*/ +l_bool l_ifc_init (l_ifc_handle iii); +/* l_ifc_ioctl */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_ifc_wake_up (l_ifc_handle iii) +* @brief Transmit the wake up signal. +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_253 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Transmit the wake up signal. +* +* @see #lin_lld_tx_wake_up +*//*END*----------------------------------------------------------------------*/ +void l_ifc_wake_up (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_ifc_rx (l_ifc_handle iii) +* @brief Receive one frame +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_254 +* @endif +* +* @details +* Receive one frame +* +*//*END*----------------------------------------------------------------------*/ +void l_ifc_rx (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_ifc_tx (l_ifc_handle iii) +* @brief Transmit one frame +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_255 +* @endif +* +* @details +* Transmit one frame +* +*//*END*----------------------------------------------------------------------*/ +void l_ifc_tx (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u16 l_ifc_read_status (l_ifc_handle iii) +* @brief This function will return the status of the previous communication +* +* @param iii [IN] interface name +* +* @return #l_u16 +* +* @SDD_ID LIN_SDD_259 +* @endif +* +* @local_var +* -# #l_u16 tmp_word_status +* -# #lin_configuration conf +* +* @static_global_var +* -# #lin_word_status +* -# #lin_ifc_configuration +* +* @details +* This function will return the status of the previous communication +* +*//*END*----------------------------------------------------------------------*/ +l_u16 l_ifc_read_status (l_ifc_handle iii); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_ifc_aux (l_ifc_handle iii) +* @brief synchronize to the break/sync field +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_256 +* @endif +* +* @details +* This function may be used in the slave nodes to synchronize to the +* break/sync field sequence transmitted by the master node on the +* interface specified by name. +* +*//*END*----------------------------------------------------------------------*/ + +void l_ifc_aux (l_ifc_handle iii); +/** @} */ + +/** @addtogroup call_out_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u16 l_sys_irq_disable (l_ifc_handle iii) +* @brief Disable LIN related IRQ +* +* @param iii [IN] interface name +* +* @return #l_u16 +* +* @SDD_ID LIN_SDD_257 +* @endif +* +* @details +* Disable LIN related IRQ +* +* @see #lin_lld_int_disable +*//*END*----------------------------------------------------------------------*/ +l_u16 l_sys_irq_disable (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void l_sys_irq_restore (l_ifc_handle iii) +* @brief Enable LIN related IRQ +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_258 +* @endif +* +* @details +* Enable LIN related IRQ +* +* @see #lin_lld_int_enable +*//*END*----------------------------------------------------------------------*/ +void l_sys_irq_restore (l_ifc_handle iii); +/** @} */ +/** @addtogroup common_core_api_group +* @{ */ +/** @} */ +#endif /* _LIN_COMMON_API_H */ diff --git a/LIN_Stack/include/lin_common_proto.h b/LIN_Stack/include/lin_common_proto.h new file mode 100644 index 0000000..3cffff7 --- /dev/null +++ b/LIN_Stack/include/lin_common_proto.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup common_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_common_proto.h +* +* @author FPT Software +* +* @brief Common LIN protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_COMMON_PROTO_H +#define _LIN_COMMON_PROTO_H + +#include "lin.h" + +#define MAKE_UNCONDITIONAL_FRAME 0 /**< make unconditional frame */ +#define UPDATE_UNCONDITIONAL_FRAME 1 /**< update unconditional frame */ + +#if LIN_MODE == _MASTER_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_pid_response_callback_handler (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid) +* @brief The upper slave task is in charge of handling PID or Response complete events +* +* @param iii [IN] interface name +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_264 +* @endif +* +* @details +* The upper slave task is in charge of handling PID or Response complete events +* +* @see #lin_process_pid +* @see #lin_update_tx +* @see #lin_update_rx +* @see #lin_bus_activity_timeout +* @see #lin_handle_error +*//*END*----------------------------------------------------------------------*/ +void lin_pid_response_callback_handler (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_tick_callback_handler (l_ifc_handle iii) +* @brief Tick handle function used for master task. This function is called periodically, +* +* @param iii [IN] interface name +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_265 +* @endif +* +* @local_var +* -# #lin_schedule_struct *sch +* -# #l_u8 *current_entry +* -# #l_u8 frame_index +* -# #l_u8 i +* -# #lin_configuration *conf +* -# #lin_tl_queue *current_pdu +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #schedule_tbl +* +* @details +* Tick handle function used for master task. This function is called periodically, +* +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +* @see #lin_collision_resolve +* @see #lin_switch_sch_table +* @see #lin_check_sporadic_update +* @see #lin_lld_tx_header +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_tick_callback_handler (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_pid (l_ifc_handle iii, l_u8 pid) +* @brief Handle the received PID and decide the next action of stack +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_266 +* @endif +* +* @local_var +* -# #l_u8 action +* -# #l_u8 associate_frame +* -# #lin_frame_struct *lin_frame_ptr +* -# #l_u8 frame_index +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #lin_associate_frame_struct +* +* @details +* Handle the received PID and decide the next action of Stack +* +* @see #lin_get_frame_index +* @see #lin_process_uncd_frame +* @see #lin_make_res_evnt_frame +* @see #lin_tl_make_mreq_pdu +* @see #lin_make_res_diag_frame +* @see #lin_lld_rx_response +* @see #lin_lld_set_response +* @see #lin_lld_ignore_response +*//*END*----------------------------------------------------------------------*/ +void lin_process_pid (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_rx (l_ifc_handle iii, l_u8 pid) +* @brief Update signal, status and flags after received response +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_267 +* @endif +* +* @local_var +* -# #l_bool pid_found +* -# #l_u8 frame_index +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #lin_flag_frame_handle_tbl +* +* @details +* Update signal, status and flags after received response +* +* @see #lin_get_frame_index +* @see #lin_process_uncd_frame +* @see #lin_update_rx_evnt_frame +* @see #lin_update_rx_diag_frame +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_update_rx (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_tx (l_ifc_handle iii, l_u8 pid) +* @brief Update status and flags after transmit response +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_268 +* @endif +* +* @local_var +* -# #l_u8 frame_index +* -# #const lin_configuration *conf +* -# #const lin_frame_struct *lin_frame_ptr +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #frame_signal_error +* -# #lin_flag_frame_handle_tbl +* -# #lin_frame_flag_tbl +* -# #lin_associate_frame_struct +* +* @details +* Update status and flags after transmit response +* +* @see #lin_get_frame_index +* @see #lin_update_tx_flags +* @see #tl_process_mreq +* @see #lin_update_err_signal +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_update_tx (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_handle_error (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid) +* @brief Handle error raised by low-level +* +* @param iii [IN] interface name +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_269 +* @endif +* +* @local_var +* -# #l_u8 frame_index +* -# #const lin_configuration *conf +* -# #const lin_frame_struct *lin_frame_ptr +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #frame_signal_error +* -# #lin_flag_frame_handle_tbl +* -# #lin_frame_flag_tbl +* -# #lin_associate_frame_struct +* +* @details +* Handle error raised by low-level +* +* @see #lin_get_frame_index +* @see #lin_update_tx_flags +* @see #tl_process_mreq +* @see #lin_update_err_signal +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_handle_error (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_bus_activity_timeout (l_ifc_handle iii, l_u8 pid) +* @brief Set bus activity timeout +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_270 +* @endif +* +* @local_var +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Set bus activity timeout +* +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +* @see #lin_lld_set_low_power_mode +*//*END*----------------------------------------------------------------------*/ +void lin_bus_activity_timeout (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_switch_sch_table (l_ifc_handle iii) +* @brief Check to see if the current schedule table is needed to change +* or not +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_271 +* @endif +* +* @local_var +* -# #l_u8 tmp_sch_id +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Check to see if the current schedule table is needed to change +* or not. Used in tick callback function. +* +*//*END*----------------------------------------------------------------------*/ +void lin_switch_sch_table (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_check_sporadic_update (l_ifc_handle iii, l_frame_handle frm_id) +* @brief Find the frame associated with a specified sporadic frame which is updated +* +* @param iii [IN] interface name +* @param frm_id [IN] index of frame +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_272 +* @endif +* +* @local_var +* -# #l_u8 j +* -# #lin_associate_frame_struct *ptr +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Find the frame associated with a specified sporadic frame which is updated +* +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_check_sporadic_update (l_ifc_handle iii, l_frame_handle frm_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_tx_flags (l_ifc_handle iii, l_u8 frm_id) +* @brief Update transmit flags +* +* @param iii [IN] interface name +* @param frm_id [IN] index of frame +* +* @return #void +* +* @SDD_ID LIN_SDD_273 +* @endif +* +* @local_var +* -# #const lin_configuration *conf +* -# #const lin_frame_struct *frame_struct_ptr +* -# #lin_frm2sig *ptr +* -# #l_u8 i +* -# #l_u8 signal_id +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #lin_flag_signal_handle_tbl +* +* @details +* Update transmit flags +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_tx_flags (l_ifc_handle iii, l_u8 frm_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_rx_diag_frame (l_ifc_handle iii, l_u8 pid) +* @brief The function is to update the receive flags associated with signals/frames +* in case receive a diagnostic frame. +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_274 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #l_u8 j +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The function is to update the receive flags associated with signals/frames +* in case receive a diagnostic frame. +* +* @see #lin_lld_set_low_power_mode (iii) +* @see #lin_tl_handler (iii) +*//*END*----------------------------------------------------------------------*/ +void lin_update_rx_diag_frame (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_uncd_frame (l_ifc_handle iii, l_u8 pid, l_u8 type) +* @brief This function to pack signals associated with unconditional frame into buffer +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* @param type [IN] make or update +* +* @return #void +* +* @SDD_ID LIN_SDD_278 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #l_u8 tmp_offset +* -# #l_u8 index +* -# #l_u8 frame_index +* -# #l_u8 signal_id +* -# #l_u8 *response_buffer_ptr +* -# #l_u8 tmp_sig_size +* -# #l_u8 tmp_byte_data +* -# #l_s8 length +* -# #l_s8 to_fill +* -# #l_s8 byte_offset +* -# #const lin_frame_struct *frame_struct_ptr +* -# #const lin_signal_struct *lin_signal_str_ptr +* -# #l_u16 tmp16 +* -# #lin_frm2sig *ptr +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #frame_signal_error +* -# #lin_flag_signal_handle_tbl +* +* @details +* This function to pack signals associated with unconditional frame into buffer +* +* @see #lin_update_signal_scalar +* @see #l_bytes_rd +* @see #l_bytes_wr +*//*END*----------------------------------------------------------------------*/ +void lin_process_uncd_frame(l_ifc_handle iii, l_u8 pid, l_u8 type); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_make_res_diag_frame (l_ifc_handle iii, l_u8 pid) +* @brief This function is to copy diagnostic data into buffer +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_275 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #const lin_configuration *conf +* -# #lin_tl_pdu_data lin_tl_pdu +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function is to copy diagnostic data into buffer +* +*//*END*----------------------------------------------------------------------*/ +void lin_make_res_diag_frame (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_get_frame_index (l_ifc_handle iii, l_u8 pid) +* @brief This function is return the index of a frame in frame list or 0xFF if not found. +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_276 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function is return the index of a frame in frame list or 0xFF if not found. +* +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_get_frame_index (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_signal_scalar (const lin_configuration *conf_ptr, l_u16 value, l_signal_handle signal_name) +* @brief Check and update scalar signal +* +* @param conf_ptr [IN] current configuration +* @param value [IN] value to compare +* @param signal_name [IN] signal name +* +* @return #void +* +* @SDD_ID LIN_SDD_277 +* @endif +* +* @local_var +* -# #l_u8 signal_size +* -# #l_u16 sig_value +* +* @details +* Check and update scalar signal +* +* @see #l_u16_wr +* @see #l_u8_wr +* @see #l_bool_wr +*//*END*----------------------------------------------------------------------*/ +void lin_update_signal_scalar(const lin_configuration *conf_ptr, l_u16 value, l_signal_handle signal_name); +#endif /* end of LIN_MODE == _MASTER_MODE_ */ + +/* ---------------------------- For 1 interface -----------------------------------*/ +#if LIN_MODE == _SLAVE_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_pid_response_callback_handler (lin_lld_event_id event_id, l_u8 pid) +* @brief The upper slave task is in charge of handling PID or Response complete events +* +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_287 +* @endif +* +* @details +* The upper slave task is in charge of handling PID or Response complete events +* +* @see #lin_process_pid +* @see #lin_update_tx +* @see #lin_update_rx +* @see #lin_handle_error (event_id, pid) +*//*END*----------------------------------------------------------------------*/ +void lin_pid_response_callback_handler (lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_pid (l_u8 pid) +* @brief Handle the received PID and decide the next action of the Stack +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_288 +* @endif +* +* @local_var +* -# #l_u8 action +* -# #lin_frame_struct *lin_frame_ptr +* +* @static_global_var +* -# #frame_index +* -# #lin_frame_tbl +* -# #lin_frame_flag_tbl +* -# #lin_configuration_RAM +* -# #tl_slaveresp_cnt +* +* @details +* Handle the received PID and decide the next action of the Stack +* +* @see #lin_get_frame_index +* @see #lin_make_res_evnt_frame +* @see #lin_process_uncd_frame +* @see #lin_make_res_diag_frame +* @see #lin_lld_rx_response +* @see #lin_lld_set_response +* @see #lin_lld_ignore_response +*//*END*----------------------------------------------------------------------*/ +void lin_process_pid (l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_rx (l_u8 pid) +* @brief Update signal, status and flags after received response +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_289 +* @endif +* +* @local_var +* -# #l_bool pid_found +* +* @static_global_var +* -# #lin_successful_transfer +* -# #lin_frame_tbl +* -# #lin_flag_frame_handle_tbl +* +* @details +* Update signal, status and flags after received response +* +* @see #lin_process_uncd_frame +* @see #lin_update_rx_diag_frame +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_update_rx (l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_tx (l_u8 pid) +* @brief Update status and flags after transmit response +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_290 +* @endif +* +* @static_global_var +* -# #lin_successful_transfer +* -# #lin_frame_flag_tbl +* -# #frame_index +* +* @details +* Update status and flags after transmit response +* +* @see #lin_process_uncd_frame +* @see #lin_update_rx_diag_frame +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_update_tx (l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_handle_error (lin_lld_event_id event_id, l_u8 pid) +* @brief Handle error raised by low-level +* +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_291 +* @endif +* +* @static_global_var +* -# #frame_index +* -# #lin_frame_tbl +* -# #lin_error_in_response +* -# #tl_slaveresp_cnt +* +* @details +* Handle error raised by low-level +* +* @see #lin_get_frame_index +* @see #lin_update_err_signal +* @see #lin_update_word_status_lin21 +* @see #lin_update_status_byte +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_handle_error (lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_bus_activity_timeout (l_u8 pid) +* @brief Set bus activity timeout +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_292 +* @endif +* +* @details +* Set bus activity timeout +* +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +* @see #lin_lld_set_low_power_mode +*//*END*----------------------------------------------------------------------*/ +void lin_bus_activity_timeout (l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_tx_flags (l_u8 frm_id) +* @brief Update transmit flags +* +* @param frm_id [IN] index of frame +* +* @return #void +* +* @SDD_ID LIN_SDD_293 +* @endif +* +* @local_var +* -# #lin_frame_struct frame_struct_ptr +* -# #lin_frm2sig *ptr +* -# #l_u8 i +* -# #l_u8 signal_id +* +* @static_global_var +* -# #lin_frame_tbl +* -# #lin_flag_signal_handle_tbl +* +* @details +* Update transmit flags +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_tx_flags (l_u8 frm_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_rx_diag_frame ( void ) +* @brief update the receive flags associated with signals/frames +* in case receive a diagnostic frame. +* +* @return #void +* +* @SDD_ID LIN_SDD_294 +* @endif +* +* @static_global_var +* -# #lin_lld_response_buffer +* -# #lin_goto_sleep_flg +* +* @details +* The function is to update the receive flags associated with signals/frames +* in case receive a diagnostic frame. +* +* @see #lin_lld_set_low_power_mode +* @see #lin_tl_put_pdu +* @see #lin_tl_handler +*//*END*----------------------------------------------------------------------*/ +void lin_update_rx_diag_frame (void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_uncd_frame (l_u8 pid, l_u8 type) +* @brief Update signal, status and flags after received response +* +* @param pid [IN] PID to process +* @param type [IN] make or update +* +* @return #void +* +* @SDD_ID LIN_SDD_297 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #l_u8 tmp_offset +* -# #l_u8 index +* -# #l_u8 signal_id +* -# #l_s8 length +* -# #l_s8 to_fill +* -# #l_s8 byte_offset +* -# #l_s8 tmp_byte_data +* -# #l_u16 tmp16 +* -# #l_u16 tmp_sig_size +* -# #lin_frm2sig *ptr +* +* @static_global_var +* -# #frame_index +* -# #lin_frame_tbl +* -# #lin_lld_response_buffer +* -# #response_error +* -# #frame_signal_error +* -# #lin_flag_signal_handle_tbl +* -# #lin_signal_flag_tbl +* +* @details +* Update signal, status and flags after received response +* +* @see #lin_get_frame_index +* @see #l_u16_wr +* @see #l_u8_wr +* @see #l_bool_wr +* @see #l_bytes_rd +* @see #l_bytes_wr +*//*END*----------------------------------------------------------------------*/ +void lin_process_uncd_frame(l_u8 pid, l_u8 type); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_make_res_diag_frame ( void ) +* @brief This function is to copy diagnostic data into buffer +* +* @return #void +* +* @SDD_ID LIN_SDD_295 +* @endif +* +* @details +* This function is to copy diagnostic data into buffer +* +* @see #lin_tl_get_pdu +*//*END*----------------------------------------------------------------------*/ +void lin_make_res_diag_frame (void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_get_frame_index (l_u8 pid) +* @brief This function is return the index of a frame in frame list or 0xFF if not found. +* +* @param pid [IN] PID to process +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_296 +* @endif +* +* @local_var +* -# #l_u8 i +* +* @static_global_var +* -# #lin_configuration_RAM +* +* @details +* This function is return the index of a frame in frame list or 0xFF if not found. +* +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_get_frame_index (l_u8 pid); +#endif /* end of LIN_MODE == _SLAVE_MODE_*/ +#endif /* _LIN_COMMON_PROTO_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_commontl_api.h b/LIN_Stack/include/lin_commontl_api.h new file mode 100644 index 0000000..0aef06e --- /dev/null +++ b/LIN_Stack/include/lin_commontl_api.h @@ -0,0 +1,868 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup commontl_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_commontl_api.h +* +* @author FPT Software +* +* @brief Common LIN transport layer and configuration functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * 20111005 v1.1 Added porotytpe functions + * + *****************************************************************************/ + +#ifndef _LIN_COMMONTL_API_H +#define _LIN_COMMONTL_API_H +/** @} */ + +#include "lin.h" + +/* Node configuration */ +#define LD_READ_OK 0x33 /**< Read OK */ +#define LD_LENGTH_TOO_SHORT 0x34 /**< Lenghth too short */ + +#define LD_DATA_ERROR 0x43 /**< Data error */ +#define LD_LENGTH_NOT_CORRECT 0x44 /**< Lenghth not correct */ +#define LD_SET_OK 0x45 /**< Set OK */ + +#if LIN_MODE == _MASTER_MODE_ + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* Initialized transport layer */ +/** @addtogroup initialization_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_init (l_ifc_handle iii) +* @brief initialize or reinitalize the raw and cooked layers +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_17 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This call will initialize or reinitalize the raw and cooked layers +* on the interface iii. +* All the transport layer buffers will be initialized. +*//*END*----------------------------------------------------------------------*/ +void ld_init(l_ifc_handle iii); +/** @} */ +/* Transport layer RAW APIs */ + +/** @addtogroup raw_api_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_put_raw (l_ifc_handle iii, const l_u8* const data) +* @brief The call queues the transmisson of 8 bytes of data in one frame +* +* @param iii [IN] lin interface handle +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @SDD_ID LIN_SDD_318 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call queues the transmisson of 8 bytes of data in one frame +* The data is sent in the next suitable frame. +* +* @see #tl_put_raw +*//*END*----------------------------------------------------------------------*/ +void ld_put_raw(l_ifc_handle iii,const l_u8* const data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_get_raw (l_ifc_handle iii, l_u8* const data) +* @brief The call copies the oldest received diagnostic frame data to the memory +* specified by data +* +* @param iii [IN] lin interface handle +* @param data [IN] buffer for store data received +* +* @return #void +* +* @SDD_ID LIN_SDD_319 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call copies the oldest received diagnostic frame data to the memory +* specified by data. +* The data returned is received from master request frame for slave node +* and the slave response frame for master node. +*//*END*----------------------------------------------------------------------*/ +void ld_get_raw(l_ifc_handle iii,l_u8* const data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_raw_tx_status (l_ifc_handle iii) +* @brief The call returns the status of the raw frame transmission function +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_320 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call returns the status of the raw frame transmission function:
+* LD_QUEUE_EMPTY : The transmit queue is empty. In case previous calls to
+* ld_put_raw, all frames in the queue have been
+* trans-mitted.
+* LD_QUEUE_AVAILABLE: The transmit queue contains entries, but is not full.
+* LD_QUEUE_FULL : The transmit queue is full and can not accept further
+* frames.
+* LD_TRANSMIT_ERROR : LIN protocol errors occurred during the transfer;
+* ini-tialize and redo the transfer. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_raw_tx_status(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_raw_rx_status (l_ifc_handle iii) +* @brief The call returns the status of the raw frame receive function +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_321 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call returns the status of the raw frame receive function: +* LD_NO_DATA The receive queue is empty. +* LD_DATA_AVAILABLE The receive queue contains data that can be read. +* LD_RECEIVE_ERROR LIN protocol errors occurred during the transfer; +* ini-tialize and redo the transfer. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_raw_rx_status(l_ifc_handle iii); +/** @} */ +/* Transport layer COOKED APIs */ +/** @addtogroup cooked_api_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_send_message (l_ifc_handle iii, l_u16 length, l_u8 NAD, const l_u8* const data) +* @brief The call packs the information specified by data and length into one or multiple diagnostic frames +* +* @param iii [IN] lin interface handle +* @param length [IN] length of data to send +* @param NAD [IN] Node address of slave node +* @param data [IN] data to be sent +* @return #void +* +* @SDD_ID LIN_SDD_322 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* -# #lin_tl_pdu_data queue_data +* -# #lin_tl_pdu_data pdu +* -# #l_u8 i +* -# #l_u8 message_size +* -# #l_u16 data_index = 0 +* -# #l_u16 tmp_length = length +* -# #l_u16 frame_counter = 0 +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call packs the information specified by data and length into one or multiple +* diagnostic frames. If the call is made in a master node application the frames +* are transmitted to the slave node with the address NAD. If the call is made in +* a slave node application the frames are transmitted to the master node with the +* address NAD. The parameter NAD is not used in slave nodes. +*//*END*----------------------------------------------------------------------*/ +/** @} */ +void ld_send_message(l_ifc_handle iii, l_u16 length, l_u8 NAD, const l_u8* const data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_receive_message (l_ifc_handle iii, l_u16 *const length, l_u8 *const NAD, l_u8 *const data) +* @brief The call prepares the LIN diagnostic module to receive one message and store it in the buffer pointed to by data +* +* @param iii [IN] lin interface handle +* @param length [OUT] length of data to receive +* @param NAD [OUT] Node address of slave node +* @param data [OUT] data to be sent +* +* @return #void +* +* @SDD_ID LIN_SDD_323 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* -# #lin_tl_pdu_data queue_data +* -# #lin_tl_pdu_data pdu +* -# #l_u8 i +* -# #l_u16 data_index = 0 +* -# #l_u16 tmp_length +* -# #l_u16 frame_counter +* -# #l_u8 PCI_type +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call prepares the LIN diagnostic module to receive one message and store it in +* the buffer pointed to by data. At the call, length shall specify the maximum length +* allowed. When the reception has completed, length is changed to the actual length +* and NAD to the NAD in the message. +*//*END*----------------------------------------------------------------------*/ +void ld_receive_message(l_ifc_handle iii, l_u16* const length, l_u8* const NAD, l_u8* const data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_tx_status (l_ifc_handle iii) +* @brief The call returns the status of the last made call to ld_send_message. +* +* @param iii [IN] lin interface handle +* @return #l_u8 +* +* @SDD_ID LIN_SDD_324 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call returns the status of the last made call to ld_send_message. +* The following values can be returned: +* LD_IN_PROGRESS: The transmission is not yet completed. +* LD_COMPLETED: The transmission has completed successfully (and +* you can issue a new ld_send_message call). This +* value is also returned after initialization of +* the transport layer. +* LD_FAILED: The transmission ended in an error. The data was +* only partially sent. The transport layer shall +* be reinitialized before processing further messages. +* To find out why a transmission has failed, check +* the status management function l_read_status +* LD_N_AS_TIMEOUT: The transmission failed because of a N_As timeout, +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_tx_status(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_rx_status (l_ifc_handle iii) +* @brief The call returns the status of the last made call to ld_send_message. +* +* @param iii [IN] lin interface handle +* @return #void +* +* @SDD_ID LIN_SDD_325 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call returns the status of the last made call to ld_receive_message.
+* The following values can be returned:
+* LD_IN_PROGRESS: The reception is not yet completed.
+* LD_COMPLETED: The reception has completed successfully and all
+* information (length, NAD, data) is available. (You can
+* also issue a new ld_receive_message call). This
+* value is also returned after initialization of the
+* transport layer.
+* LD_FAILED: The reception ended in an error. The data was only
+* partially received and should not be trusted. Initialize
+* before processing further transport layer messages.
+* To find out why a reception has failed, check the status
+* management function l_read_status.
+* LD_N_CR_TIMEOUT The reception failed because of a N_Cr timeout
+* LD_WRONG_SN The reception failed because of an unexpected sequence number. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_rx_status(l_ifc_handle iii); +/** @} */ + +/* Configuration and Identify APIs */ +/** @addtogroup node_configuration_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_assign_NAD (l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 function_id, l_u8 new_NAD) +* @brief This call assigns the NAD (node diagnostic address) of all slave nodes that matches the initial_NAD, the supplier ID and the function ID. +* +* @param iii [IN] lin interface handle +* @param initial_NAD [IN] initial node address of the target node +* @param supplier_id [IN] supplier ID of the target node +* @param function_id [IN] function identifier of the target node +* @param new_NAD [IN] new node address +* +* @return #void +* +* @SDD_ID LIN_SDD_305 +* @endif +* +* @local_var +* -# #l_u8 data[6] +* -# #lin_configuration conf + +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This call assigns the NAD (node diagnostic address) of all slave nodes +* that matches the initial_NAD, the supplier ID and the function ID. +* The new NAD of the slave node will be new_NAD. +*//*END*----------------------------------------------------------------------*/ +#endif /*End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_)*/ +void ld_assign_NAD(l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 function_id, l_u8 new_NAD); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_conditional_change_NAD (l_ifc_handle iii, l_u8 NAD, l_u8 id, l_u8 byte, l_u8 mask, l_u8 invert, l_u8 new_NAD) +* @brief This call changes the NAD if the node properties fullfil the test specified by id, byte, mask and invert. +* +* @param iii [IN] lin interface handle +* @param NAD [IN] current NAD value of the target node +* @param id [IN] property ID of the target node +* @param byte [IN] byte location of property value to be read from the target node +* @param mask [IN] value for masking the read property byte +* @param invert [IN] value for excluding the read property byte +* @param new_NAD [IN] new NAD value to be assigned when the condition is met +* +* @return #void +* +* @SDD_ID LIN_SDD_206 +* @endif +* +* @local_var +* -# #l_u8 data[6] +* -# #lin_configuration conf + +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This call changes the NAD if the node properties fullfil the test +* specified by id, byte, mask and invert. +*//*END*----------------------------------------------------------------------*/ +void ld_conditional_change_NAD (l_ifc_handle iii, l_u8 NAD, l_u8 id, l_u8 byte, l_u8 mask, l_u8 invert, l_u8 new_NAD); +/** @} */ +/** @addtogroup node_identification_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_read_by_id(l_ifc_handle iii, l_u8 NAD, l_u16 supplier_id, l_u16 function_id, l_u8 id, l_u8* const data) +* @brief The call requests the slave node selected with the NAD to return the property associated with the id parameter. +* +* @param iii [IN] lin interface handle +* @param NAD [IN] alue of the target node +* @param supplier_id [IN] supplier ID of the target node +* @param function_id [IN] function ID of the target node +* @param id [IN] ID of the target node +* @param data [IN] buffer for saving the data read from the node +* +* @return #void +* +* @SDD_ID LIN_SDD_307 +* @endif +* +* @local_var +* -# #l_u8 buf[6] +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The call requests the slave node selected with the NAD to return the +* property associated with the id parameter. +*//*END*----------------------------------------------------------------------*/ +void ld_read_by_id (l_ifc_handle iii, l_u8 NAD, l_u16 supplier_id, l_u16 function_id, l_u8 id, l_u8* const data); + + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_save_configuration(l_ifc_handle iii,l_u8 NAD) +* @brief This function to issue a save configuration request to a slave node +* +* @param iii [IN] interface name +* @param NAD [IN] node adress of target +* +* @return #void +* +* @SDD_ID LIN_SDD_xxx +* @endif +* +* @param iii [IN] lin interface handle +* @param NAD [IN] Node address of target +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# l_u8 data[6] +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* This function is called to send a save configuration request to a specific slave node
+* with the given NAD, or to all slave nodes if NAD is set to broadcast +* This function is implemented for Master Only +*//*END*----------------------------------------------------------------------*/ +void ld_save_configuration(l_ifc_handle iii,l_u8 NAD); + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_read_configuration(l_ifc_handle iii, l_u8* const data, l_u8* const length) +* @brief This function to copy current configuration in a reserved area +* +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_xxx +* @endif +* +* @param iii [IN] lin interface handle +* @param data [IN] data area to save configuration, +* @param length [IN] length of data arean (1+n, NAD+PIDs) +* +* @local_var +* -# #i l_u8 +* -# #temp l_u8 +* -# #retval l_u8 +* -# #expected_length l_u8 +* +* @static_global_var +* -# #lin_configured_NAD +* -# #lin_configuration_RAM +* +* @details +* This function is implemented Slave Only +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_read_configuration(l_ifc_handle iii, l_u8* const data, l_u8* const length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_set_configuration(l_ifc_handle iii, const l_u8* const data, l_u16 length) +* @brief This function function to configure slave node according to data +* +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_xxx +* @endif +* +* @param iii [IN] lin interface handle +* @param data [IN] structure containing the NAD and all the n PIDs for the frames of the specified NAD, +* @param length [IN] length of data arean (1+n, NAD+PIDs) +* +* @local_var +* -# #i l_u8 +* -# #retval l_u8 +* -# #expected_length l_u8 +* +* @static_global_var +* -# #lin_configured_NAD +* -# #lin_configuration_RAM +* +* @details +* This function is implemented Slave Only +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_set_configuration(l_ifc_handle iii, const l_u8* const data, l_u16 length); + + +/** @} */ +#endif /* End LIN_MODE == _MASTER_MODE_ */ + + + +/* SLAVE MODE */ +#if LIN_MODE == _SLAVE_MODE_ +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + +/* INITIALIZATION */ +/** @addtogroup initialization_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_init (void) +* @brief initialize or reinitalize the transport layer +* +* @return #void +* +* @SDD_ID LIN_SDD_341 +* @endif +* +* @static_global_var +* -# #lin_tl_tx_queue +* -# #lin_tl_rx_queue +* -# #tl_rx_msg_status +* -# #tl_rx_msg_index +* -# #tl_rx_msg_size +* -# #tl_receive_msg_status +* -# #tl_tx_msg_status +* -# #tl_tx_msg_index +* -# #tl_tx_msg_size +* -# #tl_last_cfg_result +* -# #tl_last_RSID +* -# #tl_ld_error_code +* -# #tl_frame_counter +* -# #tl_no_of_pdu +* -# #tl_slaveresp_cnt +* -# #tl_check_timeout_type +* -# #tl_check_timeout +* -# #tl_service_status +* +* @details +* This call will initialize or reinitalize the raw and cooked layers +* on the interface iii. +* All the transport layer buffers will be initialized. +*//*END*----------------------------------------------------------------------*/ +void ld_init(void); +/** @} */ + +/* RAW APIs */ +/** @addtogroup raw_api_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_put_raw (const l_u8* const data) +* @brief The call queues the transmisson of 8 bytes of data in one frame +* +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @SDD_ID LIN_SDD_342 +* @endif +* +* @details +* The call queues the transmisson of 8 bytes of data in one frame +* The data is sent in the next suitable frame. +* +* @see #tl_put_raw +*//*END*----------------------------------------------------------------------*/ +void ld_put_raw(const l_u8* const data); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_get_raw (l_u8* const data) +* @brief The call copies the oldest received diagnostic frame data to the memory +* specified by data +* +* @param data [IN] buffer for store data received +* +* @return #void +* +* @SDD_ID LIN_SDD_343 +* @endif +* +* @details +* The call copies the oldest received diagnostic frame data to the memory +* specified by data. +* The data returned is received from master request frame for slave node +* and the slave response frame for master node. +* @see #tl_get_raw +*//*END*----------------------------------------------------------------------*/ +void ld_get_raw(l_u8* const data); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_raw_tx_status (void) +* @brief The call returns the status of the raw frame transmission function +* +* @return #void +* +* @SDD_ID LIN_SDD_344 +* @endif +* +* @static_global_var +* -# #lin_tl_tx_queue +* +* @details +* The call returns the status of the raw frame transmission function:
+* LD_QUEUE_EMPTY : The transmit queue is empty. In case previous calls to
+* ld_put_raw, all frames in the queue have been
+* trans-mitted.
+* LD_QUEUE_AVAILABLE: The transmit queue contains entries, but is not full.
+* LD_QUEUE_FULL : The transmit queue is full and can not accept further
+* frames.
+* LD_TRANSMIT_ERROR : LIN protocol errors occurred during the transfer;
+* ini-tialize and redo the transfer. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_raw_tx_status(void); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_raw_rx_status (void) +* @brief The call returns the status of the raw frame receive function +* +* @return #void +* +* @SDD_ID LIN_SDD_345 +* @endif +* +* @static_global_var +* -# #lin_tl_rx_queue +* +* @details +* The call returns the status of the raw frame receive function: +* LD_NO_DATA The receive queue is empty. +* LD_DATA_AVAILABLE The receive queue contains data that can be read. +* LD_RECEIVE_ERROR LIN protocol errors occurred during the transfer; +* ini-tialize and redo the transfer. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_raw_rx_status(void); +/** @} */ +/* COOKED APIs */ +/** @addtogroup cooked_api_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_send_message (l_u16 length, const l_u8* const data) +* @brief The call packs the information specified by data and length into one or multiple diagnostic frames +* +* @param length [IN] length of data to send +* @param data [IN] data to be sent +* +* @return #void +* +* @SDD_ID LIN_SDD_346 +* @endif +* +* @local_var +* -# #lin_tl_pdu_data pdu +* -# #l_u8 i +* -# #l_u8 message_size +* -# #l_u16 data_index +* -# #l_u16 tmp_length +* -# #l_u16 frame_counter +* +* @static_global_var +* -# #tl_tx_msg_status +* -# #tl_slaveresp_cnt +* -# #lin_tl_tx_queue +* -# #tl_tx_msg_index +* -# #tl_tx_msg_size +* -# #tl_tx_msg_status +* -# #lin_configured_NAD +* -# #tl_check_timeout +* -# #tl_check_timeout_type +* +* @details +* The call packs the information specified by data and length into one or multiple +* diagnostic frames. If the call is made in a master node application the frames +* are transmitted to the slave node with the address NAD. If the call is made in +* a slave node application the frames are transmitted to the master node with the +* address NAD. The parameter NAD is not used in slave nodes. +* +* @see #ld_put_raw +*//*END*----------------------------------------------------------------------*/ +void ld_send_message(l_u16 length, const l_u8* const data); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_receive_message (l_u16 *const length, l_u8 *const data) +* @brief The call prepares the LIN diagnostic module to receive one message and store it in the buffer pointed to by data +* +* @param length [OUT] length of data to receive +* @param data [OUT] data to be sent +* +* @return #void +* +* @SDD_ID LIN_SDD_347 +* @endif +* +* @local_var +* -# #lin_tl_pdu_data pdu +* -# #l_u8 i +* -# #l_u16 data_index = 0 +* -# #l_u16 tmp_length +* -# #l_u16 frame_counter +* -# #l_u8 PCI_type +* +* @static_global_var +* -# #tl_rx_msg_status +* -# #tl_receive_msg_status +* +* @details +* The call prepares the LIN diagnostic module to receive one message and store it in +* the buffer pointed to by data. At the call, length shall specify the maximum length +* allowed. When the reception has completed, length is changed to the actual length +* and NAD to the NAD in the message. +* +* @see #ld_get_raw +*//*END*----------------------------------------------------------------------*/ +void ld_receive_message(l_u16* const length, l_u8* const data); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_tx_status () +* @brief The call returns the status of the last made call to ld_send_message. +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_348 +* @endif +* +* @static_global_var +* -# #tl_tx_msg_status +* +* @details +* The call returns the status of the last made call to ld_send_message. +* The following values can be returned: +* LD_IN_PROGRESS: The transmission is not yet completed. +* LD_COMPLETED: The transmission has completed successfully (and +* you can issue a new ld_send_message call). This +* value is also returned after initialization of +* the transport layer. +* LD_FAILED: The transmission ended in an error. The data was +* only partially sent. The transport layer shall +* be reinitialized before processing further messages. +* To find out why a transmission has failed, check +* the status management function l_read_status +* LD_N_AS_TIMEOUT: The transmission failed because of a N_As timeout, +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_tx_status(void); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_rx_status (void) +* @brief The call returns the status of the last made call to ld_send_message. +* +* @return #void +* +* @SDD_ID LIN_SDD_349 +* @endif +* +* @static_global_var +* -# #tl_rx_msg_status +* +* @details +* The call returns the status of the last made call to ld_receive_message.
+* The following values can be returned:
+* LD_IN_PROGRESS: The reception is not yet completed.
+* LD_COMPLETED: The reception has completed successfully and all
+* information (length, NAD, data) is available. (You can
+* also issue a new ld_receive_message call). This
+* value is also returned after initialization of the
+* transport layer.
+* LD_FAILED: The reception ended in an error. The data was only
+* partially received and should not be trusted. Initialize
+* before processing further transport layer messages.
+* To find out why a reception has failed, check the status
+* management function l_read_status.
+* LD_N_CR_TIMEOUT The reception failed because of a N_Cr timeout
+* LD_WRONG_SN The reception failed because of an unexpected sequence number. +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_rx_status(void); +/** @} */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_read_configuration() +* @brief This function to copy current configuration in a reserved area +* +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_xxx +* @endif +* @param data [IN] data area to save configuration, +* @param length [IN] length of data arean (1+n, NAD+PIDs) +* +* @local_var +* -# #i l_u8 +* -# #temp l_u8 +* -# #retval l_u8 +* -# #expected_length l_u8 +* +* @static_global_var +* -# #lin_configured_NAD +* -# #lin_configuration_RAM +* +* @details +* This function is implemented Slave Only +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_read_configuration(l_u8* const data, l_u8* const length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_set_configuration() +* @brief This function function to configure slave node according to data +* +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_xxx +* @endif +* +* @param data [IN] structure containing the NAD and all the n PIDs for the frames of the specified NAD, +* @param length [IN] length of data arean (1+n, NAD+PIDs) +* +* @local_var +* -# #i l_u8 +* -# #retval l_u8 +* -# #expected_length l_u8 +* +* @static_global_var +* -# #lin_configured_NAD +* -# #lin_configuration_RAM +* +* @details +* This function is implemented Slave Only +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_set_configuration(const l_u8* const data, l_u16 length); + +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ +#endif /* End LIN_MODE == _SLAVE_MODE_ */ +#endif /* _LIN_COMMONTL_API_H */ diff --git a/LIN_Stack/include/lin_commontl_proto.h b/LIN_Stack/include/lin_commontl_proto.h new file mode 100644 index 0000000..25c63af --- /dev/null +++ b/LIN_Stack/include/lin_commontl_proto.h @@ -0,0 +1,576 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup transport_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_commontl_proto.h +* +* @author FPT Software +* +* @brief Common Handle LIN transport layer and configuration functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * 20111005 v1.1 Added extern functions + * + *****************************************************************************/ + +#ifndef _LIN_COMMONTL_PROTO_H +#define _LIN_COMMONTL_PROTO_H + +#include "lin.h" + +/* define PCI type */ +#define PCI_SF 0x00 /**< Single Frame */ +#define PCI_FF 0x01 /**< First Frame */ +#define PCI_CF 0x02 /**< Consecutive Frame */ + +/* For J2602 */ +#define SERVICE_TARGET_RESET 0xB5 /**< target reset service */ +#define RES_POSITIVE 0x40 /**< positive response */ + +/* For negative response */ +#define RES_NEGATIVE 0x7F /**< negative response */ +#define GENERAL_REJECT 0x10 /**< Error code raised when request for service not supported comes */ +#define SERVICE_NOT_SUPPORTED 0x11 /**< Error code in negative response for not supported service */ +#define SUBFUNCTION_NOT_SUPPORTED 0x12 /**< Error code in negative response for not supported subfunction */ + +/* Response type from Slave */ +#define NEGATIVE 0 /**< negative response */ +#define POSITIVE 1 /**< positive response */ +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* Transmission direction */ +#define TRANSMISSION 0 /**< transmission */ +#define RECEIVING 1 /**< receiveing */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +/* Define wildcards */ +#define LD_BROADCAST 0x7F /**< NAD */ +#define LD_FUNCTIONAL_NAD 0x7E /**< functional NAD */ +#define LD_ANY_SUPPLIER 0x7FFF /**< Supplier */ +#define LD_ANY_FUNCTION 0xFFFF /**< Function */ +#define LD_ANY_MESSAGE 0xFFFF /**< Message */ + +/* Identifiers of node read by identifier service */ +#define LIN_PRODUCT_IDENT 0x00 /**< Node product identifier */ +#define SERIAL_NUMBER 0x01 /**< Serial number */ + + +#if LIN_MODE == _SLAVE_MODE_ +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) + +extern l_u8 ld_read_by_id_callout(l_u8 id, l_u8 *data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_make_slaveres_pdu (l_u8 sid, l_u8 res_type, l_u8 error_code) +* @brief This function is implemented for Slave only +* +* @param sid [IN] service identifier +* @param res_type [IN] type of response +* @param error_code [IN] Error code in case of negative response, if positive = 0 +* +* @return #void +* +* @SDD_ID LIN_SDD_350 +* @endif +* +* @static_global_var +* -# #tx_single_pdu_data +* -# #tl_current_tx_pdu_ptr +* -# #product_id +* -# #tl_pdu_frame_mode +* -# #tl_slaveresp_cnt + + +* @details +* This function is implemented for Slave only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_make_slaveres_pdu(l_u8 sid, l_u8 res_type, l_u8 error_code); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_attach_service() +* @brief This function make a connection to Diag service class that support for LIN function +* +* +* @return #void +* +* @SDD_ID LIN_SDD_355 +* @endif +* +* @local_var +* -# #sci l_u8 +* +* @static_global_var +* -# #tl_current_rx_pdu_ptr +* +* @see lin_tl_make_slaveres_pdu + +* +* @details +* This function make a connection to Diag service class that support for LIN function +* This function is implemented for Slave only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_attach_service(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_get_pdu() +* @brief This function copy the current PDU to Response Buffer in Low-level +* +* +* @return #void +* +* @SDD_ID LIN_SDD_351 +* @endif +* +* @local_var +* -# #l_u8 i +* +* @static_global_var +* -# #lin_lld_response_buffer[9] +* -# #tl_current_tx_pdu_ptr +* +* @details +* This function copy the current PDU to Response Buffer in Low-level +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_get_pdu(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_put_pdu() +* @brief This function put response buffer (in Low-level ) to PDU data on the Transport Layer +* +* +* @return #void +* +* @SDD_ID LIN_SDD_352 +* @endif +* +* @local_var +* -# #l_u8 i +* +* @static_global_var +* -# #lin_lld_response_buffer +* -# #tl_current_rx_pdu_ptr +* -# #rx_single_pdu_data +* +* @details +* This function put response buffer (in Low-level ) to PDU data on the Transport Layer +* Call in callback function +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_put_pdu(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_handler() +* @brief This function handles the diag service and control event and data in Transport Layer +* +* +* @return #void +* +* @SDD_ID LIN_SDD_353 +* @endif +* +* @local_var +* -# #pci_type l_u8 +* -# #length l_u8 +* +* @static_global_var +* -# #lin_initial_NAD[9] +* -# #tl_current_rx_pdu_ptr +* -# #lin_configured_NAD +* -# #lin_tl_attach_service +* +* @details +* This function handles the diag service and control event and data in TL +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_handler(void); + +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ +#endif /* End (LIN_MODE == _SLAVE_MODE_)*/ + + +#if LIN_MODE == _MASTER_MODE_ + +extern l_u8 ld_read_by_id_callout(l_ifc_handle iii, l_u8 id, l_u8 *data); + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_make_mreq_pdu(l_ifc_handle iii) +* @brief This function will be called on Master Task in LIN protocol, it create a pointer to PDU data +* +* @param iii [IN] interface name +* @return #void +* +* @SDD_ID LIN_SDD_308 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* +* @static_global_var +* -# #tl_current_rx_pdu_ptr +* +* @see lin_tl_make_slaveres_pdu +* +* @details +* This function will be called on Master Task in LIN protocol, it create a pointer to PDU data +* which available for Master request commmand, correspond to Diag frame to send +* This function is implemented for Master +*//*END*----------------------------------------------------------------------*/ +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +void lin_tl_make_mreq_pdu(l_ifc_handle iii); +#else /*Single frame support */ +void lin_tl_make_mreq_pdu(l_ifc_handle iii,lin_tl_pdu_data *pdu_ptr); +#endif /*End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_get_response(l_ifc_handle iii) +* @brief This function check result of service, it is called when the Slave Response Frame received +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_315 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# #l_u8 sci* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* This function check result of service, it is called when the Slave Response Frame received +* This function is implemented for Master only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_get_response(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_make_slaveres_pdu(l_ifc_handle iii, l_u8 sid, l_u8 res_type, l_u8 error_code) +* @brief This function is implemented for Slave only +* +* @param iii [IN] interface name +* @param sid [IN] service identifier +* @param res_type [IN] type of response +* @param error_code [IN] Error code in case of negative response, if positive = 0 +* +* @return #void +* +* @SDD_ID LIN_SDD_309 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_tl_pdu_data lin_tl_pdu +* -# #lin_node_attribute node_conf +* -# #lin_product_id ident +* -# #l_u8 i +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* This function is implemented for Slave only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_make_slaveres_pdu(l_ifc_handle iii, l_u8 sid, l_u8 res_type, l_u8 error_code); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_attach_service(l_ifc_handle iii) +* @brief This function make a connection to Diag service class that support for LIN function +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_314 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_transport_layer_queue *tl_queue +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# #l_u8 sci* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* This function make a connection to Diag service class that support for LIN function +* This function is implemented for Slave only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_attach_service(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_get_pdu(l_ifc_handle iii) +* @brief This function copy the current PDU to Response Buffer in Low-level +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_311 +* @endif +* +* @local_var +* -# #l_u8 i +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data lin_tl_pdu +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see tl_get_raw +* @details +* This function copy the current PDU to Response Buffer in Low-level +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_get_pdu(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_handler(l_ifc_handle iii) +* @brief This function handles the diag service and control event and data in TL +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_313 +* @endif +* +* @local_var +* -# #l_u8 pci_type +* -# #l_u8 length +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# #lin_node_attribute *node_conf +* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see lin_process_pdu +* +* @details +* This function handles the diag service and control event and data in TL +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ + +void lin_tl_handler(l_ifc_handle iii); + +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_handler_error(l_ifc_handle iii, l_u8 pid) +* @brief This function handles the diag service and control error in TL +* +* @param iii [IN] interface name +* @param pid [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_328 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* This function handles the diag service and control error in TL +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_handler_error(l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void tl_process_mreq(l_ifc_handle iii) +* @brief This function is process transport layer +* @param iii [IN] interface name +* @return #void +* +* @SDD_ID LIN_SDD_326 +* @endif +* +* @local_var +* -# #lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #lin_transport_layer_queue tl_queue +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see lin_tl_make_slaveres_pdu +* +* @details +* This function is process transport layer +*//*END*----------------------------------------------------------------------*/ +void tl_process_mreq(l_ifc_handle iii); +#else /* Single frame support */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_no_response(l_ifc_handle iii) +* @brief set the result of service +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_316 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function set the result of service, it is called when the master has no Slave Response Frame.
+* This function is implemented for Master only +*//*END*----------------------------------------------------------------------*/ +void lin_tl_no_response(l_ifc_handle iii); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_update_tx_flag(l_ifc_handle iii) +* @brief update flags related to Diag frame when received and transmited successful +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_310 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function update flags related to Diag frame when received and transmited successful.
+* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_update_tx_flag(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_tl_put_pdu(l_ifc_handle iii) +* @brief put response buffer (in Low-level ) to PDU data on the Transport Layer +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_312 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data *lin_tl_pdu +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function put response buffer (in Low-level ) to PDU data on the Transport Layer +* Call in callback function +* This function is implemented for Slave and Master +*//*END*----------------------------------------------------------------------*/ +void lin_tl_put_pdu(l_ifc_handle iii); + + +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_)*/ +#endif /* End (LIN_MODE == _MASTER_MODE_)*/ + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* COMMON FUNCTIONS */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void tl_put_raw(const l_u8* const data, lin_transport_layer_queue *queue, l_u8 direction) +* @brief The call copies the raw data specified by data to the queue specified by queue. +* +* @param data [IN] buffer for the data +* @param *queue queue for containing data +* @param direction Direction +* +* @return #void +* +* @SDD_ID LIN_SDD_303 +* @endif +* +* @local_var +* -# #lin_tl_pdu_data *queue_data +* -# #l_u8 i +* +* @static_global_var +* +* @details +* The call copies the raw data specified by data to the queue specified by queue. +*//*END*----------------------------------------------------------------------*/ +void tl_put_raw(const l_u8* const data,lin_transport_layer_queue *queue,l_u8 direction); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void tl_get_raw(l_u8* const data, lin_transport_layer_queue *queue, l_u8 direction) +* @brief +* The call gets the raw data from the queue specified by queue to +* the raw data specified by data +* specified by queue. +* +* @param data [OUT] buffer for store data received +* @param *queue queue for containing data +* @param direction Direction for transmission +* +* @return #void +* +* @SDD_ID LIN_SDD_304 +* @endif +* +* @local_var +* -# #lin_transport_layer_queue *tl_queue +* -# #lin_tl_pdu_data *queue_data +* -# #l_u8 i +* +* @static_global_var +* -# #lin_ifc_configuration +* +* +* @details +* The call gets the raw data from the queue specified by queue to +* the raw data specified by data +* specified by queue. +*//*END*----------------------------------------------------------------------*/ +void tl_get_raw(l_u8* const data,lin_transport_layer_queue *queue,l_u8 direction); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* end of_LIN_COMMONTL_PROTO_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_diagnostic_service.h b/LIN_Stack/include/lin_diagnostic_service.h new file mode 100644 index 0000000..2424c92 --- /dev/null +++ b/LIN_Stack/include/lin_diagnostic_service.h @@ -0,0 +1,293 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup diagnostic_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_diagnostic_service.h +* +* @author FPT Software +* +* @brief diagnostic service +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_DIAGNOSTIC_SERVICE_H +#define _LIN_DIAGNOSTIC_SERVICE_H + +#include "lin.h" +#if LIN_MODE == _SLAVE_MODE_ +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H)&& !defined(MCU_SKEAZN84) +#if LIN_PROTOCOL == PROTOCOL_21 + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_assign_frame_id_range ( void ) +* @brief process assign frame id range request, and also prepare its response data +* +* +* @return #void +* +* @SDD_ID LIN_SDD_359 +* @endif +* +* @local_var +* -# #l_u8 start_index +* -# #l_s8 i +* -# #l_s8 j +* +* @static_global_var +* -# #tl_current_rx_pdu_ptr +* -# #lin_configuration_RAM +* +* @details +* This function to process assign frame id range request, and also prepare its response data. +* This function is only for Slave Node. +* Required: Mandatory. +* For LIN 2.1 +* +* @see #lin_tl_make_slaveres_pdu +* @see #lin_process_parity +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_assign_frame_id(); +void lin_diagservice_assign_frame_id_range(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_read_by_identifier ( void ) +* @brief process read by identifier request, and also prepare its response data +* +* +* @return #void +* +* @SDD_ID LIN_SDD_360 +* @endif +* +* @local_var +* -# #l_u8 id +* -# #l_u16 supid +* -# #l_u16 fid +* +* @static_global_var +* -# #tl_current_rx_pdu_ptr +* -# #product_id +* -# #tl_slaveresp_cnt +* +* @details +* This function to process read by identifier request, and also prepare its response data
+* This function is only for Slave Node
+* Required: Mandatory
+* For LIN 2.1 and 2.0
+* +* @see #lin_tl_make_slaveres_pdu +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_read_by_identifier(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagsrv_functional_service ( void ) +* @brief process functional request +* +* +* @return #void +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @local_var +* -# #l_u16 length +* -# #l_u8 data[] +* +* @static_global_var +* +* @details +* This function to process functional request. Slave do not response when receive a functional request +* @see #ld_receive_message +*//*END*----------------------------------------------------------------------*/ +void lin_diagsrv_functional_service(void); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_condittional_change_nad ( void ) +* @brief process functional request +* +* +* @return #void +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @local_var +* -# #l_u16 length +* -# #l_u8 data[] +* +* @static_global_var +* +* @details +* This function to process functional request. Slave do not response when receive a functional request +* @see #ld_receive_message +*//*END*----------------------------------------------------------------------*/ +void lin_condittional_change_nad(void); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + + +#if LIN_PROTOCOL == PROTOCOL_J2602 + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_target_reset ( void ) +* @brief process read by identifier request, and also prepare its response data +* +* +* @return #void +* +* @SDD_ID LIN_SDD_361 +* @endif +* +* @local_var +* -# #l_u8 *signal_data_ptr +* -# #l_u8 nad +* +* @static_global_var +* -# #tl_current_rx_pdu_ptr +* -# #tl_slaveresp_cnt +* +* @details +* This function to process read by identifier request, and also prepare its response data
+* and Reset the Slave Node
+* This function is only for Slave Node
+* Required: Mandatory
+* For J2602 +* +* @see #lin_tl_make_slaveres_pdu +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_target_reset(void); +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ +#endif /* LIN_MODE == _SLAVE_MODE_ */ + +#if LIN_MODE == _MASTER_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_assign_frame_id_range ( l_ifc_handle iii ) +* @brief process assign frame id range request, and also prepare its response data +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_356 +* @endif +* +* @local_var +* -# #const lin_configuration conf +* -# #lin_tl_descriptor tl_conf +* -# #l_s8 i +* -# #l_s8 j +* -# #l_u8 start_index +* -# #l_u8 cfg_frame_num +* -# #lin_tl_pdu_data *lin_tl_pdu +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function to process assign frame id range request, and also prepare its response data +* This function is only for Slave Node +* Required: Mandatory +* For LIN 2.1 +* +* @see #lin_tl_make_slaveres_pdu +* @see #lin_process_parity +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_assign_frame_id_range(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_read_by_identifier ( l_ifc_handle iii ) +* @brief process assign frame id range request, and also prepare its response data +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_357 +* @endif +* +* @local_var +* -# #const lin_configuration *conf +* -# #const lin_node_attribute *node_conf +* -# #lin_product_id node_conf +* -# #lin_tl_descriptor *tl_conf +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# #l_u8 id +* -# #l_u16 supid +* -# #l_u16 fid +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function to process read by identifier request, and also prepare its response data +* This function is only for Slave Node +* Required: Mandatory +* For LIN 2.1 and 2.0 +* +* @see #lin_tl_make_slaveres_pdu +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_read_by_identifier(l_ifc_handle iii); +/* J2602 */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_diagservice_target_reset ( l_ifc_handle iii ) +* @brief process read by identifier request, and also prepare its response data +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_358 +* @endif +* +* @local_var +* -# #const lin_configuration *conf +* -# #lin_tl_descriptor1 *tl_conf +* -# #lin_tl_pdu_data *pdu +* -# #l_u8 *signal_data_ptr +* -# #l_u8 *nad +* +* @static_global_var +* -# #lin_ifc_configuration +* -# #lin_tl_pdu +* +* @details +* This function to process read by identifier request, and also prepare its response data +* and Reset the Slave Node +* This function is only for Slave Node +* Required: Mandatory +* For J2602 +* +* @see #lin_tl_make_slaveres_pdu +*//*END*----------------------------------------------------------------------*/ +void lin_diagservice_target_reset(l_ifc_handle iii); + +/*! + * @brief Process Conditional Change NAD request + * + * @param iii Interface name + * @return void + */ +void lin_condittional_change_nad(l_ifc_handle iii); +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#endif /* _LIN_DIAGNOSTIC_SERVICE_H */ +/* End of definition if _LIN_DIAGNOSTIC_SERVICE_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_j2602_api.h b/LIN_Stack/include/lin_j2602_api.h new file mode 100644 index 0000000..9d93c87 --- /dev/null +++ b/LIN_Stack/include/lin_j2602_api.h @@ -0,0 +1,72 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup J2602_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602_api.h +* +* @author FPT Software +* +* @brief J2602 LIN core API functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_J2602_API_H +#define _LIN_J2602_API_H + +#include "lin.h" + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_bool l_ifc_connect (l_ifc_handle iii) +* @brief Connect the interface iii to the LIN cluster and enable the transmission +* +* @param iii [IN] interface name +* +* @return #l_bool +* +* @SDD_ID LIN_SDD_260 +* @endif +* +* @details +* Connect the interface iii to the LIN cluster and enable the transmission +* of headers and data to the bus. (For J2602 and LIN 2.0 only) +* +*//*END*----------------------------------------------------------------------*/ +l_bool l_ifc_connect (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_bool l_ifc_disconnect (l_ifc_handle iii) +* @brief Disconnect the interface iii from the LIN cluster and thus disable the +* interaction with the other nodes in the cluster. +* +* @param iii [IN] interface name +* +* @return #l_bool +* +* @SDD_ID LIN_SDD_261 +* @endif +* +* @details +* Disconnect the interface iii from the LIN cluster and thus disable the +* interaction with the other nodes in the cluster. (For J2602 and LIN 2.0 only) +* +*//*END*----------------------------------------------------------------------*/ +l_bool l_ifc_disconnect (l_ifc_handle iii); + +#endif /* _LIN_J2602_API_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_j2602_proto.h b/LIN_Stack/include/lin_j2602_proto.h new file mode 100644 index 0000000..cf8e209 --- /dev/null +++ b/LIN_Stack/include/lin_j2602_proto.h @@ -0,0 +1,144 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup J2602_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602_proto.h +* +* @author FPT Software +* +* @brief J2602 LIN protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_J2602_PROTO_H +#define _LIN_J2602_PROTO_H + +#include "lin.h" + +#if LIN_MODE == _MASTER_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_word_status_j2602 (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid) +* @brief Update date word status +* +* @param iii [IN] interface name +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_285 +* @endif +* +* @local_var +* -# #l_u8 err_in_res +* -# #l_u8 suc_in_tras +* -# #lin_word_status_str *word_status +* -# #lin_configuration const *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Update date word status +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_word_status_j2602 (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_status_byte (l_ifc_handle iii, lin_lld_event_id event_id) +* @brief The function is to perform the update of error signal in J2602 system +* +* @param iii [IN] interface name +* @param event_id [IN] event id +* +* @return #void +* +* @SDD_ID LIN_SDD_284 +* @endif +* +* @local_var +* -# #l_u8 *signal_data_ptr +* -# #lin_configuration const *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The function is to perform the update of error signal in J2602 system +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_status_byte (l_ifc_handle iii, lin_lld_event_id event_id); +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/* ---------------------------- For 1 interface -----------------------------------*/ +#if LIN_MODE == _SLAVE_MODE_ +#if LIN_PROTOCOL != PROTOCOL_21 + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_word_status_j2602 (lin_lld_event_id event_id, l_u8 pid) +* @brief Update date word status +* +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_301 +* @endif +* +* @static_global_var +* -# #lin_word_status +* -# #lin_error_in_response +* -# #lin_successful_transfer +* +* @details +* Update date word status +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_word_status_j2602 (lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_status_byte (lin_lld_event_id event_id) +* @brief The function is to perform the update of error signal in J2602 system +* +* @param event_id [IN] event id +* +* @return #void +* +* @SDD_ID LIN_SDD_302 +* @endif +* +* @local_var +* -# #l_u8 *signal_data_ptr +* +* @static_global_var +* -# #response_error +* @details +* The function is to perform the update of error signal in J2602 system +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_status_byte (lin_lld_event_id event_id); +#endif /* End (LIN_PROTOCOL != PROTOCOL_21) */ + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + + +#endif /* _LIN_J2602_PROTO_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_j2602tl_api.h b/LIN_Stack/include/lin_j2602tl_api.h new file mode 100644 index 0000000..5f8db36 --- /dev/null +++ b/LIN_Stack/include/lin_j2602tl_api.h @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup j2602tl_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602tl_api.h +* +* @author FPT Software +* +* @brief J2602 LIN transport layer and configuration functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +/** @} */ +#ifndef _LIN_J2602TL_API_H +#define _LIN_J2602TL_API_H + +#include "lin.h" + +#if LIN_MODE == _MASTER_MODE_ +#if LIN_PROTOCOL == PROTOCOL_J2602 +/** @addtogroup j2602tl_api_group +* @{ */ +/* API functions */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_bool ld_is_ready(l_ifc_handle iii) +* @brief Verifies a state of node setting (using for J2602) +* +* @param iii [IN] lin interface handle +* +* @return #l_bool +* +* @SDD_ID LIN_SDD_338 +* @endif +* +* @local_var +* -# #lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Verifies a state of node setting (using for J2602) +*//*END*----------------------------------------------------------------------*/ +l_bool ld_is_ready (l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 ld_check_response(l_ifc_handle iii, l_u8* const RSID, l_u8* const error_code) +* @brief Verifies the state of response (using for J2602) +* +* @param iii [IN] lin interface handle +* @param RSID [OUT] buffer for saving the response ID +* @param error_code [OUT] buffer for saving the error code +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_339 +* @endif +* +* @local_var + +* -# #lin_last_cfg_result temp +* -# #lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Verifies the state of response (using for J2602) +*//*END*----------------------------------------------------------------------*/ +l_u8 ld_check_response (l_ifc_handle iii, l_u8* const RSID, l_u8* const error_code); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void ld_assign_frame_id(l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 message_id, l_u8 PID) +* @brief +* This call assigns the protected identifier of a frame in the slave node +* with the address NAD and the specified supplier ID (using for J2602) +* +* @param iii [IN] lin interface handle +* @param initial_NAD [IN] initial node address of the target node +* @param supplier_id [IN] supplier ID of the target node +* @param message_id [IN] message ID of the target node +* @param PID [IN] protected ID of the target node +* +* @return #void +* +* @SDD_ID LIN_SDD_340 +* @endif +* +* @local_var + +* -# #lin_tl_pdu_data *lin_tl_pdu +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This call assigns the protected identifier of a frame in the slave node +* with the address NAD and the specified supplier ID (using for J2602) +*//*END*----------------------------------------------------------------------*/ +void ld_assign_frame_id (l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 message_id, l_u8 PID); +/** @} */ +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ +#endif /* End (LIN_MODE == _MASTER_MODE_) */ +#endif /* _LIN_J2602TL_API_H */ diff --git a/LIN_Stack/include/lin_lin21_api.h b/LIN_Stack/include/lin_lin21_api.h new file mode 100644 index 0000000..5001516 --- /dev/null +++ b/LIN_Stack/include/lin_lin21_api.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup LIN21_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_lin21_api.h +* +* @author FPT Software +* +* @brief Common LIN 2.1 API functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090407 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_LIN21_API_H +#define _LIN_LIN21_API_H + +#include "lin.h" + +#endif /* _LIN_LIN21_API_H */ +/** @} */ \ No newline at end of file diff --git a/LIN_Stack/include/lin_lin21_proto.h b/LIN_Stack/include/lin_lin21_proto.h new file mode 100644 index 0000000..0700190 --- /dev/null +++ b/LIN_Stack/include/lin_lin21_proto.h @@ -0,0 +1,247 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup LIN21_core_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_lin21_proto.h +* +* @author FPT Software +* +* @brief Common LIN 2.1 protocol functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +#ifndef _LIN_LIN21_PROTO_H +#define _LIN_LIN21_PROTO_H + +#include "lin.h" + +#if LIN_MODE == _MASTER_MODE_ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_collision_resolve (l_ifc_handle iii, l_u8 pid) +* @brief Switch to collision resolve table +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_279 +* @endif +* +* @local_var +* -# #lin_associate_frame_struct *ptr +* -# #l_u8 frame_index +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Switch to collision resolve table +* +* @see #lin_get_frame_index +*//*END*----------------------------------------------------------------------*/ +void lin_collision_resolve (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_word_status_lin21 (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid) +* @brief Update date word status +* +* @param iii [IN] interface name +* @param event_id [IN] event id +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_280 +* @endif +* +* @local_var +* -# #l_bool pid_found +* +* @static_global_var +* -# #lin_successful_transfer +* -# #lin_frame_tbl +* -# #lin_flag_frame_handle_tbl +* +* @details +* Update date word status +* +* @see #lin_process_uncd_frame +* @see #lin_update_rx_diag_frame +* @see #lin_update_word_status_lin21 +* @see #lin_update_word_status_j2602 +*//*END*----------------------------------------------------------------------*/ +void lin_update_word_status_lin21 (l_ifc_handle iii, lin_lld_event_id event_id, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_err_signal (l_ifc_handle iii) +* @brief Update error signal +* +* @param iii [IN] interface name +* +* @return #void +* +* @SDD_ID LIN_SDD_281 +* @endif +* +* @local_var +* -# #const lin_configuration *conf +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* Update error signal +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_err_signal (l_ifc_handle iii, l_u8 frm_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_rx_evnt_frame (l_ifc_handle iii, l_u8 pid) +* @brief The function is to update the receive flags associated with signals/frames +* in case receive an event trigger frame. +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_282 +* @endif +* +* @local_var +* -# #lin_associate_frame_struct *ptr +* -# #const lin_configuration *conf +* -# #l_u8 frame_index +* -# #l_u8 ass_pid +* -# #l_u8 i +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* The function is to update the receive flags associated with signals/frames +* in case receive an event trigger frame. +* +* @see #lin_get_frame_index +* @see #lin_process_parity +* @see #lin_process_uncd_frame +*//*END*----------------------------------------------------------------------*/ +void lin_update_rx_evnt_frame (l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_make_res_evnt_frame (l_ifc_handle iii, l_u8 pid) +* @brief This function is to pack signals associated with event trigger frame into buffer +* +* @param iii [IN] interface name +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_278 +* @endif +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @details +* This function is to pack signals associated with event trigger frame into buffer +* +* @see #lin_process_uncd_frame +* @see #lin_process_parity +*//*END*----------------------------------------------------------------------*/ +void lin_make_res_evnt_frame (l_ifc_handle iii, l_u8 pid); +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/* ---------------------------- For 1 interface -----------------------------------*/ +#if LIN_MODE == _SLAVE_MODE_ + +#if ((LIN_PROTOCOL == PROTOCOL_21) || (LIN_PROTOCOL == PROTOCOL_20)) + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_word_status_lin21 (l_u8 pid) +* @brief Update date word status +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_298 +* @endif +* +* @static_global_var +* -# #lin_word_status +* -# #lin_error_in_response +* -# #lin_successful_transfer +* -# #lin_goto_sleep_flg +* +* @details +* Update date word status +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_word_status_lin21 (l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_update_err_signal ( void ) +* @brief Update error signal +* +* @return #void +* +* @SDD_ID LIN_SDD_299 +* @endif +* +* @local_var +* -# #l_bool pid_found +* +* @static_global_var +* -# #response_error +* -# #lin_error_in_response +* +* @details +* Update error signal +* +*//*END*----------------------------------------------------------------------*/ +void lin_update_err_signal ( l_u8 frm_id); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_make_res_evnt_frame (l_u8 pid) +* @brief This function is to pack signals associated with event trigger frame into buffer +* +* @param pid [IN] PID to process +* +* @return #void +* +* @SDD_ID LIN_SDD_300 +* @endif +* +* @details +* This function is to pack signals associated with event trigger frame into buffer +* +* @see #lin_process_uncd_frame +* @see #lin_lld_response_buffer +*//*END*----------------------------------------------------------------------*/ +void lin_make_res_evnt_frame (l_u8 pid); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + +#endif /* End ( LIN_MODE == _SLAVE_MODE_) */ + +#endif /* _LIN_LIN21_PROTO_H */ +/** @} */ diff --git a/LIN_Stack/include/lin_lin21tl_api.h b/LIN_Stack/include/lin_lin21tl_api.h new file mode 100644 index 0000000..6b3c358 --- /dev/null +++ b/LIN_Stack/include/lin_lin21tl_api.h @@ -0,0 +1,321 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2008-2015 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ******************************************************************************/ +/**************************************************************************//** + * @addtogroup lin21tl_api_group + * @{ + ******************************************************************************/ +/**************************************************************************//** + * + * @file lin_lin21tl_api.h + * + * @author FPT Software + * + * @brief LIN21 LIN transport layer and configuration functions + * + ******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +/** @} */ +#ifndef _LIN_LIN21TL_API_H +#define _LIN_LIN21TL_API_H + +#include "lin.h" +#if LIN_MODE == _MASTER_MODE_ +#if LIN_PROTOCOL == PROTOCOL_21 + +/* API functions */ +/** @addtogroup node_configuration_group +* @{ */ +/*FUNCTION*--------------------------------------------------------------*//** + * @fn l_u8 ld_is_ready(l_ifc_handle iii) + * @brief Verifies a state of node setting (using for LIN2.1) + * + * @param iii [IN] lin interface handle + * + * @return #l_u8 + * + * @SDD_ID LIN_SDD_329 +* @endif + * + * + * @static_global_var + * -# #lin_ifc_configuration + * + * @details + * Verifies a state of node setting (using for LIN2.1) + *//*END*----------------------------------------------------------------------*/ +l_u8 ld_is_ready(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** + * @fn void ld_check_response(l_ifc_handle iii, l_u8* const RSID, l_u8* const error_code) + * @brief Verifies the state of response (using for LIN2.1) + * + * @param iii [IN] lin interface handle + * @param RSID [OUT] buffer for saving the response ID + * @param error_code [OUT] buffer for saving the error code + * + * @return #void + * + * @local_var + * -# #lin_configuration *conf + * + * @SDD_ID LIN_SDD_330 +* @endif + * + * + * @static_global_var + * -# #lin_ifc_configuration + * + * @details + * Verifies the state of response (using for LIN2.1) + *//*END*----------------------------------------------------------------------*/ +void ld_check_response( + l_ifc_handle iii, + l_u8* const RSID, + l_u8* const error_code); + +/*FUNCTION*--------------------------------------------------------------*//** + * @fn void ld_assign_frame_id_range(l_ifc_handle iii, l_u8 NAD, l_u8 start_index, const l_u8* const PIDs) + * @brief + * This call assigns the protected identifier of up to four frames in the slave node with the + * addressed NAD (using for LIN2.1) + * + * @param iii [IN] lin interface handle + * @param NAD [IN] NAD value of the target node + * @param start_index [IN] specifies which is the first frame to assign a PID + * @param PIDs [IN] list of protected identifier + * + * @return #void + * + * @local_var + * -# #lin_configuration *conf + * -# #l_u8 Buff + * + * @SDD_ID LIN_SDD_331 +* @endif + * + * + * @static_global_var + * -# #lin_ifc_configuration + * + * @details + * This call assigns the protected identifier of up to four frames in the slave node with the + * addressed NAD (using for LIN2.1) + *//*END*----------------------------------------------------------------------*/ +void ld_assign_frame_id_range(l_ifc_handle iii, + l_u8 NAD, + l_u8 start_index, + const l_u8* const PIDs); +/** @} */ + +/* Multi frame support */ +/** @addtogroup lin21tl_api_group +* @{ */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* Diagnostic class II services, they can be used in class III */ + +/*FUNCTION*--------------------------------------------------------------*//** + * @fn void diag_read_data_by_identifier(l_ifc_handle iii, const l_u8 NAD, l_u8 *const data) + * @brief This function is read data by identifier. + * + * @param iii [IN] lin interface handle + * @param NAD [IN] NAD value of the destination node for the transmission + * @param data [IN] buffer for the data to be transmitted + * + * @return #void + * + * @local_var + * -# #l_u16 temp + * -# #l_u8 Buff + * -# #lin_configuration *conf + * + * @SDD_ID LIN_SDD_332 +* @endif + * + * + * @static_global_var + * -# #lin_ifc_configuration + * @see ld_send_message + * + * @details + * This function is read data by identifier.
+ * iii: name of interface
+ * NAD: NAD value of the destination node for the transmission
+ * data: buffer for the data to be transmitted
+ * 0x0202 - Read - A2D Values/Measurement
+ * 0x0206 - Read - LIN Stack Information
+ * 0xF18C - Read - ECU Barcode Number (Delphi)
+ *//*END*----------------------------------------------------------------------*/ +void diag_read_data_by_identifier(l_ifc_handle iii, const l_u8 NAD, l_u8 * const data); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void diag_write_data_by_identifier(l_ifc_handle iii, l_u8 NAD,l_u16 data_length, l_u8 *const data) +* @brief This function is write data by identifier service (0x2E) +* +* @param iii [IN] lin interface handle +* @param NAD [IN] NAD value of the destination node for the transmission +* @param data_length [IN] data length of frame +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @local_var +* -# #l_u16 temp = 0 +* -# #l_u8 Buff +* -# #l_u8 i +* -# #lin_configuration conf +* +* @SDD_ID LIN_SDD_333 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* @see ld_send_message +* +* @details +* Write_Data_By_Identifier service (0x2E)
+* iii: name of interface
+* NAD: NAD value of the destination node for the transmission
+* data: buffer for the data to be transmitted +*//*END*----------------------------------------------------------------------*/ +void diag_write_data_by_identifier(l_ifc_handle iii, const l_u8 NAD, l_u16 data_length, l_u8 * const data); + +/* END diagnostic class II services */ +/* Diagnostic class III services, these services only belong to diagnostic class III */ +#if (_DIAG_CLASS_SUPPORT_ == _DIAG_CLASS_III_) +/* Session control */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void diag_session_control(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data) +* @brief This function is session control service (service id: 0x10) +* +* @param iii [IN] lin interface handle +* @param NAD [IN] NAD value of the destination node for the transmission +* @param data_length [IN] data length of frame +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @local_var +* -# #l_u8 Buff +* -# #l_u8 i +* -# #lin_configuration conf +* +* @SDD_ID LIN_SDD_334 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* @see ld_send_message +* +* @details +* This function is used for master node only. It will packing data and send request to slave node with service ID = 0x10: Session control +*//*END*----------------------------------------------------------------------*/ +void diag_session_control(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data); +/* Fault memory */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void diag_fault_memory_read(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data) +* @brief This function is fault management read service (SID = 0x19) +* +* @param iii [IN] lin interface handle +* @param NAD [IN] NAD value of the destination node for the transmission +* @param data_length [IN] data length of frame +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @local_var +* -# #l_u8 Buff +* -# #l_u8 i +* -# #lin_configuration conf +* +* @SDD_ID LIN_SDD_335 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* @see ld_send_message +* +* @details +* This function is used for master node only. It will packing data and send request to slave node with service ID = 0x19: Fault memory read +*//*END*----------------------------------------------------------------------*/ +void diag_fault_memory_read (l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void diag_fault_memory_clear(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data) +* @brief This function is fault management clear service (SID = 0x14) +* +* @param iii [IN] lin interface handle +* @param NAD [IN] NAD value of the destination node for the transmission +* @param data_length [IN] data length of frame +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @local_var +* -# #l_u8 Buff +* -# #l_u8 i +* -# #lin_configuration conf +* +* @SDD_ID LIN_SDD_336 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* @see ld_send_message +* +* @details +* This function is used for master node only. It will packing data and send request to slave node with service ID = 0x14: Fault memory clear +*//*END*----------------------------------------------------------------------*/ +void diag_fault_memory_clear(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data); +/* IO control */ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void diag_IO_control(l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data) +* @brief This function is Input/Output control service (SID = 0x2F) +* +* @param iii [IN] lin interface handle +* @param NAD [IN] NAD value of the destination node for the transmission +* @param data_length [IN] data length of frame +* @param data [IN] buffer for the data to be transmitted +* +* @return #void +* +* @local_var +* -# #l_u8 Buff +* -# #l_u8 i +* -# #lin_configuration conf +* +* @SDD_ID LIN_SDD_337 +* @endif +* +* +* @static_global_var +* -# #lin_ifc_configuration +* @see ld_send_message +* +* @details +* This function is used for master node only. It will packing data and send request to slave node with service ID = 0x2F: Input/Output control service +*//*END*----------------------------------------------------------------------*/ +void diag_IO_control (l_ifc_handle iii, const l_u8 NAD,l_u16 data_length, l_u8 *const data); +#endif /* End (_DIAG_CLASS_SUPPORT_ == _DIAG_CLASS_III_) */ +/* End diagnostic class III services */ + +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* End of (LIN_PROTOCOL == PROTOCOL_21) */ +#endif /* End (LIN_MODE == _MASTER_MODE_) */ +/** @} */ +#endif /* _LIN_LIN21TL_API_H */ diff --git a/LIN_Stack/lowlevel/lin.c b/LIN_Stack/lowlevel/lin.c new file mode 100644 index 0000000..9477a96 --- /dev/null +++ b/LIN_Stack/lowlevel/lin.c @@ -0,0 +1,1152 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup lowlevel_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin.c +* +* @author FPT Software +* +* @brief LIN low level functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * + *****************************************************************************/ + +#include "lin.h" + +#if (_LIN_SCI_ == 1) +#include "lin_lld_sci.h" +#include "lin_lld_timesrv.h" +#endif /* End (_LIN_SCI_ == 1) */ + +#if (_LIN_XGATE_ == 1) +#include "lin_lld_xgate.h" +#include "lin_lld_timesrv.h" +#endif /* End (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) +#include "lin_lld_slic.h" +#include "MC9S08EL32.h" +/* Check Multi frame transmission */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +#include "lin_lld_timesrv.h" +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* End (_LIN_SLIC_ == 1) */ + +#if (_LIN_GPIO_ == 1) +#include "lin_lld_gpio.h" +#endif /* End (_LIN_GPIO_ == 1) */ + +#if (_LIN_UART_ == 1) +#include "lin_lld_uart.h" +#include "lin_lld_timesrv.h" +#endif /* End (_LIN_SCI_ == 1) */ + +/* Globle variable */ +#if (LIN_MODE == _SLAVE_MODE_) +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME__) +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) +lin_message_timeout_type tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; /**< timeout type */ +l_u16 tl_check_timeout = N_MAX_TIMEOUT_CNT; /**< timeout counter*/ +lin_service_status tl_service_status = LD_SERVICE_IDLE; /**< Status of the last configuration service */ +#endif +#endif +#endif + +#if (LIN_MODE == _MASTER_MODE_) +l_u8 etf_collision_flag[LIN_NUM_OF_IFCS] = {0}; +/* Extern globle variable */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME__) +lin_message_timeout_type tl_check_timeout_type_array[LIN_NUM_OF_IFCS] = {LD_NO_CHECK_TIMEOUT}; +l_u16 tl_check_timeout_array[LIN_NUM_OF_IFCS] = {N_MAX_TIMEOUT_CNT}; +#endif + +l_u8 lin_lld_init +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_init */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_init(lin_hw, iii); + #else + lin_lld_xgate_init(lin_hw, iii); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_init(); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_init(lin_hw, iii); + #endif /* End (_LIN_UART_ == 1) */ + ret = LIN_LLD_OK; + } + return ret; +} + +l_u8 lin_lld_deinit +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_deinit */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_deinit(lin_hw); + #else + lin_lld_xgate_deinit(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_deinit(); + #endif /* End (_LIN_GPIO_ == 1 */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_deinit(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + ret = LIN_LLD_OK; + } + + return ret; +} + +l_u8 lin_lld_get_state +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + + #if ((_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1)) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_get_status */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + ret = lin_lld_sci_get_state(lin_hw); + #else + ret = lin_lld_xgate_get_state(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End ((_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1)) */ + + #if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_hw = lin_virtual_ifc[iii]; + ret = lin_lld_uart_get_state(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + ret = lin_lld_gpio_get_status(); + #endif /* End (_LIN_GPIO_ == 1) */ + } + + return ret; +} + +void lin_lld_tx_header +( + /* [IN] interface identifier */ + l_ifc_handle iii, + /* [IN] ID of the header to be sent */ + l_u8 pid +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + + /* Check for valid interface */ + if (iii <= LIN_NUM_OF_IFCS) + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_tx_header */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_tx_header(lin_hw, pid); + #else + lin_lld_xgate_tx_header(lin_hw, pid); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* defined(_LIN_SCI_) || defined(_LIN_XGATE_) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_tx_header(lin_hw, pid); + #endif /* End (_LIN_UART_ == 1) */ + } + + return; +} + +void lin_lld_tx_wake_up +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; + + /* Check for valid interface */ + if (iii <= LIN_NUM_OF_IFCS) + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_tx_wake_up */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_tx_wake_up(lin_hw); + #else + lin_lld_xgate_tx_wake_up(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_tx_wake_up(); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_tx_wake_up(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + } + + return; +} + +void lin_lld_int_enable +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; + + /* Check for valid interface */ + if (iii <= LIN_NUM_OF_IFCS) + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_int_enable */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_int_enable(lin_hw); + #else + lin_lld_xgate_int_enable(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_int_enable(); + #endif /* (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_int_enable(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + } + + return; +} + +l_u8 lin_lld_int_disable +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_int_disable */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_int_disable(lin_hw); + #else + lin_lld_xgate_int_disable(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_int_disable(); + #endif /* (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_int_disable(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + ret = LIN_LLD_OK; + } + + return ret; +} + +void lin_lld_ignore_response +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + + /* Check for valid interface */ + if (iii <= LIN_NUM_OF_IFCS) + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_ignore_response */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_ignore_response(lin_hw); + #else + lin_lld_xgate_ignore_response(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_ignore_response(); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_ignore_response(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + } + + return; +} + +void lin_lld_set_low_power_mode +( + /* [IN] interface identifier */ + l_ifc_handle iii +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + + /* Check for valid interface */ + if (iii <= LIN_NUM_OF_IFCS) + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_ignore_response */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_set_low_power_mode(lin_hw); + #else + lin_lld_xgate_set_low_power_mode(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_set_low_power_mode(); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_set_low_power_mode(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + } + + return; +} + +l_u8 lin_lld_set_response +( + /* [IN] interface identifier */ + l_ifc_handle iii, + /* [IN] response length */ + l_u8 response_length +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + /* Check for valid response length */ + if (response_length > 8) + { + ret = LIN_LLD_INVALID_PARA; + } + else + { + /* Put response length into buffer */ + *(lin_ifc_configuration[iii].response_buffer) = response_length; + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_set_response */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_tx_response(lin_hw); + #else + lin_lld_xgate_tx_response(lin_hw); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ + lin_lld_gpio_tx_response(); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_tx_response(lin_hw); + #endif /* End (_LIN_UART_ == 1) */ + ret = LIN_LLD_OK; + } + } + + return ret; +} + +l_u8 lin_lld_rx_response +( + /* [IN] interface identifier */ + l_ifc_handle iii, + /* [IN] response length */ + l_u8 response_length +) +{ + lin_hardware_name lin_hw; /* Indicator of LIN HW */ + l_u8 ret = 0; + + /* Check for valid interface */ + if (iii > LIN_NUM_OF_IFCS) + { + ret = LIN_LLD_INVALID_IFC; + } + else + { + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + /* Call lin_lld_xxx_rx_response */ + if (lin_hw <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_rx_response(lin_hw, response_length); + #else + lin_lld_xgate_rx_response(lin_hw, response_length); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ + lin_lld_gpio_rx_response(response_length); + #endif /* End (_LIN_GPIO_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis only */ + /* Find LIN HW interface which is mounted to interface */ + lin_hw = lin_virtual_ifc[iii]; + lin_lld_uart_rx_response(lin_hw, response_length); + #endif /* End (_LIN_UART_ == 1) */ + ret = LIN_LLD_OK; + } + + return ret; +} + +void lin_lld_set_etf_collision_flag( + /* [IN] interface identifier */ + l_ifc_handle iii) +{ + /* Set flag in case of occurring collision in event trigger frame */ + etf_collision_flag[iii] = 1; +} + +void lin_lld_clear_etf_collision_flag( + /* [IN] interface identifier */ + l_ifc_handle iii) +{ + /* Clear flag in case of occurring collision in event trigger frame */ + etf_collision_flag[iii] = 0; +} + +#endif /* end of LIN_MODE == _MASTER_MODE_ */ + + +#if LIN_MODE == _SLAVE_MODE_ +/* Extern globle variable */ + +l_u8 lin_lld_init +( +) +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_init */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_init((l_ifc_handle)0); + #else + lin_lld_xgate_init((l_ifc_handle)0); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_init(); + } +#endif /* End (_LIN_SLIC_ == 1) */ + +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_init((l_ifc_handle)0); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_init(); +#endif /* End (_LIN_GPIO_ == 1) */ + return LIN_LLD_OK; +} + +l_u8 lin_lld_deinit +( +) +{ + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_deinit */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_deinit(); + #else + lin_lld_xgate_deinit(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_deinit(); + } +#endif /* End (_LIN_SLIC_ == 1) */ + +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_deinit(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_deinit(); +#endif /* End (_LIN_GPIO_ == 1) */ + + return LIN_LLD_OK; +} + +l_u8 lin_lld_get_status +( +) +{ + l_u8 ret = 0; + + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_get_status */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + ret = lin_lld_sci_get_status(); + #else + ret = lin_lld_xgate_get_status(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + /* Add code here */ + } +#endif /* End (_LIN_SLIC_ == 1) */ + +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_get_status(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ +#endif /* End (_LIN_GPIO_ == 1) */ + + return ret; +} + +l_u8 lin_lld_get_state() +{ + l_u8 ret = 0; + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_get_status */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + ret = lin_lld_sci_get_state(); + #else + ret = lin_lld_xgate_get_state(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + ret = lin_lld_slic_get_state(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + ret = lin_lld_uart_get_state(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + ret = lin_lld_gpio_get_status(); +#endif /* End (_LIN_GPIO_ == 1) */ + + return ret; +} + +void lin_lld_tx_wake_up () +{ + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_tx_wake_up */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_tx_wake_up(); + #else + lin_lld_xgate_tx_wake_up(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_tx_wake_up(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_tx_wake_up(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_tx_wake_up(); +#endif /* End (_LIN_GPIO_ == 1) */ + + return; +} + +void lin_lld_int_enable () +{ + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_int_enable */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_int_enable(); + #else + lin_lld_xgate_int_enable(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_int_enable(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_int_enable(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_int_enable(); +#endif /* End #if (_LIN_GPIO_ == 1) */ + + return; +} + +l_u8 lin_lld_int_disable () +{ + /* Check for valid interface */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_int_disable */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_int_disable(); + #else + lin_lld_xgate_int_disable(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_int_disable(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_int_disable(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_int_disable(); +#endif /* End (_LIN_GPIO_ == 1) */ + + return LIN_LLD_OK; +} + +void lin_lld_ignore_response +( +) +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_ignore_response */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_ignore_response(); + #else + lin_lld_xgate_ignore_response(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_ignore_response(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_ignore_response(); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_ignore_response(); +#endif /* End (_LIN_GPIO_ == 1) */ + + return; +} + +void lin_lld_set_low_power_mode () +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_ignore_response */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_set_low_power_mode(); + #else + lin_lld_xgate_set_low_power_mode(); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + lin_lld_slic_set_low_power_mode(); + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + lin_lld_gpio_set_low_power_mode(); +#endif /* End (_LIN_GPIO_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis only */ + lin_lld_uart_set_low_power_mode(); +#endif /* End (_LIN_UART_ == 1) */ + + return; +} + +l_u8 lin_lld_set_response +( + /* [IN] response length */ + l_u8 response_length +) +{ + l_u8 ret = 0; + + /* Check for valid response length */ + if (response_length > 8) + { + ret = LIN_LLD_INVALID_PARA; + } + else + { + /* Put response length into buffer */ + lin_lld_response_buffer[0] = response_length; + + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_set_response */ + #if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_tx_response(); + #else + lin_lld_xgate_tx_response(); + #endif /* End (_LIN_SCI_ == 1) */ + } + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + + #if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + /* Add code here */ + lin_lld_slic_tx_response(&lin_lld_response_buffer[0]); + } + #endif /* End (_LIN_SLIC_ == 1) */ + #endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + + #if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_tx_response(); + #endif /* End (_LIN_UART_ == 1) */ + + #if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ + lin_lld_gpio_tx_response(); + #endif /* End (_LIN_GPIO_ == 1) */ + ret = LIN_LLD_OK; + } + + return ret; +} + +l_u8 lin_lld_rx_response +( + /* [IN] response length */ + l_u8 response_length +) +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_rx_response */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + lin_lld_sci_rx_response(response_length); + #else + lin_lld_xgate_rx_response(response_length); + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + /* Add code here */ + lin_lld_slic_rx_response(response_length); + } +#endif /* End (_LIN_SLIC_ == 1) */ + +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) /* For Kinetis platform */ + lin_lld_uart_rx_response(response_length); +#endif /* End (_LIN_UART_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ + lin_lld_gpio_rx_response(response_length); +#endif /* End (_LIN_GPIO_ == 1) */ + + return LIN_LLD_OK; +} + +#endif /* End of LIN_MODE == _SLAVE_MODE_ */ + +/*** Common function used to all low-level driver ***/ + +l_u8 lin_process_parity +( + /* [IN] PID need to be send */ + l_u8 pid, + /* [IN] Check or Make parity */ + l_u8 type +) +{ + l_u8 parity; + l_u8 ret; + + parity = (((BIT(pid, 0)^BIT(pid, 1)^BIT(pid, 2)^BIT(pid, 4)) << 6)| + ((~(BIT(pid, 1)^BIT(pid, 3)^BIT(pid, 4)^BIT(pid, 5))) << 7)); + if (CHECK_PARITY == type) + { + if ((pid&0xC0) != parity) + { + ret = 0xFF; + } + else + { + ret = (l_u8)(pid&0x3F); + } + } + else + { + ret = (l_u8)(pid|parity); + } + + return (ret); +} + +l_u8 lin_checksum +( + /* [IN] pointer to buffer */ + l_u8 *buffer, + /* [IN] pid */ + l_u8 raw_pid +) +{ + l_u8 length; + l_u16 check_sum; + + /* 1. PID correspond to Master request and Slave response, their checksum cal is classic + the non-diagnostic frame is calculated in Enhanced */ + if ((0x3C != raw_pid) && (0x7D != raw_pid)) + { + check_sum = raw_pid; + } + else + { + check_sum = 0; + } + + for (length = *buffer; 0 < length; length--) + { + buffer++; + check_sum += *(buffer); + /* 2. to deal with the carry */ + if (check_sum > 0xFF) + { + check_sum -= 0xFF; + } + } + + /* 3. to reverse */ + return (l_u8)(~check_sum); +} + +void lin_lld_timer_init +( + void +) +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + +#if (_MCU_ == _S12X_) + /* if use PIT for time service */ + lin_lld_timer_S12X_init(); +#endif /* End (_MCU_ == _S12X_) */ + +#if (_MCU_ == _S12_) + lin_lld_timer_S12_init(); +#endif /* End (_MCU_ == _S12_) */ + +#if (_MCU_ == _S08_) + lin_lld_timer_S08_init(); +#endif /* End (_MCU_ == _S08_) */ + +#endif /* (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + /* Init timer for SLIC interface, which using for check transport layer timeout */ + /* Use for multi frames transmission only. */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_lld_timer_S08_init(); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* End (_LIN_SLIC_ == 1) */ + +#if (_LIN_UART_ == 1) +#if (_MCU_ == _K_) + lin_lld_timer_K_init(); +#endif /* End (_MCU_ == _S12_) */ +#endif /* End (_LIN_UART_ == 1) */ +} + + +#if (LIN_MODE == _SLAVE_MODE_) +void lin_lld_mcu_reset() +{ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) + /* Call lin_lld_xxx_rx_response */ +#if (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) + if (lin_virtual_ifc <= SCI5) + { + #if (_LIN_SCI_ == 1) + + #else + + #endif /* End (_LIN_SCI_ == 1) */ + } +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) */ + +#if (_LIN_SLIC_ == 1) + if (lin_virtual_ifc == SLIC) + { + /* Add code here */ + } +#endif /* End (_LIN_SLIC_ == 1) */ +#endif /* End (_LIN_SCI_ == 1) || (_LIN_XGATE_ == 1) || (_LIN_SLIC_ == 1) */ + +#if (_LIN_GPIO_ == 1) /* For S09QD4 only */ + /* Add code here */ +#endif /* End (_LIN_GPIO_ == 1) */ +} + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + + +/** + * @} + */ diff --git a/LIN_Stack/lowlevel/lin.h b/LIN_Stack/lowlevel/lin.h new file mode 100644 index 0000000..4835de9 --- /dev/null +++ b/LIN_Stack/lowlevel/lin.h @@ -0,0 +1,1822 @@ +/****************************************************************************** +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +*****************************************************************************/ + +/**************************************************************************//** +* @addtogroup lowlevel_group +* @{ +******************************************************************************/ + +/**************************************************************************//** +* +* @file lin.h +* +* @author FPT Software +* +* @brief LIN low level functions +* +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090408 v1.0 First version + * 20111005 v1.1 Added some defines and extern functions + * 20140611 v1.2 Added UART support + * + *****************************************************************************/ + +#ifndef _LIN_H +#define _LIN_H + +#include "lin_cfg.h" +#include "lin_hw_cfg.h" + +#if (_LIN_SCI_ == 1)|(_LIN_UART_ == 1) + #include "lin_reg.h" + /* Disable warning: SP debug info */ + #if (_MCU_ == _S12X_) + #pragma MESSAGE DISABLE C12056 /* Disable warning message with ID C12056 */ + #endif /* End (_MCU_ == _S12X_) */ +#endif /* End (_LIN_SCI_ == 1)|(_LIN_UART_ == 1) */ + +#pragma MESSAGE DISABLE C5703 /* Disable warning message with ID C5703 */ + +#ifndef _DIAG_CLASS_SUPPORT_ + #error "_DIAG_CLASS_SUPPORT_ is not defined in lin_cfg.h" +#endif +#ifndef _TL_FRAME_SUPPORT_ + #error "_TL_FRAME_SUPPORT_ is not defined in lin_cfg.h" +#endif + +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) + /* Calculate N_As & N_Cr max timeout */ + #define N_MAX_TIMEOUT_CNT ((l_u16)(1000*(1000/TIME_BASE_PERIOD))) +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ + +/* Define data structure used for LIN Stack */ + +/**************************************************************************//** +* +* @var typedef unsigned char l_u8 +* lin unsigned char data type +* @var typedef signed char l_s8 +* lin signed char data type +* @var typedef volatile unsigned char l_vu8 +* lin volatile unsigned char data type +* @var typedef volatile signed char l_vs8 +* lin volatile signed char data type +* +* @var typedef unsigned int l_u16 +* lin unsigned int data type +* @var typedef signed int l_s16 +* lin signed int data type +* @var typedef volatile unsigned int l_vu16 +* lin volatile unsigned int data type +* @var typedef volatile signed int l_vs16 +* lin volatile signed int data type +* +* @var typedef unsigned long l_u32 +* lin unsigned long data type +* @var typedef signed long l_s32 +* lin signed long data type +* @var typedef volatile unsigned long l_vu32 +* lin volatile unsigned long data type +* @var typedef volatile signed long l_vs32 +* lin volatile signed long data type +* +* @var typedef unsigned char l_bool +* lin bool data type (true or false) +******************************************************************************/ +typedef signed char l_s8; +typedef unsigned char l_u8; + +typedef volatile signed char l_vs8; +typedef volatile unsigned char l_vu8; + +typedef signed short int l_s16; +typedef unsigned short int l_u16; + +typedef volatile signed short int l_vs16; +typedef volatile unsigned short int l_vu16; + +typedef signed long l_s32; +typedef unsigned long l_u32; + +typedef volatile signed long l_vs32; +typedef volatile unsigned long l_vu32; + +typedef unsigned char l_bool; + +#define MAKE_PARITY 0 /**< make parity bits */ +#define CHECK_PARITY 1 /**< check parity bits */ + +/* Define diagnostic services id */ +#define SERVICE_ASSIGN_NAD 0xB0 /**< assign NAD service */ +#define SERVICE_ASSIGN_FRAME_ID 0xB1 /**< assign frame id service */ +#define SERVICE_READ_BY_IDENTIFY 0xB2 /**< read by identify service */ +#define SERVICE_CONDITIONAL_CHANGE_NAD 0xB3 /**< conditional change NAD service */ +#define SERVICE_DATA_DUMP 0xB4 /**< data dump service */ +#define SERVICE_ASSIGN_NAD_VIA_SNPD 0xB5 /**< assign NAD via SN service */ +#define SERVICE_SAVE_CONFIGURATION 0xB6 /**< save configuration service */ +#define SERVICE_ASSIGN_FRAME_ID_RANGE 0xB7 /**< assign frame id range service */ + +#define SERVICE_READ_DATA_BY_IDENTIFY 0x22 /**< service read data by identifier */ +#define SERVICE_WRITE_DATA_BY_IDENTIFY 0x2E /**< service write data by identifier */ +#define SERVICE_SESSION_CONTROL 0x10 /**< service session control */ +#define SERVICE_IO_CONTROL_BY_IDENTIFY 0x2F /**< service I/O control */ +#define SERVICE_FAULT_MEMORY_READ 0x19 /**< service fault memory read */ +#define SERIVCE_FAULT_MEMORY_CLEAR 0x14 /**< service fault memory clear */ + +/* Define PCI's services */ +#define PCI_ASSIGN_NAD 0x06 /**< PCI value assign NAD */ +#define PCI_READ_BY_IDENTIFY 0x06 /**< PCI value read by identify */ +#define PCI_CONDITIONAL_CHANGE_NAD 0x06 /**< PCI value conditional change NAD */ +#define PCI_DATA_DUMP 0x06 /**< PCI value data dump */ +#define PCI_SAVE_CONFIGURATION 0x01 /**< PCI value save configuration */ +#define PCI_ASSIGN_FRAME_ID_RANGE 0x06 /**< PCI value assign frame id range */ + +/* Define PCI response's services */ +#define PCI_RES_ASSIGN_NAD 0x01 /**< PCI response value assign NAD */ +#define PCI_RES_READ_BY_IDENTIFY 0x06 /**< PCI response value read by identify */ +#define PCI_RES_READ_BY_IDENTIFY1 0x05 /**< PCI response value read by identify1 */ +#define PCI_RES_CONDITIONAL_CHANGE_NAD 0x01 /**< PCI response value conditional change NAD */ +#define PCI_RES_DATA_DUMP 0x06 /**< PCI response value data dump */ +#define PCI_RES_SAVE_CONFIGURATION 0x01 /**< PCI response value save configuration */ +#define PCI_RES_ASSIGN_FRAME_ID_RANGE 0x01 /**< PCI response value assign frame id range */ + +/* Identifire user defined */ +#define LIN_READ_USR_DEF_MIN 32U /**< Min user defined */ +#define LIN_READ_USR_DEF_MAX 63U /**< Max user defined */ + +/* Identification */ +#define LD_ID_NO_RESPONSE 0x52 /**< Positive response */ +#define LD_NEGATIVE_RESPONSE 0x53 /**< Negative response */ +#define LD_POSITIVE_RESPONSE 0x54 /**< Positive response */ + + + +/** +* @var typedef l_u8 lin_tl_pdu_data[8] +* PDU data +*/ +typedef l_u8 lin_tl_pdu_data[8]; + +/**********************************************************************/ +/*************** LOW LEVEL DRIVER *******************/ +/**********************************************************************/ + +/** +* @enum lin_checksum_type +* Checksum type +*/ +typedef enum { + NORMAL_CHECKSUM, /**< NORMAL_CHECKSUM */ + ENHANCED_CHECKSUM /**< ENHANCED_CHECKSUM */ +} lin_checksum_type; + +/** +* @enum lin_lld_event_id +* Event id +*/ +typedef enum { + LIN_LLD_PID_OK, /**< LIN_LLD_PID_OK */ + LIN_LLD_TX_COMPLETED, /**< LIN_LLD_TX_COMPLETED */ + LIN_LLD_RX_COMPLETED, /**< LIN_LLD_RX_COMPLETED */ + LIN_LLD_PID_ERR, /**< LIN_LLD_PID_ERR */ + LIN_LLD_FRAME_ERR , /**< LIN_LLD_FRAME_ERR */ + LIN_LLD_CHECKSUM_ERR, /**< LIN_LLD_CHECKSUM_ERR */ + LIN_LLD_READBACK_ERR, /**< LIN_LLD_READBACK_ERR */ + LIN_LLD_NODATA_TIMEOUT, /**< Nodata timeout */ + LIN_LLD_BUS_ACTIVITY_TIMEOUT /**< LIN_LLD_BUS_ACTIVITY_TIMEOUT */ +} lin_lld_event_id; + +/** +* @enum lin_lld_mode +* Low level driver mode +*/ +typedef enum { + LIN_LLD_OK, /**< OK */ + LIN_LLD_INVALID_MODE, /**< Invalid mode */ + LIN_LLD_INVALID_ID, /**< invalid ID */ + LIN_LLD_NO_ID, /**< No ID */ + LIN_LLD_INVALID_TIMEBASE, /**< Invalid timebase */ + LIN_LLD_INVALID_PARA, /**< Invalid parity */ + LIN_LLD_INVALID_IFC /**< Invalid interface */ +} lin_lld_mode; + +#if ((_LIN_SCI_ == 1)|(_LIN_UART_ == 1)) + +#define IDLE 0x00 /**< IDLE state */ +#define SEND_BREAK 0x01 /**< Send break field state */ +#define SEND_PID 0x02 /**< send PID state */ +#define RECV_SYN 0x03 /**< receive synchronize state */ +#define RECV_PID 0x04 /**< receive PID state */ +#define IGNORE_DATA 0x05 /**< ignore data state */ +#define RECV_DATA 0x06 /**< receive data state */ +#define SEND_DATA 0x07 /**< send data state */ +#define SEND_DATA_COMPLETED 0x08 /**< send data completed state */ +#define PROC_CALLBACK 0x09 /**< proceduce callback state */ +#define SLEEP_MODE 0x0A /**< sleep mode state */ +#define UNINIT 0xFF /**< uninitialize state */ + +/** +* @var typedef l_u16 sci_channel_name +* +* @details +* SCI channel +*/ +typedef l_u16 sci_channel_name; +/** +* @var typedef l_u16 uart_channel_name +* +* @details +* UART channel +*/ +#if (_LIN_UART_ == 1) +typedef l_u16 uart_channel_name; +#endif /* (_LIN_UART_ == 1) */ +/** +* @union lin_status +* status of lin driver +*/ +typedef union { + l_u8 byte; /**< a data byte refer to 8 data bits follow */ + struct + { + /* LIN 2.1 */ + l_u8 successful_transfer:1; /**< Transfer flag LIN 2.1*/ + l_u8 error_in_response:1; /**< Error response LIN 2.1*/ + l_u8 bus_activity; /**< Bus activity timeout LIN 2.1*/ + /* J2602 */ + l_u8 framing_error:1; /**< frame error flag J2602*/ + l_u8 checksum_error:1; /**< checksum error flag */ + l_u8 readback_error:1; /**< readback error in J2602 to be called Data Error */ + l_u8 parity_error:1; /**< frame error flag */ + l_u8 reset:1; /**< reset flag (not implemented) */ + } bit; +} lin_status; + +#if (LIN_MODE == _MASTER_MODE_) +/* lin_node struct */ +/** +* @struct lin_node +* contain informations of a lin node +*/ +typedef struct { +#if (_LIN_SCI_ == 1) + tSCI* pSCI; /**< pointer to the SCI peripheral */ +#endif/* (_LIN_SCI_ = 1) */ +#if (_LIN_UART_ == 1) + tUART* pUART; /**< pointer to the UART peripheral */ +#endif /* (_LIN_UART_ = 1) */ + l_bool func; /**< LIN Function : Master=0 or Slave=1 */ + l_u8 ifc; /**< LIN core interface number */ + l_u8 state; /**< LIN-SCI operational state */ + lin_status l_status; /**< LIN status */ + l_u8 cnt_byte; /**< Byte counter used when either transmit and receive data */ + l_u8 *ptr; /**< pointer to Data out/in */ + l_u8 current_id; /**< Current ID */ + l_u8 *response_buffer; /**< Frame data pointer */ + l_u8 pid; /**< PID to send out */ + l_u16 tbit; /**< Tbit */ + l_u16 frame_timeout_cnt; /**< Frame timeout counter */ + l_u16 res_frame_timeout_cnt; /**< ResponseFrame timeout counter */ + l_u16 idle_timeout_cnt; /**< Idle timeout counter */ +} lin_node; +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#endif /* End (_LIN_SCI_ == 1) */ + +/**********************************************************************/ +/*************** Protocol *******************/ +/**********************************************************************/ + +/** +* @enum lin_protocol_handle +* List of protocols +*/ +typedef enum { + LIN_PROTOCOL_21, /**< LIN protocol version 2.1 */ + LIN_PROTOCOL_20, /**< LIN protocol version 2.0 */ + LIN_PROTOCOL_J2602 /**< J2602 protocol */ +} lin_protocol_handle; + +/** +* @typedef lin_word_status_str +* status of lin bus +* @union wstatus +* word status +*/ +typedef union wstatus { + l_u16 word; /**< this is a word, refer to 16 data bits follow*/ + /** + * @struct bit + * + */ + struct { + l_u16 error_in_res:1; /**< Error in response */ + l_u16 successful_transfer:1; /**< Successful transfer */ + l_u16 overrun:1; /**< Overrun */ + l_u16 gotosleep:1; /**< Goto sleep */ + l_u16 bus_activity:1; /**< Bus activity */ + l_u16 etf_collision:1; /**< Event trigger collision */ + l_u16 save_conf:1; /**< Save configuration */ + l_u16 dummy:1; /**< Dummy */ + l_u16 last_pid:8; /**< Last PID */ + } bit; /**< these bits contain data of status */ +} lin_word_status_str; + + +/**********************************************************************/ +/*************** Interfaces *******************/ +/**********************************************************************/ +#if (LIN_MODE == _MASTER_MODE_) +/** +* @enum lin_function +* function of lin node (master or slave) +*/ +typedef enum { + _MASTER_, /**< master node */ + _SLAVE_ /**< slave node */ +} lin_function; +extern l_ifc_handle lin_diag_interface; +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/**********************************************************************/ +/*************** Signals *******************/ +/**********************************************************************/ + +/** +* @enum lin_signal_type +* list of signal types +*/ +typedef enum { + LIN_SIG_SCALAR, /**< scalar signal */ + LIN_SIG_ARRAY /**< array signal */ +} lin_signal_type; + +/** +* @enum lin_diagnostic_signal +* List of diagnostic signals +*/ +typedef enum { + MasterReqB0, /**< diagnostic master request bit 0 */ + MasterReqB1, /**< diagnostic master request bit 1 */ + MasterReqB2, /**< diagnostic master request bit 2 */ + MasterReqB3, /**< diagnostic master request bit 3 */ + MasterReqB4, /**< diagnostic master request bit 4 */ + MasterReqB5, /**< diagnostic master request bit 5 */ + MasterReqB6, /**< diagnostic master request bit 6 */ + MasterReqB7, /**< diagnostic master request bit 7 */ + SlaveRespB0, /**< diagnostic slave response bit 0 */ + SlaveRespB1, /**< diagnostic slave response bit 1 */ + SlaveRespB2, /**< diagnostic slave response bit 2 */ + SlaveRespB3, /**< diagnostic slave response bit 3 */ + SlaveRespB4, /**< diagnostic slave response bit 4 */ + SlaveRespB5, /**< diagnostic slave response bit 5 */ + SlaveRespB6, /**< diagnostic slave response bit 6 */ + SlaveRespB7 /**< diagnostic slave response bit 7 */ +} lin_diagnostic_signal; + +/**********************************************************************/ +/*************** General *******************/ +/**********************************************************************/ + +/* Node atrribute */ +/** +* @struct lin_product_id +* product id structure +*/ +typedef struct { + l_u16 supplier_id; /**< Supplier ID */ + l_u16 function_id; /**< Function ID */ + l_u8 variant; /**< Variant value */ +} lin_product_id; + +/** +* @struct lin_node_attribute +* attributies of lin node +*/ +typedef struct { + lin_protocol_handle lin_protocol; /**< LIN protocol used in node */ + l_u8 configured_NAD; /**< NAD value used in configuration command */ + l_u8 initial_NAD; /**< Intial NAD */ + lin_product_id product_id; /**< Product ID */ + l_signal_handle response_error; /**< Signal used to update response error */ + l_u8 num_frame_have_esignal; /*!< Number of frame contain error signal */ + l_u16* response_error_byte_offset_ptr; /*!< Byte offset of response error signal */ + l_u8* response_error_bit_offset_ptr; /*!< Bit offset of response error signal */ + l_u8 num_of_fault_state_signal; /**< Num of Fault state signal */ + const l_signal_handle *fault_state_signal; /**< List of fault state signal */ + l_u16 P2_min; /**< P2 min */ + l_u16 ST_min; /**< ST min */ + l_u16 N_As_timeout; /**< N_As_timeout */ + l_u16 N_Cr_timeout; /**< N_Cr_timeout */ +} lin_node_attribute; + +/**********************************************************************/ +/*************** Frame *******************/ +/**********************************************************************/ + +/** +* @enum lin_frame_type +* types of frame +*/ +typedef enum { + LIN_FRM_UNCD = 0x00, /**< Unconditional frame */ + LIN_FRM_EVNT = 0x01, /**< Event triggered frame.*/ + LIN_FRM_SPRDC = 0x10, /**< Sporadic frame.*/ + LIN_FRM_DIAG = 0x11 /**< Diagnostic frame.*/ +} lin_frame_type; + +/** +* @enum lin_frame_response +* lin frame response +*/ +typedef enum { + LIN_RES_NOTHING = 0x00, /**< This frame does not require to response.*/ + LIN_RES_PUB = 0x01, /**< Publisher response.*/ + LIN_RES_SUB = 0x10 /**< Subscriber response.*/ +} lin_frame_response; + +/** +* @struct lin_frame_struct +* Informations of frame +*/ +typedef struct { + lin_frame_type frm_type; /**< Frame information (unconditional or event triggered..) */ + l_u8 frm_len; /**< Length of the frame */ + lin_frame_response frm_response; /**< action response when received PID */ + l_u16 frm_offset; /**< Frame byte offset in frame buffer */ + l_u16 flag_offset; /**< Flag byte offset in flag buffer */ + l_u8 flag_size; /**< Flag size in flag buffer */ + l_u8 *frame_data; /**< List of Signal to which the frame is associated and its offset */ +} lin_frame_struct; + +/** +* @struct lin_associate_frame_struct +* Informations of associated frame +*/ +typedef struct { + l_u8 num_asct_uncn_pid; /**< Number of associated unconditional frame ID*/ + const l_u8* act_uncn_frm; /**< Associated unconditional frame ID. */ +#if LIN_MODE == _MASTER_MODE_ + l_u8 coll_resolver_id; /**< Collision resolver index in the schedule table, used in event trigger frame case MASTER*/ +#endif /* End LIN_MODE == _MASTER_MODE_ */ +} lin_associate_frame_struct; + +/**********************************************************************/ +/*************** Schedule table *******************/ +/**********************************************************************/ + +/* Structures of Diagnostic queue */ +/** +* @typedef l_u8 lin_tl_queue[8] +* lin transport layer queue +*/ +typedef l_u8 lin_tl_queue[8]; + +#if (LIN_MODE == _MASTER_MODE_) + +/** +* @enum lin_sch_tbl_type +* Type of schedule table +*/ +typedef enum { + LIN_SCH_TBL_NULL, /**< Run nothing */ + LIN_SCH_TBL_NORM, /**< Normal schedule table*/ + LIN_SCH_TBL_DIAG, /**< Diagnostic schedule table */ + LIN_SCH_TBL_GOTO, /**< Goto sleep schedule table */ + LIN_SCH_TBL_COLL /**< Collision schedule table */ +} lin_sch_tbl_type; + +/** +* @struct lin_schedule_data +* lin schedule structure +*/ +typedef struct { + l_frame_handle frm_id; /**< Frame ID, in case of unconditional or event triggered frame. For sporadic frame the value will be 0 (zero). */ + l_u8 delay_integer; /**< Actual slot time in INTEGER for one frame.*/ + lin_tl_queue tl_queue_data; /**< Data used in case of diagnostic or configuration frame*/ +} lin_schedule_data; + +/** +* @struct lin_schedule_struct +* Informations of schedule +*/ +typedef struct { + l_u8 num_slots; /**< Number of frame slots in the schedule table.*/ + lin_sch_tbl_type sch_tbl_type; /**< Schedule table type (configuration and normal)*/ + const lin_schedule_data *ptr_sch_data; /**< Address of the schedule table.*/ +} lin_schedule_struct; + +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/**********************************************************************/ +/*************** Transport Layer /Diagnostic ****************/ +/**********************************************************************/ + +/* Diagnostic mode */ +/** +* @enum l_diagnostic_mode +* Diagnostic mode +*/ +#if (XGATE_SUPPORT == 1) +#pragma align on +#endif /* End (XGATE_SUPPORT == 1) */ +typedef enum { + DIAG_NONE, /**< diagnostic none */ + DIAG_INTER_LEAVE_MODE, /**< diagnostic interleave mode */ + DIAG_ONLY_MODE /**< diagnostic only mode */ +} l_diagnostic_mode; +#if (XGATE_SUPPORT == 1) +#pragma align off +#endif /* End (XGATE_SUPPORT == 1) */ + +/** +* @enum lin_service_status +* Status of the last configuration call for LIN 2.1 +*/ +#if (XGATE_SUPPORT == 1) +#pragma align on +#endif /* End (XGATE_SUPPORT == 1) */ +typedef enum { + LD_SERVICE_BUSY, /**< Service is ongoing */ + LD_REQUEST_FINISHED, /**< The configuration request has been completed */ + LD_SERVICE_IDLE, /**< The configuration request/response combination has been completed*/ + LD_SERVICE_ERROR /**< The configuration request or response experienced an error */ +} lin_service_status; +#if (XGATE_SUPPORT == 1) +#pragma align off +#endif /* End (XGATE_SUPPORT == 1) */ + +/** +* @enum lin_last_cfg_result +* Status of the last configuration call completed for J2602 +*/ +typedef enum { + LD_SUCCESS, /**< The service was successfully carried out */ + LD_NEGATIVE, /**< The service failed, more information can be found by parsing error_code */ + LD_NO_RESPONSE, /**< No response was received on the request */ + LD_OVERWRITTEN /**< The slave response frame has been overwritten by another operation */ +} lin_last_cfg_result; + +/* TL support */ + +/*------------------------ Transport layer multi frames -----------------------*/ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* TL Descriptor used in the TL/Diagnostic */ + +#define SF 0x00 /**< single frame */ +#define FF 0x01 /**< first frame */ +#define CF 0x02 /**< consecutive frame */ + +/** +* @enum ld_queue_status +* status of queue +*/ +typedef enum { + LD_NO_DATA, /**< Queue is empty, has no data */ + LD_DATA_AVAILABLE, /**< data in queue is available */ + LD_RECEIVE_ERROR, /**< receive data is error */ + LD_QUEUE_FULL, /**< the queue is full */ + LD_QUEUE_AVAILABLE, /**< queue is available for insert data */ + LD_QUEUE_EMPTY, /**< queue is empty */ + LD_TRANSMIT_ERROR /**< error while transmitting */ +} ld_queue_status; + +/** +* @enum lin_message_status +* status of lin message +*/ +typedef enum { + LD_NO_MSG, /**< no message */ + LD_IN_PROGRESS, /**< in progress */ + LD_COMPLETED, /**< completed */ + LD_FAILED, /**< failed */ + LD_N_AS_TIMEOUT, /**< N_As timeout */ + LD_N_CR_TIMEOUT, /**< N_Cr timeout */ + LD_WRONG_SN /**< wrong sequence number */ +} lin_message_status; + +/** +* enum lin_diagnostic_state +* lin diagnostic state +*/ +typedef enum { + LD_DIAG_IDLE, /**< Diagnostic IDLE */ + LD_DIAG_TX_ACTIVE, /**< Diagnostic transmit active */ + LD_DIAG_TX_PHY, /**< Diagnostic transmit physical */ + LD_DIAG_INTERLEAVED_TX, /**< Diagnostic transmit in interleave mode */ + LD_DIAG_RX_PHY, /**< Diagnostic receive in physical */ + LD_DIAG_INTERLEAVED_RX, /**< Diagnostic receive in interleave mode */ + LD_DIAG_RX_FUNCTIONAL /**< Diagnostic receive functional request */ +} lin_diagnostic_state; + +/** +* @enum lin_message_timeout_type +* types of message timeout +*/ +typedef enum { + LD_NO_CHECK_TIMEOUT, /**< No check timeout */ + LD_CHECK_N_AS_TIMEOUT, /**< check N_As timeout */ + LD_CHECK_N_CR_TIMEOUT /**< check N_Cr timeout */ +} lin_message_timeout_type; + +/** +* @struct lin_transport_layer_queue +* transport layer queue +*/ +typedef struct { + l_u16 queue_header; /**< the first element of queue */ + l_u16 queue_tail; /**< the last element of queue */ + ld_queue_status queue_status; /**< status of queue */ + l_u16 queue_current_size; /**< current size */ + const l_u16 queue_max_size; /**< maximume size */ + lin_tl_pdu_data *tl_pdu; /**< PDU data */ +} lin_transport_layer_queue; + +#else /* single frame support */ + +typedef enum { + LD_NO_CHECK_TIMEOUT, /**< No check timeout */ + LD_CHECK_N_AS_TIMEOUT /**< check N_As timeout */ +} lin_message_timeout_type; + +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + +#if (LIN_MODE == _MASTER_MODE_) +/* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +#define INTERLEAVE_MAX_TIMEOUT 15 +/** +* @struct lin_tl_descriptor +* transport layer description +*/ +#if (XGATE_SUPPORT == 1) +#pragma align on +#endif /* End (XGATE_SUPPORT == 1) */ +typedef struct { + /* Declaration for both Master and Slave interface */ + lin_transport_layer_queue *tl_tx_queue; /**< pointer to transmit queue on TL */ + lin_transport_layer_queue *tl_rx_queue; /**< pointer to receive queue on TL */ + + /* Declaration only for Master interface */ + /* message information in transmit queue */ + lin_message_status tl_rx_msg_status; /**< cooked rx status */ + l_u16 tl_rx_msg_index; /**< index of message in queue */ + l_u16 tl_rx_msg_size; /**< Size of message in queue */ + lin_message_status tl_receive_msg_status; /**< receive message status */ + + /* message information in receive queue */ + lin_message_status tl_tx_msg_status; /**< cooked tx status */ + l_u16 tl_tx_msg_index; /**< index of message in queue */ + l_u16 tl_tx_msg_size; /**< Size of message in queue */ + + lin_last_cfg_result tl_last_cfg_result; /**< Status of the last configuration service in LIN 2.0, J2602 */ + l_u8 tl_last_RSID; /**< RSID of the last node configuration service */ + l_u8 tl_ld_error_code; /**< Error code in case of positive response */ + + l_u8 tl_no_of_pdu; /**< number of received pdu */ + l_u8 tl_frame_counter; /**< frame counter in received message */ + + lin_message_timeout_type tl_check_timeout_type; /**< timeout type */ + l_u16 tl_check_timeout; /**< timeout counter*/ + + l_u8 *tl_ident_data; /**< To store address of RAM area contain response */ + + l_u8 tl_interleave_timeout_counter; /**< interleaved timeout counter */ + const l_u8 number_support_sid; + l_u8 *tl_service_supported; /*!< diagnostic service supported */ + l_u8 *tl_service_flags; /**< diagnostic service flags */ + /* Declaration only for Slave interface */ + l_u8 tl_slaveresp_cnt; /**< Slave Response data counter */ +} lin_tl_descriptor; + +/** +* @struct lin_tl_descriptor1 +* transport layer description J2602 +*/ +typedef struct { + const lin_tl_pdu_data *tl_tx_single_pdu; /**< pointer to transmit PDU data of Single Frame on TL */ + const lin_tl_pdu_data *tl_rx_single_pdu; /**< pointer to receive PDU data of Single Frame on TL */ + lin_tl_pdu_data *tl_current_tx_pdu_ptr; /**< current PDU pointer*/ + lin_tl_pdu_data *tl_current_rx_pdu_ptr; /**< current PDU pointer*/ + + /* Declaration only for Master interface */ + l_u8 tl_cnt_to_send; /**< Send counter, if=0 no data, #0 number of PDU need to be sent */ + lin_service_status tl_service_status; /**< Status of the last configuration service */ + + lin_last_cfg_result tl_last_cfg_result; /**< Status of the last configuration service in LIN 2.0, J2602 */ + l_u8 tl_last_RSID; /**< RSID of the last node configuration service */ + l_u8 tl_ld_error_code; /**< Error code in case of positive response */ + l_u8 *tl_ident_data; /**< To store address of RAM area contain response */ + /* End of declaration for only Master interface */ + const l_u8 number_support_sid; + l_u8 *tl_service_supported; /*!< diagnostic service supported */ + l_u8 *tl_service_flags; /*!< diagnostic service flags */ + /* Declaration only for Slave interface */ + l_u8 tl_slaveresp_cnt; /**< Slave Response data counter */ + /* End of declaration only for Slave interface */ +} lin_tl_descriptor1; + +/** @enum diag_interleaved_state +* state of diagnostic interleaved mode */ +typedef enum { + DIAG_NOT_START, /**< not into slave response schedule with interleaved mode */ + DIAG_NO_RESPONSE, /**< master send 0x3D but slave does not response */ + DIAG_RESPONSE /**< response receive */ +} diag_interleaved_state; +#else /* Single frame support */ +/** +* @struct lin_tl_descriptor1 +* transport layer description J2602 +*/ +typedef struct { + const lin_tl_pdu_data *tl_tx_single_pdu; /**< pointer to transmit PDU data of Single Frame on TL */ + const lin_tl_pdu_data *tl_rx_single_pdu; /**< pointer to receive PDU data of Single Frame on TL */ + lin_tl_pdu_data *tl_current_tx_pdu_ptr; /**< current PDU pointer*/ + lin_tl_pdu_data *tl_current_rx_pdu_ptr; /**< current PDU pointer*/ + + /* Declaration only for Master interface */ + l_u8 tl_cnt_to_send; /**< Send counter, if=0 no data, #0 number of PDU need to be sent */ + lin_service_status tl_service_status; /**< Status of the last configuration service */ + + lin_last_cfg_result tl_last_cfg_result; /**< Status of the last configuration service in LIN 2.0, J2602 */ + l_u8 tl_last_RSID; /**< RSID of the last node configuration service */ + l_u8 tl_ld_error_code; /**< Error code in case of positive response */ + l_u8 *tl_ident_data; /**< To store address of RAM area contain response */ + /* End of declaration for only Master interface */ + const l_u8 number_support_sid; + l_u8 *tl_service_supported; /*!< diagnostic service supported */ + l_u8 *tl_service_flags; /*!< diagnostic service flags */ + /* Declaration only for Slave interface */ + l_u8 tl_slaveresp_cnt; /**< Slave Response data counter */ + /* End of declaration only for Slave interface */ +} lin_tl_descriptor; + +extern lin_message_timeout_type tl_check_timeout_type_array[LIN_NUM_OF_IFCS]; +extern l_u16 tl_check_timeout_array[LIN_NUM_OF_IFCS]; +#if (XGATE_SUPPORT == 1) +#pragma align off +#endif /* End (XGATE_SUPPORT == 1) */ +#endif /*End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_)*/ +/* End of TL support */ + +/**********************************************************************/ +/*************** Configuration *******************/ +/**********************************************************************/ +/** +* @struct lin_configuration +* configuration structure +*/ +typedef struct { + lin_protocol_handle lin_protocol_version; /**< Protocol version */ + lin_protocol_handle lin_language_version; /**< Language version */ + const l_u16 baud_rate; /**< Cluster baudrate */ + lin_function function; /**< Function (_MASTER_ or _SLAVE_) */ + lin_node_attribute *node_attribute; /**< Node attribute */ + /* LIN data pointer */ + l_u8 *response_buffer; /**< Response buffer */ + l_u8 *successful_transfer; /**< Transfer flag */ + l_u8 *error_in_response; /**< Error response */ + l_u8 *goto_sleep_flg; /**< Goto sleep flag */ + l_u8 *current_pid; /**< Current pid */ + lin_word_status_str *word_status; /**< Word status */ + /* Protocol */ + l_u8 timebase; /**< Timebase only used for master */ + l_u8 *diag_signal_tbl; /**< Diagnostic signal list */ + l_u8 num_of_frames; /**< Number of frame except diagnostic frames */ + l_u8 frame_start; /**< Start index of frame list */ + const lin_frame_struct *frame_tbl; /**< Frame list except diagnostic frames */ + l_u8 *frame_flg; /**< Frame flag */ + l_u8 num_of_schedules; /**< Number of schedule table */ + l_u8 schedule_start; /**< Start index of schedule table list */ + const lin_schedule_struct *schedule_tbl; /**< Shedule table list */ + l_u8 *schedule_start_entry; /**< Start entry of each schedule table */ + l_u8 *next_transmit_tick; /**< Used to count the next transmit tick */ + l_u8 *active_schedule_id; /**< Active schedule table id */ + l_u8 *previous_schedule_id; /**< Previous schedule table id */ + l_u8 *diagnostic_frame_to_send; /**< Number of diagnostic frame to send */ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_diagnostic_mode *diagnostic_mode; /**< Diagnostic mode */ +#else /* Single frame support */ + l_diagnostic_mode diagnostic_mode; /**< Diagnostic mode */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + l_u8 *configuration_RAM; /**< Configuration in RAM */ + const l_u16 *configuration_ROM; /**< Configuration in ROM */ + /* TL support*/ + lin_tl_descriptor *tl_desc; /**< TL Configuration */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_diagnostic_state *tl_diag_state; /**< diagnostic state */ + lin_service_status *tl_service_status; /**< Status of the last configuration service */ + diag_interleaved_state *tl_diag_interleave_state; /**< state of diagnostic interleaved mode */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} lin_configuration; +/* End of data definition */ +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/***** Macros *****/ +#define BIT(A,B) (((A)>>(B))&0x01) /**< return bit has position \a B in byte \a A, A is the variable while */ + +/* Global functions */ +/** +* @def CALLBACK_HANDLER(iii, event_id, pid) +* call lin_pid_response_callback_handler function in MASTER mode +*/ +#if (LIN_MODE == _MASTER_MODE_) +#define CALLBACK_HANDLER(iii, event_id, pid) lin_pid_response_callback_handler((iii), (event_id), (pid)) +#else +#define CALLBACK_HANDLER(iii, event_id, pid) lin_pid_response_callback_handler((event_id), (pid)) +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#if LIN_MODE == _MASTER_MODE_ +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_init (l_ifc_handle iii) +* @brief This function will initialize the specified interface (if available) +* with the predefine configuration +* +* @param iii [IN] lin interface handle +* +* @return #l_u8 +*
0 if successful, else return error code +* +* @SDD_ID LIN_SDD_216 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw +* -# #l_u8 ret +*
return this variable at the end of function +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function will initialize the specified interface (if available) +* with the predefine configuration +* +* @see #lin_lld_sci_init +* @see #lin_lld_xgate_init +* @see #lin_lld_slic_init +* @see #lin_lld_gpio_init +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_init(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_deinit (l_ifc_handle iii) +* @brief This function disconnect the node from the cluster and +* free all hardware used +* +* @param iii [IN] lin interface handle +* +* @return #l_u8 +*
0 if successful, else return error code +* +* @SDD_ID LIN_SDD_217 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw +* -# #l_u8 ret +*
return this variable at the end of function +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function disconnect the node from the cluster and +* free all hardware used +* +* @see #lin_lld_sci_deinit +* @see #lin_lld_xgate_deinit +* @see #lin_lld_slic_deinit +* @see #lin_lld_gpio_deinit +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_deinit(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_get_state ( l_ifc_handle iii ) +* +* @brief +* This function gets current state of an interface +*@param iii [IN] lin interface handle +* +* @return #l_u8 +* +* @SDD_ID N/A +* @endif +* +* @local_var +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function gets current state of an interface +* +* @see #lin_lld_sci_get_state +* @see #lin_lld_xgate_get_state +* @see #lin_lld_slic_get_state +* @see #lin_lld_gpio_get_status +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_get_state(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_tx_header (l_ifc_handle iii, l_u8 pid) +* @brief Master transmit header +* +* @param iii [IN] lin interface handle +* @param pid [IN] ID of the header to be sent +* +* @return #void +* +* @SDD_ID LIN_SDD_219 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Issues the LIN header with specified ID. The function cause the LIN frame transmission, +* applicable for the master only +* +* @see #lin_lld_sci_tx_header +* @see #lin_lld_xgate_tx_header +*//*END*----------------------------------------------------------------------*/ +void lin_lld_tx_header(l_ifc_handle iii, l_u8 pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_tx_wake_up (l_ifc_handle iii) +* @brief This function send wakeup signal +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_220 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function send wakeup signal +* +* @see #lin_lld_sci_tx_wake_up +* @see #lin_lld_xgate_tx_wake_up +* @see #lin_lld_slic_tx_wake_up +* @see #lin_lld_gpio_tx_wake_up +*//*END*----------------------------------------------------------------------*/ +void lin_lld_tx_wake_up(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_int_enable (l_ifc_handle iii) +* +* @brief Enable the interrupt related the interface +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_221 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function send wakeup signal +* +* @see #lin_lld_sci_int_enable +* @see #lin_lld_xgate_int_enable +* @see #lin_lld_slic_int_enable +* @see #lin_lld_gpio_int_enable +*//*END*----------------------------------------------------------------------*/ +void lin_lld_int_enable(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_int_disable (l_ifc_handle iii) +* +* @brief +* Disable the interrupt related the interface +* +* @param iii [IN] lin interface handle +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_222 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Disable the interrupt related the interface +* +* @see #lin_lld_sci_int_disable +* @see #lin_lld_xgate_int_disable +* @see #lin_lld_slic_int_disable +* @see #lin_lld_gpio_int_disable +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_int_disable(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_ignore_response (l_ifc_handle iii) +* +* @brief +* Let the low level driver ignore the next respond +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_223 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Let the low level driver ignore the next respond +* (i.e. because the PID is not relevant) +* +* @see #lin_lld_sci_ignore_response +* @see #lin_lld_xgate_ignore_response +* @see #lin_lld_slic_ignore_response +* @see #lin_lld_gpio_ignore_response +*//*END*----------------------------------------------------------------------*/ +void lin_lld_ignore_response(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_set_low_power_mode (l_ifc_handle iii) +* +* @brief +* Let the low level driver go to low power mode +* +* @param iii [IN] lin interface handle +* +* @return #void +* +* @SDD_ID LIN_SDD_224 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Let the low level driver go to low power mode +* (In sleep mode for example) +* +* @see #lin_lld_sci_set_low_power_mode +* @see #lin_lld_xgate_set_low_power_mode +* @see #lin_lld_slic_set_low_power_mode +* @see #lin_lld_gpio_set_low_power_mode +*//*END*----------------------------------------------------------------------*/ +void lin_lld_set_low_power_mode(l_ifc_handle iii); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_set_response (l_ifc_handle iii, l_u8 response_length) +* +* @brief +* Switch the low level driver to transmit response state +* +* @param iii [IN] lin interface handle +* @param response_length [IN] length of response +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_225 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* -# #lin_ifc_configuration +* +* @details +* Switch the low level driver to transmit response state +* (RX Request for response) +* +* @see #lin_lld_sci_tx_response +* @see #lin_lld_xgate_tx_response +* @see #lin_lld_slic_tx_response +* @see #lin_lld_gpio_tx_response +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_set_response(l_ifc_handle iii, l_u8 response_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_rx_response (l_ifc_handle iii, l_u8 response_length) +* +* @brief +* Switch the low level driver to receiving respond state +* +* @param iii [IN] lin interface handle +* @param response_length [IN] length of response +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_226 +* @endif +* +* @local_var +* -# #lin_hardware_name lin_hw Indicator of LIN HW +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Switch the low level driver to receiving respond state +* +* @see #lin_lld_sci_rx_response +* @see #lin_lld_xgate_rx_response +* @see #lin_lld_slic_rx_response +* @see #lin_lld_gpio_rx_response +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_rx_response(l_ifc_handle iii, l_u8 response_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_set_etf_collision_flag (l_ifc_handle iii) +* +* @brief +* Set flag for collision in event trigger frame +* +* @param +* @param +* +* @return #void +* +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @local_var +* +* @details +* Set flag for collision in event trigger frame* +*//*END*----------------------------------------------------------------------*/ +void lin_lld_set_etf_collision_flag( + /* [IN] interface identifier */ + l_ifc_handle iii); +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_clear_etf_collision_flag (l_ifc_handle iii) +* +* @brief +* Clear flag for collision in event trigger frame +* +* @param +* @param +* +* @return #void +* +* +* @SDD_ID LIN_SDD_ +* @endif +* +* @local_var +* +* @details +* Clear flag for collision in event trigger frame* +*//*END*----------------------------------------------------------------------*/ +void lin_lld_clear_etf_collision_flag( + /* [IN] interface identifier */ + l_ifc_handle iii); + +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +#if (LIN_MODE == _SLAVE_MODE_) + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_init ( void ) +* +* @brief +* Initialize the specified interface +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_227 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function will initialize the specified interface (if available) +* with the predefine configuration +* +* @see #lin_lld_sci_init +* @see #lin_lld_xgate_init +* @see #lin_lld_slic_init +* @see #lin_lld_gpio_init +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_init(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_deinit ( void ) +* +* @brief +* disconnect the node from the cluster +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_228 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function disconnect the node from the cluster and +* free all hardware used +* +* @see #lin_lld_sci_deinit +* @see #lin_lld_xgate_deinit +* @see #lin_lld_slic_deinit +* @see #lin_lld_gpio_deinit +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_deinit(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_get_status ( void ) +* +* @brief +* This function gets current status of an interface +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_229 +* @endif +* +* @local_var +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function gets current status of an interface +* +* @see #lin_lld_sci_get_status +* @see #lin_lld_xgate_get_status +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_get_status(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_get_state ( void ) +* +* @brief +* This function gets current state of an interface +* +* @return #l_u8 +* +* @SDD_ID N/A +* @endif +* +* @local_var +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function gets current state of an interface +* +* @see #lin_lld_sci_get_state +* @see #lin_lld_xgate_get_state +* @see #lin_lld_slic_get_state +* @see #lin_lld_gpio_get_status +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_get_state(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_tx_wake_up ( void ) +* +* @brief +* This function send wakeup signal +* +* @return #void +* +* @SDD_ID LIN_SDD_230 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* This function send wakeup signal +* +* @see #lin_lld_sci_tx_wake_up +* @see #lin_lld_xgate_tx_wake_up +* @see #lin_lld_slic_tx_wake_up +* @see #lin_lld_gpio_tx_wake_up +*//*END*----------------------------------------------------------------------*/ +void lin_lld_tx_wake_up(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_int_enable ( void ) +* +* @brief +* Enable the interrupt related the interface +* +* @return #void +* +* @SDD_ID LIN_SDD_231 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Enable the interrupt related the interface +* +* @see #lin_lld_sci_int_enable +* @see #lin_lld_xgate_int_enable +* @see #lin_lld_slic_int_enable +* @see #lin_lld_gpio_int_enable +*//*END*----------------------------------------------------------------------*/ +void lin_lld_int_enable(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_int_disable ( void ) +* +* @brief +* Disable the interrupt related the interface +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_232 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Disable the interrupt related the interface +* +* @see #lin_lld_sci_int_disable +* @see #lin_lld_xgate_int_disable +* @see #lin_lld_slic_int_disable +* @see #lin_lld_gpio_int_disable +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_int_disable(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_ignore_response ( void ) +* +* @brief +* Let the low level driver ignore the next respond +* +* @return #void +* +* @SDD_ID LIN_SDD_233 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Let the low level driver ignore the next respond +* (i.e. because the PID is not relevant) +* +* @see #lin_lld_sci_ignore_response +* @see #lin_lld_xgate_ignore_response +* @see #lin_lld_slic_ignore_response +* @see #lin_lld_gpio_ignore_response +*//*END*----------------------------------------------------------------------*/ +void lin_lld_ignore_response(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_set_low_power_mode ( void ) +* +* @brief +* Let the low level driver go to low power mode +* +* @return #void +* +* @SDD_ID LIN_SDD_234 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Let the low level driver go to low power mode +* (In sleep mode for example) +* +* @see #lin_lld_uart_set_low_power_mode +* @see #lin_lld_sci_set_low_power_mode +* @see #lin_lld_xgate_set_low_power_mode +* @see #lin_lld_slic_set_low_power_mode +* @see #lin_lld_gpio_set_low_power_mode +*//*END*----------------------------------------------------------------------*/ +void lin_lld_set_low_power_mode(void); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_set_response (l_u8 response_length) +* +* @brief +* Switch the low level driver to transmit response state +* +* @param response_length [IN] length of response +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_235 +* @endif +* +* @local_var +* -# #l_u8 ret +* +* @static_global_var +* -# #lin_virtual_ifc +* -# #lin_lld_response_buffer +* +* @details +* Switch the low level driver to transmit response state +* (RX Request for response) +* +* @see #lin_lld_sci_tx_response +* @see #lin_lld_xgate_tx_response +* @see #lin_lld_slic_tx_response +* @see #lin_lld_gpio_tx_response +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_set_response(l_u8 response_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_lld_rx_response (l_u8 response_length) +* +* @brief +* Switch the low level driver to receiving respond state +* +* @param response_length [IN] length of response +* +* @return #l_u8 +* +* @SDD_ID LIN_SDD_236 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Switch the low level driver to receiving respond state +* +* @see #lin_lld_sci_rx_response +* @see #lin_lld_xgate_rx_response +* @see #lin_lld_slic_rx_response +* @see #lin_lld_gpio_rx_response +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_lld_rx_response(l_u8 response_length); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_mcu_reset ( void ) +* +* @brief +* Reset device +* +* @return #void +* +* @SDD_ID LIN_SDD_237 +* @endif +* +* @static_global_var +* -# #lin_virtual_ifc +* +* @details +* Reset device +*//*END*----------------------------------------------------------------------*/ +void lin_lld_mcu_reset(void); + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_lld_timer_init ( void ) +* +* @brief +* Initialize the timer +* +* @return #void +* +* @SDD_ID LIN_SDD_215 +* @endif +* +* @details +* Initialize the timer +* +* @see #lin_lld_timer_S12X_init +* @see #lin_lld_timer_S12_init +* @see #lin_lld_timer_S08_init +*//*END*----------------------------------------------------------------------*/ +void lin_lld_timer_init(void); + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_checksum (l_u8 *buffer, l_u8 raw_pid) +* +* @brief +* Calculate checksum byte +* +* @param *buffer [IN] pointer to buffer +* @param raw_pid [IN] product identifier +* +* @return #l_u8 +*
checksum byte +* +* @SDD_ID LIN_SDD_214 +* @endif +* +* @local_var +* -# #l_u8 length +* -# #l_u16 check_sum +* +* @details +* Calculate checksum byte +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_checksum(l_u8 *buffer, l_u8 raw_pid); + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn l_u8 lin_process_parity (l_u8 pid, l_u8 type) +* +* @brief +* Check parity and generate PID +* +* @param pid [IN] product identifier +* @param type [IN] check parity or make parity +* +* @return #l_u8 +*
#pid if checkparity ok, otherwise return 0xFF +* +* @SDD_ID LIN_SDD_213 +* @endif +* +* @local_var +* -# #_lu8 parity +* -# #l_u8 ret +* +* @details +* Check parity and generate PID +* XGATE Module not use this routine +*//*END*----------------------------------------------------------------------*/ +l_u8 lin_process_parity(l_u8 pid, l_u8 type); +/*****************************************************************/ +/**** extern variables ****/ +/*****************************************************************/ +/***** Common variables *****/ +extern const lin_frame_struct lin_frame_tbl[LIN_NUM_OF_FRMS]; +extern l_bool lin_frame_flag_tbl[LIN_NUM_OF_FRMS]; +extern l_u8 lin_pFrameBuf[LIN_FRAME_BUF_SIZE]; +extern l_u8 lin_flag_handle_tbl[LIN_FLAG_BUF_SIZE]; +extern volatile l_u8 buffer_backup_data[8]; +extern volatile l_u8 lin_frame_updating_flag_tbl[LIN_NUM_OF_FRMS]; + + +/***** Slave mode variables *****/ +#if LIN_MODE == _SLAVE_MODE_ + #if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) + /* diagnostic flag */ + extern const l_u8 lin_diag_services_supported[_DIAG_NUMBER_OF_SERVICES_]; + extern l_u8 lin_diag_services_flag[_DIAG_NUMBER_OF_SERVICES_]; + #endif +extern const lin_frame_struct lin_frame_tbl[LIN_NUM_OF_FRMS]; +extern l_u8 lin_configuration_RAM[LIN_SIZE_OF_CFG]; +extern l_u8 lin_successful_transfer; +extern l_u8 lin_error_in_response; +extern l_u8 lin_goto_sleep_flg; + +extern l_u8 lin_save_configuration_flg; + +extern l_u8 lin_diag_signal_tbl[16]; +extern const l_signal_handle response_error; +extern l_u8 tl_slaveresp_cnt; +extern lin_word_status_str lin_word_status; +/** +* @var l_u8 frame_index +* @details +* index of frame in frames table +*/ +extern l_u8 frame_index; +extern const l_u16 lin_configuration_ROM[LIN_SIZE_OF_CFG]; /* Configuration stores in ROM */ +extern const lin_product_id product_id; +extern l_u8 tl_slaveresp_cnt; /**< Slave Response data counter */ +/* if single frame */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) +extern lin_tl_pdu_data tx_single_pdu_data; +extern lin_tl_pdu_data rx_single_pdu_data ; +extern lin_tl_pdu_data *tl_current_tx_pdu_ptr; /* current PDU pointer*/ +extern lin_tl_pdu_data *tl_current_rx_pdu_ptr; /* current PDU pointer*/ +extern lin_message_timeout_type tl_check_timeout_type; /**< timeout type */ +extern l_u16 tl_check_timeout; /**< timeout counter*/ +extern lin_service_status tl_service_status; /**< Status of the last configuration service */ +#else /* Multi frame support */ +/*transport layer support */ +extern lin_transport_layer_queue lin_tl_tx_queue; /**< transport layer transmit queue */ +extern lin_transport_layer_queue lin_tl_rx_queue; /**< transport layer receive queue */ +extern lin_message_status tl_rx_msg_status; /**< transport layer rx message status */ +extern l_u16 tl_rx_msg_index; /**< rx message index */ +extern l_u16 tl_rx_msg_size; /**< rx message size */ +extern lin_message_status tl_receive_msg_status; /**< receive message status */ + +extern lin_message_status tl_tx_msg_status; /**< cooked tx status */ +extern l_u16 tl_tx_msg_index; /**< index of message in queue */ +extern l_u16 tl_tx_msg_size; /**< Size of message in queue */ + +extern lin_last_cfg_result tl_last_cfg_result; /**< Status of the last configuration service in LIN 2.0, J2602 */ +extern l_u8 tl_last_RSID; /**< RSID of the last node configuration service */ +extern l_u8 tl_ld_error_code; /**< Error code in case of positive response */ + +extern l_u8 tl_no_of_pdu; /**< number of received pdu */ +extern l_u8 tl_frame_counter; /**< frame counter in received message */ + +extern lin_message_timeout_type tl_check_timeout_type; /**< timeout type */ +extern l_u16 tl_check_timeout; /**< timeout counter*/ + +extern l_u8 *tl_ident_data; /**< To store address of RAM area contain response */ + +/* Declaration only for Slave interface */ +extern lin_diagnostic_state tl_diag_state; /**< diagnostic state */ +extern lin_service_status tl_service_status; /**< Status of the last configuration service */ + +#endif /*End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_)*/ + +extern l_u8 lin_current_pid; +extern l_u8 lin_configured_NAD; +extern const l_u8 lin_initial_NAD; +extern const l_u8 num_frame_have_esignal;/*number of frame contain error signal*/ +extern const l_u16 lin_response_error_byte_offset[];/*_< response_error>*/ +extern const l_u8 lin_response_error_bit_offset[];/*_< response_error>*/ + + + +/* if XGATE Support */ +#if XGATE_SUPPORT == 1 +#pragma DATA_SEG SHARED_DATA /* Define a specific segment to store the data */ +extern const lin_hardware_name lin_virtual_ifc; +extern l_u8 lin_lld_response_buffer[10]; +#pragma DATA_SEG DEFAULT /* Return to default data segment */ +#endif /* End (XGATE_SUPPORT == 1) */ + +/* If XGATE not support */ +#if XGATE_SUPPORT == 0 +extern const lin_hardware_name lin_virtual_ifc; +extern l_u8 lin_lld_response_buffer[10]; +#endif /* End (XGATE_SUPPORT == 0) */ + +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ +/***** Master mode variables *****/ + +#if LIN_MODE == _MASTER_MODE_ + +extern l_u8 lin_save_configuration_flg[LIN_NUM_OF_IFCS]; + +/* if XGATE Support */ +#if XGATE_SUPPORT == 1 +#pragma DATA_SEG SHARED_DATA /* Define a specific segment to store the data */ +extern const lin_hardware_name lin_virtual_ifc[LIN_NUM_OF_IFCS]; +extern l_u8 lin_lld_response_buffer[LIN_NUM_OF_IFCS][10]; +#pragma DATA_SEG DEFAULT /* Return to default data segment */ +#endif /* End (XGATE_SUPPORT == 1) */ + +/* If XGATE not support */ +#if XGATE_SUPPORT == 0 +extern const lin_hardware_name lin_virtual_ifc[LIN_NUM_OF_IFCS]; +#endif /* End (XGATE_SUPPORT == 1) */ + +extern const lin_configuration lin_ifc_configuration[LIN_NUM_OF_IFCS]; +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/*****************************************************************/ +/**** extern api functions ****/ +/*****************************************************************/ +/********************************/ +/******* common core apis *******/ +/*********************************/ +extern l_bool l_sys_init (void); +/*********************************/ +/***** APIs for Master Mode ******/ +/*********************************/ +#if LIN_MODE == _MASTER_MODE_ +extern void l_sch_set (l_ifc_handle iii, l_schedule_handle schedule_iii, l_u8 entry); +extern l_u8 l_sch_tick (l_ifc_handle iii); +extern void l_ifc_goto_sleep (l_ifc_handle iii); +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + +/*********************************/ +/***** APIs for Slave Mode *******/ +/*********************************/ +extern l_bool l_ifc_init (l_ifc_handle iii); +extern void l_ifc_wake_up (l_ifc_handle iii); +extern void l_ifc_rx (l_ifc_handle iii); +extern void l_ifc_tx (l_ifc_handle iii); +extern l_u16 l_ifc_read_status (l_ifc_handle iii); +extern void l_ifc_aux (l_ifc_handle iii); +extern l_u16 l_sys_irq_disable (l_ifc_handle iii); +extern void l_sys_irq_restore (l_ifc_handle iii); +#if LIN_MODE == _SLAVE_MODE_ + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* INITIALIZATION */ +extern void ld_init(void); +/* RAW APIs */ +extern void ld_put_raw(const l_u8* const data); +extern void ld_get_raw(l_u8* const data); +extern l_u8 ld_raw_tx_status(void); +extern l_u8 ld_raw_rx_status(void); +/* COOKED APIs */ +extern void ld_send_message(l_u16 length, const l_u8* const data); +extern void ld_receive_message(l_u16* const length, l_u8* const data); +extern l_u8 ld_tx_status(void); +extern l_u8 ld_rx_status(void); + +extern l_u8 diag_get_flag(l_u8 flag_order); +extern void diag_clear_flag(l_u8 flag_order); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +#if LIN_PROTOCOL == PROTOCOL_J2602 +extern l_bool ld_assign_NAD_j2602(l_u8 dnn); +extern l_bool ld_reconfig_msg_ID(l_u8 dnn); +#endif /* End LIN_PROTOCOL == PROTOCOL_J2602 */ +#endif /* End LIN_MODE == _SLAVE_MODE_) */ + +/* J2602 core apis */ +extern l_bool l_ifc_connect (l_ifc_handle iii); +extern l_bool l_ifc_disconnect (l_ifc_handle iii); + +/****************************************/ +/******** Transport layer APIs **********/ +/****************************************/ +/*********************************/ +/***** APIs for Master Mode ******/ +/*********************************/ +#if LIN_MODE == _MASTER_MODE_ +/* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +extern void ld_init(l_ifc_handle iii); +extern void ld_put_raw(l_ifc_handle iii,const l_u8* const data); +extern void ld_get_raw(l_ifc_handle iii,l_u8* const data); +extern l_u8 ld_raw_tx_status(l_ifc_handle iii); +extern l_u8 ld_raw_rx_status(l_ifc_handle iii); +extern void ld_send_message(l_ifc_handle iii, l_u16 length, l_u8 NAD, const l_u8* const data); +extern void ld_receive_message(l_ifc_handle iii, l_u16* const length, l_u8* const NAD, l_u8* const data); +extern l_u8 ld_tx_status(l_ifc_handle iii); +extern l_u8 ld_rx_status(l_ifc_handle iii); +extern l_u8 diag_get_flag(l_ifc_handle iii,l_u8 flag_order); +extern void diag_clear_flag(l_ifc_handle iii,l_u8 flag_order); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +extern void ld_assign_NAD(l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 function_id, l_u8 new_NAD); +extern void ld_conditional_change_NAD (l_ifc_handle iii, l_u8 NAD, l_u8 id, l_u8 byte, l_u8 mask, l_u8 invert, l_u8 new_NAD); +extern void ld_read_by_id (l_ifc_handle iii, l_u8 NAD, l_u16 supplier_id, l_u16 function_id, l_u8 id, l_u8* const data); + + +/***** J2602 *****/ +#if LIN_PROTOCOL == PROTOCOL_J2602 +extern l_bool ld_is_ready (l_ifc_handle iii); +extern l_u8 ld_check_response (l_ifc_handle iii, l_u8* const RSID, l_u8* const error_code); +extern void ld_assign_frame_id_range (l_ifc_handle iii, l_u8 initial_NAD, l_u16 supplier_id, l_u16 message_id, l_u8 PID); +extern l_bool ld_assign_NAD_j2602(l_ifc_handle iii, l_u8 dnn); +extern l_bool ld_reconfig_msg_ID(l_ifc_handle iii, l_u8 dnn); +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ +/***** LIN21 *****/ +#if LIN_PROTOCOL == PROTOCOL_21 +extern l_u8 ld_is_ready (l_ifc_handle iii); +extern void ld_check_response (l_ifc_handle iii, l_u8* const RSID, l_u8* const error_code); +extern void ld_assign_frame_id_range (l_ifc_handle iii,l_u8 NAD, l_u8 start_index, const l_u8* const PIDs); +#endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + +l_u8 ld_read_by_id_callout(l_ifc_handle iii, l_u8 id, l_u8 *data); + +#endif /* End (LIN_MODE == _MASTER_MODE_) */ + + +#endif /* _LIN_H */ +/** @} */ diff --git a/LIN_Stack/mainpage.h b/LIN_Stack/mainpage.h new file mode 100644 index 0000000..51769cf --- /dev/null +++ b/LIN_Stack/mainpage.h @@ -0,0 +1,340 @@ +/** @mainpage LIN Stack Documentation +* +* @authors FPT Software
Copyright by Freescale Semiconductor, 2008-2016 +*
Copyright by NXP Semiconductors, 2016-2017 +* +*
+*

Introduction

+*
    +*

  • System Architecture

    • +*

    +* The layered architecture of the LIN2.1/ J2602 Stack package is shown on Figure 1. Such architecture approach aims maximum reusability of +* common code base for LIN2.1 and J2602 standards for 8 bit and 16 bit Freescale automotive MCU portfolio.

    +*

    The core API layer of LIN2.1/ J2602 handles initialization, processing and signal based interaction between application and LIN Core. +* The LIN2.1 TL (Transport Layer) provides methods for tester to transmit diagnostic requests.

    +*

    The low level layer offers method of handling signal transmission between user application and hardware independence +* such as byte sending, response receiving, break symbol detection, etc.

    +*

    The physical transport layer of the Stack supports three standard interfaces SCI, SLIC, GPIO to operate with 8 bit and 16 bit MCU hardware.

    +* +* @image html LIN_Stack_Architecture.jpg +*
    Figure 1. LIN Stack Architecture diagram
    +*
    +*

  • Supported Derivatives

    • +*

    The following table displays the list of supported MCU derivatives including the functionalities. Note that all +* derivatives support the LIN 2.0, LIN2.1 and J2602 variant. +* +* @image html support.jpg +*

    Figure 2. Supported Derivatives
    +* +*
    +*

  • LIN Stack Package Components

    • +* +* LIN Stack Package consists of two major parts: +* +*
      +*
    • Node Configuration Tool: PC based script for LIN Stack configuration generation.
      • +* +*
    • LIN Stack: Embedded SW package supporting the LIN 2.0, LIN2.1 and J2602 communication
      • +* +*
    +*
+*

+*

+*

    +*
  1. Node Configuration Tool:

    2. +* +* The Node Configuration Tool is a built-in script of the LIN Stack package which allows user to easily generate the node +* configuration .h and .c files based on LIN Configuration Description File (LCF) and Node Private Description File (LPF). +* Those files are then in compiler integrated with LIN Stack source code and user application and after compilation downloaded +* to the target derivative. Figure 3. shows the diagram of configuration data flow. +* +* @image html ConfigurationData.JPG +*
    Figure 3. Configuration data
    +* +* The LDF file describes a complete LIN cluster including Master/slave mode definition and contains information to handle the cluster.
    +* The NPF file contains information about LIN nodes such as node name, number of interface, MCU clock frequency, used communication channel +* (e.g. SCI channel) and port (e.g. GPIO port), etc., required for full description of the node. +* +*
  2. LIN Stack:

    3. +* +* The Figure 4. shows the details of modules in the LIN Stack package. It also demonstrates the relationship among modules and the direction of function call among them. +* +* @image html LIN_Stack_Architecture1.jpg +*
    Figure 4. LIN Stack Layer Diagram
    +* +* +* LIN Stack software package provides support for LIN2.1, LIN 2.0 and J2602 communication protocols. The stack package is divided into the layers as follows: +* +*
      +*
    1. The lowest layer, Board Support Package (BSP) layer is comprised of codes, which implements the tasks dedicated to specific MCU platform: +* interrupt service routines, i/o port setup, memory handling and so on. There are three interfaces implemented within the stack package: SCI, SLIC, GPIO and XGATE.
      2. +* +*
    2. Low level layer consists of core functions for the LIN protocol such as the frames handling, signals transmission and reception, +* data preparation, etc. Besides, this layer contains common implementation functions for the lowest layer to provide the interface abstraction. +* Function for LIN cluster setup can be found here as well. This layer interacts with the core API layer through low level API functions.
      3. +* +*
    3. Core API layer consists of API functions as defined by the LIN2.1/J2602 specification enabling the user to utilize the LIN2.1/J2602 +* communication within the user application. Both the static and dynamic modes for calling the API functions are supported. The core API layer +* interacts with the low level layer and can be called by such upper layers as LIN2.1 TL API, LIN TL J2602 or application for diagnostic implementation
      4. +* +*
    4. Transport layer stands between the application layer and the core API layer including LIN2.1 TL API and LIN TL J2602. +* This layer provides APIs for the transport protocol, node configuration and diagnostic. For LIN2.1, all components will be +* extended from LIN 2.0 specification. The node configuration for J2602 implements only some functions of LIN 2.0 specification. +* The layer contains some main components below: +*
        +*
      • Transport protocol: +*
          +*
        • LIN2.1: Error handing and communication functions are added to LIN 2.0 specification.
          • +*
        +*
        • +* +*
      • Node configuration: +*
          +*
        • LIN2.1 extends slave configuration and assign frame with ID range to LIN 2.0. The assign frame with ID is removed.
          • +* +*
        • J2602 simplifies LIN 2.0 Node configuration.
          • +*
        +*
        • +* +*
      • Diagnostic: +* +*
          +*
        • LIN 2.0 Diagnostic implements functions as diagnostic service. In the other hand, LIN2.1 Diagnostic implements functions.
          • +*
        +*
        • +*
      +*
      5. +* +*
    5. Application layer is the highest layer which stands for applications of user.
      6. +*
    +*
+* +*

+* +*/ + +/** +* @defgroup LIN_Stack LIN stack */ + +/** @defgroup diagnostic_group Diagnostic services +* @ingroup LIN_Stack +* @brief Diagnostic services defines methods to implement diagnostic data transfer between a master node, respectively a diagnostic tester, and the slave nodes +* @details Three different classes of diagnostic nodes are defined. Class I is using normal signalling and class II and class III uses the transport layer.

+* The master node and the diagnostic tester are connected via a back-bone bus (e.g. CAN). The master +* node shall receive all diagnostic requests addressed to the slave nodes from the +* back-bone bus, and gateway them to the correct LIN cluster(s). Responses from the +* slave nodes shall be gatewayed back to the back-bone bus through the master node.

+* All diagnostic requests and responses (services) addressed to the slave nodes can be +* routed in the network layer (i.e. no application layer routing), if the Diagnostic and +* Transport Layer Protocol of tester back-bone-bus master node fulfills the respective +* needs. In this case, the master node must implement the LIN transport protocol, see +* Transport Layer Specification, as well as the transport protocols used on the back- +* bone busses (e.g. ISO15765-2 on CAN) +*/ + +/** @defgroup transport_group Transport layer API +* @ingroup LIN_Stack +* @brief Transport layer stands between the application layer and the core API layer +* @details +* This layer consists the implementation of data transportation which contains one or more LIN frames. +* It is situated between the application layer and the core API layer including LIN2.1 TL API and LIN TL J2602. +* This layer provides APIs for the transport protocol, node configuration and diagnostic. +* For LIN 2.1, all components will be extended from LIN 2.0 specification. +* The node configuration for J2602 implements only some functions of LIN 2.0 specification +*/ + +/** @defgroup coreapi_group LIN Core API +* @ingroup LIN_Stack +* @brief Refer to chappter 7, LIN 2.1 specification +* @details +* - Core API layer consists of API functions as defined by the LIN2.1/J2602 specification +* - Enabling the user to utilize the LIN2.1/J2602 communication within the user application. +* - Both the static and dynamic modes for calling the API functions are supported. +* - The core API layer interacts with the low level layer and can be called by such upper layers as LIN2.1 TL API, +* LIN TL J2602 or application for diagnostic implementation +*/ + +/** @defgroup lowlevel_group Low level API +* @ingroup LIN_Stack +* @brief Low level layer consists of core functions for the LIN protocol +* @details This layer contains the implementation of LIN protocol such as the frames handling, +* signals transmission and reception, data preparation, etc. Besides, this layer contains common implementation functions +* for the lowest layer to provide the interface abstraction. Function for LIN cluster setup can be found here as well. +* This layer interacts with the core API layer through low level API functions. +*/ + +/** @defgroup bsp_group Board Support Package +* @ingroup LIN_Stack +* @brief BSP (Board Support Package) is the lowest layer of the LIN Stack. +* @details BSP is comprised of codes, +* which implements the tasks dedicated to specific MCU platform: interrupt service routines, i/o port setup, memory handling and so on. +* There are four interfaces implemented within the stack package: SCI, SLIC, GPIO and SCI + XGATE, UART. +*/ + +/** @defgroup common_core_api_group Common Core API +* This group contains general core APIs that used for both protocol LIN 2.1 and J2602. +* +* @ingroup coreapi_group */ +/** @defgroup LIN21_core_api_group LIN 2.1 Specific API +* LIN 2.1 is extended from in LIN 2.0 specification through diagnostic services and few functions were removed as obsolete. +*
    +*
  1. LIN 2.1 is compatible with LIN 2.0: +* +*
      +*
    • A LIN 2.1 master node may handle a LIN 2.0 slave node if the master node also contains +* all functionality of a LIN 2.0 master node, e.g. obsolete functions like Assign frame Id.
      • +* +*
    • A LIN 2.1 slave node can be used in a cluster with a LIN 2.0 master node if the LIN 2.1 slave node +* is pre-configured, i.e. the LIN 2.1 slave node has a valid configuration after reset.
      • +*
    +*
    2. +* +*
  2. Changes between LIN 2.0 and LIN 2.1 +* +* LIN2.1 enhance the capacity of LIN2.0 on event-triggered frame collision handling and diagnostic services supported. +* Besides, several features are add to fulfill powerful capacity of LIN network such as configuration service, assign frame ID range configuration, etc. +*
+* @ingroup coreapi_group */ +/** @defgroup J2602_core_api_group J2602 Specific API +* J2602 protocol is LIN 2.0 based. It contains LIN 2.0's modules to support Signal management, network management, scheduler and J2602 status management. +* The goal of J2602 is to improve the interoperability and interchangeability of LIN devices within a network by resolving those LIN2.0 requirements that are ambiguous, conflicting, or optional. +* Moreover, J2602 provides additional requirements that are not present in LIN2.0. For example: fault tolerant, operation, network topology, etc. +* Different to LIN2.1 protocol, J2602 does not support sporadic and event trigger frames in communication. +* @ingroup coreapi_group */ + +/** @defgroup GPIO_group GPIO interface +* GPIO interface uses GPIO pins to communicates with LIN network. This group provides functions that help higher layers communicate with it. Only 9S12QD4 is supported. +* +* @ingroup bsp_group */ +/** @defgroup SLIC_group SLIC interface +* SLIC (Slave LIN Interface Controller) is one integrated module of MCU, it support MCU communicating with LIN network as slave node. Only 9S08EL32 is supported. +* +* @ingroup bsp_group */ +/** @defgroup SCI_group SCI interface +* This group contains functions that help physical module can communicate with LIN network through SCI module. +* List of supported MCUs with version of SCI and number of SCI channels is in table below: +* @image html SCI_allversions.png +* +* @ingroup bsp_group */ +/** @defgroup UART_group UART interface +* UART interface uses UART to communicate with LIN network. +* @ingroup bsp_group */ +/** @defgroup XGATE_group XGATE interface +* This interface use SCI to communicate with LIN network and XGATE to process MCU's interrupts. +* +* @ingroup bsp_group */ +/** @defgroup resync_group Resynchronize module +* Local interconnect network (LIN) is widely used standard for low cost automotive networks. +* In order to ensure reliable communication via LIN bus, a bus clock of MCU needs to be accurate enough to avoid errors. +* MCU can use crystal or ceramic resonator to provide very accurate bus clocks. However, LIN protocol was designed to allow more cost-effective solution. +* An automatic resynchronization feature allows more cost-effective solution: MCUs can use on-chip oscillators to implement LIN slaves, even though the on-chip oscillators have less accuracy than a crystal. +* The automatic resynchronization module use the LIN SYNC field which is composed of five falling edges to synchronize with the master baud rate. +* The module measures the sync byte field and adjusts the slave bus frequency after each LIN sync field reception from the master node. +* +* @ingroup bsp_group */ + +/** @defgroup autobaud_group Autobaud Feature +* AUTOBAUD is an extensive feature in LIN Driver which allows a peripheral MCU to detect baud rate of LIN bus and adapt its original baud rate to bus value. +* Auto Baud is applied when the baud rate of the incoming data is unknown or the baud rate is fixed with some specific values. +* Each LIN network might have different configuration on such baudrates. +* One MCU can work with different configurations without flashing. +* @ingroup bsp_group */ + +/** @defgroup 9s08qd4_group 9S08QD4 MCU +* @ingroup GPIO_group */ +/** @defgroup 9s08el32_group 9S08EL32 MCU +* @ingroup SLIC_group */ + +/** @defgroup driver_cluster_group Driver and cluster management +* +* @brief initialization for LIN node. +* +* @details +* +* @ingroup common_core_api_group */ +/** @defgroup signal_interract_group Signal interaction +* +* @brief This group contains APIs that help you communicate with signals of LIN node. +* +* @details +* +* @ingroup common_core_api_group */ +/** @defgroup notification_group Notification +* +* @brief This group contains APIs that let you know when a signal's value changed. +* +* @details +* +* @ingroup common_core_api_group */ +/** @defgroup schedule_management_group Schedule management +* +* @brief This group contains APIs that help you manage schedules table in master node only. +* +* @details +* +* @ingroup common_core_api_group */ +/** @defgroup interface_management_group Interface management +* +* @brief This group contains APIs that help you manage interface(s) in LIN node. +* +* @details +* +* @ingroup common_core_api_group */ +/** @defgroup call_out_group User provided call-outs +* +* @brief This group contains APIs which may be called from within the LIN module in order to enable/disable LIN communication interrupts. +* +* @details +* +* @ingroup common_core_api_group */ + +/** @defgroup commontl_api_group Common API +* @brief contains APIs that used for both protocols LIN2.1 and J2602 +* +* @ingroup transport_group */ +/** @defgroup lin21tl_api_group LIN 2.1 specific API +* @brief contains APIs that only used for LIN 2.1 protocol +* +* @ingroup transport_group */ +/** @defgroup j2602tl_api_group J2602 specific API +* @brief contains APIs that only used for J2602 protocol +* +* @ingroup transport_group */ + +/** @defgroup node_configuration_group Node configuration +* +* @brief This group contains APIs that used for node configuration purpose. +* +* @details +* +* @ingroup lin21tl_api_group */ +/** @defgroup node_identification_group Node identification +* +* @brief This group contains API that used for node identification purpose. +* +* @details +* +* @ingroup lin21tl_api_group */ + +/** @defgroup initialization_group Initialization +* +* @brief Initialize transport layer (queues, status, ...). +* +* @details +* +* @ingroup commontl_api_group */ +/** @defgroup raw_api_group Raw API +* +* @brief The raw API is operating on PDU level and it is typically used to gateway PDUs +* between CAN and LIN. +* +* @details Usually, a FIFO is used to buffer PDUs in order to handle the +* different bus speeds. +* +* @ingroup commontl_api_group */ +/** @defgroup cooked_api_group Cooked API +* +* @brief Cooked processing of diagnostic messages manages one complete message at a time. +* +* @ingroup commontl_api_group */ + diff --git a/LIN_Stack/transport/lin_commontl_api.c b/LIN_Stack/transport/lin_commontl_api.c new file mode 100644 index 0000000..2b38c1b --- /dev/null +++ b/LIN_Stack/transport/lin_commontl_api.c @@ -0,0 +1,1359 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2008-2015 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ******************************************************************************/ +/**************************************************************************//** + * @addtogroup commontl_api_group + * @{ + ******************************************************************************/ +/**************************************************************************//** + * + * @file lin_commontl_api.c + * + * @author FPT Software + * + * @brief Common LIN transport layer and configuration functions + * + ******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090409 v1.0 First version + * 20111005 v1.1 Added 3 functions: ld_save_configuration, ld_read_configuration, ld_set_configuration + * + *****************************************************************************/ + +#include "lin_commontl_api.h" +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +#include "lin_commontl_proto.h" +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +/** @} */ +#if LIN_MODE == _MASTER_MODE_ +/********------------- Code supports SINGLE interface ----------------**********/ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + +/* Multi timer selection */ +#ifdef MULTI_TIMER_MODE +extern const l_u16 max_tl_timeout_counter[LIN_NUM_OF_IFCS]; +#endif /* End MULTI_TIMER_MODE */ + +/** @addtogroup initialization_group + * @{ */ +void ld_init (l_ifc_handle iii) +{ + static lin_configuration *conf; + static lin_tl_descriptor *tl_conf; + static lin_transport_layer_queue *tl_queue; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* init transmit queue */ + /* Get TL tx queue */ + tl_queue = tl_conf->tl_tx_queue; + tl_queue->queue_header = 0; + tl_queue->queue_tail = 0; + tl_queue->queue_status = LD_QUEUE_EMPTY; + tl_queue->queue_current_size = 0; + /* init receive queue */ + /* Get TL rx queue */ + tl_queue = tl_conf->tl_rx_queue; + tl_queue->queue_header = 0; + tl_queue->queue_tail = 0; + tl_queue->queue_status = LD_NO_DATA; + tl_queue->queue_current_size = 0; + /* Init transmit message */ + tl_conf->tl_rx_msg_status = LD_COMPLETED; + tl_conf->tl_rx_msg_index = 0; + tl_conf->tl_rx_msg_size = 0; + tl_conf->tl_receive_msg_status = LD_NO_MSG; + + /* Init receive message */ + tl_conf->tl_tx_msg_status = LD_COMPLETED; + tl_conf->tl_tx_msg_index = 0; + tl_conf->tl_tx_msg_size = 0; + + tl_conf->tl_last_cfg_result = LD_SUCCESS; + tl_conf->tl_last_RSID = 0; + tl_conf->tl_ld_error_code = 0; + + tl_conf->tl_frame_counter = 0; + tl_conf->tl_no_of_pdu = 0; + tl_conf->tl_slaveresp_cnt = 0; + + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; +#ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; +#else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; +#endif /* End MULTI_TIMER_MODE */ + + *conf->tl_diag_state = LD_DIAG_IDLE; + *conf->tl_service_status = LD_SERVICE_IDLE; + *conf->diagnostic_mode = DIAG_NONE; + *conf->tl_diag_interleave_state = DIAG_NOT_START; + tl_conf->tl_interleave_timeout_counter = 0; +} +/** @} */ +/** @addtogroup raw_api_group + * @{ */ +void ld_put_raw( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] buffer for the data to be transmitted */ + const l_u8* const data) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_transport_layer_queue *tl_queue; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get transmit queue */ + tl_queue = tl_conf->tl_tx_queue; + + tl_put_raw(data, tl_queue, TRANSMISSION); + tl_conf->tl_slaveresp_cnt++; +} + +void ld_get_raw( + /* [IN] interface name */ + l_ifc_handle iii, + /* [OUT] buffer for store data received */ + l_u8* const data) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_transport_layer_queue *tl_queue; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get transmit queue */ + tl_queue = tl_conf->tl_rx_queue; + + tl_get_raw(data, tl_queue, RECEIVING); +} + +l_u8 ld_raw_tx_status( + /* [IN] interface name */ + l_ifc_handle iii) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_transport_layer_queue *tl_queue; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get transmit queue */ + tl_queue = tl_conf->tl_tx_queue; + + return (l_u8) (tl_queue->queue_status); +} + +l_u8 ld_raw_rx_status( + /* [IN] interface name */ + l_ifc_handle iii) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_transport_layer_queue *tl_queue; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get transmit queue */ + tl_queue = tl_conf->tl_rx_queue; + + return (l_u8) (tl_queue->queue_status); +} +/** @} */ +/** @addtogroup cooked_api_group + * @{ */ +void ld_send_message( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] length of data to send */ + l_u16 length, + /* [IN] Node address of slave node */ + l_u8 NAD, + /* [IN] data to be sent */ + const l_u8* const data) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_transport_layer_queue *tl_queue; + lin_tl_pdu_data pdu; + l_u8 i; + l_u8 message_size; + l_u16 data_index = 0; + l_u16 tmp_length = length; + l_u16 frame_counter = 0; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get transmit queue */ + tl_queue = tl_conf->tl_tx_queue; + + /* check message status in queue */ + if (LD_COMPLETED == tl_conf->tl_tx_msg_status) + { + /* calculate number of PDU for this message */ + if (length <= 6) + { + message_size = 1; + } + else + { + if ((length - 5) % 6 == 0) + { + message_size = ((length - 5) / 6) + 1; + } + else + { + message_size = ((length - 5) / 6) + 2; + } + } + if (message_size <= (tl_queue->queue_max_size - tl_queue->queue_current_size)) + { + /* update information of message in queue */ + tl_conf->tl_tx_msg_index = tl_queue->queue_tail; + tl_conf->tl_tx_msg_size = message_size; + tl_conf->tl_tx_msg_status = LD_IN_PROGRESS; + *conf->tl_service_status = LD_SERVICE_BUSY; + + /* package data */ + if (length <= 6) + { + /* package single frame */ + /* ____________________________________________ */ + /* | NAD | PCI | SID | D1 | D2 | D3 | D4 | D5 | */ + /* |_____|_____|_____|____|____|____|____|____| */ + if (_MASTER_ == conf->function) + { + pdu[0] = NAD; + } + else + { + pdu[0] = conf->node_attribute->configured_NAD; + } + pdu[1] = (l_u8) length; + pdu[2] = data[0]; /* SID / RSID */ + for (i = 1; i < length; i++) + { + pdu[i + 2] = data[i]; /* used data */ + } + for (i = (l_u8) length; i < 6; i++) + { + pdu[i + 2] = 0xFF; /* unused data */ + } + ld_put_raw(iii, pdu); + } + else + { + /* package first frame */ + /* ____________________________________________ */ + /* | NAD | PCI | LEN |SID | D2 | D3 | D4 | D5 | */ + /* |_____|_____|_____|____|____|____|____|____| */ + if (_MASTER_ == conf->function) + { + pdu[0] = NAD; + } + else + { + pdu[0] = conf->node_attribute->configured_NAD; + } + pdu[1] = ((length / 256) & 0x0F) | 0x10; /* PCI */ + pdu[2] = length % 256; /* length */ + pdu[3] = data[0]; /* SID / RSID */ + for (i = 1; i < 5; i++) + { + /* data */ + pdu[i + 3] = data[i]; + } + data_index += 5; + tmp_length -= 5; + ld_put_raw(iii, pdu); + + /* package consecutive frame */ + /* ___________________________________________ */ + /* | NAD | PCI | D1 | D2 | D3 | D4 | D5 | D6 | */ + /* |_____|_____|____|____|____|____|____|____| */ + message_size--; + if (_MASTER_ == conf->function) + { + pdu[0] = NAD; + } + else + { + pdu[0] = conf->node_attribute->configured_NAD; + } + while (message_size > 0) + { + frame_counter++; + pdu[1] = 0x20 | (frame_counter & 0x0F); + if (tmp_length < 6) + { + /* last PDU */ + /* used data */ + for (i = 0; i < tmp_length; i++) + { + pdu[i + 2] = data[data_index++]; + } + /* unused data */ + for (i = (l_u8) tmp_length; i < 6; i++) + { + pdu[i + 2] = 0xFF; + } + } + else + { + for (i = 2; i < 8; i++) + { + pdu[i] = data[data_index++]; + } + tmp_length -= 6; + } /* end of (tmp < 6 ) */ + message_size--; + ld_put_raw(iii, pdu); + } /* end of (message > 0) */ + } /* end of (length < 6) */ + /* For Master nodes, set Diagnostic Interleaved mode */ + if (_MASTER_ == conf->function) + { + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + /* Start send message */ + *conf->diagnostic_mode = DIAG_INTER_LEAVE_MODE; + } + /* For slave nodes, start checking N_As_timeout*/ + else + { + /* Set check N_As timeout */ + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_conf->tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + } + } /* end of check message size */ + } /* end of (LD_COMPLETED == tl_conf->tl_message_status) */ +} /* end of ld_send_message */ + +void ld_receive_message( + /* [IN] interface name */ + l_ifc_handle iii, + /* [OUT] length of data to receive */ + l_u16* const length, + /* [OUT] Node address of slave node */ + l_u8* const NAD, + /* [OUT] data to be sent */ + l_u8* const data +) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_message_status *_tl_receive_msg_status; + lin_transport_layer_queue *tl_queue; + lin_tl_pdu_data *queue_data; + lin_tl_pdu_data pdu; + l_u8 i; + l_u16 data_index = 0; + l_u16 tmp_length = 0; + l_u16 frame_counter; + l_u8 PCI_type; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get message status */ + _tl_receive_msg_status = &(tl_conf->tl_receive_msg_status); + /* Get transmit queue */ + tl_queue = tl_conf->tl_rx_queue; + queue_data = tl_queue->tl_pdu; + /* set status of receive message */ + tl_conf->tl_rx_msg_status = LD_IN_PROGRESS; + + /* wait message is received completely */ + while (LD_COMPLETED != *_tl_receive_msg_status) + { + /* check message error */ + if ((LD_FAILED == *_tl_receive_msg_status) || (LD_WRONG_SN == *_tl_receive_msg_status) || + (LD_N_CR_TIMEOUT == *_tl_receive_msg_status)) + { + tl_conf->tl_rx_msg_status = *_tl_receive_msg_status; + return; + } + } + /* Message is received completely */ + /* get data from receive queue */ + ld_get_raw(iii, pdu); + /* Analyze data */ + if (_MASTER_ == conf->function) + { + *NAD = pdu[0]; + } + /* Check type of pdu */ + PCI_type = (pdu[1] & 0xF0) >> 4; + switch (PCI_type) + { + /* Single frame */ + case SF: + tmp_length = pdu[1] & 0x0f; + *length = tmp_length; + data[0] = pdu[2]; + for (i = 1; i < tmp_length; i++) + { + data[i] = pdu[i + 2]; + } + break; + /* First frame */ + case FF: + tmp_length = (pdu[1] & 0x0F) * 256 + pdu[2]; + *length = tmp_length; + data[0] = pdu[3]; + for (i = 1; i < 5; i++) + { + data[i] = pdu[i + 3]; + } + tmp_length -= 5; + data_index += 5; + /* Consecutive frame */ + case CF: + while (tmp_length > 6) + { + /* get PDU */ + ld_get_raw(iii, pdu); + frame_counter = pdu[1] & 0x0F; + + for (i = 2; i < 8; i++) + { + data[data_index++] = pdu[i]; + } + tmp_length -= 6; + } + + /* Last frame */ + if (tmp_length > 0) + { + /* get PDU */ + ld_get_raw(iii, pdu); + frame_counter = pdu[1] & 0x0F; + + for (i = 0; i < tmp_length; i++) + { + data[data_index++] = pdu[i + 2]; + } + } + + break; + default: + break; + } /* end of switch */ + *_tl_receive_msg_status = LD_NO_MSG; + tl_conf->tl_rx_msg_status = LD_COMPLETED; +} + +l_u8 ld_tx_status( + /* [IN] interface name */ + l_ifc_handle iii) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + return (l_u8) (tl_conf->tl_tx_msg_status); +} + +l_u8 ld_rx_status( + /* [IN] interface name */ + l_ifc_handle iii) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + return (l_u8) (tl_conf->tl_rx_msg_status); +} +/** @} */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +/** @addtogroup node_configuration_group + * @{ */ +void ld_assign_NAD( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] initial node address of the target node */ + l_u8 initial_NAD, + /* [IN] supplier ID of the target node */ + l_u16 supplier_id, + /* [IN] function identifier of the target node */ + l_u16 function_id, + /* [IN] new node address */ + l_u8 new_NAD) +{ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 data[6]; + lin_configuration *conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* check service is busy? */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + data[0] = 0xB0; + data[1] = supplier_id & 0x00FF; + data[2] = (supplier_id >> 8) & 0x00FF; + data[3] = function_id & 0x00FF; + data[4] = (function_id >> 8) & 0x00FF; + data[5] = new_NAD; + + /* put data into TX_QUEUE */ + ld_send_message(iii, 6, initial_NAD, data); + + /* set node config status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } /* End of checking service status */ + } + +#else /* Single frame support */ + + lin_tl_pdu_data *lin_tl_pdu; + + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + + /* Create data for Assign NAD command */ + (*lin_tl_pdu)[0] = initial_NAD; + (*lin_tl_pdu)[1] = 0x06; + (*lin_tl_pdu)[2] = 0xB0; + (*lin_tl_pdu)[3] = supplier_id &0x00FF; + (*lin_tl_pdu)[4] = (supplier_id >> 8) & 0x00FF; + (*lin_tl_pdu)[5] = function_id &0x00FF; + (*lin_tl_pdu)[6] = (function_id >> 8) & 0x00FF; + (*lin_tl_pdu)[7] = new_NAD; + + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + /* Switch to master request schedule table */ + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } /* End of checking service status */ + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void ld_conditional_change_NAD( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] current NAD value of the target node */ + l_u8 NAD, + /* [IN] property ID of the target node */ + l_u8 id, + /* [IN] byte location of property value to be read from the target node */ + l_u8 byte_data, + /* [IN] value for masking the read property byte */ + l_u8 mask, + /* [IN] value for excluding the read property byte */ + l_u8 invert, + /* [IN] new NAD value to be assigned when the condition is met */ + l_u8 new_NAD) +{ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 data[6]; + lin_configuration *conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* check service is busy? */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + data[0] = 0xB3; + data[1] = id; + data[2] = byte_data; + data[3] = mask; + data[4] = invert; + data[5] = new_NAD; + + /* put data into TX_QUEUE */ + ld_send_message(iii, 6, NAD, data); + + /* set node config status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + }/* End of checking service status */ + } + +#else /* Single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + /* Create data for Conditional change NAD command */ + (*lin_tl_pdu)[0] = NAD; + (*lin_tl_pdu)[1] = 0x06; + (*lin_tl_pdu)[2] = 0xB3; + (*lin_tl_pdu)[3] = id; + (*lin_tl_pdu)[4] = byte_data; + (*lin_tl_pdu)[5] = mask; + (*lin_tl_pdu)[6] = invert; + (*lin_tl_pdu)[7] = new_NAD; + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + /* Switch to master request schedule table */ + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } /* End of checking service status */ + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} +/** @} */ + +/** @addtogroup node_identification_group + * @{ */ +void ld_read_by_id( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] value of the target node */ + l_u8 NAD, + /* [IN] supplier ID of the target node */ + l_u16 supplier_id, + /* [IN] function ID of the target node */ + l_u16 function_id, + /* [IN] ID of the target node */ + l_u8 id, + /* [OUT] buffer for saving the data read from the node */ + l_u8* const data) +{ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 buff[6]; + + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + tl_conf = conf->tl_desc; + + /* check service is busy? */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + /* Create data for Read by Identifier command */ + buff[0] = 0xB2; + buff[1] = id; + buff[2] = supplier_id & 0x00FF; + buff[3] = (supplier_id >> 8) & 0x00FF; + buff[4] = function_id & 0x00FF; + buff[5] = (function_id >> 8) & 0x00FF; + + /* Store address of RAM data which contain response infor */ + tl_conf->tl_ident_data = data; + + /* put data into TX_QUEUE */ + ld_send_message(iii, 6, NAD, buff); + + /* set node config status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + + } /* End of checking service status */ + } +#else /* Single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + /* Create data for Read by Identifier command */ + (*lin_tl_pdu)[0] = NAD; + (*lin_tl_pdu)[1] = 0x06; + (*lin_tl_pdu)[2] = 0xB2; + (*lin_tl_pdu)[3] = id; + (*lin_tl_pdu)[4] = supplier_id &0x00FF; + (*lin_tl_pdu)[5] = (supplier_id >> 8) & 0x00FF; + (*lin_tl_pdu)[6] = function_id &0x00FF; + (*lin_tl_pdu)[7] = (function_id >> 8) & 0x00FF; + + /* Store address of RAM data which contain response infor */ + tl_conf->tl_ident_data = data; + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + + /* Switch to master request schedule table */ + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } /* End of checking service status */ + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + + + +void ld_save_configuration( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] node address of the target node */ + l_u8 NAD +) +{ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 data[6]; + lin_configuration *conf; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* check service is busy? */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + data[0] = SERVICE_SAVE_CONFIGURATION; + data[1] = 0xFF; + data[2] = 0xFF; + data[3] = 0xFF; + data[4] = 0xFF; + data[5] = 0xFF; + /* put data into TX_QUEUE */ + ld_send_message(iii, PCI_SAVE_CONFIGURATION, NAD, data); + + /* set node config status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } /* End of checking service status */ + } + +#else /* Single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* This function is only for Master nodes*/ + if (conf->function == _MASTER_) + { + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + /* Create data for Assign NAD command */ + (*lin_tl_pdu)[0] = NAD; + (*lin_tl_pdu)[1] = PCI_SAVE_CONFIGURATION; + (*lin_tl_pdu)[2] = SERVICE_SAVE_CONFIGURATION; + (*lin_tl_pdu)[3] = 0xFF; + (*lin_tl_pdu)[4] = 0xFF; + (*lin_tl_pdu)[5] = 0xFF; + (*lin_tl_pdu)[6] = 0xFF; + (*lin_tl_pdu)[7] = 0xFF; + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + /* Switch to master request schedule table */ + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } /* End of checking service status */ + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + + +l_u8 ld_read_configuration +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] data area to save configuration */ + l_u8* const data, + /* [IN] length of data area */ + l_u8* const length +) +{ + l_u8 i, temp; + /* Set the default returned value to LD_READ_OK */ + l_u8 retval = (l_u8)LD_READ_OK; + /** Set the expected length value to + * EXP = NN + NF, where : + * NN = the number of NAD. + * NF = the number of configurable frames; + * Moreover: + * Not taken PID's diagnostics frame: 3C, 3D + */ + l_u8 expected_length; + + lin_configuration const *conf; + lin_node_attribute *node_att; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + expected_length = (l_u8) (conf->num_of_frames - 1); + /* Check if slave node */ + if (_SLAVE_ == conf->function) + { + temp = *length; + /* Get node attibute */ + node_att = conf->node_attribute; + + if (temp < expected_length) + { + /* The 'data' size is not enough to store NAD+PIDs */ + retval = (l_u8)LD_LENGTH_TOO_SHORT; + } + else + { + /* The 'data' size is enough to store NAD+PIDs, so proceed to store them */ + /* Copy actual NAD to 'data' */ + data[0] = node_att ->configured_NAD; + + /* Copy protected IDs to 'data' */ + for (i = 1U; i < expected_length; ++i) + { + data[i] = conf->configuration_RAM[i]; + } + /* Set the length parameter to the actual size of the configuration */ + *length = expected_length; + } + } + return retval; +} /* End ld_read_configuration() */ + + + +l_u8 ld_set_configuration +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] data area to set configuration */ + const l_u8* const data, + /* [IN] length of data area */ + l_u16 length +) +{ + l_u8 i; + /* Set the default returned value to LD_DATA_ERROR */ + l_u8 retval = LD_DATA_ERROR; + /** Set the expected length value to + * EXP = NN + NF, where : + * NN = the number of NAD. + * NF = the number of configurable frames; + * Moreover: + * Not taken PID's diagnostics frame: 3C, 3D + */ + l_u16 expected_length; + lin_configuration const *conf; + lin_node_attribute *node_att; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + expected_length = (l_u16) (conf->num_of_frames - 1); + + /* Check if slave node */ + if (_SLAVE_ == conf->function) + { + /* Get node attibute */ + node_att = conf->node_attribute; + + if (length < expected_length) + { + /* The 'data' size is not enough to contain NAD+PIDs */ + retval = LD_LENGTH_NOT_CORRECT; + } + else + { + /* The 'data' size is enough to contain NAD+PIDs, so proceed to read from 'data' */ + /* Read actual NAD from 'data' */ + node_att ->configured_NAD = data[0]; + + /* Copy protected IDs in 'data' to RAM configuration */ + for (i = 1U; i < expected_length; ++i) + { + conf->configuration_RAM[i] = data[i]; + } + /* No error, return OK */ + retval = LD_SET_OK; + } + } + return retval; +} /* End ld_set_configuration() */ + + +/** @} */ +#endif /* End LIN_MODE == _MASTER_MODE_ */ + +/* -------------------------------------------------------------------- */ + +#if LIN_MODE == _SLAVE_MODE_ +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) +/* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + +/* INITIALIZATION */ +/** @addtogroup initialization_group + * @{ */ +void ld_init(void) +{ + /* init transmit queue */ + lin_tl_tx_queue.queue_header = 0; + lin_tl_tx_queue.queue_tail = 0; + lin_tl_tx_queue.queue_status = LD_QUEUE_EMPTY; + lin_tl_tx_queue.queue_current_size = 0; + /* init receive queue */ + lin_tl_rx_queue.queue_header = 0; + lin_tl_rx_queue.queue_tail = 0; + lin_tl_rx_queue.queue_status = LD_NO_DATA; + lin_tl_rx_queue.queue_current_size = 0; + + /* Init transmit message */ + tl_rx_msg_status = LD_COMPLETED; + tl_rx_msg_index = 0; + tl_rx_msg_size = 0; + tl_receive_msg_status = LD_NO_MSG; + + /* Init receive message */ + tl_tx_msg_status = LD_COMPLETED; + tl_tx_msg_index = 0; + tl_tx_msg_size = 0; + + tl_last_cfg_result = LD_SUCCESS; + tl_last_RSID = 0; + tl_ld_error_code = 0; + + tl_frame_counter = 0; + tl_no_of_pdu = 0; + tl_slaveresp_cnt = 0; + + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_check_timeout = N_MAX_TIMEOUT_CNT; + + tl_diag_state = LD_DIAG_IDLE; + tl_service_status = LD_SERVICE_IDLE; +} +/** @} */ +/* RAW APIs */ +/** @addtogroup raw_api_group + * @{ */ +void ld_put_raw(const l_u8* const data) +{ + tl_put_raw(data, &lin_tl_tx_queue, TRANSMISSION); + tl_slaveresp_cnt++; +} + +void ld_get_raw(l_u8* const data) +{ + tl_get_raw(data, &lin_tl_rx_queue, RECEIVING); +} + +l_u8 ld_raw_tx_status(void) +{ + return (l_u8)lin_tl_tx_queue.queue_status; +} + +l_u8 ld_raw_rx_status(void) +{ + return (l_u8)lin_tl_rx_queue.queue_status; +} +/** @} */ +/* COOKED APIs */ +/** @addtogroup cooked_api_group + * @{ */ +void ld_send_message(l_u16 length, const l_u8* const data) +{ + lin_tl_pdu_data pdu; + l_u8 i; + l_u8 message_size; + l_u16 data_index = 0; + l_u16 tmp_length = length; + l_u16 frame_counter = 1; + + /* check message status in queue */ + if (LD_COMPLETED == tl_tx_msg_status) + { + /* calculate number of PDU for this message */ + if (length <= 6) + { + message_size = 1; + } + else + { + if ((length-5)%6 == 0) + { + message_size = ((length - 5) / 6) + 1; + } + else + { + message_size = ((length - 5) / 6) + 2; + } + } + + if (message_size <= (lin_tl_tx_queue.queue_max_size - lin_tl_tx_queue.queue_current_size)) + { + /* update information of message in queue */ + tl_tx_msg_index = lin_tl_tx_queue.queue_tail; + tl_tx_msg_size = message_size; + tl_tx_msg_status = LD_IN_PROGRESS; + tl_service_status = LD_SERVICE_BUSY; + + /* package data */ + if (length <= 6) + { + /* package single frame */ + /* ____________________________________________ */ + /* | NAD | PCI | SID | D1 | D2 | D3 | D4 | D5 | */ + /* |_____|_____|_____|____|____|____|____|____| */ + + pdu[0] = lin_configured_NAD; + + pdu[1] = (l_u8) length; + pdu[2] = data[0]; /* SID / RSID */ + for (i = 1; i < length; i++) + { + pdu[i + 2] = data[i]; /* used data */ + } + for (i = (l_u8) length; i < 6; i++) + { + pdu[i + 2] = 0xFF; /* unused data */ + } + ld_put_raw(pdu); + } + else + { + /* package first frame */ + /* ____________________________________________ */ + /* | NAD | PCI | LEN |SID | D2 | D3 | D4 | D5 | */ + /* |_____|_____|_____|____|____|____|____|____| */ + + pdu[0] = lin_configured_NAD; + pdu[1] = ((length / 256) & 0x0F) | 0x10; /* PCI */ + pdu[2] = length % 256; /* length */ + pdu[3] = data[0]; /* SID / RSID */ + for (i = 1; i < 5; i++) + { + /* data */ + pdu[i + 3] = data[i]; + } + data_index += 5; + tmp_length -= 5; + ld_put_raw(pdu); + + /* package consecutive frame */ + /* ___________________________________________ */ + /* | NAD | PCI | D1 | D2 | D3 | D4 | D5 | D6 | */ + /* |_____|_____|____|____|____|____|____|____| */ + message_size--; + + pdu[0] = lin_configured_NAD; + while (message_size > 0) + { + pdu[1] = 0x20 | (frame_counter & 0x0F); + frame_counter++; + if (frame_counter > 15) + { + frame_counter = 0; + } + if (tmp_length < 6) + { + /* last PDU */ + /* used data */ + for (i = 0; i < tmp_length; i++) + { + pdu[i + 2] = data[data_index++]; + } + /* unused data */ + for (i = (l_u8) tmp_length; i < 6; i++) + { + pdu[i + 2] = 0xFF; + } + } + else + { + for (i = 2; i < 8; i++) + { + pdu[i] = data[data_index++]; + } + tmp_length -= 6; + } /* end of (tmp < 6 ) */ + message_size--; + ld_put_raw(pdu); + } /* end of (message > 0) */ + } /* end of (length < 6) */ + + /* Set check N_As timeout */ + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + } /* end of check message size */ + } /* end of (LD_COMPLETED == tl_conf->tl_message_status) */ +} + +void ld_receive_message(l_u16* const length, l_u8* const data) +{ + + lin_tl_pdu_data pdu; + l_u8 i; + l_u16 data_index = 0; + l_u16 tmp_length; + l_u16 frame_counter; + l_u8 PCI_type; + + /* set status of receive message */ + tl_rx_msg_status = LD_IN_PROGRESS; + + /* wait message is received completely */ + while (LD_COMPLETED != tl_receive_msg_status) + { + /* check message error */ + if ((LD_FAILED == tl_receive_msg_status) || (LD_WRONG_SN == tl_receive_msg_status) || + (LD_N_CR_TIMEOUT == tl_receive_msg_status)) + { + tl_rx_msg_status = tl_receive_msg_status; + return; + } + } + /* Message is received completely */ + /* get data from receive queue */ + ld_get_raw(pdu); + /* Check type of pdu */ + PCI_type = (pdu[1] & 0xF0) >> 4; + switch (PCI_type) + { + /* Single frame */ + case SF: + tmp_length = pdu[1] & 0x0f; + *length = tmp_length; + data[0] = pdu[2]; + for (i = 1; i < tmp_length; i++) + { + data[i] = pdu[i + 2]; + } + break; + /* First frame */ + case FF: + tmp_length = (pdu[1] & 0x0F) * 256 + pdu[2]; + *length = tmp_length; + data[0] = pdu[3]; + for (i = 1; i < 5; i++) + { + data[i] = pdu[i + 3]; + } + tmp_length -= 5; + data_index += 5; + /* Consecutive frame */ + case CF: + while (tmp_length > 6) + { + /* get PDU */ + ld_get_raw(pdu); + frame_counter = pdu[1] & 0x0F; + + for (i = 2; i < 8; i++) + { + data[data_index++] = pdu[i]; + } + tmp_length -= 6; + } + + /* Last frame */ + if (tmp_length > 0) + { + /* get PDU */ + ld_get_raw(pdu); + frame_counter = pdu[1] & 0x0F; + + for (i = 0; i < tmp_length; i++) + { + data[data_index++] = pdu[i + 2]; + } + } + + break; + default: + break; + } /* end of switch */ + tl_receive_msg_status = LD_NO_MSG; + tl_rx_msg_status = LD_COMPLETED; +} + +l_u8 ld_tx_status(void) +{ + return (l_u8)tl_tx_msg_status; +} + +l_u8 ld_rx_status(void) +{ + return (l_u8)tl_rx_msg_status; +} +/** @} */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + +l_u8 ld_read_configuration +( + /* [IN] data area to save configuration */ + l_u8* const data, + /* [IN] length of data area */ + l_u8* const length +) +{ + l_u8 i, temp; + /* Set the default returned value to LD_READ_OK */ + l_u8 retval = (l_u8)LD_READ_OK; + /** Set the expected length value to + * EXP = NN + NF, where : + * NN = the number of NAD. + * NF = the number of configurable frames; + * Moreover: + * Not taken PID's diagnostics frame: 3C, 3D + */ + l_u8 expected_length = (l_u8)(LIN_NUM_OF_FRMS - 1U); + temp = *length; + if (temp < expected_length) + { + /* The 'data' size is not enough to store NAD+PIDs */ + retval = (l_u8)LD_LENGTH_TOO_SHORT; + } + else + { + /* The 'data' size is enough to store NAD+PIDs, so proceed to store them */ + /* Copy actual NAD to 'data' */ + data[0] = lin_configured_NAD; + /* Copy protected IDs to 'data' */ + for (i = 1U; i < expected_length; ++i) + { + data[i] = lin_configuration_RAM[i]; + } + /* Set the length parameter to the actual size of the configuration */ + *length = expected_length; + } + return retval; +} /* End ld_read_configuration() */ + + +l_u8 ld_set_configuration +( + /* [IN] data area to set configuration */ + const l_u8* const data, + /* [IN] length of data area */ + l_u16 length +) +{ + l_u8 i; + /* Set the default returned value to LD_DATA_ERROR */ + l_u8 retval = LD_DATA_ERROR; + /** Set the expected length value to + * EXP = NN + NF, where : + * NN = the number of NAD. + * NF = the number of configurable frames; + * Moreover: + * Not taken PID's diagnostics frame: 3C, 3D + */ + l_u16 expected_length = (l_u8)(LIN_NUM_OF_FRMS - 1U); + if (length < expected_length) + { + /* The 'data' size is not enough to contain NAD+PIDs */ + retval = LD_LENGTH_NOT_CORRECT; + } + else + { + /* The 'data' size is enough to contain NAD+PIDs, so proceed to read from 'data' */ + /* Read actual NAD from 'data' */ + lin_configured_NAD = data[0]; + /* Copy protected IDs in 'data' to RAM configuration */ + for (i = 1U; i < expected_length; ++i) + { + lin_configuration_RAM[i] = data[i]; + } + /* No error, return OK */ + retval = LD_SET_OK; + } + return retval; +} /* End ld_set_configuration() */ + +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ +#endif /* End LIN_MODE == _SLAVE_MODE_ */ +/** + * @} + */ diff --git a/LIN_Stack/transport/lin_commontl_proto.c b/LIN_Stack/transport/lin_commontl_proto.c new file mode 100644 index 0000000..564ee39 --- /dev/null +++ b/LIN_Stack/transport/lin_commontl_proto.c @@ -0,0 +1,2085 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ +/**************************************************************************//** +* @addtogroup transport_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_commontl_proto.c +* +* @author FPT Software +* +* @brief Common Handle LIN transport layer and configuration functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090409 v1.0 First version + * 20111005 v1.1 Added code for save configuration request and response + * + *****************************************************************************/ + +#include "lin_commontl_proto.h" +#include "lin_diagnostic_service.h" + +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +#include "lin_commontl_api.h" +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +/* Define functionality */ +#ifndef MULTI_PDU_SUPPORT +#define MULTI_PDU_SUPPORT 0 /**< multi PDU support */ +#endif /* MULTI_PDU_SUPPORT */ + +/********------------- Code supports SINGLE interface ----------------**********/ + +#if LIN_MODE == _SLAVE_MODE_ +/* Unuse for GPIO */ +#if (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) && !defined(MCU_SKEAZN84) +/*************************** FUNCTIONS *******************/ + + +void lin_tl_make_slaveres_pdu +( + /* [IN] service identifier */ + l_u8 sid, + /* [IN] type of response */ + l_u8 res_type, + /* [IN] Error code in case of negative response, if positive = 0 */ + l_u8 error_code + +) +{ + lin_tl_pdu_data lin_tl_pdu; + l_u8 i; + + lin_tl_pdu[0] = lin_configured_NAD; /* NAD */ + lin_tl_pdu[1] = 0x03; /* PCI */ + lin_tl_pdu[2] = RES_NEGATIVE; /* SID */ + lin_tl_pdu[3] = sid; /* D0 */ + lin_tl_pdu[4] = error_code; /* D1 */ + lin_tl_pdu[5] = 0xFF; /* D2 */ + lin_tl_pdu[6] = 0xFF; /* D3 */ + lin_tl_pdu[7] = 0xFF; /* D4 */ + + switch (sid) + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + + case SERVICE_TARGET_RESET: + /* PCI type */ + lin_tl_pdu[1] = 0x06; + /* SID */ + if (NEGATIVE == res_type) + { + lin_tl_pdu[2] = RES_NEGATIVE; + } + else + { + lin_tl_pdu[2] = RES_POSITIVE+ sid; + } + /* Get Identifier infor */ + lin_tl_pdu[3] = (l_u8)(product_id.supplier_id & 0xFF); + lin_tl_pdu[4] = (l_u8)(product_id.supplier_id >> 8); + lin_tl_pdu[5] = (l_u8)(product_id.function_id & 0xFF); + lin_tl_pdu[6] = (l_u8)(product_id.function_id >> 8); + lin_tl_pdu[7] = product_id.variant; + break; + #endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + + #if (LIN_PROTOCOL == PROTOCOL_21) + case SERVICE_ASSIGN_FRAME_ID: + if (POSITIVE == res_type) + { + /* SID */ + lin_tl_pdu[2] = RES_POSITIVE + sid; + if (error_code == LIN_PRODUCT_IDENT) + { + /* PCI type */ + lin_tl_pdu[1] = 0x01; + /* Get Identifier infor */ + lin_tl_pdu[3] = 0xFF; + lin_tl_pdu[4] = 0xFF; + lin_tl_pdu[5] = 0xFF; + lin_tl_pdu[6] = 0xFF; + lin_tl_pdu[7] = 0xFF; + } + } + break; + case SERVICE_READ_BY_IDENTIFY: + if (POSITIVE == res_type) + { + /* SID */ + lin_tl_pdu[2] = RES_POSITIVE + sid; + + if (error_code == LIN_PRODUCT_IDENT) + { + /* PCI type */ + lin_tl_pdu[1] = PCI_RES_READ_BY_IDENTIFY; + /* Get Identifier infor */ + lin_tl_pdu[3] = (l_u8)(product_id.supplier_id >> 8); + lin_tl_pdu[4] = (l_u8)(product_id.supplier_id & 0xFF); + lin_tl_pdu[5] = (l_u8)(product_id.function_id & 0xFF); + lin_tl_pdu[6] = (l_u8)(product_id.function_id >> 8); + lin_tl_pdu[7] = product_id.variant; + } + else if (error_code == SERIAL_NUMBER) + { + /* PCI type */ + lin_tl_pdu[1] = PCI_RES_READ_BY_IDENTIFY1; + lin_tl_pdu[3] = 0x00; + lin_tl_pdu[4] = 0x00; + lin_tl_pdu[5] = 0x00; + lin_tl_pdu[6] = 0x00; + lin_tl_pdu[7] = 0xFF; + } + + else if (error_code >= LIN_READ_USR_DEF_MIN && error_code <= LIN_READ_USR_DEF_MAX) + { + + //l_u8 data_callout[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + // l_u8 retval = ld_read_by_id_callout(error_code, data_callout); + /* packing user defined pdu */ + lin_tl_pdu[1] = 0x04; + lin_tl_pdu[3] = 0x00; + lin_tl_pdu[4] = 0x00; + lin_tl_pdu[5] = 0x00; + lin_tl_pdu[6] = 0x00; + lin_tl_pdu[7] = 0x00; + /* Check for data values*/ + // for (i = 4; i >= 0; i --) + // { + // if (data_callout[i] != 0xFF) + // { + // /* PCI: Data length is 1 (RSID) + all data exclude 0xFF */ + // lin_tl_pdu[1] = i + 2; + // break; + // } + // } + } + } + break; + case SERVICE_ASSIGN_FRAME_ID_RANGE: /* Mandatory for TL LIN 2.1 */ + if (POSITIVE == res_type) + { + lin_tl_pdu[1] = 0x06; + lin_tl_pdu[2] = RES_POSITIVE + sid; + lin_tl_pdu[3] = 0xFF; + lin_tl_pdu[4] = 0xFF; + lin_tl_pdu[5] = 0xFF; + lin_tl_pdu[6] = 0xFF; + lin_tl_pdu[7] = 0xFF; + } + break; + case SERVICE_SAVE_CONFIGURATION: + if (POSITIVE == res_type) + { + /* PCI type */ + lin_tl_pdu[1] = PCI_RES_SAVE_CONFIGURATION; + /* SID */ + lin_tl_pdu[2] = RES_POSITIVE + sid; + /* Data unused */ + lin_tl_pdu[3] = 0xFF; + lin_tl_pdu[4] = 0xFF; + } + break; + case SERVICE_ASSIGN_NAD: + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_configured_NAD = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][7]; + #else /* Single frame support */ + lin_configured_NAD = (*tl_current_rx_pdu_ptr)[7]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + lin_tl_pdu[0] = lin_initial_NAD; /* Use Initial NAD */ + lin_tl_pdu[1] = 0x01; /* PCI */ + lin_tl_pdu[2] = 0xF0; /* RSID */ + lin_tl_pdu[3] = 0xFF; + lin_tl_pdu[4] = 0xFF; + break; + case SERVICE_CONDITIONAL_CHANGE_NAD: + lin_tl_pdu[1] = 0x01; /* PCI */ + lin_tl_pdu[2] = 0xF3; /* RSID */ + lin_tl_pdu[3] = 0xFF; + lin_tl_pdu[4] = 0xFF; + break; + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + default: + break; + }/* end of switch statement */ + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_tx_queue.queue_status = LD_QUEUE_FULL; + lin_tl_tx_queue.queue_current_size = 1; + + /* Put to transmit queue */ + for (i = 0; i < 8; i++) + { + lin_tl_tx_queue.tl_pdu[lin_tl_tx_queue.queue_header][i] = lin_tl_pdu[i]; + } + /* Set check N_As Timeout */ + tl_tx_msg_index = lin_tl_tx_queue.queue_tail; + tl_tx_msg_size = 1; + tl_tx_msg_status = LD_IN_PROGRESS; +#else /* Single frame support */ + for (i = 0; i < 8; i++) + { + tx_single_pdu_data[i] = lin_tl_pdu[i]; + } + /* set current TX PDU to send out */ + tl_current_tx_pdu_ptr = (lin_tl_pdu_data*)tx_single_pdu_data; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Set check N_As timeout */ + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + /* set number of SlaveResp response data */ + tl_slaveresp_cnt = 1; +} + +void lin_tl_get_pdu() +{ + l_u8 i; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu_data lin_tl_pdu; + + tl_get_raw(lin_tl_pdu, &lin_tl_tx_queue, TRANSMISSION); + /* Copy PDU to response buffer */ + for (i = 1; i < 9; i++) + { + lin_lld_response_buffer[i] = lin_tl_pdu[i - 1]; + } +#else /* Single frame support */ + /* Copy PDU to response buffer */ + for (i = 1; i < 9; i++) + { + lin_lld_response_buffer[i] = (*tl_current_tx_pdu_ptr)[i - 1]; + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +/* Single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) +void lin_tl_put_pdu () +{ + l_u8 i; + + /* Set PDU for RX buffer */ + tl_current_rx_pdu_ptr = &rx_single_pdu_data; + + for (i = 0; i < 8; i++) + { + (*tl_current_rx_pdu_ptr)[i] = lin_lld_response_buffer[i+1]; + } +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + + +/* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_pdu(lin_tl_pdu_data *pdu) +* @brief LIN process packet data unit +* +* @param pdu [IN] packet data unit +* +* @return #void +* +* @SDD_ID LIN_SDD_354 +* @endif +* +* @local_var +* -# #l_u8 pci_type +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #l_u16 length +* -# #l_u8 tmp_frame_counter +* -# #lin_transport_layer_queue *tl_queue +* -# #l_u8 i +* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see tl_get_raw +* @see tl_put_raw +* @see lin_tl_get_response +* +* @details +* LIN process packet data unit +*//*END*----------------------------------------------------------------------*/ + +static void lin_process_pdu(lin_tl_pdu_data *pdu) +{ + l_u8 pci_type; + l_u16 length; + l_u8 tmp_frame_counter; + + /* get PCI type */ + pci_type = ((*pdu)[1] & 0xF0) >> 4; + switch (pci_type) + { + case PCI_SF: + length = ((*pdu)[1]) & 0x0F; + /* check length of SF. If not valid, ignore this PDU */ + if (length <= 6) + { + tl_receive_msg_status = LD_COMPLETED; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_service_status = LD_REQUEST_FINISHED; + /* put PDU to rx queue */ + lin_tl_rx_queue.queue_header = 0; + lin_tl_rx_queue.queue_tail = 0; + lin_tl_rx_queue.queue_current_size = 0; + lin_tl_rx_queue.queue_status = LD_NO_DATA; + tl_put_raw(&(lin_lld_response_buffer[1]), &lin_tl_rx_queue, RECEIVING); + tl_frame_counter = 1; + tl_no_of_pdu = 1; + if (tl_diag_state != LD_DIAG_RX_FUNCTIONAL) + { + tl_diag_state = LD_DIAG_TX_PHY; + } + lin_tl_attach_service(); + } + else + { + tl_diag_state = LD_DIAG_IDLE; + } + break; + case PCI_FF: + length = ((*pdu)[1] & 0x0F) * 256 + ((*pdu)[2]); + /* check length of FF. If not valid, ignore this PDU */ + if (length >= 7 && length <= (MAX_QUEUE_SIZE*6 - 1)) + { + /* Set check N_Cr timeout */ + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* put PDU to rx queue */ + lin_tl_rx_queue.queue_header = 0; + lin_tl_rx_queue.queue_tail = 0; + lin_tl_rx_queue.queue_current_size = 0; + lin_tl_rx_queue.queue_status = LD_NO_DATA; + tl_put_raw(lin_lld_response_buffer + 1, &lin_tl_rx_queue, RECEIVING); + + /* canculate number of PDU for this message */ + if ((length-5)%6 == 0) + { + tl_no_of_pdu = (l_u8)((length - 5) / 6); + } + else + { + tl_no_of_pdu = (l_u8)((length - 5) / 6) + 1; + } + /* set frame counter = 1 */ + tl_frame_counter = 1; + tl_service_status = LD_SERVICE_BUSY; + if (tl_diag_state != LD_DIAG_RX_FUNCTIONAL) + { + tl_diag_state = LD_DIAG_RX_PHY; + } + } + else + { + tl_diag_state = LD_DIAG_IDLE; + } + break; + case PCI_CF: + /* Set check N_Cr timeout */ + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* get frame counter of this PDU */ + tmp_frame_counter = ((*pdu)[1] & 0x0F); + /* Check valid frame counter */ + if (tmp_frame_counter == tl_frame_counter) + { + /* increase frame counter */ + tl_frame_counter++; + if (tl_frame_counter > 15) + { + tl_frame_counter = 0; + } + /* decrease number of PDU to check message is complete */ + tl_no_of_pdu--; + /* put PDU to rx queue */ + tl_put_raw(&(lin_lld_response_buffer[1]), &lin_tl_rx_queue, RECEIVING); + if (tl_diag_state != LD_DIAG_RX_FUNCTIONAL) + { + tl_diag_state = LD_DIAG_RX_PHY; + } + } + else + { + /* abort this message */ + tl_receive_msg_status = LD_WRONG_SN; + tl_rx_msg_status = LD_WRONG_SN; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } + if (0 == tl_no_of_pdu) + { + /* message is received completely */ + /* set status is IDLE to receive new message */ + + tl_receive_msg_status = LD_COMPLETED; + tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + + tl_service_status = LD_REQUEST_FINISHED; + if (tl_diag_state != LD_DIAG_RX_FUNCTIONAL) + { + tl_diag_state = LD_DIAG_TX_PHY; + } + lin_tl_attach_service(); + } + break; + default: + /* ignore this PDU */ + break; + } +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + +void lin_tl_handler() +{ + l_u8 NAD, SID; + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 frame_type; + NAD = lin_lld_response_buffer[1]; + SID = lin_lld_response_buffer[3]; + frame_type = (l_u8)((lin_lld_response_buffer[2] & 0xF0) >> 4); + /* check NAD whether or not belongs to this slave node */ + /* receive both broadcast NAD and functional NAD */ + if ((LD_BROADCAST != NAD) && \ + (LD_FUNCTIONAL_NAD != NAD) && \ + (((lin_configured_NAD != NAD) && \ + (SERVICE_ASSIGN_NAD != SID)) || \ + ((lin_initial_NAD != NAD) && \ + (SERVICE_ASSIGN_NAD == SID)))) + { + /* ignore any response */ + tl_slaveresp_cnt = 0; + return; + } + /* check if functional request is received while transmitting response */ + if ((tl_diag_state == LD_DIAG_TX_PHY || tl_diag_state == LD_DIAG_RX_PHY) && NAD == LD_FUNCTIONAL_NAD && tl_service_status == LD_SERVICE_BUSY) + { + tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* ignore request */ + NAD = 0x00; + return; + } + /* check if slave node is transmitting response while receive functional request */ + if (tl_diag_state == LD_DIAG_TX_PHY && NAD != LD_FUNCTIONAL_NAD) + { + /* clear received request & response */ + tl_service_status = LD_SERVICE_BUSY; + /* clear queue */ + lin_tl_tx_queue.queue_tail = 0; + lin_tl_tx_queue.queue_header = 0; + lin_tl_tx_queue.queue_current_size = 0; + lin_tl_tx_queue.queue_status = LD_QUEUE_EMPTY; + + lin_tl_rx_queue.queue_tail = 0; + lin_tl_rx_queue.queue_header = 0; + lin_tl_rx_queue.queue_current_size = 0; + lin_tl_rx_queue.queue_status = LD_NO_DATA; + /* transmit status */ + tl_tx_msg_status = LD_COMPLETED; + /* receive status */ + tl_receive_msg_status = LD_NO_MSG; + tl_rx_msg_status = LD_COMPLETED; + + tl_slaveresp_cnt = 0; + /* then receive and process new request */ + } + + if (tl_service_status == LD_SERVICE_ERROR && frame_type == PCI_CF) + { + return; + } + + if (NAD != LD_FUNCTIONAL_NAD) + { + tl_diag_state = LD_DIAG_RX_PHY; + } + else + { + tl_diag_state = LD_DIAG_RX_FUNCTIONAL; + } + /* call process pdu */ + lin_process_pdu((lin_tl_pdu_data *)&(lin_lld_response_buffer[1])); + +#else /* Single frame support */ + + l_u8 pci_type, length; + + NAD = (*tl_current_rx_pdu_ptr)[0]; + SID = (*tl_current_rx_pdu_ptr)[2]; + /* check NAD whether or not belongs to this slave node */ + /* receive both broadcast NAD and functional NAD */ + + if (NAD == 0x05) + { + length = 1; + } + if ((LD_BROADCAST != NAD) && \ + (LD_FUNCTIONAL_NAD != NAD) && \ + (((lin_configured_NAD != NAD) && (SERVICE_ASSIGN_NAD != SID)) || \ + ((lin_initial_NAD != NAD) && (SERVICE_ASSIGN_NAD == SID)))) + { + tl_slaveresp_cnt = 0; + return; + } + + /* Get PCI type */ + pci_type = ((*tl_current_rx_pdu_ptr)[1] & 0xF0) >> 4; + switch (pci_type) + { + case PCI_SF: /* Single frame */ + /* error handling: check length of message */ + length = (*tl_current_rx_pdu_ptr)[1] & 0x0F; + if (6 < length) + { + return; + } + lin_tl_attach_service(); + break; + default: + break; + } /* End of ckeck PCI_type */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void lin_tl_attach_service() +{ + l_u8 sid; + l_u8 i; + l_u8 sid_supported_flag = 0; + + /* Multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 frame_type, NAD; + l_u16 supplierIdLsb; + l_u16 supplierIdMsb; + l_u16 functionIdLsb; + l_u16 functionIdMsb; + + /* get frame type */ + frame_type = (lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][1] & 0xF0) >> 4; + NAD = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][0]; + /* check if request is functional request */ + if (NAD == LD_FUNCTIONAL_NAD) + { + #if (LIN_PROTOCOL == PROTOCOL_21) + lin_diagsrv_functional_service(); + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + /* update service state */ + tl_diag_state = LD_DIAG_IDLE; + tl_service_status = LD_SERVICE_IDLE; + /* ignore response */ + tl_no_of_pdu = 0; + tl_frame_counter = 0; + return; + } + + /* Get SID information */ + if (frame_type == PCI_FF) + { + sid = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][3]; + } + else + { + sid = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][2]; + } +#else /* Single frame support */ + l_u8 NAD; + l_u16 supplierIdLsb; + l_u16 supplierIdMsb; + l_u16 functionIdLsb; + l_u16 functionIdMsb; + + NAD = (*tl_current_rx_pdu_ptr)[0]; + /* check functional request */ + if (NAD == LD_FUNCTIONAL_NAD) + { + return; + } + /* Get SID information */ + sid = (*tl_current_rx_pdu_ptr)[2]; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + for (i = 0; i < _DIAG_NUMBER_OF_SERVICES_; i++) + { + if (lin_diag_services_supported[i] == sid) + { + lin_diag_services_flag[i] = 1; + sid_supported_flag = 1; + break; + } + } + if (sid_supported_flag == 1) + { + /*Clear sid_supported_flag */ + sid_supported_flag = 0; + switch (sid) + { +#if LIN_PROTOCOL == PROTOCOL_21 + case SERVICE_ASSIGN_FRAME_ID: + if(NAD==lin_configured_NAD|| NAD==0x7F){ + lin_diagservice_assign_frame_id(); + } + + break; + case SERVICE_READ_BY_IDENTIFY: /* Mandatory for TL LIN 2.1 & 2.0 */ + lin_diagservice_read_by_identifier(); + break; + + case SERVICE_ASSIGN_FRAME_ID_RANGE: /* Mandatory for TL LIN 2.1 */ + lin_diagservice_assign_frame_id_range(); + break; + + case SERVICE_SAVE_CONFIGURATION: + /* Set save configuration flag */ + lin_save_configuration_flg = 1; + /* Response to master - RSID */ + lin_tl_make_slaveres_pdu(SERVICE_SAVE_CONFIGURATION, POSITIVE, 0); + break; + + case SERVICE_ASSIGN_NAD: + /* Get Supplier ID and Function ID*/ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + if ((NAD == lin_initial_NAD)|| (NAD == LD_BROADCAST)) + { + supplierIdLsb = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][3]; + supplierIdMsb = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][4]; + functionIdLsb = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][5]; + functionIdMsb = lin_tl_rx_queue.tl_pdu[lin_tl_rx_queue.queue_header][6]; + /*Check if Supplier ID and Function ID match, then send positive response */ + if ((((supplierIdMsb<<8)|supplierIdLsb) == product_id.supplier_id)||(((supplierIdMsb<<8)|supplierIdLsb) == LD_ANY_SUPPLIER)) + if ((((functionIdMsb<<8)|functionIdLsb) == product_id.function_id)||(((functionIdMsb<<8)|functionIdLsb) == LD_ANY_FUNCTION)) + { + lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_NAD, POSITIVE, 0); + } + } +#else + if ((NAD == lin_initial_NAD)|| (NAD == LD_BROADCAST)) + { + supplierIdLsb = (*tl_current_rx_pdu_ptr)[3]; + supplierIdMsb = (*tl_current_rx_pdu_ptr)[4]; + functionIdLsb = (*tl_current_rx_pdu_ptr)[5]; + functionIdMsb = (*tl_current_rx_pdu_ptr)[6]; + /*Check if Supplier ID and Function ID match, then send positive response */ + if ((((supplierIdMsb<<8)|supplierIdLsb) == product_id.supplier_id)||(((supplierIdMsb<<8)|supplierIdLsb) == LD_ANY_SUPPLIER)) + if ((((functionIdMsb<<8)|functionIdLsb) == product_id.function_id)||(((functionIdMsb<<8)|functionIdLsb) == LD_ANY_FUNCTION)) + { + lin_tl_make_slaveres_pdu(SERVICE_ASSIGN_NAD, POSITIVE, 0); + } + } +#endif + break; + + case SERVICE_CONDITIONAL_CHANGE_NAD: + lin_condittional_change_nad(); + break; +#endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_21) */ + +#if LIN_PROTOCOL == PROTOCOL_J2602 + case SERVICE_TARGET_RESET: + lin_diagservice_target_reset(); + break; +#endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_J2602) */ + default: + break; + }/* end of switch */ + } + else + { + lin_tl_make_slaveres_pdu(sid, NEGATIVE, SERVICE_NOT_SUPPORTED); + } +} + +#endif /* End (_LIN_GPIO_ == 0) && !defined(_MC9S08SC4_H) */ +#endif /* End (LIN_MODE == _SLAVE_MODE_) */ + +/********------------ End of code for SINGLE Interface --------------**********/ + + +/********------------- Code supports Multi interface ----------------**********/ +#if LIN_MODE == _MASTER_MODE_ +#ifdef MULTI_TIMER_MODE +extern const l_u16 max_tl_timeout_counter[LIN_NUM_OF_IFCS]; +#endif /* End MULTI_TIMER_MODE */ + +/*************************** FUNCTIONS *******************/ + +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +void tl_process_mreq +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* decrease number of PDU for sending message */ + tl_conf->tl_tx_msg_size--; + /* Check message is sent completely */ + if (0 == tl_conf->tl_tx_msg_size) + { + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + tl_conf->tl_tx_msg_status = LD_COMPLETED; + *conf->tl_service_status = LD_REQUEST_FINISHED; + /* back to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*(conf->active_schedule_id)] = 0; + } + else + { + #ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; + #else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + #endif /* End MULTI_TIMER_MODE */ + tl_conf->tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; + } +} + + +/*FUNCTION*--------------------------------------------------------------*//** +* @fn void lin_process_pdu(l_ifc_handle iii, lin_tl_pdu_data *pdu) +* @brief LIN process packet data unit +* +* @param iii [IN] interface name +* @param pdu [IN] packet data unit +* +* @return #void +* +* @SDD_ID LIN_SDD_327 +* @endif +* +* @local_var +* -# #l_u8 pci_type +* -# #lin_configuration *conf +* -# #lin_tl_descriptor *tl_conf +* -# #l_u16 length +* -# #l_u8 tmp_frame_counter +* -# #lin_transport_layer_queue *tl_queue +* -# #l_u8 i +* +* +* @static_global_var +* -# #lin_ifc_configuration +* +* @see tl_get_raw +* @see tl_put_raw +* @see lin_tl_get_response +* +* @details +* LIN process packet data unit +*//*END*----------------------------------------------------------------------*/ + +static void lin_process_pdu(l_ifc_handle iii, lin_tl_pdu_data *pdu) +{ + l_u8 pci_type; + l_u16 length; + l_u8 tmp_frame_counter; + const lin_configuration * conf; + lin_tl_descriptor *tl_conf; + + /* Get the current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + tl_conf = conf->tl_desc; + + /* get PCI type */ + pci_type = ((*pdu)[1] & 0xF0) >> 4; + switch(pci_type) + { + case PCI_SF: + length = ((*pdu)[1]) & 0x0F; + /* check length of SF. If not valid, ignore this PDU */ + if (length <= 6) + { + if (_MASTER_ == conf->function) + { + /* reset queue header and queue tail */ + tl_conf->tl_rx_queue->queue_header = 0; + tl_conf->tl_rx_queue->queue_tail = 0; + tl_conf->tl_rx_queue->queue_current_size = 0; + tl_conf->tl_rx_queue->queue_status = LD_NO_DATA; + /* put to rx queue */ + tl_put_raw(&(conf->response_buffer[1]), tl_conf->tl_rx_queue, RECEIVING); + + /* process diagnostic interleaved mode */ + *conf->tl_diag_interleave_state = DIAG_NOT_START; + + /* set status is IDLE to receive new message */ + tl_conf->tl_receive_msg_status = LD_COMPLETED; + /* Exit Diagnostic Interleaved Mode*/ + *conf->diagnostic_mode = DIAG_NONE; + *conf->tl_service_status = LD_SERVICE_IDLE; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + + /* process response */ + lin_tl_get_response(iii); + + /*If Master node is running with Diagnostic Slave Response Schedule table */ + /* then switch back to previous normal table */ + if (*conf->active_schedule_id == (conf->schedule_start + 3)) + { + /* switch to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + + } + } + else /* Slave interface */ + { + /* put PDU to rx queue */ + tl_conf->tl_receive_msg_status = LD_COMPLETED; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + *conf->tl_service_status = LD_REQUEST_FINISHED; + /* reset queue header and queue tail */ + tl_conf->tl_rx_queue->queue_header = 0; + tl_conf->tl_rx_queue->queue_tail = 0; + tl_conf->tl_rx_queue->queue_current_size = 0; + tl_conf->tl_rx_queue->queue_status = LD_NO_DATA; + /* put to rx queue */ + tl_put_raw(&(conf->response_buffer[1]), tl_conf->tl_rx_queue, RECEIVING); + tl_conf->tl_frame_counter = 1; + tl_conf->tl_no_of_pdu = 1; + lin_tl_attach_service(iii); + } + } + break; + case PCI_FF: + /* for both MASTER and SLAVE */ + length = ((*pdu)[1] & 0x0F) * 256 + ((*pdu)[2]); + /* check length of FF. If not valid, ignore this PDU */ + if (length >= 7 && length <= (MAX_QUEUE_SIZE*6 - 1)) + { + /* Set check N_Cr timeout */ + + #ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; + #else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + #endif /* End MULTI_TIMER_MODE */ + + tl_conf->tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* put PDU to rx queue */ + /* reset queue header and queue tail */ + tl_conf->tl_rx_queue->queue_header = 0; + tl_conf->tl_rx_queue->queue_tail = 0; + tl_conf->tl_rx_queue->queue_current_size = 0; + tl_conf->tl_rx_queue->queue_status = LD_NO_DATA; + tl_put_raw(&(conf->response_buffer[1]), tl_conf->tl_rx_queue, RECEIVING); + + /* calculate number of PDU for this message */ + if ((length-5)%6 == 0) + { + tl_conf->tl_no_of_pdu = (l_u8)((length - 5) / 6); + } + else + { + tl_conf->tl_no_of_pdu = (l_u8)((length - 5) / 6) + 1; + } + /* set frame counter = 1 */ + tl_conf->tl_frame_counter = 1; + *conf->tl_service_status = LD_SERVICE_BUSY; + } + break; + case PCI_CF: + /* Only for MASTER */ + if (_MASTER_ == conf->function) + { + /* Set check N_Cr timeout */ + #ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; + #else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + #endif /* End MULTI_TIMER_MODE */ + tl_conf->tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* get frame counter of this PDU */ + tmp_frame_counter = ((*pdu)[1]&0x0F); + /* Check valid frame counter */ + if (tmp_frame_counter == tl_conf->tl_frame_counter) + { + /* increase frame counter */ + tl_conf->tl_frame_counter++; + if (tl_conf->tl_frame_counter > 15) + { + tl_conf->tl_frame_counter = 0; + } + /* decrease number of PDU to check message is complete */ + tl_conf->tl_no_of_pdu--; + /* put PDU to rx queue */ + tl_put_raw(&(conf->response_buffer[1]), tl_conf->tl_rx_queue, RECEIVING); + } + else + { + /* abort this message */ + tl_conf->tl_rx_msg_status = LD_WRONG_SN; + tl_conf->tl_receive_msg_status = LD_WRONG_SN; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + *conf->diagnostic_mode = DIAG_NONE; + + /*If Master node is running with Diagnostic Slave Response Schedule table */ + /* then switch back to previous normal table */ + if (*conf->active_schedule_id == (conf->schedule_start + 3)) + { + /* switch to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } + } + if (0 == tl_conf->tl_no_of_pdu) + { + /* message is received completely */ + + /* set status is IDLE to receive new message */ + tl_conf->tl_receive_msg_status = LD_COMPLETED; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + *conf->tl_service_status = LD_SERVICE_IDLE; + /* process diagnostic interleaved mode */ + if (*conf->current_pid == 0x3D && *conf->diagnostic_mode == DIAG_INTER_LEAVE_MODE) + { + *conf->tl_diag_interleave_state = DIAG_NOT_START; + *conf->diagnostic_mode = DIAG_NONE; + } + + /* call function to process this response */ + lin_tl_get_response(iii); + /*If Master node is running with Diagnostic Slave Response Schedule table */ + /* then switch back to previous normal table */ + if (*conf->active_schedule_id == (conf->schedule_start + 3)) + { + /* switch to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } + + } + } + else /* for SLAVE */ + { + /* Set check N_Cr timeout */ + #ifdef MULTI_TIMER_MODE + tl_conf->tl_check_timeout = max_tl_timeout_counter[iii]; + #else + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + #endif /* End MULTI_TIMER_MODE */ + tl_conf->tl_check_timeout_type = LD_CHECK_N_CR_TIMEOUT; + /* get frame counter of this PDU */ + tmp_frame_counter = ((*pdu)[1]&0x0F); + /* Check valid frame counter */ + if (tmp_frame_counter == tl_conf->tl_frame_counter) + { + /* increase frame counter */ + tl_conf->tl_frame_counter++; + if (tl_conf->tl_frame_counter > 15) + { + tl_conf->tl_frame_counter = 0; + } + /* decrease number of PDU to check message is complete */ + tl_conf->tl_no_of_pdu--; + /* put PDU to rx queue */ + tl_put_raw(&(conf->response_buffer[1]), tl_conf->tl_rx_queue, RECEIVING); + } + else + { + /* abort this message */ + tl_conf->tl_receive_msg_status = LD_WRONG_SN; + tl_conf->tl_rx_msg_status = LD_WRONG_SN; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } + if (0 == tl_conf->tl_no_of_pdu) + { + /* message is received completely */ + /* set status is IDLE to receive new message */ + tl_conf->tl_receive_msg_status = LD_COMPLETED; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + *conf->tl_service_status = LD_REQUEST_FINISHED; + + lin_tl_attach_service(iii); + } + } + break; + default: + /* ignore this PDU */ + break; + } +} + + +void lin_tl_handler_error +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] interface name */ + l_u8 pid +) +{ + const lin_configuration* conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL description */ + tl_conf = conf->tl_desc; + + /* for master */ + if ((_MASTER_ == conf->function) && (DIAG_INTER_LEAVE_MODE == *conf->diagnostic_mode)) + { + /* Master request */ + if (0x3C == pid) + { + /* update status of message and queue */ + tl_conf->tl_tx_msg_status = LD_FAILED; + tl_conf->tl_tx_queue->queue_status = LD_TRANSMIT_ERROR; + } + else /* Slave Response */ + { + /* update status of message and queue */ + tl_conf->tl_receive_msg_status = LD_FAILED; + tl_conf->tl_rx_msg_status = LD_FAILED; + tl_conf->tl_rx_queue->queue_status = LD_RECEIVE_ERROR; + } /* end of (0x3C == pid) */ + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + *conf->tl_service_status = LD_SERVICE_ERROR; + *conf->diagnostic_mode = DIAG_NONE; + /* switch to normal table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } + else + { + /* for slave */ + /* Master request */ + if (0x3C == pid) + { + /* update status of message and queue */ + tl_conf->tl_receive_msg_status = LD_FAILED; + tl_conf->tl_rx_msg_status = LD_FAILED; + tl_conf->tl_rx_queue->queue_status = LD_RECEIVE_ERROR; + tl_conf->tl_slaveresp_cnt = 0; + } + else /* Slave Response */ + { + /* update status of message and queue */ + tl_conf->tl_tx_msg_status = LD_FAILED; + tl_conf->tl_tx_queue->queue_status = LD_TRANSMIT_ERROR; + } /* end of (0x3C == pid) */ + *conf->tl_service_status = LD_SERVICE_ERROR; + tl_conf->tl_check_timeout_type = LD_NO_CHECK_TIMEOUT; + } +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + +void lin_tl_make_mreq_pdu +( + /* [IN] interface name */ + l_ifc_handle iii + /* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + ,/* [IN] PDU pointer */ + lin_tl_pdu_data *pdu_ptr +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ +) +{ + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + /* Single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + l_u8 i; + lin_tl_pdu_data *tl_tx_pdu; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + tl_get_raw(&conf->response_buffer[1], tl_conf->tl_tx_queue, TRANSMISSION); + conf->response_buffer[0] = 8; +#else /* single frame support */ + /* check if Service Mode and set current PDU pointer to PDU data based on Diag Service */ + + tl_conf->tl_current_tx_pdu_ptr = (lin_tl_pdu_data*)tl_conf->tl_tx_single_pdu; + tl_tx_pdu = (lin_tl_pdu_data*)tl_conf->tl_tx_single_pdu; + + for (i = 0; i < 8; ++i) + { + conf->response_buffer[i+1] = (*tl_tx_pdu)[i]; + } +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void lin_tl_make_slaveres_pdu +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] service identifier */ + l_u8 sid, + /* [IN] type of response */ + l_u8 res_type, + /* [IN] Error code in case of negative response, if positive = 0 */ + l_u8 error_code + +) +{ + const lin_configuration * conf; + lin_tl_descriptor *tl_conf; + lin_node_attribute *node_conf; + lin_product_id *ident; + l_u8 i; + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu_data lin_tl_pdu_buff, *lin_tl_pdu; + lin_transport_layer_queue *rx_queue; + lin_tl_pdu = (lin_tl_pdu_data *)&lin_tl_pdu_buff; +#else /* single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + lin_tl_pdu_data *lin_tl_rx_pdu; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL configuratio */ + tl_conf = conf->tl_desc; + + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* Get receive queue */ + rx_queue = tl_conf->tl_rx_queue; + + /* Single frame suport */ +#else + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* Get current PDU pointer of RX buffer */ + lin_tl_rx_pdu = tl_conf->tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + + /* Get the node attribute */ + node_conf = conf->node_attribute; + + /* Pack data to response PDU */ + (*lin_tl_pdu)[0] = node_conf->configured_NAD; + (*lin_tl_pdu)[1] = 0x03; /* PCI */ + (*lin_tl_pdu)[2] = RES_NEGATIVE; /* SID */ + (*lin_tl_pdu)[3] = sid; /* D0 */ + (*lin_tl_pdu)[4] = error_code; /* D1 */ + (*lin_tl_pdu)[5] = 0xFF; /* D2 */ + (*lin_tl_pdu)[6] = 0xFF; /* D3 */ + (*lin_tl_pdu)[7] = 0xFF; /* D4 */ + + switch (sid) + { + #if (LIN_PROTOCOL == PROTOCOL_J2602) + case SERVICE_TARGET_RESET: + (*lin_tl_pdu)[1] = 0x06; + + if (NEGATIVE == res_type) + { + (*lin_tl_pdu)[2] = RES_NEGATIVE; + } + else + { + + (*lin_tl_pdu)[2] = RES_POSITIVE+ sid; + } + + ident = (lin_product_id*)&node_conf->product_id; + (*lin_tl_pdu)[3] = (l_u8)(ident->supplier_id & 0xFF); + (*lin_tl_pdu)[4] = (l_u8)(ident->supplier_id >> 8); + (*lin_tl_pdu)[5] = (l_u8)(ident->function_id & 0xFF); + (*lin_tl_pdu)[6] = (l_u8)(ident->function_id >> 8); + (*lin_tl_pdu)[7] = ident->variant; + break; + #endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ + + #if (LIN_PROTOCOL == PROTOCOL_21) + case SERVICE_READ_BY_IDENTIFY: + if (NEGATIVE == res_type) + { + (*lin_tl_pdu)[1] = 0x03; + (*lin_tl_pdu)[2] = RES_NEGATIVE; + (*lin_tl_pdu)[3] = sid; + (*lin_tl_pdu)[4] = error_code; + (*lin_tl_pdu)[5] = 0xFF; + (*lin_tl_pdu)[6] = 0xFF; + (*lin_tl_pdu)[7] = 0xFF; + } + else + { + (*lin_tl_pdu)[1] = PCI_RES_READ_BY_IDENTIFY; + (*lin_tl_pdu)[2] = RES_POSITIVE + sid; + + if (error_code == LIN_PRODUCT_IDENT) + { + /* Get Identifier infor */ + ident = (lin_product_id*)&node_conf->product_id; + (*lin_tl_pdu)[3] = (l_u8)(ident->supplier_id & 0xFF); + (*lin_tl_pdu)[4] = (l_u8)(ident->supplier_id >> 8); + (*lin_tl_pdu)[5] = (l_u8)(ident->function_id & 0xFF); + (*lin_tl_pdu)[6] = (l_u8)(ident->function_id >> 8); + (*lin_tl_pdu)[7] = ident->variant; + } + else if (error_code >= LIN_READ_USR_DEF_MIN && error_code <= LIN_READ_USR_DEF_MAX) + { + l_u8 data_callout[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + l_u8 retval = ld_read_by_id_callout(iii, error_code, data_callout); + if (retval == LD_POSITIVE_RESPONSE) + { + /* packing user defined pdu */ + (*lin_tl_pdu)[3] = data_callout[0]; + (*lin_tl_pdu)[4] = data_callout[1]; + (*lin_tl_pdu)[5] = data_callout[2]; + (*lin_tl_pdu)[6] = data_callout[3]; + (*lin_tl_pdu)[7] = data_callout[4]; + } + /* Check for data values*/ + for (i = 4; i >= 0; i --) + { + if (data_callout[i] != 0xFF) + { + /* PCI: Data length is 1 (RSID) + all data exclude 0xFF */ + (*lin_tl_pdu)[1] = i + 2; + break; + } + } + } + } + break; + + case SERVICE_ASSIGN_FRAME_ID_RANGE: /* Mandatory for TL LIN 2.1 */ + if (POSITIVE == res_type) + { + (*lin_tl_pdu)[1] = PCI_RES_ASSIGN_FRAME_ID_RANGE; + (*lin_tl_pdu)[2] = RES_POSITIVE + sid; + (*lin_tl_pdu)[3] = 0xFF; + (*lin_tl_pdu)[4] = 0xFF; + } + break; + + case SERVICE_SAVE_CONFIGURATION: + if (POSITIVE == res_type) + { + /* PCI type */ + (*lin_tl_pdu)[1] = PCI_RES_SAVE_CONFIGURATION; + /* SID */ + (*lin_tl_pdu)[2] = RES_POSITIVE + sid; + /* Data unused */ + (*lin_tl_pdu)[3] = 0xFF; + (*lin_tl_pdu)[4] = 0xFF; + } + break; + case SERVICE_ASSIGN_NAD: + if (POSITIVE == res_type) + { + #if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + node_conf->configured_NAD = rx_queue->tl_pdu[rx_queue->queue_header][7]; + #else /* Single frame support */ + node_conf->configured_NAD = (*lin_tl_rx_pdu)[7]; + #endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Use intial NAD in response */ + (*lin_tl_pdu)[0] = node_conf->initial_NAD; + /* PCI */ + (*lin_tl_pdu)[1] = 0x01; + /* RSID */ + (*lin_tl_pdu)[2] = 0xF0; + (*lin_tl_pdu)[3] = 0xFF; + (*lin_tl_pdu)[4] = 0xFF; + } + break; + case SERVICE_CONDITIONAL_CHANGE_NAD: + (*lin_tl_pdu)[1] = 0x01; /* PCI */ + (*lin_tl_pdu)[2] = 0xF3; /* RSID */ + (*lin_tl_pdu)[3] = 0xFF; + (*lin_tl_pdu)[4] = 0xFF; + break; + #endif /* End (LIN_PROTOCOL == PROTOCOL_21) */ + default: + break; + } /* end of switch statement */ + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + tl_conf->tl_tx_queue->queue_status = LD_QUEUE_FULL; + tl_conf->tl_tx_queue->queue_current_size = 1; + /* Put to transmit queue */ + for (i = 0; i < 8; i++) + { + tl_conf->tl_tx_queue->tl_pdu[0][i] = (*lin_tl_pdu)[i]; + } + tl_conf->tl_tx_msg_size = 1; + /* Set check N_As timeout */ + tl_conf->tl_check_timeout = N_MAX_TIMEOUT_CNT; + tl_conf->tl_check_timeout_type = LD_CHECK_N_AS_TIMEOUT; +#else /* single frame support */ + /* set current TX PDU to send out */ + tl_conf->tl_current_tx_pdu_ptr = lin_tl_pdu; + tl_check_timeout_array[iii] = N_MAX_TIMEOUT_CNT; + tl_check_timeout_type_array[iii] = LD_CHECK_N_AS_TIMEOUT; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* set number of SlaveResp response data */ + tl_conf->tl_slaveresp_cnt = 1; +} + + +void lin_tl_get_pdu +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + l_u8 i; + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data lin_tl_pdu_buff; + lin_tl_pdu_data *lin_tl_pdu = (lin_tl_pdu_data *)&lin_tl_pdu_buff; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* Get data from tx queue */ + tl_get_raw(*lin_tl_pdu, tl_conf->tl_tx_queue, TRANSMISSION); +#else /* single frame support */ + /* Get current PDU poiter of TX buffer */ + lin_tl_pdu = tl_conf->tl_current_tx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Copy PDU to response buffer */ + for (i = 1; i < 9; i++) + { + conf->response_buffer[i] = (*lin_tl_pdu)[i - 1]; + } +} + + +void lin_tl_handler +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration * conf; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data *lin_tl_pdu; + lin_node_attribute *node_conf; + l_u8 pci_type; + + /* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + l_u8 length; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + + /* Get the current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* Get the node attribute */ + node_conf = (lin_node_attribute *)conf->node_attribute; + + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_tl_pdu = (lin_tl_pdu_data *)&(conf->response_buffer[1]); + pci_type = ((*lin_tl_pdu)[1] & 0xF0) >> 4; +#else /* single frame support */ + lin_tl_pdu = tl_conf->tl_current_rx_pdu_ptr; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* check NAD whether or not belongs to this slave node */ + if (_SLAVE_ == conf->function) + { + if ((LD_BROADCAST != (*lin_tl_pdu)[0]) && \ + (LD_FUNCTIONAL_NAD != (*lin_tl_pdu)[0]) && \ + (((node_conf->configured_NAD != (*lin_tl_pdu)[0]) && (SERVICE_ASSIGN_NAD != (*lin_tl_pdu)[2])) || \ + ((node_conf->initial_NAD != (*lin_tl_pdu)[0]) && (SERVICE_ASSIGN_NAD == (*lin_tl_pdu)[2])))) + { + tl_conf->tl_slaveresp_cnt = 0; + return; + } + } + /* ingore Functional request */ + if ((*lin_tl_pdu)[0] == LD_FUNCTIONAL_NAD) + { + return; + } + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* check error */ + if (*conf->tl_service_status == LD_SERVICE_ERROR && pci_type == PCI_CF) + { + return; + } + /* process received PDU */ + lin_process_pdu(iii, lin_tl_pdu); +#else /* single frame support */ + /* Get PCI type */ + pci_type = ((*lin_tl_pdu)[1] & 0xF0) >> 4; + switch (pci_type) + { + case PCI_SF: /* Single frame */ + /* error handling: check length of message */ + length = (*lin_tl_pdu)[1] & 0x0F; + if (6 < length) + { + return; + } + if (_SLAVE_ == conf->function) + { + lin_tl_attach_service(iii); + } + else + { + lin_tl_get_response(iii); + } + break; + case PCI_FF: /* First frame */ + break; + case PCI_CF: /* Consecutive frame */ + break; + default: + break; + } /* end of ckeck PCI_type */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + + +void lin_tl_attach_service (l_ifc_handle iii) +{ + const lin_configuration* conf; + lin_tl_descriptor *tl_conf; + lin_node_attribute *node_conf; + l_u8 sid; + + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + l_u8 frame_type; + lin_transport_layer_queue *rx_queue, *tx_queue; + l_u8 *service_flag; + l_u8 *service_supported; + l_u8 i; + l_u8 sid_supported_flag; + l_u8 NAD; + l_u16 supplierIdLsb; + l_u16 supplierIdMsb; + l_u16 functionIdLsb; + l_u16 functionIdMsb; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get the node attribute */ + node_conf = (lin_node_attribute *)conf->node_attribute; + /* Get TL description */ + tl_conf = conf->tl_desc; + /* Get support sid */ + service_supported = tl_conf->tl_service_supported; + service_flag = tl_conf->tl_service_flags; + rx_queue = tl_conf->tl_rx_queue; + tx_queue = tl_conf->tl_tx_queue; + NAD = rx_queue->tl_pdu[rx_queue->queue_header][0]; + /* check if request is functional request */ + if (NAD == LD_FUNCTIONAL_NAD) + { + /* reset receive queue */ + rx_queue->queue_current_size = 0; + rx_queue->queue_header = 0; + rx_queue->queue_tail = 0; + rx_queue->queue_status = LD_NO_DATA; + /* update service state */ + *conf->tl_diag_state = LD_DIAG_IDLE; + *conf->tl_service_status = LD_SERVICE_IDLE; + /* ignore response */ + tl_conf->tl_no_of_pdu = 0; + tl_conf->tl_frame_counter = 0; + return; + } + /* prepare tx queue */ + tx_queue->queue_current_size = 0; + tx_queue->queue_header = 0; + tx_queue->queue_tail = 0; + tx_queue->queue_status = LD_QUEUE_EMPTY; + /* Check whether RX Queue contains data */ + if ((LD_DATA_AVAILABLE == ld_raw_rx_status(iii))) + { + /* get frame type */ + frame_type = (rx_queue->tl_pdu[rx_queue->queue_header][1] & 0xF0) >> 4; + /* Get SID information */ + if (frame_type == PCI_FF) + { + sid = rx_queue->tl_pdu[rx_queue->queue_header][3]; + } + else + { + sid = rx_queue->tl_pdu[rx_queue->queue_header][2]; + } + + sid_supported_flag = 0; + for (i = 0; i < tl_conf->number_support_sid; i++) + { + if (service_supported[i] == sid) + { + service_flag[i] = 1; + sid_supported_flag = 1; + break; + } + } + + if (sid_supported_flag == 1) + { + switch (sid) + { +#if (LIN_PROTOCOL == PROTOCOL_21) + case SERVICE_ASSIGN_FRAME_ID_RANGE: /* Mandatory for TL LIN 2.1 */ + lin_diagservice_assign_frame_id_range(iii); + break; + case SERVICE_READ_BY_IDENTIFY: /* Mandatory for TL LIN 2.1 & 2.0, Reject by J2602 */ + lin_diagservice_read_by_identifier(iii); /* Mandatory LIN TL 2.1 */ + break; + case SERVICE_SAVE_CONFIGURATION: + /* Set save configuration flag */ + if (_MASTER_ == conf->function) + { + lin_save_configuration_flg[iii] = 0U; + } + else + { + lin_save_configuration_flg[iii] = 1U; + } + /* Response to master - RSID */ + lin_tl_make_slaveres_pdu(iii, SERVICE_SAVE_CONFIGURATION, POSITIVE, 0U); + break; + case SERVICE_ASSIGN_NAD: + /* Get Supplier ID and Function ID*/ + if ((NAD == node_conf->initial_NAD)|| (NAD == LD_BROADCAST)) + { + supplierIdLsb = rx_queue->tl_pdu[rx_queue->queue_header][3]; + supplierIdMsb = rx_queue->tl_pdu[rx_queue->queue_header][4]; + functionIdLsb = rx_queue->tl_pdu[rx_queue->queue_header][5]; + functionIdMsb = rx_queue->tl_pdu[rx_queue->queue_header][6]; + /*Check if Supplier ID and Function ID match, then send positive response */ + if ((((supplierIdMsb<<8)|supplierIdLsb) == (node_conf->product_id).supplier_id)||(((supplierIdMsb<<8)|supplierIdLsb) == LD_ANY_SUPPLIER)) + if ((((functionIdMsb<<8)|functionIdLsb) == (node_conf->product_id).function_id)||(((functionIdMsb<<8)|functionIdLsb) == LD_ANY_FUNCTION)) + { + lin_tl_make_slaveres_pdu(iii,SERVICE_ASSIGN_NAD, POSITIVE, 0); + } + } + break; + case SERVICE_CONDITIONAL_CHANGE_NAD: + lin_condittional_change_nad(iii); + break; +#endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_21) */ + +#if LIN_PROTOCOL == PROTOCOL_J2602 + case SERVICE_TARGET_RESET: + if (LIN_PROTOCOL_J2602 == conf->lin_protocol_version) + { + lin_diagservice_target_reset(iii); + } + break; +#endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_J2602) */ + default: + break; + } + } + else + { + lin_tl_make_slaveres_pdu(iii, sid, NEGATIVE, SERVICE_NOT_SUPPORTED); + /* clear queue */ + tl_conf->tl_receive_msg_status = LD_NO_MSG; + tl_conf->tl_rx_msg_status = LD_COMPLETED; + rx_queue->queue_status = LD_NO_DATA; + rx_queue->queue_current_size = 0; + rx_queue->queue_header = rx_queue->queue_tail; + } + } + +#else /* single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + l_u8 NAD; + l_u8 *service_flag; + l_u8 *service_supported; + l_u8 i; + l_u8 sid_supported_flag; + l_u16 supplierIdLsb; + l_u16 supplierIdMsb; + l_u16 functionIdLsb; + l_u16 functionIdMsb; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get the node attribute */ + node_conf = (lin_node_attribute *)conf->node_attribute; + /* Get TL description */ + tl_conf = conf->tl_desc; + /* Get support sid */ + service_supported = tl_conf->tl_service_supported; + /* Get service flag */ + service_flag = tl_conf->tl_service_flags; + /* Get current PDU pointer of RX buffer */ + lin_tl_pdu = tl_conf->tl_current_rx_pdu_ptr; + /* Get SCI information */ + sid = (*lin_tl_pdu)[2]; + NAD = (*lin_tl_pdu)[0]; + if (NAD == LD_FUNCTIONAL_NAD) + { + + return; + } + + sid_supported_flag = 0; + for (i = 0; i < tl_conf->number_support_sid; i++) + { + if (service_supported[i] == sid) + { + service_flag[i] = 1; + sid_supported_flag = 1; + break; + } + } + + if (sid_supported_flag == 1) + {/* Check whether or not the Service is supported by the Slave node */ + switch (sid) + { + #if LIN_PROTOCOL == PROTOCOL_21 + case SERVICE_ASSIGN_FRAME_ID_RANGE: /* Mandatory for TL LIN 2.1 */ + lin_diagservice_assign_frame_id_range(iii); + break; + case SERVICE_READ_BY_IDENTIFY: /* Mandatory for TL LIN 2.1 & 2.0, Reject by J2602 */ + lin_diagservice_read_by_identifier(iii); /* Mandatory LIN TL 2.1 */ + break; + + case SERVICE_SAVE_CONFIGURATION: + /* Set save configuration flag */ + if (_MASTER_ == conf->function) + { + lin_save_configuration_flg[iii] = 0; + } + else + { + lin_save_configuration_flg[iii] = 1; + } + /* Response to master - RSID */ + lin_tl_make_slaveres_pdu(iii, SERVICE_SAVE_CONFIGURATION, POSITIVE, 0); + break; + case SERVICE_ASSIGN_NAD: + if ((NAD == node_conf->initial_NAD)|| (NAD == LD_BROADCAST)) + { + supplierIdLsb = (*lin_tl_pdu)[3]; + supplierIdMsb = (*lin_tl_pdu)[4]; + functionIdLsb = (*lin_tl_pdu)[5]; + functionIdMsb = (*lin_tl_pdu)[6]; + /*Check if Supplier ID and Function ID match, then send positive response */ + if ((((supplierIdMsb<<8)|supplierIdLsb) == (node_conf->product_id).supplier_id)||(((supplierIdMsb<<8)|supplierIdLsb) == LD_ANY_SUPPLIER)) + if ((((functionIdMsb<<8)|functionIdLsb) == (node_conf->product_id).function_id)||(((functionIdMsb<<8)|functionIdLsb) == LD_ANY_FUNCTION)) + { + lin_tl_make_slaveres_pdu(iii,SERVICE_ASSIGN_NAD, POSITIVE, 0); + } + } + break; + case SERVICE_CONDITIONAL_CHANGE_NAD: + lin_condittional_change_nad(iii); + break; + #endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_21) */ + + #if LIN_PROTOCOL == PROTOCOL_J2602 + case SERVICE_TARGET_RESET: + if (LIN_PROTOCOL_J2602 == conf->lin_protocol_version) + { + lin_diagservice_target_reset(iii); + } + break; + #endif /* (End LIN_PROTOCOL == LIN_PROTOCOL_J2602) */ + default: + break; + } + } + else + { + lin_tl_make_slaveres_pdu(iii, sid, NEGATIVE, SERVICE_NOT_SUPPORTED); + } + +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void lin_tl_get_response (l_ifc_handle iii) +{ + const lin_configuration* conf; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data *lin_tl_pdu; + l_u8 *service_flag; + l_u8 *service_supported; + l_u8 i; + l_u8 sid_supported_flag; + l_u8 sci = 0; +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + lin_transport_layer_queue *rx_queue; + l_u8 frame_type; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL description */ + tl_conf = conf->tl_desc; + /* Get support sid */ + service_supported = tl_conf->tl_service_supported; + /* Get service flag */ + service_flag = tl_conf->tl_service_flags; + + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + /* Get current PDU pointer of RX buffer */ + rx_queue = tl_conf->tl_rx_queue; + lin_tl_pdu = (lin_tl_pdu_data *)(tl_conf->tl_rx_queue->tl_pdu[rx_queue->queue_header]); + /* get frame type */ + frame_type = ((*lin_tl_pdu)[1] & 0xF0) >> 4; + /* Set configuration service status */ + *conf->tl_service_status = LD_SERVICE_IDLE; + if (frame_type == SF) + { + sci = (*lin_tl_pdu)[2]; + } + else if (frame_type == FF) + { + sci = (*lin_tl_pdu)[3]; + } +#else /* single frame support */ + /* Get current PDU pointer of RX buffer */ + lin_tl_pdu = tl_conf->tl_current_rx_pdu_ptr; + tl_conf->tl_service_status = LD_SERVICE_IDLE; + sci = (*lin_tl_pdu)[2]; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /* Update last RSID */ + tl_conf->tl_last_RSID = sci; + /* Get SID information */ + + if (RES_NEGATIVE == sci) + { + /* set response configuration status to negative response */ + tl_conf->tl_last_cfg_result = LD_NEGATIVE; + /* update error code */ + tl_conf->tl_ld_error_code = (*lin_tl_pdu)[4]; + + /* switch to normal schedule table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + /* Clear queue */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + tl_conf->tl_rx_msg_status = LD_COMPLETED; + *conf->tl_service_status = LD_SERVICE_IDLE; +#else + tl_conf->tl_service_status = LD_SERVICE_IDLE; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + return; + } + sci = sci - 0x40; + + sid_supported_flag = 0; + for (i = 0; i < tl_conf->number_support_sid; i++) + { + if (service_supported[i] == sci) + { + service_flag[i] = 1; + sid_supported_flag = 1; + break; + } + } + if (sid_supported_flag == 1) + { + + sid_supported_flag = 0; + /* Check the result of service */ + switch (sci) + { + case SERVICE_READ_BY_IDENTIFY: + (tl_conf->tl_ident_data)[0] = (*lin_tl_pdu)[4]; + (tl_conf->tl_ident_data)[1] = (*lin_tl_pdu)[3]; + (tl_conf->tl_ident_data)[2] = (*lin_tl_pdu)[6]; + (tl_conf->tl_ident_data)[3] = (*lin_tl_pdu)[5]; + (tl_conf->tl_ident_data)[4] = (*lin_tl_pdu)[7]; + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + tl_conf->tl_rx_msg_status = LD_COMPLETED; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + break; + case SERVICE_TARGET_RESET: + case SERVICE_ASSIGN_FRAME_ID: + case SERVICE_ASSIGN_FRAME_ID_RANGE: + case SERVICE_ASSIGN_NAD: + case SERVICE_CONDITIONAL_CHANGE_NAD: + case SERVICE_SAVE_CONFIGURATION: + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + tl_conf->tl_rx_msg_status = LD_COMPLETED; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + break; + /* check diagnostic service is belong to class II or class III */ + default: + break; + } + } + /* Set the last configuration result */ + tl_conf->tl_last_cfg_result = LD_SUCCESS; + +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + *conf->tl_service_status = LD_SERVICE_IDLE; +#else + tl_conf->tl_service_status = LD_SERVICE_IDLE; +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ + /*If Master node is running with Diagnostic Slave Response Schedule table */ + /* then switch back to previous normal table */ + if (*conf->active_schedule_id == (conf->schedule_start + 3)) + { + /* switch to normal schedule table */ + *conf->active_schedule_id = *conf->previous_schedule_id; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + } +} + + +/* single frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) + +void lin_tl_update_tx_flag +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* Check if master node */ + if (_MASTER_ == conf->function) + { + /* Update TX : Master ->Slave */ + /* Master request */ + if (0x3C == *(conf->current_pid)) + { + tl_conf->tl_cnt_to_send--; + /* Set state of service is LD_REQUEST_FINISHED */ + tl_conf->tl_service_status = LD_REQUEST_FINISHED; + } + } + /* Slave node */ + else + { + /* Update TX SlaveResponse Frame: Slave->Master */ + + } +} + +void lin_tl_put_pdu +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + l_u8 i; + const lin_configuration *conf; + lin_tl_descriptor *tl_conf; + lin_tl_pdu_data *lin_tl_pdu; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Get TL configuration */ + tl_conf = conf->tl_desc; + + /* Set PDU for RX buffer */ + tl_conf->tl_current_rx_pdu_ptr = (lin_tl_pdu_data *)tl_conf->tl_rx_single_pdu; + + /* Get current PDU poiter of RX buffer */ + lin_tl_pdu = tl_conf->tl_current_rx_pdu_ptr; + + for (i = 0; i < 8; i++) + { + (*lin_tl_pdu)[i] = conf->response_buffer[i+1]; + } +} + + +void lin_tl_no_response +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + const lin_configuration* conf; + + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Clear response data */ + conf->tl_desc->tl_slaveresp_cnt = 0; + /* Set configuration service status */ + conf->tl_desc->tl_service_status = LD_SERVICE_ERROR; + /* Set the last configuration result */ + conf->tl_desc->tl_last_cfg_result = LD_NO_RESPONSE; +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_SINGLE_FRAME_) */ + + +#endif /* End (_LIN_MODE_ == _MASTER_MODE_) */ + +/* ------------- End of code for Multi Interface --------------- */ +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* COMMON FUNCTIONS */ +void tl_put_raw +( + /* [IN] buffer for the data */ + const l_u8* const data, + /* [IN] queue for containing data */ + lin_transport_layer_queue *queue, + /* [IN] Direction */ + l_u8 direction +) +{ + lin_tl_pdu_data *queue_data; + l_u8 i; + + /* Get transmit queue */ + queue_data = queue->tl_pdu; + + /* check status of queue */ + if (LD_QUEUE_FULL != queue->queue_status) + { + /* prcess queue tail */ + if ((LD_QUEUE_EMPTY == queue->queue_status) || (LD_NO_DATA == queue->queue_status)) + { + /* Set status of queue */ + if (TRANSMISSION == direction) + { + queue->queue_status = LD_QUEUE_AVAILABLE; + } + else + { + queue->queue_status = LD_DATA_AVAILABLE; + } + } + else + { + /* Check if queue size equal to queue tail */ + if (queue->queue_max_size == queue->queue_tail + 1) + { + queue->queue_tail = 0; + } + else + { + queue->queue_tail++; + } + } + /* copy data to queue */ + for (i = 0; i < 8; i++) + { + queue_data[queue->queue_tail][i] = data[i]; + } + /* update queue status */ + queue->queue_current_size++; + if (queue->queue_current_size >= queue->queue_max_size) + { + queue->queue_status = LD_QUEUE_FULL; + } + } +} + +void tl_get_raw +( + /* [OUT] buffer for store data received */ + l_u8* const data, + /* queue for containing data */ + lin_transport_layer_queue *queue, + /* direction for transmission */ + l_u8 direction +) +{ + + lin_transport_layer_queue *tl_queue; + lin_tl_pdu_data *queue_data; + l_u8 i; + l_u16 queue_header; + + tl_queue = queue; + /* Get queue */ + queue_data = tl_queue->tl_pdu; + + /* Check queue status (is the queue contains data? if yes: get data from queue and put them to buffer) */ + if ((LD_NO_DATA != tl_queue->queue_status) && (LD_QUEUE_EMPTY != tl_queue->queue_status)) + { + /* get data from head queue */ + queue_header = tl_queue->queue_header; + for (i = 0; i < 8; i++) + { + *(data+i) = queue_data[queue_header][i]; + } + + /* update queue status */ + if (0 == (--queue->queue_current_size)) + { + if (TRANSMISSION == direction) + { + queue->queue_status = LD_QUEUE_EMPTY; + } + else + { + queue->queue_status = LD_NO_DATA; + } + } + else + { + if (TRANSMISSION == direction) + { + queue->queue_status = LD_QUEUE_AVAILABLE; + } + else + { + queue->queue_status = LD_DATA_AVAILABLE; + } + } + + /* change queue header */ + if (0 != queue->queue_current_size) + { + if (queue->queue_header == queue->queue_max_size - 1) + { + queue->queue_header = 0; + } + else + { + queue->queue_header++; + } + } + } +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +/** + * @} + */ diff --git a/LIN_Stack/transport/lin_j2602tl_api.c b/LIN_Stack/transport/lin_j2602tl_api.c new file mode 100644 index 0000000..231ef13 --- /dev/null +++ b/LIN_Stack/transport/lin_j2602tl_api.c @@ -0,0 +1,146 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2008-2015 Freescale Semiconductor, Inc. +* ALL RIGHTS RESERVED. +* +******************************************************************************/ + +/**************************************************************************//** +* @addtogroup j2602tl_api_group +* @{ +******************************************************************************/ +/**************************************************************************//** +* +* @file lin_j2602tl_api.c +* +* @author FPT Software +* +* @brief J2602 LIN transport layer and configuration functions +* +******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090409 v1.0 First version + * + *****************************************************************************/ + +/** + * @} + */ + +#include "lin_j2602tl_api.h" + +#if LIN_MODE == _MASTER_MODE_ +#if LIN_PROTOCOL == PROTOCOL_J2602 + +/** @addtogroup j2602tl_api_group +* @{ */ +l_bool ld_is_ready +( + /* [IN] interface name */ + l_ifc_handle iii +) +{ + lin_configuration const *conf; + + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Check the service status */ + if (LD_SERVICE_BUSY == conf->tl_desc->tl_service_status) + { + return 0; + } + + return 1; +} + + +l_u8 ld_check_response +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [OUT] buffer for saving the response ID */ + l_u8* const RSID, + /* [OUT] buffer for saving the error code */ + l_u8* const error_code +) +{ + lin_last_cfg_result temp; + lin_configuration const *conf; + lin_tl_descriptor *_tl_desc; + + + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get the TL configuration */ + _tl_desc = conf->tl_desc; + + /* Get the status of the last service */ + temp = (lin_last_cfg_result)(_tl_desc->tl_last_cfg_result); + /* Check status of last configuration */ + switch (temp) + { + case LD_SUCCESS: + *RSID = _tl_desc->tl_last_RSID; + break; + case LD_NEGATIVE: + *RSID = _tl_desc->tl_last_RSID; + *error_code = _tl_desc->tl_ld_error_code; + break; + default: + break; + } /* end of switch */ + + return (l_u8)temp; +} + + +void ld_assign_frame_id +( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] initial node address of the target node */ + l_u8 initial_NAD, + /* [IN] supplier ID of the target node */ + l_u16 supplier_id, + /* [IN] message ID of the target node */ + l_u16 message_id, + /* [IN] protected ID of the target node */ + l_u8 PID +) +{ + lin_tl_pdu_data *lin_tl_pdu; + + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + /* Create data for PDU */ + (*lin_tl_pdu)[0] = initial_NAD; + (*lin_tl_pdu)[1] = 0x06; + (*lin_tl_pdu)[2] = 0xB1; + (*lin_tl_pdu)[3] = supplier_id &0x00FF; + (*lin_tl_pdu)[4] = (supplier_id >> 8) & 0x00FF; + (*lin_tl_pdu)[5] = message_id &0x00FF; + (*lin_tl_pdu)[6] = (message_id >> 8) & 0x00FF; + (*lin_tl_pdu)[7] = PID; + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + } /* End of checking service status */ +} +/** @} */ +#endif /* End (LIN_PROTOCOL == PROTOCOL_J2602) */ +#endif /* End LIN_MODE == _MASTER_MODE_ */ diff --git a/LIN_Stack/transport/lin_lin21tl_api.c b/LIN_Stack/transport/lin_lin21tl_api.c new file mode 100644 index 0000000..5cb5981 --- /dev/null +++ b/LIN_Stack/transport/lin_lin21tl_api.c @@ -0,0 +1,425 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2008-2015 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ******************************************************************************/ + +/**************************************************************************//** + * @addtogroup lin21tl_api_group + * @{ + ******************************************************************************/ +/**************************************************************************//** + * + * @file lin_lin21tl_api.c + * + * @author FPT Software + * + * @brief LIN21 LIN transport layer and configuration functions + * + ******************************************************************************/ +/****************************************************************************** + * + * History: + * + * 20090409 v1.0 First version + * + *****************************************************************************/ + +#include "lin_lin21tl_api.h" + +#if LIN_MODE == _MASTER_MODE_ +#if LIN_PROTOCOL == PROTOCOL_21 + + +/** @} */ + +/** @addtogroup node_configuration_group + * @{ */ +l_u8 ld_is_ready( + /* [IN] interface name */ + l_ifc_handle iii) +{ + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + return (l_u8) (*lin_ifc_configuration[iii].tl_service_status); +#else /* single frame support */ + lin_configuration const *conf; + /* Get current configuration */ + conf = &lin_ifc_configuration[iii]; + return (l_u8)(conf->tl_desc->tl_service_status); +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} + +void ld_check_response( + /* [IN] interface name */ + l_ifc_handle iii, + /* [OUT] buffer for saving the response ID */ + l_u8* const RSID, + /* [OUT] buffer for saving the error code */ + l_u8* const error_code) +{ + lin_configuration const *conf; + lin_tl_descriptor *_tl_desc; + + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + /* Get TL configuration */ + _tl_desc = conf->tl_desc; + /* Get last reponse service identifier */ + *RSID = _tl_desc->tl_last_RSID; + /* Get the error code of the last config sercive if it is negative response */ + if (LD_NEGATIVE == (_tl_desc->tl_last_cfg_result)) + { + *error_code = _tl_desc->tl_ld_error_code; + } +} + +void ld_assign_frame_id_range( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] NAD value of the target node */ + l_u8 NAD, + /* [IN] specifies which is the first frame to assign a PID */ + l_u8 start_index, + /* [IN] list of protected identifier */ + const l_u8* const PIDs) +{ + /* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) + const lin_configuration * conf; + l_u8 Buff[6]; + + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + /* pack data into a single frame */ + Buff[0] = 0xB7; + Buff[1] = start_index; + Buff[2] = PIDs[0]; + Buff[3] = PIDs[1]; + Buff[4] = PIDs[2]; + Buff[5] = PIDs[3]; + + /* put data into TX_QUEUE */ + ld_send_message(iii, 6, NAD, Buff); + + /* set node config status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } +#else /* single frame support */ + lin_tl_pdu_data *lin_tl_pdu; + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + + /* Get current configuration */ + conf = (lin_configuration *)&lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + /* Get pointer to TX single frame PDU */ + lin_tl_pdu = (lin_tl_pdu_data *)tl_conf->tl_tx_single_pdu; + + /* check service is busy? */ + if (LD_SERVICE_BUSY != tl_conf->tl_service_status) + { + /* Create data for PDU */ + (*lin_tl_pdu)[0] = NAD; + (*lin_tl_pdu)[1] = 0x06; + (*lin_tl_pdu)[2] = 0xB7; + (*lin_tl_pdu)[3] = start_index; + (*lin_tl_pdu)[4] = PIDs[0]; + (*lin_tl_pdu)[5] = PIDs[1]; + (*lin_tl_pdu)[6] = PIDs[2]; + (*lin_tl_pdu)[7] = PIDs[3]; + + /* Set state of service is BUSY */ + tl_conf->tl_service_status = LD_SERVICE_BUSY; + /* Notify to Master task sending frame */ + tl_conf->tl_cnt_to_send = 1; + + /* Switch to master request schedule table */ + *conf->previous_schedule_id = *conf->active_schedule_id; + *conf->active_schedule_id = conf->schedule_start + 2; + conf->schedule_start_entry[*conf->active_schedule_id] = 0; + + /* End of switch to diagnostic schedule table */ + } /* End of checking service status */ +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +} /* End of checking service status */ +/** @} */ + +/** @addtogroup lin21tl_api_group + * @{ */ +/* multi frame support */ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +l_u8 diag_get_flag( + /* [IN] interface name */ + l_ifc_handle iii, + /* [IN] flag order */ + l_u8 flag_order) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + l_u8 *service_flag; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + service_flag = tl_conf->tl_service_flags; + + if (flag_order >= tl_conf->number_support_sid) + { + return 0; + } + else + { + return (l_u8) service_flag[flag_order]; + } + +} + +void diag_clear_flag(l_ifc_handle iii, l_u8 flag_order) +{ + lin_configuration *conf; + lin_tl_descriptor *tl_conf; + l_u8 *service_flag; + + /* Get current configuration */ + conf = (lin_configuration *) &lin_ifc_configuration[iii]; + /* Get TL configuration */ + tl_conf = conf->tl_desc; + service_flag = tl_conf->tl_service_flags; + + if (flag_order < tl_conf->number_support_sid) + { + service_flag[flag_order] = 0; + } +} +/* diagnostic services class II */ +void diag_read_data_by_identifier(l_ifc_handle iii, const l_u8 NAD, + l_u8 * const data) +{ + + l_u8 Buff[3]; + const lin_configuration *conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + /* check whether input data contains correct data */ + + /* pack data */ + Buff[0] = 0x22; + Buff[1] = data[0]; + Buff[2] = data[1]; + + /* send message to transport layer */ + ld_send_message(iii, 3, NAD, Buff); + + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } +} + +void diag_write_data_by_identifier(l_ifc_handle iii, const l_u8 NAD, + l_u16 data_length, l_u8 * const data) +{ + l_u8 Buff[MAX_LENGTH_SERVICE]; + l_u8 i; + l_u16 temp = 0; + + const lin_configuration * conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Check if length of data is greater than length maximum */ + if (data_length < MAX_LENGTH_SERVICE) + { + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + /* check whether input data contains correct data */ + temp = data[0]; + temp <<= 8; + temp |= data[1]; + + /* pack data */ + Buff[0] = 0x2E; + + if ((temp == 0x0092) || (temp == 0x0205)) + { + for (i = 0; i < data_length; i++) + { + Buff[i + 1] = data[i]; + } + ld_send_message(iii, data_length + 1, NAD, Buff); + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } + } + } +} + +/* Diagnostic services class III */ +#if (_DIAG_CLASS_SUPPORT_ == _DIAG_CLASS_III_) + +/* ----------------- Session control -------------------- */ +void diag_session_control (l_ifc_handle iii, const l_u8 NAD, l_u16 data_length, l_u8 *const data) +{ + l_u8 Buff[MAX_LENGTH_SERVICE]; + l_u8 i; + + const lin_configuration * conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Check if length of data is greater than length maximum */ + if (data_length < MAX_LENGTH_SERVICE) + { + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + /* pack data */ + Buff[0] = 0x10; + + for (i = 0; i < data_length; i++) + { + Buff[i+1] = data[i]; + } + ld_send_message(iii, data_length+1, NAD, Buff); + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } + } +} + +/* ----------------- Fault memory -------------------- */ +void diag_fault_memory_read (l_ifc_handle iii, const l_u8 NAD, l_u16 data_length, l_u8 *const data) +{ + l_u8 Buff[MAX_LENGTH_SERVICE]; + l_u8 i; + l_u16 temp = 0; + + const lin_configuration * conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Check if length of data is greater than length maximum */ + if (data_length < MAX_LENGTH_SERVICE) + { + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + + /* pack data */ + Buff[0] = 0x19; + + for (i = 0; i < data_length; i++) + { + Buff[i+1] = data[i]; + } + ld_send_message(iii, data_length+1, NAD, Buff); + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } + } +} +void diag_fault_memory_clear (l_ifc_handle iii, const l_u8 NAD, l_u16 data_length, l_u8 *const data) +{ + l_u8 Buff[MAX_LENGTH_SERVICE]; + l_u8 i; + l_u16 temp = 0; + + const lin_configuration * conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Check if length of data is greater than length maximum */ + if (data_length < MAX_LENGTH_SERVICE) + { + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + + /* pack data */ + Buff[0] = 0x14; + + for (i = 0; i < data_length; i++) + { + Buff[i+1] = data[i]; + } + ld_send_message(iii, data_length+1, NAD, Buff); + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } + } +} +/* ----------------- I/O control -------------------- */ +void diag_IO_control (l_ifc_handle iii, const l_u8 NAD, l_u16 data_length, l_u8 *const data) +{ + l_u8 Buff[MAX_LENGTH_SERVICE]; + l_u8 i; + l_u16 temp = 0; + + const lin_configuration * conf; + /* Get the current configuration */ + conf = &lin_ifc_configuration[iii]; + + /* Check if length of data is greater than length maximum */ + if (data_length < MAX_LENGTH_SERVICE) + { + /* check whether service status is idle or not */ + if (*conf->tl_service_status != LD_SERVICE_BUSY) + { + + /* pack data */ + Buff[0] = 0x2F; + + for (i = 0; i < data_length; i++) + { + Buff[i+1] = data[i]; + } + ld_send_message(iii, data_length+1, NAD, Buff); + /* set service status to busy */ + *conf->tl_service_status = LD_SERVICE_BUSY; + } + } +} + +#endif /* End (_DIAG_CLASS_SUPPORT_ == _DIAG_CLASS_III_) */ + +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif /* End of (LIN_PROTOCOL == PROTOCOL_21) */ +#endif /* End LIN_MODE == _MASTER_MODE_ */ +#if LIN_MODE == _SLAVE_MODE_ +#if (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) +/* get diagnostic flag */ +l_u8 diag_get_flag(l_u8 flag_order) +{ + if (flag_order >= _DIAG_NUMBER_OF_SERVICES_) + { + return 0; + } + else + { + return (l_u8) lin_diag_services_flag[flag_order]; + } + +} + +void diag_clear_flag(l_u8 flag_order) +{ + if (flag_order < _DIAG_NUMBER_OF_SERVICES_) + { + lin_diag_services_flag[flag_order] = 0; + } +} +#endif /* End (_TL_FRAME_SUPPORT_ == _TL_MULTI_FRAME_) */ +#endif/* End LIN_MODE == _SLAVE_MODE_ */ +/** @} */ diff --git a/Lib/mc9s12zvl32.c b/Lib/mc9s12zvl32.c new file mode 100644 index 0000000..d507b94 --- /dev/null +++ b/Lib/mc9s12zvl32.c @@ -0,0 +1,314 @@ +/* Based on CPU DB MC9S12ZVL32_48, version 3.00.000 (RegistersPrg V2.33) */ +/* DataSheet : MC9S12ZVLRMV1 Rev. 0.09 December 10, 2012 */ + +#include + +/*lint -save -esym(765, *) */ + + +/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile INT_CFADDRSTR _INT_CFADDR; /* Interrupt Request Configuration Address Register; 0x00000017 */ +volatile INT_CFDATA0STR _INT_CFDATA0; /* Interrupt Request Configuration Data Register 0; 0x00000018 */ +volatile INT_CFDATA1STR _INT_CFDATA1; /* Interrupt Request Configuration Data Register 1; 0x00000019 */ +volatile INT_CFDATA2STR _INT_CFDATA2; /* Interrupt Request Configuration Data Register 2; 0x0000001A */ +volatile INT_CFDATA3STR _INT_CFDATA3; /* Interrupt Request Configuration Data Register 3; 0x0000001B */ +volatile INT_CFDATA4STR _INT_CFDATA4; /* Interrupt Request Configuration Data Register 4; 0x0000001C */ +volatile INT_CFDATA5STR _INT_CFDATA5; /* Interrupt Request Configuration Data Register 5; 0x0000001D */ +volatile INT_CFDATA6STR _INT_CFDATA6; /* Interrupt Request Configuration Data Register 6; 0x0000001E */ +volatile INT_CFDATA7STR _INT_CFDATA7; /* Interrupt Request Configuration Data Register 7; 0x0000001F */ +volatile MODESTR _MODE; /* Mode Register; 0x00000070 */ +volatile MMCPCHSTR _MMCPCH; /* Captured S12ZCPU Program Counter High; 0x00000085 */ +volatile MMCPCMSTR _MMCPCM; /* Captured S12ZCPU Program Counter Middle; 0x00000086 */ +volatile MMCPCLSTR _MMCPCL; /* Captured S12ZCPU Program Counter Low; 0x00000087 */ +volatile DBGC1STR _DBGC1; /* Debug Control Register 1; 0x00000100 */ +volatile DBGC2STR _DBGC2; /* Debug Control Register 2; 0x00000101 */ +volatile DBGSCR1STR _DBGSCR1; /* Debug State Control Register 1; 0x00000107 */ +volatile DBGSCR2STR _DBGSCR2; /* Debug State Control Register 2; 0x00000108 */ +volatile DBGSCR3STR _DBGSCR3; /* Debug State Control Register 3; 0x00000109 */ +volatile DBGEFRSTR _DBGEFR; /* Debug Event Flag Register; 0x0000010A */ +volatile DBGSRSTR _DBGSR; /* Debug Status Register; 0x0000010B */ +volatile DBGACTLSTR _DBGACTL; /* Debug Comparator A Control Register; 0x00000110 */ +volatile DBGAAHSTR _DBGAAH; /* Debug Comparator A Address Register High; 0x00000115 */ +volatile DBGAAMSTR _DBGAAM; /* Debug Comparator A Address Register Middle; 0x00000116 */ +volatile DBGAALSTR _DBGAAL; /* Debug Comparator A Address Register Low; 0x00000117 */ +volatile DBGAD0STR _DBGAD0; /* Debug Comparator A Data Register 0; 0x00000118 */ +volatile DBGAD1STR _DBGAD1; /* Debug Comparator A Data Register 1; 0x00000119 */ +volatile DBGAD2STR _DBGAD2; /* Debug Comparator A Data Register 2; 0x0000011A */ +volatile DBGAD3STR _DBGAD3; /* Debug Comparator A Data Register 3; 0x0000011B */ +volatile DBGADM0STR _DBGADM0; /* Debug Comparator A Data Mask Register 0; 0x0000011C */ +volatile DBGADM1STR _DBGADM1; /* Debug Comparator A Data Mask Register 1; 0x0000011D */ +volatile DBGADM2STR _DBGADM2; /* Debug Comparator A Data Mask Register 2; 0x0000011E */ +volatile DBGADM3STR _DBGADM3; /* Debug Comparator A Data Mask Register 3; 0x0000011F */ +volatile DBGBCTLSTR _DBGBCTL; /* Debug Comparator B Control Register; 0x00000120 */ +volatile DBGBAHSTR _DBGBAH; /* Debug Comparator B Address Register High; 0x00000125 */ +volatile DBGBAMSTR _DBGBAM; /* Debug Comparator B Address Register Middle; 0x00000126 */ +volatile DBGBALSTR _DBGBAL; /* Debug Comparator B Address Register Low; 0x00000127 */ +volatile DBGDCTLSTR _DBGDCTL; /* Debug Comparator D Control Register; 0x00000140 */ +volatile DBGDAHSTR _DBGDAH; /* Debug Comparator D Address Register High; 0x00000145 */ +volatile DBGDAMSTR _DBGDAM; /* Debug Comparator D Address Register Middle; 0x00000146 */ +volatile DBGDALSTR _DBGDAL; /* Debug Comparator D Address Register Low; 0x00000147 */ +volatile MODRR0STR _MODRR0; /* Module Routing Register 0; 0x00000200 */ +volatile MODRR1STR _MODRR1; /* Module Routing Register 1; 0x00000201 */ +volatile MODRR2STR _MODRR2; /* Module Routing Register 2; 0x00000202 */ +volatile MODRR3STR _MODRR3; /* Module Routing Register 3; 0x00000203 */ +volatile MODRR4STR _MODRR4; /* Module Routing Register 4; 0x00000204 */ +volatile ECLKCTLSTR _ECLKCTL; /* ECLK Control Register; 0x00000208 */ +volatile IRQCRSTR _IRQCR; /* Interrupt Control Register; 0x00000209 */ +volatile PTESTR _PTE; /* Port E Data Register; 0x00000260 */ +volatile PTIESTR _PTIE; /* Port E Input Register; 0x00000262 */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000264 */ +volatile PERESTR _PERE; /* Port E Pull Device Enable Register; 0x00000266 */ +volatile PPSESTR _PPSE; /* Port E Polarity Select Register; 0x00000268 */ +volatile PTTSTR _PTT; /* Port T Data Register; 0x000002C0 */ +volatile PTITSTR _PTIT; /* Port T Input Register; 0x000002C1 */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x000002C2 */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x000002C3 */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x000002C4 */ +volatile PTSSTR _PTS; /* Port S Data Register; 0x000002D0 */ +volatile PTISSTR _PTIS; /* Port S Input Register; 0x000002D1 */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x000002D2 */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x000002D3 */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x000002D4 */ +volatile PIESSTR _PIES; /* Port S Interrupt Enable Register; 0x000002D6 */ +volatile PIFSSTR _PIFS; /* Port S Interrupt Flag Register; 0x000002D7 */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x000002DF */ +volatile PTPSTR _PTP; /* Port P Data Register; 0x000002F0 */ +volatile PTIPSTR _PTIP; /* Port P Input Register; 0x000002F1 */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x000002F2 */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x000002F3 */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x000002F4 */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x000002F6 */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x000002F7 */ +volatile OCPEPSTR _OCPEP; /* Port P Over-Current Protection Enable Register; 0x000002F9 */ +volatile OCIEPSTR _OCIEP; /* Port P Over-Current Interrupt Enable Register; 0x000002FA */ +volatile OCIFPSTR _OCIFP; /* Port P Over-Current Interrupt Flag Register; 0x000002FB */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register; 0x000002FD */ +volatile PTJSTR _PTJ; /* Port J Data Register; 0x00000310 */ +volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000311 */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x00000312 */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x00000313 */ +volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x00000314 */ +volatile WOMJSTR _WOMJ; /* Port J Wired-Or Mode Register; 0x0000031F */ +volatile PTILSTR _PTIL; /* Port L Input Register; 0x00000331 */ +volatile PPSLSTR _PPSL; /* Port L Polarity Select Register; 0x00000334 */ +volatile PIELSTR _PIEL; /* Port L Interrupt Enable Register; 0x00000336 */ +volatile PIFLSTR _PIFL; /* Port L Interrupt Flag Register; 0x00000337 */ +volatile DIENLSTR _DIENL; /* Port LDigital Input Enable Register; 0x0000033C */ +volatile PTALSTR _PTAL; /* Port L Analog Access Register; 0x0000033D */ +volatile PIRLSTR _PIRL; /* Port L Input Divider Ratio Selection Register; 0x0000033E */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000380 */ +volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000381 */ +volatile FCCOBIXSTR _FCCOBIX; /* Flash CCOB Index Register; 0x00000382 */ +volatile FPSTATSTR _FPSTAT; /* Flash Protection Status Register; 0x00000383 */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000384 */ +volatile FERCNFGSTR _FERCNFG; /* Flash Error Configuration Register; 0x00000385 */ +volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000386 */ +volatile FERSTATSTR _FERSTAT; /* Flash Error Status Register; 0x00000387 */ +volatile FPROTSTR _FPROT; /* P-Flash Protection Register; 0x00000388 */ +volatile DFPROTSTR _DFPROT; /* D-Flash Protection Register; 0x00000389 */ +volatile FOPTSTR _FOPT; /* Flash Option Register; 0x0000038A */ +volatile ECCSTATSTR _ECCSTAT; /* ECC Status Register; 0x000003C0 */ +volatile ECCIESTR _ECCIE; /* ECC Interrupt Enable Register; 0x000003C1 */ +volatile ECCIFSTR _ECCIF; /* ECC Interrupt Flag Register; 0x000003C2 */ +volatile ECCDPTRHSTR _ECCDPTRH; /* ECC Debug Point Register High; 0x000003C7 */ +volatile ECCDPTRMSTR _ECCDPTRM; /* ECC Debug Point Register Middle; 0x000003C8 */ +volatile ECCDPTRLSTR _ECCDPTRL; /* ECC Debug Point Register Low; 0x000003C9 */ +volatile ECCDESTR _ECCDE; /* ECC Debug ECC; 0x000003CE */ +volatile ECCDCMDSTR _ECCDCMD; /* ECC Debug Comamnd; 0x000003CF */ +volatile TIM1TIOSSTR _TIM1TIOS; /* Timer Input Capture/Output Compare Select; 0x00000400 */ +volatile TIM1CFORCSTR _TIM1CFORC; /* Timer Compare Force Register; 0x00000401 */ +volatile TIM1TSCR1STR _TIM1TSCR1; /* Timer System Control Register1; 0x00000406 */ +volatile TIM1TTOVSTR _TIM1TTOV; /* Timer Toggle On Overflow Register; 0x00000407 */ +volatile TIM1TCTL2STR _TIM1TCTL2; /* Timer Control Register 2; 0x00000409 */ +volatile TIM1TCTL4STR _TIM1TCTL4; /* Timer Control Register 4; 0x0000040B */ +volatile TIM1TIESTR _TIM1TIE; /* Timer Interrupt Enable Register; 0x0000040C */ +volatile TIM1TSCR2STR _TIM1TSCR2; /* Timer System Control Register 2; 0x0000040D */ +volatile TIM1TFLG1STR _TIM1TFLG1; /* Main Timer Interrupt Flag 1; 0x0000040E */ +volatile TIM1TFLG2STR _TIM1TFLG2; /* Main Timer Interrupt Flag 2; 0x0000040F */ +volatile TIM1OCPDSTR _TIM1OCPD; /* Output Compare Pin Disconnect Register; 0x0000042C */ +volatile TIM1PTPSRSTR _TIM1PTPSR; /* Precision Timer Prescaler Select Register; 0x0000042E */ +volatile PWMESTR _PWME; /* PWM Enable Register; 0x00000480 */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x00000481 */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x00000482 */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x00000483 */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x00000484 */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x00000485 */ +volatile PWMCLKABSTR _PWMCLKAB; /* PWM Clock Select Register; 0x00000486 */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x00000488 */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x00000489 */ +volatile TIM0TIOSSTR _TIM0TIOS; /* Timer Input Capture/Output Compare Select; 0x000005C0 */ +volatile TIM0CFORCSTR _TIM0CFORC; /* Timer Compare Force Register; 0x000005C1 */ +volatile TIM0TSCR1STR _TIM0TSCR1; /* Timer System Control Register1; 0x000005C6 */ +volatile TIM0TTOVSTR _TIM0TTOV; /* Timer Toggle On Overflow Register; 0x000005C7 */ +volatile TIM0TCTL1STR _TIM0TCTL1; /* Timer Control Register 1; 0x000005C8 */ +volatile TIM0TCTL2STR _TIM0TCTL2; /* Timer Control Register 2; 0x000005C9 */ +volatile TIM0TCTL3STR _TIM0TCTL3; /* Timer Control Register 3; 0x000005CA */ +volatile TIM0TCTL4STR _TIM0TCTL4; /* Timer Control Register 4; 0x000005CB */ +volatile TIM0TIESTR _TIM0TIE; /* Timer Interrupt Enable Register; 0x000005CC */ +volatile TIM0TSCR2STR _TIM0TSCR2; /* Timer System Control Register 2; 0x000005CD */ +volatile TIM0TFLG1STR _TIM0TFLG1; /* Main Timer Interrupt Flag 1; 0x000005CE */ +volatile TIM0TFLG2STR _TIM0TFLG2; /* Main Timer Interrupt Flag 2; 0x000005CF */ +volatile TIM0OCPDSTR _TIM0OCPD; /* Output Compare Pin Disconnect Register; 0x000005EC */ +volatile TIM0PTPSRSTR _TIM0PTPSR; /* Precision Timer Prescaler Select Register; 0x000005EE */ +volatile ADC0STSSTR _ADC0STS; /* ADC0 Status Register; 0x00000602 */ +volatile ADC0TIMSTR _ADC0TIM; /* ADC0 Timing Register; 0x00000603 */ +volatile ADC0FMTSTR _ADC0FMT; /* ADC0 Format Register; 0x00000604 */ +volatile ADC0FLWCTLSTR _ADC0FLWCTL; /* ADC0 Conversion Flow Control Register; 0x00000605 */ +volatile ADC0EIESTR _ADC0EIE; /* ADC0 Error Interrupt Enable Register; 0x00000606 */ +volatile ADC0IESTR _ADC0IE; /* ADC0 Interrupt Enable Register; 0x00000607 */ +volatile ADC0EIFSTR _ADC0EIF; /* ADC0 Error Interrupt Flag Register; 0x00000608 */ +volatile ADC0IFSTR _ADC0IF; /* ADC0 Interrupt Flag Register; 0x00000609 */ +volatile ADC0EOLRISTR _ADC0EOLRI; /* ADC0 End Of List Result Information Register; 0x00000610 */ +volatile ADC0CIDXSTR _ADC0CIDX; /* ADC0 Command Index Register; 0x0000061C */ +volatile ADC0CBP_0STR _ADC0CBP_0; /* ADC0 Command Base Pointer Register 0; 0x0000061D */ +volatile ADC0CBP_1STR _ADC0CBP_1; /* ADC0 Command Base Pointer Register 1; 0x0000061E */ +volatile ADC0CBP_2STR _ADC0CBP_2; /* ADC0 Command Base Pointer Register 2; 0x0000061F */ +volatile ADC0RIDXSTR _ADC0RIDX; /* ADC0 Result Index Register; 0x00000620 */ +volatile ADC0RBP_0STR _ADC0RBP_0; /* ADC0 Result Base Pointer Register 0; 0x00000621 */ +volatile ADC0RBP_1STR _ADC0RBP_1; /* ADC0 Result Base Pointer Register 1; 0x00000622 */ +volatile ADC0RBP_2STR _ADC0RBP_2; /* ADC0 Result Base Pointer Register 2; 0x00000623 */ +volatile ADC0CROFF0STR _ADC0CROFF0; /* ADC0 Command and Result Offset Register 0; 0x00000624 */ +volatile ADC0CROFF1STR _ADC0CROFF1; /* ADC0 Command and Result Offset Register 1; 0x00000625 */ +volatile CPMURFLGSTR _CPMURFLG; /* CPMU Reset Flags Register; 0x000006C3 */ +volatile CPMUSYNRSTR _CPMUSYNR; /* CPMU Synthesizer Register; 0x000006C4 */ +volatile CPMUREFDIVSTR _CPMUREFDIV; /* CPMU Reference Divider Register; 0x000006C5 */ +volatile CPMUPOSTDIVSTR _CPMUPOSTDIV; /* CPMU Post Divider Register; 0x000006C6 */ +volatile CPMUIFLGSTR _CPMUIFLG; /* CPMU Interrupt Flags Register; 0x000006C7 */ +volatile CPMUINTSTR _CPMUINT; /* CPMU Interrupt Enable Register; 0x000006C8 */ +volatile CPMUCLKSSTR _CPMUCLKS; /* CPMU Clock Select Register; 0x000006C9 */ +volatile CPMUPLLSTR _CPMUPLL; /* CPMU PLL Control Register; 0x000006CA */ +volatile CPMURTISTR _CPMURTI; /* CPMU RTI Control Register; 0x000006CB */ +volatile CPMUCOPSTR _CPMUCOP; /* CPMU COP Control Register; 0x000006CC */ +volatile CPMUARMCOPSTR _CPMUARMCOP; /* CPMU COP Timer Arm/Reset Register; 0x000006CF */ +volatile CPMUHTCTLSTR _CPMUHTCTL; /* High Temperature Control Register; 0x000006D0 */ +volatile CPMULVCTLSTR _CPMULVCTL; /* Low Voltage Control Register; 0x000006D1 */ +volatile CPMUAPICTLSTR _CPMUAPICTL; /* Autonomous Periodical Interrupt Control Register; 0x000006D2 */ +volatile CPMUACLKTRSTR _CPMUACLKTR; /* Autonomous Clock Trimming Register; 0x000006D3 */ +volatile CPMUHTTRSTR _CPMUHTTR; /* High Temperature Trimming Register; 0x000006D7 */ +volatile CPMUOSCSTR _CPMUOSC; /* CPMU Oscillator Register; 0x000006DA */ +volatile CPMUPROTSTR _CPMUPROT; /* CPMUV1 Protection Register; 0x000006DB */ +volatile CPMUVREGCTLSTR _CPMUVREGCTL; /* Voltage Regulator Control Register; 0x000006DD */ +volatile CPMUOSC2STR _CPMUOSC2; /* CPMU Oscillator Register 2; 0x000006DE */ +volatile BATESTR _BATE; /* BATS Module Enable Register; 0x000006F0 */ +volatile BATSRSTR _BATSR; /* BATS Module Status Register; 0x000006F1 */ +volatile BATIESTR _BATIE; /* BATS Interrupt Enable Register; 0x000006F2 */ +volatile BATIFSTR _BATIF; /* BATS Interrupt Flag Register; 0x000006F3 */ +volatile SCI0ACR2STR _SCI0ACR2; /* SCI 0 Alternative Control Register 2; 0x00000702 */ +volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x00000703 */ +volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x00000704 */ +volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x00000705 */ +volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x00000706 */ +volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x00000707 */ +volatile SCI1ACR2STR _SCI1ACR2; /* SCI 1 Alternative Control Register 2; 0x00000712 */ +volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x00000713 */ +volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x00000714 */ +volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x00000715 */ +volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x00000716 */ +volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x00000717 */ +volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register 1; 0x00000780 */ +volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x00000781 */ +volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x00000782 */ +volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x00000783 */ +volatile IIC0IBADSTR _IIC0IBAD; /* IIC Address Register; 0x000007C0 */ +volatile IIC0IBFDSTR _IIC0IBFD; /* IIC Frequency Divider Register; 0x000007C1 */ +volatile IIC0IBCRSTR _IIC0IBCR; /* IIC Control Register; 0x000007C2 */ +volatile IIC0IBSRSTR _IIC0IBSR; /* IIC Status Register; 0x000007C3 */ +volatile IIC0IBDRSTR _IIC0IBDR; /* IIC Data I/O Register; 0x000007C4 */ +volatile IIC0IBCR2STR _IIC0IBCR2; /* IIC Control Register 2; 0x000007C5 */ +volatile LP0DRSTR _LP0DR; /* Port LP Data Register; 0x00000980 */ +volatile LP0CRSTR _LP0CR; /* LIN Control Register; 0x00000981 */ +volatile LP0SLRMSTR _LP0SLRM; /* LIN Slew Rate Register; 0x00000983 */ +volatile LP0SRSTR _LP0SR; /* LIN Status Register; 0x00000985 */ +volatile LP0IESTR _LP0IE; /* LIN Interrupt Enable Register; 0x00000986 */ +volatile LP0IFSTR _LP0IF; /* LIN Interrupt Flags Register; 0x00000987 */ +/* NVFPROT - macro for reading non volatile register Non Volatile P-Flash Protection Register; 0x00FFFE0C */ +/* Tip for register initialization in the user code: const byte NVFPROT_INIT @0x00FFFE0C = ; */ +/* NVDFPROT - macro for reading non volatile register Non Volatile D-Flash Protection Register; 0x00FFFE0D */ +/* Tip for register initialization in the user code: const byte NVDFPROT_INIT @0x00FFFE0D = ; */ +/* NVFOPT - macro for reading non volatile register Non Volatile Flash Option Register; 0x00FFFE0E */ +/* Tip for register initialization in the user code: const byte NVFOPT_INIT @0x00FFFE0E = ; */ +/* NVFSEC - macro for reading non volatile register Non Volatile Flash Security Register; 0x00FFFE0F */ +/* Tip for register initialization in the user code: const byte NVFSEC_INIT @0x00FFFE0F = ; */ + + +/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile IVBRSTR _IVBR; /* Interrupt Vector Base Register; 0x00000010 */ +volatile MMCECSTR _MMCEC; /* Error code register; 0x00000080 */ +volatile MMCCCRSTR _MMCCCR; /* Captured S12ZCPU Condition Code Register Low; 0x00000082 */ +volatile PTADSTR _PTAD; /* Port AD Data Register; 0x00000280 */ +volatile PTIADSTR _PTIAD; /* Port AD Input Register; 0x00000282 */ +volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register; 0x00000284 */ +volatile PERADSTR _PERAD; /* Port AD Pull Up Enable Register; 0x00000286 */ +volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register; 0x00000288 */ +volatile PIEADSTR _PIEAD; /* Port AD Interrupt Enable Register; 0x0000028C */ +volatile PIFADSTR _PIFAD; /* Port AD Interrupt Flag Register; 0x0000028E */ +volatile DIENADSTR _DIENAD; /* Digital Input Enable Register; 0x00000298 */ +volatile FCCOB0STR _FCCOB0; /* Flash Common Command Object Register; 0x0000038C */ +volatile FCCOB1STR _FCCOB1; /* Flash Common Command Object Register; 0x0000038E */ +volatile FCCOB2STR _FCCOB2; /* Flash Common Command Object Register; 0x00000390 */ +volatile FCCOB3STR _FCCOB3; /* Flash Common Command Object Register; 0x00000392 */ +volatile FCCOB4STR _FCCOB4; /* Flash Common Command Object Register; 0x00000394 */ +volatile FCCOB5STR _FCCOB5; /* Flash Common Command Object Register; 0x00000396 */ +volatile ECCDDSTR _ECCDD; /* ECC Debug Data; 0x000003CC */ +volatile TIM1TCNTSTR _TIM1TCNT; /* Timer Count Register; 0x00000404 */ +volatile TIM1TC0STR _TIM1TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000410 */ +volatile TIM1TC1STR _TIM1TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000412 */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x0000048C */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x0000048E */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x00000490 */ +volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x00000492 */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x00000494 */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x00000496 */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x00000498 */ +volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x0000049A */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x0000049C */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x0000049E */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000004A0 */ +volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000004A2 */ +volatile TIM0TCNTSTR _TIM0TCNT; /* Timer Count Register; 0x000005C4 */ +volatile TIM0TC0STR _TIM0TC0; /* Timer Input Capture/Output Compare Register 0; 0x000005D0 */ +volatile TIM0TC1STR _TIM0TC1; /* Timer Input Capture/Output Compare Register 1; 0x000005D2 */ +volatile TIM0TC2STR _TIM0TC2; /* Timer Input Capture/Output Compare Register 2; 0x000005D4 */ +volatile TIM0TC3STR _TIM0TC3; /* Timer Input Capture/Output Compare Register 3; 0x000005D6 */ +volatile TIM0TC4STR _TIM0TC4; /* Timer Input Capture/Output Compare Register 4; 0x000005D8 */ +volatile TIM0TC5STR _TIM0TC5; /* Timer Input Capture/Output Compare Register 5; 0x000005DA */ +volatile ADC0CTLSTR _ADC0CTL; /* ADC0 Control Register; 0x00000600 */ +volatile ADC0CONIESTR _ADC0CONIE; /* ADC0 Conversion Interrupt Enable Register; 0x0000060A */ +volatile ADC0CONIFSTR _ADC0CONIF; /* ADC0 Conversion Interrupt Flag Register; 0x0000060C */ +volatile ADC0IMDRISTR _ADC0IMDRI; /* ADC0 Intermediate Result Information Register; 0x0000060E */ +volatile CPMUAPIRSTR _CPMUAPIR; /* Autonomous Periodical Interrupt Rate Register; 0x000006D4 */ +volatile CPMUIRCTRIMSTR _CPMUIRCTRIM; /* CPMU IRC1M Trim Registers; 0x000006D8 */ +volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x00000700 */ +volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x00000710 */ +volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x00000784 */ +/* BAKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x00FFFE00 */ +/* Tip for register initialization in the user code: const byte BAKEY0_INIT @0x00FFFE00 = ; */ +/* BAKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x00FFFE02 */ +/* Tip for register initialization in the user code: const byte BAKEY1_INIT @0x00FFFE02 = ; */ +/* BAKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x00FFFE04 */ +/* Tip for register initialization in the user code: const byte BAKEY2_INIT @0x00FFFE04 = ; */ +/* BAKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x00FFFE06 */ +/* Tip for register initialization in the user code: const byte BAKEY3_INIT @0x00FFFE06 = ; */ +/* PROTKEY - macro for reading non volatile register Non Volatile Protection Override Comparison Key; 0x00FFFE08 */ +/* Tip for register initialization in the user code: const byte PROTKEY_INIT @0x00FFFE08 = ; */ + + +/* * * * * 32-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile PARTIDSTR _PARTID; /* Part ID Register; 0x00000000 */ +volatile ADC0CMDSTR _ADC0CMD; /* ADC0 Command Register; 0x00000614 */ + + +/* * * * * 24-BIT ADDRESS REGISTERS * * * * * * * * * * * * * * * * * * * * * * */ +volatile void* volatile MMCPC; /* Captured S12ZCPU Program Counter Low; 0x00000087 */ +volatile void* volatile DBGAA; /* Debug Comparator A Address Register Low; 0x00000117 */ +volatile void* volatile DBGBA; /* Debug Comparator B Address Register Low; 0x00000127 */ +volatile void* volatile DBGDA; /* Debug Comparator D Address Register Low; 0x00000147 */ +volatile void* volatile ECCDPTR; /* ECC Debug Point Register Low; 0x000003C9 */ +volatile void* volatile ADC0CBP; /* ADC0 Command Base Pointer Register 0; 0x000003C9 */ +volatile void* volatile ADC0RBP; /* ADC0 Result Base Pointer Register 0; 0x000003C9 */ + + + +/*lint -restore */ + +/* EOF */ diff --git a/Project_Headers/derivative.h b/Project_Headers/derivative.h new file mode 100644 index 0000000..c8ec597 --- /dev/null +++ b/Project_Headers/derivative.h @@ -0,0 +1,155 @@ +#ifndef _DERIVATIVE__H +#define _DERIVATIVE__H + +#include + +// +#define V_12_Ctrl PTP_PTP6 +#define O_STAT_DIS PTP_PTP5 +#define O_STATUS PTJ_PTJ0 + +// +#define Button_PHONE PTADL_PTADL7 +#define Button_UP PTADH_PTADH0 +#define Button_OK PTADH_PTADH1 +#define Button_DOWN PTP_PTP1 +#define Button_SIRI PTJ_PTJ1 +#define Signal_HORN PTT_PTT7 +#define Button_SEEK_Add PTADL_PTADL3 +#define Button_MUTE PTADL_PTADL4 +#define Button_V_Reduce PTADL_PTADL6 +#define Button_SEEK_Reduce PTADL_PTADL5 +#define Button_V_Add PTADL_PTADL2 + +/* +// +#define O_LED_PWM PWMDTY7 +*/ + +extern unsigned char FLAG_GO_TO_Sleep; +extern unsigned char M_ASK_S_Sleep; +extern unsigned char NO_DATA_Sleep;//ʱ˯ + +/********˴ΪPE_Types*************/ +#define setRegBit(reg, bit) (reg |= reg##_##bit##_##MASK) +#define clrRegBit(reg, bit) (reg &= ~reg##_##bit##_##MASK) +#define getRegBit(reg, bit) (reg & reg##_##bit##_##MASK) +#define setReg(reg, val) (reg = (word)(val)) +#define getReg(reg) (reg) +#define setRegBits(reg, mask) (reg |= (word)(mask)) +#define getRegBits(reg, mask) (reg & (word)(mask)) +#define clrRegBits(reg, mask) (reg &= (word)(~(mask))) +#define setRegBitGroup(reg, bits, val) (reg = (word)((reg & ~reg##_##bits##_##MASK) | ((val) << reg##_##bits##_##BITNUM))) +#define getRegBitGroup(reg, bits) ((reg & reg##_##bits##_##MASK) >> reg##_##bits##_##BITNUM) +#define setRegMask(reg, maskAnd, maskOr) (reg = (word)((getReg(reg) & ~(maskAnd)) | (maskOr))) +#define setRegBitVal(reg, bit, val) ((val) == 0 ? (reg &= ~reg##_##bit##_##MASK) : (reg |= reg##_##bit##_##MASK)) +#define changeRegBits(reg, mask) (reg ^= (mask)) +#define changeRegBit(reg, bit) (reg ^= reg##_##bit##_##MASK) + +/******************************************************************/ +/* Uniform multiplatform peripheral access macros - 16 bit access */ +/******************************************************************/ +#define setReg16Bit(RegName, BitName) (RegName |= RegName##_##BitName##_##MASK) +#define clrReg16Bit(RegName, BitName) (RegName &= ~(word)RegName##_##BitName##_##MASK) +#define invertReg16Bit(RegName, BitName) (RegName ^= RegName##_##BitName##_##MASK) +#define testReg16Bit(RegName, BitName) (RegName & RegName##_##BitName##_##MASK) + +/* Whole peripheral register access macros */ +#define setReg16(RegName, val) (RegName = (word)(val)) +#define getReg16(RegName) (RegName) + +/* Bits peripheral register access macros */ +#define testReg16Bits(RegName, GetMask) (RegName & (GetMask)) +#define clrReg16Bits(RegName, ClrMask) (RegName &= (word)(~(word)(ClrMask))) +#define setReg16Bits(RegName, SetMask) (RegName |= (word)(SetMask)) +#define invertReg16Bits(RegName, InvMask) (RegName ^= (word)(InvMask)) +#define clrSetReg16Bits(RegName, ClrMask, SetMask) (RegName = (RegName & (~(word)(ClrMask))) | (word)(SetMask)) +#define seqClrSetReg16Bits(RegName, BitsMask, BitsVal) ((RegName &= ~(~(word)(BitsVal) & (word)(BitsMask))),\ + (RegName |= (word)(BitsVal) & (word)(BitsMask)) ) +#define seqSetClrReg16Bits(RegName, BitsMask, BitsVal) ((RegName |= (word)(BitsVal) & (word)(BitsMask)),\ + (RegName &= ~(~(word)(BitsVal) & (word)(BitsMask))) ) +#define seqResetSetReg16Bits(RegName, BitsMask, BitsVal) ((RegName &= ~(word)(BitsMask)),\ + (RegName |= (word)(BitsVal) & (word)(BitsMask)) ) +#define clrReg16BitsByOne(RegName, ClrMask, BitsMask) (RegName &= (word)(ClrMask) & (word)(BitsMask)) + +/* Bit group peripheral register access macros */ +#define testReg16BitGroup(RegName, GroupName) (RegName & RegName##_##GroupName##_##MASK) +#define getReg16BitGroupVal(RegName, GroupName) ((RegName & RegName##_##GroupName##_##MASK) >> RegName##_##GroupName##_##BITNUM) +#define setReg16BitGroupVal(RegName, GroupName, GroupVal) (RegName = (RegName & ~(word)RegName##_##GroupName##_##MASK) | (((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM)) +#define seqClrSetReg16BitGroupVal(RegName,GroupName,GroupVal) ((RegName &= ~(~(((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK)),\ + (RegName |= (((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK) ) +#define seqSetClrReg16BitGroupVal(RegName,GroupName,GroupVal) ((RegName |= (((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK),\ + (RegName &= ~(~(((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK)) ) +#define seqResetSetReg16BitGroupVal(RegName,GroupName,GroupVal) ((RegName &= ~(word)RegName##_##GroupName##_##MASK),\ + (RegName |= (((word)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK) ) + +/*****************************************************************/ +/* Uniform multiplatform peripheral access macros - 8 bit access */ +/*****************************************************************/ +#define setReg8Bit(RegName, BitName) (RegName |= RegName##_##BitName##_##MASK) +#define clrReg8Bit(RegName, BitName) (RegName &= (byte)~(byte)RegName##_##BitName##_##MASK) +#define invertReg8Bit(RegName, BitName) (RegName ^= RegName##_##BitName##_##MASK) +#define testReg8Bit(RegName, BitName) (RegName & RegName##_##BitName##_##MASK) + +/* Whole peripheral register access macros */ +#define setReg8(RegName, val) (RegName = (byte)(val)) +#define getReg8(RegName) (RegName) + +/* Bits peripheral register access macros */ +#define testReg8Bits(RegName, GetMask) (RegName & (GetMask)) +#define clrReg8Bits(RegName, ClrMask) (RegName &= (byte)(~(byte)(ClrMask))) +#define setReg8Bits(RegName, SetMask) (RegName |= (byte)(SetMask)) +#define invertReg8Bits(RegName, InvMask) (RegName ^= (byte)(InvMask)) +#define clrSetReg8Bits(RegName, ClrMask, SetMask) (RegName = (RegName & ((byte)(~(byte)(ClrMask)))) | (byte)(SetMask)) +#define seqClrSetReg8Bits(RegName, BitsMask, BitsVal) ((RegName &= (byte)~((byte)~((byte)(BitsVal)) & ((byte)(BitsMask)))),\ + (RegName |= ((byte)(BitsVal)) & ((byte)(BitsMask))) ) +#define seqSetClrReg8Bits(RegName, BitsMask, BitsVal) ((RegName |= (byte)(BitsVal) & (byte)(BitsMask)),\ + (RegName &= (byte)~((byte)~((byte)(BitsVal)) & (byte)(BitsMask))) ) +#define seqResetSetReg8Bits(RegName, BitsMask, BitsVal) ((RegName &= (byte)~((byte)(BitsMask))),\ + (RegName |= (byte)(BitsVal) & (byte)(BitsMask)) ) +#define clrReg8BitsByOne(RegName, ClrMask, BitsMask) (RegName &= (byte)(ClrMask) & (byte)(BitsMask)) + +/* Bit group peripheral register access macros */ +#define testReg8BitGroup(RegName, GroupName) (RegName & RegName##_##GroupName##_##MASK) +#define getReg8BitGroupVal(RegName, GroupName) ((RegName & RegName##_##GroupName##_##MASK) >> RegName##_##GroupName##_##BITNUM) +#define setReg8BitGroupVal(RegName, GroupName, GroupVal) (RegName = (RegName & (byte)~(byte)RegName##_##GroupName##_##MASK) | (byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM)) +#define seqClrSetReg8BitGroupVal(RegName,GroupName,GroupVal) ((RegName &= (byte)~((byte)~(byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & (byte)RegName##_##GroupName##_##MASK)),\ + (RegName |= (byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & (byte)RegName##_##GroupName##_##MASK) ) +#define seqSetClrReg8BitGroupVal(RegName,GroupName,GroupVal) ((RegName |= (byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & (byte)RegName##_##GroupName##_##MASK),\ + (RegName &= (byte)~((byte)~(byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & (byte)RegName##_##GroupName##_##MASK)) ) +#define seqResetSetReg8BitGroupVal(RegName,GroupName,GroupVal) ((RegName &= (byte)~(byte)RegName##_##GroupName##_##MASK),\ + (RegName |= (byte)(((byte)(GroupVal)) << RegName##_##GroupName##_##BITNUM) & RegName##_##GroupName##_##MASK) ) + + +/******˴ΪPE_Errorĺ궨********/ +#define ERR_OK 0U /* OK */ +#define ERR_SPEED 1U /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2U /* Parameter out of range. */ +#define ERR_VALUE 3U /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4U /* Timer overflow. */ +#define ERR_MATH 5U /* Overflow during evaluation. */ +#define ERR_ENABLED 6U /* Device is enabled. */ +#define ERR_DISABLED 7U /* Device is disabled. */ +#define ERR_BUSY 8U /* Device is busy. */ +#define ERR_NOTAVAIL 9U /* Requested value or method not available. */ +#define ERR_RXEMPTY 10U /* No data in receiver. */ +#define ERR_TXFULL 11U /* Transmitter is full. */ +#define ERR_BUSOFF 12U /* Bus not available. */ +#define ERR_OVERRUN 13U /* Overrun error is detected. */ +#define ERR_FRAMING 14U /* Framing error is detected. */ +#define ERR_PARITY 15U /* Parity error is detected. */ +#define ERR_NOISE 16U /* Noise error is detected. */ +#define ERR_IDLE 17U /* Idle error is detected. */ +#define ERR_FAULT 18U /* Fault error is detected. */ +#define ERR_BREAK 19U /* Break char is received during communication. */ +#define ERR_CRC 20U /* CRC error is detected. */ +#define ERR_ARBITR 21U /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22U /* Protection error is detected. */ +#define ERR_UNDERFLOW 23U /* Underflow error is detected. */ +#define ERR_UNDERRUN 24U /* Underrun error is detected. */ +#define ERR_COMMON 25U /* Common error of a device. */ +#define ERR_LINSYNC 26U /* LIN synchronization error is detected. */ +#define ERR_FAILED 27U /* Requested functionality or process failed. */ +#define ERR_QFULL 28U /* Queue is full. */ + +#endif diff --git a/Project_Headers/diagnostic_service_slave.h b/Project_Headers/diagnostic_service_slave.h new file mode 100644 index 0000000..71d7dd5 --- /dev/null +++ b/Project_Headers/diagnostic_service_slave.h @@ -0,0 +1,24 @@ +#ifndef _DIAGNOSTIC_SERVICE_SLAVE_H_ +#define _DIAGNOSTIC_SERVICE_SLAVE_H_ + +#include "lin_commontl_api.h" +#include "lin.h" +#include "lin_lin21tl_api.h" +/*------------------------------------------*/ +#define SERIAL_NUBER_INT 0x00 +#define IO_CONTROL_STATUS_INT 0x00 +#define SESSION_CONTROL_P3 0x01F4 +#define SESSION_CONTROL_P3Ex 0x09C4 +#define DTCSTATUSBTYE_INT 0x00 +#define DTCFORMATIDENTIFER_INT 0x01 +#define COUNTDTC_INT 0x00 +/*------------------------------------------*/ +/* diagnostic services class II */ +void diagsrv_read_data_by_identifier(void); +void diagsrv_write_data_by_identifier(void); +void diagsrv_session_control(void); +void diagsrv_io_control_by_identifier(void); +void diagsrv_fault_memory_read(void); +void diagsrv_fault_memory_clear(void); +void slave_task(void); +#endif /* End _DIAGNOSTIC_SERVICE_SLAVE_H_ */ \ No newline at end of file diff --git a/Project_Headers/mc9s12zvl32.h b/Project_Headers/mc9s12zvl32.h new file mode 100644 index 0000000..e1f7557 --- /dev/null +++ b/Project_Headers/mc9s12zvl32.h @@ -0,0 +1,11137 @@ +/* Based on CPU DB MC9S12ZVL32_48, version 3.00.000 (RegistersPrg V2.33) */ +/* +** ################################################################### +** Filename : mc9s12zvl32.h +** Processor : MC9S12ZVL32MLF +** FileFormat: V2.33 +** DataSheet : MC9S12ZVLRMV1 Rev. 0.09 December 10, 2012 +** Compiler : CodeWarrior compiler +** Date/Time : 2/28/2013, 9:00 AM +** Abstract : +** This header implements the mapping of I/O devices. +** +** Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http : www.freescale.com +** mail : support@freescale.com +** +** CPU Registers Revisions: +** - 07.02.2012, V0.09: +** - New features : SCI V6, ADC10B_LBA_V1, S12LINPHYV2 +** +** File-Format-Revisions: +** - none +** +** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific +** derivative device. To avoid extra current drain from floating input pins, the users reset +** initialization routine in the application program must either enable on-chip pull-up devices +** or change the direction of unconnected pins to outputs so the pins do not float. +** ################################################################### +*/ + +#ifndef _MC9S12ZVL32_H +#define _MC9S12ZVL32_H + +/*lint -save -e950 -esym(960,18.4) -e46 -esym(961,19.7) Disable MISRA rule (1.1,18.4,6.4,19.7) checking. */ +/* Types definition */ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + + +#pragma bfield_gap_limit -1 /*this guarantee correct bitfield positions*/ + +/**************** interrupt vector numbers ****************/ +#define VectorNumber_VReserved123 123U +#define VectorNumber_VReserved122 122U +#define VectorNumber_VReserved121 121U +#define VectorNumber_VReserved120 120U +#define VectorNumber_VReserved119 119U +#define VectorNumber_VReserved118 118U +#define VectorNumber_VReserved117 117U +#define VectorNumber_VReserved116 116U +#define VectorNumber_VReserved115 115U +#define VectorNumber_VReserved114 114U +#define VectorNumber_VReserved113 113U +#define VectorNumber_VReserved112 112U +#define VectorNumber_VReserved111 111U +#define VectorNumber_VReserved110 110U +#define VectorNumber_VReserved109 109U +#define VectorNumber_VReserved108 108U +#define VectorNumber_VReserved107 107U +#define VectorNumber_VReserved106 106U +#define VectorNumber_VReserved105 105U +#define VectorNumber_VReserved104 104U +#define VectorNumber_Viic 103U +#define VectorNumber_VReserved102 102U +#define VectorNumber_VReserved101 101U +#define VectorNumber_VReserved100 100U +#define VectorNumber_VReserved99 99U +#define VectorNumber_VReserved98 98U +#define VectorNumber_VReserved97 97U +#define VectorNumber_VReserved96 96U +#define VectorNumber_VReserved95 95U +#define VectorNumber_VReserved94 94U +#define VectorNumber_VReserved93 93U +#define VectorNumber_Vtim1ovf 92U +#define VectorNumber_VReserved91 91U +#define VectorNumber_VReserved90 90U +#define VectorNumber_VReserved89 89U +#define VectorNumber_VReserved88 88U +#define VectorNumber_VReserved87 87U +#define VectorNumber_VReserved86 86U +#define VectorNumber_Vtim1ch1 85U +#define VectorNumber_Vtim1ch0 84U +#define VectorNumber_VReserved83 83U +#define VectorNumber_VReserved82 82U +#define VectorNumber_VReserved81 81U +#define VectorNumber_VReserved80 80U +#define VectorNumber_Vportl 79U +#define VectorNumber_VReserved78 78U +#define VectorNumber_VReserved77 77U +#define VectorNumber_VReserved76 76U +#define VectorNumber_VReserved75 75U +#define VectorNumber_VReserved74 74U +#define VectorNumber_VReserved73 73U +#define VectorNumber_VReserved72 72U +#define VectorNumber_VReserved71 71U +#define VectorNumber_VReserved70 70U +#define VectorNumber_VReserved69 69U +#define VectorNumber_VReserved68 68U +#define VectorNumber_VReserved67 67U +#define VectorNumber_Vportad 66U +#define VectorNumber_VReserved65 65U +#define VectorNumber_Vhti 64U +#define VectorNumber_Vapi 63U +#define VectorNumber_Vlvi 62U +#define VectorNumber_Vevddx 61U +#define VectorNumber_Vportp 60U +#define VectorNumber_VReserved59 59U +#define VectorNumber_VReserved58 58U +#define VectorNumber_VReserved57 57U +#define VectorNumber_VReserved56 56U +#define VectorNumber_VReserved55 55U +#define VectorNumber_Vports 54U +#define VectorNumber_VReserved53 53U +#define VectorNumber_VReserved52 52U +#define VectorNumber_VReserved51 51U +#define VectorNumber_VReserved50 50U +#define VectorNumber_VReserved49 49U +#define VectorNumber_VReserved48 48U +#define VectorNumber_Vbats 47U +#define VectorNumber_Vlinphy0 46U +#define VectorNumber_VReserved45 45U +#define VectorNumber_VReserved44 44U +#define VectorNumber_VReserved43 43U +#define VectorNumber_VReserved42 42U +#define VectorNumber_VReserved41 41U +#define VectorNumber_VReserved40 40U +#define VectorNumber_Vflash 39U +#define VectorNumber_Vflasherr 38U +#define VectorNumber_VReserved37 37U +#define VectorNumber_VReserved36 36U +#define VectorNumber_VRAM_err 35U +#define VectorNumber_VReserved34 34U +#define VectorNumber_VReserved33 33U +#define VectorNumber_Vcpmuplllck 32U +#define VectorNumber_Vcpmuosc 31U +#define VectorNumber_Vadc0conv_compl 30U +#define VectorNumber_Vadc0conv_seq_abrt 29U +#define VectorNumber_Vadc0err 28U +#define VectorNumber_VReserved27 27U +#define VectorNumber_VReserved26 26U +#define VectorNumber_Vsci1 25U +#define VectorNumber_Vsci0 24U +#define VectorNumber_Vspi0 23U +#define VectorNumber_VReserved22 22U +#define VectorNumber_VReserved21 21U +#define VectorNumber_Vtim0ovf 20U +#define VectorNumber_VReserved19 19U +#define VectorNumber_VReserved18 18U +#define VectorNumber_Vtim0ch5 17U +#define VectorNumber_Vtim0ch4 16U +#define VectorNumber_Vtim0ch3 15U +#define VectorNumber_Vtim0ch2 14U +#define VectorNumber_Vtim0ch1 13U +#define VectorNumber_Vtim0ch0 12U +#define VectorNumber_Vrti 11U +#define VectorNumber_Virq 10U +#define VectorNumber_Vxirq 9U +#define VectorNumber_Vsi 8U +#define VectorNumber_VReserved7 7U +#define VectorNumber_VReserved6 6U +#define VectorNumber_Vme 5U +#define VectorNumber_Vsys 4U +#define VectorNumber_Vswi 3U +#define VectorNumber_Vtrap 2U +#define VectorNumber_Vspare 1U +#define VectorNumber_Vreset 0U + +/**************** interrupt vector table ****************/ +#define VReserved123 0x00FFFE10UL +#define VReserved122 0x00FFFE14UL +#define VReserved121 0x00FFFE18UL +#define VReserved120 0x00FFFE1CUL +#define VReserved119 0x00FFFE20UL +#define VReserved118 0x00FFFE24UL +#define VReserved117 0x00FFFE28UL +#define VReserved116 0x00FFFE2CUL +#define VReserved115 0x00FFFE30UL +#define VReserved114 0x00FFFE34UL +#define VReserved113 0x00FFFE38UL +#define VReserved112 0x00FFFE3CUL +#define VReserved111 0x00FFFE40UL +#define VReserved110 0x00FFFE44UL +#define VReserved109 0x00FFFE48UL +#define VReserved108 0x00FFFE4CUL +#define VReserved107 0x00FFFE50UL +#define VReserved106 0x00FFFE54UL +#define VReserved105 0x00FFFE58UL +#define VReserved104 0x00FFFE5CUL +#define Viic 0x00FFFE60UL +#define VReserved102 0x00FFFE64UL +#define VReserved101 0x00FFFE68UL +#define VReserved100 0x00FFFE6CUL +#define VReserved99 0x00FFFE70UL +#define VReserved98 0x00FFFE74UL +#define VReserved97 0x00FFFE78UL +#define VReserved96 0x00FFFE7CUL +#define VReserved95 0x00FFFE80UL +#define VReserved94 0x00FFFE84UL +#define VReserved93 0x00FFFE88UL +#define Vtim1ovf 0x00FFFE8CUL +#define VReserved91 0x00FFFE90UL +#define VReserved90 0x00FFFE94UL +#define VReserved89 0x00FFFE98UL +#define VReserved88 0x00FFFE9CUL +#define VReserved87 0x00FFFEA0UL +#define VReserved86 0x00FFFEA4UL +#define Vtim1ch1 0x00FFFEA8UL +#define Vtim1ch0 0x00FFFEACUL +#define VReserved83 0x00FFFEB0UL +#define VReserved82 0x00FFFEB4UL +#define VReserved81 0x00FFFEB8UL +#define VReserved80 0x00FFFEBCUL +#define Vportl 0x00FFFEC0UL +#define VReserved78 0x00FFFEC4UL +#define VReserved77 0x00FFFEC8UL +#define VReserved76 0x00FFFECCUL +#define VReserved75 0x00FFFED0UL +#define VReserved74 0x00FFFED4UL +#define VReserved73 0x00FFFED8UL +#define VReserved72 0x00FFFEDCUL +#define VReserved71 0x00FFFEE0UL +#define VReserved70 0x00FFFEE4UL +#define VReserved69 0x00FFFEE8UL +#define VReserved68 0x00FFFEECUL +#define VReserved67 0x00FFFEF0UL +#define Vportad 0x00FFFEF4UL +#define VReserved65 0x00FFFEF8UL +#define Vhti 0x00FFFEFCUL +#define Vapi 0x00FFFF00UL +#define Vlvi 0x00FFFF04UL +#define Vevddx 0x00FFFF08UL +#define Vportp 0x00FFFF0CUL +#define VReserved59 0x00FFFF10UL +#define VReserved58 0x00FFFF14UL +#define VReserved57 0x00FFFF18UL +#define VReserved56 0x00FFFF1CUL +#define VReserved55 0x00FFFF20UL +#define Vports 0x00FFFF24UL +#define VReserved53 0x00FFFF28UL +#define VReserved52 0x00FFFF2CUL +#define VReserved51 0x00FFFF30UL +#define VReserved50 0x00FFFF34UL +#define VReserved49 0x00FFFF38UL +#define VReserved48 0x00FFFF3CUL +#define Vbats 0x00FFFF40UL +#define Vlinphy0 0x00FFFF44UL +#define VReserved45 0x00FFFF48UL +#define VReserved44 0x00FFFF4CUL +#define VReserved43 0x00FFFF50UL +#define VReserved42 0x00FFFF54UL +#define VReserved41 0x00FFFF58UL +#define VReserved40 0x00FFFF5CUL +#define Vflash 0x00FFFF60UL +#define Vflasherr 0x00FFFF64UL +#define VReserved37 0x00FFFF68UL +#define VReserved36 0x00FFFF6CUL +#define VRAM_err 0x00FFFF70UL +#define VReserved34 0x00FFFF74UL +#define VReserved33 0x00FFFF78UL +#define Vcpmuplllck 0x00FFFF7CUL +#define Vcpmuosc 0x00FFFF80UL +#define Vadc0conv_compl 0x00FFFF84UL +#define Vadc0conv_seq_abrt 0x00FFFF88UL +#define Vadc0err 0x00FFFF8CUL +#define VReserved27 0x00FFFF90UL +#define VReserved26 0x00FFFF94UL +#define Vsci1 0x00FFFF98UL +#define Vsci0 0x00FFFF9CUL +#define Vspi0 0x00FFFFA0UL +#define VReserved22 0x00FFFFA4UL +#define VReserved21 0x00FFFFA8UL +#define Vtim0ovf 0x00FFFFACUL +#define VReserved19 0x00FFFFB0UL +#define VReserved18 0x00FFFFB4UL +#define Vtim0ch5 0x00FFFFB8UL +#define Vtim0ch4 0x00FFFFBCUL +#define Vtim0ch3 0x00FFFFC0UL +#define Vtim0ch2 0x00FFFFC4UL +#define Vtim0ch1 0x00FFFFC8UL +#define Vtim0ch0 0x00FFFFCCUL +#define Vrti 0x00FFFFD0UL +#define Virq 0x00FFFFD4UL +#define Vxirq 0x00FFFFD8UL +#define Vsi 0x00FFFFDCUL +#define VReserved7 0x00FFFFE0UL +#define VReserved6 0x00FFFFE4UL +#define Vme 0x00FFFFE8UL +#define Vsys 0x00FFFFECUL +#define Vswi 0x00FFFFF0UL +#define Vtrap 0x00FFFFF4UL +#define Vspare 0x00FFFFF8UL +#define Vreset 0x00FFFFFCUL + +/**************** registers I/O map ****************/ + +/*** PARTID - Part ID Register; 0x00000000 ***/ +typedef union { + dword Dword; + /* Overlapped registers: */ + struct { + /*** PARTID0 - Part ID Register 0; 0x00000000 ***/ + union { + byte Byte; + struct { + byte ID0 :8; /* Part ID 0 */ + } Bits; + } PARTID0STR; + #define PARTID0 _PARTID.Overlap_STR.PARTID0STR.Byte + #define PARTID0_ID0 _PARTID.Overlap_STR.PARTID0STR.Bits.ID0 + /* PARTID_ARR: Access 4 PARTIDx registers in an array */ + #define PARTID_ARR ((volatile byte *) &PARTID0) + + #define PARTID0_ID0_MASK 255U + #define PARTID0_ID0_BITNUM 0U + + + /*** PARTID1 - Part ID Register 1; 0x00000001 ***/ + union { + byte Byte; + struct { + byte ID1 :8; /* Part ID 1 */ + } Bits; + } PARTID1STR; + #define PARTID1 _PARTID.Overlap_STR.PARTID1STR.Byte + #define PARTID1_ID1 _PARTID.Overlap_STR.PARTID1STR.Bits.ID1 + + #define PARTID1_ID1_MASK 255U + #define PARTID1_ID1_BITNUM 0U + + + /*** PARTID2 - Part ID Register 2; 0x00000002 ***/ + union { + byte Byte; + struct { + byte ID2 :8; /* Part ID 2 */ + } Bits; + } PARTID2STR; + #define PARTID2 _PARTID.Overlap_STR.PARTID2STR.Byte + #define PARTID2_ID2 _PARTID.Overlap_STR.PARTID2STR.Bits.ID2 + + #define PARTID2_ID2_MASK 255U + #define PARTID2_ID2_BITNUM 0U + + + /*** PARTID3 - Part ID Register 3; 0x00000003 ***/ + union { + byte Byte; + struct { + byte ID3 :8; /* Part ID 3 */ + } Bits; + } PARTID3STR; + #define PARTID3 _PARTID.Overlap_STR.PARTID3STR.Byte + #define PARTID3_ID3 _PARTID.Overlap_STR.PARTID3STR.Bits.ID3 + + #define PARTID3_ID3_MASK 255U + #define PARTID3_ID3_BITNUM 0U + + } Overlap_STR; + +} PARTIDSTR; +extern volatile PARTIDSTR _PARTID @0x00000000; +#define PARTID _PARTID.Dword + + +/*** IVBR - Interrupt Vector Base Register; 0x00000010 ***/ +typedef union { + word Word; + struct { + word :1; + word IVB_ADDR :15; /* Interrupt Vector Base Address Bits */ + } Bits; +} IVBRSTR; +extern volatile IVBRSTR _IVBR @0x00000010; +#define IVBR _IVBR.Word +#define IVBR_IVB_ADDR _IVBR.Bits.IVB_ADDR + +#define IVBR_IVB_ADDR_MASK 65534U +#define IVBR_IVB_ADDR_BITNUM 1U + + +/*** INT_CFADDR - Interrupt Request Configuration Address Register; 0x00000017 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte INT_CFADDR_grp :4; /* Interrupt Request Configuration Data Register Select Bits */ /*Warning: group name is duplicated with register name*/ + byte :1; + } Bits; +} INT_CFADDRSTR; +extern volatile INT_CFADDRSTR _INT_CFADDR @0x00000017; +#define INT_CFADDR _INT_CFADDR.Byte +#define INT_CFADDR_INT_CFADDR _INT_CFADDR.Bits.INT_CFADDR_grp + +#define INT_CFADDR_INT_CFADDR_MASK 120U +#define INT_CFADDR_INT_CFADDR_BITNUM 3U + + +/*** INT_CFDATA0 - Interrupt Request Configuration Data Register 0; 0x00000018 ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA0STR; +extern volatile INT_CFDATA0STR _INT_CFDATA0 @0x00000018; +#define INT_CFDATA0 _INT_CFDATA0.Byte +#define INT_CFDATA0_PRIOLVL _INT_CFDATA0.Bits.PRIOLVL +/* INT_CFDATA_ARR: Access 8 INT_CFDATAx registers in an array */ +#define INT_CFDATA_ARR ((volatile byte *) &INT_CFDATA0) + +#define INT_CFDATA0_PRIOLVL_MASK 7U +#define INT_CFDATA0_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA1 - Interrupt Request Configuration Data Register 1; 0x00000019 ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA1STR; +extern volatile INT_CFDATA1STR _INT_CFDATA1 @0x00000019; +#define INT_CFDATA1 _INT_CFDATA1.Byte +#define INT_CFDATA1_PRIOLVL _INT_CFDATA1.Bits.PRIOLVL + +#define INT_CFDATA1_PRIOLVL_MASK 7U +#define INT_CFDATA1_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA2 - Interrupt Request Configuration Data Register 2; 0x0000001A ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA2STR; +extern volatile INT_CFDATA2STR _INT_CFDATA2 @0x0000001A; +#define INT_CFDATA2 _INT_CFDATA2.Byte +#define INT_CFDATA2_PRIOLVL _INT_CFDATA2.Bits.PRIOLVL + +#define INT_CFDATA2_PRIOLVL_MASK 7U +#define INT_CFDATA2_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA3 - Interrupt Request Configuration Data Register 3; 0x0000001B ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA3STR; +extern volatile INT_CFDATA3STR _INT_CFDATA3 @0x0000001B; +#define INT_CFDATA3 _INT_CFDATA3.Byte +#define INT_CFDATA3_PRIOLVL _INT_CFDATA3.Bits.PRIOLVL + +#define INT_CFDATA3_PRIOLVL_MASK 7U +#define INT_CFDATA3_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA4 - Interrupt Request Configuration Data Register 4; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA4STR; +extern volatile INT_CFDATA4STR _INT_CFDATA4 @0x0000001C; +#define INT_CFDATA4 _INT_CFDATA4.Byte +#define INT_CFDATA4_PRIOLVL _INT_CFDATA4.Bits.PRIOLVL + +#define INT_CFDATA4_PRIOLVL_MASK 7U +#define INT_CFDATA4_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA5 - Interrupt Request Configuration Data Register 5; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA5STR; +extern volatile INT_CFDATA5STR _INT_CFDATA5 @0x0000001D; +#define INT_CFDATA5 _INT_CFDATA5.Byte +#define INT_CFDATA5_PRIOLVL _INT_CFDATA5.Bits.PRIOLVL + +#define INT_CFDATA5_PRIOLVL_MASK 7U +#define INT_CFDATA5_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA6 - Interrupt Request Configuration Data Register 6; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA6STR; +extern volatile INT_CFDATA6STR _INT_CFDATA6 @0x0000001E; +#define INT_CFDATA6 _INT_CFDATA6.Byte +#define INT_CFDATA6_PRIOLVL _INT_CFDATA6.Bits.PRIOLVL + +#define INT_CFDATA6_PRIOLVL_MASK 7U +#define INT_CFDATA6_PRIOLVL_BITNUM 0U + + +/*** INT_CFDATA7 - Interrupt Request Configuration Data Register 7; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte PRIOLVL :3; /* Interrupt Request Priority Level Bits */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} INT_CFDATA7STR; +extern volatile INT_CFDATA7STR _INT_CFDATA7 @0x0000001F; +#define INT_CFDATA7 _INT_CFDATA7.Byte +#define INT_CFDATA7_PRIOLVL _INT_CFDATA7.Bits.PRIOLVL + +#define INT_CFDATA7_PRIOLVL_MASK 7U +#define INT_CFDATA7_PRIOLVL_BITNUM 0U + + +/*** MODE - Mode Register; 0x00000070 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte MODC :1; /* Mode Select Bit */ + } Bits; +} MODESTR; +extern volatile MODESTR _MODE @0x00000070; +#define MODE _MODE.Byte +#define MODE_MODC _MODE.Bits.MODC + +#define MODE_MODC_MASK 128U + + +/*** MMCEC - Error code register; 0x00000080 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MMCECH - Error code register high; 0x00000080 ***/ + union { + byte Byte; + struct { + byte TGT :4; /* Target Field */ + byte ITR :4; /* Initiator Field */ + } Bits; + } MMCECHSTR; + #define MMCECH _MMCEC.Overlap_STR.MMCECHSTR.Byte + #define MMCECH_TGT _MMCEC.Overlap_STR.MMCECHSTR.Bits.TGT + #define MMCECH_ITR _MMCEC.Overlap_STR.MMCECHSTR.Bits.ITR + + #define MMCECH_TGT_MASK 15U + #define MMCECH_TGT_BITNUM 0U + #define MMCECH_ITR_MASK 240U + #define MMCECH_ITR_BITNUM 4U + + + /*** MMCECL - Error code register low; 0x00000081 ***/ + union { + byte Byte; + struct { + byte ERR :4; /* Error Type Field */ + byte ACC :4; /* Access Type Field */ + } Bits; + } MMCECLSTR; + #define MMCECL _MMCEC.Overlap_STR.MMCECLSTR.Byte + #define MMCECL_ERR _MMCEC.Overlap_STR.MMCECLSTR.Bits.ERR + #define MMCECL_ACC _MMCEC.Overlap_STR.MMCECLSTR.Bits.ACC + + #define MMCECL_ERR_MASK 15U + #define MMCECL_ERR_BITNUM 0U + #define MMCECL_ACC_MASK 240U + #define MMCECL_ACC_BITNUM 4U + + } Overlap_STR; + + struct { + word ERR :4; /* Error Type Field */ + word ACC :4; /* Access Type Field */ + word TGT :4; /* Target Field */ + word ITR :4; /* Initiator Field */ + } Bits; +} MMCECSTR; +extern volatile MMCECSTR _MMCEC @0x00000080; +#define MMCEC _MMCEC.Word +#define MMCEC_ERR _MMCEC.Bits.ERR +#define MMCEC_ACC _MMCEC.Bits.ACC +#define MMCEC_TGT _MMCEC.Bits.TGT +#define MMCEC_ITR _MMCEC.Bits.ITR + +#define MMCEC_ERR_MASK 15U +#define MMCEC_ERR_BITNUM 0U +#define MMCEC_ACC_MASK 240U +#define MMCEC_ACC_BITNUM 4U +#define MMCEC_TGT_MASK 3840U +#define MMCEC_TGT_BITNUM 8U +#define MMCEC_ITR_MASK 61440U +#define MMCEC_ITR_BITNUM 12U + + +/*** MMCCCR - Captured S12ZCPU Condition Code Register Low; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MMCCCRH - Captured S12ZCPU Condition Code Register High; 0x00000082 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CPUU :1; /* S12ZCPU User State Flag */ + } Bits; + } MMCCCRHSTR; + #define MMCCCRH _MMCCCR.Overlap_STR.MMCCCRHSTR.Byte + #define MMCCCRH_CPUU _MMCCCR.Overlap_STR.MMCCCRHSTR.Bits.CPUU + + #define MMCCCRH_CPUU_MASK 128U + + + /*** MMCCCRL - Captured S12ZCPU Condition Code Register Low; 0x00000083 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte CPUI :1; /* S12ZCPU I-Interrupt Mask */ + byte :1; + byte CPUX :1; /* S12ZCPU X-Interrupt Mask */ + byte :1; + } Bits; + } MMCCCRLSTR; + #define MMCCCRL _MMCCCR.Overlap_STR.MMCCCRLSTR.Byte + #define MMCCCRL_CPUI _MMCCCR.Overlap_STR.MMCCCRLSTR.Bits.CPUI + #define MMCCCRL_CPUX _MMCCCR.Overlap_STR.MMCCCRLSTR.Bits.CPUX + + #define MMCCCRL_CPUI_MASK 16U + #define MMCCCRL_CPUX_MASK 64U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word CPUI :1; /* S12ZCPU I-Interrupt Mask */ + word :1; + word CPUX :1; /* S12ZCPU X-Interrupt Mask */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word CPUU :1; /* S12ZCPU User State Flag */ + } Bits; +} MMCCCRSTR; +extern volatile MMCCCRSTR _MMCCCR @0x00000082; +#define MMCCCR _MMCCCR.Word +#define MMCCCR_CPUI _MMCCCR.Bits.CPUI +#define MMCCCR_CPUX _MMCCCR.Bits.CPUX +#define MMCCCR_CPUU _MMCCCR.Bits.CPUU + +#define MMCCCR_CPUI_MASK 16U +#define MMCCCR_CPUX_MASK 64U +#define MMCCCR_CPUU_MASK 32768U + + +/*** MMCPCH - Captured S12ZCPU Program Counter High; 0x00000085 ***/ +typedef union { + byte Byte; + struct { + byte CPUPC :8; /* S12ZCPU Program Counter Value */ + } Bits; +} MMCPCHSTR; +extern volatile MMCPCHSTR _MMCPCH @0x00000085; +#define MMCPCH _MMCPCH.Byte +#define MMCPCH_CPUPC _MMCPCH.Bits.CPUPC + +#define MMCPCH_CPUPC_MASK 255U +#define MMCPCH_CPUPC_BITNUM 0U + + +/*** MMCPCM - Captured S12ZCPU Program Counter Middle; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CPUPC :8; /* S12ZCPU Program Counter Value */ + } Bits; +} MMCPCMSTR; +extern volatile MMCPCMSTR _MMCPCM @0x00000086; +#define MMCPCM _MMCPCM.Byte +#define MMCPCM_CPUPC _MMCPCM.Bits.CPUPC + +#define MMCPCM_CPUPC_MASK 255U +#define MMCPCM_CPUPC_BITNUM 0U + + +/*** MMCPCL - Captured S12ZCPU Program Counter Low; 0x00000087 ***/ +typedef union { + byte Byte; + struct { + byte CPUPC :8; /* S12ZCPU Program Counter Value */ + } Bits; +} MMCPCLSTR; +extern volatile MMCPCLSTR _MMCPCL @0x00000087; +#define MMCPCL _MMCPCL.Byte +#define MMCPCL_CPUPC _MMCPCL.Bits.CPUPC + +#define MMCPCL_CPUPC_MASK 255U +#define MMCPCL_CPUPC_BITNUM 0U + + +/*** DBGC1 - Debug Control Register 1; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte EEVE :2; /* External Event Enable Bits */ + byte :1; + byte BRKCPU :1; /* CPU Breakpoint Enable */ + byte BDMBP :1; /* Background Debug Mode Enable */ + byte :1; + byte TRIG :1; /* Immediate Trigger Request Bit */ + byte ARM :1; /* Arm Bit */ + } Bits; +} DBGC1STR; +extern volatile DBGC1STR _DBGC1 @0x00000100; +#define DBGC1 _DBGC1.Byte +#define DBGC1_EEVE _DBGC1.Bits.EEVE +#define DBGC1_BRKCPU _DBGC1.Bits.BRKCPU +#define DBGC1_BDMBP _DBGC1.Bits.BDMBP +#define DBGC1_TRIG _DBGC1.Bits.TRIG +#define DBGC1_ARM _DBGC1.Bits.ARM + +#define DBGC1_EEVE_MASK 3U +#define DBGC1_EEVE_BITNUM 0U +#define DBGC1_BRKCPU_MASK 8U +#define DBGC1_BDMBP_MASK 16U +#define DBGC1_TRIG_MASK 64U +#define DBGC1_ARM_MASK 128U + + +/*** DBGC2 - Debug Control Register 2; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte ABCM :2; /* A and B Comparator Match Control */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} DBGC2STR; +extern volatile DBGC2STR _DBGC2 @0x00000101; +#define DBGC2 _DBGC2.Byte +#define DBGC2_ABCM _DBGC2.Bits.ABCM + +#define DBGC2_ABCM_MASK 3U +#define DBGC2_ABCM_BITNUM 0U + + +/*** DBGSCR1 - Debug State Control Register 1; 0x00000107 ***/ +typedef union { + byte Byte; + struct { + byte C0SC :2; /* Match State Sequencer Transitions Bits */ + byte C1SC :2; /* Match State Sequencer Transitions Bits */ + byte :1; + byte :1; + byte C3SC :2; /* Match State Sequencer Transitions Bits */ + } Bits; +} DBGSCR1STR; +extern volatile DBGSCR1STR _DBGSCR1 @0x00000107; +#define DBGSCR1 _DBGSCR1.Byte +#define DBGSCR1_C0SC _DBGSCR1.Bits.C0SC +#define DBGSCR1_C1SC _DBGSCR1.Bits.C1SC +#define DBGSCR1_C3SC _DBGSCR1.Bits.C3SC + +#define DBGSCR1_C0SC_MASK 3U +#define DBGSCR1_C0SC_BITNUM 0U +#define DBGSCR1_C1SC_MASK 12U +#define DBGSCR1_C1SC_BITNUM 2U +#define DBGSCR1_C3SC_MASK 192U +#define DBGSCR1_C3SC_BITNUM 6U + + +/*** DBGSCR2 - Debug State Control Register 2; 0x00000108 ***/ +typedef union { + byte Byte; + struct { + byte C0SC :2; /* Match State Sequencer Transitions Bits */ + byte C1SC :2; /* Match State Sequencer Transitions Bits */ + byte :1; + byte :1; + byte C3SC :2; /* Match State Sequencer Transitions Bits */ + } Bits; +} DBGSCR2STR; +extern volatile DBGSCR2STR _DBGSCR2 @0x00000108; +#define DBGSCR2 _DBGSCR2.Byte +#define DBGSCR2_C0SC _DBGSCR2.Bits.C0SC +#define DBGSCR2_C1SC _DBGSCR2.Bits.C1SC +#define DBGSCR2_C3SC _DBGSCR2.Bits.C3SC + +#define DBGSCR2_C0SC_MASK 3U +#define DBGSCR2_C0SC_BITNUM 0U +#define DBGSCR2_C1SC_MASK 12U +#define DBGSCR2_C1SC_BITNUM 2U +#define DBGSCR2_C3SC_MASK 192U +#define DBGSCR2_C3SC_BITNUM 6U + + +/*** DBGSCR3 - Debug State Control Register 3; 0x00000109 ***/ +typedef union { + byte Byte; + struct { + byte C0SC :2; /* Match State Sequencer Transitions Bits */ + byte C1SC :2; /* Match State Sequencer Transitions Bits */ + byte :1; + byte :1; + byte C3SC :2; /* Match State Sequencer Transitions Bits */ + } Bits; +} DBGSCR3STR; +extern volatile DBGSCR3STR _DBGSCR3 @0x00000109; +#define DBGSCR3 _DBGSCR3.Byte +#define DBGSCR3_C0SC _DBGSCR3.Bits.C0SC +#define DBGSCR3_C1SC _DBGSCR3.Bits.C1SC +#define DBGSCR3_C3SC _DBGSCR3.Bits.C3SC + +#define DBGSCR3_C0SC_MASK 3U +#define DBGSCR3_C0SC_BITNUM 0U +#define DBGSCR3_C1SC_MASK 12U +#define DBGSCR3_C1SC_BITNUM 2U +#define DBGSCR3_C3SC_MASK 192U +#define DBGSCR3_C3SC_BITNUM 6U + + +/*** DBGEFR - Debug Event Flag Register; 0x0000010A ***/ +typedef union { + byte Byte; + struct { + byte ME0 :1; /* Match Event 0 */ + byte ME1 :1; /* Match Event 1 */ + byte :1; + byte ME3 :1; /* Match Event 3 */ + byte EEVF :1; /* External Event Flag */ + byte :1; + byte TRIGF :1; /* TRIG Flag */ + byte :1; + } Bits; + struct { + byte grpME :2; + byte :1; + byte grpME_3 :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DBGEFRSTR; +extern volatile DBGEFRSTR _DBGEFR @0x0000010A; +#define DBGEFR _DBGEFR.Byte +#define DBGEFR_ME0 _DBGEFR.Bits.ME0 +#define DBGEFR_ME1 _DBGEFR.Bits.ME1 +#define DBGEFR_ME3 _DBGEFR.Bits.ME3 +#define DBGEFR_EEVF _DBGEFR.Bits.EEVF +#define DBGEFR_TRIGF _DBGEFR.Bits.TRIGF +#define DBGEFR_ME _DBGEFR.MergedBits.grpME + +#define DBGEFR_ME0_MASK 1U +#define DBGEFR_ME1_MASK 2U +#define DBGEFR_ME3_MASK 8U +#define DBGEFR_EEVF_MASK 16U +#define DBGEFR_TRIGF_MASK 64U +#define DBGEFR_ME_MASK 3U +#define DBGEFR_ME_BITNUM 0U + + +/*** DBGSR - Debug Status Register; 0x0000010B ***/ +typedef union { + byte Byte; + struct { + byte SSF0 :1; /* State Sequencer Flag Bits */ + byte SSF1 :1; /* State Sequencer Flag Bit 1 */ + byte SSF2 :1; /* State Sequencer Flag Bit 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSSF :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DBGSRSTR; +extern volatile DBGSRSTR _DBGSR @0x0000010B; +#define DBGSR _DBGSR.Byte +#define DBGSR_SSF0 _DBGSR.Bits.SSF0 +#define DBGSR_SSF1 _DBGSR.Bits.SSF1 +#define DBGSR_SSF2 _DBGSR.Bits.SSF2 +#define DBGSR_SSF _DBGSR.MergedBits.grpSSF + +#define DBGSR_SSF0_MASK 1U +#define DBGSR_SSF1_MASK 2U +#define DBGSR_SSF2_MASK 4U +#define DBGSR_SSF_MASK 7U +#define DBGSR_SSF_BITNUM 0U + + +/*** DBGACTL - Debug Comparator A Control Register; 0x00000110 ***/ +typedef union { + byte Byte; + struct { + byte COMPE :1; /* Determines if comparator is enabled */ + byte :1; + byte RWE :1; /* Read/Write Enable Bit */ + byte RW :1; /* Read/Write Comparator Value Bit */ + byte :1; + byte INST :1; /* Instruction Select */ + byte NDB :1; /* Not Data Bus */ + byte :1; + } Bits; +} DBGACTLSTR; +extern volatile DBGACTLSTR _DBGACTL @0x00000110; +#define DBGACTL _DBGACTL.Byte +#define DBGACTL_COMPE _DBGACTL.Bits.COMPE +#define DBGACTL_RWE _DBGACTL.Bits.RWE +#define DBGACTL_RW _DBGACTL.Bits.RW +#define DBGACTL_INST _DBGACTL.Bits.INST +#define DBGACTL_NDB _DBGACTL.Bits.NDB + +#define DBGACTL_COMPE_MASK 1U +#define DBGACTL_RWE_MASK 4U +#define DBGACTL_RW_MASK 8U +#define DBGACTL_INST_MASK 32U +#define DBGACTL_NDB_MASK 64U + + +/*** DBGAAH - Debug Comparator A Address Register High; 0x00000115 ***/ +typedef union { + byte Byte; + struct { + byte DBGAA :8; /* Comparator Address Bits */ + } Bits; +} DBGAAHSTR; +extern volatile DBGAAHSTR _DBGAAH @0x00000115; +#define DBGAAH _DBGAAH.Byte +#define DBGAAH_DBGAA _DBGAAH.Bits.DBGAA + +#define DBGAAH_DBGAA_MASK 255U +#define DBGAAH_DBGAA_BITNUM 0U + + +/*** DBGAAM - Debug Comparator A Address Register Middle; 0x00000116 ***/ +typedef union { + byte Byte; + struct { + byte DBGAA :8; /* Comparator Address Bits */ + } Bits; +} DBGAAMSTR; +extern volatile DBGAAMSTR _DBGAAM @0x00000116; +#define DBGAAM _DBGAAM.Byte +#define DBGAAM_DBGAA _DBGAAM.Bits.DBGAA + +#define DBGAAM_DBGAA_MASK 255U +#define DBGAAM_DBGAA_BITNUM 0U + + +/*** DBGAAL - Debug Comparator A Address Register Low; 0x00000117 ***/ +typedef union { + byte Byte; + struct { + byte DBGAA :8; /* Comparator Address Bits */ + } Bits; +} DBGAALSTR; +extern volatile DBGAALSTR _DBGAAL @0x00000117; +#define DBGAAL _DBGAAL.Byte +#define DBGAAL_DBGAA _DBGAAL.Bits.DBGAA + +#define DBGAAL_DBGAA_MASK 255U +#define DBGAAL_DBGAA_BITNUM 0U + + +/*** DBGAD0 - Debug Comparator A Data Register 0; 0x00000118 ***/ +typedef union { + byte Byte; + struct { + byte BIT24 :1; /* Comparator Data Bit 24 */ + byte BIT25 :1; /* Comparator Data Bit 25 */ + byte BIT26 :1; /* Comparator Data Bit 26 */ + byte BIT27 :1; /* Comparator Data Bit 27 */ + byte BIT28 :1; /* Comparator Data Bit 28 */ + byte BIT29 :1; /* Comparator Data Bit 29 */ + byte BIT30 :1; /* Comparator Data Bit 30 */ + byte BIT31 :1; /* Comparator Data Bit 31 */ + } Bits; +} DBGAD0STR; +extern volatile DBGAD0STR _DBGAD0 @0x00000118; +#define DBGAD0 _DBGAD0.Byte +#define DBGAD0_BIT24 _DBGAD0.Bits.BIT24 +#define DBGAD0_BIT25 _DBGAD0.Bits.BIT25 +#define DBGAD0_BIT26 _DBGAD0.Bits.BIT26 +#define DBGAD0_BIT27 _DBGAD0.Bits.BIT27 +#define DBGAD0_BIT28 _DBGAD0.Bits.BIT28 +#define DBGAD0_BIT29 _DBGAD0.Bits.BIT29 +#define DBGAD0_BIT30 _DBGAD0.Bits.BIT30 +#define DBGAD0_BIT31 _DBGAD0.Bits.BIT31 +/* DBGAD_ARR: Access 4 DBGADx registers in an array */ +#define DBGAD_ARR ((volatile byte *) &DBGAD0) + +#define DBGAD0_BIT24_MASK 1U +#define DBGAD0_BIT25_MASK 2U +#define DBGAD0_BIT26_MASK 4U +#define DBGAD0_BIT27_MASK 8U +#define DBGAD0_BIT28_MASK 16U +#define DBGAD0_BIT29_MASK 32U +#define DBGAD0_BIT30_MASK 64U +#define DBGAD0_BIT31_MASK 128U + + +/*** DBGAD1 - Debug Comparator A Data Register 1; 0x00000119 ***/ +typedef union { + byte Byte; + struct { + byte BIT16 :1; /* Comparator Data Bit 16 */ + byte BIT17 :1; /* Comparator Data Bit 17 */ + byte BIT18 :1; /* Comparator Data Bit 18 */ + byte BIT19 :1; /* Comparator Data Bit 19 */ + byte BIT20 :1; /* Comparator Data Bit 20 */ + byte BIT21 :1; /* Comparator Data Bit 21 */ + byte BIT22 :1; /* Comparator Data Bit 22 */ + byte BIT23 :1; /* Comparator Data Bit 23 */ + } Bits; +} DBGAD1STR; +extern volatile DBGAD1STR _DBGAD1 @0x00000119; +#define DBGAD1 _DBGAD1.Byte +#define DBGAD1_BIT16 _DBGAD1.Bits.BIT16 +#define DBGAD1_BIT17 _DBGAD1.Bits.BIT17 +#define DBGAD1_BIT18 _DBGAD1.Bits.BIT18 +#define DBGAD1_BIT19 _DBGAD1.Bits.BIT19 +#define DBGAD1_BIT20 _DBGAD1.Bits.BIT20 +#define DBGAD1_BIT21 _DBGAD1.Bits.BIT21 +#define DBGAD1_BIT22 _DBGAD1.Bits.BIT22 +#define DBGAD1_BIT23 _DBGAD1.Bits.BIT23 + +#define DBGAD1_BIT16_MASK 1U +#define DBGAD1_BIT17_MASK 2U +#define DBGAD1_BIT18_MASK 4U +#define DBGAD1_BIT19_MASK 8U +#define DBGAD1_BIT20_MASK 16U +#define DBGAD1_BIT21_MASK 32U +#define DBGAD1_BIT22_MASK 64U +#define DBGAD1_BIT23_MASK 128U + + +/*** DBGAD2 - Debug Comparator A Data Register 2; 0x0000011A ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Comparator Data Bit 8 */ + byte BIT9 :1; /* Comparator Data Bit 9 */ + byte BIT10 :1; /* Comparator Data Bit 10 */ + byte BIT11 :1; /* Comparator Data Bit 11 */ + byte BIT12 :1; /* Comparator Data Bit 12 */ + byte BIT13 :1; /* Comparator Data Bit 13 */ + byte BIT14 :1; /* Comparator Data Bit 14 */ + byte BIT15 :1; /* Comparator Data Bit 15 */ + } Bits; +} DBGAD2STR; +extern volatile DBGAD2STR _DBGAD2 @0x0000011A; +#define DBGAD2 _DBGAD2.Byte +#define DBGAD2_BIT8 _DBGAD2.Bits.BIT8 +#define DBGAD2_BIT9 _DBGAD2.Bits.BIT9 +#define DBGAD2_BIT10 _DBGAD2.Bits.BIT10 +#define DBGAD2_BIT11 _DBGAD2.Bits.BIT11 +#define DBGAD2_BIT12 _DBGAD2.Bits.BIT12 +#define DBGAD2_BIT13 _DBGAD2.Bits.BIT13 +#define DBGAD2_BIT14 _DBGAD2.Bits.BIT14 +#define DBGAD2_BIT15 _DBGAD2.Bits.BIT15 + +#define DBGAD2_BIT8_MASK 1U +#define DBGAD2_BIT9_MASK 2U +#define DBGAD2_BIT10_MASK 4U +#define DBGAD2_BIT11_MASK 8U +#define DBGAD2_BIT12_MASK 16U +#define DBGAD2_BIT13_MASK 32U +#define DBGAD2_BIT14_MASK 64U +#define DBGAD2_BIT15_MASK 128U + + +/*** DBGAD3 - Debug Comparator A Data Register 3; 0x0000011B ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Comparator Data Bit 0 */ + byte BIT1 :1; /* Comparator Data Bit 1 */ + byte BIT2 :1; /* Comparator Data Bit 2 */ + byte BIT3 :1; /* Comparator Data Bit 3 */ + byte BIT4 :1; /* Comparator Data Bit 4 */ + byte BIT5 :1; /* Comparator Data Bit 5 */ + byte BIT6 :1; /* Comparator Data Bit 6 */ + byte BIT7 :1; /* Comparator Data Bit 7 */ + } Bits; +} DBGAD3STR; +extern volatile DBGAD3STR _DBGAD3 @0x0000011B; +#define DBGAD3 _DBGAD3.Byte +#define DBGAD3_BIT0 _DBGAD3.Bits.BIT0 +#define DBGAD3_BIT1 _DBGAD3.Bits.BIT1 +#define DBGAD3_BIT2 _DBGAD3.Bits.BIT2 +#define DBGAD3_BIT3 _DBGAD3.Bits.BIT3 +#define DBGAD3_BIT4 _DBGAD3.Bits.BIT4 +#define DBGAD3_BIT5 _DBGAD3.Bits.BIT5 +#define DBGAD3_BIT6 _DBGAD3.Bits.BIT6 +#define DBGAD3_BIT7 _DBGAD3.Bits.BIT7 + +#define DBGAD3_BIT0_MASK 1U +#define DBGAD3_BIT1_MASK 2U +#define DBGAD3_BIT2_MASK 4U +#define DBGAD3_BIT3_MASK 8U +#define DBGAD3_BIT4_MASK 16U +#define DBGAD3_BIT5_MASK 32U +#define DBGAD3_BIT6_MASK 64U +#define DBGAD3_BIT7_MASK 128U + + +/*** DBGADM0 - Debug Comparator A Data Mask Register 0; 0x0000011C ***/ +typedef union { + byte Byte; + struct { + byte BIT24 :1; /* Comparator Data Mask Bit 24 */ + byte BIT25 :1; /* Comparator Data Mask Bit 25 */ + byte BIT26 :1; /* Comparator Data Mask Bit 26 */ + byte BIT27 :1; /* Comparator Data Mask Bit 27 */ + byte BIT28 :1; /* Comparator Data Mask Bit 28 */ + byte BIT29 :1; /* Comparator Data Mask Bit 29 */ + byte BIT30 :1; /* Comparator Data Mask Bit 30 */ + byte BIT31 :1; /* Comparator Data Mask Bit 31 */ + } Bits; +} DBGADM0STR; +extern volatile DBGADM0STR _DBGADM0 @0x0000011C; +#define DBGADM0 _DBGADM0.Byte +#define DBGADM0_BIT24 _DBGADM0.Bits.BIT24 +#define DBGADM0_BIT25 _DBGADM0.Bits.BIT25 +#define DBGADM0_BIT26 _DBGADM0.Bits.BIT26 +#define DBGADM0_BIT27 _DBGADM0.Bits.BIT27 +#define DBGADM0_BIT28 _DBGADM0.Bits.BIT28 +#define DBGADM0_BIT29 _DBGADM0.Bits.BIT29 +#define DBGADM0_BIT30 _DBGADM0.Bits.BIT30 +#define DBGADM0_BIT31 _DBGADM0.Bits.BIT31 +/* DBGADM_ARR: Access 4 DBGADMx registers in an array */ +#define DBGADM_ARR ((volatile byte *) &DBGADM0) + +#define DBGADM0_BIT24_MASK 1U +#define DBGADM0_BIT25_MASK 2U +#define DBGADM0_BIT26_MASK 4U +#define DBGADM0_BIT27_MASK 8U +#define DBGADM0_BIT28_MASK 16U +#define DBGADM0_BIT29_MASK 32U +#define DBGADM0_BIT30_MASK 64U +#define DBGADM0_BIT31_MASK 128U + + +/*** DBGADM1 - Debug Comparator A Data Mask Register 1; 0x0000011D ***/ +typedef union { + byte Byte; + struct { + byte BIT16 :1; /* Comparator Data Mask Bit 16 */ + byte BIT17 :1; /* Comparator Data Mask Bit 17 */ + byte BIT18 :1; /* Comparator Data Mask Bit 18 */ + byte BIT19 :1; /* Comparator Data Mask Bit 19 */ + byte BIT20 :1; /* Comparator Data Mask Bit 20 */ + byte BIT21 :1; /* Comparator Data Mask Bit 21 */ + byte BIT22 :1; /* Comparator Data Mask Bit 22 */ + byte BIT23 :1; /* Comparator Data Mask Bit 23 */ + } Bits; +} DBGADM1STR; +extern volatile DBGADM1STR _DBGADM1 @0x0000011D; +#define DBGADM1 _DBGADM1.Byte +#define DBGADM1_BIT16 _DBGADM1.Bits.BIT16 +#define DBGADM1_BIT17 _DBGADM1.Bits.BIT17 +#define DBGADM1_BIT18 _DBGADM1.Bits.BIT18 +#define DBGADM1_BIT19 _DBGADM1.Bits.BIT19 +#define DBGADM1_BIT20 _DBGADM1.Bits.BIT20 +#define DBGADM1_BIT21 _DBGADM1.Bits.BIT21 +#define DBGADM1_BIT22 _DBGADM1.Bits.BIT22 +#define DBGADM1_BIT23 _DBGADM1.Bits.BIT23 + +#define DBGADM1_BIT16_MASK 1U +#define DBGADM1_BIT17_MASK 2U +#define DBGADM1_BIT18_MASK 4U +#define DBGADM1_BIT19_MASK 8U +#define DBGADM1_BIT20_MASK 16U +#define DBGADM1_BIT21_MASK 32U +#define DBGADM1_BIT22_MASK 64U +#define DBGADM1_BIT23_MASK 128U + + +/*** DBGADM2 - Debug Comparator A Data Mask Register 2; 0x0000011E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Comparator Data Mask Bit 8 */ + byte BIT9 :1; /* Comparator Data Mask Bit 9 */ + byte BIT10 :1; /* Comparator Data Mask Bit 10 */ + byte BIT11 :1; /* Comparator Data Mask Bit 11 */ + byte BIT12 :1; /* Comparator Data Mask Bit 12 */ + byte BIT13 :1; /* Comparator Data Mask Bit 13 */ + byte BIT14 :1; /* Comparator Data Mask Bit 14 */ + byte BIT15 :1; /* Comparator Data Mask Bit 15 */ + } Bits; +} DBGADM2STR; +extern volatile DBGADM2STR _DBGADM2 @0x0000011E; +#define DBGADM2 _DBGADM2.Byte +#define DBGADM2_BIT8 _DBGADM2.Bits.BIT8 +#define DBGADM2_BIT9 _DBGADM2.Bits.BIT9 +#define DBGADM2_BIT10 _DBGADM2.Bits.BIT10 +#define DBGADM2_BIT11 _DBGADM2.Bits.BIT11 +#define DBGADM2_BIT12 _DBGADM2.Bits.BIT12 +#define DBGADM2_BIT13 _DBGADM2.Bits.BIT13 +#define DBGADM2_BIT14 _DBGADM2.Bits.BIT14 +#define DBGADM2_BIT15 _DBGADM2.Bits.BIT15 + +#define DBGADM2_BIT8_MASK 1U +#define DBGADM2_BIT9_MASK 2U +#define DBGADM2_BIT10_MASK 4U +#define DBGADM2_BIT11_MASK 8U +#define DBGADM2_BIT12_MASK 16U +#define DBGADM2_BIT13_MASK 32U +#define DBGADM2_BIT14_MASK 64U +#define DBGADM2_BIT15_MASK 128U + + +/*** DBGADM3 - Debug Comparator A Data Mask Register 3; 0x0000011F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Comparator Data Mask Bit 0 */ + byte BIT1 :1; /* Comparator Data Mask Bit 1 */ + byte BIT2 :1; /* Comparator Data Mask Bit 2 */ + byte BIT3 :1; /* Comparator Data Mask Bit 3 */ + byte BIT4 :1; /* Comparator Data Mask Bit 4 */ + byte BIT5 :1; /* Comparator Data Mask Bit 5 */ + byte BIT6 :1; /* Comparator Data Mask Bit 6 */ + byte BIT7 :1; /* Comparator Data Mask Bit 7 */ + } Bits; +} DBGADM3STR; +extern volatile DBGADM3STR _DBGADM3 @0x0000011F; +#define DBGADM3 _DBGADM3.Byte +#define DBGADM3_BIT0 _DBGADM3.Bits.BIT0 +#define DBGADM3_BIT1 _DBGADM3.Bits.BIT1 +#define DBGADM3_BIT2 _DBGADM3.Bits.BIT2 +#define DBGADM3_BIT3 _DBGADM3.Bits.BIT3 +#define DBGADM3_BIT4 _DBGADM3.Bits.BIT4 +#define DBGADM3_BIT5 _DBGADM3.Bits.BIT5 +#define DBGADM3_BIT6 _DBGADM3.Bits.BIT6 +#define DBGADM3_BIT7 _DBGADM3.Bits.BIT7 + +#define DBGADM3_BIT0_MASK 1U +#define DBGADM3_BIT1_MASK 2U +#define DBGADM3_BIT2_MASK 4U +#define DBGADM3_BIT3_MASK 8U +#define DBGADM3_BIT4_MASK 16U +#define DBGADM3_BIT5_MASK 32U +#define DBGADM3_BIT6_MASK 64U +#define DBGADM3_BIT7_MASK 128U + + +/*** DBGBCTL - Debug Comparator B Control Register; 0x00000120 ***/ +typedef union { + byte Byte; + struct { + byte COMPE :1; /* Determines if comparator is enabled */ + byte :1; + byte RWE :1; /* Read/Write Enable Bit */ + byte RW :1; /* Read/Write Comparator Value Bit */ + byte :1; + byte INST :1; /* Instruction Select */ + byte :1; + byte :1; + } Bits; +} DBGBCTLSTR; +extern volatile DBGBCTLSTR _DBGBCTL @0x00000120; +#define DBGBCTL _DBGBCTL.Byte +#define DBGBCTL_COMPE _DBGBCTL.Bits.COMPE +#define DBGBCTL_RWE _DBGBCTL.Bits.RWE +#define DBGBCTL_RW _DBGBCTL.Bits.RW +#define DBGBCTL_INST _DBGBCTL.Bits.INST + +#define DBGBCTL_COMPE_MASK 1U +#define DBGBCTL_RWE_MASK 4U +#define DBGBCTL_RW_MASK 8U +#define DBGBCTL_INST_MASK 32U + + +/*** DBGBAH - Debug Comparator B Address Register High; 0x00000125 ***/ +typedef union { + byte Byte; + struct { + byte DBGBA :8; /* Comparator Address Bits */ + } Bits; +} DBGBAHSTR; +extern volatile DBGBAHSTR _DBGBAH @0x00000125; +#define DBGBAH _DBGBAH.Byte +#define DBGBAH_DBGBA _DBGBAH.Bits.DBGBA + +#define DBGBAH_DBGBA_MASK 255U +#define DBGBAH_DBGBA_BITNUM 0U + + +/*** DBGBAM - Debug Comparator B Address Register Middle; 0x00000126 ***/ +typedef union { + byte Byte; + struct { + byte DBGBA :8; /* Comparator Address Bits */ + } Bits; +} DBGBAMSTR; +extern volatile DBGBAMSTR _DBGBAM @0x00000126; +#define DBGBAM _DBGBAM.Byte +#define DBGBAM_DBGBA _DBGBAM.Bits.DBGBA + +#define DBGBAM_DBGBA_MASK 255U +#define DBGBAM_DBGBA_BITNUM 0U + + +/*** DBGBAL - Debug Comparator B Address Register Low; 0x00000127 ***/ +typedef union { + byte Byte; + struct { + byte DBGBA :8; /* Comparator Address Bits */ + } Bits; +} DBGBALSTR; +extern volatile DBGBALSTR _DBGBAL @0x00000127; +#define DBGBAL _DBGBAL.Byte +#define DBGBAL_DBGBA _DBGBAL.Bits.DBGBA + +#define DBGBAL_DBGBA_MASK 255U +#define DBGBAL_DBGBA_BITNUM 0U + + +/*** DBGDCTL - Debug Comparator D Control Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte COMPE :1; /* Determines if comparator is enabled */ + byte :1; + byte RWE :1; /* Read/Write Enable Bit */ + byte RW :1; /* Read/Write Comparator Value Bit */ + byte :1; + byte INST :1; /* Instruction Select */ + byte :1; + byte :1; + } Bits; +} DBGDCTLSTR; +extern volatile DBGDCTLSTR _DBGDCTL @0x00000140; +#define DBGDCTL _DBGDCTL.Byte +#define DBGDCTL_COMPE _DBGDCTL.Bits.COMPE +#define DBGDCTL_RWE _DBGDCTL.Bits.RWE +#define DBGDCTL_RW _DBGDCTL.Bits.RW +#define DBGDCTL_INST _DBGDCTL.Bits.INST + +#define DBGDCTL_COMPE_MASK 1U +#define DBGDCTL_RWE_MASK 4U +#define DBGDCTL_RW_MASK 8U +#define DBGDCTL_INST_MASK 32U + + +/*** DBGDAH - Debug Comparator D Address Register High; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte DBGDA :8; /* Comparator Address Bits */ + } Bits; +} DBGDAHSTR; +extern volatile DBGDAHSTR _DBGDAH @0x00000145; +#define DBGDAH _DBGDAH.Byte +#define DBGDAH_DBGDA _DBGDAH.Bits.DBGDA + +#define DBGDAH_DBGDA_MASK 255U +#define DBGDAH_DBGDA_BITNUM 0U + + +/*** DBGDAM - Debug Comparator D Address Register Middle; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte DBGDA :8; /* Comparator Address Bits */ + } Bits; +} DBGDAMSTR; +extern volatile DBGDAMSTR _DBGDAM @0x00000146; +#define DBGDAM _DBGDAM.Byte +#define DBGDAM_DBGDA _DBGDAM.Bits.DBGDA + +#define DBGDAM_DBGDA_MASK 255U +#define DBGDAM_DBGDA_BITNUM 0U + + +/*** DBGDAL - Debug Comparator D Address Register Low; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte DBGDA :8; /* Comparator Address Bits */ + } Bits; +} DBGDALSTR; +extern volatile DBGDALSTR _DBGDAL @0x00000147; +#define DBGDAL _DBGDAL.Byte +#define DBGDAL_DBGDA _DBGDAL.Bits.DBGDA + +#define DBGDAL_DBGDA_MASK 255U +#define DBGDAL_DBGDA_BITNUM 0U + + +/*** MODRR0 - Module Routing Register 0; 0x00000200 ***/ +typedef union { + byte Byte; + struct { + byte S0L0RR :3; /* SCI0-LINPHY routing */ + byte SCI1RR :1; /* SCI1 routing */ + byte IIC0RR :1; /* IIC0 routing */ + byte :1; + byte :1; + byte :1; + } Bits; +} MODRR0STR; +extern volatile MODRR0STR _MODRR0 @0x00000200; +#define MODRR0 _MODRR0.Byte +#define MODRR0_S0L0RR _MODRR0.Bits.S0L0RR +#define MODRR0_SCI1RR _MODRR0.Bits.SCI1RR +#define MODRR0_IIC0RR _MODRR0.Bits.IIC0RR +/* MODRR_ARR: Access 5 MODRRx registers in an array */ +#define MODRR_ARR ((volatile byte *) &MODRR0) + +#define MODRR0_S0L0RR_MASK 7U +#define MODRR0_S0L0RR_BITNUM 0U +#define MODRR0_SCI1RR_MASK 8U +#define MODRR0_IIC0RR_MASK 16U + + +/*** MODRR1 - Module Routing Register 1; 0x00000201 ***/ +typedef union { + byte Byte; + struct { + byte PWM0RR :1; /* PWM0 routing */ + byte :1; + byte PWM2RR :1; /* PWM2 routing */ + byte :1; + byte PWM4RR :1; /* PWM4 routing */ + byte PWM5RR :1; /* PWM5 routing */ + byte PWM6RR :1; /* PWM6 routing */ + byte PWM7RR :1; /* PWM7 routing */ + } Bits; +} MODRR1STR; +extern volatile MODRR1STR _MODRR1 @0x00000201; +#define MODRR1 _MODRR1.Byte +#define MODRR1_PWM0RR _MODRR1.Bits.PWM0RR +#define MODRR1_PWM2RR _MODRR1.Bits.PWM2RR +#define MODRR1_PWM4RR _MODRR1.Bits.PWM4RR +#define MODRR1_PWM5RR _MODRR1.Bits.PWM5RR +#define MODRR1_PWM6RR _MODRR1.Bits.PWM6RR +#define MODRR1_PWM7RR _MODRR1.Bits.PWM7RR + +#define MODRR1_PWM0RR_MASK 1U +#define MODRR1_PWM2RR_MASK 4U +#define MODRR1_PWM4RR_MASK 16U +#define MODRR1_PWM5RR_MASK 32U +#define MODRR1_PWM6RR_MASK 64U +#define MODRR1_PWM7RR_MASK 128U + + +/*** MODRR2 - Module Routing Register 2; 0x00000202 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte T0C2RR :1; /* IOC0_2 routing */ + byte T0C3RR :1; /* IOC0_3 routing */ + byte T0C4RR :1; /* IOC0_4 routing */ + byte T0C5RR :1; /* IOC0_5 routing */ + byte T1C0RR :1; /* IOC1_0 routing */ + byte T1C1RR :1; /* IOC1_1 routing */ + } Bits; +} MODRR2STR; +extern volatile MODRR2STR _MODRR2 @0x00000202; +#define MODRR2 _MODRR2.Byte +#define MODRR2_T0C2RR _MODRR2.Bits.T0C2RR +#define MODRR2_T0C3RR _MODRR2.Bits.T0C3RR +#define MODRR2_T0C4RR _MODRR2.Bits.T0C4RR +#define MODRR2_T0C5RR _MODRR2.Bits.T0C5RR +#define MODRR2_T1C0RR _MODRR2.Bits.T1C0RR +#define MODRR2_T1C1RR _MODRR2.Bits.T1C1RR + +#define MODRR2_T0C2RR_MASK 4U +#define MODRR2_T0C3RR_MASK 8U +#define MODRR2_T0C4RR_MASK 16U +#define MODRR2_T0C5RR_MASK 32U +#define MODRR2_T1C0RR_MASK 64U +#define MODRR2_T1C1RR_MASK 128U + + +/*** MODRR3 - Module Routing Register 3; 0x00000203 ***/ +typedef union { + byte Byte; + struct { + byte TRIG0RR :2; /* ADC0 Trigger input routing */ + byte TRIG0NEG :1; /* ADC0 Trigger input inverted polarity */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} MODRR3STR; +extern volatile MODRR3STR _MODRR3 @0x00000203; +#define MODRR3 _MODRR3.Byte +#define MODRR3_TRIG0RR _MODRR3.Bits.TRIG0RR +#define MODRR3_TRIG0NEG _MODRR3.Bits.TRIG0NEG + +#define MODRR3_TRIG0RR_MASK 3U +#define MODRR3_TRIG0RR_BITNUM 0U +#define MODRR3_TRIG0NEG_MASK 4U + + +/*** MODRR4 - Module Routing Register 4; 0x00000204 ***/ +typedef union { + byte Byte; + struct { + byte T0IC3RR :2; /* TIM0 IC3 routing */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} MODRR4STR; +extern volatile MODRR4STR _MODRR4 @0x00000204; +#define MODRR4 _MODRR4.Byte +#define MODRR4_T0IC3RR _MODRR4.Bits.T0IC3RR + +#define MODRR4_T0IC3RR_MASK 3U +#define MODRR4_T0IC3RR_BITNUM 0U + + +/*** ECLKCTL - ECLK Control Register; 0x00000208 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte NECLK :1; /* No ECLK */ + } Bits; +} ECLKCTLSTR; +extern volatile ECLKCTLSTR _ECLKCTL @0x00000208; +#define ECLKCTL _ECLKCTL.Byte +#define ECLKCTL_NECLK _ECLKCTL.Bits.NECLK + +#define ECLKCTL_NECLK_MASK 128U + + +/*** IRQCR - Interrupt Control Register; 0x00000209 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} IRQCRSTR; +extern volatile IRQCRSTR _IRQCR @0x00000209; +#define IRQCR _IRQCR.Byte +#define IRQCR_IRQEN _IRQCR.Bits.IRQEN +#define IRQCR_IRQE _IRQCR.Bits.IRQE + +#define IRQCR_IRQEN_MASK 64U +#define IRQCR_IRQE_MASK 128U + + +/*** PTE - Port E Data Register; 0x00000260 ***/ +typedef union { + byte Byte; + struct { + byte PTE0 :1; /* Port E general purpose I/O data 0 */ + byte PTE1 :1; /* Port E general purpose I/O data 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTE :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTESTR; +extern volatile PTESTR _PTE @0x00000260; +#define PTE _PTE.Byte +#define PTE_PTE0 _PTE.Bits.PTE0 +#define PTE_PTE1 _PTE.Bits.PTE1 +#define PTE_PTE _PTE.MergedBits.grpPTE + +#define PTE_PTE0_MASK 1U +#define PTE_PTE1_MASK 2U +#define PTE_PTE_MASK 3U +#define PTE_PTE_BITNUM 0U + + +/*** PTIE - Port E Input Register; 0x00000262 ***/ +typedef union { + byte Byte; + struct { + byte PTIE0 :1; /* Port E data input 0 */ + byte PTIE1 :1; /* Port E data input 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIE :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTIESTR; +extern volatile PTIESTR _PTIE @0x00000262; +#define PTIE _PTIE.Byte +#define PTIE_PTIE0 _PTIE.Bits.PTIE0 +#define PTIE_PTIE1 _PTIE.Bits.PTIE1 +#define PTIE_PTIE _PTIE.MergedBits.grpPTIE + +#define PTIE_PTIE0_MASK 1U +#define PTIE_PTIE1_MASK 2U +#define PTIE_PTIE_MASK 3U +#define PTIE_PTIE_BITNUM 0U + + +/*** DDRE - Port E Data Direction Register; 0x00000264 ***/ +typedef union { + byte Byte; + struct { + byte DDRE0 :1; /* Port E data direction select 0 */ + byte DDRE1 :1; /* Port E data direction select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRE :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @0x00000264; +#define DDRE _DDRE.Byte +#define DDRE_DDRE0 _DDRE.Bits.DDRE0 +#define DDRE_DDRE1 _DDRE.Bits.DDRE1 +#define DDRE_DDRE _DDRE.MergedBits.grpDDRE + +#define DDRE_DDRE0_MASK 1U +#define DDRE_DDRE1_MASK 2U +#define DDRE_DDRE_MASK 3U +#define DDRE_DDRE_BITNUM 0U + + +/*** PERE - Port E Pull Device Enable Register; 0x00000266 ***/ +typedef union { + byte Byte; + struct { + byte PERE0 :1; /* Port E pull device enable 0 */ + byte PERE1 :1; /* Port E pull device enable 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERE :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PERESTR; +extern volatile PERESTR _PERE @0x00000266; +#define PERE _PERE.Byte +#define PERE_PERE0 _PERE.Bits.PERE0 +#define PERE_PERE1 _PERE.Bits.PERE1 +#define PERE_PERE _PERE.MergedBits.grpPERE + +#define PERE_PERE0_MASK 1U +#define PERE_PERE1_MASK 2U +#define PERE_PERE_MASK 3U +#define PERE_PERE_BITNUM 0U + + +/*** PPSE - Port E Polarity Select Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte PPSE0 :1; /* Port E pull polarity select 0 */ + byte PPSE1 :1; /* Port E pull polarity select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSE :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PPSESTR; +extern volatile PPSESTR _PPSE @0x00000268; +#define PPSE _PPSE.Byte +#define PPSE_PPSE0 _PPSE.Bits.PPSE0 +#define PPSE_PPSE1 _PPSE.Bits.PPSE1 +#define PPSE_PPSE _PPSE.MergedBits.grpPPSE + +#define PPSE_PPSE0_MASK 1U +#define PPSE_PPSE1_MASK 2U +#define PPSE_PPSE_MASK 3U +#define PPSE_PPSE_BITNUM 0U + + +/*** PTAD - Port AD Data Register; 0x00000280 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PTADH - Port ADH Data Register; 0x00000280 ***/ + union { + byte Byte; + struct { + byte PTADH0 :1; /* Port ADH general purpose I/O data 0 */ + byte PTADH1 :1; /* Port ADH general purpose I/O data 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PTADHSTR; + #define PTADH _PTAD.Overlap_STR.PTADHSTR.Byte + #define PTADH_PTADH0 _PTAD.Overlap_STR.PTADHSTR.Bits.PTADH0 + #define PTADH_PTADH1 _PTAD.Overlap_STR.PTADHSTR.Bits.PTADH1 + #define PTADH_PTADH _PTAD.Overlap_STR.PTADHSTR.MergedBits.grpPTADH + + #define PTADH_PTADH0_MASK 1U + #define PTADH_PTADH1_MASK 2U + #define PTADH_PTADH_MASK 3U + #define PTADH_PTADH_BITNUM 0U + + + /*** PTADL - Port ADL Data Register; 0x00000281 ***/ + union { + byte Byte; + struct { + byte PTADL0 :1; /* Port ADL general purpose I/O data 0 */ + byte PTADL1 :1; /* Port ADL general purpose I/O data 1 */ + byte PTADL2 :1; /* Port ADL general purpose I/O data 2 */ + byte PTADL3 :1; /* Port ADL general purpose I/O data 3 */ + byte PTADL4 :1; /* Port ADL general purpose I/O data 4 */ + byte PTADL5 :1; /* Port ADL general purpose I/O data 5 */ + byte PTADL6 :1; /* Port ADL general purpose I/O data 6 */ + byte PTADL7 :1; /* Port ADL general purpose I/O data 7 */ + } Bits; + } PTADLSTR; + #define PTADL _PTAD.Overlap_STR.PTADLSTR.Byte + #define PTADL_PTADL0 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL0 + #define PTADL_PTADL1 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL1 + #define PTADL_PTADL2 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL2 + #define PTADL_PTADL3 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL3 + #define PTADL_PTADL4 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL4 + #define PTADL_PTADL5 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL5 + #define PTADL_PTADL6 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL6 + #define PTADL_PTADL7 _PTAD.Overlap_STR.PTADLSTR.Bits.PTADL7 + + #define PTADL_PTADL0_MASK 1U + #define PTADL_PTADL1_MASK 2U + #define PTADL_PTADL2_MASK 4U + #define PTADL_PTADL3_MASK 8U + #define PTADL_PTADL4_MASK 16U + #define PTADL_PTADL5_MASK 32U + #define PTADL_PTADL6_MASK 64U + #define PTADL_PTADL7_MASK 128U + + } Overlap_STR; + + struct { + word PTADL0 :1; /* Port AD general purpose I/O data 0 */ + word PTADL1 :1; /* Port AD general purpose I/O data 1 */ + word PTADL2 :1; /* Port AD general purpose I/O data 2 */ + word PTADL3 :1; /* Port AD general purpose I/O data 3 */ + word PTADL4 :1; /* Port AD general purpose I/O data 4 */ + word PTADL5 :1; /* Port AD general purpose I/O data 5 */ + word PTADL6 :1; /* Port AD general purpose I/O data 6 */ + word PTADL7 :1; /* Port AD general purpose I/O data 7 */ + word PTADH0 :1; /* Port AD general purpose I/O data 8 */ + word PTADH1 :1; /* Port AD general purpose I/O data 9 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPTADL :8; + word grpPTADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PTADSTR; +extern volatile PTADSTR _PTAD @0x00000280; +#define PTAD _PTAD.Word +#define PTAD_PTADL0 _PTAD.Bits.PTADL0 +#define PTAD_PTADL1 _PTAD.Bits.PTADL1 +#define PTAD_PTADL2 _PTAD.Bits.PTADL2 +#define PTAD_PTADL3 _PTAD.Bits.PTADL3 +#define PTAD_PTADL4 _PTAD.Bits.PTADL4 +#define PTAD_PTADL5 _PTAD.Bits.PTADL5 +#define PTAD_PTADL6 _PTAD.Bits.PTADL6 +#define PTAD_PTADL7 _PTAD.Bits.PTADL7 +#define PTAD_PTADH0 _PTAD.Bits.PTADH0 +#define PTAD_PTADH1 _PTAD.Bits.PTADH1 +#define PTAD_PTADL _PTAD.MergedBits.grpPTADL +#define PTAD_PTADH _PTAD.MergedBits.grpPTADH + +#define PTAD_PTADL0_MASK 1U +#define PTAD_PTADL1_MASK 2U +#define PTAD_PTADL2_MASK 4U +#define PTAD_PTADL3_MASK 8U +#define PTAD_PTADL4_MASK 16U +#define PTAD_PTADL5_MASK 32U +#define PTAD_PTADL6_MASK 64U +#define PTAD_PTADL7_MASK 128U +#define PTAD_PTADH0_MASK 256U +#define PTAD_PTADH1_MASK 512U +#define PTAD_PTADL_MASK 255U +#define PTAD_PTADL_BITNUM 0U +#define PTAD_PTADH_MASK 768U +#define PTAD_PTADH_BITNUM 8U + + +/*** PTIAD - Port AD Input Register; 0x00000282 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PTIADH - Port ADH Input Register; 0x00000282 ***/ + union { + byte Byte; + struct { + byte PTIADH0 :1; /* Port ADH data input 0 */ + byte PTIADH1 :1; /* Port ADH data input 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PTIADHSTR; + #define PTIADH _PTIAD.Overlap_STR.PTIADHSTR.Byte + #define PTIADH_PTIADH0 _PTIAD.Overlap_STR.PTIADHSTR.Bits.PTIADH0 + #define PTIADH_PTIADH1 _PTIAD.Overlap_STR.PTIADHSTR.Bits.PTIADH1 + #define PTIADH_PTIADH _PTIAD.Overlap_STR.PTIADHSTR.MergedBits.grpPTIADH + + #define PTIADH_PTIADH0_MASK 1U + #define PTIADH_PTIADH1_MASK 2U + #define PTIADH_PTIADH_MASK 3U + #define PTIADH_PTIADH_BITNUM 0U + + + /*** PTIADL - Port ADL Input Register; 0x00000283 ***/ + union { + byte Byte; + struct { + byte PTIADL0 :1; /* Port ADL data input 0 */ + byte PTIADL1 :1; /* Port ADL data input 1 */ + byte PTIADL2 :1; /* Port ADL data input 2 */ + byte PTIADL3 :1; /* Port ADL data input 3 */ + byte PTIADL4 :1; /* Port ADL data input 4 */ + byte PTIADL5 :1; /* Port ADL data input 5 */ + byte PTIADL6 :1; /* Port ADL data input 6 */ + byte PTIADL7 :1; /* Port ADL data input 7 */ + } Bits; + } PTIADLSTR; + #define PTIADL _PTIAD.Overlap_STR.PTIADLSTR.Byte + #define PTIADL_PTIADL0 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL0 + #define PTIADL_PTIADL1 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL1 + #define PTIADL_PTIADL2 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL2 + #define PTIADL_PTIADL3 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL3 + #define PTIADL_PTIADL4 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL4 + #define PTIADL_PTIADL5 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL5 + #define PTIADL_PTIADL6 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL6 + #define PTIADL_PTIADL7 _PTIAD.Overlap_STR.PTIADLSTR.Bits.PTIADL7 + + #define PTIADL_PTIADL0_MASK 1U + #define PTIADL_PTIADL1_MASK 2U + #define PTIADL_PTIADL2_MASK 4U + #define PTIADL_PTIADL3_MASK 8U + #define PTIADL_PTIADL4_MASK 16U + #define PTIADL_PTIADL5_MASK 32U + #define PTIADL_PTIADL6_MASK 64U + #define PTIADL_PTIADL7_MASK 128U + + } Overlap_STR; + + struct { + word PTIADL0 :1; /* Port AD data input 0 */ + word PTIADL1 :1; /* Port AD data input 1 */ + word PTIADL2 :1; /* Port AD data input 2 */ + word PTIADL3 :1; /* Port AD data input 3 */ + word PTIADL4 :1; /* Port AD data input 4 */ + word PTIADL5 :1; /* Port AD data input 5 */ + word PTIADL6 :1; /* Port AD data input 6 */ + word PTIADL7 :1; /* Port AD data input 7 */ + word PTIADH0 :1; /* Port AD data input 0 */ + word PTIADH1 :1; /* Port AD data input 1 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPTIADL :8; + word grpPTIADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PTIADSTR; +extern volatile PTIADSTR _PTIAD @0x00000282; +#define PTIAD _PTIAD.Word +#define PTIAD_PTIADL0 _PTIAD.Bits.PTIADL0 +#define PTIAD_PTIADL1 _PTIAD.Bits.PTIADL1 +#define PTIAD_PTIADL2 _PTIAD.Bits.PTIADL2 +#define PTIAD_PTIADL3 _PTIAD.Bits.PTIADL3 +#define PTIAD_PTIADL4 _PTIAD.Bits.PTIADL4 +#define PTIAD_PTIADL5 _PTIAD.Bits.PTIADL5 +#define PTIAD_PTIADL6 _PTIAD.Bits.PTIADL6 +#define PTIAD_PTIADL7 _PTIAD.Bits.PTIADL7 +#define PTIAD_PTIADH0 _PTIAD.Bits.PTIADH0 +#define PTIAD_PTIADH1 _PTIAD.Bits.PTIADH1 +#define PTIAD_PTIADL _PTIAD.MergedBits.grpPTIADL +#define PTIAD_PTIADH _PTIAD.MergedBits.grpPTIADH + +#define PTIAD_PTIADL0_MASK 1U +#define PTIAD_PTIADL1_MASK 2U +#define PTIAD_PTIADL2_MASK 4U +#define PTIAD_PTIADL3_MASK 8U +#define PTIAD_PTIADL4_MASK 16U +#define PTIAD_PTIADL5_MASK 32U +#define PTIAD_PTIADL6_MASK 64U +#define PTIAD_PTIADL7_MASK 128U +#define PTIAD_PTIADH0_MASK 256U +#define PTIAD_PTIADH1_MASK 512U +#define PTIAD_PTIADL_MASK 255U +#define PTIAD_PTIADL_BITNUM 0U +#define PTIAD_PTIADH_MASK 768U +#define PTIAD_PTIADH_BITNUM 8U + + +/*** DDRAD - Port AD Data Direction Register; 0x00000284 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRADH - Port ADH Data Direction Register; 0x00000284 ***/ + union { + byte Byte; + struct { + byte DDRADH0 :1; /* Port ADH data direction select 0 */ + byte DDRADH1 :1; /* Port ADH data direction select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } DDRADHSTR; + #define DDRADH _DDRAD.Overlap_STR.DDRADHSTR.Byte + #define DDRADH_DDRADH0 _DDRAD.Overlap_STR.DDRADHSTR.Bits.DDRADH0 + #define DDRADH_DDRADH1 _DDRAD.Overlap_STR.DDRADHSTR.Bits.DDRADH1 + #define DDRADH_DDRADH _DDRAD.Overlap_STR.DDRADHSTR.MergedBits.grpDDRADH + + #define DDRADH_DDRADH0_MASK 1U + #define DDRADH_DDRADH1_MASK 2U + #define DDRADH_DDRADH_MASK 3U + #define DDRADH_DDRADH_BITNUM 0U + + + /*** DDRADL - Port ADL Data Direction Register; 0x00000285 ***/ + union { + byte Byte; + struct { + byte DDRADL0 :1; /* Port ADL data direction select 0 */ + byte DDRADL1 :1; /* Port ADL data direction select 1 */ + byte DDRADL2 :1; /* Port ADL data direction select 2 */ + byte DDRADL3 :1; /* Port ADL data direction select 3 */ + byte DDRADL4 :1; /* Port ADL data direction select 4 */ + byte DDRADL5 :1; /* Port ADL data direction select 5 */ + byte DDRADL6 :1; /* Port ADL data direction select 6 */ + byte DDRADL7 :1; /* Port ADL data direction select 7 */ + } Bits; + } DDRADLSTR; + #define DDRADL _DDRAD.Overlap_STR.DDRADLSTR.Byte + #define DDRADL_DDRADL0 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL0 + #define DDRADL_DDRADL1 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL1 + #define DDRADL_DDRADL2 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL2 + #define DDRADL_DDRADL3 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL3 + #define DDRADL_DDRADL4 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL4 + #define DDRADL_DDRADL5 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL5 + #define DDRADL_DDRADL6 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL6 + #define DDRADL_DDRADL7 _DDRAD.Overlap_STR.DDRADLSTR.Bits.DDRADL7 + + #define DDRADL_DDRADL0_MASK 1U + #define DDRADL_DDRADL1_MASK 2U + #define DDRADL_DDRADL2_MASK 4U + #define DDRADL_DDRADL3_MASK 8U + #define DDRADL_DDRADL4_MASK 16U + #define DDRADL_DDRADL5_MASK 32U + #define DDRADL_DDRADL6_MASK 64U + #define DDRADL_DDRADL7_MASK 128U + + } Overlap_STR; + + struct { + word DDRADL0 :1; /* Port AD data direction select 0 */ + word DDRADL1 :1; /* Port AD data direction select 1 */ + word DDRADL2 :1; /* Port AD data direction select 2 */ + word DDRADL3 :1; /* Port AD data direction select 3 */ + word DDRADL4 :1; /* Port AD data direction select 4 */ + word DDRADL5 :1; /* Port AD data direction select 5 */ + word DDRADL6 :1; /* Port AD data direction select 6 */ + word DDRADL7 :1; /* Port AD data direction select 7 */ + word DDRADH0 :1; /* Port AD data direction select 8 */ + word DDRADH1 :1; /* Port AD data direction select 9 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpDDRADL :8; + word grpDDRADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} DDRADSTR; +extern volatile DDRADSTR _DDRAD @0x00000284; +#define DDRAD _DDRAD.Word +#define DDRAD_DDRADL0 _DDRAD.Bits.DDRADL0 +#define DDRAD_DDRADL1 _DDRAD.Bits.DDRADL1 +#define DDRAD_DDRADL2 _DDRAD.Bits.DDRADL2 +#define DDRAD_DDRADL3 _DDRAD.Bits.DDRADL3 +#define DDRAD_DDRADL4 _DDRAD.Bits.DDRADL4 +#define DDRAD_DDRADL5 _DDRAD.Bits.DDRADL5 +#define DDRAD_DDRADL6 _DDRAD.Bits.DDRADL6 +#define DDRAD_DDRADL7 _DDRAD.Bits.DDRADL7 +#define DDRAD_DDRADH0 _DDRAD.Bits.DDRADH0 +#define DDRAD_DDRADH1 _DDRAD.Bits.DDRADH1 +#define DDRAD_DDRADL _DDRAD.MergedBits.grpDDRADL +#define DDRAD_DDRADH _DDRAD.MergedBits.grpDDRADH + +#define DDRAD_DDRADL0_MASK 1U +#define DDRAD_DDRADL1_MASK 2U +#define DDRAD_DDRADL2_MASK 4U +#define DDRAD_DDRADL3_MASK 8U +#define DDRAD_DDRADL4_MASK 16U +#define DDRAD_DDRADL5_MASK 32U +#define DDRAD_DDRADL6_MASK 64U +#define DDRAD_DDRADL7_MASK 128U +#define DDRAD_DDRADH0_MASK 256U +#define DDRAD_DDRADH1_MASK 512U +#define DDRAD_DDRADL_MASK 255U +#define DDRAD_DDRADL_BITNUM 0U +#define DDRAD_DDRADH_MASK 768U +#define DDRAD_DDRADH_BITNUM 8U + + +/*** PERAD - Port AD Pull Up Enable Register; 0x00000286 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PERADH - Port ADH Pull Device Enable Register; 0x00000286 ***/ + union { + byte Byte; + struct { + byte PERADH0 :1; /* Port ADH pull device enable 0 */ + byte PERADH1 :1; /* Port ADH pull device enable 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PERADHSTR; + #define PERADH _PERAD.Overlap_STR.PERADHSTR.Byte + #define PERADH_PERADH0 _PERAD.Overlap_STR.PERADHSTR.Bits.PERADH0 + #define PERADH_PERADH1 _PERAD.Overlap_STR.PERADHSTR.Bits.PERADH1 + #define PERADH_PERADH _PERAD.Overlap_STR.PERADHSTR.MergedBits.grpPERADH + + #define PERADH_PERADH0_MASK 1U + #define PERADH_PERADH1_MASK 2U + #define PERADH_PERADH_MASK 3U + #define PERADH_PERADH_BITNUM 0U + + + /*** PERADL - Port ADL Pull Device Enable Register; 0x00000287 ***/ + union { + byte Byte; + struct { + byte PERADL0 :1; /* Port ADL pull device enable 0 */ + byte PERADL1 :1; /* Port ADL pull device enable 1 */ + byte PERADL2 :1; /* Port ADL pull device enable 2 */ + byte PERADL3 :1; /* Port ADL pull device enable 3 */ + byte PERADL4 :1; /* Port ADL pull device enable 4 */ + byte PERADL5 :1; /* Port ADL pull device enable 5 */ + byte PERADL6 :1; /* Port ADL pull device enable 6 */ + byte PERADL7 :1; /* Port ADL pull device enable 7 */ + } Bits; + } PERADLSTR; + #define PERADL _PERAD.Overlap_STR.PERADLSTR.Byte + #define PERADL_PERADL0 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL0 + #define PERADL_PERADL1 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL1 + #define PERADL_PERADL2 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL2 + #define PERADL_PERADL3 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL3 + #define PERADL_PERADL4 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL4 + #define PERADL_PERADL5 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL5 + #define PERADL_PERADL6 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL6 + #define PERADL_PERADL7 _PERAD.Overlap_STR.PERADLSTR.Bits.PERADL7 + + #define PERADL_PERADL0_MASK 1U + #define PERADL_PERADL1_MASK 2U + #define PERADL_PERADL2_MASK 4U + #define PERADL_PERADL3_MASK 8U + #define PERADL_PERADL4_MASK 16U + #define PERADL_PERADL5_MASK 32U + #define PERADL_PERADL6_MASK 64U + #define PERADL_PERADL7_MASK 128U + + } Overlap_STR; + + struct { + word PERADL0 :1; /* Port AD pull device enable 0 */ + word PERADL1 :1; /* Port AD pull device enable 1 */ + word PERADL2 :1; /* Port AD pull device enable 2 */ + word PERADL3 :1; /* Port AD pull device enable 3 */ + word PERADL4 :1; /* Port AD pull device enable 4 */ + word PERADL5 :1; /* Port AD pull device enable 5 */ + word PERADL6 :1; /* Port AD pull device enable 6 */ + word PERADL7 :1; /* Port AD pull device enable 7 */ + word PERADH0 :1; /* Port AD pull device enable 8 */ + word PERADH1 :1; /* Port AD pull device enable 9 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPERADL :8; + word grpPERADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PERADSTR; +extern volatile PERADSTR _PERAD @0x00000286; +#define PERAD _PERAD.Word +#define PERAD_PERADL0 _PERAD.Bits.PERADL0 +#define PERAD_PERADL1 _PERAD.Bits.PERADL1 +#define PERAD_PERADL2 _PERAD.Bits.PERADL2 +#define PERAD_PERADL3 _PERAD.Bits.PERADL3 +#define PERAD_PERADL4 _PERAD.Bits.PERADL4 +#define PERAD_PERADL5 _PERAD.Bits.PERADL5 +#define PERAD_PERADL6 _PERAD.Bits.PERADL6 +#define PERAD_PERADL7 _PERAD.Bits.PERADL7 +#define PERAD_PERADH0 _PERAD.Bits.PERADH0 +#define PERAD_PERADH1 _PERAD.Bits.PERADH1 +#define PERAD_PERADL _PERAD.MergedBits.grpPERADL +#define PERAD_PERADH _PERAD.MergedBits.grpPERADH + +#define PERAD_PERADL0_MASK 1U +#define PERAD_PERADL1_MASK 2U +#define PERAD_PERADL2_MASK 4U +#define PERAD_PERADL3_MASK 8U +#define PERAD_PERADL4_MASK 16U +#define PERAD_PERADL5_MASK 32U +#define PERAD_PERADL6_MASK 64U +#define PERAD_PERADL7_MASK 128U +#define PERAD_PERADH0_MASK 256U +#define PERAD_PERADH1_MASK 512U +#define PERAD_PERADL_MASK 255U +#define PERAD_PERADL_BITNUM 0U +#define PERAD_PERADH_MASK 768U +#define PERAD_PERADH_BITNUM 8U + + +/*** PPSAD - Port AD Polarity Select Register; 0x00000288 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PPSADH - Port ADH Polarity Select Register; 0x00000288 ***/ + union { + byte Byte; + struct { + byte PPSADH0 :1; /* Port ADH pull polarity select 0 */ + byte PPSADH1 :1; /* Port ADH pull polarity select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PPSADHSTR; + #define PPSADH _PPSAD.Overlap_STR.PPSADHSTR.Byte + #define PPSADH_PPSADH0 _PPSAD.Overlap_STR.PPSADHSTR.Bits.PPSADH0 + #define PPSADH_PPSADH1 _PPSAD.Overlap_STR.PPSADHSTR.Bits.PPSADH1 + #define PPSADH_PPSADH _PPSAD.Overlap_STR.PPSADHSTR.MergedBits.grpPPSADH + + #define PPSADH_PPSADH0_MASK 1U + #define PPSADH_PPSADH1_MASK 2U + #define PPSADH_PPSADH_MASK 3U + #define PPSADH_PPSADH_BITNUM 0U + + + /*** PPSADL - Port ADL Polarity Select Register; 0x00000289 ***/ + union { + byte Byte; + struct { + byte PPSADL0 :1; /* Port ADL pull polarity select 0 */ + byte PPSADL1 :1; /* Port ADL pull polarity select 1 */ + byte PPSADL2 :1; /* Port ADL pull polarity select 2 */ + byte PPSADL3 :1; /* Port ADL pull polarity select 3 */ + byte PPSADL4 :1; /* Port ADL pull polarity select 4 */ + byte PPSADL5 :1; /* Port ADL pull polarity select 5 */ + byte PPSADL6 :1; /* Port ADL pull polarity select 6 */ + byte PPSADL7 :1; /* Port ADL pull polarity select 7 */ + } Bits; + } PPSADLSTR; + #define PPSADL _PPSAD.Overlap_STR.PPSADLSTR.Byte + #define PPSADL_PPSADL0 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL0 + #define PPSADL_PPSADL1 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL1 + #define PPSADL_PPSADL2 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL2 + #define PPSADL_PPSADL3 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL3 + #define PPSADL_PPSADL4 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL4 + #define PPSADL_PPSADL5 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL5 + #define PPSADL_PPSADL6 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL6 + #define PPSADL_PPSADL7 _PPSAD.Overlap_STR.PPSADLSTR.Bits.PPSADL7 + + #define PPSADL_PPSADL0_MASK 1U + #define PPSADL_PPSADL1_MASK 2U + #define PPSADL_PPSADL2_MASK 4U + #define PPSADL_PPSADL3_MASK 8U + #define PPSADL_PPSADL4_MASK 16U + #define PPSADL_PPSADL5_MASK 32U + #define PPSADL_PPSADL6_MASK 64U + #define PPSADL_PPSADL7_MASK 128U + + } Overlap_STR; + + struct { + word PPSADL0 :1; /* Port AD pull polarity select 0 */ + word PPSADL1 :1; /* Port AD pull polarity select 1 */ + word PPSADL2 :1; /* Port AD pull polarity select 2 */ + word PPSADL3 :1; /* Port AD pull polarity select 3 */ + word PPSADL4 :1; /* Port AD pull polarity select 4 */ + word PPSADL5 :1; /* Port AD pull polarity select 5 */ + word PPSADL6 :1; /* Port AD pull polarity select 6 */ + word PPSADL7 :1; /* Port AD pull polarity select 7 */ + word PPSADH0 :1; /* Port AD pull polarity select 0 */ + word PPSADH1 :1; /* Port AD pull polarity select 1 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPPSADL :8; + word grpPPSADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PPSADSTR; +extern volatile PPSADSTR _PPSAD @0x00000288; +#define PPSAD _PPSAD.Word +#define PPSAD_PPSADL0 _PPSAD.Bits.PPSADL0 +#define PPSAD_PPSADL1 _PPSAD.Bits.PPSADL1 +#define PPSAD_PPSADL2 _PPSAD.Bits.PPSADL2 +#define PPSAD_PPSADL3 _PPSAD.Bits.PPSADL3 +#define PPSAD_PPSADL4 _PPSAD.Bits.PPSADL4 +#define PPSAD_PPSADL5 _PPSAD.Bits.PPSADL5 +#define PPSAD_PPSADL6 _PPSAD.Bits.PPSADL6 +#define PPSAD_PPSADL7 _PPSAD.Bits.PPSADL7 +#define PPSAD_PPSADH0 _PPSAD.Bits.PPSADH0 +#define PPSAD_PPSADH1 _PPSAD.Bits.PPSADH1 +#define PPSAD_PPSADL _PPSAD.MergedBits.grpPPSADL +#define PPSAD_PPSADH _PPSAD.MergedBits.grpPPSADH + +#define PPSAD_PPSADL0_MASK 1U +#define PPSAD_PPSADL1_MASK 2U +#define PPSAD_PPSADL2_MASK 4U +#define PPSAD_PPSADL3_MASK 8U +#define PPSAD_PPSADL4_MASK 16U +#define PPSAD_PPSADL5_MASK 32U +#define PPSAD_PPSADL6_MASK 64U +#define PPSAD_PPSADL7_MASK 128U +#define PPSAD_PPSADH0_MASK 256U +#define PPSAD_PPSADH1_MASK 512U +#define PPSAD_PPSADL_MASK 255U +#define PPSAD_PPSADL_BITNUM 0U +#define PPSAD_PPSADH_MASK 768U +#define PPSAD_PPSADH_BITNUM 8U + + +/*** PIEAD - Port AD Interrupt Enable Register; 0x0000028C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PIEADH - Port ADH Interrupt Enable Register; 0x0000028C ***/ + union { + byte Byte; + struct { + byte PIEADH0 :1; /* Port ADH interrupt enable 0 */ + byte PIEADH1 :1; /* Port ADH interrupt enable 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPIEADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PIEADHSTR; + #define PIEADH _PIEAD.Overlap_STR.PIEADHSTR.Byte + #define PIEADH_PIEADH0 _PIEAD.Overlap_STR.PIEADHSTR.Bits.PIEADH0 + #define PIEADH_PIEADH1 _PIEAD.Overlap_STR.PIEADHSTR.Bits.PIEADH1 + #define PIEADH_PIEADH _PIEAD.Overlap_STR.PIEADHSTR.MergedBits.grpPIEADH + + #define PIEADH_PIEADH0_MASK 1U + #define PIEADH_PIEADH1_MASK 2U + #define PIEADH_PIEADH_MASK 3U + #define PIEADH_PIEADH_BITNUM 0U + + + /*** PIEADL - Port ADL Interrupt Enable Register; 0x0000028D ***/ + union { + byte Byte; + struct { + byte PIEADL0 :1; /* Port ADL interrupt enable 0 */ + byte PIEADL1 :1; /* Port ADL interrupt enable 1 */ + byte PIEADL2 :1; /* Port ADL interrupt enable 2 */ + byte PIEADL3 :1; /* Port ADL interrupt enable 3 */ + byte PIEADL4 :1; /* Port ADL interrupt enable 4 */ + byte PIEADL5 :1; /* Port ADL interrupt enable 5 */ + byte PIEADL6 :1; /* Port ADL interrupt enable 6 */ + byte PIEADL7 :1; /* Port ADL interrupt enable 7 */ + } Bits; + } PIEADLSTR; + #define PIEADL _PIEAD.Overlap_STR.PIEADLSTR.Byte + #define PIEADL_PIEADL0 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL0 + #define PIEADL_PIEADL1 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL1 + #define PIEADL_PIEADL2 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL2 + #define PIEADL_PIEADL3 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL3 + #define PIEADL_PIEADL4 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL4 + #define PIEADL_PIEADL5 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL5 + #define PIEADL_PIEADL6 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL6 + #define PIEADL_PIEADL7 _PIEAD.Overlap_STR.PIEADLSTR.Bits.PIEADL7 + + #define PIEADL_PIEADL0_MASK 1U + #define PIEADL_PIEADL1_MASK 2U + #define PIEADL_PIEADL2_MASK 4U + #define PIEADL_PIEADL3_MASK 8U + #define PIEADL_PIEADL4_MASK 16U + #define PIEADL_PIEADL5_MASK 32U + #define PIEADL_PIEADL6_MASK 64U + #define PIEADL_PIEADL7_MASK 128U + + } Overlap_STR; + + struct { + word PIEADL0 :1; /* Port AD interrupt enable 0 */ + word PIEADL1 :1; /* Port AD interrupt enable 1 */ + word PIEADL2 :1; /* Port AD interrupt enable 2 */ + word PIEADL3 :1; /* Port AD interrupt enable 3 */ + word PIEADL4 :1; /* Port AD interrupt enable 4 */ + word PIEADL5 :1; /* Port AD interrupt enable 5 */ + word PIEADL6 :1; /* Port AD interrupt enable 6 */ + word PIEADL7 :1; /* Port AD interrupt enable 7 */ + word PIEADH0 :1; /* Port AD interrupt enable 0 */ + word PIEADH1 :1; /* Port AD interrupt enable 1 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPIEADL :8; + word grpPIEADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PIEADSTR; +extern volatile PIEADSTR _PIEAD @0x0000028C; +#define PIEAD _PIEAD.Word +#define PIEAD_PIEADL0 _PIEAD.Bits.PIEADL0 +#define PIEAD_PIEADL1 _PIEAD.Bits.PIEADL1 +#define PIEAD_PIEADL2 _PIEAD.Bits.PIEADL2 +#define PIEAD_PIEADL3 _PIEAD.Bits.PIEADL3 +#define PIEAD_PIEADL4 _PIEAD.Bits.PIEADL4 +#define PIEAD_PIEADL5 _PIEAD.Bits.PIEADL5 +#define PIEAD_PIEADL6 _PIEAD.Bits.PIEADL6 +#define PIEAD_PIEADL7 _PIEAD.Bits.PIEADL7 +#define PIEAD_PIEADH0 _PIEAD.Bits.PIEADH0 +#define PIEAD_PIEADH1 _PIEAD.Bits.PIEADH1 +#define PIEAD_PIEADL _PIEAD.MergedBits.grpPIEADL +#define PIEAD_PIEADH _PIEAD.MergedBits.grpPIEADH + +#define PIEAD_PIEADL0_MASK 1U +#define PIEAD_PIEADL1_MASK 2U +#define PIEAD_PIEADL2_MASK 4U +#define PIEAD_PIEADL3_MASK 8U +#define PIEAD_PIEADL4_MASK 16U +#define PIEAD_PIEADL5_MASK 32U +#define PIEAD_PIEADL6_MASK 64U +#define PIEAD_PIEADL7_MASK 128U +#define PIEAD_PIEADH0_MASK 256U +#define PIEAD_PIEADH1_MASK 512U +#define PIEAD_PIEADL_MASK 255U +#define PIEAD_PIEADL_BITNUM 0U +#define PIEAD_PIEADH_MASK 768U +#define PIEAD_PIEADH_BITNUM 8U + + +/*** PIFAD - Port AD Interrupt Flag Register; 0x0000028E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PIFADH - Port ADH Interrupt Flag Register; 0x0000028E ***/ + union { + byte Byte; + struct { + byte PIFADH0 :1; /* Port ADH interrupt flag 0 */ + byte PIFADH1 :1; /* Port ADH interrupt flag 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPIFADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } PIFADHSTR; + #define PIFADH _PIFAD.Overlap_STR.PIFADHSTR.Byte + #define PIFADH_PIFADH0 _PIFAD.Overlap_STR.PIFADHSTR.Bits.PIFADH0 + #define PIFADH_PIFADH1 _PIFAD.Overlap_STR.PIFADHSTR.Bits.PIFADH1 + #define PIFADH_PIFADH _PIFAD.Overlap_STR.PIFADHSTR.MergedBits.grpPIFADH + + #define PIFADH_PIFADH0_MASK 1U + #define PIFADH_PIFADH1_MASK 2U + #define PIFADH_PIFADH_MASK 3U + #define PIFADH_PIFADH_BITNUM 0U + + + /*** PIFADL - Port ADL Interrupt Flag Register; 0x0000028F ***/ + union { + byte Byte; + struct { + byte PIFADL0 :1; /* Port ADL interrupt flag 0 */ + byte PIFADL1 :1; /* Port ADL interrupt flag 1 */ + byte PIFADL2 :1; /* Port ADL interrupt flag 2 */ + byte PIFADL3 :1; /* Port ADL interrupt flag 3 */ + byte PIFADL4 :1; /* Port ADL interrupt flag 4 */ + byte PIFADL5 :1; /* Port ADL interrupt flag 5 */ + byte PIFADL6 :1; /* Port ADL interrupt flag 6 */ + byte PIFADL7 :1; /* Port ADL interrupt flag 7 */ + } Bits; + } PIFADLSTR; + #define PIFADL _PIFAD.Overlap_STR.PIFADLSTR.Byte + #define PIFADL_PIFADL0 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL0 + #define PIFADL_PIFADL1 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL1 + #define PIFADL_PIFADL2 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL2 + #define PIFADL_PIFADL3 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL3 + #define PIFADL_PIFADL4 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL4 + #define PIFADL_PIFADL5 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL5 + #define PIFADL_PIFADL6 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL6 + #define PIFADL_PIFADL7 _PIFAD.Overlap_STR.PIFADLSTR.Bits.PIFADL7 + + #define PIFADL_PIFADL0_MASK 1U + #define PIFADL_PIFADL1_MASK 2U + #define PIFADL_PIFADL2_MASK 4U + #define PIFADL_PIFADL3_MASK 8U + #define PIFADL_PIFADL4_MASK 16U + #define PIFADL_PIFADL5_MASK 32U + #define PIFADL_PIFADL6_MASK 64U + #define PIFADL_PIFADL7_MASK 128U + + } Overlap_STR; + + struct { + word PIFADL0 :1; /* Port AD interrupt flag 0 */ + word PIFADL1 :1; /* Port AD interrupt flag 1 */ + word PIFADL2 :1; /* Port AD interrupt flag 2 */ + word PIFADL3 :1; /* Port AD interrupt flag 3 */ + word PIFADL4 :1; /* Port AD interrupt flag 4 */ + word PIFADL5 :1; /* Port AD interrupt flag 5 */ + word PIFADL6 :1; /* Port AD interrupt flag 6 */ + word PIFADL7 :1; /* Port AD interrupt flag 7 */ + word PIFADH0 :1; /* Port AD interrupt flag 0 */ + word PIFADH1 :1; /* Port AD interrupt flag 1 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpPIFADL :8; + word grpPIFADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} PIFADSTR; +extern volatile PIFADSTR _PIFAD @0x0000028E; +#define PIFAD _PIFAD.Word +#define PIFAD_PIFADL0 _PIFAD.Bits.PIFADL0 +#define PIFAD_PIFADL1 _PIFAD.Bits.PIFADL1 +#define PIFAD_PIFADL2 _PIFAD.Bits.PIFADL2 +#define PIFAD_PIFADL3 _PIFAD.Bits.PIFADL3 +#define PIFAD_PIFADL4 _PIFAD.Bits.PIFADL4 +#define PIFAD_PIFADL5 _PIFAD.Bits.PIFADL5 +#define PIFAD_PIFADL6 _PIFAD.Bits.PIFADL6 +#define PIFAD_PIFADL7 _PIFAD.Bits.PIFADL7 +#define PIFAD_PIFADH0 _PIFAD.Bits.PIFADH0 +#define PIFAD_PIFADH1 _PIFAD.Bits.PIFADH1 +#define PIFAD_PIFADL _PIFAD.MergedBits.grpPIFADL +#define PIFAD_PIFADH _PIFAD.MergedBits.grpPIFADH + +#define PIFAD_PIFADL0_MASK 1U +#define PIFAD_PIFADL1_MASK 2U +#define PIFAD_PIFADL2_MASK 4U +#define PIFAD_PIFADL3_MASK 8U +#define PIFAD_PIFADL4_MASK 16U +#define PIFAD_PIFADL5_MASK 32U +#define PIFAD_PIFADL6_MASK 64U +#define PIFAD_PIFADL7_MASK 128U +#define PIFAD_PIFADH0_MASK 256U +#define PIFAD_PIFADH1_MASK 512U +#define PIFAD_PIFADL_MASK 255U +#define PIFAD_PIFADL_BITNUM 0U +#define PIFAD_PIFADH_MASK 768U +#define PIFAD_PIFADH_BITNUM 8U + + +/*** DIENAD - Digital Input Enable Register; 0x00000298 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DIENADH - Digital Input Enable Register; 0x00000298 ***/ + union { + byte Byte; + struct { + byte DIENADH0 :1; /* Digital input enable 0 */ + byte DIENADH1 :1; /* Digital input enable 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDIENADH :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } DIENADHSTR; + #define DIENADH _DIENAD.Overlap_STR.DIENADHSTR.Byte + #define DIENADH_DIENADH0 _DIENAD.Overlap_STR.DIENADHSTR.Bits.DIENADH0 + #define DIENADH_DIENADH1 _DIENAD.Overlap_STR.DIENADHSTR.Bits.DIENADH1 + #define DIENADH_DIENADH _DIENAD.Overlap_STR.DIENADHSTR.MergedBits.grpDIENADH + + #define DIENADH_DIENADH0_MASK 1U + #define DIENADH_DIENADH1_MASK 2U + #define DIENADH_DIENADH_MASK 3U + #define DIENADH_DIENADH_BITNUM 0U + + + /*** DIENADL - Digital Input Enable Register; 0x00000299 ***/ + union { + byte Byte; + struct { + byte DIENADL0 :1; /* Digital input enable 0 */ + byte DIENADL1 :1; /* Digital input enable 1 */ + byte DIENADL2 :1; /* Digital input enable 2 */ + byte DIENADL3 :1; /* Digital input enable 3 */ + byte DIENADL4 :1; /* Digital input enable 4 */ + byte DIENADL5 :1; /* Digital input enable 5 */ + byte DIENADL6 :1; /* Digital input enable 6 */ + byte DIENADL7 :1; /* Digital input enable 7 */ + } Bits; + } DIENADLSTR; + #define DIENADL _DIENAD.Overlap_STR.DIENADLSTR.Byte + #define DIENADL_DIENADL0 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL0 + #define DIENADL_DIENADL1 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL1 + #define DIENADL_DIENADL2 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL2 + #define DIENADL_DIENADL3 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL3 + #define DIENADL_DIENADL4 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL4 + #define DIENADL_DIENADL5 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL5 + #define DIENADL_DIENADL6 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL6 + #define DIENADL_DIENADL7 _DIENAD.Overlap_STR.DIENADLSTR.Bits.DIENADL7 + + #define DIENADL_DIENADL0_MASK 1U + #define DIENADL_DIENADL1_MASK 2U + #define DIENADL_DIENADL2_MASK 4U + #define DIENADL_DIENADL3_MASK 8U + #define DIENADL_DIENADL4_MASK 16U + #define DIENADL_DIENADL5_MASK 32U + #define DIENADL_DIENADL6_MASK 64U + #define DIENADL_DIENADL7_MASK 128U + + } Overlap_STR; + + struct { + word DIENADL0 :1; /* Digital input enable 0 */ + word DIENADL1 :1; /* Digital input enable 1 */ + word DIENADL2 :1; /* Digital input enable 2 */ + word DIENADL3 :1; /* Digital input enable 3 */ + word DIENADL4 :1; /* Digital input enable 4 */ + word DIENADL5 :1; /* Digital input enable 5 */ + word DIENADL6 :1; /* Digital input enable 6 */ + word DIENADL7 :1; /* Digital input enable 7 */ + word DIENADH0 :1; /* Digital input enable 8 */ + word DIENADH1 :1; /* Digital input enable 9 */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } Bits; + struct { + word grpDIENADL :8; + word grpDIENADH :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} DIENADSTR; +extern volatile DIENADSTR _DIENAD @0x00000298; +#define DIENAD _DIENAD.Word +#define DIENAD_DIENADL0 _DIENAD.Bits.DIENADL0 +#define DIENAD_DIENADL1 _DIENAD.Bits.DIENADL1 +#define DIENAD_DIENADL2 _DIENAD.Bits.DIENADL2 +#define DIENAD_DIENADL3 _DIENAD.Bits.DIENADL3 +#define DIENAD_DIENADL4 _DIENAD.Bits.DIENADL4 +#define DIENAD_DIENADL5 _DIENAD.Bits.DIENADL5 +#define DIENAD_DIENADL6 _DIENAD.Bits.DIENADL6 +#define DIENAD_DIENADL7 _DIENAD.Bits.DIENADL7 +#define DIENAD_DIENADH0 _DIENAD.Bits.DIENADH0 +#define DIENAD_DIENADH1 _DIENAD.Bits.DIENADH1 +#define DIENAD_DIENADL _DIENAD.MergedBits.grpDIENADL +#define DIENAD_DIENADH _DIENAD.MergedBits.grpDIENADH + +#define DIENAD_DIENADL0_MASK 1U +#define DIENAD_DIENADL1_MASK 2U +#define DIENAD_DIENADL2_MASK 4U +#define DIENAD_DIENADL3_MASK 8U +#define DIENAD_DIENADL4_MASK 16U +#define DIENAD_DIENADL5_MASK 32U +#define DIENAD_DIENADL6_MASK 64U +#define DIENAD_DIENADL7_MASK 128U +#define DIENAD_DIENADH0_MASK 256U +#define DIENAD_DIENADH1_MASK 512U +#define DIENAD_DIENADL_MASK 255U +#define DIENAD_DIENADL_BITNUM 0U +#define DIENAD_DIENADH_MASK 768U +#define DIENAD_DIENADH_BITNUM 8U + + +/*** PTT - Port T Data Register; 0x000002C0 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T general purpose I/O data 0 */ + byte PTT1 :1; /* Port T general purpose I/O data 1 */ + byte PTT2 :1; /* Port T general purpose I/O data 2 */ + byte PTT3 :1; /* Port T general purpose I/O data 3 */ + byte PTT4 :1; /* Port T general purpose I/O data 4 */ + byte PTT5 :1; /* Port T general purpose I/O data 5 */ + byte PTT6 :1; /* Port T general purpose I/O data 6 */ + byte PTT7 :1; /* Port T general purpose I/O data 7 */ + } Bits; +} PTTSTR; +extern volatile PTTSTR _PTT @0x000002C0; +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 + +#define PTT_PTT0_MASK 1U +#define PTT_PTT1_MASK 2U +#define PTT_PTT2_MASK 4U +#define PTT_PTT3_MASK 8U +#define PTT_PTT4_MASK 16U +#define PTT_PTT5_MASK 32U +#define PTT_PTT6_MASK 64U +#define PTT_PTT7_MASK 128U + + +/*** PTIT - Port T Input Register; 0x000002C1 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T data input 0 */ + byte PTIT1 :1; /* Port T data input 1 */ + byte PTIT2 :1; /* Port T data input 2 */ + byte PTIT3 :1; /* Port T data input 3 */ + byte PTIT4 :1; /* Port T data input 4 */ + byte PTIT5 :1; /* Port T data input 5 */ + byte PTIT6 :1; /* Port T data input 6 */ + byte PTIT7 :1; /* Port T data input 7 */ + } Bits; +} PTITSTR; +extern volatile PTITSTR _PTIT @0x000002C1; +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 + +#define PTIT_PTIT0_MASK 1U +#define PTIT_PTIT1_MASK 2U +#define PTIT_PTIT2_MASK 4U +#define PTIT_PTIT3_MASK 8U +#define PTIT_PTIT4_MASK 16U +#define PTIT_PTIT5_MASK 32U +#define PTIT_PTIT6_MASK 64U +#define PTIT_PTIT7_MASK 128U + + +/*** DDRT - Port T Data Direction Register; 0x000002C2 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Port T data direction select 0 */ + byte DDRT1 :1; /* Port T data direction select 1 */ + byte DDRT2 :1; /* Port T data direction select 2 */ + byte DDRT3 :1; /* Port T data direction select 3 */ + byte DDRT4 :1; /* Port T data direction select 4 */ + byte DDRT5 :1; /* Port T data direction select 5 */ + byte DDRT6 :1; /* Port T data direction select 6 */ + byte DDRT7 :1; /* Port T data direction select 7 */ + } Bits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @0x000002C2; +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 + +#define DDRT_DDRT0_MASK 1U +#define DDRT_DDRT1_MASK 2U +#define DDRT_DDRT2_MASK 4U +#define DDRT_DDRT3_MASK 8U +#define DDRT_DDRT4_MASK 16U +#define DDRT_DDRT5_MASK 32U +#define DDRT_DDRT6_MASK 64U +#define DDRT_DDRT7_MASK 128U + + +/*** PERT - Port T Pull Device Enable Register; 0x000002C3 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Port T pull device enable 0 */ + byte PERT1 :1; /* Port T pull device enable 1 */ + byte PERT2 :1; /* Port T pull device enable 2 */ + byte PERT3 :1; /* Port T pull device enable 3 */ + byte PERT4 :1; /* Port T pull device enable 4 */ + byte PERT5 :1; /* Port T pull device enable 5 */ + byte PERT6 :1; /* Port T pull device enable 6 */ + byte PERT7 :1; /* Port T pull device enable 7 */ + } Bits; +} PERTSTR; +extern volatile PERTSTR _PERT @0x000002C3; +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 + +#define PERT_PERT0_MASK 1U +#define PERT_PERT1_MASK 2U +#define PERT_PERT2_MASK 4U +#define PERT_PERT3_MASK 8U +#define PERT_PERT4_MASK 16U +#define PERT_PERT5_MASK 32U +#define PERT_PERT6_MASK 64U +#define PERT_PERT7_MASK 128U + + +/*** PPST - Port T Polarity Select Register; 0x000002C4 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Port T pull polarity select 0 */ + byte PPST1 :1; /* Port T pull polarity select 1 */ + byte PPST2 :1; /* Port T pull polarity select 2 */ + byte PPST3 :1; /* Port T pull polarity select 3 */ + byte PPST4 :1; /* Port T pull polarity select 4 */ + byte PPST5 :1; /* Port T pull polarity select 5 */ + byte PPST6 :1; /* Port T pull polarity select 6 */ + byte PPST7 :1; /* Port T pull polarity select 7 */ + } Bits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @0x000002C4; +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 + +#define PPST_PPST0_MASK 1U +#define PPST_PPST1_MASK 2U +#define PPST_PPST2_MASK 4U +#define PPST_PPST3_MASK 8U +#define PPST_PPST4_MASK 16U +#define PPST_PPST5_MASK 32U +#define PPST_PPST6_MASK 64U +#define PPST_PPST7_MASK 128U + + +/*** PTS - Port S Data Register; 0x000002D0 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S general purpose I/O data 0 */ + byte PTS1 :1; /* Port S general purpose I/O data 1 */ + byte PTS2 :1; /* Port S general purpose I/O data 2 */ + byte PTS3 :1; /* Port S general purpose I/O data 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTSSTR; +extern volatile PTSSTR _PTS @0x000002D0; +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS _PTS.MergedBits.grpPTS + +#define PTS_PTS0_MASK 1U +#define PTS_PTS1_MASK 2U +#define PTS_PTS2_MASK 4U +#define PTS_PTS3_MASK 8U +#define PTS_PTS_MASK 15U +#define PTS_PTS_BITNUM 0U + + +/*** PTIS - Port S Input Register; 0x000002D1 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S data input 0 */ + byte PTIS1 :1; /* Port S data input 1 */ + byte PTIS2 :1; /* Port S data input 2 */ + byte PTIS3 :1; /* Port S data input 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTISSTR; +extern volatile PTISSTR _PTIS @0x000002D1; +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS _PTIS.MergedBits.grpPTIS + +#define PTIS_PTIS0_MASK 1U +#define PTIS_PTIS1_MASK 2U +#define PTIS_PTIS2_MASK 4U +#define PTIS_PTIS3_MASK 8U +#define PTIS_PTIS_MASK 15U +#define PTIS_PTIS_BITNUM 0U + + +/*** DDRS - Port S Data Direction Register; 0x000002D2 ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Port S data direction select 0 */ + byte DDRS1 :1; /* Port S data direction select 1 */ + byte DDRS2 :1; /* Port S data direction select 2 */ + byte DDRS3 :1; /* Port S data direction select 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @0x000002D2; +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS _DDRS.MergedBits.grpDDRS + +#define DDRS_DDRS0_MASK 1U +#define DDRS_DDRS1_MASK 2U +#define DDRS_DDRS2_MASK 4U +#define DDRS_DDRS3_MASK 8U +#define DDRS_DDRS_MASK 15U +#define DDRS_DDRS_BITNUM 0U + + +/*** PERS - Port S Pull Device Enable Register; 0x000002D3 ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Port S pull device enable 0 */ + byte PERS1 :1; /* Port S pull device enable 1 */ + byte PERS2 :1; /* Port S pull device enable 2 */ + byte PERS3 :1; /* Port S pull device enable 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PERSSTR; +extern volatile PERSSTR _PERS @0x000002D3; +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS _PERS.MergedBits.grpPERS + +#define PERS_PERS0_MASK 1U +#define PERS_PERS1_MASK 2U +#define PERS_PERS2_MASK 4U +#define PERS_PERS3_MASK 8U +#define PERS_PERS_MASK 15U +#define PERS_PERS_BITNUM 0U + + +/*** PPSS - Port S Polarity Select Register; 0x000002D4 ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Port S pull polarity select 0 */ + byte PPSS1 :1; /* Port S pull polarity select 1 */ + byte PPSS2 :1; /* Port S pull polarity select 2 */ + byte PPSS3 :1; /* Port S pull polarity select 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @0x000002D4; +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS _PPSS.MergedBits.grpPPSS + +#define PPSS_PPSS0_MASK 1U +#define PPSS_PPSS1_MASK 2U +#define PPSS_PPSS2_MASK 4U +#define PPSS_PPSS3_MASK 8U +#define PPSS_PPSS_MASK 15U +#define PPSS_PPSS_BITNUM 0U + + +/*** PIES - Port S Interrupt Enable Register; 0x000002D6 ***/ +typedef union { + byte Byte; + struct { + byte PIES0 :1; /* Port S interrupt enable 0 */ + byte PIES1 :1; /* Port S interrupt enable 1 */ + byte PIES2 :1; /* Port S interrupt enable 2 */ + byte PIES3 :1; /* Port S interrupt enable 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPIES :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PIESSTR; +extern volatile PIESSTR _PIES @0x000002D6; +#define PIES _PIES.Byte +#define PIES_PIES0 _PIES.Bits.PIES0 +#define PIES_PIES1 _PIES.Bits.PIES1 +#define PIES_PIES2 _PIES.Bits.PIES2 +#define PIES_PIES3 _PIES.Bits.PIES3 +#define PIES_PIES _PIES.MergedBits.grpPIES + +#define PIES_PIES0_MASK 1U +#define PIES_PIES1_MASK 2U +#define PIES_PIES2_MASK 4U +#define PIES_PIES3_MASK 8U +#define PIES_PIES_MASK 15U +#define PIES_PIES_BITNUM 0U + + +/*** PIFS - Port S Interrupt Flag Register; 0x000002D7 ***/ +typedef union { + byte Byte; + struct { + byte PIFS0 :1; /* Port S interrupt flag 0 */ + byte PIFS1 :1; /* Port S interrupt flag 1 */ + byte PIFS2 :1; /* Port S interrupt flag 2 */ + byte PIFS3 :1; /* Port S interrupt flag 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPIFS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PIFSSTR; +extern volatile PIFSSTR _PIFS @0x000002D7; +#define PIFS _PIFS.Byte +#define PIFS_PIFS0 _PIFS.Bits.PIFS0 +#define PIFS_PIFS1 _PIFS.Bits.PIFS1 +#define PIFS_PIFS2 _PIFS.Bits.PIFS2 +#define PIFS_PIFS3 _PIFS.Bits.PIFS3 +#define PIFS_PIFS _PIFS.MergedBits.grpPIFS + +#define PIFS_PIFS0_MASK 1U +#define PIFS_PIFS1_MASK 2U +#define PIFS_PIFS2_MASK 4U +#define PIFS_PIFS3_MASK 8U +#define PIFS_PIFS_MASK 15U +#define PIFS_PIFS_BITNUM 0U + + +/*** WOMS - Port S Wired-Or Mode Register; 0x000002DF ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Port S wired-or mode 0 */ + byte WOMS1 :1; /* Port S wired-or mode 1 */ + byte WOMS2 :1; /* Port S wired-or mode 2 */ + byte WOMS3 :1; /* Port S wired-or mode 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @0x000002DF; +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS _WOMS.MergedBits.grpWOMS + +#define WOMS_WOMS0_MASK 1U +#define WOMS_WOMS1_MASK 2U +#define WOMS_WOMS2_MASK 4U +#define WOMS_WOMS3_MASK 8U +#define WOMS_WOMS_MASK 15U +#define WOMS_WOMS_BITNUM 0U + + +/*** PTP - Port P Data Register; 0x000002F0 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P general purpose I/O data 0 */ + byte PTP1 :1; /* Port P general purpose I/O data 1 */ + byte PTP2 :1; /* Port P general purpose I/O data 2 */ + byte PTP3 :1; /* Port P general purpose I/O data 3 */ + byte PTP4 :1; /* Port P general purpose I/O data 4 */ + byte PTP5 :1; /* Port P general purpose I/O data 5 */ + byte PTP6 :1; /* Port P general purpose I/O data 6 */ + byte PTP7 :1; /* Port P general purpose I/O data 7 */ + } Bits; +} PTPSTR; +extern volatile PTPSTR _PTP @0x000002F0; +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 + +#define PTP_PTP0_MASK 1U +#define PTP_PTP1_MASK 2U +#define PTP_PTP2_MASK 4U +#define PTP_PTP3_MASK 8U +#define PTP_PTP4_MASK 16U +#define PTP_PTP5_MASK 32U +#define PTP_PTP6_MASK 64U +#define PTP_PTP7_MASK 128U + + +/*** PTIP - Port P Input Register; 0x000002F1 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P data input 0 */ + byte PTIP1 :1; /* Port P data input 1 */ + byte PTIP2 :1; /* Port P data input 2 */ + byte PTIP3 :1; /* Port P data input 3 */ + byte PTIP4 :1; /* Port P data input 4 */ + byte PTIP5 :1; /* Port P data input 5 */ + byte PTIP6 :1; /* Port P data input 6 */ + byte PTIP7 :1; /* Port P data input 7 */ + } Bits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @0x000002F1; +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 + +#define PTIP_PTIP0_MASK 1U +#define PTIP_PTIP1_MASK 2U +#define PTIP_PTIP2_MASK 4U +#define PTIP_PTIP3_MASK 8U +#define PTIP_PTIP4_MASK 16U +#define PTIP_PTIP5_MASK 32U +#define PTIP_PTIP6_MASK 64U +#define PTIP_PTIP7_MASK 128U + + +/*** DDRP - Port P Data Direction Register; 0x000002F2 ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Port P data direction select 0 */ + byte DDRP1 :1; /* Port P data direction select 1 */ + byte DDRP2 :1; /* Port P data direction select 2 */ + byte DDRP3 :1; /* Port P data direction select 3 */ + byte DDRP4 :1; /* Port P data direction select 4 */ + byte DDRP5 :1; /* Port P data direction select 5 */ + byte DDRP6 :1; /* Port P data direction select 6 */ + byte DDRP7 :1; /* Port P data direction select 7 */ + } Bits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @0x000002F2; +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 + +#define DDRP_DDRP0_MASK 1U +#define DDRP_DDRP1_MASK 2U +#define DDRP_DDRP2_MASK 4U +#define DDRP_DDRP3_MASK 8U +#define DDRP_DDRP4_MASK 16U +#define DDRP_DDRP5_MASK 32U +#define DDRP_DDRP6_MASK 64U +#define DDRP_DDRP7_MASK 128U + + +/*** PERP - Port P Pull Device Enable Register; 0x000002F3 ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Port P pull device enable 0 */ + byte PERP1 :1; /* Port P pull device enable 1 */ + byte PERP2 :1; /* Port P pull device enable 2 */ + byte PERP3 :1; /* Port P pull device enable 3 */ + byte PERP4 :1; /* Port P pull device enable 4 */ + byte PERP5 :1; /* Port P pull device enable 5 */ + byte PERP6 :1; /* Port P pull device enable 6 */ + byte PERP7 :1; /* Port P pull device enable 7 */ + } Bits; +} PERPSTR; +extern volatile PERPSTR _PERP @0x000002F3; +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 + +#define PERP_PERP0_MASK 1U +#define PERP_PERP1_MASK 2U +#define PERP_PERP2_MASK 4U +#define PERP_PERP3_MASK 8U +#define PERP_PERP4_MASK 16U +#define PERP_PERP5_MASK 32U +#define PERP_PERP6_MASK 64U +#define PERP_PERP7_MASK 128U + + +/*** PPSP - Port P Polarity Select Register; 0x000002F4 ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Port P pull polarity select 0 */ + byte PPSP1 :1; /* Port P pull polarity select 1 */ + byte PPSP2 :1; /* Port P pull polarity select 2 */ + byte PPSP3 :1; /* Port P pull polarity select 3 */ + byte PPSP4 :1; /* Port P pull polarity select 4 */ + byte PPSP5 :1; /* Port P pull polarity select 5 */ + byte PPSP6 :1; /* Port P pull polarity select 6 */ + byte PPSP7 :1; /* Port P pull polarity select 7 */ + } Bits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @0x000002F4; +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 + +#define PPSP_PPSP0_MASK 1U +#define PPSP_PPSP1_MASK 2U +#define PPSP_PPSP2_MASK 4U +#define PPSP_PPSP3_MASK 8U +#define PPSP_PPSP4_MASK 16U +#define PPSP_PPSP5_MASK 32U +#define PPSP_PPSP6_MASK 64U +#define PPSP_PPSP7_MASK 128U + + +/*** PIEP - Port P Interrupt Enable Register; 0x000002F6 ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Port P interrupt enable 0 */ + byte PIEP1 :1; /* Port P interrupt enable 1 */ + byte PIEP2 :1; /* Port P interrupt enable 2 */ + byte PIEP3 :1; /* Port P interrupt enable 3 */ + byte PIEP4 :1; /* Port P interrupt enable 4 */ + byte PIEP5 :1; /* Port P interrupt enable 5 */ + byte PIEP6 :1; /* Port P interrupt enable 6 */ + byte PIEP7 :1; /* Port P interrupt enable 7 */ + } Bits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @0x000002F6; +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 + +#define PIEP_PIEP0_MASK 1U +#define PIEP_PIEP1_MASK 2U +#define PIEP_PIEP2_MASK 4U +#define PIEP_PIEP3_MASK 8U +#define PIEP_PIEP4_MASK 16U +#define PIEP_PIEP5_MASK 32U +#define PIEP_PIEP6_MASK 64U +#define PIEP_PIEP7_MASK 128U + + +/*** PIFP - Port P Interrupt Flag Register; 0x000002F7 ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Port P interrupt flag 0 */ + byte PIFP1 :1; /* Port P interrupt flag 1 */ + byte PIFP2 :1; /* Port P interrupt flag 2 */ + byte PIFP3 :1; /* Port P interrupt flag 3 */ + byte PIFP4 :1; /* Port P interrupt flag 4 */ + byte PIFP5 :1; /* Port P interrupt flag 5 */ + byte PIFP6 :1; /* Port P interrupt flag 6 */ + byte PIFP7 :1; /* Port P interrupt flag 7 */ + } Bits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @0x000002F7; +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 + +#define PIFP_PIFP0_MASK 1U +#define PIFP_PIFP1_MASK 2U +#define PIFP_PIFP2_MASK 4U +#define PIFP_PIFP3_MASK 8U +#define PIFP_PIFP4_MASK 16U +#define PIFP_PIFP5_MASK 32U +#define PIFP_PIFP6_MASK 64U +#define PIFP_PIFP7_MASK 128U + + +/*** OCPEP - Port P Over-Current Protection Enable Register; 0x000002F9 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte OCPEP1 :1; /* Over-Current Protection Enable on PP1 */ + byte :1; + byte OCPEP3 :1; /* Over-Current Protection Enable on PP3 */ + byte :1; + byte OCPEP5 :1; /* Over-Current Protection Enable on PP5 */ + byte :1; + byte OCPEP7 :1; /* Over-Current Protection Enable on EVDD1 */ + } Bits; +} OCPEPSTR; +extern volatile OCPEPSTR _OCPEP @0x000002F9; +#define OCPEP _OCPEP.Byte +#define OCPEP_OCPEP1 _OCPEP.Bits.OCPEP1 +#define OCPEP_OCPEP3 _OCPEP.Bits.OCPEP3 +#define OCPEP_OCPEP5 _OCPEP.Bits.OCPEP5 +#define OCPEP_OCPEP7 _OCPEP.Bits.OCPEP7 + +#define OCPEP_OCPEP1_MASK 2U +#define OCPEP_OCPEP3_MASK 8U +#define OCPEP_OCPEP5_MASK 32U +#define OCPEP_OCPEP7_MASK 128U + + +/*** OCIEP - Port P Over-Current Interrupt Enable Register; 0x000002FA ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte OCIEP1 :1; /* Over-Current Interrupt Enable on PP1 */ + byte :1; + byte OCIEP3 :1; /* Over-Current Interrupt Enable on PP3 */ + byte :1; + byte OCIEP5 :1; /* Over-Current Interrupt Enable on PP5 */ + byte :1; + byte OCIEP7 :1; /* Over-Current Interrupt Enable on EVDD1 */ + } Bits; +} OCIEPSTR; +extern volatile OCIEPSTR _OCIEP @0x000002FA; +#define OCIEP _OCIEP.Byte +#define OCIEP_OCIEP1 _OCIEP.Bits.OCIEP1 +#define OCIEP_OCIEP3 _OCIEP.Bits.OCIEP3 +#define OCIEP_OCIEP5 _OCIEP.Bits.OCIEP5 +#define OCIEP_OCIEP7 _OCIEP.Bits.OCIEP7 + +#define OCIEP_OCIEP1_MASK 2U +#define OCIEP_OCIEP3_MASK 8U +#define OCIEP_OCIEP5_MASK 32U +#define OCIEP_OCIEP7_MASK 128U + + +/*** OCIFP - Port P Over-Current Interrupt Flag Register; 0x000002FB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte OCIFP1 :1; /* Over-Current Interrupt Flag on PP1 */ + byte :1; + byte OCIFP3 :1; /* Over-Current Interrupt Flag on PP3 */ + byte :1; + byte OCIFP5 :1; /* Over-Current Interrupt Flag on PP5 */ + byte :1; + byte OCIFP7 :1; /* Over-Current Interrupt Flag on EVDD1 */ + } Bits; +} OCIFPSTR; +extern volatile OCIFPSTR _OCIFP @0x000002FB; +#define OCIFP _OCIFP.Byte +#define OCIFP_OCIFP1 _OCIFP.Bits.OCIFP1 +#define OCIFP_OCIFP3 _OCIFP.Bits.OCIFP3 +#define OCIFP_OCIFP5 _OCIFP.Bits.OCIFP5 +#define OCIFP_OCIFP7 _OCIFP.Bits.OCIFP7 + +#define OCIFP_OCIFP1_MASK 2U +#define OCIFP_OCIFP3_MASK 8U +#define OCIFP_OCIFP5_MASK 32U +#define OCIFP_OCIFP7_MASK 128U + + +/*** RDRP - Port P Reduced Drive Register; 0x000002FD ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte RDRP1 :1; /* Port P reduced drive select 1 */ + byte :1; + byte RDRP3 :1; /* Port P reduced drive select 3 */ + byte :1; + byte RDRP5 :1; /* Port P reduced drive select 5 */ + byte :1; + byte RDRP7 :1; /* Port P reduced drive select 7 */ + } Bits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @0x000002FD; +#define RDRP _RDRP.Byte +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 + +#define RDRP_RDRP1_MASK 2U +#define RDRP_RDRP3_MASK 8U +#define RDRP_RDRP5_MASK 32U +#define RDRP_RDRP7_MASK 128U + + +/*** PTJ - Port J Data Register; 0x00000310 ***/ +typedef union { + byte Byte; + struct { + byte PTJ0 :1; /* Port J general purpose I/O data 0 */ + byte PTJ1 :1; /* Port J general purpose I/O data 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @0x00000310; +#define PTJ _PTJ.Byte +#define PTJ_PTJ0 _PTJ.Bits.PTJ0 +#define PTJ_PTJ1 _PTJ.Bits.PTJ1 +#define PTJ_PTJ _PTJ.MergedBits.grpPTJ + +#define PTJ_PTJ0_MASK 1U +#define PTJ_PTJ1_MASK 2U +#define PTJ_PTJ_MASK 3U +#define PTJ_PTJ_BITNUM 0U + + +/*** PTIJ - Port J Input Register; 0x00000311 ***/ +typedef union { + byte Byte; + struct { + byte PTIJ0 :1; /* Port J data input 0 */ + byte PTIJ1 :1; /* Port J data input 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @0x00000311; +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 +#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 +#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ + +#define PTIJ_PTIJ0_MASK 1U +#define PTIJ_PTIJ1_MASK 2U +#define PTIJ_PTIJ_MASK 3U +#define PTIJ_PTIJ_BITNUM 0U + + +/*** DDRJ - Port J Data Direction Register; 0x00000312 ***/ +typedef union { + byte Byte; + struct { + byte DDRJ0 :1; /* Port J data direction select 0 */ + byte DDRJ1 :1; /* Port J data direction select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @0x00000312; +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 +#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 +#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ + +#define DDRJ_DDRJ0_MASK 1U +#define DDRJ_DDRJ1_MASK 2U +#define DDRJ_DDRJ_MASK 3U +#define DDRJ_DDRJ_BITNUM 0U + + +/*** PERJ - Port J Pull Device Enable Register; 0x00000313 ***/ +typedef union { + byte Byte; + struct { + byte PERJ0 :1; /* Port J pull device enable 0 */ + byte PERJ1 :1; /* Port J pull device enable 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @0x00000313; +#define PERJ _PERJ.Byte +#define PERJ_PERJ0 _PERJ.Bits.PERJ0 +#define PERJ_PERJ1 _PERJ.Bits.PERJ1 +#define PERJ_PERJ _PERJ.MergedBits.grpPERJ + +#define PERJ_PERJ0_MASK 1U +#define PERJ_PERJ1_MASK 2U +#define PERJ_PERJ_MASK 3U +#define PERJ_PERJ_BITNUM 0U + + +/*** PPSJ - Port J Polarity Select Register; 0x00000314 ***/ +typedef union { + byte Byte; + struct { + byte PPSJ0 :1; /* Port J pull polarity select 0 */ + byte PPSJ1 :1; /* Port J pull polarity select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @0x00000314; +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 +#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 +#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ + +#define PPSJ_PPSJ0_MASK 1U +#define PPSJ_PPSJ1_MASK 2U +#define PPSJ_PPSJ_MASK 3U +#define PPSJ_PPSJ_BITNUM 0U + + +/*** WOMJ - Port J Wired-Or Mode Register; 0x0000031F ***/ +typedef union { + byte Byte; + struct { + byte WOMJ0 :1; /* Port J wired-or mode 0 */ + byte WOMJ1 :1; /* Port J wired-or mode 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} WOMJSTR; +extern volatile WOMJSTR _WOMJ @0x0000031F; +#define WOMJ _WOMJ.Byte +#define WOMJ_WOMJ0 _WOMJ.Bits.WOMJ0 +#define WOMJ_WOMJ1 _WOMJ.Bits.WOMJ1 +#define WOMJ_WOMJ _WOMJ.MergedBits.grpWOMJ + +#define WOMJ_WOMJ0_MASK 1U +#define WOMJ_WOMJ1_MASK 2U +#define WOMJ_WOMJ_MASK 3U +#define WOMJ_WOMJ_BITNUM 0U + + +/*** PTIL - Port L Input Register; 0x00000331 ***/ +typedef union { + byte Byte; + struct { + byte PTIL0 :1; /* Port L data input 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PTILSTR; +extern volatile PTILSTR _PTIL @0x00000331; +#define PTIL _PTIL.Byte +#define PTIL_PTIL0 _PTIL.Bits.PTIL0 + +#define PTIL_PTIL0_MASK 1U + + +/*** PPSL - Port L Polarity Select Register; 0x00000334 ***/ +typedef union { + byte Byte; + struct { + byte PPSL0 :1; /* Port L pull polarity select 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PPSLSTR; +extern volatile PPSLSTR _PPSL @0x00000334; +#define PPSL _PPSL.Byte +#define PPSL_PPSL0 _PPSL.Bits.PPSL0 + +#define PPSL_PPSL0_MASK 1U + + +/*** PIEL - Port L Interrupt Enable Register; 0x00000336 ***/ +typedef union { + byte Byte; + struct { + byte PIEL0 :1; /* Port L interrupt enable 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PIELSTR; +extern volatile PIELSTR _PIEL @0x00000336; +#define PIEL _PIEL.Byte +#define PIEL_PIEL0 _PIEL.Bits.PIEL0 + +#define PIEL_PIEL0_MASK 1U + + +/*** PIFL - Port L Interrupt Flag Register; 0x00000337 ***/ +typedef union { + byte Byte; + struct { + byte PIFL0 :1; /* Port L interrupt flag 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PIFLSTR; +extern volatile PIFLSTR _PIFL @0x00000337; +#define PIFL _PIFL.Byte +#define PIFL_PIFL0 _PIFL.Bits.PIFL0 + +#define PIFL_PIFL0_MASK 1U + + +/*** DIENL - Port LDigital Input Enable Register; 0x0000033C ***/ +typedef union { + byte Byte; + struct { + byte DIENL0 :1; /* Digital input enable 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} DIENLSTR; +extern volatile DIENLSTR _DIENL @0x0000033C; +#define DIENL _DIENL.Byte +#define DIENL_DIENL0 _DIENL.Bits.DIENL0 + +#define DIENL_DIENL0_MASK 1U + + +/*** PTAL - Port L Analog Access Register; 0x0000033D ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte PTAENL :1; /* Port L ADC connection Enable */ + byte PTADIRL :1; /* Port L ADC Direct connection */ + byte PTABYPL :1; /* Port L ADC connection Bypass */ + byte PTPSL :1; /* Port L Pull Select */ + byte PTTEL :1; /* Port L Test Enable */ + } Bits; +} PTALSTR; +extern volatile PTALSTR _PTAL @0x0000033D; +#define PTAL _PTAL.Byte +#define PTAL_PTAENL _PTAL.Bits.PTAENL +#define PTAL_PTADIRL _PTAL.Bits.PTADIRL +#define PTAL_PTABYPL _PTAL.Bits.PTABYPL +#define PTAL_PTPSL _PTAL.Bits.PTPSL +#define PTAL_PTTEL _PTAL.Bits.PTTEL + +#define PTAL_PTAENL_MASK 8U +#define PTAL_PTADIRL_MASK 16U +#define PTAL_PTABYPL_MASK 32U +#define PTAL_PTPSL_MASK 64U +#define PTAL_PTTEL_MASK 128U + + +/*** PIRL - Port L Input Divider Ratio Selection Register; 0x0000033E ***/ +typedef union { + byte Byte; + struct { + byte PIRL0 :1; /* Port L Input Divider Ratio Selection bit 0 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PIRLSTR; +extern volatile PIRLSTR _PIRL @0x0000033E; +#define PIRL _PIRL.Byte +#define PIRL_PIRL0 _PIRL.Bits.PIRL0 + +#define PIRL_PIRL0_MASK 1U + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000380 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Clock Divider Bit 0 */ + byte FDIV1 :1; /* Clock Divider Bit 1 */ + byte FDIV2 :1; /* Clock Divider Bit 2 */ + byte FDIV3 :1; /* Clock Divider Bit 3 */ + byte FDIV4 :1; /* Clock Divider Bit 4 */ + byte FDIV5 :1; /* Clock Divider Bit 5 */ + byte FDIVLCK :1; /* Clock divider locked */ + byte FDIVLD :1; /* Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @0x00000380; +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_FDIVLCK _FCLKDIV.Bits.FDIVLCK +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + +#define FCLKDIV_FDIV0_MASK 1U +#define FCLKDIV_FDIV1_MASK 2U +#define FCLKDIV_FDIV2_MASK 4U +#define FCLKDIV_FDIV3_MASK 8U +#define FCLKDIV_FDIV4_MASK 16U +#define FCLKDIV_FDIV5_MASK 32U +#define FCLKDIV_FDIVLCK_MASK 64U +#define FCLKDIV_FDIVLD_MASK 128U +#define FCLKDIV_FDIV_MASK 63U +#define FCLKDIV_FDIV_BITNUM 0U + + +/*** FSEC - Flash Security Register; 0x00000381 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Flash Security Bit 0 */ + byte SEC1 :1; /* Flash Security Bit 1 */ + byte RNV2 :1; /* Reserved Nonvolatile Bit 2 */ + byte RNV3 :1; /* Reserved Nonvolatile Bit 3 */ + byte RNV4 :1; /* Reserved Nonvolatile Bit 4 */ + byte RNV5 :1; /* Reserved Nonvolatile Bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpRNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @0x00000381; +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_RNV2 _FSEC.Bits.RNV2 +#define FSEC_RNV3 _FSEC.Bits.RNV3 +#define FSEC_RNV4 _FSEC.Bits.RNV4 +#define FSEC_RNV5 _FSEC.Bits.RNV5 +#define FSEC_KEYEN0 _FSEC.Bits.KEYEN0 +#define FSEC_KEYEN1 _FSEC.Bits.KEYEN1 +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_RNV_2 _FSEC.MergedBits.grpRNV_2 +#define FSEC_KEYEN _FSEC.MergedBits.grpKEYEN +#define FSEC_RNV FSEC_RNV_2 + +#define FSEC_SEC0_MASK 1U +#define FSEC_SEC1_MASK 2U +#define FSEC_RNV2_MASK 4U +#define FSEC_RNV3_MASK 8U +#define FSEC_RNV4_MASK 16U +#define FSEC_RNV5_MASK 32U +#define FSEC_KEYEN0_MASK 64U +#define FSEC_KEYEN1_MASK 128U +#define FSEC_SEC_MASK 3U +#define FSEC_SEC_BITNUM 0U +#define FSEC_RNV_2_MASK 60U +#define FSEC_RNV_2_BITNUM 2U +#define FSEC_KEYEN_MASK 192U +#define FSEC_KEYEN_BITNUM 6U + + +/*** FCCOBIX - Flash CCOB Index Register; 0x00000382 ***/ +typedef union { + byte Byte; + struct { + byte CCOBIX0 :1; /* Common Command Register Index Bit 0 */ + byte CCOBIX1 :1; /* Common Command Register Index Bit 1 */ + byte CCOBIX2 :1; /* Common Command Register Index Bit 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpCCOBIX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCCOBIXSTR; +extern volatile FCCOBIXSTR _FCCOBIX @0x00000382; +#define FCCOBIX _FCCOBIX.Byte +#define FCCOBIX_CCOBIX0 _FCCOBIX.Bits.CCOBIX0 +#define FCCOBIX_CCOBIX1 _FCCOBIX.Bits.CCOBIX1 +#define FCCOBIX_CCOBIX2 _FCCOBIX.Bits.CCOBIX2 +#define FCCOBIX_CCOBIX _FCCOBIX.MergedBits.grpCCOBIX + +#define FCCOBIX_CCOBIX0_MASK 1U +#define FCCOBIX_CCOBIX1_MASK 2U +#define FCCOBIX_CCOBIX2_MASK 4U +#define FCCOBIX_CCOBIX_MASK 7U +#define FCCOBIX_CCOBIX_BITNUM 0U + + +/*** FPSTAT - Flash Protection Status Register; 0x00000383 ***/ +typedef union { + byte Byte; + struct { + byte WSTATACK :1; /* Wait-State Switch Acknowledge */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte FPOVRD :1; /* Flash Protection Override Status */ + } Bits; +} FPSTATSTR; +extern volatile FPSTATSTR _FPSTAT @0x00000383; +#define FPSTAT _FPSTAT.Byte +#define FPSTAT_WSTATACK _FPSTAT.Bits.WSTATACK +#define FPSTAT_FPOVRD _FPSTAT.Bits.FPOVRD + +#define FPSTAT_WSTATACK_MASK 1U +#define FPSTAT_FPOVRD_MASK 128U + + +/*** FCNFG - Flash Configuration Register; 0x00000384 ***/ +typedef union { + byte Byte; + struct { + byte FSFD :1; /* Force Single Bit Fault Detect */ + byte FDFD :1; /* Force Double Bit Fault Detect */ + byte WSTAT :2; /* Wait State control bits */ + byte IGNSF :1; /* Ignore Single Bit Fault */ + byte ERSAREQ :1; /* Erase All Request */ + byte :1; + byte CCIE :1; /* Command Complete Interrupt Enable */ + } Bits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @0x00000384; +#define FCNFG _FCNFG.Byte +#define FCNFG_FSFD _FCNFG.Bits.FSFD +#define FCNFG_FDFD _FCNFG.Bits.FDFD +#define FCNFG_WSTAT _FCNFG.Bits.WSTAT +#define FCNFG_IGNSF _FCNFG.Bits.IGNSF +#define FCNFG_ERSAREQ _FCNFG.Bits.ERSAREQ +#define FCNFG_CCIE _FCNFG.Bits.CCIE + +#define FCNFG_FSFD_MASK 1U +#define FCNFG_FDFD_MASK 2U +#define FCNFG_WSTAT_MASK 12U +#define FCNFG_WSTAT_BITNUM 2U +#define FCNFG_IGNSF_MASK 16U +#define FCNFG_ERSAREQ_MASK 32U +#define FCNFG_CCIE_MASK 128U + + +/*** FERCNFG - Flash Error Configuration Register; 0x00000385 ***/ +typedef union { + byte Byte; + struct { + byte SFDIE :1; /* Single Bit Fault Detect Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} FERCNFGSTR; +extern volatile FERCNFGSTR _FERCNFG @0x00000385; +#define FERCNFG _FERCNFG.Byte +#define FERCNFG_SFDIE _FERCNFG.Bits.SFDIE + +#define FERCNFG_SFDIE_MASK 1U + + +/*** FSTAT - Flash Status Register; 0x00000386 ***/ +typedef union { + byte Byte; + struct { + byte MGSTAT0 :1; /* Memory Controller Command Completion Status Flag 0 */ + byte MGSTAT1 :1; /* Memory Controller Command Completion Status Flag 1 */ + byte :1; + byte MGBUSY :1; /* Memory Controller Busy Flag */ + byte FPVIOL :1; /* Flash Protection Violation Flag */ + byte ACCERR :1; /* Flash Access Error Flag */ + byte :1; + byte CCIF :1; /* Command Complete Interrupt Flag */ + } Bits; + struct { + byte grpMGSTAT :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @0x00000386; +#define FSTAT _FSTAT.Byte +#define FSTAT_MGSTAT0 _FSTAT.Bits.MGSTAT0 +#define FSTAT_MGSTAT1 _FSTAT.Bits.MGSTAT1 +#define FSTAT_MGBUSY _FSTAT.Bits.MGBUSY +#define FSTAT_FPVIOL _FSTAT.Bits.FPVIOL +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_MGSTAT _FSTAT.MergedBits.grpMGSTAT + +#define FSTAT_MGSTAT0_MASK 1U +#define FSTAT_MGSTAT1_MASK 2U +#define FSTAT_MGBUSY_MASK 8U +#define FSTAT_FPVIOL_MASK 16U +#define FSTAT_ACCERR_MASK 32U +#define FSTAT_CCIF_MASK 128U +#define FSTAT_MGSTAT_MASK 3U +#define FSTAT_MGSTAT_BITNUM 0U + + +/*** FERSTAT - Flash Error Status Register; 0x00000387 ***/ +typedef union { + byte Byte; + struct { + byte SFDIF :1; /* Single Bit Fault Detect Interrupt Flag */ + byte DFDF :1; /* Double Bit Fault Detect Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} FERSTATSTR; +extern volatile FERSTATSTR _FERSTAT @0x00000387; +#define FERSTAT _FERSTAT.Byte +#define FERSTAT_SFDIF _FERSTAT.Bits.SFDIF +#define FERSTAT_DFDF _FERSTAT.Bits.DFDF + +#define FERSTAT_SFDIF_MASK 1U +#define FERSTAT_DFDF_MASK 2U + + +/*** FPROT - P-Flash Protection Register; 0x00000388 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address Size Bit 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address Size Bit 1 */ + byte FPLDIS :1; /* Flash Protection Lower Address Range Disable */ + byte FPHS0 :1; /* Flash Protection Higher Address Size Bit 0 */ + byte FPHS1 :1; /* Flash Protection Higher Address Size Bit 1 */ + byte FPHDIS :1; /* Flash Protection Higher Address Range Disable */ + byte RNV6 :1; /* Reserved Nonvolatile Bit */ + byte FPOPEN :1; /* Flash Protection Operation Enable */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpRNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @0x00000388; +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_RNV6 _FPROT.Bits.RNV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + +#define FPROT_FPLS0_MASK 1U +#define FPROT_FPLS1_MASK 2U +#define FPROT_FPLDIS_MASK 4U +#define FPROT_FPHS0_MASK 8U +#define FPROT_FPHS1_MASK 16U +#define FPROT_FPHDIS_MASK 32U +#define FPROT_RNV6_MASK 64U +#define FPROT_FPOPEN_MASK 128U +#define FPROT_FPLS_MASK 3U +#define FPROT_FPLS_BITNUM 0U +#define FPROT_FPHS_MASK 24U +#define FPROT_FPHS_BITNUM 3U + + +/*** DFPROT - D-Flash Protection Register; 0x00000389 ***/ +typedef union { + byte Byte; + struct { + byte DPS0 :1; /* D-Flash Protection Size Bit 0 */ + byte DPS1 :1; /* D-Flash Protection Size Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte DPOPEN :1; /* D-Flash Protection Control */ + } Bits; + struct { + byte grpDPS :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DFPROTSTR; +extern volatile DFPROTSTR _DFPROT @0x00000389; +#define DFPROT _DFPROT.Byte +#define DFPROT_DPS0 _DFPROT.Bits.DPS0 +#define DFPROT_DPS1 _DFPROT.Bits.DPS1 +#define DFPROT_DPOPEN _DFPROT.Bits.DPOPEN +#define DFPROT_DPS _DFPROT.MergedBits.grpDPS + +#define DFPROT_DPS0_MASK 1U +#define DFPROT_DPS1_MASK 2U +#define DFPROT_DPOPEN_MASK 128U +#define DFPROT_DPS_MASK 3U +#define DFPROT_DPS_BITNUM 0U + + +/*** FOPT - Flash Option Register; 0x0000038A ***/ +typedef union { + byte Byte; + struct { + byte NV0 :1; /* Nonvolatile Bit 0 */ + byte NV1 :1; /* Nonvolatile Bit 1 */ + byte NV2 :1; /* Nonvolatile Bit 2 */ + byte NV3 :1; /* Nonvolatile Bit 3 */ + byte NV4 :1; /* Nonvolatile Bit 4 */ + byte NV5 :1; /* Nonvolatile Bit 5 */ + byte NV6 :1; /* Nonvolatile Bit 6 */ + byte NV7 :1; /* Nonvolatile Bit 7 */ + } Bits; +} FOPTSTR; +extern volatile FOPTSTR _FOPT @0x0000038A; +#define FOPT _FOPT.Byte +#define FOPT_NV0 _FOPT.Bits.NV0 +#define FOPT_NV1 _FOPT.Bits.NV1 +#define FOPT_NV2 _FOPT.Bits.NV2 +#define FOPT_NV3 _FOPT.Bits.NV3 +#define FOPT_NV4 _FOPT.Bits.NV4 +#define FOPT_NV5 _FOPT.Bits.NV5 +#define FOPT_NV6 _FOPT.Bits.NV6 +#define FOPT_NV7 _FOPT.Bits.NV7 + +#define FOPT_NV0_MASK 1U +#define FOPT_NV1_MASK 2U +#define FOPT_NV2_MASK 4U +#define FOPT_NV3_MASK 8U +#define FOPT_NV4_MASK 16U +#define FOPT_NV5_MASK 32U +#define FOPT_NV6_MASK 64U +#define FOPT_NV7_MASK 128U + + +/*** FCCOB0 - Flash Common Command Object Register; 0x0000038C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB0HI - Flash Common Command Object Register High; 0x0000038C ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB0HISTR; + #define FCCOB0HI _FCCOB0.Overlap_STR.FCCOB0HISTR.Byte + #define FCCOB0HI_CCOB8 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB8 + #define FCCOB0HI_CCOB9 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB9 + #define FCCOB0HI_CCOB10 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB10 + #define FCCOB0HI_CCOB11 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB11 + #define FCCOB0HI_CCOB12 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB12 + #define FCCOB0HI_CCOB13 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB13 + #define FCCOB0HI_CCOB14 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB14 + #define FCCOB0HI_CCOB15 _FCCOB0.Overlap_STR.FCCOB0HISTR.Bits.CCOB15 + + #define FCCOB0HI_CCOB8_MASK 1U + #define FCCOB0HI_CCOB9_MASK 2U + #define FCCOB0HI_CCOB10_MASK 4U + #define FCCOB0HI_CCOB11_MASK 8U + #define FCCOB0HI_CCOB12_MASK 16U + #define FCCOB0HI_CCOB13_MASK 32U + #define FCCOB0HI_CCOB14_MASK 64U + #define FCCOB0HI_CCOB15_MASK 128U + + + /*** FCCOB0LO - Flash Common Command Object Register Low; 0x0000038D ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB0LOSTR; + #define FCCOB0LO _FCCOB0.Overlap_STR.FCCOB0LOSTR.Byte + #define FCCOB0LO_CCOB0 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB0 + #define FCCOB0LO_CCOB1 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB1 + #define FCCOB0LO_CCOB2 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB2 + #define FCCOB0LO_CCOB3 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB3 + #define FCCOB0LO_CCOB4 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB4 + #define FCCOB0LO_CCOB5 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB5 + #define FCCOB0LO_CCOB6 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB6 + #define FCCOB0LO_CCOB7 _FCCOB0.Overlap_STR.FCCOB0LOSTR.Bits.CCOB7 + + #define FCCOB0LO_CCOB0_MASK 1U + #define FCCOB0LO_CCOB1_MASK 2U + #define FCCOB0LO_CCOB2_MASK 4U + #define FCCOB0LO_CCOB3_MASK 8U + #define FCCOB0LO_CCOB4_MASK 16U + #define FCCOB0LO_CCOB5_MASK 32U + #define FCCOB0LO_CCOB6_MASK 64U + #define FCCOB0LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB0STR; +extern volatile FCCOB0STR _FCCOB0 @0x0000038C; +#define FCCOB0 _FCCOB0.Word +#define FCCOB0_CCOB0 _FCCOB0.Bits.CCOB0 +#define FCCOB0_CCOB1 _FCCOB0.Bits.CCOB1 +#define FCCOB0_CCOB2 _FCCOB0.Bits.CCOB2 +#define FCCOB0_CCOB3 _FCCOB0.Bits.CCOB3 +#define FCCOB0_CCOB4 _FCCOB0.Bits.CCOB4 +#define FCCOB0_CCOB5 _FCCOB0.Bits.CCOB5 +#define FCCOB0_CCOB6 _FCCOB0.Bits.CCOB6 +#define FCCOB0_CCOB7 _FCCOB0.Bits.CCOB7 +#define FCCOB0_CCOB8 _FCCOB0.Bits.CCOB8 +#define FCCOB0_CCOB9 _FCCOB0.Bits.CCOB9 +#define FCCOB0_CCOB10 _FCCOB0.Bits.CCOB10 +#define FCCOB0_CCOB11 _FCCOB0.Bits.CCOB11 +#define FCCOB0_CCOB12 _FCCOB0.Bits.CCOB12 +#define FCCOB0_CCOB13 _FCCOB0.Bits.CCOB13 +#define FCCOB0_CCOB14 _FCCOB0.Bits.CCOB14 +#define FCCOB0_CCOB15 _FCCOB0.Bits.CCOB15 +/* FCCOB_ARR: Access 6 FCCOBx registers in an array */ +#define FCCOB_ARR ((volatile word *) &FCCOB0) + +#define FCCOB0_CCOB0_MASK 1U +#define FCCOB0_CCOB1_MASK 2U +#define FCCOB0_CCOB2_MASK 4U +#define FCCOB0_CCOB3_MASK 8U +#define FCCOB0_CCOB4_MASK 16U +#define FCCOB0_CCOB5_MASK 32U +#define FCCOB0_CCOB6_MASK 64U +#define FCCOB0_CCOB7_MASK 128U +#define FCCOB0_CCOB8_MASK 256U +#define FCCOB0_CCOB9_MASK 512U +#define FCCOB0_CCOB10_MASK 1024U +#define FCCOB0_CCOB11_MASK 2048U +#define FCCOB0_CCOB12_MASK 4096U +#define FCCOB0_CCOB13_MASK 8192U +#define FCCOB0_CCOB14_MASK 16384U +#define FCCOB0_CCOB15_MASK 32768U + + +/*** FCCOB1 - Flash Common Command Object Register; 0x0000038E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB1HI - Flash Common Command Object Register High; 0x0000038E ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB1HISTR; + #define FCCOB1HI _FCCOB1.Overlap_STR.FCCOB1HISTR.Byte + #define FCCOB1HI_CCOB8 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB8 + #define FCCOB1HI_CCOB9 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB9 + #define FCCOB1HI_CCOB10 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB10 + #define FCCOB1HI_CCOB11 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB11 + #define FCCOB1HI_CCOB12 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB12 + #define FCCOB1HI_CCOB13 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB13 + #define FCCOB1HI_CCOB14 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB14 + #define FCCOB1HI_CCOB15 _FCCOB1.Overlap_STR.FCCOB1HISTR.Bits.CCOB15 + + #define FCCOB1HI_CCOB8_MASK 1U + #define FCCOB1HI_CCOB9_MASK 2U + #define FCCOB1HI_CCOB10_MASK 4U + #define FCCOB1HI_CCOB11_MASK 8U + #define FCCOB1HI_CCOB12_MASK 16U + #define FCCOB1HI_CCOB13_MASK 32U + #define FCCOB1HI_CCOB14_MASK 64U + #define FCCOB1HI_CCOB15_MASK 128U + + + /*** FCCOB1LO - Flash Common Command Object Register Low; 0x0000038F ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB1LOSTR; + #define FCCOB1LO _FCCOB1.Overlap_STR.FCCOB1LOSTR.Byte + #define FCCOB1LO_CCOB0 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB0 + #define FCCOB1LO_CCOB1 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB1 + #define FCCOB1LO_CCOB2 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB2 + #define FCCOB1LO_CCOB3 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB3 + #define FCCOB1LO_CCOB4 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB4 + #define FCCOB1LO_CCOB5 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB5 + #define FCCOB1LO_CCOB6 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB6 + #define FCCOB1LO_CCOB7 _FCCOB1.Overlap_STR.FCCOB1LOSTR.Bits.CCOB7 + + #define FCCOB1LO_CCOB0_MASK 1U + #define FCCOB1LO_CCOB1_MASK 2U + #define FCCOB1LO_CCOB2_MASK 4U + #define FCCOB1LO_CCOB3_MASK 8U + #define FCCOB1LO_CCOB4_MASK 16U + #define FCCOB1LO_CCOB5_MASK 32U + #define FCCOB1LO_CCOB6_MASK 64U + #define FCCOB1LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB1STR; +extern volatile FCCOB1STR _FCCOB1 @0x0000038E; +#define FCCOB1 _FCCOB1.Word +#define FCCOB1_CCOB0 _FCCOB1.Bits.CCOB0 +#define FCCOB1_CCOB1 _FCCOB1.Bits.CCOB1 +#define FCCOB1_CCOB2 _FCCOB1.Bits.CCOB2 +#define FCCOB1_CCOB3 _FCCOB1.Bits.CCOB3 +#define FCCOB1_CCOB4 _FCCOB1.Bits.CCOB4 +#define FCCOB1_CCOB5 _FCCOB1.Bits.CCOB5 +#define FCCOB1_CCOB6 _FCCOB1.Bits.CCOB6 +#define FCCOB1_CCOB7 _FCCOB1.Bits.CCOB7 +#define FCCOB1_CCOB8 _FCCOB1.Bits.CCOB8 +#define FCCOB1_CCOB9 _FCCOB1.Bits.CCOB9 +#define FCCOB1_CCOB10 _FCCOB1.Bits.CCOB10 +#define FCCOB1_CCOB11 _FCCOB1.Bits.CCOB11 +#define FCCOB1_CCOB12 _FCCOB1.Bits.CCOB12 +#define FCCOB1_CCOB13 _FCCOB1.Bits.CCOB13 +#define FCCOB1_CCOB14 _FCCOB1.Bits.CCOB14 +#define FCCOB1_CCOB15 _FCCOB1.Bits.CCOB15 + +#define FCCOB1_CCOB0_MASK 1U +#define FCCOB1_CCOB1_MASK 2U +#define FCCOB1_CCOB2_MASK 4U +#define FCCOB1_CCOB3_MASK 8U +#define FCCOB1_CCOB4_MASK 16U +#define FCCOB1_CCOB5_MASK 32U +#define FCCOB1_CCOB6_MASK 64U +#define FCCOB1_CCOB7_MASK 128U +#define FCCOB1_CCOB8_MASK 256U +#define FCCOB1_CCOB9_MASK 512U +#define FCCOB1_CCOB10_MASK 1024U +#define FCCOB1_CCOB11_MASK 2048U +#define FCCOB1_CCOB12_MASK 4096U +#define FCCOB1_CCOB13_MASK 8192U +#define FCCOB1_CCOB14_MASK 16384U +#define FCCOB1_CCOB15_MASK 32768U + + +/*** FCCOB2 - Flash Common Command Object Register; 0x00000390 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB2HI - Flash Common Command Object Register High; 0x00000390 ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB2HISTR; + #define FCCOB2HI _FCCOB2.Overlap_STR.FCCOB2HISTR.Byte + #define FCCOB2HI_CCOB8 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB8 + #define FCCOB2HI_CCOB9 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB9 + #define FCCOB2HI_CCOB10 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB10 + #define FCCOB2HI_CCOB11 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB11 + #define FCCOB2HI_CCOB12 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB12 + #define FCCOB2HI_CCOB13 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB13 + #define FCCOB2HI_CCOB14 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB14 + #define FCCOB2HI_CCOB15 _FCCOB2.Overlap_STR.FCCOB2HISTR.Bits.CCOB15 + + #define FCCOB2HI_CCOB8_MASK 1U + #define FCCOB2HI_CCOB9_MASK 2U + #define FCCOB2HI_CCOB10_MASK 4U + #define FCCOB2HI_CCOB11_MASK 8U + #define FCCOB2HI_CCOB12_MASK 16U + #define FCCOB2HI_CCOB13_MASK 32U + #define FCCOB2HI_CCOB14_MASK 64U + #define FCCOB2HI_CCOB15_MASK 128U + + + /*** FCCOB2LO - Flash Common Command Object Register Low; 0x00000391 ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB2LOSTR; + #define FCCOB2LO _FCCOB2.Overlap_STR.FCCOB2LOSTR.Byte + #define FCCOB2LO_CCOB0 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB0 + #define FCCOB2LO_CCOB1 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB1 + #define FCCOB2LO_CCOB2 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB2 + #define FCCOB2LO_CCOB3 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB3 + #define FCCOB2LO_CCOB4 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB4 + #define FCCOB2LO_CCOB5 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB5 + #define FCCOB2LO_CCOB6 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB6 + #define FCCOB2LO_CCOB7 _FCCOB2.Overlap_STR.FCCOB2LOSTR.Bits.CCOB7 + + #define FCCOB2LO_CCOB0_MASK 1U + #define FCCOB2LO_CCOB1_MASK 2U + #define FCCOB2LO_CCOB2_MASK 4U + #define FCCOB2LO_CCOB3_MASK 8U + #define FCCOB2LO_CCOB4_MASK 16U + #define FCCOB2LO_CCOB5_MASK 32U + #define FCCOB2LO_CCOB6_MASK 64U + #define FCCOB2LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB2STR; +extern volatile FCCOB2STR _FCCOB2 @0x00000390; +#define FCCOB2 _FCCOB2.Word +#define FCCOB2_CCOB0 _FCCOB2.Bits.CCOB0 +#define FCCOB2_CCOB1 _FCCOB2.Bits.CCOB1 +#define FCCOB2_CCOB2 _FCCOB2.Bits.CCOB2 +#define FCCOB2_CCOB3 _FCCOB2.Bits.CCOB3 +#define FCCOB2_CCOB4 _FCCOB2.Bits.CCOB4 +#define FCCOB2_CCOB5 _FCCOB2.Bits.CCOB5 +#define FCCOB2_CCOB6 _FCCOB2.Bits.CCOB6 +#define FCCOB2_CCOB7 _FCCOB2.Bits.CCOB7 +#define FCCOB2_CCOB8 _FCCOB2.Bits.CCOB8 +#define FCCOB2_CCOB9 _FCCOB2.Bits.CCOB9 +#define FCCOB2_CCOB10 _FCCOB2.Bits.CCOB10 +#define FCCOB2_CCOB11 _FCCOB2.Bits.CCOB11 +#define FCCOB2_CCOB12 _FCCOB2.Bits.CCOB12 +#define FCCOB2_CCOB13 _FCCOB2.Bits.CCOB13 +#define FCCOB2_CCOB14 _FCCOB2.Bits.CCOB14 +#define FCCOB2_CCOB15 _FCCOB2.Bits.CCOB15 + +#define FCCOB2_CCOB0_MASK 1U +#define FCCOB2_CCOB1_MASK 2U +#define FCCOB2_CCOB2_MASK 4U +#define FCCOB2_CCOB3_MASK 8U +#define FCCOB2_CCOB4_MASK 16U +#define FCCOB2_CCOB5_MASK 32U +#define FCCOB2_CCOB6_MASK 64U +#define FCCOB2_CCOB7_MASK 128U +#define FCCOB2_CCOB8_MASK 256U +#define FCCOB2_CCOB9_MASK 512U +#define FCCOB2_CCOB10_MASK 1024U +#define FCCOB2_CCOB11_MASK 2048U +#define FCCOB2_CCOB12_MASK 4096U +#define FCCOB2_CCOB13_MASK 8192U +#define FCCOB2_CCOB14_MASK 16384U +#define FCCOB2_CCOB15_MASK 32768U + + +/*** FCCOB3 - Flash Common Command Object Register; 0x00000392 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB3HI - Flash Common Command Object Register High; 0x00000392 ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB3HISTR; + #define FCCOB3HI _FCCOB3.Overlap_STR.FCCOB3HISTR.Byte + #define FCCOB3HI_CCOB8 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB8 + #define FCCOB3HI_CCOB9 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB9 + #define FCCOB3HI_CCOB10 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB10 + #define FCCOB3HI_CCOB11 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB11 + #define FCCOB3HI_CCOB12 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB12 + #define FCCOB3HI_CCOB13 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB13 + #define FCCOB3HI_CCOB14 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB14 + #define FCCOB3HI_CCOB15 _FCCOB3.Overlap_STR.FCCOB3HISTR.Bits.CCOB15 + + #define FCCOB3HI_CCOB8_MASK 1U + #define FCCOB3HI_CCOB9_MASK 2U + #define FCCOB3HI_CCOB10_MASK 4U + #define FCCOB3HI_CCOB11_MASK 8U + #define FCCOB3HI_CCOB12_MASK 16U + #define FCCOB3HI_CCOB13_MASK 32U + #define FCCOB3HI_CCOB14_MASK 64U + #define FCCOB3HI_CCOB15_MASK 128U + + + /*** FCCOB3LO - Flash Common Command Object Register Low; 0x00000393 ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB3LOSTR; + #define FCCOB3LO _FCCOB3.Overlap_STR.FCCOB3LOSTR.Byte + #define FCCOB3LO_CCOB0 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB0 + #define FCCOB3LO_CCOB1 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB1 + #define FCCOB3LO_CCOB2 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB2 + #define FCCOB3LO_CCOB3 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB3 + #define FCCOB3LO_CCOB4 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB4 + #define FCCOB3LO_CCOB5 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB5 + #define FCCOB3LO_CCOB6 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB6 + #define FCCOB3LO_CCOB7 _FCCOB3.Overlap_STR.FCCOB3LOSTR.Bits.CCOB7 + + #define FCCOB3LO_CCOB0_MASK 1U + #define FCCOB3LO_CCOB1_MASK 2U + #define FCCOB3LO_CCOB2_MASK 4U + #define FCCOB3LO_CCOB3_MASK 8U + #define FCCOB3LO_CCOB4_MASK 16U + #define FCCOB3LO_CCOB5_MASK 32U + #define FCCOB3LO_CCOB6_MASK 64U + #define FCCOB3LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB3STR; +extern volatile FCCOB3STR _FCCOB3 @0x00000392; +#define FCCOB3 _FCCOB3.Word +#define FCCOB3_CCOB0 _FCCOB3.Bits.CCOB0 +#define FCCOB3_CCOB1 _FCCOB3.Bits.CCOB1 +#define FCCOB3_CCOB2 _FCCOB3.Bits.CCOB2 +#define FCCOB3_CCOB3 _FCCOB3.Bits.CCOB3 +#define FCCOB3_CCOB4 _FCCOB3.Bits.CCOB4 +#define FCCOB3_CCOB5 _FCCOB3.Bits.CCOB5 +#define FCCOB3_CCOB6 _FCCOB3.Bits.CCOB6 +#define FCCOB3_CCOB7 _FCCOB3.Bits.CCOB7 +#define FCCOB3_CCOB8 _FCCOB3.Bits.CCOB8 +#define FCCOB3_CCOB9 _FCCOB3.Bits.CCOB9 +#define FCCOB3_CCOB10 _FCCOB3.Bits.CCOB10 +#define FCCOB3_CCOB11 _FCCOB3.Bits.CCOB11 +#define FCCOB3_CCOB12 _FCCOB3.Bits.CCOB12 +#define FCCOB3_CCOB13 _FCCOB3.Bits.CCOB13 +#define FCCOB3_CCOB14 _FCCOB3.Bits.CCOB14 +#define FCCOB3_CCOB15 _FCCOB3.Bits.CCOB15 + +#define FCCOB3_CCOB0_MASK 1U +#define FCCOB3_CCOB1_MASK 2U +#define FCCOB3_CCOB2_MASK 4U +#define FCCOB3_CCOB3_MASK 8U +#define FCCOB3_CCOB4_MASK 16U +#define FCCOB3_CCOB5_MASK 32U +#define FCCOB3_CCOB6_MASK 64U +#define FCCOB3_CCOB7_MASK 128U +#define FCCOB3_CCOB8_MASK 256U +#define FCCOB3_CCOB9_MASK 512U +#define FCCOB3_CCOB10_MASK 1024U +#define FCCOB3_CCOB11_MASK 2048U +#define FCCOB3_CCOB12_MASK 4096U +#define FCCOB3_CCOB13_MASK 8192U +#define FCCOB3_CCOB14_MASK 16384U +#define FCCOB3_CCOB15_MASK 32768U + + +/*** FCCOB4 - Flash Common Command Object Register; 0x00000394 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB4HI - Flash Common Command Object Register High; 0x00000394 ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB4HISTR; + #define FCCOB4HI _FCCOB4.Overlap_STR.FCCOB4HISTR.Byte + #define FCCOB4HI_CCOB8 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB8 + #define FCCOB4HI_CCOB9 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB9 + #define FCCOB4HI_CCOB10 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB10 + #define FCCOB4HI_CCOB11 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB11 + #define FCCOB4HI_CCOB12 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB12 + #define FCCOB4HI_CCOB13 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB13 + #define FCCOB4HI_CCOB14 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB14 + #define FCCOB4HI_CCOB15 _FCCOB4.Overlap_STR.FCCOB4HISTR.Bits.CCOB15 + + #define FCCOB4HI_CCOB8_MASK 1U + #define FCCOB4HI_CCOB9_MASK 2U + #define FCCOB4HI_CCOB10_MASK 4U + #define FCCOB4HI_CCOB11_MASK 8U + #define FCCOB4HI_CCOB12_MASK 16U + #define FCCOB4HI_CCOB13_MASK 32U + #define FCCOB4HI_CCOB14_MASK 64U + #define FCCOB4HI_CCOB15_MASK 128U + + + /*** FCCOB4LO - Flash Common Command Object Register Low; 0x00000395 ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB4LOSTR; + #define FCCOB4LO _FCCOB4.Overlap_STR.FCCOB4LOSTR.Byte + #define FCCOB4LO_CCOB0 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB0 + #define FCCOB4LO_CCOB1 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB1 + #define FCCOB4LO_CCOB2 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB2 + #define FCCOB4LO_CCOB3 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB3 + #define FCCOB4LO_CCOB4 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB4 + #define FCCOB4LO_CCOB5 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB5 + #define FCCOB4LO_CCOB6 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB6 + #define FCCOB4LO_CCOB7 _FCCOB4.Overlap_STR.FCCOB4LOSTR.Bits.CCOB7 + + #define FCCOB4LO_CCOB0_MASK 1U + #define FCCOB4LO_CCOB1_MASK 2U + #define FCCOB4LO_CCOB2_MASK 4U + #define FCCOB4LO_CCOB3_MASK 8U + #define FCCOB4LO_CCOB4_MASK 16U + #define FCCOB4LO_CCOB5_MASK 32U + #define FCCOB4LO_CCOB6_MASK 64U + #define FCCOB4LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB4STR; +extern volatile FCCOB4STR _FCCOB4 @0x00000394; +#define FCCOB4 _FCCOB4.Word +#define FCCOB4_CCOB0 _FCCOB4.Bits.CCOB0 +#define FCCOB4_CCOB1 _FCCOB4.Bits.CCOB1 +#define FCCOB4_CCOB2 _FCCOB4.Bits.CCOB2 +#define FCCOB4_CCOB3 _FCCOB4.Bits.CCOB3 +#define FCCOB4_CCOB4 _FCCOB4.Bits.CCOB4 +#define FCCOB4_CCOB5 _FCCOB4.Bits.CCOB5 +#define FCCOB4_CCOB6 _FCCOB4.Bits.CCOB6 +#define FCCOB4_CCOB7 _FCCOB4.Bits.CCOB7 +#define FCCOB4_CCOB8 _FCCOB4.Bits.CCOB8 +#define FCCOB4_CCOB9 _FCCOB4.Bits.CCOB9 +#define FCCOB4_CCOB10 _FCCOB4.Bits.CCOB10 +#define FCCOB4_CCOB11 _FCCOB4.Bits.CCOB11 +#define FCCOB4_CCOB12 _FCCOB4.Bits.CCOB12 +#define FCCOB4_CCOB13 _FCCOB4.Bits.CCOB13 +#define FCCOB4_CCOB14 _FCCOB4.Bits.CCOB14 +#define FCCOB4_CCOB15 _FCCOB4.Bits.CCOB15 + +#define FCCOB4_CCOB0_MASK 1U +#define FCCOB4_CCOB1_MASK 2U +#define FCCOB4_CCOB2_MASK 4U +#define FCCOB4_CCOB3_MASK 8U +#define FCCOB4_CCOB4_MASK 16U +#define FCCOB4_CCOB5_MASK 32U +#define FCCOB4_CCOB6_MASK 64U +#define FCCOB4_CCOB7_MASK 128U +#define FCCOB4_CCOB8_MASK 256U +#define FCCOB4_CCOB9_MASK 512U +#define FCCOB4_CCOB10_MASK 1024U +#define FCCOB4_CCOB11_MASK 2048U +#define FCCOB4_CCOB12_MASK 4096U +#define FCCOB4_CCOB13_MASK 8192U +#define FCCOB4_CCOB14_MASK 16384U +#define FCCOB4_CCOB15_MASK 32768U + + +/*** FCCOB5 - Flash Common Command Object Register; 0x00000396 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** FCCOB5HI - Flash Common Command Object Register High; 0x00000396 ***/ + union { + byte Byte; + struct { + byte CCOB8 :1; /* Flash Common Command Object Bit 8 */ + byte CCOB9 :1; /* Flash Common Command Object Bit 9 */ + byte CCOB10 :1; /* Flash Common Command Object Bit 10 */ + byte CCOB11 :1; /* Flash Common Command Object Bit 11 */ + byte CCOB12 :1; /* Flash Common Command Object Bit 12 */ + byte CCOB13 :1; /* Flash Common Command Object Bit 13 */ + byte CCOB14 :1; /* Flash Common Command Object Bit 14 */ + byte CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; + } FCCOB5HISTR; + #define FCCOB5HI _FCCOB5.Overlap_STR.FCCOB5HISTR.Byte + #define FCCOB5HI_CCOB8 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB8 + #define FCCOB5HI_CCOB9 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB9 + #define FCCOB5HI_CCOB10 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB10 + #define FCCOB5HI_CCOB11 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB11 + #define FCCOB5HI_CCOB12 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB12 + #define FCCOB5HI_CCOB13 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB13 + #define FCCOB5HI_CCOB14 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB14 + #define FCCOB5HI_CCOB15 _FCCOB5.Overlap_STR.FCCOB5HISTR.Bits.CCOB15 + + #define FCCOB5HI_CCOB8_MASK 1U + #define FCCOB5HI_CCOB9_MASK 2U + #define FCCOB5HI_CCOB10_MASK 4U + #define FCCOB5HI_CCOB11_MASK 8U + #define FCCOB5HI_CCOB12_MASK 16U + #define FCCOB5HI_CCOB13_MASK 32U + #define FCCOB5HI_CCOB14_MASK 64U + #define FCCOB5HI_CCOB15_MASK 128U + + + /*** FCCOB5LO - Flash Common Command Object Register Low; 0x00000397 ***/ + union { + byte Byte; + struct { + byte CCOB0 :1; /* Flash Common Command Object Bit 0 */ + byte CCOB1 :1; /* Flash Common Command Object Bit 1 */ + byte CCOB2 :1; /* Flash Common Command Object Bit 2 */ + byte CCOB3 :1; /* Flash Common Command Object Bit 3 */ + byte CCOB4 :1; /* Flash Common Command Object Bit 4 */ + byte CCOB5 :1; /* Flash Common Command Object Bit 5 */ + byte CCOB6 :1; /* Flash Common Command Object Bit 6 */ + byte CCOB7 :1; /* Flash Common Command Object Bit 7 */ + } Bits; + } FCCOB5LOSTR; + #define FCCOB5LO _FCCOB5.Overlap_STR.FCCOB5LOSTR.Byte + #define FCCOB5LO_CCOB0 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB0 + #define FCCOB5LO_CCOB1 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB1 + #define FCCOB5LO_CCOB2 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB2 + #define FCCOB5LO_CCOB3 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB3 + #define FCCOB5LO_CCOB4 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB4 + #define FCCOB5LO_CCOB5 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB5 + #define FCCOB5LO_CCOB6 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB6 + #define FCCOB5LO_CCOB7 _FCCOB5.Overlap_STR.FCCOB5LOSTR.Bits.CCOB7 + + #define FCCOB5LO_CCOB0_MASK 1U + #define FCCOB5LO_CCOB1_MASK 2U + #define FCCOB5LO_CCOB2_MASK 4U + #define FCCOB5LO_CCOB3_MASK 8U + #define FCCOB5LO_CCOB4_MASK 16U + #define FCCOB5LO_CCOB5_MASK 32U + #define FCCOB5LO_CCOB6_MASK 64U + #define FCCOB5LO_CCOB7_MASK 128U + + } Overlap_STR; + + struct { + word CCOB0 :1; /* Flash Common Command Object Bit 0 */ + word CCOB1 :1; /* Flash Common Command Object Bit 1 */ + word CCOB2 :1; /* Flash Common Command Object Bit 2 */ + word CCOB3 :1; /* Flash Common Command Object Bit 3 */ + word CCOB4 :1; /* Flash Common Command Object Bit 4 */ + word CCOB5 :1; /* Flash Common Command Object Bit 5 */ + word CCOB6 :1; /* Flash Common Command Object Bit 6 */ + word CCOB7 :1; /* Flash Common Command Object Bit 7 */ + word CCOB8 :1; /* Flash Common Command Object Bit 8 */ + word CCOB9 :1; /* Flash Common Command Object Bit 9 */ + word CCOB10 :1; /* Flash Common Command Object Bit 10 */ + word CCOB11 :1; /* Flash Common Command Object Bit 11 */ + word CCOB12 :1; /* Flash Common Command Object Bit 12 */ + word CCOB13 :1; /* Flash Common Command Object Bit 13 */ + word CCOB14 :1; /* Flash Common Command Object Bit 14 */ + word CCOB15 :1; /* Flash Common Command Object Bit 15 */ + } Bits; +} FCCOB5STR; +extern volatile FCCOB5STR _FCCOB5 @0x00000396; +#define FCCOB5 _FCCOB5.Word +#define FCCOB5_CCOB0 _FCCOB5.Bits.CCOB0 +#define FCCOB5_CCOB1 _FCCOB5.Bits.CCOB1 +#define FCCOB5_CCOB2 _FCCOB5.Bits.CCOB2 +#define FCCOB5_CCOB3 _FCCOB5.Bits.CCOB3 +#define FCCOB5_CCOB4 _FCCOB5.Bits.CCOB4 +#define FCCOB5_CCOB5 _FCCOB5.Bits.CCOB5 +#define FCCOB5_CCOB6 _FCCOB5.Bits.CCOB6 +#define FCCOB5_CCOB7 _FCCOB5.Bits.CCOB7 +#define FCCOB5_CCOB8 _FCCOB5.Bits.CCOB8 +#define FCCOB5_CCOB9 _FCCOB5.Bits.CCOB9 +#define FCCOB5_CCOB10 _FCCOB5.Bits.CCOB10 +#define FCCOB5_CCOB11 _FCCOB5.Bits.CCOB11 +#define FCCOB5_CCOB12 _FCCOB5.Bits.CCOB12 +#define FCCOB5_CCOB13 _FCCOB5.Bits.CCOB13 +#define FCCOB5_CCOB14 _FCCOB5.Bits.CCOB14 +#define FCCOB5_CCOB15 _FCCOB5.Bits.CCOB15 + +#define FCCOB5_CCOB0_MASK 1U +#define FCCOB5_CCOB1_MASK 2U +#define FCCOB5_CCOB2_MASK 4U +#define FCCOB5_CCOB3_MASK 8U +#define FCCOB5_CCOB4_MASK 16U +#define FCCOB5_CCOB5_MASK 32U +#define FCCOB5_CCOB6_MASK 64U +#define FCCOB5_CCOB7_MASK 128U +#define FCCOB5_CCOB8_MASK 256U +#define FCCOB5_CCOB9_MASK 512U +#define FCCOB5_CCOB10_MASK 1024U +#define FCCOB5_CCOB11_MASK 2048U +#define FCCOB5_CCOB12_MASK 4096U +#define FCCOB5_CCOB13_MASK 8192U +#define FCCOB5_CCOB14_MASK 16384U +#define FCCOB5_CCOB15_MASK 32768U + + +/*** ECCSTAT - ECC Status Register; 0x000003C0 ***/ +typedef union { + byte Byte; + struct { + byte RDY :1; /* ECC Ready */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ECCSTATSTR; +extern volatile ECCSTATSTR _ECCSTAT @0x000003C0; +#define ECCSTAT _ECCSTAT.Byte +#define ECCSTAT_RDY _ECCSTAT.Bits.RDY + +#define ECCSTAT_RDY_MASK 1U + + +/*** ECCIE - ECC Interrupt Enable Register; 0x000003C1 ***/ +typedef union { + byte Byte; + struct { + byte SBEEIE :1; /* Single Bit ECC Error Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ECCIESTR; +extern volatile ECCIESTR _ECCIE @0x000003C1; +#define ECCIE _ECCIE.Byte +#define ECCIE_SBEEIE _ECCIE.Bits.SBEEIE + +#define ECCIE_SBEEIE_MASK 1U + + +/*** ECCIF - ECC Interrupt Flag Register; 0x000003C2 ***/ +typedef union { + byte Byte; + struct { + byte SBEEIF :1; /* Single bit ECC Error Interrupt Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ECCIFSTR; +extern volatile ECCIFSTR _ECCIF @0x000003C2; +#define ECCIF _ECCIF.Byte +#define ECCIF_SBEEIF _ECCIF.Bits.SBEEIF + +#define ECCIF_SBEEIF_MASK 1U + + +/*** ECCDPTRH - ECC Debug Point Register High; 0x000003C7 ***/ +typedef union { + byte Byte; + struct { + byte DPTR :8; /* ECC Debug Pointer */ + } Bits; +} ECCDPTRHSTR; +extern volatile ECCDPTRHSTR _ECCDPTRH @0x000003C7; +#define ECCDPTRH _ECCDPTRH.Byte +#define ECCDPTRH_DPTR _ECCDPTRH.Bits.DPTR + +#define ECCDPTRH_DPTR_MASK 255U +#define ECCDPTRH_DPTR_BITNUM 0U + + +/*** ECCDPTRM - ECC Debug Point Register Middle; 0x000003C8 ***/ +typedef union { + byte Byte; + struct { + byte DPTR :8; /* ECC Debug Pointer */ + } Bits; +} ECCDPTRMSTR; +extern volatile ECCDPTRMSTR _ECCDPTRM @0x000003C8; +#define ECCDPTRM _ECCDPTRM.Byte +#define ECCDPTRM_DPTR _ECCDPTRM.Bits.DPTR + +#define ECCDPTRM_DPTR_MASK 255U +#define ECCDPTRM_DPTR_BITNUM 0U + + +/*** ECCDPTRL - ECC Debug Point Register Low; 0x000003C9 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte DPTR :7; /* ECC Debug Pointer */ + } Bits; +} ECCDPTRLSTR; +extern volatile ECCDPTRLSTR _ECCDPTRL @0x000003C9; +#define ECCDPTRL _ECCDPTRL.Byte +#define ECCDPTRL_DPTR _ECCDPTRL.Bits.DPTR + +#define ECCDPTRL_DPTR_MASK 254U +#define ECCDPTRL_DPTR_BITNUM 1U + + +/*** ECCDD - ECC Debug Data; 0x000003CC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ECCDDH - ECC Debug Data High; 0x000003CC ***/ + union { + byte Byte; + struct { + byte DDATA :8; /* ECC Debug Data */ + } Bits; + } ECCDDHSTR; + #define ECCDDH _ECCDD.Overlap_STR.ECCDDHSTR.Byte + #define ECCDDH_DDATA _ECCDD.Overlap_STR.ECCDDHSTR.Bits.DDATA + + #define ECCDDH_DDATA_MASK 255U + #define ECCDDH_DDATA_BITNUM 0U + + + /*** ECCDDL - ECC Debug Data Low; 0x000003CD ***/ + union { + byte Byte; + struct { + byte DDATA :8; /* ECC Debug Data */ + } Bits; + } ECCDDLSTR; + #define ECCDDL _ECCDD.Overlap_STR.ECCDDLSTR.Byte + #define ECCDDL_DDATA _ECCDD.Overlap_STR.ECCDDLSTR.Bits.DDATA + + #define ECCDDL_DDATA_MASK 255U + #define ECCDDL_DDATA_BITNUM 0U + + } Overlap_STR; + + struct { + word DDATA :16; /* ECC Debug Data */ + } Bits; +} ECCDDSTR; +extern volatile ECCDDSTR _ECCDD @0x000003CC; +#define ECCDD _ECCDD.Word +#define ECCDD_DDATA _ECCDD.Bits.DDATA + +#define ECCDD_DDATA_MASK 65535U +#define ECCDD_DDATA_BITNUM 0U + + +/*** ECCDE - ECC Debug ECC; 0x000003CE ***/ +typedef union { + byte Byte; + struct { + byte DECC :6; /* ECC Debug ECC */ + byte :1; + byte :1; + } Bits; +} ECCDESTR; +extern volatile ECCDESTR _ECCDE @0x000003CE; +#define ECCDE _ECCDE.Byte +#define ECCDE_DECC _ECCDE.Bits.DECC + +#define ECCDE_DECC_MASK 63U +#define ECCDE_DECC_BITNUM 0U + + +/*** ECCDCMD - ECC Debug Comamnd; 0x000003CF ***/ +typedef union { + byte Byte; + struct { + byte ECCDR :1; /* ECC Debug Read Command */ + byte ECCDW :1; /* ECC Debug Write Command */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte ECCDRR :1; /* ECC Disable Read Repair Function */ + } Bits; +} ECCDCMDSTR; +extern volatile ECCDCMDSTR _ECCDCMD @0x000003CF; +#define ECCDCMD _ECCDCMD.Byte +#define ECCDCMD_ECCDR _ECCDCMD.Bits.ECCDR +#define ECCDCMD_ECCDW _ECCDCMD.Bits.ECCDW +#define ECCDCMD_ECCDRR _ECCDCMD.Bits.ECCDRR + +#define ECCDCMD_ECCDR_MASK 1U +#define ECCDCMD_ECCDW_MASK 2U +#define ECCDCMD_ECCDRR_MASK 128U + + +/*** TIM1TIOS - Timer Input Capture/Output Compare Select; 0x00000400 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpIOS :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1TIOSSTR; +extern volatile TIM1TIOSSTR _TIM1TIOS @0x00000400; +#define TIM1TIOS _TIM1TIOS.Byte +#define TIM1TIOS_IOS0 _TIM1TIOS.Bits.IOS0 +#define TIM1TIOS_IOS1 _TIM1TIOS.Bits.IOS1 +#define TIM1TIOS_IOS _TIM1TIOS.MergedBits.grpIOS + +#define TIM1TIOS_IOS0_MASK 1U +#define TIM1TIOS_IOS1_MASK 2U +#define TIM1TIOS_IOS_MASK 3U +#define TIM1TIOS_IOS_BITNUM 0U + + +/*** TIM1CFORC - Timer Compare Force Register; 0x00000401 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpFOC :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1CFORCSTR; +extern volatile TIM1CFORCSTR _TIM1CFORC @0x00000401; +#define TIM1CFORC _TIM1CFORC.Byte +#define TIM1CFORC_FOC0 _TIM1CFORC.Bits.FOC0 +#define TIM1CFORC_FOC1 _TIM1CFORC.Bits.FOC1 +#define TIM1CFORC_FOC _TIM1CFORC.MergedBits.grpFOC + +#define TIM1CFORC_FOC0_MASK 1U +#define TIM1CFORC_FOC1_MASK 2U +#define TIM1CFORC_FOC_MASK 3U +#define TIM1CFORC_FOC_BITNUM 0U + + +/*** TIM1TCNT - Timer Count Register; 0x00000404 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM1TCNTHi - Timer Count Register High (OBSOLETE - defined for backward compatibility); 0x00000404 ***/ + union { + byte Byte; + /*** TIM1TCNTHi - Timer Count Register High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TCNTHi _TIM1TCNT.Overlap_STR.TIM1TCNTHiSTR.Byte + + /*** TIM1TCNTH - Timer Count Register High; Several registers at the same address ***/ + #define TIM1TCNTH _TIM1TCNT.Overlap_STR.TIM1TCNTHiSTR.Byte + + } TIM1TCNTHiSTR; + + + /*** TIM1TCNTLo - Timer Count Register Low (OBSOLETE - defined for backward compatibility); 0x00000405 ***/ + union { + byte Byte; + /*** TIM1TCNTLo - Timer Count Register Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TCNTLo _TIM1TCNT.Overlap_STR.TIM1TCNTLoSTR.Byte + + /*** TIM1TCNTL - Timer Count Register Low; Several registers at the same address ***/ + #define TIM1TCNTL _TIM1TCNT.Overlap_STR.TIM1TCNTLoSTR.Byte + + } TIM1TCNTLoSTR; + + } Overlap_STR; + +} TIM1TCNTSTR; +extern volatile TIM1TCNTSTR _TIM1TCNT @0x00000404; +#define TIM1TCNT _TIM1TCNT.Word + + +/*** TIM1TSCR1 - Timer System Control Register1; 0x00000406 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte PRNT :1; /* Precision Timer */ + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TIM1TSCR1STR; +extern volatile TIM1TSCR1STR _TIM1TSCR1 @0x00000406; +#define TIM1TSCR1 _TIM1TSCR1.Byte +#define TIM1TSCR1_PRNT _TIM1TSCR1.Bits.PRNT +#define TIM1TSCR1_TFFCA _TIM1TSCR1.Bits.TFFCA +#define TIM1TSCR1_TSFRZ _TIM1TSCR1.Bits.TSFRZ +#define TIM1TSCR1_TSWAI _TIM1TSCR1.Bits.TSWAI +#define TIM1TSCR1_TEN _TIM1TSCR1.Bits.TEN + +#define TIM1TSCR1_PRNT_MASK 8U +#define TIM1TSCR1_TFFCA_MASK 16U +#define TIM1TSCR1_TSFRZ_MASK 32U +#define TIM1TSCR1_TSWAI_MASK 64U +#define TIM1TSCR1_TEN_MASK 128U + + +/*** TIM1TTOV - Timer Toggle On Overflow Register; 0x00000407 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTOV :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1TTOVSTR; +extern volatile TIM1TTOVSTR _TIM1TTOV @0x00000407; +#define TIM1TTOV _TIM1TTOV.Byte +#define TIM1TTOV_TOV0 _TIM1TTOV.Bits.TOV0 +#define TIM1TTOV_TOV1 _TIM1TTOV.Bits.TOV1 +#define TIM1TTOV_TOV _TIM1TTOV.MergedBits.grpTOV + +#define TIM1TTOV_TOV0_MASK 1U +#define TIM1TTOV_TOV1_MASK 2U +#define TIM1TTOV_TOV_MASK 3U +#define TIM1TTOV_TOV_BITNUM 0U + + +/*** TIM1TCTL2 - Timer Control Register 2; 0x00000409 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIM1TCTL2STR; +extern volatile TIM1TCTL2STR _TIM1TCTL2 @0x00000409; +#define TIM1TCTL2 _TIM1TCTL2.Byte +#define TIM1TCTL2_OL0 _TIM1TCTL2.Bits.OL0 +#define TIM1TCTL2_OM0 _TIM1TCTL2.Bits.OM0 +#define TIM1TCTL2_OL1 _TIM1TCTL2.Bits.OL1 +#define TIM1TCTL2_OM1 _TIM1TCTL2.Bits.OM1 + +#define TIM1TCTL2_OL0_MASK 1U +#define TIM1TCTL2_OM0_MASK 2U +#define TIM1TCTL2_OL1_MASK 4U +#define TIM1TCTL2_OM1_MASK 8U + + +/*** TIM1TCTL4 - Timer Control Register 4; 0x0000040B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpEDG0x :2; + byte grpEDG1x :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1TCTL4STR; +extern volatile TIM1TCTL4STR _TIM1TCTL4 @0x0000040B; +#define TIM1TCTL4 _TIM1TCTL4.Byte +#define TIM1TCTL4_EDG0A _TIM1TCTL4.Bits.EDG0A +#define TIM1TCTL4_EDG0B _TIM1TCTL4.Bits.EDG0B +#define TIM1TCTL4_EDG1A _TIM1TCTL4.Bits.EDG1A +#define TIM1TCTL4_EDG1B _TIM1TCTL4.Bits.EDG1B +#define TIM1TCTL4_EDG0x _TIM1TCTL4.MergedBits.grpEDG0x +#define TIM1TCTL4_EDG1x _TIM1TCTL4.MergedBits.grpEDG1x + +#define TIM1TCTL4_EDG0A_MASK 1U +#define TIM1TCTL4_EDG0B_MASK 2U +#define TIM1TCTL4_EDG1A_MASK 4U +#define TIM1TCTL4_EDG1B_MASK 8U +#define TIM1TCTL4_EDG0x_MASK 3U +#define TIM1TCTL4_EDG0x_BITNUM 0U +#define TIM1TCTL4_EDG1x_MASK 12U +#define TIM1TCTL4_EDG1x_BITNUM 2U + + +/*** TIM1TIE - Timer Interrupt Enable Register; 0x0000040C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIM1TIESTR; +extern volatile TIM1TIESTR _TIM1TIE @0x0000040C; +#define TIM1TIE _TIM1TIE.Byte +#define TIM1TIE_C0I _TIM1TIE.Bits.C0I +#define TIM1TIE_C1I _TIM1TIE.Bits.C1I + +#define TIM1TIE_C0I_MASK 1U +#define TIM1TIE_C1I_MASK 2U + + +/*** TIM1TSCR2 - Timer System Control Register 2; 0x0000040D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1TSCR2STR; +extern volatile TIM1TSCR2STR _TIM1TSCR2 @0x0000040D; +#define TIM1TSCR2 _TIM1TSCR2.Byte +#define TIM1TSCR2_PR0 _TIM1TSCR2.Bits.PR0 +#define TIM1TSCR2_PR1 _TIM1TSCR2.Bits.PR1 +#define TIM1TSCR2_PR2 _TIM1TSCR2.Bits.PR2 +#define TIM1TSCR2_TOI _TIM1TSCR2.Bits.TOI +#define TIM1TSCR2_PR _TIM1TSCR2.MergedBits.grpPR + +#define TIM1TSCR2_PR0_MASK 1U +#define TIM1TSCR2_PR1_MASK 2U +#define TIM1TSCR2_PR2_MASK 4U +#define TIM1TSCR2_TOI_MASK 128U +#define TIM1TSCR2_PR_MASK 7U +#define TIM1TSCR2_PR_BITNUM 0U + + +/*** TIM1TFLG1 - Main Timer Interrupt Flag 1; 0x0000040E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel interrupt flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel interrupt flag 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIM1TFLG1STR; +extern volatile TIM1TFLG1STR _TIM1TFLG1 @0x0000040E; +#define TIM1TFLG1 _TIM1TFLG1.Byte +#define TIM1TFLG1_C0F _TIM1TFLG1.Bits.C0F +#define TIM1TFLG1_C1F _TIM1TFLG1.Bits.C1F + +#define TIM1TFLG1_C0F_MASK 1U +#define TIM1TFLG1_C1F_MASK 2U + + +/*** TIM1TFLG2 - Main Timer Interrupt Flag 2; 0x0000040F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow interrupt flag */ + } Bits; +} TIM1TFLG2STR; +extern volatile TIM1TFLG2STR _TIM1TFLG2 @0x0000040F; +#define TIM1TFLG2 _TIM1TFLG2.Byte +#define TIM1TFLG2_TOF _TIM1TFLG2.Bits.TOF + +#define TIM1TFLG2_TOF_MASK 128U + + +/*** TIM1TC0 - Timer Input Capture/Output Compare Register 0; 0x00000410 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM1TC0Hi - Timer Input Capture/Output Compare Register 0 High (OBSOLETE - defined for backward compatibility); 0x00000410 ***/ + union { + byte Byte; + /*** TIM1TC0Hi - Timer Input Capture/Output Compare Register 0 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TC0Hi _TIM1TC0.Overlap_STR.TIM1TC0HiSTR.Byte + + /*** TIM1TC0H - Timer Input Capture/Output Compare Register 0 High; Several registers at the same address ***/ + #define TIM1TC0H _TIM1TC0.Overlap_STR.TIM1TC0HiSTR.Byte + + } TIM1TC0HiSTR; + + + /*** TIM1TC0Lo - Timer Input Capture/Output Compare Register 0 Low (OBSOLETE - defined for backward compatibility); 0x00000411 ***/ + union { + byte Byte; + /*** TIM1TC0Lo - Timer Input Capture/Output Compare Register 0 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TC0Lo _TIM1TC0.Overlap_STR.TIM1TC0LoSTR.Byte + + /*** TIM1TC0L - Timer Input Capture/Output Compare Register 0 Low; Several registers at the same address ***/ + #define TIM1TC0L _TIM1TC0.Overlap_STR.TIM1TC0LoSTR.Byte + + } TIM1TC0LoSTR; + + } Overlap_STR; + +} TIM1TC0STR; +extern volatile TIM1TC0STR _TIM1TC0 @0x00000410; +#define TIM1TC0 _TIM1TC0.Word +/* TIM1TC_ARR: Access 2 TIM1TCx registers in an array */ +#define TIM1TC_ARR ((volatile word *) &TIM1TC0) + + +/*** TIM1TC1 - Timer Input Capture/Output Compare Register 1; 0x00000412 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM1TC1Hi - Timer Input Capture/Output Compare Register 1 High (OBSOLETE - defined for backward compatibility); 0x00000412 ***/ + union { + byte Byte; + /*** TIM1TC1Hi - Timer Input Capture/Output Compare Register 1 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TC1Hi _TIM1TC1.Overlap_STR.TIM1TC1HiSTR.Byte + + /*** TIM1TC1H - Timer Input Capture/Output Compare Register 1 High; Several registers at the same address ***/ + #define TIM1TC1H _TIM1TC1.Overlap_STR.TIM1TC1HiSTR.Byte + + } TIM1TC1HiSTR; + + + /*** TIM1TC1Lo - Timer Input Capture/Output Compare Register 1 Low (OBSOLETE - defined for backward compatibility); 0x00000413 ***/ + union { + byte Byte; + /*** TIM1TC1Lo - Timer Input Capture/Output Compare Register 1 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM1TC1Lo _TIM1TC1.Overlap_STR.TIM1TC1LoSTR.Byte + + /*** TIM1TC1L - Timer Input Capture/Output Compare Register 1 Low; Several registers at the same address ***/ + #define TIM1TC1L _TIM1TC1.Overlap_STR.TIM1TC1LoSTR.Byte + + } TIM1TC1LoSTR; + + } Overlap_STR; + +} TIM1TC1STR; +extern volatile TIM1TC1STR _TIM1TC1 @0x00000412; +#define TIM1TC1 _TIM1TC1.Word + + +/*** TIM1OCPD - Output Compare Pin Disconnect Register; 0x0000042C ***/ +typedef union { + byte Byte; + struct { + byte OCPD0 :1; /* Output Compare Pin Disconnect Bit 0 */ + byte OCPD1 :1; /* Output Compare Pin Disconnect Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpOCPD :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM1OCPDSTR; +extern volatile TIM1OCPDSTR _TIM1OCPD @0x0000042C; +#define TIM1OCPD _TIM1OCPD.Byte +#define TIM1OCPD_OCPD0 _TIM1OCPD.Bits.OCPD0 +#define TIM1OCPD_OCPD1 _TIM1OCPD.Bits.OCPD1 +#define TIM1OCPD_OCPD _TIM1OCPD.MergedBits.grpOCPD + +#define TIM1OCPD_OCPD0_MASK 1U +#define TIM1OCPD_OCPD1_MASK 2U +#define TIM1OCPD_OCPD_MASK 3U +#define TIM1OCPD_OCPD_BITNUM 0U + + +/*** TIM1PTPSR - Precision Timer Prescaler Select Register; 0x0000042E ***/ +typedef union { + byte Byte; + struct { + byte PTPS0 :1; /* Precision Timer Prescaler Select Bit 0 */ + byte PTPS1 :1; /* Precision Timer Prescaler Select Bit 1 */ + byte PTPS2 :1; /* Precision Timer Prescaler Select Bit 2 */ + byte PTPS3 :1; /* Precision Timer Prescaler Select Bit 3 */ + byte PTPS4 :1; /* Precision Timer Prescaler Select Bit 4 */ + byte PTPS5 :1; /* Precision Timer Prescaler Select Bit 5 */ + byte PTPS6 :1; /* Precision Timer Prescaler Select Bit 6 */ + byte PTPS7 :1; /* Precision Timer Prescaler Select Bit 7 */ + } Bits; +} TIM1PTPSRSTR; +extern volatile TIM1PTPSRSTR _TIM1PTPSR @0x0000042E; +#define TIM1PTPSR _TIM1PTPSR.Byte +#define TIM1PTPSR_PTPS0 _TIM1PTPSR.Bits.PTPS0 +#define TIM1PTPSR_PTPS1 _TIM1PTPSR.Bits.PTPS1 +#define TIM1PTPSR_PTPS2 _TIM1PTPSR.Bits.PTPS2 +#define TIM1PTPSR_PTPS3 _TIM1PTPSR.Bits.PTPS3 +#define TIM1PTPSR_PTPS4 _TIM1PTPSR.Bits.PTPS4 +#define TIM1PTPSR_PTPS5 _TIM1PTPSR.Bits.PTPS5 +#define TIM1PTPSR_PTPS6 _TIM1PTPSR.Bits.PTPS6 +#define TIM1PTPSR_PTPS7 _TIM1PTPSR.Bits.PTPS7 + +#define TIM1PTPSR_PTPS0_MASK 1U +#define TIM1PTPSR_PTPS1_MASK 2U +#define TIM1PTPSR_PTPS2_MASK 4U +#define TIM1PTPSR_PTPS3_MASK 8U +#define TIM1PTPSR_PTPS4_MASK 16U +#define TIM1PTPSR_PTPS5_MASK 32U +#define TIM1PTPSR_PTPS6_MASK 64U +#define TIM1PTPSR_PTPS7_MASK 128U + + +/*** PWME - PWM Enable Register; 0x00000480 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; +} PWMESTR; +extern volatile PWMESTR _PWME @0x00000480; +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 + +#define PWME_PWME0_MASK 1U +#define PWME_PWME1_MASK 2U +#define PWME_PWME2_MASK 4U +#define PWME_PWME3_MASK 8U +#define PWME_PWME4_MASK 16U +#define PWME_PWME5_MASK 32U +#define PWME_PWME6_MASK 64U +#define PWME_PWME7_MASK 128U + + +/*** PWMPOL - PWM Polarity Register; 0x00000481 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @0x00000481; +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 + +#define PWMPOL_PPOL0_MASK 1U +#define PWMPOL_PPOL1_MASK 2U +#define PWMPOL_PPOL2_MASK 4U +#define PWMPOL_PPOL3_MASK 8U +#define PWMPOL_PPOL4_MASK 16U +#define PWMPOL_PPOL5_MASK 32U +#define PWMPOL_PPOL6_MASK 64U +#define PWMPOL_PPOL7_MASK 128U + + +/*** PWMCLK - PWM Clock Select Register; 0x00000482 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @0x00000482; +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 + +#define PWMCLK_PCLK0_MASK 1U +#define PWMCLK_PCLK1_MASK 2U +#define PWMCLK_PCLK2_MASK 4U +#define PWMCLK_PCLK3_MASK 8U +#define PWMCLK_PCLK4_MASK 16U +#define PWMCLK_PCLK5_MASK 32U +#define PWMCLK_PCLK6_MASK 64U +#define PWMCLK_PCLK7_MASK 128U + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x00000483 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @0x00000483; +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + +#define PWMPRCLK_PCKA0_MASK 1U +#define PWMPRCLK_PCKA1_MASK 2U +#define PWMPRCLK_PCKA2_MASK 4U +#define PWMPRCLK_PCKB0_MASK 16U +#define PWMPRCLK_PCKB1_MASK 32U +#define PWMPRCLK_PCKB2_MASK 64U +#define PWMPRCLK_PCKA_MASK 7U +#define PWMPRCLK_PCKA_BITNUM 0U +#define PWMPRCLK_PCKB_MASK 112U +#define PWMPRCLK_PCKB_BITNUM 4U + + +/*** PWMCAE - PWM Center Align Enable Register; 0x00000484 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @0x00000484; +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 + +#define PWMCAE_CAE0_MASK 1U +#define PWMCAE_CAE1_MASK 2U +#define PWMCAE_CAE2_MASK 4U +#define PWMCAE_CAE3_MASK 8U +#define PWMCAE_CAE4_MASK 16U +#define PWMCAE_CAE5_MASK 32U +#define PWMCAE_CAE6_MASK 64U +#define PWMCAE_CAE7_MASK 128U + + +/*** PWMCTL - PWM Control Register; 0x00000485 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @0x00000485; +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + +#define PWMCTL_PFRZ_MASK 4U +#define PWMCTL_PSWAI_MASK 8U +#define PWMCTL_CON01_MASK 16U +#define PWMCTL_CON23_MASK 32U +#define PWMCTL_CON45_MASK 64U +#define PWMCTL_CON67_MASK 128U + + +/*** PWMCLKAB - PWM Clock Select Register; 0x00000486 ***/ +typedef union { + byte Byte; + struct { + byte PCLKAB0 :1; /* Pulse Width Channel 0 Clock A/B Select */ + byte PCLKAB1 :1; /* Pulse Width Channel 1 Clock A/B Select */ + byte PCLKAB2 :1; /* Pulse Width Channel 2 Clock A/B Select */ + byte PCLKAB3 :1; /* Pulse Width Channel 3 Clock A/B Select */ + byte PCLKAB4 :1; /* Pulse Width Channel 4 Clock A/B Select */ + byte PCLKAB5 :1; /* Pulse Width Channel 5 Clock A/B Select */ + byte PCLKAB6 :1; /* Pulse Width Channel 6 Clock A/B Select */ + byte PCLKAB7 :1; /* Pulse Width Channel 7 Clock A/B Select */ + } Bits; +} PWMCLKABSTR; +extern volatile PWMCLKABSTR _PWMCLKAB @0x00000486; +#define PWMCLKAB _PWMCLKAB.Byte +#define PWMCLKAB_PCLKAB0 _PWMCLKAB.Bits.PCLKAB0 +#define PWMCLKAB_PCLKAB1 _PWMCLKAB.Bits.PCLKAB1 +#define PWMCLKAB_PCLKAB2 _PWMCLKAB.Bits.PCLKAB2 +#define PWMCLKAB_PCLKAB3 _PWMCLKAB.Bits.PCLKAB3 +#define PWMCLKAB_PCLKAB4 _PWMCLKAB.Bits.PCLKAB4 +#define PWMCLKAB_PCLKAB5 _PWMCLKAB.Bits.PCLKAB5 +#define PWMCLKAB_PCLKAB6 _PWMCLKAB.Bits.PCLKAB6 +#define PWMCLKAB_PCLKAB7 _PWMCLKAB.Bits.PCLKAB7 + +#define PWMCLKAB_PCLKAB0_MASK 1U +#define PWMCLKAB_PCLKAB1_MASK 2U +#define PWMCLKAB_PCLKAB2_MASK 4U +#define PWMCLKAB_PCLKAB3_MASK 8U +#define PWMCLKAB_PCLKAB4_MASK 16U +#define PWMCLKAB_PCLKAB5_MASK 32U +#define PWMCLKAB_PCLKAB6_MASK 64U +#define PWMCLKAB_PCLKAB7_MASK 128U + + +/*** PWMSCLA - PWM Scale A Register; 0x00000488 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @0x00000488; +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 + +#define PWMSCLA_BIT0_MASK 1U +#define PWMSCLA_BIT1_MASK 2U +#define PWMSCLA_BIT2_MASK 4U +#define PWMSCLA_BIT3_MASK 8U +#define PWMSCLA_BIT4_MASK 16U +#define PWMSCLA_BIT5_MASK 32U +#define PWMSCLA_BIT6_MASK 64U +#define PWMSCLA_BIT7_MASK 128U + + +/*** PWMSCLB - PWM Scale B Register; 0x00000489 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @0x00000489; +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 + +#define PWMSCLB_BIT0_MASK 1U +#define PWMSCLB_BIT1_MASK 2U +#define PWMSCLB_BIT2_MASK 4U +#define PWMSCLB_BIT3_MASK 8U +#define PWMSCLB_BIT4_MASK 16U +#define PWMSCLB_BIT5_MASK 32U +#define PWMSCLB_BIT6_MASK 64U +#define PWMSCLB_BIT7_MASK 128U + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x0000048C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x0000048C ***/ + union { + byte Byte; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + /* PWMCNT_ARR: Access 8 PWMCNTx registers in an array */ + #define PWMCNT_ARR ((volatile byte *) &PWMCNT0) + + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x0000048D ***/ + union { + byte Byte; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + + } Overlap_STR; + +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @0x0000048C; +#define PWMCNT01 _PWMCNT01.Word + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x0000048E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x0000048E ***/ + union { + byte Byte; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x0000048F ***/ + union { + byte Byte; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + + } Overlap_STR; + +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @0x0000048E; +#define PWMCNT23 _PWMCNT23.Word + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x00000490 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x00000490 ***/ + union { + byte Byte; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x00000491 ***/ + union { + byte Byte; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + + } Overlap_STR; + +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @0x00000490; +#define PWMCNT45 _PWMCNT45.Word + + +/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x00000492 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x00000492 ***/ + union { + byte Byte; + } PWMCNT6STR; + #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte + + + /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x00000493 ***/ + union { + byte Byte; + } PWMCNT7STR; + #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte + + } Overlap_STR; + +} PWMCNT67STR; +extern volatile PWMCNT67STR _PWMCNT67 @0x00000492; +#define PWMCNT67 _PWMCNT67.Word + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x00000494 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x00000494 ***/ + union { + byte Byte; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + /* PWMPER_ARR: Access 8 PWMPERx registers in an array */ + #define PWMPER_ARR ((volatile byte *) &PWMPER0) + + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x00000495 ***/ + union { + byte Byte; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + + } Overlap_STR; + +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @0x00000494; +#define PWMPER01 _PWMPER01.Word + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x00000496 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x00000496 ***/ + union { + byte Byte; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x00000497 ***/ + union { + byte Byte; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + + } Overlap_STR; + +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @0x00000496; +#define PWMPER23 _PWMPER23.Word + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x00000498 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x00000498 ***/ + union { + byte Byte; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x00000499 ***/ + union { + byte Byte; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + + } Overlap_STR; + +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @0x00000498; +#define PWMPER45 _PWMPER45.Word + + +/*** PWMPER67 - PWM Channel Period 67 Register; 0x0000049A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER6 - PWM Channel Period 6 Register; 0x0000049A ***/ + union { + byte Byte; + } PWMPER6STR; + #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte + + + /*** PWMPER7 - PWM Channel Period 7 Register; 0x0000049B ***/ + union { + byte Byte; + } PWMPER7STR; + #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte + + } Overlap_STR; + +} PWMPER67STR; +extern volatile PWMPER67STR _PWMPER67 @0x0000049A; +#define PWMPER67 _PWMPER67.Word + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x0000049C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x0000049C ***/ + union { + byte Byte; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + /* PWMDTY_ARR: Access 8 PWMDTYx registers in an array */ + #define PWMDTY_ARR ((volatile byte *) &PWMDTY0) + + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x0000049D ***/ + union { + byte Byte; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + + } Overlap_STR; + +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @0x0000049C; +#define PWMDTY01 _PWMDTY01.Word + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x0000049E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x0000049E ***/ + union { + byte Byte; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x0000049F ***/ + union { + byte Byte; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + + } Overlap_STR; + +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @0x0000049E; +#define PWMDTY23 _PWMDTY23.Word + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000004A0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000004A0 ***/ + union { + byte Byte; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000004A1 ***/ + union { + byte Byte; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + + } Overlap_STR; + +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @0x000004A0; +#define PWMDTY45 _PWMDTY45.Word + + +/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000004A2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000004A2 ***/ + union { + byte Byte; + } PWMDTY6STR; + #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte + + + /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000004A3 ***/ + union { + byte Byte; + } PWMDTY7STR; + #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte + + } Overlap_STR; + +} PWMDTY67STR; +extern volatile PWMDTY67STR _PWMDTY67 @0x000004A2; +#define PWMDTY67 _PWMDTY67.Word + + +/*** TIM0TIOS - Timer Input Capture/Output Compare Select; 0x000005C0 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIOS :6; + byte :1; + byte :1; + } MergedBits; +} TIM0TIOSSTR; +extern volatile TIM0TIOSSTR _TIM0TIOS @0x000005C0; +#define TIM0TIOS _TIM0TIOS.Byte +#define TIM0TIOS_IOS0 _TIM0TIOS.Bits.IOS0 +#define TIM0TIOS_IOS1 _TIM0TIOS.Bits.IOS1 +#define TIM0TIOS_IOS2 _TIM0TIOS.Bits.IOS2 +#define TIM0TIOS_IOS3 _TIM0TIOS.Bits.IOS3 +#define TIM0TIOS_IOS4 _TIM0TIOS.Bits.IOS4 +#define TIM0TIOS_IOS5 _TIM0TIOS.Bits.IOS5 +#define TIM0TIOS_IOS _TIM0TIOS.MergedBits.grpIOS + +#define TIM0TIOS_IOS0_MASK 1U +#define TIM0TIOS_IOS1_MASK 2U +#define TIM0TIOS_IOS2_MASK 4U +#define TIM0TIOS_IOS3_MASK 8U +#define TIM0TIOS_IOS4_MASK 16U +#define TIM0TIOS_IOS5_MASK 32U +#define TIM0TIOS_IOS_MASK 63U +#define TIM0TIOS_IOS_BITNUM 0U + + +/*** TIM0CFORC - Timer Compare Force Register; 0x000005C1 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpFOC :6; + byte :1; + byte :1; + } MergedBits; +} TIM0CFORCSTR; +extern volatile TIM0CFORCSTR _TIM0CFORC @0x000005C1; +#define TIM0CFORC _TIM0CFORC.Byte +#define TIM0CFORC_FOC0 _TIM0CFORC.Bits.FOC0 +#define TIM0CFORC_FOC1 _TIM0CFORC.Bits.FOC1 +#define TIM0CFORC_FOC2 _TIM0CFORC.Bits.FOC2 +#define TIM0CFORC_FOC3 _TIM0CFORC.Bits.FOC3 +#define TIM0CFORC_FOC4 _TIM0CFORC.Bits.FOC4 +#define TIM0CFORC_FOC5 _TIM0CFORC.Bits.FOC5 +#define TIM0CFORC_FOC _TIM0CFORC.MergedBits.grpFOC + +#define TIM0CFORC_FOC0_MASK 1U +#define TIM0CFORC_FOC1_MASK 2U +#define TIM0CFORC_FOC2_MASK 4U +#define TIM0CFORC_FOC3_MASK 8U +#define TIM0CFORC_FOC4_MASK 16U +#define TIM0CFORC_FOC5_MASK 32U +#define TIM0CFORC_FOC_MASK 63U +#define TIM0CFORC_FOC_BITNUM 0U + + +/*** TIM0TCNT - Timer Count Register; 0x000005C4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TCNTHi - Timer Count Register High (OBSOLETE - defined for backward compatibility); 0x000005C4 ***/ + union { + byte Byte; + /*** TIM0TCNTHi - Timer Count Register High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TCNTHi _TIM0TCNT.Overlap_STR.TIM0TCNTHiSTR.Byte + + /*** TIM0TCNTH - Timer Count Register High; Several registers at the same address ***/ + #define TIM0TCNTH _TIM0TCNT.Overlap_STR.TIM0TCNTHiSTR.Byte + + } TIM0TCNTHiSTR; + + + /*** TIM0TCNTLo - Timer Count Register Low (OBSOLETE - defined for backward compatibility); 0x000005C5 ***/ + union { + byte Byte; + /*** TIM0TCNTLo - Timer Count Register Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TCNTLo _TIM0TCNT.Overlap_STR.TIM0TCNTLoSTR.Byte + + /*** TIM0TCNTL - Timer Count Register Low; Several registers at the same address ***/ + #define TIM0TCNTL _TIM0TCNT.Overlap_STR.TIM0TCNTLoSTR.Byte + + } TIM0TCNTLoSTR; + + } Overlap_STR; + +} TIM0TCNTSTR; +extern volatile TIM0TCNTSTR _TIM0TCNT @0x000005C4; +#define TIM0TCNT _TIM0TCNT.Word + + +/*** TIM0TSCR1 - Timer System Control Register1; 0x000005C6 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte PRNT :1; /* Precision Timer */ + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TIM0TSCR1STR; +extern volatile TIM0TSCR1STR _TIM0TSCR1 @0x000005C6; +#define TIM0TSCR1 _TIM0TSCR1.Byte +#define TIM0TSCR1_PRNT _TIM0TSCR1.Bits.PRNT +#define TIM0TSCR1_TFFCA _TIM0TSCR1.Bits.TFFCA +#define TIM0TSCR1_TSFRZ _TIM0TSCR1.Bits.TSFRZ +#define TIM0TSCR1_TSWAI _TIM0TSCR1.Bits.TSWAI +#define TIM0TSCR1_TEN _TIM0TSCR1.Bits.TEN + +#define TIM0TSCR1_PRNT_MASK 8U +#define TIM0TSCR1_TFFCA_MASK 16U +#define TIM0TSCR1_TSFRZ_MASK 32U +#define TIM0TSCR1_TSWAI_MASK 64U +#define TIM0TSCR1_TEN_MASK 128U + + +/*** TIM0TTOV - Timer Toggle On Overflow Register; 0x000005C7 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpTOV :6; + byte :1; + byte :1; + } MergedBits; +} TIM0TTOVSTR; +extern volatile TIM0TTOVSTR _TIM0TTOV @0x000005C7; +#define TIM0TTOV _TIM0TTOV.Byte +#define TIM0TTOV_TOV0 _TIM0TTOV.Bits.TOV0 +#define TIM0TTOV_TOV1 _TIM0TTOV.Bits.TOV1 +#define TIM0TTOV_TOV2 _TIM0TTOV.Bits.TOV2 +#define TIM0TTOV_TOV3 _TIM0TTOV.Bits.TOV3 +#define TIM0TTOV_TOV4 _TIM0TTOV.Bits.TOV4 +#define TIM0TTOV_TOV5 _TIM0TTOV.Bits.TOV5 +#define TIM0TTOV_TOV _TIM0TTOV.MergedBits.grpTOV + +#define TIM0TTOV_TOV0_MASK 1U +#define TIM0TTOV_TOV1_MASK 2U +#define TIM0TTOV_TOV2_MASK 4U +#define TIM0TTOV_TOV3_MASK 8U +#define TIM0TTOV_TOV4_MASK 16U +#define TIM0TTOV_TOV5_MASK 32U +#define TIM0TTOV_TOV_MASK 63U +#define TIM0TTOV_TOV_BITNUM 0U + + +/*** TIM0TCTL1 - Timer Control Register 1; 0x000005C8 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIM0TCTL1STR; +extern volatile TIM0TCTL1STR _TIM0TCTL1 @0x000005C8; +#define TIM0TCTL1 _TIM0TCTL1.Byte +#define TIM0TCTL1_OL4 _TIM0TCTL1.Bits.OL4 +#define TIM0TCTL1_OM4 _TIM0TCTL1.Bits.OM4 +#define TIM0TCTL1_OL5 _TIM0TCTL1.Bits.OL5 +#define TIM0TCTL1_OM5 _TIM0TCTL1.Bits.OM5 + +#define TIM0TCTL1_OL4_MASK 1U +#define TIM0TCTL1_OM4_MASK 2U +#define TIM0TCTL1_OL5_MASK 4U +#define TIM0TCTL1_OM5_MASK 8U + + +/*** TIM0TCTL2 - Timer Control Register 2; 0x000005C9 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TIM0TCTL2STR; +extern volatile TIM0TCTL2STR _TIM0TCTL2 @0x000005C9; +#define TIM0TCTL2 _TIM0TCTL2.Byte +#define TIM0TCTL2_OL0 _TIM0TCTL2.Bits.OL0 +#define TIM0TCTL2_OM0 _TIM0TCTL2.Bits.OM0 +#define TIM0TCTL2_OL1 _TIM0TCTL2.Bits.OL1 +#define TIM0TCTL2_OM1 _TIM0TCTL2.Bits.OM1 +#define TIM0TCTL2_OL2 _TIM0TCTL2.Bits.OL2 +#define TIM0TCTL2_OM2 _TIM0TCTL2.Bits.OM2 +#define TIM0TCTL2_OL3 _TIM0TCTL2.Bits.OL3 +#define TIM0TCTL2_OM3 _TIM0TCTL2.Bits.OM3 + +#define TIM0TCTL2_OL0_MASK 1U +#define TIM0TCTL2_OM0_MASK 2U +#define TIM0TCTL2_OL1_MASK 4U +#define TIM0TCTL2_OM1_MASK 8U +#define TIM0TCTL2_OL2_MASK 16U +#define TIM0TCTL2_OM2_MASK 32U +#define TIM0TCTL2_OL3_MASK 64U +#define TIM0TCTL2_OM3_MASK 128U + + +/*** TIM0TCTL3 - Timer Control Register 3; 0x000005CA ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpEDG4x :2; + byte grpEDG5x :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM0TCTL3STR; +extern volatile TIM0TCTL3STR _TIM0TCTL3 @0x000005CA; +#define TIM0TCTL3 _TIM0TCTL3.Byte +#define TIM0TCTL3_EDG4A _TIM0TCTL3.Bits.EDG4A +#define TIM0TCTL3_EDG4B _TIM0TCTL3.Bits.EDG4B +#define TIM0TCTL3_EDG5A _TIM0TCTL3.Bits.EDG5A +#define TIM0TCTL3_EDG5B _TIM0TCTL3.Bits.EDG5B +#define TIM0TCTL3_EDG4x _TIM0TCTL3.MergedBits.grpEDG4x +#define TIM0TCTL3_EDG5x _TIM0TCTL3.MergedBits.grpEDG5x + +#define TIM0TCTL3_EDG4A_MASK 1U +#define TIM0TCTL3_EDG4B_MASK 2U +#define TIM0TCTL3_EDG5A_MASK 4U +#define TIM0TCTL3_EDG5B_MASK 8U +#define TIM0TCTL3_EDG4x_MASK 3U +#define TIM0TCTL3_EDG4x_BITNUM 0U +#define TIM0TCTL3_EDG5x_MASK 12U +#define TIM0TCTL3_EDG5x_BITNUM 2U + + +/*** TIM0TCTL4 - Timer Control Register 4; 0x000005CB ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; + struct { + byte grpEDG0x :2; + byte grpEDG1x :2; + byte grpEDG2x :2; + byte grpEDG3x :2; + } MergedBits; +} TIM0TCTL4STR; +extern volatile TIM0TCTL4STR _TIM0TCTL4 @0x000005CB; +#define TIM0TCTL4 _TIM0TCTL4.Byte +#define TIM0TCTL4_EDG0A _TIM0TCTL4.Bits.EDG0A +#define TIM0TCTL4_EDG0B _TIM0TCTL4.Bits.EDG0B +#define TIM0TCTL4_EDG1A _TIM0TCTL4.Bits.EDG1A +#define TIM0TCTL4_EDG1B _TIM0TCTL4.Bits.EDG1B +#define TIM0TCTL4_EDG2A _TIM0TCTL4.Bits.EDG2A +#define TIM0TCTL4_EDG2B _TIM0TCTL4.Bits.EDG2B +#define TIM0TCTL4_EDG3A _TIM0TCTL4.Bits.EDG3A +#define TIM0TCTL4_EDG3B _TIM0TCTL4.Bits.EDG3B +#define TIM0TCTL4_EDG0x _TIM0TCTL4.MergedBits.grpEDG0x +#define TIM0TCTL4_EDG1x _TIM0TCTL4.MergedBits.grpEDG1x +#define TIM0TCTL4_EDG2x _TIM0TCTL4.MergedBits.grpEDG2x +#define TIM0TCTL4_EDG3x _TIM0TCTL4.MergedBits.grpEDG3x + +#define TIM0TCTL4_EDG0A_MASK 1U +#define TIM0TCTL4_EDG0B_MASK 2U +#define TIM0TCTL4_EDG1A_MASK 4U +#define TIM0TCTL4_EDG1B_MASK 8U +#define TIM0TCTL4_EDG2A_MASK 16U +#define TIM0TCTL4_EDG2B_MASK 32U +#define TIM0TCTL4_EDG3A_MASK 64U +#define TIM0TCTL4_EDG3B_MASK 128U +#define TIM0TCTL4_EDG0x_MASK 3U +#define TIM0TCTL4_EDG0x_BITNUM 0U +#define TIM0TCTL4_EDG1x_MASK 12U +#define TIM0TCTL4_EDG1x_BITNUM 2U +#define TIM0TCTL4_EDG2x_MASK 48U +#define TIM0TCTL4_EDG2x_BITNUM 4U +#define TIM0TCTL4_EDG3x_MASK 192U +#define TIM0TCTL4_EDG3x_BITNUM 6U + + +/*** TIM0TIE - Timer Interrupt Enable Register; 0x000005CC ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte :1; + byte :1; + } Bits; +} TIM0TIESTR; +extern volatile TIM0TIESTR _TIM0TIE @0x000005CC; +#define TIM0TIE _TIM0TIE.Byte +#define TIM0TIE_C0I _TIM0TIE.Bits.C0I +#define TIM0TIE_C1I _TIM0TIE.Bits.C1I +#define TIM0TIE_C2I _TIM0TIE.Bits.C2I +#define TIM0TIE_C3I _TIM0TIE.Bits.C3I +#define TIM0TIE_C4I _TIM0TIE.Bits.C4I +#define TIM0TIE_C5I _TIM0TIE.Bits.C5I + +#define TIM0TIE_C0I_MASK 1U +#define TIM0TIE_C1I_MASK 2U +#define TIM0TIE_C2I_MASK 4U +#define TIM0TIE_C3I_MASK 8U +#define TIM0TIE_C4I_MASK 16U +#define TIM0TIE_C5I_MASK 32U + + +/*** TIM0TSCR2 - Timer System Control Register 2; 0x000005CD ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TIM0TSCR2STR; +extern volatile TIM0TSCR2STR _TIM0TSCR2 @0x000005CD; +#define TIM0TSCR2 _TIM0TSCR2.Byte +#define TIM0TSCR2_PR0 _TIM0TSCR2.Bits.PR0 +#define TIM0TSCR2_PR1 _TIM0TSCR2.Bits.PR1 +#define TIM0TSCR2_PR2 _TIM0TSCR2.Bits.PR2 +#define TIM0TSCR2_TOI _TIM0TSCR2.Bits.TOI +#define TIM0TSCR2_PR _TIM0TSCR2.MergedBits.grpPR + +#define TIM0TSCR2_PR0_MASK 1U +#define TIM0TSCR2_PR1_MASK 2U +#define TIM0TSCR2_PR2_MASK 4U +#define TIM0TSCR2_TOI_MASK 128U +#define TIM0TSCR2_PR_MASK 7U +#define TIM0TSCR2_PR_BITNUM 0U + + +/*** TIM0TFLG1 - Main Timer Interrupt Flag 1; 0x000005CE ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel interrupt flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel interrupt flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel interrupt flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel interrupt flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel interrupt flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel interrupt flag 5 */ + byte :1; + byte :1; + } Bits; +} TIM0TFLG1STR; +extern volatile TIM0TFLG1STR _TIM0TFLG1 @0x000005CE; +#define TIM0TFLG1 _TIM0TFLG1.Byte +#define TIM0TFLG1_C0F _TIM0TFLG1.Bits.C0F +#define TIM0TFLG1_C1F _TIM0TFLG1.Bits.C1F +#define TIM0TFLG1_C2F _TIM0TFLG1.Bits.C2F +#define TIM0TFLG1_C3F _TIM0TFLG1.Bits.C3F +#define TIM0TFLG1_C4F _TIM0TFLG1.Bits.C4F +#define TIM0TFLG1_C5F _TIM0TFLG1.Bits.C5F + +#define TIM0TFLG1_C0F_MASK 1U +#define TIM0TFLG1_C1F_MASK 2U +#define TIM0TFLG1_C2F_MASK 4U +#define TIM0TFLG1_C3F_MASK 8U +#define TIM0TFLG1_C4F_MASK 16U +#define TIM0TFLG1_C5F_MASK 32U + + +/*** TIM0TFLG2 - Main Timer Interrupt Flag 2; 0x000005CF ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow interrupt flag */ + } Bits; +} TIM0TFLG2STR; +extern volatile TIM0TFLG2STR _TIM0TFLG2 @0x000005CF; +#define TIM0TFLG2 _TIM0TFLG2.Byte +#define TIM0TFLG2_TOF _TIM0TFLG2.Bits.TOF + +#define TIM0TFLG2_TOF_MASK 128U + + +/*** TIM0TC0 - Timer Input Capture/Output Compare Register 0; 0x000005D0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC0Hi - Timer Input Capture/Output Compare Register 0 High (OBSOLETE - defined for backward compatibility); 0x000005D0 ***/ + union { + byte Byte; + /*** TIM0TC0Hi - Timer Input Capture/Output Compare Register 0 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC0Hi _TIM0TC0.Overlap_STR.TIM0TC0HiSTR.Byte + + /*** TIM0TC0H - Timer Input Capture/Output Compare Register 0 High; Several registers at the same address ***/ + #define TIM0TC0H _TIM0TC0.Overlap_STR.TIM0TC0HiSTR.Byte + + } TIM0TC0HiSTR; + + + /*** TIM0TC0Lo - Timer Input Capture/Output Compare Register 0 Low (OBSOLETE - defined for backward compatibility); 0x000005D1 ***/ + union { + byte Byte; + /*** TIM0TC0Lo - Timer Input Capture/Output Compare Register 0 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC0Lo _TIM0TC0.Overlap_STR.TIM0TC0LoSTR.Byte + + /*** TIM0TC0L - Timer Input Capture/Output Compare Register 0 Low; Several registers at the same address ***/ + #define TIM0TC0L _TIM0TC0.Overlap_STR.TIM0TC0LoSTR.Byte + + } TIM0TC0LoSTR; + + } Overlap_STR; + +} TIM0TC0STR; +extern volatile TIM0TC0STR _TIM0TC0 @0x000005D0; +#define TIM0TC0 _TIM0TC0.Word +/* TIM0TC_ARR: Access 6 TIM0TCx registers in an array */ +#define TIM0TC_ARR ((volatile word *) &TIM0TC0) + + +/*** TIM0TC1 - Timer Input Capture/Output Compare Register 1; 0x000005D2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC1Hi - Timer Input Capture/Output Compare Register 1 High (OBSOLETE - defined for backward compatibility); 0x000005D2 ***/ + union { + byte Byte; + /*** TIM0TC1Hi - Timer Input Capture/Output Compare Register 1 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC1Hi _TIM0TC1.Overlap_STR.TIM0TC1HiSTR.Byte + + /*** TIM0TC1H - Timer Input Capture/Output Compare Register 1 High; Several registers at the same address ***/ + #define TIM0TC1H _TIM0TC1.Overlap_STR.TIM0TC1HiSTR.Byte + + } TIM0TC1HiSTR; + + + /*** TIM0TC1Lo - Timer Input Capture/Output Compare Register 1 Low (OBSOLETE - defined for backward compatibility); 0x000005D3 ***/ + union { + byte Byte; + /*** TIM0TC1Lo - Timer Input Capture/Output Compare Register 1 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC1Lo _TIM0TC1.Overlap_STR.TIM0TC1LoSTR.Byte + + /*** TIM0TC1L - Timer Input Capture/Output Compare Register 1 Low; Several registers at the same address ***/ + #define TIM0TC1L _TIM0TC1.Overlap_STR.TIM0TC1LoSTR.Byte + + } TIM0TC1LoSTR; + + } Overlap_STR; + +} TIM0TC1STR; +extern volatile TIM0TC1STR _TIM0TC1 @0x000005D2; +#define TIM0TC1 _TIM0TC1.Word + + +/*** TIM0TC2 - Timer Input Capture/Output Compare Register 2; 0x000005D4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC2Hi - Timer Input Capture/Output Compare Register 2 High (OBSOLETE - defined for backward compatibility); 0x000005D4 ***/ + union { + byte Byte; + /*** TIM0TC2Hi - Timer Input Capture/Output Compare Register 2 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC2Hi _TIM0TC2.Overlap_STR.TIM0TC2HiSTR.Byte + + /*** TIM0TC2H - Timer Input Capture/Output Compare Register 2 High; Several registers at the same address ***/ + #define TIM0TC2H _TIM0TC2.Overlap_STR.TIM0TC2HiSTR.Byte + + } TIM0TC2HiSTR; + + + /*** TIM0TC2Lo - Timer Input Capture/Output Compare Register 2 Low (OBSOLETE - defined for backward compatibility); 0x000005D5 ***/ + union { + byte Byte; + /*** TIM0TC2Lo - Timer Input Capture/Output Compare Register 2 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC2Lo _TIM0TC2.Overlap_STR.TIM0TC2LoSTR.Byte + + /*** TIM0TC2L - Timer Input Capture/Output Compare Register 2 Low; Several registers at the same address ***/ + #define TIM0TC2L _TIM0TC2.Overlap_STR.TIM0TC2LoSTR.Byte + + } TIM0TC2LoSTR; + + } Overlap_STR; + +} TIM0TC2STR; +extern volatile TIM0TC2STR _TIM0TC2 @0x000005D4; +#define TIM0TC2 _TIM0TC2.Word + + +/*** TIM0TC3 - Timer Input Capture/Output Compare Register 3; 0x000005D6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC3Hi - Timer Input Capture/Output Compare Register 3 High (OBSOLETE - defined for backward compatibility); 0x000005D6 ***/ + union { + byte Byte; + /*** TIM0TC3Hi - Timer Input Capture/Output Compare Register 3 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC3Hi _TIM0TC3.Overlap_STR.TIM0TC3HiSTR.Byte + + /*** TIM0TC3H - Timer Input Capture/Output Compare Register 3 High; Several registers at the same address ***/ + #define TIM0TC3H _TIM0TC3.Overlap_STR.TIM0TC3HiSTR.Byte + + } TIM0TC3HiSTR; + + + /*** TIM0TC3Lo - Timer Input Capture/Output Compare Register 3 Low (OBSOLETE - defined for backward compatibility); 0x000005D7 ***/ + union { + byte Byte; + /*** TIM0TC3Lo - Timer Input Capture/Output Compare Register 3 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC3Lo _TIM0TC3.Overlap_STR.TIM0TC3LoSTR.Byte + + /*** TIM0TC3L - Timer Input Capture/Output Compare Register 3 Low; Several registers at the same address ***/ + #define TIM0TC3L _TIM0TC3.Overlap_STR.TIM0TC3LoSTR.Byte + + } TIM0TC3LoSTR; + + } Overlap_STR; + +} TIM0TC3STR; +extern volatile TIM0TC3STR _TIM0TC3 @0x000005D6; +#define TIM0TC3 _TIM0TC3.Word + + +/*** TIM0TC4 - Timer Input Capture/Output Compare Register 4; 0x000005D8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC4Hi - Timer Input Capture/Output Compare Register 4 High (OBSOLETE - defined for backward compatibility); 0x000005D8 ***/ + union { + byte Byte; + /*** TIM0TC4Hi - Timer Input Capture/Output Compare Register 4 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC4Hi _TIM0TC4.Overlap_STR.TIM0TC4HiSTR.Byte + + /*** TIM0TC4H - Timer Input Capture/Output Compare Register 4 High; Several registers at the same address ***/ + #define TIM0TC4H _TIM0TC4.Overlap_STR.TIM0TC4HiSTR.Byte + + } TIM0TC4HiSTR; + + + /*** TIM0TC4Lo - Timer Input Capture/Output Compare Register 4 Low (OBSOLETE - defined for backward compatibility); 0x000005D9 ***/ + union { + byte Byte; + /*** TIM0TC4Lo - Timer Input Capture/Output Compare Register 4 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC4Lo _TIM0TC4.Overlap_STR.TIM0TC4LoSTR.Byte + + /*** TIM0TC4L - Timer Input Capture/Output Compare Register 4 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC4L _TIM0TC4.Overlap_STR.TIM0TC4LoSTR.Byte + + } TIM0TC4LoSTR; + + } Overlap_STR; + +} TIM0TC4STR; +extern volatile TIM0TC4STR _TIM0TC4 @0x000005D8; +#define TIM0TC4 _TIM0TC4.Word + + +/*** TIM0TC5 - Timer Input Capture/Output Compare Register 5; 0x000005DA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TIM0TC5Hi - Timer Input Capture/Output Compare Register 5 High (OBSOLETE - defined for backward compatibility); 0x000005DA ***/ + union { + byte Byte; + /*** TIM0TC5Hi - Timer Input Capture/Output Compare Register 5 High (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC5Hi _TIM0TC5.Overlap_STR.TIM0TC5HiSTR.Byte + + /*** TIM0TC5H - Timer Input Capture/Output Compare Register 5 High; Several registers at the same address ***/ + #define TIM0TC5H _TIM0TC5.Overlap_STR.TIM0TC5HiSTR.Byte + + } TIM0TC5HiSTR; + + + /*** TIM0TC5Lo - Timer Input Capture/Output Compare Register 5 Low (OBSOLETE - defined for backward compatibility); 0x000005DB ***/ + union { + byte Byte; + /*** TIM0TC5Lo - Timer Input Capture/Output Compare Register 5 Low (OBSOLETE - defined for backward compatibility); Several registers at the same address ***/ + #define TIM0TC5Lo _TIM0TC5.Overlap_STR.TIM0TC5LoSTR.Byte + + /*** TIM0TC5L - Timer Input Capture/Output Compare Register 5 Low; Several registers at the same address ***/ + #define TIM0TC5L _TIM0TC5.Overlap_STR.TIM0TC5LoSTR.Byte + + } TIM0TC5LoSTR; + + } Overlap_STR; + +} TIM0TC5STR; +extern volatile TIM0TC5STR _TIM0TC5 @0x000005DA; +#define TIM0TC5 _TIM0TC5.Word + + +/*** TIM0OCPD - Output Compare Pin Disconnect Register; 0x000005EC ***/ +typedef union { + byte Byte; + struct { + byte OCPD0 :1; /* Output Compare Pin Disconnect Bit 0 */ + byte OCPD1 :1; /* Output Compare Pin Disconnect Bit 1 */ + byte OCPD2 :1; /* Output Compare Pin Disconnect Bit 2 */ + byte OCPD3 :1; /* Output Compare Pin Disconnect Bit 3 */ + byte OCPD4 :1; /* Output Compare Pin Disconnect Bit 4 */ + byte OCPD5 :1; /* Output Compare Pin Disconnect Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpOCPD :6; + byte :1; + byte :1; + } MergedBits; +} TIM0OCPDSTR; +extern volatile TIM0OCPDSTR _TIM0OCPD @0x000005EC; +#define TIM0OCPD _TIM0OCPD.Byte +#define TIM0OCPD_OCPD0 _TIM0OCPD.Bits.OCPD0 +#define TIM0OCPD_OCPD1 _TIM0OCPD.Bits.OCPD1 +#define TIM0OCPD_OCPD2 _TIM0OCPD.Bits.OCPD2 +#define TIM0OCPD_OCPD3 _TIM0OCPD.Bits.OCPD3 +#define TIM0OCPD_OCPD4 _TIM0OCPD.Bits.OCPD4 +#define TIM0OCPD_OCPD5 _TIM0OCPD.Bits.OCPD5 +#define TIM0OCPD_OCPD _TIM0OCPD.MergedBits.grpOCPD + +#define TIM0OCPD_OCPD0_MASK 1U +#define TIM0OCPD_OCPD1_MASK 2U +#define TIM0OCPD_OCPD2_MASK 4U +#define TIM0OCPD_OCPD3_MASK 8U +#define TIM0OCPD_OCPD4_MASK 16U +#define TIM0OCPD_OCPD5_MASK 32U +#define TIM0OCPD_OCPD_MASK 63U +#define TIM0OCPD_OCPD_BITNUM 0U + + +/*** TIM0PTPSR - Precision Timer Prescaler Select Register; 0x000005EE ***/ +typedef union { + byte Byte; + struct { + byte PTPS0 :1; /* Precision Timer Prescaler Select Bit 0 */ + byte PTPS1 :1; /* Precision Timer Prescaler Select Bit 1 */ + byte PTPS2 :1; /* Precision Timer Prescaler Select Bit 2 */ + byte PTPS3 :1; /* Precision Timer Prescaler Select Bit 3 */ + byte PTPS4 :1; /* Precision Timer Prescaler Select Bit 4 */ + byte PTPS5 :1; /* Precision Timer Prescaler Select Bit 5 */ + byte PTPS6 :1; /* Precision Timer Prescaler Select Bit 6 */ + byte PTPS7 :1; /* Precision Timer Prescaler Select Bit 7 */ + } Bits; +} TIM0PTPSRSTR; +extern volatile TIM0PTPSRSTR _TIM0PTPSR @0x000005EE; +#define TIM0PTPSR _TIM0PTPSR.Byte +#define TIM0PTPSR_PTPS0 _TIM0PTPSR.Bits.PTPS0 +#define TIM0PTPSR_PTPS1 _TIM0PTPSR.Bits.PTPS1 +#define TIM0PTPSR_PTPS2 _TIM0PTPSR.Bits.PTPS2 +#define TIM0PTPSR_PTPS3 _TIM0PTPSR.Bits.PTPS3 +#define TIM0PTPSR_PTPS4 _TIM0PTPSR.Bits.PTPS4 +#define TIM0PTPSR_PTPS5 _TIM0PTPSR.Bits.PTPS5 +#define TIM0PTPSR_PTPS6 _TIM0PTPSR.Bits.PTPS6 +#define TIM0PTPSR_PTPS7 _TIM0PTPSR.Bits.PTPS7 + +#define TIM0PTPSR_PTPS0_MASK 1U +#define TIM0PTPSR_PTPS1_MASK 2U +#define TIM0PTPSR_PTPS2_MASK 4U +#define TIM0PTPSR_PTPS3_MASK 8U +#define TIM0PTPSR_PTPS4_MASK 16U +#define TIM0PTPSR_PTPS5_MASK 32U +#define TIM0PTPSR_PTPS6_MASK 64U +#define TIM0PTPSR_PTPS7_MASK 128U + + +/*** ADC0CTL - ADC0 Control Register; 0x00000600 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0CTL_0 - ADC0 Control Register 0; 0x00000600 ***/ + union { + byte Byte; + struct { + byte MOD_CFG :1; /* Trigger Mode Configuration */ + byte STR_SEQA :1; /* Handling Restart Requests during End Of List Command Type Execution */ + byte ACC_CFG :2; /* ADCFLWCTL Register Access Configuration */ + byte SWAI :1; /* Wait Mode Configuration */ + byte FRZ_MOD :1; /* Freeze Mode Configuration */ + byte ADC_SR :1; /* ADC Soft Reset */ + byte ADC_EN :1; /* ADC Enable Bit */ + } Bits; + } ADC0CTL_0STR; + #define ADC0CTL_0 _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Byte + #define ADC0CTL_0_MOD_CFG _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.MOD_CFG + #define ADC0CTL_0_STR_SEQA _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.STR_SEQA + #define ADC0CTL_0_ACC_CFG _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.ACC_CFG + #define ADC0CTL_0_SWAI _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.SWAI + #define ADC0CTL_0_FRZ_MOD _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.FRZ_MOD + #define ADC0CTL_0_ADC_SR _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.ADC_SR + #define ADC0CTL_0_ADC_EN _ADC0CTL.Overlap_STR.ADC0CTL_0STR.Bits.ADC_EN + /* ADC0CTL__ARR: Access 2 ADC0CTL_x registers in an array */ + #define ADC0CTL__ARR ((volatile byte *) &ADC0CTL_0) + + #define ADC0CTL_0_MOD_CFG_MASK 1U + #define ADC0CTL_0_STR_SEQA_MASK 2U + #define ADC0CTL_0_ACC_CFG_MASK 12U + #define ADC0CTL_0_ACC_CFG_BITNUM 2U + #define ADC0CTL_0_SWAI_MASK 16U + #define ADC0CTL_0_FRZ_MOD_MASK 32U + #define ADC0CTL_0_ADC_SR_MASK 64U + #define ADC0CTL_0_ADC_EN_MASK 128U + + + /*** ADC0CTL_1 - ADC0 Control Register 1; 0x00000601 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte AUT_RSTA :1; /* Automatic Restart Event after exit from MCU Stop and Wait Mode */ + byte SMOD_ACC :1; /* Special Mode Access Control */ + byte RVL_BMOD :1; /* RVL Buffer Mode Select */ + byte CSL_BMOD :1; /* CSL Buffer Mode Select */ + } Bits; + } ADC0CTL_1STR; + #define ADC0CTL_1 _ADC0CTL.Overlap_STR.ADC0CTL_1STR.Byte + #define ADC0CTL_1_AUT_RSTA _ADC0CTL.Overlap_STR.ADC0CTL_1STR.Bits.AUT_RSTA + #define ADC0CTL_1_SMOD_ACC _ADC0CTL.Overlap_STR.ADC0CTL_1STR.Bits.SMOD_ACC + #define ADC0CTL_1_RVL_BMOD _ADC0CTL.Overlap_STR.ADC0CTL_1STR.Bits.RVL_BMOD + #define ADC0CTL_1_CSL_BMOD _ADC0CTL.Overlap_STR.ADC0CTL_1STR.Bits.CSL_BMOD + + #define ADC0CTL_1_AUT_RSTA_MASK 16U + #define ADC0CTL_1_SMOD_ACC_MASK 32U + #define ADC0CTL_1_RVL_BMOD_MASK 64U + #define ADC0CTL_1_CSL_BMOD_MASK 128U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word AUT_RSTA :1; /* Automatic Restart Event after exit from MCU Stop and Wait Mode */ + word SMOD_ACC :1; /* Special Mode Access Control */ + word RVL_BMOD :1; /* RVL Buffer Mode Select */ + word CSL_BMOD :1; /* CSL Buffer Mode Select */ + word MOD_CFG :1; /* Trigger Mode Configuration */ + word STR_SEQA :1; /* Control Of Conversion Result Storage during Sequence abort (SEQA) or Restart request (RSTA) */ + word ACC_CFG :2; /* ADCFLWCTL Register Access Configuration */ + word SWAI :1; /* Wait Mode Configuration */ + word FRZ_MOD :1; /* Freeze Mode Configuration */ + word ADC_SR :1; /* ADC Soft Reset */ + word ADC_EN :1; /* ADC Enable Bit */ + } Bits; +} ADC0CTLSTR; +extern volatile ADC0CTLSTR _ADC0CTL @0x00000600; +#define ADC0CTL _ADC0CTL.Word +#define ADC0CTL_AUT_RSTA _ADC0CTL.Bits.AUT_RSTA +#define ADC0CTL_SMOD_ACC _ADC0CTL.Bits.SMOD_ACC +#define ADC0CTL_RVL_BMOD _ADC0CTL.Bits.RVL_BMOD +#define ADC0CTL_CSL_BMOD _ADC0CTL.Bits.CSL_BMOD +#define ADC0CTL_MOD_CFG _ADC0CTL.Bits.MOD_CFG +#define ADC0CTL_STR_SEQA _ADC0CTL.Bits.STR_SEQA +#define ADC0CTL_ACC_CFG _ADC0CTL.Bits.ACC_CFG +#define ADC0CTL_SWAI _ADC0CTL.Bits.SWAI +#define ADC0CTL_FRZ_MOD _ADC0CTL.Bits.FRZ_MOD +#define ADC0CTL_ADC_SR _ADC0CTL.Bits.ADC_SR +#define ADC0CTL_ADC_EN _ADC0CTL.Bits.ADC_EN + +#define ADC0CTL_AUT_RSTA_MASK 16U +#define ADC0CTL_SMOD_ACC_MASK 32U +#define ADC0CTL_RVL_BMOD_MASK 64U +#define ADC0CTL_CSL_BMOD_MASK 128U +#define ADC0CTL_MOD_CFG_MASK 256U +#define ADC0CTL_STR_SEQA_MASK 512U +#define ADC0CTL_ACC_CFG_MASK 3072U +#define ADC0CTL_ACC_CFG_BITNUM 10U +#define ADC0CTL_SWAI_MASK 4096U +#define ADC0CTL_FRZ_MOD_MASK 8192U +#define ADC0CTL_ADC_SR_MASK 16384U +#define ADC0CTL_ADC_EN_MASK 32768U + + +/*** ADC0STS - ADC0 Status Register; 0x00000602 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte READY :1; /* Flag indicates that ADC is in its idle state and ready for a Restart Event */ + byte :1; + byte DBECC_ERR :1; /* Double Bit ECC Error Flag */ + byte RVL_SEL :1; /* Result Value List Select */ + byte CSL_SEL :1; /* Command Sequence List Select */ + } Bits; +} ADC0STSSTR; +extern volatile ADC0STSSTR _ADC0STS @0x00000602; +#define ADC0STS _ADC0STS.Byte +#define ADC0STS_READY _ADC0STS.Bits.READY +#define ADC0STS_DBECC_ERR _ADC0STS.Bits.DBECC_ERR +#define ADC0STS_RVL_SEL _ADC0STS.Bits.RVL_SEL +#define ADC0STS_CSL_SEL _ADC0STS.Bits.CSL_SEL + +#define ADC0STS_READY_MASK 8U +#define ADC0STS_DBECC_ERR_MASK 32U +#define ADC0STS_RVL_SEL_MASK 64U +#define ADC0STS_CSL_SEL_MASK 128U + + +/*** ADC0TIM - ADC0 Timing Register; 0x00000603 ***/ +typedef union { + byte Byte; + struct { + byte PRS :7; /* ADC Clock Prescaler */ + byte :1; + } Bits; +} ADC0TIMSTR; +extern volatile ADC0TIMSTR _ADC0TIM @0x00000603; +#define ADC0TIM _ADC0TIM.Byte +#define ADC0TIM_PRS _ADC0TIM.Bits.PRS + +#define ADC0TIM_PRS_MASK 127U +#define ADC0TIM_PRS_BITNUM 0U + + +/*** ADC0FMT - ADC0 Format Register; 0x00000604 ***/ +typedef union { + byte Byte; + struct { + byte SRES :3; /* ADC Resolution Select */ + byte :1; + byte :1; + byte :1; + byte :1; + byte DJM :1; /* Result Register Data Justification */ + } Bits; +} ADC0FMTSTR; +extern volatile ADC0FMTSTR _ADC0FMT @0x00000604; +#define ADC0FMT _ADC0FMT.Byte +#define ADC0FMT_SRES _ADC0FMT.Bits.SRES +#define ADC0FMT_DJM _ADC0FMT.Bits.DJM + +#define ADC0FMT_SRES_MASK 7U +#define ADC0FMT_SRES_BITNUM 0U +#define ADC0FMT_DJM_MASK 128U + + +/*** ADC0FLWCTL - ADC0 Conversion Flow Control Register; 0x00000605 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte LDOK :1; /* Load OK for alternative Command Sequence List */ + byte RSTA :1; /* Restart Event (Restart from Top of Command Sequence List) */ + byte TRIG :1; /* Conversion Sequence Trigger */ + byte SEQA :1; /* Conversion Sequence Abort Event */ + } Bits; +} ADC0FLWCTLSTR; +extern volatile ADC0FLWCTLSTR _ADC0FLWCTL @0x00000605; +#define ADC0FLWCTL _ADC0FLWCTL.Byte +#define ADC0FLWCTL_LDOK _ADC0FLWCTL.Bits.LDOK +#define ADC0FLWCTL_RSTA _ADC0FLWCTL.Bits.RSTA +#define ADC0FLWCTL_TRIG _ADC0FLWCTL.Bits.TRIG +#define ADC0FLWCTL_SEQA _ADC0FLWCTL.Bits.SEQA + +#define ADC0FLWCTL_LDOK_MASK 16U +#define ADC0FLWCTL_RSTA_MASK 32U +#define ADC0FLWCTL_TRIG_MASK 64U +#define ADC0FLWCTL_SEQA_MASK 128U + + +/*** ADC0EIE - ADC0 Error Interrupt Enable Register; 0x00000606 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte LDOK_EIE :1; /* Load OK Error Interrupt Enable */ + byte RSTAR_EIE :1; /* Restart Request Error Interrupt Enable */ + byte TRIG_EIE :1; /* Conversion Sequence Trigger Error Interrupt Enable */ + byte :1; + byte EOL_EIE :1; /* End Of List Error Interrupt Enable */ + byte CMD_EIE :1; /* Command Value Error Interrupt Enable */ + byte IA_EIE :1; /* Illegal Access Error Interrupt Enable */ + } Bits; +} ADC0EIESTR; +extern volatile ADC0EIESTR _ADC0EIE @0x00000606; +#define ADC0EIE _ADC0EIE.Byte +#define ADC0EIE_LDOK_EIE _ADC0EIE.Bits.LDOK_EIE +#define ADC0EIE_RSTAR_EIE _ADC0EIE.Bits.RSTAR_EIE +#define ADC0EIE_TRIG_EIE _ADC0EIE.Bits.TRIG_EIE +#define ADC0EIE_EOL_EIE _ADC0EIE.Bits.EOL_EIE +#define ADC0EIE_CMD_EIE _ADC0EIE.Bits.CMD_EIE +#define ADC0EIE_IA_EIE _ADC0EIE.Bits.IA_EIE + +#define ADC0EIE_LDOK_EIE_MASK 2U +#define ADC0EIE_RSTAR_EIE_MASK 4U +#define ADC0EIE_TRIG_EIE_MASK 8U +#define ADC0EIE_EOL_EIE_MASK 32U +#define ADC0EIE_CMD_EIE_MASK 64U +#define ADC0EIE_IA_EIE_MASK 128U + + +/*** ADC0IE - ADC0 Interrupt Enable Register; 0x00000607 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CONIF_OIE :1; /* ADCCONIF Register Flags Overrun Interrupt Enable */ + byte SEQAD_IE :1; /* Conversion Sequence Abort Done Interrupt Enable */ + } Bits; +} ADC0IESTR; +extern volatile ADC0IESTR _ADC0IE @0x00000607; +#define ADC0IE _ADC0IE.Byte +#define ADC0IE_CONIF_OIE _ADC0IE.Bits.CONIF_OIE +#define ADC0IE_SEQAD_IE _ADC0IE.Bits.SEQAD_IE + +#define ADC0IE_CONIF_OIE_MASK 64U +#define ADC0IE_SEQAD_IE_MASK 128U + + +/*** ADC0EIF - ADC0 Error Interrupt Flag Register; 0x00000608 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte LDOK_EIF :1; /* Load OK Error Interrupt Flag */ + byte RSTAR_EIF :1; /* Restart Request Error Interrupt Flag */ + byte TRIG_EIF :1; /* Trigger Error Interrupt Flag */ + byte :1; + byte EOL_EIF :1; /* End Of List Error Interrupt Flag */ + byte CMD_EIF :1; /* Command Value Error Interrupt Flag */ + byte IA_EIF :1; /* Illegal Access Error Interrupt Flag */ + } Bits; +} ADC0EIFSTR; +extern volatile ADC0EIFSTR _ADC0EIF @0x00000608; +#define ADC0EIF _ADC0EIF.Byte +#define ADC0EIF_LDOK_EIF _ADC0EIF.Bits.LDOK_EIF +#define ADC0EIF_RSTAR_EIF _ADC0EIF.Bits.RSTAR_EIF +#define ADC0EIF_TRIG_EIF _ADC0EIF.Bits.TRIG_EIF +#define ADC0EIF_EOL_EIF _ADC0EIF.Bits.EOL_EIF +#define ADC0EIF_CMD_EIF _ADC0EIF.Bits.CMD_EIF +#define ADC0EIF_IA_EIF _ADC0EIF.Bits.IA_EIF + +#define ADC0EIF_LDOK_EIF_MASK 2U +#define ADC0EIF_RSTAR_EIF_MASK 4U +#define ADC0EIF_TRIG_EIF_MASK 8U +#define ADC0EIF_EOL_EIF_MASK 32U +#define ADC0EIF_CMD_EIF_MASK 64U +#define ADC0EIF_IA_EIF_MASK 128U + + +/*** ADC0IF - ADC0 Interrupt Flag Register; 0x00000609 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CONIF_OIF :1; /* ADCxCONIF Register Flags Overrun Interrupt Flag */ + byte SEQAD_IF :1; /* Conversion Sequence Abort Done Interrupt Flag */ + } Bits; +} ADC0IFSTR; +extern volatile ADC0IFSTR _ADC0IF @0x00000609; +#define ADC0IF _ADC0IF.Byte +#define ADC0IF_CONIF_OIF _ADC0IF.Bits.CONIF_OIF +#define ADC0IF_SEQAD_IF _ADC0IF.Bits.SEQAD_IF + +#define ADC0IF_CONIF_OIF_MASK 64U +#define ADC0IF_SEQAD_IF_MASK 128U + + +/*** ADC0CONIE - ADC0 Conversion Interrupt Enable Register; 0x0000060A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0CONIE_0 - ADC0 Conversion Interrupt Enable Register 0; 0x0000060A ***/ + union { + byte Byte; + struct { + byte CON_IE8 :1; /* Conversion Interrupt 8 Enable */ + byte CON_IE9 :1; /* Conversion Interrupt 9 Enable */ + byte CON_IE10 :1; /* Conversion Interrupt 10 Enable */ + byte CON_IE11 :1; /* Conversion Interrupt 11 Enable */ + byte CON_IE12 :1; /* Conversion Interrupt 12 Enable */ + byte CON_IE13 :1; /* Conversion Interrupt 13 Enable */ + byte CON_IE14 :1; /* Conversion Interrupt 14 Enable */ + byte CON_IE15 :1; /* Conversion Interrupt 15 Enable */ + } Bits; + } ADC0CONIE_0STR; + #define ADC0CONIE_0 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Byte + #define ADC0CONIE_0_CON_IE8 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE8 + #define ADC0CONIE_0_CON_IE9 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE9 + #define ADC0CONIE_0_CON_IE10 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE10 + #define ADC0CONIE_0_CON_IE11 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE11 + #define ADC0CONIE_0_CON_IE12 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE12 + #define ADC0CONIE_0_CON_IE13 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE13 + #define ADC0CONIE_0_CON_IE14 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE14 + #define ADC0CONIE_0_CON_IE15 _ADC0CONIE.Overlap_STR.ADC0CONIE_0STR.Bits.CON_IE15 + /* ADC0CONIE__ARR: Access 2 ADC0CONIE_x registers in an array */ + #define ADC0CONIE__ARR ((volatile byte *) &ADC0CONIE_0) + + #define ADC0CONIE_0_CON_IE8_MASK 1U + #define ADC0CONIE_0_CON_IE9_MASK 2U + #define ADC0CONIE_0_CON_IE10_MASK 4U + #define ADC0CONIE_0_CON_IE11_MASK 8U + #define ADC0CONIE_0_CON_IE12_MASK 16U + #define ADC0CONIE_0_CON_IE13_MASK 32U + #define ADC0CONIE_0_CON_IE14_MASK 64U + #define ADC0CONIE_0_CON_IE15_MASK 128U + + + /*** ADC0CONIE_1 - ADC0 Conversion Interrupt Enable Register 1; 0x0000060B ***/ + union { + byte Byte; + struct { + byte EOL_IE :1; /* End Of List Interrupt Enable */ + byte CON_IE1 :1; /* Conversion Interrupt 1 Enable */ + byte CON_IE2 :1; /* Conversion Interrupt 2 Enable */ + byte CON_IE3 :1; /* Conversion Interrupt 3 Enable */ + byte CON_IE4 :1; /* Conversion Interrupt 4 Enable */ + byte CON_IE5 :1; /* Conversion Interrupt 5 Enable */ + byte CON_IE6 :1; /* Conversion Interrupt 6 Enable */ + byte CON_IE7 :1; /* Conversion Interrupt 7 Enable */ + } Bits; + struct { + byte :1; + byte grpCON_IE_1 :7; + } MergedBits; + } ADC0CONIE_1STR; + #define ADC0CONIE_1 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Byte + #define ADC0CONIE_1_EOL_IE _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.EOL_IE + #define ADC0CONIE_1_CON_IE1 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE1 + #define ADC0CONIE_1_CON_IE2 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE2 + #define ADC0CONIE_1_CON_IE3 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE3 + #define ADC0CONIE_1_CON_IE4 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE4 + #define ADC0CONIE_1_CON_IE5 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE5 + #define ADC0CONIE_1_CON_IE6 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE6 + #define ADC0CONIE_1_CON_IE7 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.Bits.CON_IE7 + #define ADC0CONIE_1_CON_IE_1 _ADC0CONIE.Overlap_STR.ADC0CONIE_1STR.MergedBits.grpCON_IE_1 + #define ADC0CONIE_1_CON_IE ADC0CONIE_1_CON_IE_1 + + #define ADC0CONIE_1_EOL_IE_MASK 1U + #define ADC0CONIE_1_CON_IE1_MASK 2U + #define ADC0CONIE_1_CON_IE2_MASK 4U + #define ADC0CONIE_1_CON_IE3_MASK 8U + #define ADC0CONIE_1_CON_IE4_MASK 16U + #define ADC0CONIE_1_CON_IE5_MASK 32U + #define ADC0CONIE_1_CON_IE6_MASK 64U + #define ADC0CONIE_1_CON_IE7_MASK 128U + #define ADC0CONIE_1_CON_IE_1_MASK 254U + #define ADC0CONIE_1_CON_IE_1_BITNUM 1U + + } Overlap_STR; + + struct { + word EOL_IE :1; /* End Of List Interrupt Enable */ + word CON_IE1 :1; /* Conversion Interrupt 1 Enable */ + word CON_IE2 :1; /* Conversion Interrupt 2 Enable */ + word CON_IE3 :1; /* Conversion Interrupt 3 Enable */ + word CON_IE4 :1; /* Conversion Interrupt 4 Enable */ + word CON_IE5 :1; /* Conversion Interrupt 5 Enable */ + word CON_IE6 :1; /* Conversion Interrupt 6 Enable */ + word CON_IE7 :1; /* Conversion Interrupt 7 Enable */ + word CON_IE8 :1; /* Conversion Interrupt 8 Enable */ + word CON_IE9 :1; /* Conversion Interrupt 9 Enable */ + word CON_IE10 :1; /* Conversion Interrupt 10 Enable */ + word CON_IE11 :1; /* Conversion Interrupt 11 Enable */ + word CON_IE12 :1; /* Conversion Interrupt 12 Enable */ + word CON_IE13 :1; /* Conversion Interrupt 13 Enable */ + word CON_IE14 :1; /* Conversion Interrupt 14 Enable */ + word CON_IE15 :1; /* Conversion Interrupt 15 Enable */ + } Bits; + struct { + word :1; + word grpCON_IE_1 :15; + } MergedBits; +} ADC0CONIESTR; +extern volatile ADC0CONIESTR _ADC0CONIE @0x0000060A; +#define ADC0CONIE _ADC0CONIE.Word +#define ADC0CONIE_EOL_IE _ADC0CONIE.Bits.EOL_IE +#define ADC0CONIE_CON_IE1 _ADC0CONIE.Bits.CON_IE1 +#define ADC0CONIE_CON_IE2 _ADC0CONIE.Bits.CON_IE2 +#define ADC0CONIE_CON_IE3 _ADC0CONIE.Bits.CON_IE3 +#define ADC0CONIE_CON_IE4 _ADC0CONIE.Bits.CON_IE4 +#define ADC0CONIE_CON_IE5 _ADC0CONIE.Bits.CON_IE5 +#define ADC0CONIE_CON_IE6 _ADC0CONIE.Bits.CON_IE6 +#define ADC0CONIE_CON_IE7 _ADC0CONIE.Bits.CON_IE7 +#define ADC0CONIE_CON_IE8 _ADC0CONIE.Bits.CON_IE8 +#define ADC0CONIE_CON_IE9 _ADC0CONIE.Bits.CON_IE9 +#define ADC0CONIE_CON_IE10 _ADC0CONIE.Bits.CON_IE10 +#define ADC0CONIE_CON_IE11 _ADC0CONIE.Bits.CON_IE11 +#define ADC0CONIE_CON_IE12 _ADC0CONIE.Bits.CON_IE12 +#define ADC0CONIE_CON_IE13 _ADC0CONIE.Bits.CON_IE13 +#define ADC0CONIE_CON_IE14 _ADC0CONIE.Bits.CON_IE14 +#define ADC0CONIE_CON_IE15 _ADC0CONIE.Bits.CON_IE15 +#define ADC0CONIE_CON_IE_1 _ADC0CONIE.MergedBits.grpCON_IE_1 +#define ADC0CONIE_CON_IE ADC0CONIE_CON_IE_1 + +#define ADC0CONIE_EOL_IE_MASK 1U +#define ADC0CONIE_CON_IE1_MASK 2U +#define ADC0CONIE_CON_IE2_MASK 4U +#define ADC0CONIE_CON_IE3_MASK 8U +#define ADC0CONIE_CON_IE4_MASK 16U +#define ADC0CONIE_CON_IE5_MASK 32U +#define ADC0CONIE_CON_IE6_MASK 64U +#define ADC0CONIE_CON_IE7_MASK 128U +#define ADC0CONIE_CON_IE8_MASK 256U +#define ADC0CONIE_CON_IE9_MASK 512U +#define ADC0CONIE_CON_IE10_MASK 1024U +#define ADC0CONIE_CON_IE11_MASK 2048U +#define ADC0CONIE_CON_IE12_MASK 4096U +#define ADC0CONIE_CON_IE13_MASK 8192U +#define ADC0CONIE_CON_IE14_MASK 16384U +#define ADC0CONIE_CON_IE15_MASK 32768U +#define ADC0CONIE_CON_IE_1_MASK 65534U +#define ADC0CONIE_CON_IE_1_BITNUM 1U + + +/*** ADC0CONIF - ADC0 Conversion Interrupt Flag Register; 0x0000060C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0CONIF_0 - ADC0 Conversion Interrupt Flag Register 0; 0x0000060C ***/ + union { + byte Byte; + struct { + byte CON_IF8 :1; /* Conversion Interrupt 8 Flag */ + byte CON_IF9 :1; /* Conversion Interrupt 9 Flag */ + byte CON_IF10 :1; /* Conversion Interrupt 10 Flag */ + byte CON_IF11 :1; /* Conversion Interrupt 11 Flag */ + byte CON_IF12 :1; /* Conversion Interrupt 12 Flag */ + byte CON_IF13 :1; /* Conversion Interrupt 13 Flag */ + byte CON_IF14 :1; /* Conversion Interrupt 14 Flag */ + byte CON_IF15 :1; /* Conversion Interrupt 15 Flag */ + } Bits; + } ADC0CONIF_0STR; + #define ADC0CONIF_0 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Byte + #define ADC0CONIF_0_CON_IF8 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF8 + #define ADC0CONIF_0_CON_IF9 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF9 + #define ADC0CONIF_0_CON_IF10 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF10 + #define ADC0CONIF_0_CON_IF11 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF11 + #define ADC0CONIF_0_CON_IF12 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF12 + #define ADC0CONIF_0_CON_IF13 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF13 + #define ADC0CONIF_0_CON_IF14 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF14 + #define ADC0CONIF_0_CON_IF15 _ADC0CONIF.Overlap_STR.ADC0CONIF_0STR.Bits.CON_IF15 + /* ADC0CONIF__ARR: Access 2 ADC0CONIF_x registers in an array */ + #define ADC0CONIF__ARR ((volatile byte *) &ADC0CONIF_0) + + #define ADC0CONIF_0_CON_IF8_MASK 1U + #define ADC0CONIF_0_CON_IF9_MASK 2U + #define ADC0CONIF_0_CON_IF10_MASK 4U + #define ADC0CONIF_0_CON_IF11_MASK 8U + #define ADC0CONIF_0_CON_IF12_MASK 16U + #define ADC0CONIF_0_CON_IF13_MASK 32U + #define ADC0CONIF_0_CON_IF14_MASK 64U + #define ADC0CONIF_0_CON_IF15_MASK 128U + + + /*** ADC0CONIF_1 - ADC0 Conversion Interrupt Flag Register 1; 0x0000060D ***/ + union { + byte Byte; + struct { + byte EOL_IF :1; /* End Of List Interrupt Flag */ + byte CON_IF1 :1; /* Conversion Interrupt 1 Flag */ + byte CON_IF2 :1; /* Conversion Interrupt 2 Flag */ + byte CON_IF3 :1; /* Conversion Interrupt 3 Flag */ + byte CON_IF4 :1; /* Conversion Interrupt 4 Flag */ + byte CON_IF5 :1; /* Conversion Interrupt 5 Flag */ + byte CON_IF6 :1; /* Conversion Interrupt 6 Flag */ + byte CON_IF7 :1; /* Conversion Interrupt 7 Flag */ + } Bits; + struct { + byte :1; + byte grpCON_IF_1 :7; + } MergedBits; + } ADC0CONIF_1STR; + #define ADC0CONIF_1 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Byte + #define ADC0CONIF_1_EOL_IF _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.EOL_IF + #define ADC0CONIF_1_CON_IF1 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF1 + #define ADC0CONIF_1_CON_IF2 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF2 + #define ADC0CONIF_1_CON_IF3 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF3 + #define ADC0CONIF_1_CON_IF4 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF4 + #define ADC0CONIF_1_CON_IF5 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF5 + #define ADC0CONIF_1_CON_IF6 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF6 + #define ADC0CONIF_1_CON_IF7 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.Bits.CON_IF7 + #define ADC0CONIF_1_CON_IF_1 _ADC0CONIF.Overlap_STR.ADC0CONIF_1STR.MergedBits.grpCON_IF_1 + #define ADC0CONIF_1_CON_IF ADC0CONIF_1_CON_IF_1 + + #define ADC0CONIF_1_EOL_IF_MASK 1U + #define ADC0CONIF_1_CON_IF1_MASK 2U + #define ADC0CONIF_1_CON_IF2_MASK 4U + #define ADC0CONIF_1_CON_IF3_MASK 8U + #define ADC0CONIF_1_CON_IF4_MASK 16U + #define ADC0CONIF_1_CON_IF5_MASK 32U + #define ADC0CONIF_1_CON_IF6_MASK 64U + #define ADC0CONIF_1_CON_IF7_MASK 128U + #define ADC0CONIF_1_CON_IF_1_MASK 254U + #define ADC0CONIF_1_CON_IF_1_BITNUM 1U + + } Overlap_STR; + + struct { + word EOL_IF :1; /* End Of List Interrupt Flag */ + word CON_IF1 :1; /* Conversion Interrupt 1 Flag */ + word CON_IF2 :1; /* Conversion Interrupt 2 Flag */ + word CON_IF3 :1; /* Conversion Interrupt 3 Flag */ + word CON_IF4 :1; /* Conversion Interrupt 4 Flag */ + word CON_IF5 :1; /* Conversion Interrupt 5 Flag */ + word CON_IF6 :1; /* Conversion Interrupt 6 Flag */ + word CON_IF7 :1; /* Conversion Interrupt 7 Flag */ + word CON_IF8 :1; /* Conversion Interrupt 8 Flag */ + word CON_IF9 :1; /* Conversion Interrupt 9 Flag */ + word CON_IF10 :1; /* Conversion Interrupt 10 Flag */ + word CON_IF11 :1; /* Conversion Interrupt 11 Flag */ + word CON_IF12 :1; /* Conversion Interrupt 12 Flag */ + word CON_IF13 :1; /* Conversion Interrupt 13 Flag */ + word CON_IF14 :1; /* Conversion Interrupt 14 Flag */ + word CON_IF15 :1; /* Conversion Interrupt 15 Flag */ + } Bits; + struct { + word :1; + word grpCON_IF_1 :15; + } MergedBits; +} ADC0CONIFSTR; +extern volatile ADC0CONIFSTR _ADC0CONIF @0x0000060C; +#define ADC0CONIF _ADC0CONIF.Word +#define ADC0CONIF_EOL_IF _ADC0CONIF.Bits.EOL_IF +#define ADC0CONIF_CON_IF1 _ADC0CONIF.Bits.CON_IF1 +#define ADC0CONIF_CON_IF2 _ADC0CONIF.Bits.CON_IF2 +#define ADC0CONIF_CON_IF3 _ADC0CONIF.Bits.CON_IF3 +#define ADC0CONIF_CON_IF4 _ADC0CONIF.Bits.CON_IF4 +#define ADC0CONIF_CON_IF5 _ADC0CONIF.Bits.CON_IF5 +#define ADC0CONIF_CON_IF6 _ADC0CONIF.Bits.CON_IF6 +#define ADC0CONIF_CON_IF7 _ADC0CONIF.Bits.CON_IF7 +#define ADC0CONIF_CON_IF8 _ADC0CONIF.Bits.CON_IF8 +#define ADC0CONIF_CON_IF9 _ADC0CONIF.Bits.CON_IF9 +#define ADC0CONIF_CON_IF10 _ADC0CONIF.Bits.CON_IF10 +#define ADC0CONIF_CON_IF11 _ADC0CONIF.Bits.CON_IF11 +#define ADC0CONIF_CON_IF12 _ADC0CONIF.Bits.CON_IF12 +#define ADC0CONIF_CON_IF13 _ADC0CONIF.Bits.CON_IF13 +#define ADC0CONIF_CON_IF14 _ADC0CONIF.Bits.CON_IF14 +#define ADC0CONIF_CON_IF15 _ADC0CONIF.Bits.CON_IF15 +#define ADC0CONIF_CON_IF_1 _ADC0CONIF.MergedBits.grpCON_IF_1 +#define ADC0CONIF_CON_IF ADC0CONIF_CON_IF_1 + +#define ADC0CONIF_EOL_IF_MASK 1U +#define ADC0CONIF_CON_IF1_MASK 2U +#define ADC0CONIF_CON_IF2_MASK 4U +#define ADC0CONIF_CON_IF3_MASK 8U +#define ADC0CONIF_CON_IF4_MASK 16U +#define ADC0CONIF_CON_IF5_MASK 32U +#define ADC0CONIF_CON_IF6_MASK 64U +#define ADC0CONIF_CON_IF7_MASK 128U +#define ADC0CONIF_CON_IF8_MASK 256U +#define ADC0CONIF_CON_IF9_MASK 512U +#define ADC0CONIF_CON_IF10_MASK 1024U +#define ADC0CONIF_CON_IF11_MASK 2048U +#define ADC0CONIF_CON_IF12_MASK 4096U +#define ADC0CONIF_CON_IF13_MASK 8192U +#define ADC0CONIF_CON_IF14_MASK 16384U +#define ADC0CONIF_CON_IF15_MASK 32768U +#define ADC0CONIF_CON_IF_1_MASK 65534U +#define ADC0CONIF_CON_IF_1_BITNUM 1U + + +/*** ADC0IMDRI - ADC0 Intermediate Result Information Register; 0x0000060E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0IMDRI_0 - ADC0 Intermediate Result Information Register 0; 0x0000060E ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RVL_IMD :1; /* Active RVL At Intermediate Event */ + byte CSL_IMD :1; /* Active CSL At Intermediate Event */ + } Bits; + } ADC0IMDRI_0STR; + #define ADC0IMDRI_0 _ADC0IMDRI.Overlap_STR.ADC0IMDRI_0STR.Byte + #define ADC0IMDRI_0_RVL_IMD _ADC0IMDRI.Overlap_STR.ADC0IMDRI_0STR.Bits.RVL_IMD + #define ADC0IMDRI_0_CSL_IMD _ADC0IMDRI.Overlap_STR.ADC0IMDRI_0STR.Bits.CSL_IMD + /* ADC0IMDRI__ARR: Access 2 ADC0IMDRI_x registers in an array */ + #define ADC0IMDRI__ARR ((volatile byte *) &ADC0IMDRI_0) + + #define ADC0IMDRI_0_RVL_IMD_MASK 64U + #define ADC0IMDRI_0_CSL_IMD_MASK 128U + + + /*** ADC0IMDRI_1 - ADC0 Intermediate Result Information Register 1; 0x0000060F ***/ + union { + byte Byte; + struct { + byte RIDX_IMD :6; /* RES_IDX Value At Intermediate Event */ + byte :1; + byte :1; + } Bits; + } ADC0IMDRI_1STR; + #define ADC0IMDRI_1 _ADC0IMDRI.Overlap_STR.ADC0IMDRI_1STR.Byte + #define ADC0IMDRI_1_RIDX_IMD _ADC0IMDRI.Overlap_STR.ADC0IMDRI_1STR.Bits.RIDX_IMD + + #define ADC0IMDRI_1_RIDX_IMD_MASK 63U + #define ADC0IMDRI_1_RIDX_IMD_BITNUM 0U + + } Overlap_STR; + + struct { + word RIDX_IMD :6; /* RES_IDX Value At Intermediate Event */ + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word RVL_IMD :1; /* Active RVL At Intermediate Event */ + word CSL_IMD :1; /* Active CSL At Intermediate Event */ + } Bits; +} ADC0IMDRISTR; +extern volatile ADC0IMDRISTR _ADC0IMDRI @0x0000060E; +#define ADC0IMDRI _ADC0IMDRI.Word +#define ADC0IMDRI_RIDX_IMD _ADC0IMDRI.Bits.RIDX_IMD +#define ADC0IMDRI_RVL_IMD _ADC0IMDRI.Bits.RVL_IMD +#define ADC0IMDRI_CSL_IMD _ADC0IMDRI.Bits.CSL_IMD + +#define ADC0IMDRI_RIDX_IMD_MASK 63U +#define ADC0IMDRI_RIDX_IMD_BITNUM 0U +#define ADC0IMDRI_RVL_IMD_MASK 16384U +#define ADC0IMDRI_CSL_IMD_MASK 32768U + + +/*** ADC0EOLRI - ADC0 End Of List Result Information Register; 0x00000610 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RVL_EOL :1; /* Active RVL When End Of List Command Type Was Executed */ + byte CSL_EOL :1; /* Active CSL When End Of List Command Type Was Executed */ + } Bits; +} ADC0EOLRISTR; +extern volatile ADC0EOLRISTR _ADC0EOLRI @0x00000610; +#define ADC0EOLRI _ADC0EOLRI.Byte +#define ADC0EOLRI_RVL_EOL _ADC0EOLRI.Bits.RVL_EOL +#define ADC0EOLRI_CSL_EOL _ADC0EOLRI.Bits.CSL_EOL + +#define ADC0EOLRI_RVL_EOL_MASK 64U +#define ADC0EOLRI_CSL_EOL_MASK 128U + + +/*** ADC0CMD - ADC0 Command Register; 0x00000614 ***/ +typedef union { + dword Dword; + /* Overlapped registers: */ + struct { + /*** ADC0CMD_01 - ADC0 Command Register 01; 0x00000614 ***/ + union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0CMD_0 - ADC0 Command Register 0; 0x00000614 ***/ + union { + byte Byte; + struct { + byte INTFLG_SEL :4; /* Conversion Interrupt Flag Select */ + byte :1; + byte :1; + byte CMD_SEL :2; /* Conversion Command Select */ + } Bits; + } ADC0CMD_0STR; + #define ADC0CMD_0 _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_0STR.Byte + #define ADC0CMD_0_INTFLG_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_0STR.Bits.INTFLG_SEL + #define ADC0CMD_0_CMD_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_0STR.Bits.CMD_SEL + /* ADC0CMD__ARR: Access 4 ADC0CMD_x registers in an array */ + #define ADC0CMD__ARR ((volatile byte *) &ADC0CMD_0) + + #define ADC0CMD_0_INTFLG_SEL_MASK 15U + #define ADC0CMD_0_INTFLG_SEL_BITNUM 0U + #define ADC0CMD_0_CMD_SEL_MASK 192U + #define ADC0CMD_0_CMD_SEL_BITNUM 6U + + + /*** ADC0CMD_1 - ADC0 Command Register 1; 0x00000615 ***/ + union { + byte Byte; + struct { + byte CH_SEL :6; /* ADC Input Channel Select */ + byte VRL_SEL :1; /* Reference Low Voltage Select */ + byte VRH_SEL :1; /* Reference High Voltage Select */ + } Bits; + } ADC0CMD_1STR; + #define ADC0CMD_1 _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_1STR.Byte + #define ADC0CMD_1_CH_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_1STR.Bits.CH_SEL + #define ADC0CMD_1_VRL_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_1STR.Bits.VRL_SEL + #define ADC0CMD_1_VRH_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Overlap_STR.ADC0CMD_1STR.Bits.VRH_SEL + + #define ADC0CMD_1_CH_SEL_MASK 63U + #define ADC0CMD_1_CH_SEL_BITNUM 0U + #define ADC0CMD_1_VRL_SEL_MASK 64U + #define ADC0CMD_1_VRH_SEL_MASK 128U + + } Overlap_STR; + + struct { + word CH_SEL :6; /* ADC Input Channel Select */ + word VRL_SEL :1; /* Reference Low Voltage Select */ + word VRH_SEL :1; /* Reference High Voltage Select */ + word INTFLG_SEL :4; /* Conversion Interrupt Flag Select */ + word :1; + word :1; + word CMD_SEL :2; /* Conversion Command Select */ + } Bits; + } ADC0CMD_01STR; + #define ADC0CMD_01 _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Word + #define ADC0CMD_01_CH_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Bits.CH_SEL + #define ADC0CMD_01_VRL_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Bits.VRL_SEL + #define ADC0CMD_01_VRH_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Bits.VRH_SEL + #define ADC0CMD_01_INTFLG_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Bits.INTFLG_SEL + #define ADC0CMD_01_CMD_SEL _ADC0CMD.Overlap_STR.ADC0CMD_01STR.Bits.CMD_SEL + + #define ADC0CMD_01_CH_SEL_MASK 63U + #define ADC0CMD_01_CH_SEL_BITNUM 0U + #define ADC0CMD_01_VRL_SEL_MASK 64U + #define ADC0CMD_01_VRH_SEL_MASK 128U + #define ADC0CMD_01_INTFLG_SEL_MASK 3840U + #define ADC0CMD_01_INTFLG_SEL_BITNUM 8U + #define ADC0CMD_01_CMD_SEL_MASK 49152U + #define ADC0CMD_01_CMD_SEL_BITNUM 14U + + + /*** ADC0CMD_23 - ADC0 Command Register 23; 0x00000616 ***/ + union { + word Word; + /* Overlapped registers: */ + struct { + /*** ADC0CMD_2 - ADC0 Command Register 2; 0x00000616 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte SMP :5; /* Sample Time Select */ + } Bits; + } ADC0CMD_2STR; + #define ADC0CMD_2 _ADC0CMD.Overlap_STR.ADC0CMD_23STR.Overlap_STR.ADC0CMD_2STR.Byte + #define ADC0CMD_2_SMP _ADC0CMD.Overlap_STR.ADC0CMD_23STR.Overlap_STR.ADC0CMD_2STR.Bits.SMP + + #define ADC0CMD_2_SMP_MASK 248U + #define ADC0CMD_2_SMP_BITNUM 3U + + + /*** ADC0CMD_3 - ADC0 Command Register 3; 0x00000617 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + } ADC0CMD_3STR; + #define ADC0CMD_3 _ADC0CMD.Overlap_STR.ADC0CMD_23STR.Overlap_STR.ADC0CMD_3STR.Byte + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word SMP :5; /* Sample Time Select */ + } Bits; + } ADC0CMD_23STR; + #define ADC0CMD_23 _ADC0CMD.Overlap_STR.ADC0CMD_23STR.Word + #define ADC0CMD_23_SMP _ADC0CMD.Overlap_STR.ADC0CMD_23STR.Bits.SMP + + #define ADC0CMD_23_SMP_MASK 63488U + #define ADC0CMD_23_SMP_BITNUM 11U + + } Overlap_STR; + +} ADC0CMDSTR; +extern volatile ADC0CMDSTR _ADC0CMD @0x00000614; +#define ADC0CMD _ADC0CMD.Dword + + +/*** ADC0CIDX - ADC0 Command Index Register; 0x0000061C ***/ +typedef union { + byte Byte; + struct { + byte CMD_IDX :6; /* ADC Command Index */ + byte :1; + byte :1; + } Bits; +} ADC0CIDXSTR; +extern volatile ADC0CIDXSTR _ADC0CIDX @0x0000061C; +#define ADC0CIDX _ADC0CIDX.Byte +#define ADC0CIDX_CMD_IDX _ADC0CIDX.Bits.CMD_IDX + +#define ADC0CIDX_CMD_IDX_MASK 63U +#define ADC0CIDX_CMD_IDX_BITNUM 0U + + +/*** ADC0CBP_0 - ADC0 Command Base Pointer Register 0; 0x0000061D ***/ +typedef union { + byte Byte; + struct { + byte CMD_PTR :8; /* ADC Command Base Pointer Address */ + } Bits; +} ADC0CBP_0STR; +extern volatile ADC0CBP_0STR _ADC0CBP_0 @0x0000061D; +#define ADC0CBP_0 _ADC0CBP_0.Byte +#define ADC0CBP_0_CMD_PTR _ADC0CBP_0.Bits.CMD_PTR +/* ADC0CBP__ARR: Access 3 ADC0CBP_x registers in an array */ +#define ADC0CBP__ARR ((volatile byte *) &ADC0CBP_0) + +#define ADC0CBP_0_CMD_PTR_MASK 255U +#define ADC0CBP_0_CMD_PTR_BITNUM 0U + + +/*** ADC0CBP_1 - ADC0 Command Base Pointer Register 1; 0x0000061E ***/ +typedef union { + byte Byte; + struct { + byte CMD_PTR :8; /* ADC Command Base Pointer Address */ + } Bits; +} ADC0CBP_1STR; +extern volatile ADC0CBP_1STR _ADC0CBP_1 @0x0000061E; +#define ADC0CBP_1 _ADC0CBP_1.Byte +#define ADC0CBP_1_CMD_PTR _ADC0CBP_1.Bits.CMD_PTR + +#define ADC0CBP_1_CMD_PTR_MASK 255U +#define ADC0CBP_1_CMD_PTR_BITNUM 0U + + +/*** ADC0CBP_2 - ADC0 Command Base Pointer Register 2; 0x0000061F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte CMD_PTR :6; /* ADC Command Base Pointer Address */ + } Bits; +} ADC0CBP_2STR; +extern volatile ADC0CBP_2STR _ADC0CBP_2 @0x0000061F; +#define ADC0CBP_2 _ADC0CBP_2.Byte +#define ADC0CBP_2_CMD_PTR _ADC0CBP_2.Bits.CMD_PTR + +#define ADC0CBP_2_CMD_PTR_MASK 252U +#define ADC0CBP_2_CMD_PTR_BITNUM 2U + + +/*** ADC0RIDX - ADC0 Result Index Register; 0x00000620 ***/ +typedef union { + byte Byte; + struct { + byte RES_IDX :6; /* ADC Result Index */ + byte :1; + byte :1; + } Bits; +} ADC0RIDXSTR; +extern volatile ADC0RIDXSTR _ADC0RIDX @0x00000620; +#define ADC0RIDX _ADC0RIDX.Byte +#define ADC0RIDX_RES_IDX _ADC0RIDX.Bits.RES_IDX + +#define ADC0RIDX_RES_IDX_MASK 63U +#define ADC0RIDX_RES_IDX_BITNUM 0U + + +/*** ADC0RBP_0 - ADC0 Result Base Pointer Register 0; 0x00000621 ***/ +typedef union { + byte Byte; + struct { + byte RES_PTR :4; /* ADC Result Base Pointer Address */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ADC0RBP_0STR; +extern volatile ADC0RBP_0STR _ADC0RBP_0 @0x00000621; +#define ADC0RBP_0 _ADC0RBP_0.Byte +#define ADC0RBP_0_RES_PTR _ADC0RBP_0.Bits.RES_PTR +/* ADC0RBP__ARR: Access 3 ADC0RBP_x registers in an array */ +#define ADC0RBP__ARR ((volatile byte *) &ADC0RBP_0) + +#define ADC0RBP_0_RES_PTR_MASK 15U +#define ADC0RBP_0_RES_PTR_BITNUM 0U + + +/*** ADC0RBP_1 - ADC0 Result Base Pointer Register 1; 0x00000622 ***/ +typedef union { + byte Byte; + struct { + byte RES_PTR :8; /* ADC Result Base Pointer Address */ + } Bits; +} ADC0RBP_1STR; +extern volatile ADC0RBP_1STR _ADC0RBP_1 @0x00000622; +#define ADC0RBP_1 _ADC0RBP_1.Byte +#define ADC0RBP_1_RES_PTR _ADC0RBP_1.Bits.RES_PTR + +#define ADC0RBP_1_RES_PTR_MASK 255U +#define ADC0RBP_1_RES_PTR_BITNUM 0U + + +/*** ADC0RBP_2 - ADC0 Result Base Pointer Register 2; 0x00000623 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RES_PTR :6; /* ADC Result Base Pointer Address */ + } Bits; +} ADC0RBP_2STR; +extern volatile ADC0RBP_2STR _ADC0RBP_2 @0x00000623; +#define ADC0RBP_2 _ADC0RBP_2.Byte +#define ADC0RBP_2_RES_PTR _ADC0RBP_2.Bits.RES_PTR + +#define ADC0RBP_2_RES_PTR_MASK 252U +#define ADC0RBP_2_RES_PTR_BITNUM 2U + + +/*** ADC0CROFF0 - ADC0 Command and Result Offset Register 0; 0x00000624 ***/ +typedef union { + byte Byte; + struct { + byte CMDRES_OFF0 :7; /* ADC Command and Result Offset Value refer to CSL_0 and RVL_0 */ + byte :1; + } Bits; +} ADC0CROFF0STR; +extern volatile ADC0CROFF0STR _ADC0CROFF0 @0x00000624; +#define ADC0CROFF0 _ADC0CROFF0.Byte +#define ADC0CROFF0_CMDRES_OFF0 _ADC0CROFF0.Bits.CMDRES_OFF0 +/* ADC0CROFF_ARR: Access 2 ADC0CROFFx registers in an array */ +#define ADC0CROFF_ARR ((volatile byte *) &ADC0CROFF0) + +#define ADC0CROFF0_CMDRES_OFF0_MASK 127U +#define ADC0CROFF0_CMDRES_OFF0_BITNUM 0U + + +/*** ADC0CROFF1 - ADC0 Command and Result Offset Register 1; 0x00000625 ***/ +typedef union { + byte Byte; + struct { + byte CMDRES_OFF1 :7; /* ADC Command and Result Offset Value refer to CSL_1 and RVL_1 */ + byte :1; + } Bits; +} ADC0CROFF1STR; +extern volatile ADC0CROFF1STR _ADC0CROFF1 @0x00000625; +#define ADC0CROFF1 _ADC0CROFF1.Byte +#define ADC0CROFF1_CMDRES_OFF1 _ADC0CROFF1.Bits.CMDRES_OFF1 + +#define ADC0CROFF1_CMDRES_OFF1_MASK 127U +#define ADC0CROFF1_CMDRES_OFF1_BITNUM 0U + + +/*** CPMURFLG - CPMU Reset Flags Register; 0x000006C3 ***/ +typedef union { + byte Byte; + struct { + byte PMRF :1; /* PLL Clock Monitor Reset Flag */ + byte OMRF :1; /* Oscillator Clock Monitor Reset Flag */ + byte :1; + byte COPRF :1; /* COP Reset Flag */ + byte :1; + byte LVRF :1; /* Low Voltage Reset Flag */ + byte PORF :1; /* Power on Reset Flag */ + byte :1; + } Bits; +} CPMURFLGSTR; +extern volatile CPMURFLGSTR _CPMURFLG @0x000006C3; +#define CPMURFLG _CPMURFLG.Byte +#define CPMURFLG_PMRF _CPMURFLG.Bits.PMRF +#define CPMURFLG_OMRF _CPMURFLG.Bits.OMRF +#define CPMURFLG_COPRF _CPMURFLG.Bits.COPRF +#define CPMURFLG_LVRF _CPMURFLG.Bits.LVRF +#define CPMURFLG_PORF _CPMURFLG.Bits.PORF + +#define CPMURFLG_PMRF_MASK 1U +#define CPMURFLG_OMRF_MASK 2U +#define CPMURFLG_COPRF_MASK 8U +#define CPMURFLG_LVRF_MASK 32U +#define CPMURFLG_PORF_MASK 64U + + +/*** CPMUSYNR - CPMU Synthesizer Register; 0x000006C4 ***/ +typedef union { + byte Byte; + struct { + byte SYNDIV0 :1; /* Multiplication factor of the IPLL bit 0 */ + byte SYNDIV1 :1; /* Multiplication factor of the IPLL bit 1 */ + byte SYNDIV2 :1; /* Multiplication factor of the IPLL bit 2 */ + byte SYNDIV3 :1; /* Multiplication factor of the IPLL bit 3 */ + byte SYNDIV4 :1; /* Multiplication factor of the IPLL bit 4 */ + byte SYNDIV5 :1; /* Multiplication factor of the IPLL bit 5 */ + byte VCOFRQ0 :1; /* VCO frequency range bit 0 */ + byte VCOFRQ1 :1; /* VCO frequency range bit 1 */ + } Bits; + struct { + byte grpSYNDIV :6; + byte grpVCOFRQ :2; + } MergedBits; +} CPMUSYNRSTR; +extern volatile CPMUSYNRSTR _CPMUSYNR @0x000006C4; +#define CPMUSYNR _CPMUSYNR.Byte +#define CPMUSYNR_SYNDIV0 _CPMUSYNR.Bits.SYNDIV0 +#define CPMUSYNR_SYNDIV1 _CPMUSYNR.Bits.SYNDIV1 +#define CPMUSYNR_SYNDIV2 _CPMUSYNR.Bits.SYNDIV2 +#define CPMUSYNR_SYNDIV3 _CPMUSYNR.Bits.SYNDIV3 +#define CPMUSYNR_SYNDIV4 _CPMUSYNR.Bits.SYNDIV4 +#define CPMUSYNR_SYNDIV5 _CPMUSYNR.Bits.SYNDIV5 +#define CPMUSYNR_VCOFRQ0 _CPMUSYNR.Bits.VCOFRQ0 +#define CPMUSYNR_VCOFRQ1 _CPMUSYNR.Bits.VCOFRQ1 +#define CPMUSYNR_SYNDIV _CPMUSYNR.MergedBits.grpSYNDIV +#define CPMUSYNR_VCOFRQ _CPMUSYNR.MergedBits.grpVCOFRQ + +#define CPMUSYNR_SYNDIV0_MASK 1U +#define CPMUSYNR_SYNDIV1_MASK 2U +#define CPMUSYNR_SYNDIV2_MASK 4U +#define CPMUSYNR_SYNDIV3_MASK 8U +#define CPMUSYNR_SYNDIV4_MASK 16U +#define CPMUSYNR_SYNDIV5_MASK 32U +#define CPMUSYNR_VCOFRQ0_MASK 64U +#define CPMUSYNR_VCOFRQ1_MASK 128U +#define CPMUSYNR_SYNDIV_MASK 63U +#define CPMUSYNR_SYNDIV_BITNUM 0U +#define CPMUSYNR_VCOFRQ_MASK 192U +#define CPMUSYNR_VCOFRQ_BITNUM 6U + + +/*** CPMUREFDIV - CPMU Reference Divider Register; 0x000006C5 ***/ +typedef union { + byte Byte; + struct { + byte REFDIV0 :1; /* Finer granularity for the IPLL multiplier steps bit 0 */ + byte REFDIV1 :1; /* Finer granularity for the IPLL multiplier steps bit 1 */ + byte REFDIV2 :1; /* Finer granularity for the IPLL multiplier steps bit 2 */ + byte REFDIV3 :1; /* Finer granularity for the IPLL multiplier steps bit 3 */ + byte :1; + byte :1; + byte REFFRQ0 :1; /* IPLL optimal stability and lock time configuration bit 0 */ + byte REFFRQ1 :1; /* IPLL optimal stability and lock time configuration bit 1 */ + } Bits; + struct { + byte grpREFDIV :4; + byte :1; + byte :1; + byte grpREFFRQ :2; + } MergedBits; +} CPMUREFDIVSTR; +extern volatile CPMUREFDIVSTR _CPMUREFDIV @0x000006C5; +#define CPMUREFDIV _CPMUREFDIV.Byte +#define CPMUREFDIV_REFDIV0 _CPMUREFDIV.Bits.REFDIV0 +#define CPMUREFDIV_REFDIV1 _CPMUREFDIV.Bits.REFDIV1 +#define CPMUREFDIV_REFDIV2 _CPMUREFDIV.Bits.REFDIV2 +#define CPMUREFDIV_REFDIV3 _CPMUREFDIV.Bits.REFDIV3 +#define CPMUREFDIV_REFFRQ0 _CPMUREFDIV.Bits.REFFRQ0 +#define CPMUREFDIV_REFFRQ1 _CPMUREFDIV.Bits.REFFRQ1 +#define CPMUREFDIV_REFDIV _CPMUREFDIV.MergedBits.grpREFDIV +#define CPMUREFDIV_REFFRQ _CPMUREFDIV.MergedBits.grpREFFRQ + +#define CPMUREFDIV_REFDIV0_MASK 1U +#define CPMUREFDIV_REFDIV1_MASK 2U +#define CPMUREFDIV_REFDIV2_MASK 4U +#define CPMUREFDIV_REFDIV3_MASK 8U +#define CPMUREFDIV_REFFRQ0_MASK 64U +#define CPMUREFDIV_REFFRQ1_MASK 128U +#define CPMUREFDIV_REFDIV_MASK 15U +#define CPMUREFDIV_REFDIV_BITNUM 0U +#define CPMUREFDIV_REFFRQ_MASK 192U +#define CPMUREFDIV_REFFRQ_BITNUM 6U + + +/*** CPMUPOSTDIV - CPMU Post Divider Register; 0x000006C6 ***/ +typedef union { + byte Byte; + struct { + byte POSTDIV0 :1; /* Frequency ratio between the VCOCLK and PLLCLK control bit 0 */ + byte POSTDIV1 :1; /* Frequency ratio between the VCOCLK and PLLCLK control bit 1 */ + byte POSTDIV2 :1; /* Frequency ratio between the VCOCLK and PLLCLK control bit 2 */ + byte POSTDIV3 :1; /* Frequency ratio between the VCOCLK and PLLCLK control bit 3 */ + byte POSTDIV4 :1; /* Frequency ratio between the VCOCLK and PLLCLK control bit 4 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPOSTDIV :5; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CPMUPOSTDIVSTR; +extern volatile CPMUPOSTDIVSTR _CPMUPOSTDIV @0x000006C6; +#define CPMUPOSTDIV _CPMUPOSTDIV.Byte +#define CPMUPOSTDIV_POSTDIV0 _CPMUPOSTDIV.Bits.POSTDIV0 +#define CPMUPOSTDIV_POSTDIV1 _CPMUPOSTDIV.Bits.POSTDIV1 +#define CPMUPOSTDIV_POSTDIV2 _CPMUPOSTDIV.Bits.POSTDIV2 +#define CPMUPOSTDIV_POSTDIV3 _CPMUPOSTDIV.Bits.POSTDIV3 +#define CPMUPOSTDIV_POSTDIV4 _CPMUPOSTDIV.Bits.POSTDIV4 +#define CPMUPOSTDIV_POSTDIV _CPMUPOSTDIV.MergedBits.grpPOSTDIV + +#define CPMUPOSTDIV_POSTDIV0_MASK 1U +#define CPMUPOSTDIV_POSTDIV1_MASK 2U +#define CPMUPOSTDIV_POSTDIV2_MASK 4U +#define CPMUPOSTDIV_POSTDIV3_MASK 8U +#define CPMUPOSTDIV_POSTDIV4_MASK 16U +#define CPMUPOSTDIV_POSTDIV_MASK 31U +#define CPMUPOSTDIV_POSTDIV_BITNUM 0U + + +/*** CPMUIFLG - CPMU Interrupt Flags Register; 0x000006C7 ***/ +typedef union { + byte Byte; + struct { + byte UPOSC :1; /* Oscillator Status Bit */ + byte OSCIF :1; /* Oscillator Interrupt Flag */ + byte :1; + byte LOCK :1; /* Lock Status Bit */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte :1; + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CPMUIFLGSTR; +extern volatile CPMUIFLGSTR _CPMUIFLG @0x000006C7; +#define CPMUIFLG _CPMUIFLG.Byte +#define CPMUIFLG_UPOSC _CPMUIFLG.Bits.UPOSC +#define CPMUIFLG_OSCIF _CPMUIFLG.Bits.OSCIF +#define CPMUIFLG_LOCK _CPMUIFLG.Bits.LOCK +#define CPMUIFLG_LOCKIF _CPMUIFLG.Bits.LOCKIF +#define CPMUIFLG_RTIF _CPMUIFLG.Bits.RTIF + +#define CPMUIFLG_UPOSC_MASK 1U +#define CPMUIFLG_OSCIF_MASK 2U +#define CPMUIFLG_LOCK_MASK 8U +#define CPMUIFLG_LOCKIF_MASK 16U +#define CPMUIFLG_RTIF_MASK 128U + + +/*** CPMUINT - CPMU Interrupt Enable Register; 0x000006C8 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte OSCIE :1; /* Oscillator Corrupt Interrupt Enable Bit */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable Bit */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable Bit */ + } Bits; +} CPMUINTSTR; +extern volatile CPMUINTSTR _CPMUINT @0x000006C8; +#define CPMUINT _CPMUINT.Byte +#define CPMUINT_OSCIE _CPMUINT.Bits.OSCIE +#define CPMUINT_LOCKIE _CPMUINT.Bits.LOCKIE +#define CPMUINT_RTIE _CPMUINT.Bits.RTIE + +#define CPMUINT_OSCIE_MASK 2U +#define CPMUINT_LOCKIE_MASK 16U +#define CPMUINT_RTIE_MASK 128U + + +/*** CPMUCLKS - CPMU Clock Select Register; 0x000006C9 ***/ +typedef union { + byte Byte; + struct { + byte COPOSCSEL0 :1; /* COP Clock Select 0 */ + byte RTIOSCSEL :1; /* RTI Clock Select */ + byte PCE :1; /* COP Enable During Pseudo Stop Bit */ + byte PRE :1; /* RTI Enable During Pseudo Stop Bit */ + byte COPOSCSEL1 :1; /* COP Clock Select 1 */ + byte CSAD :1; /* COP in Stop Mode ACLK Disable */ + byte PSTP :1; /* Pseudo Stop Bit */ + byte PLLSEL :1; /* PLL Select Bit */ + } Bits; +} CPMUCLKSSTR; +extern volatile CPMUCLKSSTR _CPMUCLKS @0x000006C9; +#define CPMUCLKS _CPMUCLKS.Byte +#define CPMUCLKS_COPOSCSEL0 _CPMUCLKS.Bits.COPOSCSEL0 +#define CPMUCLKS_RTIOSCSEL _CPMUCLKS.Bits.RTIOSCSEL +#define CPMUCLKS_PCE _CPMUCLKS.Bits.PCE +#define CPMUCLKS_PRE _CPMUCLKS.Bits.PRE +#define CPMUCLKS_COPOSCSEL1 _CPMUCLKS.Bits.COPOSCSEL1 +#define CPMUCLKS_CSAD _CPMUCLKS.Bits.CSAD +#define CPMUCLKS_PSTP _CPMUCLKS.Bits.PSTP +#define CPMUCLKS_PLLSEL _CPMUCLKS.Bits.PLLSEL + +#define CPMUCLKS_COPOSCSEL0_MASK 1U +#define CPMUCLKS_RTIOSCSEL_MASK 2U +#define CPMUCLKS_PCE_MASK 4U +#define CPMUCLKS_PRE_MASK 8U +#define CPMUCLKS_COPOSCSEL1_MASK 16U +#define CPMUCLKS_CSAD_MASK 32U +#define CPMUCLKS_PSTP_MASK 64U +#define CPMUCLKS_PLLSEL_MASK 128U + + +/*** CPMUPLL - CPMU PLL Control Register; 0x000006CA ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte FM0 :1; /* PLL Frequency Modulation Enable Bit 0 */ + byte FM1 :1; /* PLL Frequency Modulation Enable Bit 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpFM :2; + byte :1; + byte :1; + } MergedBits; +} CPMUPLLSTR; +extern volatile CPMUPLLSTR _CPMUPLL @0x000006CA; +#define CPMUPLL _CPMUPLL.Byte +#define CPMUPLL_FM0 _CPMUPLL.Bits.FM0 +#define CPMUPLL_FM1 _CPMUPLL.Bits.FM1 +#define CPMUPLL_FM _CPMUPLL.MergedBits.grpFM + +#define CPMUPLL_FM0_MASK 16U +#define CPMUPLL_FM1_MASK 32U +#define CPMUPLL_FM_MASK 48U +#define CPMUPLL_FM_BITNUM 4U + + +/*** CPMURTI - CPMU RTI Control Register; 0x000006CB ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select Bit 0 */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select Bit 1 */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select Bit 2 */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select Bit 3 */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select Bit 4 */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select Bit 5 */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select Bit 6 */ + byte RTDEC :1; /* Decimal or Binary Divider Select Bit */ + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} CPMURTISTR; +extern volatile CPMURTISTR _CPMURTI @0x000006CB; +#define CPMURTI _CPMURTI.Byte +#define CPMURTI_RTR0 _CPMURTI.Bits.RTR0 +#define CPMURTI_RTR1 _CPMURTI.Bits.RTR1 +#define CPMURTI_RTR2 _CPMURTI.Bits.RTR2 +#define CPMURTI_RTR3 _CPMURTI.Bits.RTR3 +#define CPMURTI_RTR4 _CPMURTI.Bits.RTR4 +#define CPMURTI_RTR5 _CPMURTI.Bits.RTR5 +#define CPMURTI_RTR6 _CPMURTI.Bits.RTR6 +#define CPMURTI_RTDEC _CPMURTI.Bits.RTDEC +#define CPMURTI_RTR _CPMURTI.MergedBits.grpRTR + +#define CPMURTI_RTR0_MASK 1U +#define CPMURTI_RTR1_MASK 2U +#define CPMURTI_RTR2_MASK 4U +#define CPMURTI_RTR3_MASK 8U +#define CPMURTI_RTR4_MASK 16U +#define CPMURTI_RTR5_MASK 32U +#define CPMURTI_RTR6_MASK 64U +#define CPMURTI_RTDEC_MASK 128U +#define CPMURTI_RTR_MASK 127U +#define CPMURTI_RTR_BITNUM 0U + + +/*** CPMUCOP - CPMU COP Control Register; 0x000006CC ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte WRTMASK :1; /* Write Mask for WCOP */ + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CPMUCOPSTR; +extern volatile CPMUCOPSTR _CPMUCOP @0x000006CC; +#define CPMUCOP _CPMUCOP.Byte +#define CPMUCOP_CR0 _CPMUCOP.Bits.CR0 +#define CPMUCOP_CR1 _CPMUCOP.Bits.CR1 +#define CPMUCOP_CR2 _CPMUCOP.Bits.CR2 +#define CPMUCOP_WRTMASK _CPMUCOP.Bits.WRTMASK +#define CPMUCOP_RSBCK _CPMUCOP.Bits.RSBCK +#define CPMUCOP_WCOP _CPMUCOP.Bits.WCOP +#define CPMUCOP_CR _CPMUCOP.MergedBits.grpCR + +#define CPMUCOP_CR0_MASK 1U +#define CPMUCOP_CR1_MASK 2U +#define CPMUCOP_CR2_MASK 4U +#define CPMUCOP_WRTMASK_MASK 32U +#define CPMUCOP_RSBCK_MASK 64U +#define CPMUCOP_WCOP_MASK 128U +#define CPMUCOP_CR_MASK 7U +#define CPMUCOP_CR_BITNUM 0U + + +/*** CPMUARMCOP - CPMU COP Timer Arm/Reset Register; 0x000006CF ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CPMU COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CPMU COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CPMU COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CPMU COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CPMU COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CPMU COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CPMU COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CPMU COP Timer Arm/Reset Bit 7 */ + } Bits; +} CPMUARMCOPSTR; +extern volatile CPMUARMCOPSTR _CPMUARMCOP @0x000006CF; +#define CPMUARMCOP _CPMUARMCOP.Byte +#define CPMUARMCOP_BIT0 _CPMUARMCOP.Bits.BIT0 +#define CPMUARMCOP_BIT1 _CPMUARMCOP.Bits.BIT1 +#define CPMUARMCOP_BIT2 _CPMUARMCOP.Bits.BIT2 +#define CPMUARMCOP_BIT3 _CPMUARMCOP.Bits.BIT3 +#define CPMUARMCOP_BIT4 _CPMUARMCOP.Bits.BIT4 +#define CPMUARMCOP_BIT5 _CPMUARMCOP.Bits.BIT5 +#define CPMUARMCOP_BIT6 _CPMUARMCOP.Bits.BIT6 +#define CPMUARMCOP_BIT7 _CPMUARMCOP.Bits.BIT7 + +#define CPMUARMCOP_BIT0_MASK 1U +#define CPMUARMCOP_BIT1_MASK 2U +#define CPMUARMCOP_BIT2_MASK 4U +#define CPMUARMCOP_BIT3_MASK 8U +#define CPMUARMCOP_BIT4_MASK 16U +#define CPMUARMCOP_BIT5_MASK 32U +#define CPMUARMCOP_BIT6_MASK 64U +#define CPMUARMCOP_BIT7_MASK 128U + + +/*** CPMUHTCTL - High Temperature Control Register; 0x000006D0 ***/ +typedef union { + byte Byte; + struct { + byte HTIF :1; /* High Temperature Interrupt Flag */ + byte HTIE :1; /* High Temperature Interrupt Enable Bit */ + byte HTDS :1; /* High Temperature Detect Status Bi */ + byte HTE :1; /* High Temperature Sensor/Bandgap Voltage Enable Bit */ + byte :1; + byte VSEL :1; /* Voltage Access Select Bit */ + byte :1; + byte :1; + } Bits; +} CPMUHTCTLSTR; +extern volatile CPMUHTCTLSTR _CPMUHTCTL @0x000006D0; +#define CPMUHTCTL _CPMUHTCTL.Byte +#define CPMUHTCTL_HTIF _CPMUHTCTL.Bits.HTIF +#define CPMUHTCTL_HTIE _CPMUHTCTL.Bits.HTIE +#define CPMUHTCTL_HTDS _CPMUHTCTL.Bits.HTDS +#define CPMUHTCTL_HTE _CPMUHTCTL.Bits.HTE +#define CPMUHTCTL_VSEL _CPMUHTCTL.Bits.VSEL + +#define CPMUHTCTL_HTIF_MASK 1U +#define CPMUHTCTL_HTIE_MASK 2U +#define CPMUHTCTL_HTDS_MASK 4U +#define CPMUHTCTL_HTE_MASK 8U +#define CPMUHTCTL_VSEL_MASK 32U + + +/*** CPMULVCTL - Low Voltage Control Register; 0x000006D1 ***/ +typedef union { + byte Byte; + struct { + byte LVIF :1; /* Low-Voltage Interrupt Flag */ + byte LVIE :1; /* Low-Voltage Interrupt Enable Bit */ + byte LVDS :1; /* Low-Voltage Detect Status Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} CPMULVCTLSTR; +extern volatile CPMULVCTLSTR _CPMULVCTL @0x000006D1; +#define CPMULVCTL _CPMULVCTL.Byte +#define CPMULVCTL_LVIF _CPMULVCTL.Bits.LVIF +#define CPMULVCTL_LVIE _CPMULVCTL.Bits.LVIE +#define CPMULVCTL_LVDS _CPMULVCTL.Bits.LVDS + +#define CPMULVCTL_LVIF_MASK 1U +#define CPMULVCTL_LVIE_MASK 2U +#define CPMULVCTL_LVDS_MASK 4U + + +/*** CPMUAPICTL - Autonomous Periodical Interrupt Control Register; 0x000006D2 ***/ +typedef union { + byte Byte; + struct { + byte APIF :1; /* Autonomous Periodical Interrupt Flag */ + byte APIE :1; /* Autonomous Periodical Interrupt Enable Bit */ + byte APIFE :1; /* Autonomous Periodical Interrupt Feature Enable Bit */ + byte APIEA :1; /* Autonomous Periodical Interrupt External Access Enable Bit */ + byte APIES :1; /* Autonomous Periodical Interrupt External Select Bit */ + byte :1; + byte :1; + byte APICLK :1; /* Autonomous Periodical Interrupt Clock Select Bit */ + } Bits; +} CPMUAPICTLSTR; +extern volatile CPMUAPICTLSTR _CPMUAPICTL @0x000006D2; +#define CPMUAPICTL _CPMUAPICTL.Byte +#define CPMUAPICTL_APIF _CPMUAPICTL.Bits.APIF +#define CPMUAPICTL_APIE _CPMUAPICTL.Bits.APIE +#define CPMUAPICTL_APIFE _CPMUAPICTL.Bits.APIFE +#define CPMUAPICTL_APIEA _CPMUAPICTL.Bits.APIEA +#define CPMUAPICTL_APIES _CPMUAPICTL.Bits.APIES +#define CPMUAPICTL_APICLK _CPMUAPICTL.Bits.APICLK + +#define CPMUAPICTL_APIF_MASK 1U +#define CPMUAPICTL_APIE_MASK 2U +#define CPMUAPICTL_APIFE_MASK 4U +#define CPMUAPICTL_APIEA_MASK 8U +#define CPMUAPICTL_APIES_MASK 16U +#define CPMUAPICTL_APICLK_MASK 128U + + +/*** CPMUACLKTR - Autonomous Clock Trimming Register; 0x000006D3 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte ACLKTR0 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 0 */ + byte ACLKTR1 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 1 */ + byte ACLKTR2 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 2 */ + byte ACLKTR3 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 3 */ + byte ACLKTR4 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 4 */ + byte ACLKTR5 :1; /* Autonomous Periodical Interrupt Period Trimming Bit 5 */ + } Bits; + struct { + byte :1; + byte :1; + byte grpACLKTR :6; + } MergedBits; +} CPMUACLKTRSTR; +extern volatile CPMUACLKTRSTR _CPMUACLKTR @0x000006D3; +#define CPMUACLKTR _CPMUACLKTR.Byte +#define CPMUACLKTR_ACLKTR0 _CPMUACLKTR.Bits.ACLKTR0 +#define CPMUACLKTR_ACLKTR1 _CPMUACLKTR.Bits.ACLKTR1 +#define CPMUACLKTR_ACLKTR2 _CPMUACLKTR.Bits.ACLKTR2 +#define CPMUACLKTR_ACLKTR3 _CPMUACLKTR.Bits.ACLKTR3 +#define CPMUACLKTR_ACLKTR4 _CPMUACLKTR.Bits.ACLKTR4 +#define CPMUACLKTR_ACLKTR5 _CPMUACLKTR.Bits.ACLKTR5 +#define CPMUACLKTR_ACLKTR _CPMUACLKTR.MergedBits.grpACLKTR + +#define CPMUACLKTR_ACLKTR0_MASK 4U +#define CPMUACLKTR_ACLKTR1_MASK 8U +#define CPMUACLKTR_ACLKTR2_MASK 16U +#define CPMUACLKTR_ACLKTR3_MASK 32U +#define CPMUACLKTR_ACLKTR4_MASK 64U +#define CPMUACLKTR_ACLKTR5_MASK 128U +#define CPMUACLKTR_ACLKTR_MASK 252U +#define CPMUACLKTR_ACLKTR_BITNUM 2U + + +/*** CPMUAPIR - Autonomous Periodical Interrupt Rate Register; 0x000006D4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CPMUAPIRH - Autonomous Periodical Interrupt Rate Register High; 0x000006D4 ***/ + union { + byte Byte; + struct { + byte APIR8 :1; /* Autonomous Periodical Interrupt Rate Bit 8 */ + byte APIR9 :1; /* Autonomous Periodical Interrupt Rate Bit 9 */ + byte APIR10 :1; /* Autonomous Periodical Interrupt Rate Bit 10 */ + byte APIR11 :1; /* Autonomous Periodical Interrupt Rate Bit 11 */ + byte APIR12 :1; /* Autonomous Periodical Interrupt Rate Bit 12 */ + byte APIR13 :1; /* Autonomous Periodical Interrupt Rate Bit 13 */ + byte APIR14 :1; /* Autonomous Periodical Interrupt Rate Bit 14 */ + byte APIR15 :1; /* Autonomous Periodical Interrupt Rate Bit 15 */ + } Bits; + } CPMUAPIRHSTR; + #define CPMUAPIRH _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Byte + #define CPMUAPIRH_APIR8 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR8 + #define CPMUAPIRH_APIR9 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR9 + #define CPMUAPIRH_APIR10 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR10 + #define CPMUAPIRH_APIR11 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR11 + #define CPMUAPIRH_APIR12 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR12 + #define CPMUAPIRH_APIR13 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR13 + #define CPMUAPIRH_APIR14 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR14 + #define CPMUAPIRH_APIR15 _CPMUAPIR.Overlap_STR.CPMUAPIRHSTR.Bits.APIR15 + + #define CPMUAPIRH_APIR8_MASK 1U + #define CPMUAPIRH_APIR9_MASK 2U + #define CPMUAPIRH_APIR10_MASK 4U + #define CPMUAPIRH_APIR11_MASK 8U + #define CPMUAPIRH_APIR12_MASK 16U + #define CPMUAPIRH_APIR13_MASK 32U + #define CPMUAPIRH_APIR14_MASK 64U + #define CPMUAPIRH_APIR15_MASK 128U + + + /*** CPMUAPIRL - Autonomous Periodical Interrupt Rate Register Low; 0x000006D5 ***/ + union { + byte Byte; + struct { + byte APIR0 :1; /* Autonomous Periodical Interrupt Rate Bit 0 */ + byte APIR1 :1; /* Autonomous Periodical Interrupt Rate Bit 1 */ + byte APIR2 :1; /* Autonomous Periodical Interrupt Rate Bit 2 */ + byte APIR3 :1; /* Autonomous Periodical Interrupt Rate Bit 3 */ + byte APIR4 :1; /* Autonomous Periodical Interrupt Rate Bit 4 */ + byte APIR5 :1; /* Autonomous Periodical Interrupt Rate Bit 5 */ + byte APIR6 :1; /* Autonomous Periodical Interrupt Rate Bit 6 */ + byte APIR7 :1; /* Autonomous Periodical Interrupt Rate Bit 7 */ + } Bits; + } CPMUAPIRLSTR; + #define CPMUAPIRL _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Byte + #define CPMUAPIRL_APIR0 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR0 + #define CPMUAPIRL_APIR1 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR1 + #define CPMUAPIRL_APIR2 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR2 + #define CPMUAPIRL_APIR3 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR3 + #define CPMUAPIRL_APIR4 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR4 + #define CPMUAPIRL_APIR5 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR5 + #define CPMUAPIRL_APIR6 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR6 + #define CPMUAPIRL_APIR7 _CPMUAPIR.Overlap_STR.CPMUAPIRLSTR.Bits.APIR7 + + #define CPMUAPIRL_APIR0_MASK 1U + #define CPMUAPIRL_APIR1_MASK 2U + #define CPMUAPIRL_APIR2_MASK 4U + #define CPMUAPIRL_APIR3_MASK 8U + #define CPMUAPIRL_APIR4_MASK 16U + #define CPMUAPIRL_APIR5_MASK 32U + #define CPMUAPIRL_APIR6_MASK 64U + #define CPMUAPIRL_APIR7_MASK 128U + + } Overlap_STR; + + struct { + word APIR0 :1; /* Autonomous Periodical Interrupt Rate Bit 0 */ + word APIR1 :1; /* Autonomous Periodical Interrupt Rate Bit 1 */ + word APIR2 :1; /* Autonomous Periodical Interrupt Rate Bit 2 */ + word APIR3 :1; /* Autonomous Periodical Interrupt Rate Bit 3 */ + word APIR4 :1; /* Autonomous Periodical Interrupt Rate Bit 4 */ + word APIR5 :1; /* Autonomous Periodical Interrupt Rate Bit 5 */ + word APIR6 :1; /* Autonomous Periodical Interrupt Rate Bit 6 */ + word APIR7 :1; /* Autonomous Periodical Interrupt Rate Bit 7 */ + word APIR8 :1; /* Autonomous Periodical Interrupt Rate Bit 8 */ + word APIR9 :1; /* Autonomous Periodical Interrupt Rate Bit 9 */ + word APIR10 :1; /* Autonomous Periodical Interrupt Rate Bit 10 */ + word APIR11 :1; /* Autonomous Periodical Interrupt Rate Bit 11 */ + word APIR12 :1; /* Autonomous Periodical Interrupt Rate Bit 12 */ + word APIR13 :1; /* Autonomous Periodical Interrupt Rate Bit 13 */ + word APIR14 :1; /* Autonomous Periodical Interrupt Rate Bit 14 */ + word APIR15 :1; /* Autonomous Periodical Interrupt Rate Bit 15 */ + } Bits; +} CPMUAPIRSTR; +extern volatile CPMUAPIRSTR _CPMUAPIR @0x000006D4; +#define CPMUAPIR _CPMUAPIR.Word +#define CPMUAPIR_APIR0 _CPMUAPIR.Bits.APIR0 +#define CPMUAPIR_APIR1 _CPMUAPIR.Bits.APIR1 +#define CPMUAPIR_APIR2 _CPMUAPIR.Bits.APIR2 +#define CPMUAPIR_APIR3 _CPMUAPIR.Bits.APIR3 +#define CPMUAPIR_APIR4 _CPMUAPIR.Bits.APIR4 +#define CPMUAPIR_APIR5 _CPMUAPIR.Bits.APIR5 +#define CPMUAPIR_APIR6 _CPMUAPIR.Bits.APIR6 +#define CPMUAPIR_APIR7 _CPMUAPIR.Bits.APIR7 +#define CPMUAPIR_APIR8 _CPMUAPIR.Bits.APIR8 +#define CPMUAPIR_APIR9 _CPMUAPIR.Bits.APIR9 +#define CPMUAPIR_APIR10 _CPMUAPIR.Bits.APIR10 +#define CPMUAPIR_APIR11 _CPMUAPIR.Bits.APIR11 +#define CPMUAPIR_APIR12 _CPMUAPIR.Bits.APIR12 +#define CPMUAPIR_APIR13 _CPMUAPIR.Bits.APIR13 +#define CPMUAPIR_APIR14 _CPMUAPIR.Bits.APIR14 +#define CPMUAPIR_APIR15 _CPMUAPIR.Bits.APIR15 + +#define CPMUAPIR_APIR0_MASK 1U +#define CPMUAPIR_APIR1_MASK 2U +#define CPMUAPIR_APIR2_MASK 4U +#define CPMUAPIR_APIR3_MASK 8U +#define CPMUAPIR_APIR4_MASK 16U +#define CPMUAPIR_APIR5_MASK 32U +#define CPMUAPIR_APIR6_MASK 64U +#define CPMUAPIR_APIR7_MASK 128U +#define CPMUAPIR_APIR8_MASK 256U +#define CPMUAPIR_APIR9_MASK 512U +#define CPMUAPIR_APIR10_MASK 1024U +#define CPMUAPIR_APIR11_MASK 2048U +#define CPMUAPIR_APIR12_MASK 4096U +#define CPMUAPIR_APIR13_MASK 8192U +#define CPMUAPIR_APIR14_MASK 16384U +#define CPMUAPIR_APIR15_MASK 32768U + + +/*** CPMUHTTR - High Temperature Trimming Register; 0x000006D7 ***/ +typedef union { + byte Byte; + struct { + byte HTTR :4; /* High Temperature Trimming Bits */ + byte :1; + byte :1; + byte :1; + byte HTOE :1; /* High Temperature Offeset Enable Bit */ + } Bits; +} CPMUHTTRSTR; +extern volatile CPMUHTTRSTR _CPMUHTTR @0x000006D7; +#define CPMUHTTR _CPMUHTTR.Byte +#define CPMUHTTR_HTTR _CPMUHTTR.Bits.HTTR +#define CPMUHTTR_HTOE _CPMUHTTR.Bits.HTOE + +#define CPMUHTTR_HTTR_MASK 15U +#define CPMUHTTR_HTTR_BITNUM 0U +#define CPMUHTTR_HTOE_MASK 128U + + +/*** CPMUIRCTRIM - CPMU IRC1M Trim Registers; 0x000006D8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CPMUIRCTRIMH - CPMU IRC1M Trim Registers High; 0x000006D8 ***/ + union { + byte Byte; + struct { + byte IRCTRIM8 :1; /* IRC1M Frequency Trim Bit 8 */ + byte IRCTRIM9 :1; /* IRC1M Frequency Trim Bit 9 */ + byte :1; + byte TCTRIM0 :1; /* IRC1M temperature coeficient Trim Bit 0 */ + byte TCTRIM1 :1; /* IRC1M temperature coeficient Trim Bit 1 */ + byte TCTRIM2 :1; /* IRC1M temperature coeficient Trim Bit 2 */ + byte TCTRIM3 :1; /* IRC1M temperature coeficient Trim Bit 3 */ + byte TCTRIM4 :1; /* IRC1M temperature coeficient Trim Bit 4 */ + } Bits; + struct { + byte grpIRCTRIM_8 :2; + byte :1; + byte grpTCTRIM :5; + } MergedBits; + } CPMUIRCTRIMHSTR; + #define CPMUIRCTRIMH _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Byte + #define CPMUIRCTRIMH_IRCTRIM8 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.IRCTRIM8 + #define CPMUIRCTRIMH_IRCTRIM9 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.IRCTRIM9 + #define CPMUIRCTRIMH_TCTRIM0 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.TCTRIM0 + #define CPMUIRCTRIMH_TCTRIM1 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.TCTRIM1 + #define CPMUIRCTRIMH_TCTRIM2 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.TCTRIM2 + #define CPMUIRCTRIMH_TCTRIM3 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.TCTRIM3 + #define CPMUIRCTRIMH_TCTRIM4 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.Bits.TCTRIM4 + #define CPMUIRCTRIMH_IRCTRIM_8 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.MergedBits.grpIRCTRIM_8 + #define CPMUIRCTRIMH_TCTRIM _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMHSTR.MergedBits.grpTCTRIM + #define CPMUIRCTRIMH_IRCTRIM CPMUIRCTRIMH_IRCTRIM_8 + + #define CPMUIRCTRIMH_IRCTRIM8_MASK 1U + #define CPMUIRCTRIMH_IRCTRIM9_MASK 2U + #define CPMUIRCTRIMH_TCTRIM0_MASK 8U + #define CPMUIRCTRIMH_TCTRIM1_MASK 16U + #define CPMUIRCTRIMH_TCTRIM2_MASK 32U + #define CPMUIRCTRIMH_TCTRIM3_MASK 64U + #define CPMUIRCTRIMH_TCTRIM4_MASK 128U + #define CPMUIRCTRIMH_IRCTRIM_8_MASK 3U + #define CPMUIRCTRIMH_IRCTRIM_8_BITNUM 0U + #define CPMUIRCTRIMH_TCTRIM_MASK 248U + #define CPMUIRCTRIMH_TCTRIM_BITNUM 3U + + + /*** CPMUIRCTRIML - CPMU IRC1M Trim Registers Low; 0x000006D9 ***/ + union { + byte Byte; + struct { + byte IRCTRIM0 :1; /* IRC1M Frequency Trim Bit 0 */ + byte IRCTRIM1 :1; /* IRC1M Frequency Trim Bit 1 */ + byte IRCTRIM2 :1; /* IRC1M Frequency Trim Bit 2 */ + byte IRCTRIM3 :1; /* IRC1M Frequency Trim Bit 3 */ + byte IRCTRIM4 :1; /* IRC1M Frequency Trim Bit 4 */ + byte IRCTRIM5 :1; /* IRC1M Frequency Trim Bit 5 */ + byte IRCTRIM6 :1; /* IRC1M Frequency Trim Bit 6 */ + byte IRCTRIM7 :1; /* IRC1M Frequency Trim Bit 7 */ + } Bits; + } CPMUIRCTRIMLSTR; + #define CPMUIRCTRIML _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Byte + #define CPMUIRCTRIML_IRCTRIM0 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM0 + #define CPMUIRCTRIML_IRCTRIM1 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM1 + #define CPMUIRCTRIML_IRCTRIM2 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM2 + #define CPMUIRCTRIML_IRCTRIM3 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM3 + #define CPMUIRCTRIML_IRCTRIM4 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM4 + #define CPMUIRCTRIML_IRCTRIM5 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM5 + #define CPMUIRCTRIML_IRCTRIM6 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM6 + #define CPMUIRCTRIML_IRCTRIM7 _CPMUIRCTRIM.Overlap_STR.CPMUIRCTRIMLSTR.Bits.IRCTRIM7 + + #define CPMUIRCTRIML_IRCTRIM0_MASK 1U + #define CPMUIRCTRIML_IRCTRIM1_MASK 2U + #define CPMUIRCTRIML_IRCTRIM2_MASK 4U + #define CPMUIRCTRIML_IRCTRIM3_MASK 8U + #define CPMUIRCTRIML_IRCTRIM4_MASK 16U + #define CPMUIRCTRIML_IRCTRIM5_MASK 32U + #define CPMUIRCTRIML_IRCTRIM6_MASK 64U + #define CPMUIRCTRIML_IRCTRIM7_MASK 128U + + } Overlap_STR; + + struct { + word IRCTRIM0 :1; /* IRC1M Frequency Trim Bit 0 */ + word IRCTRIM1 :1; /* IRC1M Frequency Trim Bit 1 */ + word IRCTRIM2 :1; /* IRC1M Frequency Trim Bit 2 */ + word IRCTRIM3 :1; /* IRC1M Frequency Trim Bit 3 */ + word IRCTRIM4 :1; /* IRC1M Frequency Trim Bit 4 */ + word IRCTRIM5 :1; /* IRC1M Frequency Trim Bit 5 */ + word IRCTRIM6 :1; /* IRC1M Frequency Trim Bit 6 */ + word IRCTRIM7 :1; /* IRC1M Frequency Trim Bit 7 */ + word IRCTRIM8 :1; /* IRC1M Frequency Trim Bit 8 */ + word IRCTRIM9 :1; /* IRC1M Frequency Trim Bit 9 */ + word :1; + word TCTRIM0 :1; /* IRC1M temperature coeficient Trim Bit 0 */ + word TCTRIM1 :1; /* IRC1M temperature coeficient Trim Bit 1 */ + word TCTRIM2 :1; /* IRC1M temperature coeficient Trim Bit 2 */ + word TCTRIM3 :1; /* IRC1M temperature coeficient Trim Bit 3 */ + word TCTRIM4 :1; /* IRC1M temperature coeficient Trim Bit 4 */ + } Bits; + struct { + word grpIRCTRIM :10; + word :1; + word grpTCTRIM :5; + } MergedBits; +} CPMUIRCTRIMSTR; +extern volatile CPMUIRCTRIMSTR _CPMUIRCTRIM @0x000006D8; +#define CPMUIRCTRIM _CPMUIRCTRIM.Word +#define CPMUIRCTRIM_IRCTRIM0 _CPMUIRCTRIM.Bits.IRCTRIM0 +#define CPMUIRCTRIM_IRCTRIM1 _CPMUIRCTRIM.Bits.IRCTRIM1 +#define CPMUIRCTRIM_IRCTRIM2 _CPMUIRCTRIM.Bits.IRCTRIM2 +#define CPMUIRCTRIM_IRCTRIM3 _CPMUIRCTRIM.Bits.IRCTRIM3 +#define CPMUIRCTRIM_IRCTRIM4 _CPMUIRCTRIM.Bits.IRCTRIM4 +#define CPMUIRCTRIM_IRCTRIM5 _CPMUIRCTRIM.Bits.IRCTRIM5 +#define CPMUIRCTRIM_IRCTRIM6 _CPMUIRCTRIM.Bits.IRCTRIM6 +#define CPMUIRCTRIM_IRCTRIM7 _CPMUIRCTRIM.Bits.IRCTRIM7 +#define CPMUIRCTRIM_IRCTRIM8 _CPMUIRCTRIM.Bits.IRCTRIM8 +#define CPMUIRCTRIM_IRCTRIM9 _CPMUIRCTRIM.Bits.IRCTRIM9 +#define CPMUIRCTRIM_TCTRIM0 _CPMUIRCTRIM.Bits.TCTRIM0 +#define CPMUIRCTRIM_TCTRIM1 _CPMUIRCTRIM.Bits.TCTRIM1 +#define CPMUIRCTRIM_TCTRIM2 _CPMUIRCTRIM.Bits.TCTRIM2 +#define CPMUIRCTRIM_TCTRIM3 _CPMUIRCTRIM.Bits.TCTRIM3 +#define CPMUIRCTRIM_TCTRIM4 _CPMUIRCTRIM.Bits.TCTRIM4 +#define CPMUIRCTRIM_IRCTRIM _CPMUIRCTRIM.MergedBits.grpIRCTRIM +#define CPMUIRCTRIM_TCTRIM _CPMUIRCTRIM.MergedBits.grpTCTRIM + +#define CPMUIRCTRIM_IRCTRIM0_MASK 1U +#define CPMUIRCTRIM_IRCTRIM1_MASK 2U +#define CPMUIRCTRIM_IRCTRIM2_MASK 4U +#define CPMUIRCTRIM_IRCTRIM3_MASK 8U +#define CPMUIRCTRIM_IRCTRIM4_MASK 16U +#define CPMUIRCTRIM_IRCTRIM5_MASK 32U +#define CPMUIRCTRIM_IRCTRIM6_MASK 64U +#define CPMUIRCTRIM_IRCTRIM7_MASK 128U +#define CPMUIRCTRIM_IRCTRIM8_MASK 256U +#define CPMUIRCTRIM_IRCTRIM9_MASK 512U +#define CPMUIRCTRIM_TCTRIM0_MASK 2048U +#define CPMUIRCTRIM_TCTRIM1_MASK 4096U +#define CPMUIRCTRIM_TCTRIM2_MASK 8192U +#define CPMUIRCTRIM_TCTRIM3_MASK 16384U +#define CPMUIRCTRIM_TCTRIM4_MASK 32768U +#define CPMUIRCTRIM_IRCTRIM_MASK 1023U +#define CPMUIRCTRIM_IRCTRIM_BITNUM 0U +#define CPMUIRCTRIM_TCTRIM_MASK 63488U +#define CPMUIRCTRIM_TCTRIM_BITNUM 11U + + +/*** CPMUOSC - CPMU Oscillator Register; 0x000006DA ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte OSCE :1; /* Oscillator Enable Bit */ + } Bits; +} CPMUOSCSTR; +extern volatile CPMUOSCSTR _CPMUOSC @0x000006DA; +#define CPMUOSC _CPMUOSC.Byte +#define CPMUOSC_OSCE _CPMUOSC.Bits.OSCE + +#define CPMUOSC_OSCE_MASK 128U + + +/*** CPMUPROT - CPMUV1 Protection Register; 0x000006DB ***/ +typedef union { + byte Byte; + struct { + byte PROT :1; /* Clock Configuration Registers Protection Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} CPMUPROTSTR; +extern volatile CPMUPROTSTR _CPMUPROT @0x000006DB; +#define CPMUPROT _CPMUPROT.Byte +#define CPMUPROT_PROT _CPMUPROT.Bits.PROT + +#define CPMUPROT_PROT_MASK 1U + + +/*** CPMUVREGCTL - Voltage Regulator Control Register; 0x000006DD ***/ +typedef union { + byte Byte; + struct { + byte INTXON :1; /* Internal voltage regulator Enable for VDDX domain */ + byte EXTXON :1; /* External voltage regulator Enable for VDDX domain */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} CPMUVREGCTLSTR; +extern volatile CPMUVREGCTLSTR _CPMUVREGCTL @0x000006DD; +#define CPMUVREGCTL _CPMUVREGCTL.Byte +#define CPMUVREGCTL_INTXON _CPMUVREGCTL.Bits.INTXON +#define CPMUVREGCTL_EXTXON _CPMUVREGCTL.Bits.EXTXON + +#define CPMUVREGCTL_INTXON_MASK 1U +#define CPMUVREGCTL_EXTXON_MASK 2U + + +/*** CPMUOSC2 - CPMU Oscillator Register 2; 0x000006DE ***/ +typedef union { + byte Byte; + struct { + byte OSCMOD :1; /* This bit selects the mode of the external oscillator (XOSCLCP) */ + byte OMRE :1; /* This bit enables the oscillator clock monitor reset */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} CPMUOSC2STR; +extern volatile CPMUOSC2STR _CPMUOSC2 @0x000006DE; +#define CPMUOSC2 _CPMUOSC2.Byte +#define CPMUOSC2_OSCMOD _CPMUOSC2.Bits.OSCMOD +#define CPMUOSC2_OMRE _CPMUOSC2.Bits.OMRE + +#define CPMUOSC2_OSCMOD_MASK 1U +#define CPMUOSC2_OMRE_MASK 2U + + +/*** BATE - BATS Module Enable Register; 0x000006F0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BSUSE :1; /* BATS VSUP Level Sense Enable */ + byte BSUAE :1; /* BATS VSUP ADC Connection Enable */ + byte BVLS :2; /* BATS Voltage Low Select */ + byte BVHS :1; /* BATS Voltage High Select */ + byte :1; + } Bits; +} BATESTR; +extern volatile BATESTR _BATE @0x000006F0; +#define BATE _BATE.Byte +#define BATE_BSUSE _BATE.Bits.BSUSE +#define BATE_BSUAE _BATE.Bits.BSUAE +#define BATE_BVLS _BATE.Bits.BVLS +#define BATE_BVHS _BATE.Bits.BVHS + +#define BATE_BSUSE_MASK 4U +#define BATE_BSUAE_MASK 8U +#define BATE_BVLS_MASK 48U +#define BATE_BVLS_BITNUM 4U +#define BATE_BVHS_MASK 64U + + +/*** BATSR - BATS Module Status Register; 0x000006F1 ***/ +typedef union { + byte Byte; + struct { + byte BVLC :1; /* BATS Voltage Sense Low Condition Bit */ + byte BVHC :1; /* BATS Voltage Sense High Condition Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} BATSRSTR; +extern volatile BATSRSTR _BATSR @0x000006F1; +#define BATSR _BATSR.Byte +#define BATSR_BVLC _BATSR.Bits.BVLC +#define BATSR_BVHC _BATSR.Bits.BVHC + +#define BATSR_BVLC_MASK 1U +#define BATSR_BVHC_MASK 2U + + +/*** BATIE - BATS Interrupt Enable Register; 0x000006F2 ***/ +typedef union { + byte Byte; + struct { + byte BVLIE :1; /* BATS Interrupt Enable Low */ + byte BVHIE :1; /* BATS Interrupt Enable High */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} BATIESTR; +extern volatile BATIESTR _BATIE @0x000006F2; +#define BATIE _BATIE.Byte +#define BATIE_BVLIE _BATIE.Bits.BVLIE +#define BATIE_BVHIE _BATIE.Bits.BVHIE + +#define BATIE_BVLIE_MASK 1U +#define BATIE_BVHIE_MASK 2U + + +/*** BATIF - BATS Interrupt Flag Register; 0x000006F3 ***/ +typedef union { + byte Byte; + struct { + byte BVLIF :1; /* BATS Interrupt Flag Low Detect */ + byte BVHIF :1; /* BATS Interrupt Flag High Detect */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} BATIFSTR; +extern volatile BATIFSTR _BATIF @0x000006F3; +#define BATIF _BATIF.Byte +#define BATIF_BVLIF _BATIF.Bits.BVLIF +#define BATIF_BVHIF _BATIF.Bits.BVHIF + +#define BATIF_BVLIF_MASK 1U +#define BATIF_BVHIF_MASK 2U + + +/*** SCI0BD - SCI 0 Baud Rate Register; 0x00000700 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI0ASR1 - SCI 0 Alternative Status Register 1; 0x00000700 ***/ + union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI0ASR1 - SCI 0 Alternative Status Register 1; Several registers at the same address ***/ + union { + struct { + byte BKDIF :1; /* Break Detect Interrupt Flag */ + byte BERRIF :1; /* Bit Error Interrupt Flag */ + byte BERRV :1; /* Bit Error Value */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RXEDGIF :1; /* Receive Input Active Edge Interrupt Flag */ + } Bits; + } SCI0ASR1STR; + #define SCI0ASR1 _SCI0BD.Overlap_STR.SCI0ASR1STR.Byte + #define SCI0ASR1_BKDIF _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0ASR1STR.Bits.BKDIF + #define SCI0ASR1_BERRIF _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0ASR1STR.Bits.BERRIF + #define SCI0ASR1_BERRV _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0ASR1STR.Bits.BERRV + #define SCI0ASR1_RXEDGIF _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0ASR1STR.Bits.RXEDGIF + + #define SCI0ASR1_BKDIF_MASK 1U + #define SCI0ASR1_BERRIF_MASK 2U + #define SCI0ASR1_BERRV_MASK 4U + #define SCI0ASR1_RXEDGIF_MASK 128U + + /*** SCI0BDH - SCI 0 Baud Rate Register High; Several registers at the same address ***/ + union { + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte SBR13 :1; /* SCI Baud Rate Bit 13 */ + byte SBR14 :1; /* SCI Baud Rate Bit 14 */ + byte SBR15 :1; /* SCI Baud Rate Bit 15 */ + } Bits; + } SCI0BDHSTR; + #define SCI0BDH _SCI0BD.Overlap_STR.SCI0ASR1STR.Byte + #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR8 + #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR9 + #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR10 + #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR11 + #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR12 + #define SCI0BDH_SBR13 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR13 + #define SCI0BDH_SBR14 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR14 + #define SCI0BDH_SBR15 _SCI0BD.Overlap_STR.SCI0ASR1STR.SameAddr_STR.SCI0BDHSTR.Bits.SBR15 + + #define SCI0BDH_SBR8_MASK 1U + #define SCI0BDH_SBR9_MASK 2U + #define SCI0BDH_SBR10_MASK 4U + #define SCI0BDH_SBR11_MASK 8U + #define SCI0BDH_SBR12_MASK 16U + #define SCI0BDH_SBR13_MASK 32U + #define SCI0BDH_SBR14_MASK 64U + #define SCI0BDH_SBR15_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + + } SCI0ASR1STR; + + + /*** SCI0ACR1 - SCI 0 Alternative Control Register 1; 0x00000701 ***/ + union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI0ACR1 - SCI 0 Alternative Control Register 1; Several registers at the same address ***/ + union { + struct { + byte BKDIE :1; /* Break Detect Interrupt Enable */ + byte BERRIE :1; /* Bit Error Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RXEDGIE :1; /* Receive Input Active Edge Interrupt Enable */ + } Bits; + } SCI0ACR1STR; + #define SCI0ACR1 _SCI0BD.Overlap_STR.SCI0ACR1STR.Byte + #define SCI0ACR1_BKDIE _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0ACR1STR.Bits.BKDIE + #define SCI0ACR1_BERRIE _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0ACR1STR.Bits.BERRIE + #define SCI0ACR1_RXEDGIE _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0ACR1STR.Bits.RXEDGIE + + #define SCI0ACR1_BKDIE_MASK 1U + #define SCI0ACR1_BERRIE_MASK 2U + #define SCI0ACR1_RXEDGIE_MASK 128U + + /*** SCI0BDL - SCI 0 Baud Rate Register Low; Several registers at the same address ***/ + union { + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI0BDLSTR; + #define SCI0BDL _SCI0BD.Overlap_STR.SCI0ACR1STR.Byte + #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR0 + #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR1 + #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR2 + #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR3 + #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR4 + #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR5 + #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR6 + #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0ACR1STR.SameAddr_STR.SCI0BDLSTR.Bits.SBR7 + + #define SCI0BDL_SBR0_MASK 1U + #define SCI0BDL_SBR1_MASK 2U + #define SCI0BDL_SBR2_MASK 4U + #define SCI0BDL_SBR3_MASK 8U + #define SCI0BDL_SBR4_MASK 16U + #define SCI0BDL_SBR5_MASK 32U + #define SCI0BDL_SBR6_MASK 64U + #define SCI0BDL_SBR7_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + + } SCI0ACR1STR; + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word SBR13 :1; /* SCI Baud Rate Bit 13 */ + word SBR14 :1; /* SCI Baud Rate Bit 14 */ + word SBR15 :1; /* SCI Baud Rate Bit 15 */ + } Bits; +} SCI0BDSTR; +extern volatile SCI0BDSTR _SCI0BD @0x00000700; +#define SCI0BD _SCI0BD.Word +#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 +#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 +#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 +#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 +#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 +#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 +#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 +#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 +#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 +#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 +#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 +#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 +#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 +#define SCI0BD_SBR13 _SCI0BD.Bits.SBR13 +#define SCI0BD_SBR14 _SCI0BD.Bits.SBR14 +#define SCI0BD_SBR15 _SCI0BD.Bits.SBR15 + +#define SCI0BD_SBR0_MASK 1U +#define SCI0BD_SBR1_MASK 2U +#define SCI0BD_SBR2_MASK 4U +#define SCI0BD_SBR3_MASK 8U +#define SCI0BD_SBR4_MASK 16U +#define SCI0BD_SBR5_MASK 32U +#define SCI0BD_SBR6_MASK 64U +#define SCI0BD_SBR7_MASK 128U +#define SCI0BD_SBR8_MASK 256U +#define SCI0BD_SBR9_MASK 512U +#define SCI0BD_SBR10_MASK 1024U +#define SCI0BD_SBR11_MASK 2048U +#define SCI0BD_SBR12_MASK 4096U +#define SCI0BD_SBR13_MASK 8192U +#define SCI0BD_SBR14_MASK 16384U +#define SCI0BD_SBR15_MASK 32768U + + +/*** SCI0ACR2 - SCI 0 Alternative Control Register 2; 0x00000702 ***/ +typedef union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI0ACR2 - SCI 0 Alternative Control Register 2; Several registers at the same address ***/ + union { + struct { + byte BKDFE :1; /* Break Detect Feature Enable */ + byte BERRM0 :1; /* Bit Error Mode 0 */ + byte BERRM1 :1; /* Bit Error Mode 1 */ + byte :1; + byte :1; + byte TNP0 :1; /* Transmitter Narrow Pulse Bit 0 */ + byte TNP1 :1; /* Transmitter Narrow Pulse Bit 1 */ + byte IREN :1; /* Infrared Enable Bit */ + } Bits; + struct { + byte :1; + byte grpBERRM :2; + byte :1; + byte :1; + byte grpTNP :2; + byte :1; + } MergedBits; + } SCI0ACR2STR; + #define SCI0ACR2 _SCI0ACR2.Byte + #define SCI0ACR2_BKDFE _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.BKDFE + #define SCI0ACR2_BERRM0 _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.BERRM0 + #define SCI0ACR2_BERRM1 _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.BERRM1 + #define SCI0ACR2_TNP0 _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.TNP0 + #define SCI0ACR2_TNP1 _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.TNP1 + #define SCI0ACR2_IREN _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.Bits.IREN + #define SCI0ACR2_BERRM _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.MergedBits.grpBERRM + #define SCI0ACR2_TNP _SCI0ACR2.SameAddr_STR.SCI0ACR2STR.MergedBits.grpTNP + + #define SCI0ACR2_BKDFE_MASK 1U + #define SCI0ACR2_BERRM0_MASK 2U + #define SCI0ACR2_BERRM1_MASK 4U + #define SCI0ACR2_TNP0_MASK 32U + #define SCI0ACR2_TNP1_MASK 64U + #define SCI0ACR2_IREN_MASK 128U + #define SCI0ACR2_BERRM_MASK 6U + #define SCI0ACR2_BERRM_BITNUM 1U + #define SCI0ACR2_TNP_MASK 96U + #define SCI0ACR2_TNP_BITNUM 5U + + /*** SCI0CR1 - SCI 0 Control Register 1; Several registers at the same address ***/ + union { + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; + } SCI0CR1STR; + #define SCI0CR1 _SCI0ACR2.Byte + #define SCI0CR1_PT _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.PT + #define SCI0CR1_PE _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.PE + #define SCI0CR1_ILT _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.ILT + #define SCI0CR1_WAKE _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.WAKE + #define SCI0CR1_M _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.M + #define SCI0CR1_RSRC _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.RSRC + #define SCI0CR1_SCISWAI _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.SCISWAI + #define SCI0CR1_LOOPS _SCI0ACR2.SameAddr_STR.SCI0CR1STR.Bits.LOOPS + + #define SCI0CR1_PT_MASK 1U + #define SCI0CR1_PE_MASK 2U + #define SCI0CR1_ILT_MASK 4U + #define SCI0CR1_WAKE_MASK 8U + #define SCI0CR1_M_MASK 16U + #define SCI0CR1_RSRC_MASK 32U + #define SCI0CR1_SCISWAI_MASK 64U + #define SCI0CR1_LOOPS_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + +} SCI0ACR2STR; +extern volatile SCI0ACR2STR _SCI0ACR2 @0x00000702; + + +/*** SCI0CR2 - SCI 0 Control Register 2; 0x00000703 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte TIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI0CR2STR; +extern volatile SCI0CR2STR _SCI0CR2 @0x00000703; +#define SCI0CR2 _SCI0CR2.Byte +#define SCI0CR2_SBK _SCI0CR2.Bits.SBK +#define SCI0CR2_RWU _SCI0CR2.Bits.RWU +#define SCI0CR2_RE _SCI0CR2.Bits.RE +#define SCI0CR2_TE _SCI0CR2.Bits.TE +#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE +#define SCI0CR2_RIE _SCI0CR2.Bits.RIE +#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE +#define SCI0CR2_TIE _SCI0CR2.Bits.TIE + +#define SCI0CR2_SBK_MASK 1U +#define SCI0CR2_RWU_MASK 2U +#define SCI0CR2_RE_MASK 4U +#define SCI0CR2_TE_MASK 8U +#define SCI0CR2_ILIE_MASK 16U +#define SCI0CR2_RIE_MASK 32U +#define SCI0CR2_TCIE_MASK 64U +#define SCI0CR2_TIE_MASK 128U + + +/*** SCI0SR1 - SCI 0 Status Register 1; 0x00000704 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI0SR1STR; +extern volatile SCI0SR1STR _SCI0SR1 @0x00000704; +#define SCI0SR1 _SCI0SR1.Byte +#define SCI0SR1_PF _SCI0SR1.Bits.PF +#define SCI0SR1_FE _SCI0SR1.Bits.FE +#define SCI0SR1_NF _SCI0SR1.Bits.NF +#define SCI0SR1_OR _SCI0SR1.Bits.OR +#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE +#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF +#define SCI0SR1_TC _SCI0SR1.Bits.TC +#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE + +#define SCI0SR1_PF_MASK 1U +#define SCI0SR1_FE_MASK 2U +#define SCI0SR1_NF_MASK 4U +#define SCI0SR1_OR_MASK 8U +#define SCI0SR1_IDLE_MASK 16U +#define SCI0SR1_RDRF_MASK 32U +#define SCI0SR1_TC_MASK 64U +#define SCI0SR1_TDRE_MASK 128U + + +/*** SCI0SR2 - SCI 0 Status Register 2; 0x00000705 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte RXPOL :1; /* Receive Polarity */ + byte TXPOL :1; /* Transmit Polarity */ + byte :1; + byte :1; + byte AMAP :1; /* Alternative Map */ + } Bits; +} SCI0SR2STR; +extern volatile SCI0SR2STR _SCI0SR2 @0x00000705; +#define SCI0SR2 _SCI0SR2.Byte +#define SCI0SR2_RAF _SCI0SR2.Bits.RAF +#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR +#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 +#define SCI0SR2_RXPOL _SCI0SR2.Bits.RXPOL +#define SCI0SR2_TXPOL _SCI0SR2.Bits.TXPOL +#define SCI0SR2_AMAP _SCI0SR2.Bits.AMAP + +#define SCI0SR2_RAF_MASK 1U +#define SCI0SR2_TXDIR_MASK 2U +#define SCI0SR2_BRK13_MASK 4U +#define SCI0SR2_RXPOL_MASK 8U +#define SCI0SR2_TXPOL_MASK 16U +#define SCI0SR2_AMAP_MASK 128U + + +/*** SCI0DRH - SCI 0 Data Register High; 0x00000706 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI0DRHSTR; +extern volatile SCI0DRHSTR _SCI0DRH @0x00000706; +#define SCI0DRH _SCI0DRH.Byte +#define SCI0DRH_T8 _SCI0DRH.Bits.T8 +#define SCI0DRH_R8 _SCI0DRH.Bits.R8 + +#define SCI0DRH_T8_MASK 64U +#define SCI0DRH_R8_MASK 128U + + +/*** SCI0DRL - SCI 0 Data Register Low; 0x00000707 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI0DRLSTR; +extern volatile SCI0DRLSTR _SCI0DRL @0x00000707; +#define SCI0DRL _SCI0DRL.Byte +#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 +#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 +#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 +#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 +#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 +#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 +#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 +#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 + +#define SCI0DRL_R0_T0_MASK 1U +#define SCI0DRL_R1_T1_MASK 2U +#define SCI0DRL_R2_T2_MASK 4U +#define SCI0DRL_R3_T3_MASK 8U +#define SCI0DRL_R4_T4_MASK 16U +#define SCI0DRL_R5_T5_MASK 32U +#define SCI0DRL_R6_T6_MASK 64U +#define SCI0DRL_R7_T7_MASK 128U + + +/*** SCI1BD - SCI 1 Baud Rate Register; 0x00000710 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI1ASR1 - SCI 1 Alternative Status Register 1; 0x00000710 ***/ + union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI1ASR1 - SCI 1 Alternative Status Register 1; Several registers at the same address ***/ + union { + struct { + byte BKDIF :1; /* Break Detect Interrupt Flag */ + byte BERRIF :1; /* Bit Error Interrupt Flag */ + byte BERRV :1; /* Bit Error Value */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RXEDGIF :1; /* Receive Input Active Edge Interrupt Flag */ + } Bits; + } SCI1ASR1STR; + #define SCI1ASR1 _SCI1BD.Overlap_STR.SCI1ASR1STR.Byte + #define SCI1ASR1_BKDIF _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1ASR1STR.Bits.BKDIF + #define SCI1ASR1_BERRIF _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1ASR1STR.Bits.BERRIF + #define SCI1ASR1_BERRV _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1ASR1STR.Bits.BERRV + #define SCI1ASR1_RXEDGIF _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1ASR1STR.Bits.RXEDGIF + + #define SCI1ASR1_BKDIF_MASK 1U + #define SCI1ASR1_BERRIF_MASK 2U + #define SCI1ASR1_BERRV_MASK 4U + #define SCI1ASR1_RXEDGIF_MASK 128U + + /*** SCI1BDH - SCI 1 Baud Rate Register High; Several registers at the same address ***/ + union { + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte SBR13 :1; /* SCI Baud Rate Bit 13 */ + byte SBR14 :1; /* SCI Baud Rate Bit 14 */ + byte SBR15 :1; /* SCI Baud Rate Bit 15 */ + } Bits; + } SCI1BDHSTR; + #define SCI1BDH _SCI1BD.Overlap_STR.SCI1ASR1STR.Byte + #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR8 + #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR9 + #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR10 + #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR11 + #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR12 + #define SCI1BDH_SBR13 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR13 + #define SCI1BDH_SBR14 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR14 + #define SCI1BDH_SBR15 _SCI1BD.Overlap_STR.SCI1ASR1STR.SameAddr_STR.SCI1BDHSTR.Bits.SBR15 + + #define SCI1BDH_SBR8_MASK 1U + #define SCI1BDH_SBR9_MASK 2U + #define SCI1BDH_SBR10_MASK 4U + #define SCI1BDH_SBR11_MASK 8U + #define SCI1BDH_SBR12_MASK 16U + #define SCI1BDH_SBR13_MASK 32U + #define SCI1BDH_SBR14_MASK 64U + #define SCI1BDH_SBR15_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + + } SCI1ASR1STR; + + + /*** SCI1ACR1 - SCI 1 Alternative Control Register 1; 0x00000711 ***/ + union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI1ACR1 - SCI 1 Alternative Control Register 1; Several registers at the same address ***/ + union { + struct { + byte BKDIE :1; /* Break Detect Interrupt Enable */ + byte BERRIE :1; /* Bit Error Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RXEDGIE :1; /* Receive Input Active Edge Interrupt Enable */ + } Bits; + } SCI1ACR1STR; + #define SCI1ACR1 _SCI1BD.Overlap_STR.SCI1ACR1STR.Byte + #define SCI1ACR1_BKDIE _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1ACR1STR.Bits.BKDIE + #define SCI1ACR1_BERRIE _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1ACR1STR.Bits.BERRIE + #define SCI1ACR1_RXEDGIE _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1ACR1STR.Bits.RXEDGIE + + #define SCI1ACR1_BKDIE_MASK 1U + #define SCI1ACR1_BERRIE_MASK 2U + #define SCI1ACR1_RXEDGIE_MASK 128U + + /*** SCI1BDL - SCI 1 Baud Rate Register Low; Several registers at the same address ***/ + union { + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI1BDLSTR; + #define SCI1BDL _SCI1BD.Overlap_STR.SCI1ACR1STR.Byte + #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR0 + #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR1 + #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR2 + #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR3 + #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR4 + #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR5 + #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR6 + #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1ACR1STR.SameAddr_STR.SCI1BDLSTR.Bits.SBR7 + + #define SCI1BDL_SBR0_MASK 1U + #define SCI1BDL_SBR1_MASK 2U + #define SCI1BDL_SBR2_MASK 4U + #define SCI1BDL_SBR3_MASK 8U + #define SCI1BDL_SBR4_MASK 16U + #define SCI1BDL_SBR5_MASK 32U + #define SCI1BDL_SBR6_MASK 64U + #define SCI1BDL_SBR7_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + + } SCI1ACR1STR; + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word SBR13 :1; /* SCI Baud Rate Bit 13 */ + word SBR14 :1; /* SCI Baud Rate Bit 14 */ + word SBR15 :1; /* SCI Baud Rate Bit 15 */ + } Bits; +} SCI1BDSTR; +extern volatile SCI1BDSTR _SCI1BD @0x00000710; +#define SCI1BD _SCI1BD.Word +#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 +#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 +#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 +#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 +#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 +#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 +#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 +#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 +#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 +#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 +#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 +#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 +#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 +#define SCI1BD_SBR13 _SCI1BD.Bits.SBR13 +#define SCI1BD_SBR14 _SCI1BD.Bits.SBR14 +#define SCI1BD_SBR15 _SCI1BD.Bits.SBR15 + +#define SCI1BD_SBR0_MASK 1U +#define SCI1BD_SBR1_MASK 2U +#define SCI1BD_SBR2_MASK 4U +#define SCI1BD_SBR3_MASK 8U +#define SCI1BD_SBR4_MASK 16U +#define SCI1BD_SBR5_MASK 32U +#define SCI1BD_SBR6_MASK 64U +#define SCI1BD_SBR7_MASK 128U +#define SCI1BD_SBR8_MASK 256U +#define SCI1BD_SBR9_MASK 512U +#define SCI1BD_SBR10_MASK 1024U +#define SCI1BD_SBR11_MASK 2048U +#define SCI1BD_SBR12_MASK 4096U +#define SCI1BD_SBR13_MASK 8192U +#define SCI1BD_SBR14_MASK 16384U +#define SCI1BD_SBR15_MASK 32768U + + +/*** SCI1ACR2 - SCI 1 Alternative Control Register 2; 0x00000712 ***/ +typedef union { + byte Byte; + union { /* Several registers at the same address */ + /*** SCI1ACR2 - SCI 1 Alternative Control Register 2; Several registers at the same address ***/ + union { + struct { + byte BKDFE :1; /* Break Detect Feature Enable */ + byte BERRM0 :1; /* Bit Error Mode 0 */ + byte BERRM1 :1; /* Bit Error Mode 1 */ + byte :1; + byte :1; + byte TNP0 :1; /* Transmitter Narrow Pulse Bit 0 */ + byte TNP1 :1; /* Transmitter Narrow Pulse Bit 1 */ + byte IREN :1; /* Infrared Enable Bit */ + } Bits; + struct { + byte :1; + byte grpBERRM :2; + byte :1; + byte :1; + byte grpTNP :2; + byte :1; + } MergedBits; + } SCI1ACR2STR; + #define SCI1ACR2 _SCI1ACR2.Byte + #define SCI1ACR2_BKDFE _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.BKDFE + #define SCI1ACR2_BERRM0 _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.BERRM0 + #define SCI1ACR2_BERRM1 _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.BERRM1 + #define SCI1ACR2_TNP0 _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.TNP0 + #define SCI1ACR2_TNP1 _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.TNP1 + #define SCI1ACR2_IREN _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.Bits.IREN + #define SCI1ACR2_BERRM _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.MergedBits.grpBERRM + #define SCI1ACR2_TNP _SCI1ACR2.SameAddr_STR.SCI1ACR2STR.MergedBits.grpTNP + + #define SCI1ACR2_BKDFE_MASK 1U + #define SCI1ACR2_BERRM0_MASK 2U + #define SCI1ACR2_BERRM1_MASK 4U + #define SCI1ACR2_TNP0_MASK 32U + #define SCI1ACR2_TNP1_MASK 64U + #define SCI1ACR2_IREN_MASK 128U + #define SCI1ACR2_BERRM_MASK 6U + #define SCI1ACR2_BERRM_BITNUM 1U + #define SCI1ACR2_TNP_MASK 96U + #define SCI1ACR2_TNP_BITNUM 5U + + /*** SCI1CR1 - SCI 1 Control Register 1; Several registers at the same address ***/ + union { + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; + } SCI1CR1STR; + #define SCI1CR1 _SCI1ACR2.Byte + #define SCI1CR1_PT _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.PT + #define SCI1CR1_PE _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.PE + #define SCI1CR1_ILT _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.ILT + #define SCI1CR1_WAKE _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.WAKE + #define SCI1CR1_M _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.M + #define SCI1CR1_RSRC _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.RSRC + #define SCI1CR1_SCISWAI _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.SCISWAI + #define SCI1CR1_LOOPS _SCI1ACR2.SameAddr_STR.SCI1CR1STR.Bits.LOOPS + + #define SCI1CR1_PT_MASK 1U + #define SCI1CR1_PE_MASK 2U + #define SCI1CR1_ILT_MASK 4U + #define SCI1CR1_WAKE_MASK 8U + #define SCI1CR1_M_MASK 16U + #define SCI1CR1_RSRC_MASK 32U + #define SCI1CR1_SCISWAI_MASK 64U + #define SCI1CR1_LOOPS_MASK 128U + + } SameAddr_STR; /*Several registers at the same address */ + +} SCI1ACR2STR; +extern volatile SCI1ACR2STR _SCI1ACR2 @0x00000712; + + +/*** SCI1CR2 - SCI 1 Control Register 2; 0x00000713 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte TIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI1CR2STR; +extern volatile SCI1CR2STR _SCI1CR2 @0x00000713; +#define SCI1CR2 _SCI1CR2.Byte +#define SCI1CR2_SBK _SCI1CR2.Bits.SBK +#define SCI1CR2_RWU _SCI1CR2.Bits.RWU +#define SCI1CR2_RE _SCI1CR2.Bits.RE +#define SCI1CR2_TE _SCI1CR2.Bits.TE +#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE +#define SCI1CR2_RIE _SCI1CR2.Bits.RIE +#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE +#define SCI1CR2_TIE _SCI1CR2.Bits.TIE + +#define SCI1CR2_SBK_MASK 1U +#define SCI1CR2_RWU_MASK 2U +#define SCI1CR2_RE_MASK 4U +#define SCI1CR2_TE_MASK 8U +#define SCI1CR2_ILIE_MASK 16U +#define SCI1CR2_RIE_MASK 32U +#define SCI1CR2_TCIE_MASK 64U +#define SCI1CR2_TIE_MASK 128U + + +/*** SCI1SR1 - SCI 1 Status Register 1; 0x00000714 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI1SR1STR; +extern volatile SCI1SR1STR _SCI1SR1 @0x00000714; +#define SCI1SR1 _SCI1SR1.Byte +#define SCI1SR1_PF _SCI1SR1.Bits.PF +#define SCI1SR1_FE _SCI1SR1.Bits.FE +#define SCI1SR1_NF _SCI1SR1.Bits.NF +#define SCI1SR1_OR _SCI1SR1.Bits.OR +#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE +#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF +#define SCI1SR1_TC _SCI1SR1.Bits.TC +#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE + +#define SCI1SR1_PF_MASK 1U +#define SCI1SR1_FE_MASK 2U +#define SCI1SR1_NF_MASK 4U +#define SCI1SR1_OR_MASK 8U +#define SCI1SR1_IDLE_MASK 16U +#define SCI1SR1_RDRF_MASK 32U +#define SCI1SR1_TC_MASK 64U +#define SCI1SR1_TDRE_MASK 128U + + +/*** SCI1SR2 - SCI 1 Status Register 2; 0x00000715 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte RXPOL :1; /* Receive Polarity */ + byte TXPOL :1; /* Transmit Polarity */ + byte :1; + byte :1; + byte AMAP :1; /* Alternative Map */ + } Bits; +} SCI1SR2STR; +extern volatile SCI1SR2STR _SCI1SR2 @0x00000715; +#define SCI1SR2 _SCI1SR2.Byte +#define SCI1SR2_RAF _SCI1SR2.Bits.RAF +#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR +#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 +#define SCI1SR2_RXPOL _SCI1SR2.Bits.RXPOL +#define SCI1SR2_TXPOL _SCI1SR2.Bits.TXPOL +#define SCI1SR2_AMAP _SCI1SR2.Bits.AMAP + +#define SCI1SR2_RAF_MASK 1U +#define SCI1SR2_TXDIR_MASK 2U +#define SCI1SR2_BRK13_MASK 4U +#define SCI1SR2_RXPOL_MASK 8U +#define SCI1SR2_TXPOL_MASK 16U +#define SCI1SR2_AMAP_MASK 128U + + +/*** SCI1DRH - SCI 1 Data Register High; 0x00000716 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI1DRHSTR; +extern volatile SCI1DRHSTR _SCI1DRH @0x00000716; +#define SCI1DRH _SCI1DRH.Byte +#define SCI1DRH_T8 _SCI1DRH.Bits.T8 +#define SCI1DRH_R8 _SCI1DRH.Bits.R8 + +#define SCI1DRH_T8_MASK 64U +#define SCI1DRH_R8_MASK 128U + + +/*** SCI1DRL - SCI 1 Data Register Low; 0x00000717 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI1DRLSTR; +extern volatile SCI1DRLSTR _SCI1DRL @0x00000717; +#define SCI1DRL _SCI1DRL.Byte +#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 +#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 +#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 +#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 +#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 +#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 +#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 +#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 + +#define SCI1DRL_R0_T0_MASK 1U +#define SCI1DRL_R1_T1_MASK 2U +#define SCI1DRL_R2_T2_MASK 4U +#define SCI1DRL_R3_T3_MASK 8U +#define SCI1DRL_R4_T4_MASK 16U +#define SCI1DRL_R5_T5_MASK 32U +#define SCI1DRL_R6_T6_MASK 64U +#define SCI1DRL_R7_T7_MASK 128U + + +/*** SPI0CR1 - SPI 0 Control Register 1; 0x00000780 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI0CR1STR; +extern volatile SPI0CR1STR _SPI0CR1 @0x00000780; +#define SPI0CR1 _SPI0CR1.Byte +#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE +#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE +#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA +#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL +#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR +#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE +#define SPI0CR1_SPE _SPI0CR1.Bits.SPE +#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE + +#define SPI0CR1_LSBFE_MASK 1U +#define SPI0CR1_SSOE_MASK 2U +#define SPI0CR1_CPHA_MASK 4U +#define SPI0CR1_CPOL_MASK 8U +#define SPI0CR1_MSTR_MASK 16U +#define SPI0CR1_SPTIE_MASK 32U +#define SPI0CR1_SPE_MASK 64U +#define SPI0CR1_SPIE_MASK 128U + + +/*** SPI0CR2 - SPI 0 Control Register 2; 0x00000781 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte XFRW :1; /* Transfer Width */ + byte :1; + } Bits; +} SPI0CR2STR; +extern volatile SPI0CR2STR _SPI0CR2 @0x00000781; +#define SPI0CR2 _SPI0CR2.Byte +#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 +#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI +#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE +#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN +#define SPI0CR2_XFRW _SPI0CR2.Bits.XFRW + +#define SPI0CR2_SPC0_MASK 1U +#define SPI0CR2_SPISWAI_MASK 2U +#define SPI0CR2_BIDIROE_MASK 8U +#define SPI0CR2_MODFEN_MASK 16U +#define SPI0CR2_XFRW_MASK 64U + + +/*** SPI0BR - SPI 0 Baud Rate Register; 0x00000782 ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI0BRSTR; +extern volatile SPI0BRSTR _SPI0BR @0x00000782; +#define SPI0BR _SPI0BR.Byte +#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 +#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 +#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 +#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 +#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 +#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 +#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR +#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR + +#define SPI0BR_SPR0_MASK 1U +#define SPI0BR_SPR1_MASK 2U +#define SPI0BR_SPR2_MASK 4U +#define SPI0BR_SPPR0_MASK 16U +#define SPI0BR_SPPR1_MASK 32U +#define SPI0BR_SPPR2_MASK 64U +#define SPI0BR_SPR_MASK 7U +#define SPI0BR_SPR_BITNUM 0U +#define SPI0BR_SPPR_MASK 112U +#define SPI0BR_SPPR_BITNUM 4U + + +/*** SPI0SR - SPI 0 Status Register; 0x00000783 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI0SRSTR; +extern volatile SPI0SRSTR _SPI0SR @0x00000783; +#define SPI0SR _SPI0SR.Byte +#define SPI0SR_MODF _SPI0SR.Bits.MODF +#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF +#define SPI0SR_SPIF _SPI0SR.Bits.SPIF + +#define SPI0SR_MODF_MASK 16U +#define SPI0SR_SPTEF_MASK 32U +#define SPI0SR_SPIF_MASK 128U + + +/*** SPI0DR - SPI 0 Data Register; 0x00000784 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SPI0DRH - SPI 0 Data Register High; 0x00000784 ***/ + union { + byte Byte; + struct { + byte R8_T8 :1; /* SPI 0 Data Bit 8 */ + byte R9_T9 :1; /* SPI 0 Data Bit 9 */ + byte R10_T10 :1; /* SPI 0 Data Bit 10 */ + byte R11_T11 :1; /* SPI 0 Data Bit 11 */ + byte R12_T12 :1; /* SPI 0 Data Bit 12 */ + byte R13_T13 :1; /* SPI 0 Data Bit 13 */ + byte R14_T14 :1; /* SPI 0 Data Bit 14 */ + byte R15_T15 :1; /* SPI 0 Data Bit 15 */ + } Bits; + } SPI0DRHSTR; + #define SPI0DRH _SPI0DR.Overlap_STR.SPI0DRHSTR.Byte + #define SPI0DRH_R8_T8 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R8_T8 + #define SPI0DRH_R9_T9 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R9_T9 + #define SPI0DRH_R10_T10 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R10_T10 + #define SPI0DRH_R11_T11 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R11_T11 + #define SPI0DRH_R12_T12 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R12_T12 + #define SPI0DRH_R13_T13 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R13_T13 + #define SPI0DRH_R14_T14 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R14_T14 + #define SPI0DRH_R15_T15 _SPI0DR.Overlap_STR.SPI0DRHSTR.Bits.R15_T15 + + #define SPI0DRH_R8_T8_MASK 1U + #define SPI0DRH_R9_T9_MASK 2U + #define SPI0DRH_R10_T10_MASK 4U + #define SPI0DRH_R11_T11_MASK 8U + #define SPI0DRH_R12_T12_MASK 16U + #define SPI0DRH_R13_T13_MASK 32U + #define SPI0DRH_R14_T14_MASK 64U + #define SPI0DRH_R15_T15_MASK 128U + + + /*** SPI0DRL - SPI 0 Data Register Low; 0x00000785 ***/ + union { + byte Byte; + struct { + byte R0_T0 :1; /* SPI 0 Data Bit 0 */ + byte R1_T1 :1; /* SPI 0 Data Bit 1 */ + byte R2_T2 :1; /* SPI 0 Data Bit 2 */ + byte R3_T3 :1; /* SPI 0 Data Bit 3 */ + byte R4_T4 :1; /* SPI 0 Data Bit 4 */ + byte R5_T5 :1; /* SPI 0 Data Bit 5 */ + byte R6_T6 :1; /* SPI 0 Data Bit 6 */ + byte R7_T7 :1; /* SPI 0 Data Bit 7 */ + } Bits; + } SPI0DRLSTR; + #define SPI0DRL _SPI0DR.Overlap_STR.SPI0DRLSTR.Byte + #define SPI0DRL_R0_T0 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R0_T0 + #define SPI0DRL_R1_T1 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R1_T1 + #define SPI0DRL_R2_T2 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R2_T2 + #define SPI0DRL_R3_T3 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R3_T3 + #define SPI0DRL_R4_T4 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R4_T4 + #define SPI0DRL_R5_T5 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R5_T5 + #define SPI0DRL_R6_T6 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R6_T6 + #define SPI0DRL_R7_T7 _SPI0DR.Overlap_STR.SPI0DRLSTR.Bits.R7_T7 + + #define SPI0DRL_R0_T0_MASK 1U + #define SPI0DRL_R1_T1_MASK 2U + #define SPI0DRL_R2_T2_MASK 4U + #define SPI0DRL_R3_T3_MASK 8U + #define SPI0DRL_R4_T4_MASK 16U + #define SPI0DRL_R5_T5_MASK 32U + #define SPI0DRL_R6_T6_MASK 64U + #define SPI0DRL_R7_T7_MASK 128U + + } Overlap_STR; + + struct { + word R0_T0 :1; /* SPI 0 Data Bit 0 */ + word R1_T1 :1; /* SPI 0 Data Bit 1 */ + word R2_T2 :1; /* SPI 0 Data Bit 2 */ + word R3_T3 :1; /* SPI 0 Data Bit 3 */ + word R4_T4 :1; /* SPI 0 Data Bit 4 */ + word R5_T5 :1; /* SPI 0 Data Bit 5 */ + word R6_T6 :1; /* SPI 0 Data Bit 6 */ + word R7_T7 :1; /* SPI 0 Data Bit 7 */ + word R8_T8 :1; /* SPI 0 Data Bit 8 */ + word R9_T9 :1; /* SPI 0 Data Bit 9 */ + word R10_T10 :1; /* SPI 0 Data Bit 10 */ + word R11_T11 :1; /* SPI 0 Data Bit 11 */ + word R12_T12 :1; /* SPI 0 Data Bit 12 */ + word R13_T13 :1; /* SPI 0 Data Bit 13 */ + word R14_T14 :1; /* SPI 0 Data Bit 14 */ + word R15_T15 :1; /* SPI 0 Data Bit 15 */ + } Bits; +} SPI0DRSTR; +extern volatile SPI0DRSTR _SPI0DR @0x00000784; +#define SPI0DR _SPI0DR.Word +#define SPI0DR_R0_T0 _SPI0DR.Bits.R0_T0 +#define SPI0DR_R1_T1 _SPI0DR.Bits.R1_T1 +#define SPI0DR_R2_T2 _SPI0DR.Bits.R2_T2 +#define SPI0DR_R3_T3 _SPI0DR.Bits.R3_T3 +#define SPI0DR_R4_T4 _SPI0DR.Bits.R4_T4 +#define SPI0DR_R5_T5 _SPI0DR.Bits.R5_T5 +#define SPI0DR_R6_T6 _SPI0DR.Bits.R6_T6 +#define SPI0DR_R7_T7 _SPI0DR.Bits.R7_T7 +#define SPI0DR_R8_T8 _SPI0DR.Bits.R8_T8 +#define SPI0DR_R9_T9 _SPI0DR.Bits.R9_T9 +#define SPI0DR_R10_T10 _SPI0DR.Bits.R10_T10 +#define SPI0DR_R11_T11 _SPI0DR.Bits.R11_T11 +#define SPI0DR_R12_T12 _SPI0DR.Bits.R12_T12 +#define SPI0DR_R13_T13 _SPI0DR.Bits.R13_T13 +#define SPI0DR_R14_T14 _SPI0DR.Bits.R14_T14 +#define SPI0DR_R15_T15 _SPI0DR.Bits.R15_T15 + +#define SPI0DR_R0_T0_MASK 1U +#define SPI0DR_R1_T1_MASK 2U +#define SPI0DR_R2_T2_MASK 4U +#define SPI0DR_R3_T3_MASK 8U +#define SPI0DR_R4_T4_MASK 16U +#define SPI0DR_R5_T5_MASK 32U +#define SPI0DR_R6_T6_MASK 64U +#define SPI0DR_R7_T7_MASK 128U +#define SPI0DR_R8_T8_MASK 256U +#define SPI0DR_R9_T9_MASK 512U +#define SPI0DR_R10_T10_MASK 1024U +#define SPI0DR_R11_T11_MASK 2048U +#define SPI0DR_R12_T12_MASK 4096U +#define SPI0DR_R13_T13_MASK 8192U +#define SPI0DR_R14_T14_MASK 16384U +#define SPI0DR_R15_T15_MASK 32768U + + +/*** IIC0IBAD - IIC Address Register; 0x000007C0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte ADR1 :1; /* Slave Address Bit 1 */ + byte ADR2 :1; /* Slave Address Bit 2 */ + byte ADR3 :1; /* Slave Address Bit 3 */ + byte ADR4 :1; /* Slave Address Bit 4 */ + byte ADR5 :1; /* Slave Address Bit 5 */ + byte ADR6 :1; /* Slave Address Bit 6 */ + byte ADR7 :1; /* Slave Address Bit 7 */ + } Bits; + struct { + byte :1; + byte grpADR_1 :7; + } MergedBits; +} IIC0IBADSTR; +extern volatile IIC0IBADSTR _IIC0IBAD @0x000007C0; +#define IIC0IBAD _IIC0IBAD.Byte +#define IIC0IBAD_ADR1 _IIC0IBAD.Bits.ADR1 +#define IIC0IBAD_ADR2 _IIC0IBAD.Bits.ADR2 +#define IIC0IBAD_ADR3 _IIC0IBAD.Bits.ADR3 +#define IIC0IBAD_ADR4 _IIC0IBAD.Bits.ADR4 +#define IIC0IBAD_ADR5 _IIC0IBAD.Bits.ADR5 +#define IIC0IBAD_ADR6 _IIC0IBAD.Bits.ADR6 +#define IIC0IBAD_ADR7 _IIC0IBAD.Bits.ADR7 +#define IIC0IBAD_ADR_1 _IIC0IBAD.MergedBits.grpADR_1 +#define IIC0IBAD_ADR IIC0IBAD_ADR_1 + +#define IIC0IBAD_ADR1_MASK 2U +#define IIC0IBAD_ADR2_MASK 4U +#define IIC0IBAD_ADR3_MASK 8U +#define IIC0IBAD_ADR4_MASK 16U +#define IIC0IBAD_ADR5_MASK 32U +#define IIC0IBAD_ADR6_MASK 64U +#define IIC0IBAD_ADR7_MASK 128U +#define IIC0IBAD_ADR_1_MASK 254U +#define IIC0IBAD_ADR_1_BITNUM 1U + + +/*** IIC0IBFD - IIC Frequency Divider Register; 0x000007C1 ***/ +typedef union { + byte Byte; + struct { + byte IBC0 :1; /* I-Bus Clock Rate 0 */ + byte IBC1 :1; /* I-Bus Clock Rate 1 */ + byte IBC2 :1; /* I-Bus Clock Rate 2 */ + byte IBC3 :1; /* I-Bus Clock Rate 3 */ + byte IBC4 :1; /* I-Bus Clock Rate 4 */ + byte IBC5 :1; /* I-Bus Clock Rate 5 */ + byte IBC6 :1; /* I-Bus Clock Rate 6 */ + byte IBC7 :1; /* I-Bus Clock Rate 7 */ + } Bits; +} IIC0IBFDSTR; +extern volatile IIC0IBFDSTR _IIC0IBFD @0x000007C1; +#define IIC0IBFD _IIC0IBFD.Byte +#define IIC0IBFD_IBC0 _IIC0IBFD.Bits.IBC0 +#define IIC0IBFD_IBC1 _IIC0IBFD.Bits.IBC1 +#define IIC0IBFD_IBC2 _IIC0IBFD.Bits.IBC2 +#define IIC0IBFD_IBC3 _IIC0IBFD.Bits.IBC3 +#define IIC0IBFD_IBC4 _IIC0IBFD.Bits.IBC4 +#define IIC0IBFD_IBC5 _IIC0IBFD.Bits.IBC5 +#define IIC0IBFD_IBC6 _IIC0IBFD.Bits.IBC6 +#define IIC0IBFD_IBC7 _IIC0IBFD.Bits.IBC7 + +#define IIC0IBFD_IBC0_MASK 1U +#define IIC0IBFD_IBC1_MASK 2U +#define IIC0IBFD_IBC2_MASK 4U +#define IIC0IBFD_IBC3_MASK 8U +#define IIC0IBFD_IBC4_MASK 16U +#define IIC0IBFD_IBC5_MASK 32U +#define IIC0IBFD_IBC6_MASK 64U +#define IIC0IBFD_IBC7_MASK 128U + + +/*** IIC0IBCR - IIC Control Register; 0x000007C2 ***/ +typedef union { + byte Byte; + struct { + byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ + byte :1; + byte RSTA :1; /* Repeat Start */ + byte TXAK :1; /* Transmit Acknowledge enable */ + byte TX_RX :1; /* Transmit/Receive mode select bit */ + byte MS_SL :1; /* Master/Slave mode select bit */ + byte IBIE :1; /* I-Bus Interrupt Enable */ + byte IBEN :1; /* I-Bus Enable */ + } Bits; +} IIC0IBCRSTR; +extern volatile IIC0IBCRSTR _IIC0IBCR @0x000007C2; +#define IIC0IBCR _IIC0IBCR.Byte +#define IIC0IBCR_IBSWAI _IIC0IBCR.Bits.IBSWAI +#define IIC0IBCR_RSTA _IIC0IBCR.Bits.RSTA +#define IIC0IBCR_TXAK _IIC0IBCR.Bits.TXAK +#define IIC0IBCR_TX_RX _IIC0IBCR.Bits.TX_RX +#define IIC0IBCR_MS_SL _IIC0IBCR.Bits.MS_SL +#define IIC0IBCR_IBIE _IIC0IBCR.Bits.IBIE +#define IIC0IBCR_IBEN _IIC0IBCR.Bits.IBEN + +#define IIC0IBCR_IBSWAI_MASK 1U +#define IIC0IBCR_RSTA_MASK 4U +#define IIC0IBCR_TXAK_MASK 8U +#define IIC0IBCR_TX_RX_MASK 16U +#define IIC0IBCR_MS_SL_MASK 32U +#define IIC0IBCR_IBIE_MASK 64U +#define IIC0IBCR_IBEN_MASK 128U + + +/*** IIC0IBSR - IIC Status Register; 0x000007C3 ***/ +typedef union { + byte Byte; + struct { + byte RXAK :1; /* Received Acknowledge */ + byte IBIF :1; /* I-Bus Interrupt */ + byte SRW :1; /* Slave Read/Write */ + byte :1; + byte IBAL :1; /* Arbitration Lost */ + byte IBB :1; /* Bus busy bit */ + byte IAAS :1; /* Addressed as a slave bit */ + byte TCF :1; /* Data transferring bit */ + } Bits; +} IIC0IBSRSTR; +extern volatile IIC0IBSRSTR _IIC0IBSR @0x000007C3; +#define IIC0IBSR _IIC0IBSR.Byte +#define IIC0IBSR_RXAK _IIC0IBSR.Bits.RXAK +#define IIC0IBSR_IBIF _IIC0IBSR.Bits.IBIF +#define IIC0IBSR_SRW _IIC0IBSR.Bits.SRW +#define IIC0IBSR_IBAL _IIC0IBSR.Bits.IBAL +#define IIC0IBSR_IBB _IIC0IBSR.Bits.IBB +#define IIC0IBSR_IAAS _IIC0IBSR.Bits.IAAS +#define IIC0IBSR_TCF _IIC0IBSR.Bits.TCF + +#define IIC0IBSR_RXAK_MASK 1U +#define IIC0IBSR_IBIF_MASK 2U +#define IIC0IBSR_SRW_MASK 4U +#define IIC0IBSR_IBAL_MASK 16U +#define IIC0IBSR_IBB_MASK 32U +#define IIC0IBSR_IAAS_MASK 64U +#define IIC0IBSR_TCF_MASK 128U + + +/*** IIC0IBDR - IIC Data I/O Register; 0x000007C4 ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* IIC Data Bit 0 */ + byte D1 :1; /* IIC Data Bit 1 */ + byte D2 :1; /* IIC Data Bit 2 */ + byte D3 :1; /* IIC Data Bit 3 */ + byte D4 :1; /* IIC Data Bit 4 */ + byte D5 :1; /* IIC Data Bit 5 */ + byte D6 :1; /* IIC Data Bit 6 */ + byte D7 :1; /* IIC Data Bit 7 */ + } Bits; +} IIC0IBDRSTR; +extern volatile IIC0IBDRSTR _IIC0IBDR @0x000007C4; +#define IIC0IBDR _IIC0IBDR.Byte +#define IIC0IBDR_D0 _IIC0IBDR.Bits.D0 +#define IIC0IBDR_D1 _IIC0IBDR.Bits.D1 +#define IIC0IBDR_D2 _IIC0IBDR.Bits.D2 +#define IIC0IBDR_D3 _IIC0IBDR.Bits.D3 +#define IIC0IBDR_D4 _IIC0IBDR.Bits.D4 +#define IIC0IBDR_D5 _IIC0IBDR.Bits.D5 +#define IIC0IBDR_D6 _IIC0IBDR.Bits.D6 +#define IIC0IBDR_D7 _IIC0IBDR.Bits.D7 + +#define IIC0IBDR_D0_MASK 1U +#define IIC0IBDR_D1_MASK 2U +#define IIC0IBDR_D2_MASK 4U +#define IIC0IBDR_D3_MASK 8U +#define IIC0IBDR_D4_MASK 16U +#define IIC0IBDR_D5_MASK 32U +#define IIC0IBDR_D6_MASK 64U +#define IIC0IBDR_D7_MASK 128U + + +/*** IIC0IBCR2 - IIC Control Register 2; 0x000007C5 ***/ +typedef union { + byte Byte; + struct { + byte ADR8 :1; /* Slave Address Bit 8 */ + byte ADR9 :1; /* Slave Address Bit 9 */ + byte ADR10 :1; /* Slave Address Bit 10 */ + byte :1; + byte :1; + byte :1; + byte ADTYPE :1; /* Address Type */ + byte GCEN :1; /* General Call Enable */ + } Bits; + struct { + byte grpADR_8 :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} IIC0IBCR2STR; +extern volatile IIC0IBCR2STR _IIC0IBCR2 @0x000007C5; +#define IIC0IBCR2 _IIC0IBCR2.Byte +#define IIC0IBCR2_ADR8 _IIC0IBCR2.Bits.ADR8 +#define IIC0IBCR2_ADR9 _IIC0IBCR2.Bits.ADR9 +#define IIC0IBCR2_ADR10 _IIC0IBCR2.Bits.ADR10 +#define IIC0IBCR2_ADTYPE _IIC0IBCR2.Bits.ADTYPE +#define IIC0IBCR2_GCEN _IIC0IBCR2.Bits.GCEN +#define IIC0IBCR2_ADR_8 _IIC0IBCR2.MergedBits.grpADR_8 +#define IIC0IBCR2_ADR IIC0IBCR2_ADR_8 + +#define IIC0IBCR2_ADR8_MASK 1U +#define IIC0IBCR2_ADR9_MASK 2U +#define IIC0IBCR2_ADR10_MASK 4U +#define IIC0IBCR2_ADTYPE_MASK 64U +#define IIC0IBCR2_GCEN_MASK 128U +#define IIC0IBCR2_ADR_8_MASK 7U +#define IIC0IBCR2_ADR_8_BITNUM 0U + + +/*** LP0DR - Port LP Data Register; 0x00000980 ***/ +typedef union { + byte Byte; + struct { + byte LPDR0 :1; /* LIN Rx data */ + byte LPDR1 :1; /* LIN Tx data */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpLPDR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} LP0DRSTR; +extern volatile LP0DRSTR _LP0DR @0x00000980; +#define LP0DR _LP0DR.Byte +#define LP0DR_LPDR0 _LP0DR.Bits.LPDR0 +#define LP0DR_LPDR1 _LP0DR.Bits.LPDR1 +#define LP0DR_LPDR _LP0DR.MergedBits.grpLPDR + +#define LP0DR_LPDR0_MASK 1U +#define LP0DR_LPDR1_MASK 2U +#define LP0DR_LPDR_MASK 3U +#define LP0DR_LPDR_BITNUM 0U + + +/*** LP0CR - LIN Control Register; 0x00000981 ***/ +typedef union { + byte Byte; + struct { + byte LPPUE :1; /* LIN pull-up enable */ + byte LPWUE :1; /* LIN wake-up enable */ + byte RXONLY :1; /* Receive only mode */ + byte LPE :1; /* LIN enable */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} LP0CRSTR; +extern volatile LP0CRSTR _LP0CR @0x00000981; +#define LP0CR _LP0CR.Byte +#define LP0CR_LPPUE _LP0CR.Bits.LPPUE +#define LP0CR_LPWUE _LP0CR.Bits.LPWUE +#define LP0CR_RXONLY _LP0CR.Bits.RXONLY +#define LP0CR_LPE _LP0CR.Bits.LPE + +#define LP0CR_LPPUE_MASK 1U +#define LP0CR_LPWUE_MASK 2U +#define LP0CR_RXONLY_MASK 4U +#define LP0CR_LPE_MASK 8U + + +/*** LP0SLRM - LIN Slew Rate Register; 0x00000983 ***/ +typedef union { + byte Byte; + struct { + byte LPSLR :2; /* Slew rate select */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte LPDTDIS :1; /* TxD-dominant timeout disable */ + } Bits; +} LP0SLRMSTR; +extern volatile LP0SLRMSTR _LP0SLRM @0x00000983; +#define LP0SLRM _LP0SLRM.Byte +#define LP0SLRM_LPSLR _LP0SLRM.Bits.LPSLR +#define LP0SLRM_LPDTDIS _LP0SLRM.Bits.LPDTDIS + +#define LP0SLRM_LPSLR_MASK 3U +#define LP0SLRM_LPSLR_BITNUM 0U +#define LP0SLRM_LPDTDIS_MASK 128U + + +/*** LP0SR - LIN Status Register; 0x00000985 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte LPDT :1; /* LIN Transmitter TxD-dominant timeout Status */ + } Bits; +} LP0SRSTR; +extern volatile LP0SRSTR _LP0SR @0x00000985; +#define LP0SR _LP0SR.Byte +#define LP0SR_LPDT _LP0SR.Bits.LPDT + +#define LP0SR_LPDT_MASK 128U + + +/*** LP0IE - LIN Interrupt Enable Register; 0x00000986 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte LPOCIE :1; /* LIN over-current interrupt enable */ + byte LPDTIE :1; /* LIN TxD-dominant timeout Interrupt Enable */ + } Bits; +} LP0IESTR; +extern volatile LP0IESTR _LP0IE @0x00000986; +#define LP0IE _LP0IE.Byte +#define LP0IE_LPOCIE _LP0IE.Bits.LPOCIE +#define LP0IE_LPDTIE _LP0IE.Bits.LPDTIE + +#define LP0IE_LPOCIE_MASK 64U +#define LP0IE_LPDTIE_MASK 128U + + +/*** LP0IF - LIN Interrupt Flags Register; 0x00000987 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte LPOCIF :1; /* LIN transmitter over-current interrupt flag */ + byte LPDTIF :1; /* LIN Transmitter TxD-dominant timeout Interrupt Flag */ + } Bits; +} LP0IFSTR; +extern volatile LP0IFSTR _LP0IF @0x00000987; +#define LP0IF _LP0IF.Byte +#define LP0IF_LPOCIF _LP0IF.Bits.LPOCIF +#define LP0IF_LPDTIF _LP0IF.Bits.LPDTIF + +#define LP0IF_LPOCIF_MASK 64U +#define LP0IF_LPDTIF_MASK 128U + + +/*** BAKEY0 - Backdoor Comparison Key 0; 0x00FFFE00 ***/ +typedef union { + word Word; + struct { + word KEY :16; /* Backdoor Comparison Key Bits */ + } Bits; +} BAKEY0STR; +/* Tip for register initialization in the user code: const word BAKEY0_INIT @0x00FFFE00 = ; */ +#define _BAKEY0 (*(const BAKEY0STR *)0x00FFFE00) +#define BAKEY0 _BAKEY0.Word +#define BAKEY0_KEY _BAKEY0.Bits.KEY +/* BAKEY_ARR: Access 4 BAKEYx registers in an array */ +#define BAKEY_ARR ((volatile word *) &BAKEY0) + +#define BAKEY0_KEY_MASK 65535U +#define BAKEY0_KEY_BITNUM 0U + + +/*** BAKEY1 - Backdoor Comparison Key 1; 0x00FFFE02 ***/ +typedef union { + word Word; + struct { + word KEY :16; /* Backdoor Comparison Key Bits */ + } Bits; +} BAKEY1STR; +/* Tip for register initialization in the user code: const word BAKEY1_INIT @0x00FFFE02 = ; */ +#define _BAKEY1 (*(const BAKEY1STR *)0x00FFFE02) +#define BAKEY1 _BAKEY1.Word +#define BAKEY1_KEY _BAKEY1.Bits.KEY + +#define BAKEY1_KEY_MASK 65535U +#define BAKEY1_KEY_BITNUM 0U + + +/*** BAKEY2 - Backdoor Comparison Key 2; 0x00FFFE04 ***/ +typedef union { + word Word; + struct { + word KEY :16; /* Backdoor Comparison Key Bits */ + } Bits; +} BAKEY2STR; +/* Tip for register initialization in the user code: const word BAKEY2_INIT @0x00FFFE04 = ; */ +#define _BAKEY2 (*(const BAKEY2STR *)0x00FFFE04) +#define BAKEY2 _BAKEY2.Word +#define BAKEY2_KEY _BAKEY2.Bits.KEY + +#define BAKEY2_KEY_MASK 65535U +#define BAKEY2_KEY_BITNUM 0U + + +/*** BAKEY3 - Backdoor Comparison Key 3; 0x00FFFE06 ***/ +typedef union { + word Word; + struct { + word KEY :16; /* Backdoor Comparison Key Bits */ + } Bits; +} BAKEY3STR; +/* Tip for register initialization in the user code: const word BAKEY3_INIT @0x00FFFE06 = ; */ +#define _BAKEY3 (*(const BAKEY3STR *)0x00FFFE06) +#define BAKEY3 _BAKEY3.Word +#define BAKEY3_KEY _BAKEY3.Bits.KEY + +#define BAKEY3_KEY_MASK 65535U +#define BAKEY3_KEY_BITNUM 0U + + +/*** PROTKEY - Non Volatile Protection Override Comparison Key; 0x00FFFE08 ***/ +typedef union { + word Word; + struct { + word KEY :16; /* Protection Override Comparison Key Bits */ + } Bits; +} PROTKEYSTR; +/* Tip for register initialization in the user code: const word PROTKEY_INIT @0x00FFFE08 = ; */ +#define _PROTKEY (*(const PROTKEYSTR *)0x00FFFE08) +#define PROTKEY _PROTKEY.Word +#define PROTKEY_KEY _PROTKEY.Bits.KEY + +#define PROTKEY_KEY_MASK 65535U +#define PROTKEY_KEY_BITNUM 0U + + +/*** NVFPROT - Non Volatile P-Flash Protection Register; 0x00FFFE0C ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address Size Bit 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address Size Bit 1 */ + byte FPLDIS :1; /* Flash Protection Lower Address Range Disable */ + byte FPHS0 :1; /* Flash Protection Higher Address Size Bit 0 */ + byte FPHS1 :1; /* Flash Protection Higher Address Size Bit 1 */ + byte FPHDIS :1; /* Flash Protection Higher Address Range Disable */ + byte RNV6 :1; /* Reserved Nonvolatile Bit */ + byte FPOPEN :1; /* Flash Protection Operation Enable */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpRNV_6 :1; + byte :1; + } MergedBits; +} NVFPROTSTR; +/* Tip for register initialization in the user code: const byte NVFPROT_INIT @0x00FFFE0C = ; */ +#define _NVFPROT (*(const NVFPROTSTR *)0x00FFFE0C) +#define NVFPROT _NVFPROT.Byte +#define NVFPROT_FPLS0 _NVFPROT.Bits.FPLS0 +#define NVFPROT_FPLS1 _NVFPROT.Bits.FPLS1 +#define NVFPROT_FPLDIS _NVFPROT.Bits.FPLDIS +#define NVFPROT_FPHS0 _NVFPROT.Bits.FPHS0 +#define NVFPROT_FPHS1 _NVFPROT.Bits.FPHS1 +#define NVFPROT_FPHDIS _NVFPROT.Bits.FPHDIS +#define NVFPROT_RNV6 _NVFPROT.Bits.RNV6 +#define NVFPROT_FPOPEN _NVFPROT.Bits.FPOPEN +#define NVFPROT_FPLS _NVFPROT.MergedBits.grpFPLS +#define NVFPROT_FPHS _NVFPROT.MergedBits.grpFPHS + +#define NVFPROT_FPLS0_MASK 1U +#define NVFPROT_FPLS1_MASK 2U +#define NVFPROT_FPLDIS_MASK 4U +#define NVFPROT_FPHS0_MASK 8U +#define NVFPROT_FPHS1_MASK 16U +#define NVFPROT_FPHDIS_MASK 32U +#define NVFPROT_RNV6_MASK 64U +#define NVFPROT_FPOPEN_MASK 128U +#define NVFPROT_FPLS_MASK 3U +#define NVFPROT_FPLS_BITNUM 0U +#define NVFPROT_FPHS_MASK 24U +#define NVFPROT_FPHS_BITNUM 3U + + +/*** NVDFPROT - Non Volatile D-Flash Protection Register; 0x00FFFE0D ***/ +typedef union { + byte Byte; + struct { + byte DPS0 :1; /* D-Flash Protection Size Bit 0 */ + byte DPS1 :1; /* D-Flash Protection Size Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte DPOPEN :1; /* D-Flash Protection Control */ + } Bits; + struct { + byte grpDPS :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} NVDFPROTSTR; +/* Tip for register initialization in the user code: const byte NVDFPROT_INIT @0x00FFFE0D = ; */ +#define _NVDFPROT (*(const NVDFPROTSTR *)0x00FFFE0D) +#define NVDFPROT _NVDFPROT.Byte +#define NVDFPROT_DPS0 _NVDFPROT.Bits.DPS0 +#define NVDFPROT_DPS1 _NVDFPROT.Bits.DPS1 +#define NVDFPROT_DPOPEN _NVDFPROT.Bits.DPOPEN +#define NVDFPROT_DPS _NVDFPROT.MergedBits.grpDPS + +#define NVDFPROT_DPS0_MASK 1U +#define NVDFPROT_DPS1_MASK 2U +#define NVDFPROT_DPOPEN_MASK 128U +#define NVDFPROT_DPS_MASK 3U +#define NVDFPROT_DPS_BITNUM 0U + + +/*** NVFOPT - Non Volatile Flash Option Register; 0x00FFFE0E ***/ +typedef union { + byte Byte; + struct { + byte NV0 :1; /* Nonvolatile Bit 0 */ + byte NV1 :1; /* Nonvolatile Bit 1 */ + byte NV2 :1; /* Nonvolatile Bit 2 */ + byte NV3 :1; /* Nonvolatile Bit 3 */ + byte NV4 :1; /* Nonvolatile Bit 4 */ + byte NV5 :1; /* Nonvolatile Bit 5 */ + byte NV6 :1; /* Nonvolatile Bit 6 */ + byte NV7 :1; /* Nonvolatile Bit 7 */ + } Bits; +} NVFOPTSTR; +/* Tip for register initialization in the user code: const byte NVFOPT_INIT @0x00FFFE0E = ; */ +#define _NVFOPT (*(const NVFOPTSTR *)0x00FFFE0E) +#define NVFOPT _NVFOPT.Byte +#define NVFOPT_NV0 _NVFOPT.Bits.NV0 +#define NVFOPT_NV1 _NVFOPT.Bits.NV1 +#define NVFOPT_NV2 _NVFOPT.Bits.NV2 +#define NVFOPT_NV3 _NVFOPT.Bits.NV3 +#define NVFOPT_NV4 _NVFOPT.Bits.NV4 +#define NVFOPT_NV5 _NVFOPT.Bits.NV5 +#define NVFOPT_NV6 _NVFOPT.Bits.NV6 +#define NVFOPT_NV7 _NVFOPT.Bits.NV7 + +#define NVFOPT_NV0_MASK 1U +#define NVFOPT_NV1_MASK 2U +#define NVFOPT_NV2_MASK 4U +#define NVFOPT_NV3_MASK 8U +#define NVFOPT_NV4_MASK 16U +#define NVFOPT_NV5_MASK 32U +#define NVFOPT_NV6_MASK 64U +#define NVFOPT_NV7_MASK 128U + + +/*** NVFSEC - Non Volatile Flash Security Register; 0x00FFFE0F ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Flash Security Bit 0 */ + byte SEC1 :1; /* Flash Security Bit 1 */ + byte RNV2 :1; /* Reserved Nonvolatile Bit 2 */ + byte RNV3 :1; /* Reserved Nonvolatile Bit 3 */ + byte RNV4 :1; /* Reserved Nonvolatile Bit 4 */ + byte RNV5 :1; /* Reserved Nonvolatile Bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpRNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} NVFSECSTR; +/* Tip for register initialization in the user code: const byte NVFSEC_INIT @0x00FFFE0F = ; */ +#define _NVFSEC (*(const NVFSECSTR *)0x00FFFE0F) +#define NVFSEC _NVFSEC.Byte +#define NVFSEC_SEC0 _NVFSEC.Bits.SEC0 +#define NVFSEC_SEC1 _NVFSEC.Bits.SEC1 +#define NVFSEC_RNV2 _NVFSEC.Bits.RNV2 +#define NVFSEC_RNV3 _NVFSEC.Bits.RNV3 +#define NVFSEC_RNV4 _NVFSEC.Bits.RNV4 +#define NVFSEC_RNV5 _NVFSEC.Bits.RNV5 +#define NVFSEC_KEYEN0 _NVFSEC.Bits.KEYEN0 +#define NVFSEC_KEYEN1 _NVFSEC.Bits.KEYEN1 +#define NVFSEC_SEC _NVFSEC.MergedBits.grpSEC +#define NVFSEC_RNV_2 _NVFSEC.MergedBits.grpRNV_2 +#define NVFSEC_KEYEN _NVFSEC.MergedBits.grpKEYEN +#define NVFSEC_RNV NVFSEC_RNV_2 + +#define NVFSEC_SEC0_MASK 1U +#define NVFSEC_SEC1_MASK 2U +#define NVFSEC_RNV2_MASK 4U +#define NVFSEC_RNV3_MASK 8U +#define NVFSEC_RNV4_MASK 16U +#define NVFSEC_RNV5_MASK 32U +#define NVFSEC_KEYEN0_MASK 64U +#define NVFSEC_KEYEN1_MASK 128U +#define NVFSEC_SEC_MASK 3U +#define NVFSEC_SEC_BITNUM 0U +#define NVFSEC_RNV_2_MASK 60U +#define NVFSEC_RNV_2_BITNUM 2U +#define NVFSEC_KEYEN_MASK 192U +#define NVFSEC_KEYEN_BITNUM 6U + + +/* * * * * 24-BIT ADDRESS REGISTERS * * * * * * * * * * * * * * * * * * * * * * */ +extern volatile void* volatile MMCPC @0x00000085; /* Captured S12ZCPU Program Counter Low; 0x00000087 */ +extern volatile void* volatile DBGAA @0x00000115; /* Debug Comparator A Address Register Low; 0x00000117 */ +extern volatile void* volatile DBGBA @0x00000125; /* Debug Comparator B Address Register Low; 0x00000127 */ +extern volatile void* volatile DBGDA @0x00000145; /* Debug Comparator D Address Register Low; 0x00000147 */ +extern volatile void* volatile ECCDPTR @0x000003C7; /* ECC Debug Point Register Low; 0x000003C9 */ +extern volatile void* volatile ADC0CBP @0x0000061D; /* ADC0 Command Base Pointer Register 0; 0x000003C9 */ +extern volatile void* volatile ADC0RBP @0x00000621; /* ADC0 Result Base Pointer Register 0; 0x000003C9 */ + + + /* Watchdog reset macro */ +#ifndef __RESET_WATCHDOG +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() (CPMUARMCOP = 0x55U, CPMUARMCOP = 0xAAU) +#endif +#endif /* __RESET_WATCHDOG */ + + +/***********************************************/ +/** D E P R E C I A T E D S Y M B O L S **/ +/***********************************************/ +/* --------------------------------------------------------------------------- */ +/* The following symbols were removed, because they were invalid or irrelevant */ +/* --------------------------------------------------------------------------- */ + +/* **** 07/02/2013 */ + +#define LPSLRSTR This_symb_has_been_depreciated +#define LPSLR_LPSLR This_symb_has_been_depreciated +#define LPSLR_LPSLRWD This_symb_has_been_depreciated +#define LPSLR_LPSLR_MASK This_symb_has_been_depreciated +#define LPSLR_LPSLR_BITNUM This_symb_has_been_depreciated +#define LPSLR_LPSLRWD_MASK This_symb_has_been_depreciated +#define LPSR_LPOC This_symb_has_been_depreciated +#define LPSR_LPOC_MASK This_symb_has_been_depreciated +/*lint -restore +esym(960,18.4) +esym(961,19.7) Enable MISRA rule (1.1,18.4,6.4,19.7) checking. */ +#endif diff --git a/Project_Settings/Linker_Files/mc9s12zvl32.prm b/Project_Settings/Linker_Files/mc9s12zvl32.prm new file mode 100644 index 0000000..af35aa2 --- /dev/null +++ b/Project_Settings/Linker_Files/mc9s12zvl32.prm @@ -0,0 +1,51 @@ +/* This is a linker parameter file for the MC9S12ZVL32 */ +NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */ + +SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */ + +/* Register space */ +/* IO_SEG = PAGED 0x000000 TO 0x000FFF; intentionally not defined */ + +/* RAM */ + RAM = READ_WRITE 0x001000 TO 0x0013FF; + +/* EEPROM */ + EEPROM = READ_ONLY 0x100000 TO 0x10007F; + +/* non-paged FLASHs */ + ROM = READ_ONLY 0xFF8000 TO 0xFFFDFF; + /* VECTORS = READ_ONLY 0xFFFE00 TO 0xFFFFFF; intentionally not defined: used for VECTOR commands below */ + //OSVECTORS = READ_ONLY 0xFFFE10 TO 0xFFFFFF; /* OSEK interrupt vectors (use your vector.o) */ +END + +PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */ + _PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */ + STARTUP, /* startup data structures */ + ROM_VAR, /* constant variables */ + STRINGS, /* string literals */ + VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */ + //.ostext, /* OSEK */ + NON_BANKED, /* runtime routines which must not be banked */ + DEFAULT_ROM, + COPY INTO ROM; + + //.stackstart, /* eventually used for OSEK kernel awareness: Main-Stack Start */ + SSTACK, /* allocate stack first to avoid overwriting variables on overflow */ + //.stackend, /* eventually used for OSEK kernel awareness: Main-Stack End */ + DEFAULT_RAM INTO RAM; + + + //.vectors INTO OSVECTORS; /* OSEK */ +END + +ENTRIES /* keep the following unreferenced variables */ + /* OSEK: always allocate the vector table and all dependent objects */ + //_vectab OsBuildNumber _OsOrtiStackStart _OsOrtiStart +END + +STACKSIZE 0x100 + +VECTOR 0 _Startup /* reset vector: this is the default entry point for a C/C++ application. */ +//VECTOR 0 Entry /* reset vector: this is the default entry point for an Assembly application. */ +//INIT Entry /* for assembly applications: that this is as well the initialization entry point */ + diff --git a/Project_Settings/Startup_Code/starts12z.c b/Project_Settings/Startup_Code/starts12z.c new file mode 100644 index 0000000..f21835e --- /dev/null +++ b/Project_Settings/Startup_Code/starts12z.c @@ -0,0 +1,102 @@ +/***************************************************** + starts12z.c - startup code for S12Z (S12/L-ISA) + ---------------------------------------------------- + Copyright (c) Freescale Semiconductor + All rights reserved + + *****************************************************/ + + + +#include "starts12z.h" + +#ifdef __cplusplus +#define __EXTERN_C extern "C" +#else +#define __EXTERN_C +#endif + +#if __ASM_DATA_ADDR_OPT__ +const +#endif +struct _tagStartup _startupData +#if __ASM_DATA_ADDR_OPT__ +#ifdef __cplusplus += {} +#endif +#endif +; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ + +void main(void); /* prototype of main function */ + +static void DoZeroOut(void) { + __asm { + LD D6, _startupData.nofZeroOuts + BEQ end /* nothing to do */ + LD X, _startupData.pZeroOut + zeroOutLoop: + LD Y, (0,X) /* X points to the first range */ + LD D7, (3,X) /* D7 holds size */ + doZeroOut: + CLR.b (Y+) + DBNE D7, doZeroOut + LEA X, (7,X) + DBNE D6, zeroOutLoop + end: + } +} + +static void DoCopyDown(void) { + __asm { + LD Y, _startupData.toCopyDownBeg + BEQ end /* the pointer is NULL */ + nextItemLoop: + LD D6, (Y+) /* load the size */ + BEQ end + LD X, (Y+) /* load the destination */ + copyLoop: + MOV.b (Y+), (X+) /* copy the data */ + DBNE D6, copyLoop + BRA nextItemLoop + end: + } +} + +#ifdef __cplusplus +static void __static_init(void) { + __asm { + LD D5, _startupData.nofInitBodies + BEQ end + LD X, _startupData.initBodies + initNextBody: + LD Y,(X+) + PSH ALL + JSR (Y+) + PUL ALL + DBNE D5, initNextBody + end: + } + +} +#endif + +extern int __SEG_END_SSTACK[]; + +__EXTERN_C void _Startup(void) { + __asm { + LD S, #__SEG_END_SSTACK-1 /* initialize SP */ +#ifdef __ALIGN_STACK_OPT__ + TFR S, D6 /* align SP to 4*/ + AND D6, #-4 + TFR D6, S +#endif + } + DoZeroOut(); + DoCopyDown(); +#ifdef __cplusplus + __static_init(); +#endif + main(); +} diff --git a/ReferencedRSESystems.xml b/ReferencedRSESystems.xml new file mode 100644 index 0000000..a5e2736 --- /dev/null +++ b/ReferencedRSESystems.xml @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Sources/AD1.c b/Sources/AD1.c new file mode 100644 index 0000000..e467b42 --- /dev/null +++ b/Sources/AD1.c @@ -0,0 +1,203 @@ +#include "AD1.h" + +#define IDLE 0x00U /* IDLE state */ +#define SINGLE 0x01U /* SINGLE state */ +#define MEASURE 0x02U /* MESURE state */ +#define CONTINUOUS 0x04U /* CONTINUOUS state */ + +#define CMD_EOL 0xC0000000U /* Command End of list used as the last command in CSL */ +#define CMD_EOL_CONTINUOUS 0x80000000U /* Command End of list with continuous measurement of the whole list used as the last command in CSL */ +#define CLEAR_CMD_EOL 0x3FFFFFFFU /* Constant for clearing the EOL command - for channel methods */ + +static const word Table[] = { /* Table of mask constants */ +0x01U,0x02U,0x04U,0x08U,0x10U,0x20U,0x40U,0x80U,0x0100U}; +#pragma DATA_SEG DEFAULT /* Select data segment "DEFAULT" */ + +static volatile dword CSL[10] __attribute__ ((aligned (4))) = { /* Channel/Sample settings */ +0x00D90000U,0x00D80000U,0x00D70000U,0x00D60000U,0x00D50000U,0x00D40000U,0x00D30000U,0x00D20000U,0xC0D10000U,CMD_EOL}; +static volatile word RVL[18] __attribute__ ((aligned (4))); /* HW DMA result buffer */ +static volatile word OutFlg; /* Measurement finish flag */ +static volatile byte SumChan; /* Number of the measured channels */ +static volatile word ModeFlg; /* Current state of device */ +word AD1_OutV[9]; + +#define CMD_LAST_SAMPLE_PLUS_EOL 0xC0D10000U /* Last sample with command End of list */ +#define CMD_LAST_SAMPLE_PLUS_EOL_CONTINUOUS 0x80D10000U /* Last sample with command End of list */ + +//word ADCVALUE[9]={0,0,0,0,0,0,0,0,0}; +byte ADC_convert_over_flag=0;//ADתɱ־ + +//ADתжϺ +void AD1_OnEnd() +{ + ADC_convert_over_flag=1;//ADת + /*ADCVALUE[0]=AD1_OutV[0];// + ADCVALUE[1]=AD1_OutV[1];// + ADCVALUE[2]=AD1_OutV[2];// + ADCVALUE[3]=AD1_OutV[3];// + ADCVALUE[4]=AD1_OutV[4];// + ADCVALUE[5]=AD1_OutV[5];// + ADCVALUE[6]=AD1_OutV[6];// + ADCVALUE[7]=AD1_OutV[7];// + ADCVALUE[8]=AD1_OutV[8];*/ +} + +//ADתж +void AD1_OnError() +{ + +} + +//ADתֹж +void AD1_OnAbort() +{ + +} + +//Get AD average value +word AD_Average_Calculate(word *AD_Array,byte Arrsize) +{ + byte AD_i=0; + word AD_Sum=0; + for(AD_i=0;AD_i=3) + { + lin_Signal_HORN=1; + } + } + else + { + Button_11_count=0; + lin_Signal_HORN=0; + } +} +void Button_detect(unsigned char Button_state,unsigned int *Button_delay_count, + unsigned int *Lin_switch_state,unsigned char Lin_switch_data,unsigned char *initcode) +{ + unsigned char Lin_switch_state_Bit_Feed=0; + if(Button_state==0) + { + if(*initcode != 0)return; + + (*Button_delay_count)++; + if(*Button_delay_count>=3 && *Button_delay_count<12000) + { + *Lin_switch_state|=1<<(Button_to_Bit(Lin_switch_data));//0X21 + Lin_switch_state_Bit_Feed=Lin_switch_state_Bit(Lin_switch_state); + if(Lin_switch_state_Bit_Feed==1) + { + Sig_LI0_MFL_Tastencode_1=Lin_switch_data; + Sig_LI0_MFL_Tastencode_2=0; + } + else if(Lin_switch_state_Bit_Feed==2 && (Sig_LI0_MFL_Tastencode_1!=Lin_switch_data)&&(Sig_LI0_MFL_Tastencode_2==0)) + { + Sig_LI0_MFL_Tastencode_2=Lin_switch_data; + } + } + if(*Button_delay_count>=12000) + { + *Button_delay_count = 12000; + button_stick = 1; + *Lin_switch_state&=~(1<<(Button_to_Bit(Lin_switch_data))); + } + } + else + { + *Button_delay_count=0; + *Lin_switch_state&=~(1<<(Button_to_Bit(Lin_switch_data))); + *initcode = 0; + } + /* 为啥放在这？ + if(Button_to_Bit(Lin_switch_data)==9) + { + Lin_switch_state_Bit_Feed=Lin_switch_state_Bit(Lin_switch_state); + if(Lin_switch_state_Bit_Feed==0) + { + Sig_LI0_MFL_Tastencode_1=0; + Sig_LI0_MFL_Tastencode_2=0; + } + } + */ +} + +unsigned char Button_to_Bit(unsigned char Button_Sig) +{ + if(Button_Sig==4) + { + return 0; + } + else if(Button_Sig==5) + { + return 1; + } + else if(Button_Sig==7) + { + return 2; + } + else if(Button_Sig==21) + { + return 3; + } + else if(Button_Sig==22) + { + return 4; + } + else if(Button_Sig==16) + { + return 5; + } + else if(Button_Sig==17) + { + return 6; + } + else if (Button_Sig==25) + { + return 7; + } + else if(Button_Sig==28) + { + return 8; + } + else if(Button_Sig==32) + { + return 9; + } +} + +unsigned char Lin_switch_state_Bit(unsigned int *Lin_switch_state) +{ + unsigned char i,Switch_num=0; + for(i=0;i<10;i++) + { + if(*Lin_switch_state&(1< +#include "AD1.h" +#include "PWM1.h" + +void CLK_CONFIG(void); +void Peripheral_Init(void); + +#endif /* CPU_H_ */ diff --git a/Sources/DMK-BC316-77.c b/Sources/DMK-BC316-77.c new file mode 100644 index 0000000..c7d6442 --- /dev/null +++ b/Sources/DMK-BC316-77.c @@ -0,0 +1,346 @@ +/* + * DMK-S301-77.c + * + * Created on: Apr 21, 2017 + * Author: Administrator + */ +#include "DMK-BC316-77.h" + +unsigned char Ad_cal_Loop; +unsigned int Bat_power_Data; +unsigned int Bat_Values[4]; +unsigned int Bat_power_Error_count; +unsigned char Bat_power_Error_Flag; +unsigned char Sig_LI0_DI_KL_58xs_run; +unsigned char InitButtonCode=0xF0; +//调光信号、15电信号、调光使能信号 +unsigned char Sig_LI0_DI_KL_58xs,Sig_LI0_Klemme_15_MFL,Sig_LI0_Dimmung_01_gueltig; +//按键信号 +unsigned char Sig_LI0_MFL_Toggle,Sig_LI0_MFL_ButtonRight_err=0,Sig_LI0_MFL_ButtonLeft_err=0; +unsigned char Sig_LI0_MFL_Tastencode_1,Sig_LI0_MFL_Tastencode_2; +unsigned char Sig_LI0_MFL_Eventcode_1,Sig_LI0_MFL_Eventcode_2; +extern unsigned char lin_Signal_HORN; +extern l_u8 MFS_RollingCounter; +unsigned char outputdelay1,outputdelay2; + +unsigned char Toggle_start; +unsigned char Toggle_1s; +static unsigned char last1,last2,elast1,elast2; + +void Apply_Task(void) +{ + if(app_base_2mStick == 1) + { + app_base_2mStick = 0; + AD_Data_Deal(); + } + if(app_base_5mStick == 1) + { + app_base_5mStick=0; + if(Sig_LI0_Klemme_15_MFL==1) + { + Button_Scan(); + } + else + { + Sig_LI0_MFL_Tastencode_1=0; + Sig_LI0_MFL_Tastencode_2=0; + } + Eventcode_deal(Sig_LI0_MFL_Tastencode_1,Sig_LI0_MFL_Tastencode_2); + if(last1 != Sig_LI0_MFL_Tastencode_1 || last2 != Sig_LI0_MFL_Tastencode_2) + { + if(Toggle_start == 1 && Toggle_1s%20 == 0) + { + + } + else + { + Toggle_1s = 0; + Sig_LI0_MFL_Toggle=!Sig_LI0_MFL_Toggle; + Toggle_start=1; + } + last1 = Sig_LI0_MFL_Tastencode_1; + last2 = Sig_LI0_MFL_Tastencode_2; + elast1 = Sig_LI0_MFL_Eventcode_1; + elast2 = Sig_LI0_MFL_Eventcode_2; + } + else if(elast1 != Sig_LI0_MFL_Eventcode_1 || elast2 != Sig_LI0_MFL_Eventcode_2) + { + if(Toggle_start == 1 && Toggle_1s%20 == 0) + { + + } + else + { + Toggle_1s = 0; + Sig_LI0_MFL_Toggle=!Sig_LI0_MFL_Toggle; + Toggle_start=1; + } + + + elast1 = Sig_LI0_MFL_Eventcode_1; + elast2 = Sig_LI0_MFL_Eventcode_2; + last1 = Sig_LI0_MFL_Tastencode_1; + last2 = Sig_LI0_MFL_Tastencode_2; + } + if(Sig_LI0_MFL_Tastencode_1!=0 || Sig_LI0_MFL_Tastencode_2!=0) + { + + } + else + { + if(Toggle_start==1) + { + Toggle_start=2; + Toggle_1s=0; + } + last1 = 0; + last2 = 0; + } + } + if(app_base_10mStick == 1) + { + app_base_10mStick=0; + Sleep_Command_Rece(); + if(outputdelay1 > 0) + { + outputdelay1--; + } + if(outputdelay2 > 0) + { + outputdelay2--; + } + } + if(app_base_50mStick == 1) + { + app_base_50mStick=0; + + Toggle_bit_deal(Sig_LI0_MFL_Tastencode_1,Sig_LI0_MFL_Tastencode_2); + LIN_Short_to_12v_Protect(); + if((Sig_LI0_Dimmung_01_gueltig==1) && (Sig_LI0_DI_KL_58xs <= 100) && (Sig_LI0_DI_KL_58xs >= 0)) + { + Sig_LI0_DI_KL_58xs_run=Sig_LI0_DI_KL_58xs; + } + //PWM1_SetRatio16(Sig_LI0_DI_KL_58xs_run*65535/100); + } +} + +void AD_Data_Deal(void) +{ + if(ADC_convert_over_flag == 1)//AD转换完成标志 + { + ADC_convert_over_flag=0;//AD转换完成标志位清零 + Bat_Values[Ad_cal_Loop]=AD1_OutV[0]; + Ad_cal_Loop++; + if(Ad_cal_Loop>=4) + { + Ad_cal_Loop=0; + Bat_power_Data=AD_Average_Calculate(Bat_Values,4); + if(Bat_power_Data>657) //>16.7v + { + Bat_power_Error_count++; + if(Bat_power_Error_count>=500)//125为一秒，也就是4秒 + { + Bat_power_Error_Flag=1; + Bat_power_Error_count=0; + } + } + else if(Bat_power_Data>342 && Bat_power_Data<638)//>8.7v，<16.2v + { + Bat_power_Error_count=0; + Bat_power_Error_Flag=0; + } + else if(Bat_power_Data<323)//<8.2v + { + Bat_power_Error_count++; + if(Bat_power_Error_count>=500)//125为一秒，也就是4秒 + { + Bat_power_Error_Flag=1; + Bat_power_Error_count=0; + } + } + else + { + + } + } + } +} + +void Lin_Task(void) +{ + + l_bool_wr_LI0_void(1);//1-lin_pFrameBuf[0]=0x80 0-lin_pFrameBuf[0]=0x00 + l_u8_wr_LI0_MFL_Variante(4);//lin_pFrameBuf[4]=0x40 + l_bool_wr_LI0_MFL_Signalhorn(lin_Signal_HORN);//1-lin_pFrameBuf[7]=0x01 0-lin_pFrameBuf[7]=0x00 + l_bool_wr_LI0_MFL_Toggle(Sig_LI0_MFL_Toggle);//1-lin_pFrameBuf[0]=0x90 0-lin_pFrameBuf[0]=0x80 + l_bool_wr_LI0_MFL_Taste_links_Err(Sig_LI0_MFL_ButtonLeft_err); + l_bool_wr_LI0_MFL_Taste_rechts_Err(Sig_LI0_MFL_ButtonRight_err); + if(InitButtonCode != 0) + { + l_u8_wr_LI0_MFL_Tastencode_1(InitButtonCode); + } + else + { + l_u8_wr_LI0_MFL_Tastencode_1(Sig_LI0_MFL_Tastencode_1); + } + + l_u8_wr_LI0_MFL_Tastencode_2(Sig_LI0_MFL_Tastencode_2); + l_u8_wr_LI0_MFL_Eventcode_1(Sig_LI0_MFL_Eventcode_1);//Sig_LI0_MFL_Eventcode_1 + l_u8_wr_LI0_MFL_Eventcode_2(Sig_LI0_MFL_Eventcode_2);//Sig_LI0_MFL_Eventcode_2 + Sig_LI0_DI_KL_58xs=l_u8_rd_LI0_DI_KL_58xs(); + Sig_LI0_Klemme_15_MFL=l_bool_rd_LI0_Klemme_15_MFL(); + Sig_LI0_Dimmung_01_gueltig=l_bool_rd_LI0_Dimmung_01_gueltig(); + l_u8_wr_LI0_MFL_Zaehler(MFS_RollingCounter); +} + +void Sleep_Command_Rece(void) +{ + if ((M_ASK_S_Sleep==1 || NO_DATA_Sleep==1) && (Sig_LI0_DI_KL_58xs==0X7e || Sig_LI0_DI_KL_58xs==0X7f || Sig_LI0_DI_KL_58xs==0 || Sig_LI0_DI_KL_58xs==1)) + { + V_12_Ctrl=0; + FLAG_GO_TO_Sleep=1; + //关闭中断 + SCI0CR2_RE=0; + SCI0CR2_TE=0; + SCI0CR2_RIE=0; + //开启中断 + SCI0CR2_RE=1; + SCI0CR2_TE=1; + SCI0CR2_RIE=1; + PWM1_SetRatio16(0); + PTJ_PTJ1=0; + PTP_PTP7=0; + clrReg8Bits(PWME, 0x80U); /* Run counter */ + CPU_ENTER_STOP_MODE(); + } +} + +void Eventcode_deal(unsigned char Sig_LI0_MFL_Tastencode_1_E,unsigned char Sig_LI0_MFL_Tastencode_2_E) +{ + // 静态变量，用于记录按键时长计数 + static unsigned int Event_code1_count,Event_code2_count; + if(Sig_LI0_MFL_Tastencode_1_E!=0) + { + Sig_LI0_MFL_Eventcode_1=1; + + if(Event_code1_count<=600) + { + Event_code1_count++; + } + + if(Event_code1_count>=160 && Event_code1_count<400) + { + Sig_LI0_MFL_Eventcode_1=4; + } + else if(Event_code1_count>=400 && Event_code1_count<600) + { + Sig_LI0_MFL_Eventcode_1=5; + } + else if(Event_code1_count>=600) + { + Sig_LI0_MFL_Eventcode_1=6; + } + + } + else + { + Sig_LI0_MFL_Eventcode_1=0; + Event_code1_count=0; + } + + if(Sig_LI0_MFL_Tastencode_2_E!=0) + { + Sig_LI0_MFL_Eventcode_2=1; + if(Event_code2_count<=600) + { + Event_code2_count++; + } + + if(Event_code2_count>=160 && Event_code2_count<400) + { + Sig_LI0_MFL_Eventcode_2=4; + } + else if(Event_code2_count>=400 && Event_code2_count<600) + { + Sig_LI0_MFL_Eventcode_2=5; + } + else if(Event_code2_count>=600) + { + Sig_LI0_MFL_Eventcode_2=6; + } + } + else + { + Sig_LI0_MFL_Eventcode_2=0; + Event_code2_count=0; + } +} + +void Toggle_bit_deal(unsigned char Sig_LI0_MFL_Tastencode_1_E,unsigned char Sig_LI0_MFL_Tastencode_2_E) +{ + if(Toggle_start==1) + { + Toggle_1s++; + if(Toggle_1s%20==0) + { + Sig_LI0_MFL_Toggle=!Sig_LI0_MFL_Toggle; + if(Toggle_1s==80) + { + Toggle_1s=0; + } + } + } + + if(Toggle_start==2) + { + Toggle_1s++; + if(Toggle_1s%20==0) + { + Sig_LI0_MFL_Toggle=!Sig_LI0_MFL_Toggle; + if(Toggle_1s==100) + { + Toggle_1s=0; + Toggle_start=0; + } + } + } +} + +void LIN_Short_to_12v_Protect(void) +{ + static unsigned char LIN_Short_count,LIN_Short_recover_count; + if(LP0IF_LPOCIF==1) + { + if(LIN_Short_count<=60) + { + LIN_Short_count++; + LP0IF_LPOCIF=1; + } + } + else + { + LIN_Short_recover_count++; + if(LIN_Short_recover_count>=20) + { + LIN_Short_recover_count=0; + LIN_Short_count=0; + } + } +} + +//睡眠lin唤醒使能位 +void LIN_STANDBY_Mode_wakeup_enable(void) +{ + LP0CR_LPWUE=1;//在stop mode下，若lin接收到数据，则会在LPRXD产生一个上升沿 + LP0CR_LPPUE=1;//选择上拉方式 +} + +//进入停止模式 +void CPU_ENTER_STOP_MODE(void) +{ + asm ANDCC #0x7F; //clear S bit - enable the stop mode. If the S bit is not + //cleared then STOP instruction has no effect and is + //executed as a dummy instruction NOP. + asm STOP; +} diff --git a/Sources/DMK-BC316-77.h b/Sources/DMK-BC316-77.h new file mode 100644 index 0000000..119e5c8 --- /dev/null +++ b/Sources/DMK-BC316-77.h @@ -0,0 +1,71 @@ +/* + * DMK-S301-77.h + * + * Created on: Apr 21, 2017 + * Author: Administrator + */ + +#ifndef DMK_S301_77_H_ +#define DMK_S301_77_H_ + +#include "CPU.h" +#include "lin.h" +#include "AD1.h" +#include "TI1.h" +#include "PWM1.h" +#include "WDog1.h" +#include "Button.h" + +//һ·ADһ +typedef struct +{ + unsigned int *AD_switch_array; + unsigned char AD_channel; + unsigned char *S1_switch; + unsigned int *S1_delay_count; + unsigned char *AD_short_delay_count; +}AD_LIN_one_switch; + +typedef struct +{ + unsigned int *S1_delay_count; + unsigned char *AD_short_delay_count; +}io_one_switch; +//һ·AD +typedef struct +{ + unsigned int *AD_switch_array; + unsigned char AD_channel; + unsigned char *S1_switch; + unsigned char *S2_switch; + unsigned int *S1_delay_count; + unsigned int *S2_delay_count; + unsigned char *AD_short_delay_count; +}AD_LIN_two_switch; +typedef struct +{ + unsigned int *AD_switch_array; + unsigned char AD_channel; + unsigned char *S1_switch; + unsigned char *S2_switch; + unsigned char *S3_switch; + unsigned int *S1_delay_count; + unsigned int *S2_delay_count; + unsigned int *S3_delay_count; + unsigned char *AD_short_delay_count; +}AD_LIN_three_switch; + +extern unsigned char Sig_LI0_MFL_Tastencode_1,Sig_LI0_MFL_Tastencode_2; +extern unsigned char Sig_LI0_DI_KL_58xs_run; + +void Apply_Task(void); +void Lin_Task(void); +void AD_Data_Deal(void); +void Sleep_Command_Rece(void); +void Eventcode_deal(unsigned char Sig_LI0_MFL_Tastencode_1_E,unsigned char Sig_LI0_MFL_Tastencode_2_E); +void Toggle_bit_deal(unsigned char Sig_LI0_MFL_Tastencode_1_E,unsigned char Sig_LI0_MFL_Tastencode_2_E); +void LIN_STANDBY_Mode_wakeup_enable(void); +void CPU_ENTER_STOP_MODE(void); +void LIN_Short_to_12v_Protect(void); + +#endif /* DMK_S301_77_H_ */ diff --git a/Sources/PWM1.c b/Sources/PWM1.c new file mode 100644 index 0000000..5750bfd --- /dev/null +++ b/Sources/PWM1.c @@ -0,0 +1,204 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PWM1.c +** Project : DMK-BC316-77-AUTO +** Processor : MC9S12ZVL32MLF +** Component : PWM +** Version : Component 02.240, Driver 01.16, CPU db: 3.00.000 +** Compiler : CodeWarrior HCS12Z C Compiler +** Date/Time : 2018-03-24, 10:58, # CodeGen: 18 +** Abstract : +** This component implements a pulse-width modulation generator +** that generates signal with variable duty and fixed cycle. +** Settings : +** Used output pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 39 | PP5_XIRQ_KWP5_PWM5 +** ---------------------------------------------------- +** +** Timer name : PWM5 [8-bit] +** Counter : PWMCNT5 [0x0491] +** Mode register : PWMCTL [0x0485] +** Run register : PWME [0x0480] +** Prescaler : PWMPRCLK [0x0483] +** Compare 1 register : PWMPER5 [0x0499] +** Compare 2 register : PWMDTY5 [0x04A1] +** Flip-flop 1 register : PWMPOL [0x0481] +** +** User handling procedure : not specified +** +** Output pin +** +** Port name : P +** Bit number (in port) : 5 +** Bit mask of the port : 0x0020 +** Port data register : PTP [0x02F0] +** Port control register : DDRP [0x02F2] +** +** Runtime setting period : none +** Runtime setting ratio : calculated +** Initialization: +** Aligned : Left +** Output level : low +** Timer : Enabled +** Event : Enabled +** High speed mode +** Prescaler : divide-by-1 +** Clock : 53333 Hz +** Initial value of period pulse width (ratio 0%) +** Xtal ticks : 4781 0 +** microseconds : 4781 0 +** milliseconds : 5 0 +** seconds (real) : 0.00478125 0.0 +** +** Contents : +** SetRatio16 - byte PWM1_SetRatio16(word Ratio); +** SetDutyUS - byte PWM1_SetDutyUS(word Time); +** SetDutyMS - byte PWM1_SetDutyMS(word Time); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PWM1.c +** @version 01.16 +** @brief +** This component implements a pulse-width modulation generator +** that generates signal with variable duty and fixed cycle. +*/ +/*! +** @addtogroup PWM1_module PWM1 module documentation +** @{ +*/ + + +/* MODULE PWM1. */ + +#include "PWM1.h" + +#pragma DATA_SEG PWM1_DATA /* Select data segment "PWM1_DATA" */ + +#pragma CODE_SEG PWM1_CODE + +static word RatioStore; /* Ratio of L-level to H-level */ + + +/* +** =================================================================== +** Method : SetRatio (component PWM) +** +** Description : +** The method reconfigures the compare and modulo registers of +** the peripheral(s) when the speed mode changes. The method is +** called automatically as a part of the component +** SetHigh/SetLow/SetSlow methods. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +static void SetRatio(void) +{ + PWMDTY7 = (byte)(((0xFFUL * (dword)RatioStore) + 0x8000UL) >> 0x10U); /* Calculate new value according to the given ratio */ +} + +/* +** =================================================================== +** Method : PWM1_SetRatio16 (component PWM) +** Description : +** This method sets a new duty-cycle ratio. Ratio is expressed +** as a 16-bit unsigned integer number. Value 0 - 65535 value +** is proportional to ratio 0 - 100%. +** Note: Calculated duty depends on the timer possibilities and +** on the selected period. +** The method is available only if method is +** not selected. +** Parameters : +** NAME - DESCRIPTION +** Ratio - Ratio to set. 0 - 65535 value is +** proportional to ratio 0 - 100% +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte PWM1_SetRatio16(word Ratio) +{ + RatioStore = Ratio; /* Store new value of the ratio */ + SetRatio(); /* Calculate and set up new appropriate values of the duty and period registers */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : PWM1_Init (component PWM) +** +** Description : +** Initializes the associated peripheral(s) and the component's +** internal variables. The method is called automatically as a +** part of the application initialization code. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void PWM1_Init(void) +{ + /* PWMCNT7: PWMCNT7=0 */ + setReg8(PWMCNT7, 0x00U); /* Reset Counter */ + RatioStore = 0xFFFFU; ; /* Store initial value of the ratio */ + /* PWMDTY7: PWMDTY7=0x82 */ + setReg8(PWMDTY7, 0x00U); /* Store initial value to the duty-compare register */ + /* PWMPER7: PWMPER7=0xFF */ + setReg8(PWMPER7, 0xFFU); /* and to the period register */ + /* PWMPRCLK: ??=0,PCKB2=0,PCKB1=0,PCKB0=0,??=0,PCKA2=0,PCKA1=0,PCKA0=0 */ + setReg8(PWMPRCLK, 0x00U); /* Set prescaler register */ + /* PWMSCLB: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=1,BIT2=1,BIT1=0,BIT0=0 */ + setReg8(PWMSCLB, 0x0CU); /* Set scale register */ + /* PWMCLK: PCLK7=1 */ + setReg8Bits(PWMCLK, 0x80U); /* Select clock source */ + /* PWME: PWME7=1 */ + setReg8Bits(PWME, 0x80U); /* Run counter */ +} + +/* END PWM1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.3 [05.09] +** for the Freescale HCS12Z series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Sources/PWM1.h b/Sources/PWM1.h new file mode 100644 index 0000000..4f3c7e6 --- /dev/null +++ b/Sources/PWM1.h @@ -0,0 +1,168 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PWM1.h +** Project : DMK-BC316-77-AUTO +** Processor : MC9S12ZVL32MLF +** Component : PWM +** Version : Component 02.240, Driver 01.16, CPU db: 3.00.000 +** Compiler : CodeWarrior HCS12Z C Compiler +** Date/Time : 2018-03-24, 10:58, # CodeGen: 18 +** Abstract : +** This component implements a pulse-width modulation generator +** that generates signal with variable duty and fixed cycle. +** Settings : +** Used output pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 39 | PP5_XIRQ_KWP5_PWM5 +** ---------------------------------------------------- +** +** Timer name : PWM5 [8-bit] +** Counter : PWMCNT5 [0x0491] +** Mode register : PWMCTL [0x0485] +** Run register : PWME [0x0480] +** Prescaler : PWMPRCLK [0x0483] +** Compare 1 register : PWMPER5 [0x0499] +** Compare 2 register : PWMDTY5 [0x04A1] +** Flip-flop 1 register : PWMPOL [0x0481] +** +** User handling procedure : not specified +** +** Output pin +** +** Port name : P +** Bit number (in port) : 5 +** Bit mask of the port : 0x0020 +** Port data register : PTP [0x02F0] +** Port control register : DDRP [0x02F2] +** +** Runtime setting period : none +** Runtime setting ratio : calculated +** Initialization: +** Aligned : Left +** Output level : low +** Timer : Enabled +** Event : Enabled +** High speed mode +** Prescaler : divide-by-1 +** Clock : 53333 Hz +** Initial value of period pulse width (ratio 0%) +** Xtal ticks : 4781 0 +** microseconds : 4781 0 +** milliseconds : 5 0 +** seconds (real) : 0.00478125 0.0 +** +** Contents : +** SetRatio16 - byte PWM1_SetRatio16(word Ratio); +** SetDutyUS - byte PWM1_SetDutyUS(word Time); +** SetDutyMS - byte PWM1_SetDutyMS(word Time); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PWM1.h +** @version 01.16 +** @brief +** This component implements a pulse-width modulation generator +** that generates signal with variable duty and fixed cycle. +*/ +/*! +** @addtogroup PWM1_module PWM1 module documentation +** @{ +*/ + +#ifndef __PWM1 +#define __PWM1 + +/* MODULE PWM1. */ + +#include "derivative.h" +#include "CPU.h" +#pragma CODE_SEG PWM1_CODE + +#define PWM1_PERIOD_VALUE 0xFFUL /* Initial period value in ticks of the timer */ +#define PWM1_PERIOD_VALUE_HIGH 0xFFUL /* Initial period value in ticks of the timer in high speed mode */ + +byte PWM1_SetRatio16(word Ratio); +/* +** =================================================================== +** Method : PWM1_SetRatio16 (component PWM) +** Description : +** This method sets a new duty-cycle ratio. Ratio is expressed +** as a 16-bit unsigned integer number. Value 0 - 65535 value +** is proportional to ratio 0 - 100%. +** Note: Calculated duty depends on the timer possibilities and +** on the selected period. +** The method is available only if method is +** not selected. +** Parameters : +** NAME - DESCRIPTION +** Ratio - Ratio to set. 0 - 65535 value is +** proportional to ratio 0 - 100% +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +void PWM1_Init(void); +/* +** =================================================================== +** Method : PWM1_Init (component PWM) +** +** Description : +** Initializes the associated peripheral(s) and the component's +** internal variables. The method is called automatically as a +** part of the application initialization code. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT + +/* END PWM1. */ + +#endif /* ifndef __PWM1 */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.3 [05.09] +** for the Freescale HCS12Z series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Sources/TI1.c b/Sources/TI1.c new file mode 100644 index 0000000..7ca8bb7 --- /dev/null +++ b/Sources/TI1.c @@ -0,0 +1,40 @@ +#include "TI1.h" + +static unsigned int AppliTick=0; +bool app_base_2mStick,app_base_5mStick,app_base_10mStick,app_base_20mStick,app_base_50mStick,app_base_100mStick; +//1msж +#pragma CODE_SEG __NEAR_SEG NON_BANKED +void interrupt VectorNumber_Vtim1ch0 TI1_OnInterrupt(void) +{ + TIM1TC0 += 0x7D00U; /* Add value corresponding with period */ + TIM1TFLG1 = 0x01U; /* Reset interrupt request flag */ + + AppliTick++; + if(AppliTick % 2 == 0) + { + app_base_2mStick = 1; + } + if(AppliTick % 5 == 0) + { + app_base_5mStick = 1; + } + if(AppliTick % 10 == 0) + { + app_base_10mStick = 1; + } + if(AppliTick % 20 == 0) + { + app_base_20mStick = 1; + } + if(AppliTick %50 == 0) + { + app_base_50mStick = 1; + } + if(AppliTick % 100 == 0) + { + app_base_100mStick = 1; + AppliTick=0; + } +} + +#pragma CODE_SEG TI1_CODE diff --git a/Sources/TI1.h b/Sources/TI1.h new file mode 100644 index 0000000..fef3f1b --- /dev/null +++ b/Sources/TI1.h @@ -0,0 +1,8 @@ +#ifndef __TI1 +#define __TI1 + +#include "derivative.h" + +extern bool app_base_2mStick,app_base_5mStick,app_base_10mStick,app_base_20mStick,app_base_50mStick,app_base_100mStick; + +#endif diff --git a/Sources/WDog1.c b/Sources/WDog1.c new file mode 100644 index 0000000..d31c93c --- /dev/null +++ b/Sources/WDog1.c @@ -0,0 +1,142 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : WDog1.c +** Project : DMK-BC316-77-AUTO +** Processor : MC9S12ZVL32MLF +** Component : WatchDog +** Version : Component 02.142, Driver 01.16, CPU db: 3.00.000 +** Compiler : CodeWarrior HCS12Z C Compiler +** Date/Time : 2018-01-26, 14:54, # CodeGen: 2 +** Abstract : +** This device "WatchDog" implements a watchdog. +** When enabled, the watchdog timer counts until it reaches +** a critical value corresponding to the period specified +** in 'Properties'. Then, the watchdog causes a CPU reset. +** Applications may clear the timer before it reaches the critical +** value. The timer then restarts the watchdog counter. +** Watchdog is used for increasing the safety of the system +** (unforeseeable situations can cause system crash or an +** infinite loop - watchdog can restart the system or handle +** the situation). +** +** Note: Watchdog can be enabled or disabled in the initialization +** code only. If the watchdog is once enabled user have +** to call Clear method in defined time intervals. +** Settings : +** Watchdog causes : Reset CPU +** +** Clock Source : Bus clock +** +** Initial Watchdog state : Enabled +** +** Mode of operation : Normal +** +** High speed mode +** Watchdog period/frequency +** microseconds : 4194304 +** milliseconds : 4194 +** seconds : 4 +** +** Run register : CPMUCOP [0x06CC] +** Mode register : CPMUCOP [0x06CC] +** Prescaler register : CPMUCOP [0x06CC] +** Contents : +** Clear - byte WDog1_Clear(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file WDog1.c +** @version 01.16 +** @brief +** This device "WatchDog" implements a watchdog. +** When enabled, the watchdog timer counts until it reaches +** a critical value corresponding to the period specified +** in 'Properties'. Then, the watchdog causes a CPU reset. +** Applications may clear the timer before it reaches the critical +** value. The timer then restarts the watchdog counter. +** Watchdog is used for increasing the safety of the system +** (unforeseeable situations can cause system crash or an +** infinite loop - watchdog can restart the system or handle +** the situation). +** +** Note: Watchdog can be enabled or disabled in the initialization +** code only. If the watchdog is once enabled user have +** to call Clear method in defined time intervals. +*/ +/*! +** @addtogroup WDog1_module WDog1 module documentation +** @{ +*/ + + +/* MODULE WDog1. */ + +#include "WDog1.h" + +#pragma DATA_SEG WDog1_DATA /* Select data segment "WDog1_DATA" */ +#pragma CODE_SEG WDog1_CODE + +/* +** =================================================================== +** Method : WDog1_Clear (component WatchDog) +** Description : +** Clears the watchdog timer (it makes the timer restart from +** zero). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_DISABLED - The component is disabled +** =================================================================== +*/ +void WDog1_Clear(void) +{ + CPMUARMCOP = 0x55U; + CPMUARMCOP = 0xAAU; +} + +/* END WDog1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.3 [05.09] +** for the Freescale HCS12Z series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Sources/WDog1.h b/Sources/WDog1.h new file mode 100644 index 0000000..af5586e --- /dev/null +++ b/Sources/WDog1.h @@ -0,0 +1,145 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : WDog1.h +** Project : DMK-BC316-77-AUTO +** Processor : MC9S12ZVL32MLF +** Component : WatchDog +** Version : Component 02.142, Driver 01.16, CPU db: 3.00.000 +** Compiler : CodeWarrior HCS12Z C Compiler +** Date/Time : 2018-01-26, 14:54, # CodeGen: 2 +** Abstract : +** This device "WatchDog" implements a watchdog. +** When enabled, the watchdog timer counts until it reaches +** a critical value corresponding to the period specified +** in 'Properties'. Then, the watchdog causes a CPU reset. +** Applications may clear the timer before it reaches the critical +** value. The timer then restarts the watchdog counter. +** Watchdog is used for increasing the safety of the system +** (unforeseeable situations can cause system crash or an +** infinite loop - watchdog can restart the system or handle +** the situation). +** +** Note: Watchdog can be enabled or disabled in the initialization +** code only. If the watchdog is once enabled user have +** to call Clear method in defined time intervals. +** Settings : +** Watchdog causes : Reset CPU +** +** Clock Source : Bus clock +** +** Initial Watchdog state : Enabled +** +** Mode of operation : Normal +** +** High speed mode +** Watchdog period/frequency +** microseconds : 4194304 +** milliseconds : 4194 +** seconds : 4 +** +** Run register : CPMUCOP [0x06CC] +** Mode register : CPMUCOP [0x06CC] +** Prescaler register : CPMUCOP [0x06CC] +** Contents : +** Clear - byte WDog1_Clear(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file WDog1.h +** @version 01.16 +** @brief +** This device "WatchDog" implements a watchdog. +** When enabled, the watchdog timer counts until it reaches +** a critical value corresponding to the period specified +** in 'Properties'. Then, the watchdog causes a CPU reset. +** Applications may clear the timer before it reaches the critical +** value. The timer then restarts the watchdog counter. +** Watchdog is used for increasing the safety of the system +** (unforeseeable situations can cause system crash or an +** infinite loop - watchdog can restart the system or handle +** the situation). +** +** Note: Watchdog can be enabled or disabled in the initialization +** code only. If the watchdog is once enabled user have +** to call Clear method in defined time intervals. +*/ +/*! +** @addtogroup WDog1_module WDog1 module documentation +** @{ +*/ + +#ifndef __WDog1 +#define __WDog1 + +/* MODULE WDog1. */ + +#include "CPU.h" + +#pragma CODE_SEG WDog1_CODE + + +/* +** =================================================================== +** Method : WDog1_Clear (component WatchDog) +** Description : +** Clears the watchdog timer (it makes the timer restart from +** zero). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_DISABLED - The component is disabled +** =================================================================== +*/ +void WDog1_Clear(void); + + + +#pragma CODE_SEG DEFAULT + +/* END WDog1. */ + +#endif /* ifndef __WDog1 */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.3 [05.09] +** for the Freescale HCS12Z series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Sources/diagnostic/diagnostic_DID.c b/Sources/diagnostic/diagnostic_DID.c new file mode 100644 index 0000000..e16c87a --- /dev/null +++ b/Sources/diagnostic/diagnostic_DID.c @@ -0,0 +1,143 @@ +/* + * diagnostic_DID.c + * + * Created on: Feb 16, 2019 + * Author: Administrator + */ + + +#include "diagnostic_DID.h" + +/*******************************配置DID*************************************/ +const TYPE_DIDSRVARR DID_CheckArr[DEF_DID_NUM]={ + {0xF187, 11, &DIDsrv_ReadPartnumber}, + {0xF189, 4, &DIDsrv_ReadSoftwareVersion}, + {0xF191, 11, &DIDsrv_ReadPartnumber}, + {0xF1A3, 3, &DIDsrv_ReadHardwareVersion}, + {0x062E, 3, &DIDsrv_ReadSlaveCoding}, + {0x065E, 11, &DIDsrv_ReadPartnumber}, + {0x068E, 4, &DIDsrv_ReadSoftwareVersion}, + {0x06BE, 11, &DIDsrv_ReadPartnumber}, + {0x06EE, 3, &DIDsrv_ReadHardwareVersion}, + {0x071E, 20, &DIDsrv_ReadSerialnumber}, + {0x074E, 13, &DIDsrv_ReadSystemName}, + {0x6031, 3, &DIDsrv_ReadSlaveCoding}, + {0x6231, 11, &DIDsrv_ReadPartnumber}, + {0x6431, 4, &DIDsrv_ReadSoftwareVersion}, + {0x6631, 11, &DIDsrv_ReadPartnumber}, + {0x6831, 3, &DIDsrv_ReadHardwareVersion}, + {0x6A31, 20, &DIDsrv_ReadSerialnumber}, + {0x6C31, 13, &DIDsrv_ReadSystemName}, + {0xF15B, 9, &DIDsrv_ReadF15B}, + {0xF186, 1, &DIDsrv_ReadF186}, + //{0xF198, 13, &DIDsrv_ReadF198},//样件读取错误 + //{0xF19E, 16, &DIDsrv_ReadF19E},//数据有风险 + {0xF1A2, 6, &DIDsrv_ReadF1A2}, + {0xF1DF, 1, &DIDsrv_ReadF1DF}, + {0xF18C, 20, &DIDsrv_ReadSerialnumber}, + {0xF17C, 23, &DIDsrv_ReadFAZIT}, + {0xF197, 13, &DIDsrv_ReadSystemName}, +}; + +//const char DIDList_SWVersion[8]@0xff7000="SW0102"; +const char DIDList_SWVersion[4]="0308"; +const char DIDList_HWVersion[3]="H04"; +const unsigned char DIDList_PartNumber[8]={0x11,0x22,0x33,0x44}; +const unsigned char DIDList_ManufacturingData[8]={0x20,0x20,0x07,0x22}; +const char DIDList_ECUname[16]={"DMK-BC316-77"}; +const char DIDList_PartNum[11]={"5CG959442B "}; +const unsigned char DIDList_SlaveCoding[3]={0x24,0x00,0x00};//按照样件改为24 00 00 +const char DIDList_SerialNum[20]={"0521910200700191DQ4J"}; +const char DIDList_SystemName[13]={"E221__MFL-TAT"}; +const char DIDList_F15B[9]={0,1,1,0,0,0,0,0,0}; +const char DIDList_F186[1]={1}; +const char DIDList_F198[1]={0xff}; +const char DIDList_F19E[16]={"EV_MFLTRWVW250GP"}; +const char DIDList_F1A2[6]={"001001"}; +const char DIDList_F1DF[1]={0x40}; +const char DIDList_FAZIT[23]={"S5G-DMG18.11.2400010001"}; +/******************************************************************************/ + +void DIDsrv_ReadSoftwareVersion(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_SWVersion,addr,length); +} +void DIDsrv_ReadFAZIT(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_FAZIT,addr,length); +} +void DIDsrv_ReadHardwareVersion(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_HWVersion,addr,length); +} +void DIDsrv_ReadBootloaderVersion(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)0xfff000,addr,length); +} +void DIDsrv_ReadDMPartNumber(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_PartNumber,addr,length); +} +void DIDsrv_ReadManufacturingData(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_ManufacturingData,addr,length); +} +void DIDsrv_ReadECUname(unsigned char length,unsigned char * addr) +{ + //unsigned char conf; + DataCopy8bit((unsigned char *)(DIDList_ECUname[0]),addr,length); +} + + +void DIDsrv_ReadPartnumber(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_PartNum,addr,length); +} + +void DIDsrv_ReadSlaveCoding(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_SlaveCoding,addr,length); +} + +void DIDsrv_ReadSerialnumber(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_SerialNum,addr,length); +} + +void DIDsrv_ReadSystemName(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_SystemName,addr,length); +} + +void DIDsrv_ReadF15B(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F15B,addr,length); +} +void DIDsrv_ReadF186(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F186,addr,length); +} +void DIDsrv_ReadF198(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F198,addr,length); +} +void DIDsrv_ReadF19E(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F19E,addr,length); +} +void DIDsrv_ReadF1A2(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F1A2,addr,length); +} +void DIDsrv_ReadF1DF(unsigned char length,unsigned char * addr) +{ + DataCopy8bit((unsigned char *)DIDList_F1DF,addr,length); +} + +void DataCopy8bit(unsigned char* source,unsigned char* dest,unsigned char length) +{ + while(length-- > 0) + { + *(dest++) = *(source++); + } +} diff --git a/Sources/diagnostic/diagnostic_DID.h b/Sources/diagnostic/diagnostic_DID.h new file mode 100644 index 0000000..89a6bac --- /dev/null +++ b/Sources/diagnostic/diagnostic_DID.h @@ -0,0 +1,47 @@ +/* + * diagnostic_DID.h + * + * Created on: Feb 16, 2019 + * Author: Administrator + */ + +#ifndef DIAGNOSTIC_DID_H_ +#define DIAGNOSTIC_DID_H_ + +#include "diagnostic_service_slave.h" + +#define DEF_DID_NUM 25 + +typedef struct +{ + unsigned int DID_id; + unsigned char length; + DIDSRVFUNCTION_DEF DID_Func; +}TYPE_DIDSRVARR; + +extern const TYPE_DIDSRVARR DID_CheckArr[]; + + + + + +void DIDsrv_ReadSoftwareVersion(unsigned char length,unsigned char * addr); +void DIDsrv_ReadFAZIT(unsigned char length,unsigned char * addr); +void DIDsrv_ReadHardwareVersion(unsigned char length,unsigned char * addr); +void DIDsrv_ReadBootloaderVersion(unsigned char length,unsigned char * addr); +void DIDsrv_ReadDMPartNumber(unsigned char length,unsigned char * addr); +void DIDsrv_ReadManufacturingData(unsigned char length,unsigned char * addr); +void DIDsrv_ReadECUname(unsigned char length,unsigned char * addr); +void DataCopy8bit(unsigned char* source,unsigned char* dest,unsigned char length); +void DIDsrv_ReadPartnumber(unsigned char length,unsigned char * addr); +void DIDsrv_ReadSystemName(unsigned char length,unsigned char * addr); +void DIDsrv_ReadSerialnumber(unsigned char length,unsigned char * addr); +void DIDsrv_ReadSlaveCoding(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF15B(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF186(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF198(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF19E(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF1A2(unsigned char length,unsigned char * addr); +void DIDsrv_ReadF1DF(unsigned char length,unsigned char * addr); + +#endif /* DIAGNOSTIC_DID_H_ */ diff --git a/Sources/diagnostic/diagnostic_service_slave.c b/Sources/diagnostic/diagnostic_service_slave.c new file mode 100644 index 0000000..b31df5c --- /dev/null +++ b/Sources/diagnostic/diagnostic_service_slave.c @@ -0,0 +1,453 @@ +#include "lin_cfg.h" +#include "diagnostic_service_slave.h" +#include "diagnostic_DID.h" + +#include "DMK-BC316-77.h" + + + +//extern byte LED_value; +const unsigned long serial_number = SERIAL_NUBER_INT; /* for read & write serial_number services */ +const unsigned char io_control_status = IO_CONTROL_STATUS_INT; /* for read & set io */ +const unsigned int session_control_P3 = SESSION_CONTROL_P3; /* for session control service */ +const unsigned int session_control_P3Ex = SESSION_CONTROL_P3Ex; /* for session control service */ + +const unsigned char DtcStatusByte = DTCSTATUSBTYE_INT ; /* for fault memory */ +const unsigned char DtcFormatIdentifier = DTCFORMATIDENTIFER_INT; /* for fault memory */ +const unsigned char CountDtc = COUNTDTC_INT; /* for fault memory */ + + +const TYPE_DIAGSERVICEARR DiagServiceCheckArr[DEF_DIAGSERVICE_COUNT]={ + {DIAGSRV_READ_DATA_BY_IDENTIFIER_ORDER,&diagsrv_read_data_by_identifier},//22 + {DIAGSRV_WRITE_DATA_BY_IDENTIFIER_ORDER,&diagsrv_write_data_by_identifier},//2E + {DIAGSRV_SESSION_CONTROL_ORDER,&diagsrv_session_control},//10 + {DIAGSRV_TESTERPRESENT_ORDER,&diagsrv_tester_present},//3E + {DIAGSRV_ECURESET_ORDER,&diagsrv_ECU_reset},//00 + {DIAGSRV_COMMUNICATIONCONTROL_ORDER,&diagsrv_communication_control},//28 + {DIAGSRV_ROUTINECONTROL_ORDER,&diagsrv_routine_control},//31 + {DIAGSRV_ASSIGN_FRAME_ID_RANGE_ORDER,&diagsrv_B7},//B7 +}; +/**/ +volatile l_u8 master_req_dat[MASTER_REQ_LENGTH_MAX]; +volatile l_u16 master_req_length; + +volatile l_u8 slave_resp_dat[MASTER_REQ_LENGTH_MAX]; +volatile l_u16 slave_resp_length; + +l_u8 resetflag=0; + +void diagsrv_routine_control(void) +{ + ld_receive_message((l_u16*)&master_req_length, (l_u8*)master_req_dat); + if(master_req_length != 4) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x13;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + if(master_req_dat[1] == 0x01) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x31;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x12;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + } + + /*clear diagnostic flag */ + diag_clear_flag(DIAGSRV_ROUTINECONTROL_ORDER); +} +void diagsrv_communication_control(void) +{ + ld_receive_message((l_u16*)&master_req_length, (l_u8*)master_req_dat); + if(master_req_length != 3) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x13;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + if((master_req_dat[1]&0x7f) == 0x00 || (master_req_dat[1]&0x7f) == 0x01) + { + slave_resp_length = 3; + slave_resp_dat[0] = master_req_dat[0] + 0x40; + slave_resp_dat[1] = master_req_dat[1]; + slave_resp_dat[2] = master_req_dat[2]; + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x31;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + } + /*clear diagnostic flag */ + diag_clear_flag(DIAGSRV_COMMUNICATIONCONTROL_ORDER); +} +void diagsrv_ECU_reset(void) +{ + ld_receive_message((l_u16*)&master_req_length, (l_u8*)master_req_dat); + if(master_req_length != 2) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x13;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + if(master_req_dat[1] == 0x01) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x22;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x31;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + } + /*clear diagnostic flag */ + diag_clear_flag(DIAGSRV_ECURESET_ORDER); +} +void diagsrv_tester_present(void) +{ + ld_receive_message((l_u16*)&master_req_length, (l_u8*)master_req_dat); + if(master_req_length != 2) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x13;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else + { + if(master_req_dat[1] == 0x00) + { + slave_resp_length = 2; + slave_resp_dat[0] = master_req_dat[0] + 0x40; + slave_resp_dat[1] = master_req_dat[1]; + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + else if(master_req_dat[1] == 0x80) + { + ;//0x80Ӧ + } + else + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x31;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + } + } + + + /*clear diagnostic flag */ + diag_clear_flag(DIAGSRV_TESTERPRESENT_ORDER); +} + +void diagsrv_read_data_by_identifier(void) +{ + /* Implement code of this service here */ + unsigned char i; + unsigned int DID_id; + ld_receive_message((l_u16*)&master_req_length, (l_u8*)master_req_dat); + DID_id = master_req_dat[1]; + DID_id <<= 8; + DID_id |= master_req_dat[2]; + + if(master_req_length != 3) + { + slave_resp_length = 3; + slave_resp_dat[0] = 0x7F; + slave_resp_dat[1] = master_req_dat[0]; + slave_resp_dat[2] = 0x13;//Ӧ + /* send a message to master */ + ld_send_message((l_u16)slave_resp_length, (l_u8*)slave_resp_dat); + diag_clear_flag(DIAGSRV_READ_DATA_BY_IDENTIFIER_ORDER); + return; + } + + for(i=0;i10) + SoftwareRest(); + } + else + { + resetcnt=0; + } +} diff --git a/Sources/diagnostic/diagnostic_service_slave.h b/Sources/diagnostic/diagnostic_service_slave.h new file mode 100644 index 0000000..1d58c20 --- /dev/null +++ b/Sources/diagnostic/diagnostic_service_slave.h @@ -0,0 +1,57 @@ +#ifndef _DIAGNOSTIC_SERVICE_SLAVE_H_ +#define _DIAGNOSTIC_SERVICE_SLAVE_H_ + +#include "lin_commontl_api.h" +#include "lin.h" +#include "lin_lin21tl_api.h" + +/*------------------------------------------*/ +#define SERIAL_NUBER_INT 0x00 +#define IO_CONTROL_STATUS_INT 0x00 +#define SESSION_CONTROL_P3 0x01F4 +#define SESSION_CONTROL_P3Ex 0x09C4 +#define DTCSTATUSBTYE_INT 0x00 +#define DTCFORMATIDENTIFER_INT 0x01 +#define COUNTDTC_INT 0x00 +/*------------------------------------------*/ +/* DEFINITION */ +#define MASTER_REQ_LENGTH_MAX 64 +#define DEF_DIAGSERVICE_COUNT 8 +/*------------------- Struct Define -----------------------*/ + +typedef void (*PT2FUNCTION_DEF)(void); +typedef void (*DIDSRVFUNCTION_DEF)(unsigned char,unsigned char*); + + +typedef struct +{ + unsigned char DiagServiceFlagOrder; + PT2FUNCTION_DEF DiagServiceFunc; +}TYPE_DIAGSERVICEARR; + + +/* diagnostic services class II */ +void diagsrv_read_data_by_identifier(void); +void diagsrv_write_data_by_identifier(void); +void diagsrv_session_control(void); +void diagsrv_io_control_by_identifier(void); +void diagsrv_fault_memory_read(void); +void diagsrv_fault_memory_clear(void); +void diagsrv_download_request(void); +void diagsrv_send_data(void); +void diagsrv_security_access(void); +void slave_diagnostic_task(void); +void SoftwareRest(void); +void slave_diagnostic_init(void); +void SaveArray_LINResp(unsigned char * buf); +void ReadArray_LINResp(unsigned char * buf); +unsigned char GetConfiguration(void); +void SetConfiguration(unsigned char c); +void resetDetect(void); +void diagsrv_routine_control(void); +void diagsrv_communication_control(void); +void diagsrv_ECU_reset(void); +void diagsrv_tester_present(void); +void diagsrv_B7(void); + +#endif /* End _DIAGNOSTIC_SERVICE_SLAVE_H_ */ diff --git a/Sources/main.c b/Sources/main.c new file mode 100644 index 0000000..d6818c8 --- /dev/null +++ b/Sources/main.c @@ -0,0 +1,33 @@ +#include /* for EnableInterrupts macro */ +#include "derivative.h" /* include peripheral declarations */ +#include "DMK-BC316-77.h" +#include "diagnostic_service_slave.h" +l_bool FLAG_GO_TO_Sleep=0;//进入睡眠模式标志 +l_bool M_ASK_S_Sleep=0;//主机叫子机进入休眠 +l_bool NO_DATA_Sleep=0;//超时睡眠 +extern unsigned char Toggle_start; +extern unsigned char Toggle_1s; +/* + * Internal Clock 64MHz + * Bus Clock 32MHz + * + */ +void main(void) +{ + CLK_CONFIG(); + Peripheral_Init(); + l_sys_init(); + l_ifc_init(LI0); + ld_init(); + LIN_STANDBY_Mode_wakeup_enable(); + V_12_Ctrl=1; + Toggle_start=2; + Toggle_1s=0; + while(1) + { + Apply_Task(); + Lin_Task(); + slave_diagnostic_task(); + WDog1_Clear(); + } +} diff --git a/lin_cfg/LDF_DMK-BC316-77.ldf b/lin_cfg/LDF_DMK-BC316-77.ldf new file mode 100644 index 0000000..2b6e879 --- /dev/null +++ b/lin_cfg/LDF_DMK-BC316-77.ldf @@ -0,0 +1,169 @@ +/*---------GLOBAL DEFINITIONS-----------*/ +LIN_description_file; +LIN_protocol_version = "2.1"; +LIN_language_version = "2.1"; +LIN_speed = 19.2 kbps; +/* ----------NODE DEFINITIONS---------- */ +Nodes { + Master: + GW, /* Master node name */ + 5.0 ms, /* Time base */ + 0.1 ms; /* Jitter */ + Slaves: + MFL; +} +/* ----------SIGNAL DEFINITIONS---------- */ +Signals { + /* Signal_name : Size, Init, Publisher, Subscriber(s) */ + MFL_Zaehler : 4, 0x0, MFL, GW; + MFL_Toggle : 1, 0x0, MFL, GW; + MFL_Lokalaktiv : 1, 0x0, MFL, GW; + MFL_M_Taste : 1, 0x0, MFL, GW; + void : 1, 0x0, MFL, GW; + MFL_Tastencode_1 : 8, 0x0, MFL, GW; + MFL_Tastencode_2 : 8, 0x0, MFL, GW; + MFL_Eventcode_1 : 4, 0x0, MFL, GW; + MFL_Eventcode_2 : 4, 0x0, MFL, GW; + MFL_Marke : 4, 0x0, MFL, GW; + MFL_Variante : 4, 0x0, MFL, GW; + MFL_Dummy_0_Signal_1 : 8, 0x0, MFL, GW; + MFL_Tip_Down : 1, 0x0, MFL, GW; + MFL_Tip_Up : 1, 0x0, MFL, GW; + MFL_SatModul_links_Err : 1, 0x0, MFL, GW; + MFL_SatModul_rechts_Err : 1, 0x0, MFL, GW; + MFL_Dummy_0_Signal_2 : 1, 0x0, MFL, GW; + MFL_Dummy_0_Signal_3 : 1, 0x0, MFL, GW; + MFL_LR_HZG_Status : 1, 0x0, MFL, GW; + MFL_LR_HZG_Err : 1, 0x0, MFL, GW; + MFL_Signalhorn : 1, 0x0, MFL, GW; + MFL_Signalhorn_Err : 1, 0x0, MFL, GW; + MFL_Tip_links_Err : 1, 0x0, MFL, GW; + MFL_Tip_rechts_Err : 1, 0x0, MFL, GW; + MFL_Taste_links_Err : 1, 0x0, MFL, GW; + MFL_Taste_rechts_Err : 1, 0x0, MFL, GW; + MFL_ECU_Err : 1, 0x0, MFL, GW; + MFL_Response_Err : 1, 0x0, MFL, GW; + DI_KL_58xs : 7, 0x0, GW, MFL; + DI_Emblem : 1, 0x0, GW, MFL; + Klemme_15_MFL : 1, 0x0, GW, MFL; + void_1 : 6, 0x0, GW, MFL; + Dimmung_01_gueltig : 1, 0x0, GW, MFL; + DI_KL_58xt : 7, 0x0, GW, MFL; + void_2 : 1, 0x0, GW, MFL; + void_3 : 7, 0x0, GW, MFL; + P_Mode_MFL : 1, 0x0, GW, MFL; +} +/* ----------DIAGNOSTIC SIGNAL DEFINITIONS---------- */ +Diagnostic_signals { + /* MasterReq Reserved Signals */ + MasterReqB0 : 8, 0; + MasterReqB1 : 8, 0; + MasterReqB2 : 8, 0; + MasterReqB3 : 8, 0; + MasterReqB4 : 8, 0; + MasterReqB5 : 8, 0; + MasterReqB6 : 8, 0; + MasterReqB7 : 8, 0; + /* SlaveResp Reserved Signals */ + SlaveRespB0 : 8, 0; + SlaveRespB1 : 8, 0; + SlaveRespB2 : 8, 0; + SlaveRespB3 : 8, 0; + SlaveRespB4 : 8, 0; + SlaveRespB5 : 8, 0; + SlaveRespB6 : 8, 0; + SlaveRespB7 : 8, 0; +} +/* ----------UNCONDITIONAL FRAME DEFINITIONS---------- */ +Frames { + MFLs_01 : 0xe, MFL , 8 { + MFL_Zaehler , 0; + MFL_Toggle , 4; + MFL_Lokalaktiv , 5; + MFL_M_Taste , 6; + void , 7; + MFL_Tastencode_1 , 8; + MFL_Tastencode_2 , 16; + MFL_Eventcode_1 , 24; + MFL_Eventcode_2 , 28; + MFL_Marke , 32; + MFL_Variante , 36; + MFL_Dummy_0_Signal_1, 40; + MFL_Tip_Down , 48; + MFL_Tip_Up , 49; + MFL_SatModul_links_Err, 50; + MFL_SatModul_rechts_Err, 51; + MFL_Dummy_0_Signal_2, 52; + MFL_Dummy_0_Signal_3, 53; + MFL_LR_HZG_Status , 54; + MFL_LR_HZG_Err , 55; + MFL_Signalhorn , 56; + MFL_Signalhorn_Err , 57; + MFL_Tip_links_Err , 58; + MFL_Tip_rechts_Err , 59; + MFL_Taste_links_Err , 60; + MFL_Taste_rechts_Err, 61; + MFL_ECU_Err , 62; + MFL_Response_Err , 63; + } + MFLe_01 : 0xd, GW , 4 { + DI_KL_58xs , 0; + DI_Emblem , 7; + Klemme_15_MFL , 8; + void_1 , 9; + Dimmung_01_gueltig , 15; + DI_KL_58xt , 16; + void_2 , 23; + void_3 , 24; + P_Mode_MFL , 31; + } +} +/* ----------DIAGNOSTIC FRAME DEFINITIONS---------- */ +Diagnostic_frames { + MasterReq : 0x3c { + MasterReqB0 , 0; + MasterReqB1 , 8; + MasterReqB2 , 16; + MasterReqB3 , 24; + MasterReqB4 , 32; + MasterReqB5 , 40; + MasterReqB6 , 48; + MasterReqB7 , 56; + } + SlaveResp : 0x3d { + SlaveRespB0 , 0; + SlaveRespB1 , 8; + SlaveRespB2 , 16; + SlaveRespB3 , 24; + SlaveRespB4 , 32; + SlaveRespB5 , 40; + SlaveRespB6 , 48; + SlaveRespB7 , 56; + } +} +/* ----------NODE ATTRIBUTE DEFINITIONS---------- */ +Node_attributes { + MFL { + LIN_protocol = "2.1"; /* Node protocol version */ + configured_NAD = 0xa; /* configured NAD of node (1-125) */ + initial_NAD = 0xa; /* initial NAD of node (1-125) */ + product_id = 0xb, 0x1, 0xff; /* Product id */ + response_error = MFL_Response_Err; /* Response error signal */ + P2_min = 50 ms; /* P2_min */ + ST_min = 10 ms; /* ST_min */ + N_As_timeout = 1000 ms; /* N_As timeout value */ + N_Cr_timeout = 1000 ms; /* N_Cr timeout value */ + configurable_frames { + MFLe_01; + MFLs_01; + } + } +} +/* ----------SCHEDULE TABLE DEFINITIONS---------- */ +Schedule_tables { + Dynamic { + MFLs_01 delay 10.0 ms; + MFLe_01 delay 10.0 ms; + } +} + diff --git a/lin_cfg/NPF_DMK-BC316-77.npf b/lin_cfg/NPF_DMK-BC316-77.npf new file mode 100644 index 0000000..d306cae --- /dev/null +++ b/lin_cfg/NPF_DMK-BC316-77.npf @@ -0,0 +1,49 @@ +/*** GENERAL DEFINITION ***/ +LIN_node_config_file; + +/*** MCU DEFINITION ***/ +mcu { + mcu_name = MC9S12ZVL32; + bus_clock = 32000000; /* Frequency bus of system Hz*/ + xgate_support = no; /* Support XGATE Co-Processor */ +} + +/*** LIN HARDWARE DEFINITION ***/ +/* Sci config */ +sci { + S12_sci0{ + sci_channel = 0; + } +} + +/*** NETWORK DEFINITION ***/ +network { + idle_timeout = 4 s; + time_period = 500 us; + diagnostic_class = 3; + resynchronization_support = no; + autobaud_support = no; + max_message_length = 64; + LI0 { + node = MFL; /* Name of node described in LDF (must check consistence with LDF) */ + file = "LDF_DMK-BC316-77.ldf"; /* Name of LDF file */ + device = S12_sci0; + support_sid { + READ_BY_IDENTIFIER = 0xb2; + SAVE_CONFIGURATION = 0xb6; + ASSIGN_FRAME_ID_RANGE = 0xb7; + READ_DATA_BY_IDENTIFIER = 0x22; + SESSION_CONTROL = 0x10; + IO_CONTROL_BY_IDENTIFIER = 0x2f; + FAULT_MEMORY_READ = 0x19; + FAULT_MEMORY_CLEAR = 0x14; + WRITE_DATA_BY_IDENTIFIER = 0x2e; + RoutineControl = 0x31; + CommunicationControl = 0x28; + ECUReset = 0x11; + TesterPresent = 0x3e; + ASSIGN_FRAME_IDENTIFIER = 0xb1; + } + } +} + diff --git a/lin_cfg/lin_cfg.c b/lin_cfg/lin_cfg.c new file mode 100644 index 0000000..5070e71 --- /dev/null +++ b/lin_cfg/lin_cfg.c @@ -0,0 +1,226 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2024 NXP +* ALL RIGHTS RESERVED. +* +****************************************************************************//*! +* +* @file lin_cfg.c +* +* @author FPT Software +* +* @version 1.0 +* +* @date Tue Nov 19 16:50:38 GMT+08:00 2024 +* +* @brief Common LIN configuration, data structure +* +******************************************************************************/ +#include "lin_cfg.h" +#include "lin.h" +/* Mapping interface with hardware */ +const lin_hardware_name lin_virtual_ifc = SCI0; +l_u8 lin_lld_response_buffer[10]; +l_u8 lin_successful_transfer; +l_u8 lin_error_in_response; +l_u8 lin_goto_sleep_flg; +/* Save configuration flag */ +l_u8 lin_save_configuration_flg = 0; +lin_word_status_str lin_word_status; +l_u8 lin_current_pid; + +const l_signal_handle LI0_response_error_signal = LI0_MFL_Response_Err; + +volatile l_u8 buffer_backup_data[8]; + +/* definition and initialization of signal array */ +l_u8 lin_pFrameBuf[LIN_FRAME_BUF_SIZE] = +{ + + + 0x00 /* 0 : 00000000 */ /* start of frame LI0_MFLs_01 */ + + ,0x00 /* 1 : 00000000 */ + ,0x00 /* 2 : 00000000 */ + ,0x00 /* 3 : 00000000 */ + ,0x00 /* 4 : 00000000 */ + ,0x00 /* 5 : 00000000 */ + ,0x00 /* 6 : 00000000 */ + ,0x00 /* 7 : 00000000 */ + + + ,0x00 /* 8 : 00000000 */ /* start of frame LI0_MFLe_01 */ + + ,0x00 /* 9 : 00000000 */ + + ,0x00 /* 10 : 00000000 */ + + ,0x00 /* 11 : 00000000 */ + +}; + +/* definition and initialization of signal array */ +l_u8 lin_flag_handle_tbl[LIN_FLAG_BUF_SIZE] = +{ + + + 0xFF /* 0: start of flag frame LI0_MFLs_01 */ + + ,0xFF /* 1: */ + ,0xFF /* 2: */ + ,0xFF /* 3: */ + + + ,0xFF /* 4: start of flag frame LI0_MFLe_01 */ + + ,0xFF /* 5: */ + +}; + +/*************************** Flag set when signal is updated ******************/ +/* Diagnostic signal */ +l_u8 lin_diag_signal_tbl[16]; +/*****************************event trigger frame*****************************/ + +/********************************** Frame table **********************************/ +const lin_frame_struct lin_frame_tbl[LIN_NUM_OF_FRMS] ={ + + { LIN_FRM_UNCD, 8, LIN_RES_PUB, 0, 0, 4 , (l_u8*)&LI0_response_error_signal } + + ,{ LIN_FRM_UNCD, 4, LIN_RES_SUB, 8, 4, 2 , (l_u8*)0 } + + ,{ LIN_FRM_DIAG, 8, LIN_RES_SUB, 0, 0, 0 , (l_u8*)0 } + + ,{ LIN_FRM_DIAG, 8, LIN_RES_PUB, 0, 0, 0 , (l_u8*)0 } + +}; + +/*********************************** Frame flag Initialization **********************/ +/*************************** Frame flag for send/receive successfully ***************/ +l_bool lin_frame_flag_tbl[LIN_NUM_OF_FRMS] = {0, 0, 0, 0}; +/*************************** Frame flag for updating signal in frame ****************/ +volatile l_u8 lin_frame_updating_flag_tbl[LIN_NUM_OF_FRMS] = {0, 0, 0, 0}; + + +/**************************** Lin configuration Initialization ***********************/ +/* max_response_frame_timeout = round((1.4x(10+Nx10)xTbit)/Tbase_period) + 3 */ + +const l_u16 lin_max_frame_res_timeout_val[8]={ + +6, 7, 8, 8, 12, 13, 15, 16 + +}; + + +l_u8 lin_configuration_RAM[LIN_SIZE_OF_CFG]= {0x00, 0x0E, 0x0D, 0x3C, 0x3D ,0xFF}; + + +const l_u16 lin_configuration_ROM[LIN_SIZE_OF_CFG]= {0x00, 0x0E, 0x0D, 0x3C, 0x3D ,0xFFFF}; + +/***************************************** Node Attribute*****************************************/ + +l_u8 lin_configured_NAD = 0x0A; /**/ +const l_u8 lin_initial_NAD =0x0A; /**/ +const lin_product_id product_id = {0x000B, 0x0001, 0x00FF}; /* {,,} */ +const l_signal_handle response_error = LI0_MFL_Response_Err; +const l_u8 num_frame_have_esignal = 1; /*number of frame contain error signal*/ +const l_u16 lin_response_error_byte_offset[1] = {LIN_BYTE_OFFSET_LI0_MFL_Response_Err}; /*_< response_error>*/ +const l_u8 lin_response_error_bit_offset[1] = {LIN_BIT_OFFSET_LI0_MFL_Response_Err}; /*_< response_error>*/ + + +/************************** TL Layer and Diagnostic: SINGLE interface **************************/ +/* QUEUE information */ +lin_tl_pdu_data tl_tx_queue_data[MAX_QUEUE_SIZE]; /*transmit queue data */ +lin_tl_pdu_data tl_rx_queue_data[MAX_QUEUE_SIZE]; /*receive queue data */ + +lin_transport_layer_queue lin_tl_tx_queue = { +0, /* the first element of queue */ +0, /* the last element of queue */ +LD_QUEUE_EMPTY, /* status of queue */ +0, /* curernt size of queue */ +MAX_QUEUE_SIZE, /* size of queue */ +tl_tx_queue_data, /* data of queue */ +}; + +lin_transport_layer_queue lin_tl_rx_queue = { +0, /* the first element of queue */ +0, /* the last element of queue */ +LD_QUEUE_EMPTY, /* status of queue */ +0, /* curernt size of queue */ +MAX_QUEUE_SIZE, /* size of queue */ +tl_rx_queue_data, /* data of queue */ +}; +/* message information in transmit queue */ +l_u16 tl_rx_msg_index; /* index of message in queue */ +l_u16 tl_rx_msg_size; /* Size of message in queue */ +/* message information in receive queue */ +l_u16 tl_tx_msg_index; /* index of message in queue */ +l_u16 tl_tx_msg_size; /* Size of message in queue */ +lin_last_cfg_result tl_last_cfg_result; /* Status of the last configuration service in LIN 2.0, J2602 */ +l_u8 tl_last_RSID; /* RSID of the last node configuration service */ +l_u8 tl_ld_error_code; /* Error code in case of positive response */ +l_u8 tl_no_of_pdu; /* number of received pdu */ +l_u8 tl_frame_counter; /* frame counter in received message */ +lin_message_timeout_type tl_check_timeout_type; /* timeout type */ +l_u16 tl_check_timeout; /* timeout counter*/ +l_u8 *tl_ident_data; /* To store address of RAM area contain response */ +lin_diagnostic_state tl_diag_state = LD_DIAG_IDLE; +lin_service_status tl_service_status = LD_SERVICE_IDLE ; /* service status */ +lin_message_status tl_receive_msg_status; /* receive message status */ +lin_message_status tl_rx_msg_status; /* cooked rx status */ +lin_message_status tl_tx_msg_status; /* cooked tx status */ + + + + + + + + + + +/****************************Support SID Initialization ***********************/ + +const l_u8 lin_diag_services_supported[_DIAG_NUMBER_OF_SERVICES_] = {0xB2,0xB6,0xB7,0x22,0x10,0x2F,0x19,0x14,0x2E,0x31,0x28,0x11,0x3E,0xB1}; +l_u8 lin_diag_services_flag[_DIAG_NUMBER_OF_SERVICES_] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +l_u8 tl_slaveresp_cnt = 0; +/*This ld_read_by_id_callout() function is used when the master node transmits a read by + identifier request with an identifier in the user defined area (id from 32 to 63). + The driver will call this function when such request is received. + * id: the identifier in the user defined area (32 to 63) + * data: pointer points to a data area with 5 bytes, used to give the positive response. + Driver uses 0xFF "do not care value" for unassigned data values. + Data length in PCI is (1 + number of assigned meaningful data values). + Driver will take as data for all data before and including the last value in the frame that is different from 0xFF. + PCI is 0x02-0x06, so data should have at least one value different from 0xFF. + For example, a response frame, (NAD) (PCI) (0xF2) (0xFF) (0x00) (0xFF) (0xFF) (0xFF), + PCI will be 0x03, since in this case driver takes all data before 0x00 and 0x00 as meaningful data, + and values after 0x00 are do not care value. + * return: LD_NEGATIVE_RESPONSE Respond with a negative response. + LD_POSTIVE_RESPONSE Respond with a positive response. + LD_ID_NO_RESPONSE The slave node will not answer. + */ +l_u8 ld_read_by_id_callout(l_u8 id, l_u8 *data) +{ + l_u8 retval = LD_NEGATIVE_RESPONSE; + /* Following code is an example - Real implementation is application-dependent */ + /* This example implement with ID = 32 - LIN_READ_USR_DEF_MIN */ + if (id == LIN_READ_USR_DEF_MIN) + { + /* id received is user defined 32 */ + data[0] = (l_u8) (id + 1); /* Data user define */ + data[1] = (l_u8) (id + 2); /* Data user define */ + data[2] = (l_u8) (id + 3); /* Data user define */ + data[3] = (l_u8) (id + 4); /* Data user define */ + data[4] = (l_u8) (id + 5); /* Data user define */ + retval = LD_POSITIVE_RESPONSE; + } + else + { + /* other identifiers, respond with negative response by default*/ + } + return retval; +} \ No newline at end of file diff --git a/lin_cfg/lin_cfg.h b/lin_cfg/lin_cfg.h new file mode 100644 index 0000000..e728f51 --- /dev/null +++ b/lin_cfg/lin_cfg.h @@ -0,0 +1,1415 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2024 NXP +* ALL RIGHTS RESERVED. +* +****************************************************************************//*! +* +* @file lin_cfg.h +* +* @author FPT Software +* +* @version 1.0 +* +* @date Tue Nov 19 16:50:38 GMT+08:00 2024 +* +* @brief Hardware configuration file +* +******************************************************************************/ +#ifndef _LIN_CFG_H_ +#define _LIN_CFG_H_ +#include "lin_hw_cfg.h" +/* Define operating mode */ +#define _MASTER_MODE_ 0 +#define _SLAVE_MODE_ 1 +#define LIN_MODE _SLAVE_MODE_ +/* Define protocol version */ +#define PROTOCOL_21 0 +#define PROTOCOL_J2602 1 +#define PROTOCOL_20 2 +#define LIN_PROTOCOL PROTOCOL_21 + +#define SCI_ADDR SCI0_ADDR /* For slave */ + +#define LIN_BAUD_RATE 19200 /*For slave*/ +/**********************************************************************/ +/*************** Diagnostic class selection *****************/ +/**********************************************************************/ +#define _DIAG_CLASS_I_ 0 +#define _DIAG_CLASS_II_ 1 +#define _DIAG_CLASS_III_ 2 + +#define _DIAG_CLASS_SUPPORT_ _DIAG_CLASS_III_ + +#define MAX_LENGTH_SERVICE 64 + +#define MAX_QUEUE_SIZE 11 + + +#define _DIAG_NUMBER_OF_SERVICES_ 14 + +#define DIAGSRV_READ_BY_IDENTIFIER_ORDER 0 + +#define DIAGSRV_SAVE_CONFIGURATION_ORDER 1 + +#define DIAGSRV_ASSIGN_FRAME_ID_RANGE_ORDER 2 + +#define DIAGSRV_READ_DATA_BY_IDENTIFIER_ORDER 3 + +#define DIAGSRV_SESSION_CONTROL_ORDER 4 + +#define DIAGSRV_IO_CONTROL_BY_IDENTIFIER_ORDER 5 + +#define DIAGSRV_FAULT_MEMORY_READ_ORDER 6 + +#define DIAGSRV_FAULT_MEMORY_CLEAR_ORDER 7 + +#define DIAGSRV_WRITE_DATA_BY_IDENTIFIER_ORDER 8 + +#define DIAGSRV_ROUTINECONTROL_ORDER 9 + +#define DIAGSRV_COMMUNICATIONCONTROL_ORDER 10 + +#define DIAGSRV_ECURESET_ORDER 11 + +#define DIAGSRV_TESTERPRESENT_ORDER 12 + +#define DIAGSRV_ASSIGN_FRAME_IDENTIFIER_ORDER 13 + + +/**************** FRAME SUPPORT DEFINITION ******************/ +#define _TL_SINGLE_FRAME_ 0 +#define _TL_MULTI_FRAME_ 1 + +#define _TL_FRAME_SUPPORT_ _TL_MULTI_FRAME_ + +/* frame buffer size */ +#define LIN_FRAME_BUF_SIZE 12 +#define LIN_FLAG_BUF_SIZE 6 + +/**********************************************************************/ +/*************** Interfaces *******************/ +/**********************************************************************/ +typedef enum { + LI0 +}l_ifc_handle; + +/**********************************************************************/ +/*************** Signals *******************/ +/**********************************************************************/ +/* Number of signals */ +#define LIN_NUM_OF_SIGS 37 +/* List of signals */ +typedef enum { + + /* Interface_name = LI0 */ + + LI0_MFL_Zaehler + + , LI0_MFL_Toggle + + , LI0_MFL_Lokalaktiv + + , LI0_MFL_M_Taste + + , LI0_void + + , LI0_MFL_Tastencode_1 + + , LI0_MFL_Tastencode_2 + + , LI0_MFL_Eventcode_1 + + , LI0_MFL_Eventcode_2 + + , LI0_MFL_Marke + + , LI0_MFL_Variante + + , LI0_MFL_Dummy_0_Signal_1 + + , LI0_MFL_Tip_Down + + , LI0_MFL_Tip_Up + + , LI0_MFL_SatModul_links_Err + + , LI0_MFL_SatModul_rechts_Err + + , LI0_MFL_Dummy_0_Signal_2 + + , LI0_MFL_Dummy_0_Signal_3 + + , LI0_MFL_LR_HZG_Status + + , LI0_MFL_LR_HZG_Err + + , LI0_MFL_Signalhorn + + , LI0_MFL_Signalhorn_Err + + , LI0_MFL_Tip_links_Err + + , LI0_MFL_Tip_rechts_Err + + , LI0_MFL_Taste_links_Err + + , LI0_MFL_Taste_rechts_Err + + , LI0_MFL_ECU_Err + + , LI0_MFL_Response_Err + + , LI0_DI_KL_58xs + + , LI0_DI_Emblem + + , LI0_Klemme_15_MFL + + , LI0_void_1 + + , LI0_Dimmung_01_gueltig + + , LI0_DI_KL_58xt + + , LI0_void_2 + + , LI0_void_3 + + , LI0_P_Mode_MFL + +} l_signal_handle; +/**********************************************************************/ +/***************** Frame ********************/ +/**********************************************************************/ +/* Number of frames */ +#define LIN_NUM_OF_FRMS 4 +/* List of frames */ +typedef enum { +/* All frames for master node */ + + /* Interface_name = LI0 */ + + LI0_MFLs_01 + + , LI0_MFLe_01 + + , LI0_MasterReq + + , LI0_SlaveResp + +} l_frame_handle; +/**********************************************************************/ +/*************** Configuration *******************/ +/**********************************************************************/ +/* Size of configuration in ROM and RAM used for interface: LI1 */ +#define LIN_SIZE_OF_CFG 6 +#define LIN_CFG_FRAME_NUM 2 +/********************************************************************* + * global macros + *********************************************************************/ +#define l_bool_rd(SIGNAL) l_bool_rd_##SIGNAL() +#define l_bool_wr(SIGNAL, A) l_bool_wr_##SIGNAL(A) +#define l_u8_rd(SIGNAL) l_u8_rd_##SIGNAL() +#define l_u8_wr(SIGNAL, A) l_u8_wr_##SIGNAL(A) +#define l_u16_rd(SIGNAL) l_u16_rd_##SIGNAL() +#define l_u16_wr(SIGNAL, A) l_u16_wr_##SIGNAL(A) +#define l_bytes_rd(SIGNAL, start, count, data) l_bytes_rd_##SIGNAL(start, count, data) +#define l_bytes_wr(SIGNAL, start, count, data) l_bytes_wr_##SIGNAL(start, count, data) +#define l_flg_tst(FLAG) l_flg_tst_##FLAG() +#define l_flg_clr(FLAG) l_flg_clr_##FLAG() +#define LIN_TEST_BIT(A,B) ((l_bool)((((A) & (1U << (B))) != 0U) ? 1U : 0U)) +#define LIN_SET_BIT(A,B) ((A) |= (l_u8) (1U << (B))) +#define LIN_CLEAR_BIT(A,B) ((A) &= ((l_u8) (~(1U << (B))))) +#define LIN_BYTE_MASK ((l_u16)(((l_u16)((l_u16)1 << CHAR_BIT)) - (l_u16)1)) +#define LIN_FRAME_LEN_MAX 10U + +/* Returns the low byte of the 32-bit value */ +#define BYTE_0(n) ((l_u8)((n) & (l_u8)0xFF)) +/* Returns the second byte of the 32-bit value */ +#define BYTE_1(n) ((l_u8)(BYTE_0((n) >> (l_u8)8))) +/* Returns the third byte of the 32-bit value */ +#define BYTE_2(n) ((l_u8)(BYTE_0((n) >> (l_u8)16))) +/* Returns high byte of the 32-bit value */ +#define BYTE_3(n) ((l_u8)(BYTE_0((n) >> (l_u8)24))) + +/* + * defines for signal access + */ + + + +#define LIN_BYTE_OFFSET_LI0_MFL_Zaehler 0U +#define LIN_BIT_OFFSET_LI0_MFL_Zaehler 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Zaehler 4U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Zaehler 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Zaehler 0U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Toggle 0U +#define LIN_BIT_OFFSET_LI0_MFL_Toggle 4U +#define LIN_SIGNAL_SIZE_LI0_MFL_Toggle 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Toggle 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Toggle 1U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Lokalaktiv 0U +#define LIN_BIT_OFFSET_LI0_MFL_Lokalaktiv 5U +#define LIN_SIGNAL_SIZE_LI0_MFL_Lokalaktiv 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Lokalaktiv 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Lokalaktiv 2U + + +#define LIN_BYTE_OFFSET_LI0_MFL_M_Taste 0U +#define LIN_BIT_OFFSET_LI0_MFL_M_Taste 6U +#define LIN_SIGNAL_SIZE_LI0_MFL_M_Taste 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_M_Taste 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_M_Taste 3U + + +#define LIN_BYTE_OFFSET_LI0_void 0U +#define LIN_BIT_OFFSET_LI0_void 7U +#define LIN_SIGNAL_SIZE_LI0_void 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_void 0U +#define LIN_FLAG_BIT_OFFSET_LI0_void 4U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tastencode_1 1U +#define LIN_BIT_OFFSET_LI0_MFL_Tastencode_1 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tastencode_1 8U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_1 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_1 5U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tastencode_2 2U +#define LIN_BIT_OFFSET_LI0_MFL_Tastencode_2 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tastencode_2 8U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_2 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_2 6U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Eventcode_1 3U +#define LIN_BIT_OFFSET_LI0_MFL_Eventcode_1 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Eventcode_1 4U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_1 0U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_1 7U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Eventcode_2 3U +#define LIN_BIT_OFFSET_LI0_MFL_Eventcode_2 4U +#define LIN_SIGNAL_SIZE_LI0_MFL_Eventcode_2 4U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_2 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_2 0U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Marke 4U +#define LIN_BIT_OFFSET_LI0_MFL_Marke 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Marke 4U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Marke 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Marke 1U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Variante 4U +#define LIN_BIT_OFFSET_LI0_MFL_Variante 4U +#define LIN_SIGNAL_SIZE_LI0_MFL_Variante 4U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Variante 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Variante 2U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1 5U +#define LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_1 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Dummy_0_Signal_1 8U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_1 3U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tip_Down 6U +#define LIN_BIT_OFFSET_LI0_MFL_Tip_Down 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tip_Down 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Down 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Down 4U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tip_Up 6U +#define LIN_BIT_OFFSET_LI0_MFL_Tip_Up 1U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tip_Up 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Up 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Up 5U + + +#define LIN_BYTE_OFFSET_LI0_MFL_SatModul_links_Err 6U +#define LIN_BIT_OFFSET_LI0_MFL_SatModul_links_Err 2U +#define LIN_SIGNAL_SIZE_LI0_MFL_SatModul_links_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_links_Err 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_links_Err 6U + + +#define LIN_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err 6U +#define LIN_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err 3U +#define LIN_SIGNAL_SIZE_LI0_MFL_SatModul_rechts_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err 1U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err 7U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2 6U +#define LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2 4U +#define LIN_SIGNAL_SIZE_LI0_MFL_Dummy_0_Signal_2 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2 0U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3 6U +#define LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3 5U +#define LIN_SIGNAL_SIZE_LI0_MFL_Dummy_0_Signal_3 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3 1U + + +#define LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Status 6U +#define LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Status 6U +#define LIN_SIGNAL_SIZE_LI0_MFL_LR_HZG_Status 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Status 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Status 2U + + +#define LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Err 6U +#define LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Err 7U +#define LIN_SIGNAL_SIZE_LI0_MFL_LR_HZG_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Err 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Err 3U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Signalhorn 7U +#define LIN_BIT_OFFSET_LI0_MFL_Signalhorn 0U +#define LIN_SIGNAL_SIZE_LI0_MFL_Signalhorn 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn 4U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Signalhorn_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Signalhorn_Err 1U +#define LIN_SIGNAL_SIZE_LI0_MFL_Signalhorn_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn_Err 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn_Err 5U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tip_links_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Tip_links_Err 2U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tip_links_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_links_Err 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_links_Err 6U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Tip_rechts_Err 3U +#define LIN_SIGNAL_SIZE_LI0_MFL_Tip_rechts_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err 2U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_rechts_Err 7U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Taste_links_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Taste_links_Err 4U +#define LIN_SIGNAL_SIZE_LI0_MFL_Taste_links_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_links_Err 3U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_links_Err 0U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Taste_rechts_Err 5U +#define LIN_SIGNAL_SIZE_LI0_MFL_Taste_rechts_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err 3U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_rechts_Err 1U + + +#define LIN_BYTE_OFFSET_LI0_MFL_ECU_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_ECU_Err 6U +#define LIN_SIGNAL_SIZE_LI0_MFL_ECU_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_ECU_Err 3U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_ECU_Err 2U + + +#define LIN_BYTE_OFFSET_LI0_MFL_Response_Err 7U +#define LIN_BIT_OFFSET_LI0_MFL_Response_Err 7U +#define LIN_SIGNAL_SIZE_LI0_MFL_Response_Err 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_MFL_Response_Err 3U +#define LIN_FLAG_BIT_OFFSET_LI0_MFL_Response_Err 3U + + +#define LIN_BYTE_OFFSET_LI0_DI_KL_58xs 8U +#define LIN_BIT_OFFSET_LI0_DI_KL_58xs 0U +#define LIN_SIGNAL_SIZE_LI0_DI_KL_58xs 7U +#define LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xs 4U +#define LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xs 0U + + +#define LIN_BYTE_OFFSET_LI0_DI_Emblem 8U +#define LIN_BIT_OFFSET_LI0_DI_Emblem 7U +#define LIN_SIGNAL_SIZE_LI0_DI_Emblem 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_DI_Emblem 4U +#define LIN_FLAG_BIT_OFFSET_LI0_DI_Emblem 1U + + +#define LIN_BYTE_OFFSET_LI0_Klemme_15_MFL 9U +#define LIN_BIT_OFFSET_LI0_Klemme_15_MFL 0U +#define LIN_SIGNAL_SIZE_LI0_Klemme_15_MFL 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_Klemme_15_MFL 4U +#define LIN_FLAG_BIT_OFFSET_LI0_Klemme_15_MFL 2U + + +#define LIN_BYTE_OFFSET_LI0_void_1 9U +#define LIN_BIT_OFFSET_LI0_void_1 1U +#define LIN_SIGNAL_SIZE_LI0_void_1 6U +#define LIN_FLAG_BYTE_OFFSET_LI0_void_1 4U +#define LIN_FLAG_BIT_OFFSET_LI0_void_1 3U + + +#define LIN_BYTE_OFFSET_LI0_Dimmung_01_gueltig 9U +#define LIN_BIT_OFFSET_LI0_Dimmung_01_gueltig 7U +#define LIN_SIGNAL_SIZE_LI0_Dimmung_01_gueltig 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_Dimmung_01_gueltig 4U +#define LIN_FLAG_BIT_OFFSET_LI0_Dimmung_01_gueltig 4U + + +#define LIN_BYTE_OFFSET_LI0_DI_KL_58xt 10U +#define LIN_BIT_OFFSET_LI0_DI_KL_58xt 0U +#define LIN_SIGNAL_SIZE_LI0_DI_KL_58xt 7U +#define LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xt 4U +#define LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xt 5U + + +#define LIN_BYTE_OFFSET_LI0_void_2 10U +#define LIN_BIT_OFFSET_LI0_void_2 7U +#define LIN_SIGNAL_SIZE_LI0_void_2 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_void_2 4U +#define LIN_FLAG_BIT_OFFSET_LI0_void_2 6U + + +#define LIN_BYTE_OFFSET_LI0_void_3 11U +#define LIN_BIT_OFFSET_LI0_void_3 0U +#define LIN_SIGNAL_SIZE_LI0_void_3 7U +#define LIN_FLAG_BYTE_OFFSET_LI0_void_3 4U +#define LIN_FLAG_BIT_OFFSET_LI0_void_3 7U + + +#define LIN_BYTE_OFFSET_LI0_P_Mode_MFL 11U +#define LIN_BIT_OFFSET_LI0_P_Mode_MFL 7U +#define LIN_SIGNAL_SIZE_LI0_P_Mode_MFL 1U +#define LIN_FLAG_BYTE_OFFSET_LI0_P_Mode_MFL 5U +#define LIN_FLAG_BIT_OFFSET_LI0_P_Mode_MFL 0U + + + + +#define LIN_FLAG_BYTE_OFFSET_LI0_MFLs_01 0 +#define LIN_FLAG_BIT_OFFSET_LI0_MFLs_01 0 + +#define LIN_FLAG_BYTE_OFFSET_LI0_MFLe_01 4 +#define LIN_FLAG_BIT_OFFSET_LI0_MFLe_01 0 + + +/**********************************************************************/ +/*************** Static API Functions *******************/ +/**********************************************************************/ +/* + * the static signal access macros + */ + + + +/* static access macros for signal LI0_MFL_Zaehler */ + +#define l_u8_rd_LI0_MFL_Zaehler() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Zaehler]) >> 0U) & 0x0fU)) + + +#define l_u8_wr_LI0_MFL_Zaehler(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Zaehler] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Zaehler] & 0xf0U) | \ + (((A) << 0U) & 0x0fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Zaehler],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Zaehler); \ + } + + +/* static access macros for signal LI0_MFL_Toggle */ + + +#define l_bool_rd_LI0_MFL_Toggle() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Toggle], \ + LIN_BIT_OFFSET_LI0_MFL_Toggle)) + +#define l_bool_wr_LI0_MFL_Toggle(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Toggle], \ + LIN_BIT_OFFSET_LI0_MFL_Toggle)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Toggle], \ + LIN_BIT_OFFSET_LI0_MFL_Toggle));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Toggle],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Toggle);} +/* static access macros for signal LI0_MFL_Lokalaktiv */ + + +#define l_bool_rd_LI0_MFL_Lokalaktiv() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Lokalaktiv], \ + LIN_BIT_OFFSET_LI0_MFL_Lokalaktiv)) + +#define l_bool_wr_LI0_MFL_Lokalaktiv(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Lokalaktiv], \ + LIN_BIT_OFFSET_LI0_MFL_Lokalaktiv)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Lokalaktiv], \ + LIN_BIT_OFFSET_LI0_MFL_Lokalaktiv));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Lokalaktiv],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Lokalaktiv);} +/* static access macros for signal LI0_MFL_M_Taste */ + + +#define l_bool_rd_LI0_MFL_M_Taste() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_M_Taste], \ + LIN_BIT_OFFSET_LI0_MFL_M_Taste)) + +#define l_bool_wr_LI0_MFL_M_Taste(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_M_Taste], \ + LIN_BIT_OFFSET_LI0_MFL_M_Taste)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_M_Taste], \ + LIN_BIT_OFFSET_LI0_MFL_M_Taste));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_M_Taste],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_M_Taste);} +/* static access macros for signal LI0_void */ + + +#define l_bool_rd_LI0_void() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void], \ + LIN_BIT_OFFSET_LI0_void)) + +#define l_bool_wr_LI0_void(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void], \ + LIN_BIT_OFFSET_LI0_void)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void], \ + LIN_BIT_OFFSET_LI0_void));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void],\ + LIN_FLAG_BIT_OFFSET_LI0_void);} + +/* static access macros for signal LI0_MFL_Tastencode_1 */ + +#define l_u8_rd_LI0_MFL_Tastencode_1() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_1]) >> 0U) & 0xffU)) + + +#define l_u8_wr_LI0_MFL_Tastencode_1(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_1] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_1] & 0x00U) | \ + (((A) << 0U) & 0xffU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_1); \ + } + + + +/* static access macros for signal LI0_MFL_Tastencode_2 */ + +#define l_u8_rd_LI0_MFL_Tastencode_2() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_2]) >> 0U) & 0xffU)) + + +#define l_u8_wr_LI0_MFL_Tastencode_2(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_2] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tastencode_2] & 0x00U) | \ + (((A) << 0U) & 0xffU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_2); \ + } + + + +/* static access macros for signal LI0_MFL_Eventcode_1 */ + +#define l_u8_rd_LI0_MFL_Eventcode_1() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_1]) >> 0U) & 0x0fU)) + + +#define l_u8_wr_LI0_MFL_Eventcode_1(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_1] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_1] & 0xf0U) | \ + (((A) << 0U) & 0x0fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_1); \ + } + + + +/* static access macros for signal LI0_MFL_Eventcode_2 */ + +#define l_u8_rd_LI0_MFL_Eventcode_2() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_2]) >> 4U) & 0x0fU)) + + +#define l_u8_wr_LI0_MFL_Eventcode_2(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_2] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Eventcode_2] & 0x0fU) | \ + (((A) << 4U) & 0xf0U)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_2); \ + } + + + +/* static access macros for signal LI0_MFL_Marke */ + +#define l_u8_rd_LI0_MFL_Marke() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Marke]) >> 0U) & 0x0fU)) + + +#define l_u8_wr_LI0_MFL_Marke(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Marke] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Marke] & 0xf0U) | \ + (((A) << 0U) & 0x0fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Marke],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Marke); \ + } + + + +/* static access macros for signal LI0_MFL_Variante */ + +#define l_u8_rd_LI0_MFL_Variante() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Variante]) >> 4U) & 0x0fU)) + + +#define l_u8_wr_LI0_MFL_Variante(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Variante] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Variante] & 0x0fU) | \ + (((A) << 4U) & 0xf0U)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Variante],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Variante); \ + } + + + +/* static access macros for signal LI0_MFL_Dummy_0_Signal_1 */ + +#define l_u8_rd_LI0_MFL_Dummy_0_Signal_1() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1]) >> 0U) & 0xffU)) + + +#define l_u8_wr_LI0_MFL_Dummy_0_Signal_1(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1] & 0x00U) | \ + (((A) << 0U) & 0xffU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_1); \ + } + + +/* static access macros for signal LI0_MFL_Tip_Down */ + + +#define l_bool_rd_LI0_MFL_Tip_Down() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Down], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Down)) + +#define l_bool_wr_LI0_MFL_Tip_Down(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Down], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Down)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Down], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Down));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Down],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Down);} +/* static access macros for signal LI0_MFL_Tip_Up */ + + +#define l_bool_rd_LI0_MFL_Tip_Up() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Up], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Up)) + +#define l_bool_wr_LI0_MFL_Tip_Up(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Up], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Up)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_Up], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_Up));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Up],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Up);} +/* static access macros for signal LI0_MFL_SatModul_links_Err */ + + +#define l_bool_rd_LI0_MFL_SatModul_links_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_links_Err)) + +#define l_bool_wr_LI0_MFL_SatModul_links_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_links_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_links_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_links_Err);} +/* static access macros for signal LI0_MFL_SatModul_rechts_Err */ + + +#define l_bool_rd_LI0_MFL_SatModul_rechts_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err)) + +#define l_bool_wr_LI0_MFL_SatModul_rechts_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err);} +/* static access macros for signal LI0_MFL_Dummy_0_Signal_2 */ + + +#define l_bool_rd_LI0_MFL_Dummy_0_Signal_2() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2)) + +#define l_bool_wr_LI0_MFL_Dummy_0_Signal_2(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2);} +/* static access macros for signal LI0_MFL_Dummy_0_Signal_3 */ + + +#define l_bool_rd_LI0_MFL_Dummy_0_Signal_3() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3)) + +#define l_bool_wr_LI0_MFL_Dummy_0_Signal_3(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3], \ + LIN_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3);} +/* static access macros for signal LI0_MFL_LR_HZG_Status */ + + +#define l_bool_rd_LI0_MFL_LR_HZG_Status() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Status], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Status)) + +#define l_bool_wr_LI0_MFL_LR_HZG_Status(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Status], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Status)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Status], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Status));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Status],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Status);} +/* static access macros for signal LI0_MFL_LR_HZG_Err */ + + +#define l_bool_rd_LI0_MFL_LR_HZG_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Err], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Err)) + +#define l_bool_wr_LI0_MFL_LR_HZG_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Err], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_LR_HZG_Err], \ + LIN_BIT_OFFSET_LI0_MFL_LR_HZG_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Err);} +/* static access macros for signal LI0_MFL_Signalhorn */ + + +#define l_bool_rd_LI0_MFL_Signalhorn() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn)) + +#define l_bool_wr_LI0_MFL_Signalhorn(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn);} +/* static access macros for signal LI0_MFL_Signalhorn_Err */ + + +#define l_bool_rd_LI0_MFL_Signalhorn_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn_Err)) + +#define l_bool_wr_LI0_MFL_Signalhorn_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Signalhorn_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Signalhorn_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn_Err);} +/* static access macros for signal LI0_MFL_Tip_links_Err */ + + +#define l_bool_rd_LI0_MFL_Tip_links_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_links_Err)) + +#define l_bool_wr_LI0_MFL_Tip_links_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_links_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_links_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_links_Err);} +/* static access macros for signal LI0_MFL_Tip_rechts_Err */ + + +#define l_bool_rd_LI0_MFL_Tip_rechts_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_rechts_Err)) + +#define l_bool_wr_LI0_MFL_Tip_rechts_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_rechts_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Tip_rechts_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_rechts_Err);} +/* static access macros for signal LI0_MFL_Taste_links_Err */ + + +#define l_bool_rd_LI0_MFL_Taste_links_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_links_Err)) + +#define l_bool_wr_LI0_MFL_Taste_links_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_links_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_links_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_links_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_links_Err);} +/* static access macros for signal LI0_MFL_Taste_rechts_Err */ + + +#define l_bool_rd_LI0_MFL_Taste_rechts_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_rechts_Err)) + +#define l_bool_wr_LI0_MFL_Taste_rechts_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_rechts_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Taste_rechts_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_rechts_Err);} +/* static access macros for signal LI0_MFL_ECU_Err */ + + +#define l_bool_rd_LI0_MFL_ECU_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_ECU_Err], \ + LIN_BIT_OFFSET_LI0_MFL_ECU_Err)) + +#define l_bool_wr_LI0_MFL_ECU_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_ECU_Err], \ + LIN_BIT_OFFSET_LI0_MFL_ECU_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_ECU_Err], \ + LIN_BIT_OFFSET_LI0_MFL_ECU_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_ECU_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_ECU_Err);} +/* static access macros for signal LI0_MFL_Response_Err */ + + +#define l_bool_rd_LI0_MFL_Response_Err() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Response_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Response_Err)) + +#define l_bool_wr_LI0_MFL_Response_Err(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Response_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Response_Err)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_MFL_Response_Err], \ + LIN_BIT_OFFSET_LI0_MFL_Response_Err));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Response_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Response_Err);} + +/* static access macros for signal LI0_DI_KL_58xs */ + +#define l_u8_rd_LI0_DI_KL_58xs() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xs]) >> 0U) & 0x7fU)) + + +#define l_u8_wr_LI0_DI_KL_58xs(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xs] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xs] & 0x80U) | \ + (((A) << 0U) & 0x7fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xs],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xs); \ + } + + +/* static access macros for signal LI0_DI_Emblem */ + + +#define l_bool_rd_LI0_DI_Emblem() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_Emblem], \ + LIN_BIT_OFFSET_LI0_DI_Emblem)) + +#define l_bool_wr_LI0_DI_Emblem(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_Emblem], \ + LIN_BIT_OFFSET_LI0_DI_Emblem)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_Emblem], \ + LIN_BIT_OFFSET_LI0_DI_Emblem));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_Emblem],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_Emblem);} +/* static access macros for signal LI0_Klemme_15_MFL */ + + +#define l_bool_rd_LI0_Klemme_15_MFL() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Klemme_15_MFL], \ + LIN_BIT_OFFSET_LI0_Klemme_15_MFL)) + +#define l_bool_wr_LI0_Klemme_15_MFL(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Klemme_15_MFL], \ + LIN_BIT_OFFSET_LI0_Klemme_15_MFL)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Klemme_15_MFL], \ + LIN_BIT_OFFSET_LI0_Klemme_15_MFL));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Klemme_15_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_Klemme_15_MFL);} + +/* static access macros for signal LI0_void_1 */ + +#define l_u8_rd_LI0_void_1() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_1]) >> 1U) & 0x3fU)) + + +#define l_u8_wr_LI0_void_1(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_1] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_1] & 0x81U) | \ + (((A) << 1U) & 0x7eU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_1],\ + LIN_FLAG_BIT_OFFSET_LI0_void_1); \ + } + + +/* static access macros for signal LI0_Dimmung_01_gueltig */ + + +#define l_bool_rd_LI0_Dimmung_01_gueltig() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Dimmung_01_gueltig], \ + LIN_BIT_OFFSET_LI0_Dimmung_01_gueltig)) + +#define l_bool_wr_LI0_Dimmung_01_gueltig(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Dimmung_01_gueltig], \ + LIN_BIT_OFFSET_LI0_Dimmung_01_gueltig)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_Dimmung_01_gueltig], \ + LIN_BIT_OFFSET_LI0_Dimmung_01_gueltig));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Dimmung_01_gueltig],\ + LIN_FLAG_BIT_OFFSET_LI0_Dimmung_01_gueltig);} + +/* static access macros for signal LI0_DI_KL_58xt */ + +#define l_u8_rd_LI0_DI_KL_58xt() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xt]) >> 0U) & 0x7fU)) + + +#define l_u8_wr_LI0_DI_KL_58xt(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xt] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_DI_KL_58xt] & 0x80U) | \ + (((A) << 0U) & 0x7fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xt],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xt); \ + } + + +/* static access macros for signal LI0_void_2 */ + + +#define l_bool_rd_LI0_void_2() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_2], \ + LIN_BIT_OFFSET_LI0_void_2)) + +#define l_bool_wr_LI0_void_2(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_2], \ + LIN_BIT_OFFSET_LI0_void_2)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_2], \ + LIN_BIT_OFFSET_LI0_void_2));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_2],\ + LIN_FLAG_BIT_OFFSET_LI0_void_2);} + +/* static access macros for signal LI0_void_3 */ + +#define l_u8_rd_LI0_void_3() \ + ((l_u8) (((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_3]) >> 0U) & 0x7fU)) + + +#define l_u8_wr_LI0_void_3(A) \ + { \ + lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_3] = \ + (l_u8)((lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_void_3] & 0x80U) | \ + (((A) << 0U) & 0x7fU)); \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_3],\ + LIN_FLAG_BIT_OFFSET_LI0_void_3); \ + } + + +/* static access macros for signal LI0_P_Mode_MFL */ + + +#define l_bool_rd_LI0_P_Mode_MFL() \ + (LIN_TEST_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_P_Mode_MFL], \ + LIN_BIT_OFFSET_LI0_P_Mode_MFL)) + +#define l_bool_wr_LI0_P_Mode_MFL(A) \ + {(A) ? \ + (LIN_SET_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_P_Mode_MFL], \ + LIN_BIT_OFFSET_LI0_P_Mode_MFL)):\ + (LIN_CLEAR_BIT(lin_pFrameBuf[LIN_BYTE_OFFSET_LI0_P_Mode_MFL], \ + LIN_BIT_OFFSET_LI0_P_Mode_MFL));\ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_P_Mode_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_P_Mode_MFL);} + + +/* Signal flag APIs */ + +#define l_flg_tst_LI0_MFL_Zaehler_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Zaehler],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Zaehler) +#define l_flg_clr_LI0_MFL_Zaehler_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Zaehler],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Zaehler) + +#define l_flg_tst_LI0_MFL_Toggle_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Toggle],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Toggle) +#define l_flg_clr_LI0_MFL_Toggle_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Toggle],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Toggle) + +#define l_flg_tst_LI0_MFL_Lokalaktiv_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Lokalaktiv],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Lokalaktiv) +#define l_flg_clr_LI0_MFL_Lokalaktiv_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Lokalaktiv],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Lokalaktiv) + +#define l_flg_tst_LI0_MFL_M_Taste_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_M_Taste],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_M_Taste) +#define l_flg_clr_LI0_MFL_M_Taste_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_M_Taste],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_M_Taste) + +#define l_flg_tst_LI0_void_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void],\ + LIN_FLAG_BIT_OFFSET_LI0_void) +#define l_flg_clr_LI0_void_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void],\ + LIN_FLAG_BIT_OFFSET_LI0_void) + +#define l_flg_tst_LI0_MFL_Tastencode_1_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_1) +#define l_flg_clr_LI0_MFL_Tastencode_1_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_1) + +#define l_flg_tst_LI0_MFL_Tastencode_2_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_2) +#define l_flg_clr_LI0_MFL_Tastencode_2_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tastencode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tastencode_2) + +#define l_flg_tst_LI0_MFL_Eventcode_1_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_1) +#define l_flg_clr_LI0_MFL_Eventcode_1_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_1) + +#define l_flg_tst_LI0_MFL_Eventcode_2_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_2) +#define l_flg_clr_LI0_MFL_Eventcode_2_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Eventcode_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Eventcode_2) + +#define l_flg_tst_LI0_MFL_Marke_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Marke],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Marke) +#define l_flg_clr_LI0_MFL_Marke_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Marke],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Marke) + +#define l_flg_tst_LI0_MFL_Variante_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Variante],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Variante) +#define l_flg_clr_LI0_MFL_Variante_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Variante],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Variante) + +#define l_flg_tst_LI0_MFL_Dummy_0_Signal_1_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_1) +#define l_flg_clr_LI0_MFL_Dummy_0_Signal_1_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_1],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_1) + +#define l_flg_tst_LI0_MFL_Tip_Down_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Down],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Down) +#define l_flg_clr_LI0_MFL_Tip_Down_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Down],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Down) + +#define l_flg_tst_LI0_MFL_Tip_Up_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Up],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Up) +#define l_flg_clr_LI0_MFL_Tip_Up_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_Up],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_Up) + +#define l_flg_tst_LI0_MFL_SatModul_links_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_links_Err) +#define l_flg_clr_LI0_MFL_SatModul_links_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_links_Err) + +#define l_flg_tst_LI0_MFL_SatModul_rechts_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err) +#define l_flg_clr_LI0_MFL_SatModul_rechts_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_SatModul_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_SatModul_rechts_Err) + +#define l_flg_tst_LI0_MFL_Dummy_0_Signal_2_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2) +#define l_flg_clr_LI0_MFL_Dummy_0_Signal_2_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_2],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_2) + +#define l_flg_tst_LI0_MFL_Dummy_0_Signal_3_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3) +#define l_flg_clr_LI0_MFL_Dummy_0_Signal_3_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Dummy_0_Signal_3],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Dummy_0_Signal_3) + +#define l_flg_tst_LI0_MFL_LR_HZG_Status_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Status],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Status) +#define l_flg_clr_LI0_MFL_LR_HZG_Status_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Status],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Status) + +#define l_flg_tst_LI0_MFL_LR_HZG_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Err) +#define l_flg_clr_LI0_MFL_LR_HZG_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_LR_HZG_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_LR_HZG_Err) + +#define l_flg_tst_LI0_MFL_Signalhorn_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn) +#define l_flg_clr_LI0_MFL_Signalhorn_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn) + +#define l_flg_tst_LI0_MFL_Signalhorn_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn_Err) +#define l_flg_clr_LI0_MFL_Signalhorn_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Signalhorn_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Signalhorn_Err) + +#define l_flg_tst_LI0_MFL_Tip_links_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_links_Err) +#define l_flg_clr_LI0_MFL_Tip_links_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_links_Err) + +#define l_flg_tst_LI0_MFL_Tip_rechts_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_rechts_Err) +#define l_flg_clr_LI0_MFL_Tip_rechts_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Tip_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Tip_rechts_Err) + +#define l_flg_tst_LI0_MFL_Taste_links_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_links_Err) +#define l_flg_clr_LI0_MFL_Taste_links_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_links_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_links_Err) + +#define l_flg_tst_LI0_MFL_Taste_rechts_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_rechts_Err) +#define l_flg_clr_LI0_MFL_Taste_rechts_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Taste_rechts_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Taste_rechts_Err) + +#define l_flg_tst_LI0_MFL_ECU_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_ECU_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_ECU_Err) +#define l_flg_clr_LI0_MFL_ECU_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_ECU_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_ECU_Err) + +#define l_flg_tst_LI0_MFL_Response_Err_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Response_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Response_Err) +#define l_flg_clr_LI0_MFL_Response_Err_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_MFL_Response_Err],\ + LIN_FLAG_BIT_OFFSET_LI0_MFL_Response_Err) + +#define l_flg_tst_LI0_DI_KL_58xs_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xs],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xs) +#define l_flg_clr_LI0_DI_KL_58xs_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xs],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xs) + +#define l_flg_tst_LI0_DI_Emblem_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_Emblem],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_Emblem) +#define l_flg_clr_LI0_DI_Emblem_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_Emblem],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_Emblem) + +#define l_flg_tst_LI0_Klemme_15_MFL_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Klemme_15_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_Klemme_15_MFL) +#define l_flg_clr_LI0_Klemme_15_MFL_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Klemme_15_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_Klemme_15_MFL) + +#define l_flg_tst_LI0_void_1_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_1],\ + LIN_FLAG_BIT_OFFSET_LI0_void_1) +#define l_flg_clr_LI0_void_1_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_1],\ + LIN_FLAG_BIT_OFFSET_LI0_void_1) + +#define l_flg_tst_LI0_Dimmung_01_gueltig_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Dimmung_01_gueltig],\ + LIN_FLAG_BIT_OFFSET_LI0_Dimmung_01_gueltig) +#define l_flg_clr_LI0_Dimmung_01_gueltig_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_Dimmung_01_gueltig],\ + LIN_FLAG_BIT_OFFSET_LI0_Dimmung_01_gueltig) + +#define l_flg_tst_LI0_DI_KL_58xt_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xt],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xt) +#define l_flg_clr_LI0_DI_KL_58xt_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_DI_KL_58xt],\ + LIN_FLAG_BIT_OFFSET_LI0_DI_KL_58xt) + +#define l_flg_tst_LI0_void_2_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_2],\ + LIN_FLAG_BIT_OFFSET_LI0_void_2) +#define l_flg_clr_LI0_void_2_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_2],\ + LIN_FLAG_BIT_OFFSET_LI0_void_2) + +#define l_flg_tst_LI0_void_3_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_3],\ + LIN_FLAG_BIT_OFFSET_LI0_void_3) +#define l_flg_clr_LI0_void_3_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_void_3],\ + LIN_FLAG_BIT_OFFSET_LI0_void_3) + +#define l_flg_tst_LI0_P_Mode_MFL_flag() \ + LIN_TEST_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_P_Mode_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_P_Mode_MFL) +#define l_flg_clr_LI0_P_Mode_MFL_flag() \ + LIN_CLEAR_BIT(lin_flag_handle_tbl[LIN_FLAG_BYTE_OFFSET_LI0_P_Mode_MFL],\ + LIN_FLAG_BIT_OFFSET_LI0_P_Mode_MFL) + + + +/* Frame flag APIs */ + + /* Interface_name = LI0 */ + + #define l_flg_tst_LI0_MFLs_01_flag() \ + lin_frame_flag_tbl[LI0_MFLs_01] + #define l_flg_clr_LI0_MFLs_01_flag() \ + lin_frame_flag_tbl[LI0_MFLs_01] = 0 + + #define l_flg_tst_LI0_MFLe_01_flag() \ + lin_frame_flag_tbl[LI0_MFLe_01] + #define l_flg_clr_LI0_MFLe_01_flag() \ + lin_frame_flag_tbl[LI0_MFLe_01] = 0 + + #define l_flg_tst_LI0_MasterReq_flag() \ + lin_frame_flag_tbl[LI0_MasterReq] + #define l_flg_clr_LI0_MasterReq_flag() \ + lin_frame_flag_tbl[LI0_MasterReq] = 0 + + #define l_flg_tst_LI0_SlaveResp_flag() \ + lin_frame_flag_tbl[LI0_SlaveResp] + #define l_flg_clr_LI0_SlaveResp_flag() \ + lin_frame_flag_tbl[LI0_SlaveResp] = 0 + + + +/* INTERFACE MANAGEMENT */ + +#define l_ifc_init_LI0() l_ifc_init(LI0) + + + +#define l_ifc_wake_up_LI0() l_ifc_wake_up(LI0) + + + +#define l_ifc_rx_LI0() l_ifc_rx(LI0) + + + +#define l_ifc_tx_LI0() l_ifc_tx(LI0) + + + +#define l_ifc_aux_LI0() l_ifc_aux(LI0) + + + +#define l_ifc_read_status_LI0() l_ifc_read_status(LI0) + + +#endif /* _LIN_CFG_H_ */ \ No newline at end of file diff --git a/lin_cfg/lin_hw_cfg.h b/lin_cfg/lin_hw_cfg.h new file mode 100644 index 0000000..1dea675 --- /dev/null +++ b/lin_cfg/lin_hw_cfg.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* +* Freescale Semiconductor Inc. +* (c) Copyright 2013-2016 Freescale Semiconductor, Inc. +* Copyright 2016-2024 NXP +* ALL RIGHTS RESERVED. +* +****************************************************************************//*! +* +* @file lin_hw_cfg.h +* +* @author FPT Software +* +* @version 1.0 +* +* @date Tue Nov 19 16:50:38 GMT+08:00 2024 +* +* @brief Hardware configuration file +* +******************************************************************************/ +#ifndef _LIN_HW_CFG_H +#define _LIN_HW_CFG_H +#include + +typedef enum { + SCI0, + SCI1, + SCI2, + SCI3, + SCI4, + SCI5, + GPIO, + SLIC +} lin_hardware_name; + + +/* MCU type definition */ +#define _S08_ 0 +#define _S12_ 1 +#define _S12X_ 2 +#define _K_ 3 + +#define SCI_V2 0 +#define SCI_V4 1 +#define SCI_V5 2 +#define SCI_V6 3 + +/* SCI version */ +#define SCI_VERSION SCI_V6 + +/* Type of MCU */ +#define _MCU_ _S12_ + +/* Resynchronization support */ +#define __RESYN_EN 0 + +/* Autobaud support */ +#define AUTOBAUD 0 + +/* Interface type that MCU uses */ +#define XGATE_SUPPORT 0 +#define _LIN_XGATE_ 0 +#define _LIN_SCI_ 1 +#define _LIN_UART_ 0 +#define _LIN_SLIC_ 0 +#define _LIN_GPIO_ 0 +/*********** SCI HARDWARE SECTION *********/ +#define NUM_OF_SCI_CHANNEL 2 + +/* SCI Base Register definition */ +#define SCI0_ADDR 0x0700 +#define SCI1_ADDR 0x0710 + +/* Use SCI Channel */ +#define _SCI0_ 1 +#define _SCI1_ 0 +#define _SCI2_ 0 +#define _SCI3_ 0 +#define _SCI4_ 0 +#define _SCI5_ 0 + + + +/* MCU bus frequency */ +#define MCU_BUS_FREQ 32000000 + +/* Default interrupt period of the timer for LIN is TIME_BASE_PERIOD micro seconds */ +#define TIME_BASE_PERIOD 500 + +/* max idle timeout for all networks = idle_timeout_value*1000000/time_base_period */ +#define _MAX_IDLE_TIMEOUT_ 8000 /* idle_timeout_value = 4s */ +#endif \ No newline at end of file