From ab0a8272e5cb4ceba199ce3cc44cb75e6a19d070 Mon Sep 17 00:00:00 2001
From: sunbeam <fcb1995@163.com>
Date: Sat, 22 Jun 2024 15:47:38 +0800
Subject: [PATCH] SW0101

---
 .gitignore                    |    4 +
 .vscode/c_cpp_properties.json |   22 +
 .vscode/settings.json         |   13 +
 K80.mtpj                      | 4146 +++++++++++++++++++++++++++++++++
 K80.rcpe                      | 1340 +++++++++++
 OUTPUT/K53L_SW0101.mot        |  136 ++
 OUTPUT/K53R_SW0101.mot        |  136 ++
 OUTPUT/更改履历.txt           |    1 +
 appTask.c                     |  359 +++
 appTask.h                     |   18 +
 cstart.asm                    |  229 ++
 event.c                       |   46 +
 event.h                       |   18 +
 hdwinit.asm                   |   35 +
 hwCtrl.c                      |  241 ++
 hwCtrl.h                      |   16 +
 iodefine.h                    |  542 +++++
 r_cg_adc.c                    |  138 ++
 r_cg_adc.h                    |  179 ++
 r_cg_adc_user.c               |   79 +
 r_cg_cgc.c                    |   69 +
 r_cg_cgc.h                    |  146 ++
 r_cg_cgc_user.c               |   64 +
 r_cg_macrodriver.h            |   88 +
 r_cg_port.c                   |   71 +
 r_cg_port.h                   |  200 ++
 r_cg_port_user.c              |   51 +
 r_cg_serial.c                 |  210 ++
 r_cg_serial.h                 |  399 ++++
 r_cg_serial_user.c            |  172 ++
 r_cg_timer.c                  |  120 +
 r_cg_timer.h                  |  315 +++
 r_cg_timer_user.c             |   66 +
 r_cg_userdefine.h             |   38 +
 r_cg_wdt.c                    |   74 +
 r_cg_wdt.h                    |   52 +
 r_cg_wdt_user.c               |   51 +
 r_main.c                      |   90 +
 r_systeminit.c                |   86 +
 stkinit.asm                   |   77 +
 40 files changed, 10137 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 .vscode/c_cpp_properties.json
 create mode 100644 .vscode/settings.json
 create mode 100644 K80.mtpj
 create mode 100644 K80.rcpe
 create mode 100644 OUTPUT/K53L_SW0101.mot
 create mode 100644 OUTPUT/K53R_SW0101.mot
 create mode 100644 OUTPUT/更改履历.txt
 create mode 100644 appTask.c
 create mode 100644 appTask.h
 create mode 100644 cstart.asm
 create mode 100644 event.c
 create mode 100644 event.h
 create mode 100644 hdwinit.asm
 create mode 100644 hwCtrl.c
 create mode 100644 hwCtrl.h
 create mode 100644 iodefine.h
 create mode 100644 r_cg_adc.c
 create mode 100644 r_cg_adc.h
 create mode 100644 r_cg_adc_user.c
 create mode 100644 r_cg_cgc.c
 create mode 100644 r_cg_cgc.h
 create mode 100644 r_cg_cgc_user.c
 create mode 100644 r_cg_macrodriver.h
 create mode 100644 r_cg_port.c
 create mode 100644 r_cg_port.h
 create mode 100644 r_cg_port_user.c
 create mode 100644 r_cg_serial.c
 create mode 100644 r_cg_serial.h
 create mode 100644 r_cg_serial_user.c
 create mode 100644 r_cg_timer.c
 create mode 100644 r_cg_timer.h
 create mode 100644 r_cg_timer_user.c
 create mode 100644 r_cg_userdefine.h
 create mode 100644 r_cg_wdt.c
 create mode 100644 r_cg_wdt.h
 create mode 100644 r_cg_wdt_user.c
 create mode 100644 r_main.c
 create mode 100644 r_systeminit.c
 create mode 100644 stkinit.asm

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ac83166
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+DefaultBuild
+/SmartManual Docs
+/*.mtud
+/QualityReport(K80,DefaultBuild).txt
diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..1bafd4f
--- /dev/null
+++ b/.vscode/c_cpp_properties.json
@@ -0,0 +1,22 @@
+{
+    "configurations": [
+        {
+            "name": "Win32",
+            "includePath": [
+                "${workspaceFolder}/**"
+            ],
+            "defines": [
+                "_DEBUG",
+                "UNICODE",
+                "_UNICODE",
+                "__near= "
+            ],
+            "windowsSdkVersion": "10.0.18362.0",
+            "compilerPath": "C:\\Program Files (x86)\\Microsoft Visual Studio\\2019\\Community\\VC\\Tools\\MSVC\\14.28.29333\\bin\\Hostx64\\x64\\cl.exe",
+            "cStandard": "c17",
+            "cppStandard": "c++17",
+            "intelliSenseMode": "windows-msvc-x64"
+        }
+    ],
+    "version": 4
+}
\ No newline at end of file
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..54210bb
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,13 @@
+{
+    "files.associations": {
+        "r_cg_macrodriver.h": "c",
+        "r_cg_userdefine.h": "c",
+        "r_cg_timer.h": "c",
+        "r_cg_port.h": "c",
+        "event.h": "c",
+        "r_cg_wdt.h": "c",
+        "hwctrl.h": "c",
+        "apptask.h": "c",
+        "r_cg_serial.h": "c"
+    }
+}
\ No newline at end of file
diff --git a/K80.mtpj b/K80.mtpj
new file mode 100644
index 0000000..0824e81
--- /dev/null
+++ b/K80.mtpj
@@ -0,0 +1,4146 @@
+<CubeSuiteProject>
+  <ProductVersion>9.07.00.00</ProductVersion>
+  <Class Guid="68f4a651-b9cd-473b-a595-b00447132ffa">
+    <Instance Guid="00000000-0000-0000-0000-000000000000">
+      <FormatVersion>2.0</FormatVersion>
+      <FileVersion>9.7</FileVersion>
+      <ProjectGuid>11607c7f-5d75-41e0-bfd3-04a1f8133273</ProjectGuid>
+      <ProjectItemGuid>2bb6dc7e-44fd-485c-82d2-308e3c7601d4</ProjectItemGuid>
+      <FileCategoryGuid>b2ecf786-e190-4e61-9fd3-7e096982a1e7</FileCategoryGuid>
+      <Property>fb98844b-2c27-4275-9804-f6e63e204da0</Property>
+      <ActiveProjectGuid>11607c7f-5d75-41e0-bfd3-04a1f8133273</ActiveProjectGuid>
+    </Instance>
+    <Instance Guid="1b750aae-26fa-4d6d-9527-4ce1163412f4">
+      <Name>cstart.asm</Name>
+      <Type>File</Type>
+      <RelativePath>cstart.asm</RelativePath>
+      <TreeImageGuid>f654126d-e7ad-426d-be34-8455271d959b</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="8031a32c-ef62-4564-a76a-95604fd914b8">
+      <Name>stkinit.asm</Name>
+      <Type>File</Type>
+      <RelativePath>stkinit.asm</RelativePath>
+      <TreeImageGuid>f654126d-e7ad-426d-be34-8455271d959b</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="e626c162-10fa-49ca-b0e1-3842ca33ad66">
+      <Name>iodefine.h</Name>
+      <Type>File</Type>
+      <RelativePath>iodefine.h</RelativePath>
+      <TreeImageGuid>03cad1e8-2eb3-4cde-a8a3-982423631122</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="b8348788-df17-4b71-a9fa-eab0f1824fb1">
+      <Name>Code Generator</Name>
+      <Type>Category</Type>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="342c7692-bb86-4f28-b7e5-fc0e022851a8">
+      <Name>appTask.c</Name>
+      <Type>File</Type>
+      <RelativePath>appTask.c</RelativePath>
+      <TreeImageGuid>941832c1-fc3b-4e1b-94e8-01ea17128b42</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="b53083cb-5d88-4085-9e94-4029bb936c85">
+      <Name>event.c</Name>
+      <Type>File</Type>
+      <RelativePath>event.c</RelativePath>
+      <TreeImageGuid>941832c1-fc3b-4e1b-94e8-01ea17128b42</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="47be1d1c-aca3-4427-b0d6-aaf249fc83c8">
+      <Name>hwCtrl.c</Name>
+      <Type>File</Type>
+      <RelativePath>hwCtrl.c</RelativePath>
+      <TreeImageGuid>941832c1-fc3b-4e1b-94e8-01ea17128b42</TreeImageGuid>
+      <ParentItem>b2ecf786-e190-4e61-9fd3-7e096982a1e7</ParentItem>
+    </Instance>
+    <Instance Guid="3a8bdb55-c122-4735-9349-e31bc68b13b1">
+      <Name>r_main.c</Name>
+      <Type>File</Type>
+      <RelativePath>r_main.c</RelativePath>
+      <TreeImageGuid>941832c1-fc3b-4e1b-94e8-01ea17128b42</TreeImageGuid>
+      <ParentItem>b8348788-df17-4b71-a9fa-eab0f1824fb1</ParentItem>
+    </Instance>
+    <Instance Guid="049d9623-1f0c-4448-aed7-b6f05d823294">
+      <Name>r_systeminit.c</Name>
+      <Type>File</Type>
+      <RelativePath>r_systeminit.c</RelativePath>
+      <TreeImageGuid>941832c1-fc3b-4e1b-94e8-01ea17128b42</TreeImageGuid>
+      <ParentItem>b8348788-df17-4b71-a9fa-eab0f1824fb1</ParentItem>
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+    <Instance Guid="278bbbc6-5343-4321-a327-1e64e960d202">
+      <Name>r_cg_cgc.c</Name>
+      <Type>File</Type>
+      <RelativePath>r_cg_cgc.c</RelativePath>
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+    <Instance Guid="17f20166-02fc-4f9d-b2dd-5678606c671f">
+      <Name>r_cg_cgc_user.c</Name>
+      <Type>File</Type>
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+    <Instance Guid="834d3576-6535-4ae9-b3c6-e0076a175256">
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+    <Instance Guid="8f1e6eec-4b7f-4341-b1e8-4926ad613367">
+      <Name>r_cg_serial.c</Name>
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+    <Instance Guid="eb80bee3-e714-4a3e-b8ed-56456ea256a9">
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+      <SourceItemType13>CSource</SourceItemType13>
+      <SourceItemGuid14>d16ded25-28dd-46bb-ae07-8b6312c80600</SourceItemGuid14>
+      <SourceItemType14>CSource</SourceItemType14>
+      <SourceItemGuid15>eb80bee3-e714-4a3e-b8ed-56456ea256a9</SourceItemGuid15>
+      <SourceItemType15>CSource</SourceItemType15>
+      <SourceItemGuid16>ecd17489-356b-4667-a2ea-7262a0474482</SourceItemGuid16>
+      <SourceItemType16>CSource</SourceItemType16>
+      <SourceItemCount>17</SourceItemCount>
+      <LastDeviceChangedCounter>0</LastDeviceChangedCounter>
+    </Instance>
+    <Instance Guid="6bb7060d-7e24-4135-bd9b-7db166417523">
+      <AsmOptionI-DefaultValue />
+      <BuildMode-DefaultValue>DefaultBuild</BuildMode-DefaultValue>
+      <COptionOsize-DefaultValue>Default</COptionOsize-DefaultValue>
+      <GeneralOptionCpu-DefaultValue>S2</GeneralOptionCpu-DefaultValue>
+      <GeneralOptionErrorFile-DefaultValue>False</GeneralOptionErrorFile-DefaultValue>
+      <GeneralOptionInstalledFolder-DefaultValue />
+      <GeneralOptionMirrorArea-DefaultValue>Maa0</GeneralOptionMirrorArea-DefaultValue>
+      <GeneralOptionNoWarningNum-DefaultValue />
+      <GeneralOptionOutput-DefaultValue>LoadModuleFile</GeneralOptionOutput-DefaultValue>
+      <GeneralOptionSimultaneousBuild-DefaultValue>False</GeneralOptionSimultaneousBuild-DefaultValue>
+      <HexOptionOutput-DefaultValue>True</HexOptionOutput-DefaultValue>
+      <LibOptionForm-DefaultValue>LibraryU</LibOptionForm-DefaultValue>
+      <LinkOptionLibrary-DefaultValue />
+      <Memo-DefaultValue />
+      <OutputMessageFormat-DefaultValue>%TargetFiles%</OutputMessageFormat-DefaultValue>
+      <AsmOptionISystem-DefaultValue />
+      <COptionI-DefaultValue />
+      <CompilerVersion-DefaultValue>
+
+0</CompilerVersion-DefaultValue>
+      <FormatBuildOptionList-DefaultValue>%TargetFiles% : %Program% %Options%</FormatBuildOptionList-DefaultValue>
+      <GeneralOptionCref-DefaultValue>False</GeneralOptionCref-DefaultValue>
+      <GeneralOptionEnableParallelBuilding-DefaultValue>True</GeneralOptionEnableParallelBuilding-DefaultValue>
+      <GeneralOptionErrorFolder-DefaultValue>%BuildModeName%</GeneralOptionErrorFolder-DefaultValue>
+      <GeneralOptionUseMda-DefaultValue>mda</GeneralOptionUseMda-DefaultValue>
+      <HexOptionForm-DefaultValue>Stype</HexOptionForm-DefaultValue>
+      <LibOptionOutputFolder-DefaultValue>%BuildModeName%</LibOptionOutputFolder-DefaultValue>
+      <LinkOptionOutputFolder-DefaultValue>%BuildModeName%</LinkOptionOutputFolder-DefaultValue>
+      <LinkOptionSecurityId-DefaultValue>00000000000000000000</LinkOptionSecurityId-DefaultValue>
+      <SetAllBuildModeValue-DefaultValue>False</SetAllBuildModeValue-DefaultValue>
+      <AsmOptionDefine-DefaultValue />
+      <COptionISystem-DefaultValue />
+      <DependencyFileExistCheckingType-DefaultValue>Rebuild</DependencyFileExistCheckingType-DefaultValue>
+      <GeneralOptionErrorFileName-DefaultValue>%ProjectName%.err</GeneralOptionErrorFileName-DefaultValue>
+      <GeneralOptionLimitDevice-DefaultValue>Limit</GeneralOptionLimitDevice-DefaultValue>
+      <GeneralOptionObjPath-DefaultValue>%BuildModeName%</GeneralOptionObjPath-DefaultValue>
+      <HexOptionOutputFolder-DefaultValue>%BuildModeName%</HexOptionOutputFolder-DefaultValue>
+      <LibOptionOutputFileName-DefaultValue>%ProjectName%.lib</LibOptionOutputFileName-DefaultValue>
+      <LinkOptionOutputFileName-DefaultValue>%ProjectName%.abs</LinkOptionOutputFileName-DefaultValue>
+      <TemporaryFolder-DefaultValue />
+      <COptionD-DefaultValue />
+      <HexOptionOutputFileName-DefaultValue>%ProjectName%.mot</HexOptionOutputFileName-DefaultValue>
+      <LibOptionLibraryStandard-DefaultValue>False</LibOptionLibraryStandard-DefaultValue>
+      <LinkOptionLibraryStandard-DefaultValue>True</LinkOptionLibraryStandard-DefaultValue>
+      <PreBuildCommands-DefaultValue />
+      <HexOptionDivisionOutputFile-DefaultValue />
+      <LibOptionLibraryStandard2-DefaultValue>None</LibOptionLibraryStandard2-DefaultValue>
+      <LinkOptionLibraryStandard2-DefaultValue>C90</LinkOptionLibraryStandard2-DefaultValue>
+      <PostBuildCommands-DefaultValue />
+      <GeneralOptionOtherAdditionalOptions-DefaultValue />
+      <LibOptionLibraryRuntime-DefaultValue>False</LibOptionLibraryRuntime-DefaultValue>
+      <LinkOptionLibraryRuntime-DefaultValue>True</LinkOptionLibraryRuntime-DefaultValue>
+      <IsLockedByUser>False</IsLockedByUser>
+      <TimeTagModified--0>-8585485826286815111</TimeTagModified--0>
+      <BuildMode-0>DefaultBuild</BuildMode-0>
+      <Memo-0 />
+      <OutputMessageFormat-0>%TargetFiles%</OutputMessageFormat-0>
+      <FormatBuildOptionList-0>%TargetFiles% : %Program% %Options%</FormatBuildOptionList-0>
+      <SetAllBuildModeValue-0>False</SetAllBuildModeValue-0>
+      <PreBuildCommands-0 />
+      <PostBuildCommands-0 />
+      <GeneralOptionCpu-0>S2</GeneralOptionCpu-0>
+      <GeneralOptionErrorFile-0>False</GeneralOptionErrorFile-0>
+      <GeneralOptionMirrorArea-0>Maa0</GeneralOptionMirrorArea-0>
+      <GeneralOptionNoWarningNum-0 />
+      <GeneralOptionOutput-0>LoadModuleFile</GeneralOptionOutput-0>
+      <GeneralOptionSimultaneousBuild-0>False</GeneralOptionSimultaneousBuild-0>
+      <CompilerVersion-0>
+
+0</CompilerVersion-0>
+      <GeneralOptionCref-0>False</GeneralOptionCref-0>
+      <GeneralOptionEnableParallelBuilding-0>True</GeneralOptionEnableParallelBuilding-0>
+      <GeneralOptionErrorFolder-0>%BuildModeName%</GeneralOptionErrorFolder-0>
+      <GeneralOptionUseMda-0>mda</GeneralOptionUseMda-0>
+      <LinkOptionSecurityId-0>00000000000000000000</LinkOptionSecurityId-0>
+      <DependencyFileExistCheckingType-0>Rebuild</DependencyFileExistCheckingType-0>
+      <GeneralOptionErrorFileName-0>%ProjectName%.err</GeneralOptionErrorFileName-0>
+      <GeneralOptionLimitDevice-0>Limit</GeneralOptionLimitDevice-0>
+      <GeneralOptionObjPath-0>%BuildModeName%</GeneralOptionObjPath-0>
+      <TemporaryFolder-0 />
+      <GeneralOptionOtherAdditionalOptions-0 />
+      <LastCompilerVersion-0>V1.11.00</LastCompilerVersion-0>
+    </Instance>
+    <Instance Guid="86bebc9e-2f6f-4e72-83c8-8883e6cf6d33">
+      <COptionAsmPath-DefaultValue>False</COptionAsmPath-DefaultValue>
+      <COptionChangeMessageError-DefaultValue>No</COptionChangeMessageError-DefaultValue>
+      <COptionCharacterSet-DefaultValue>Auto</COptionCharacterSet-DefaultValue>
+      <COptionConvertCc-DefaultValue>None</COptionConvertCc-DefaultValue>
+      <COptionDblSize-DefaultValue>True</COptionDblSize-DefaultValue>
+      <COptionG-DefaultValue>True</COptionG-DefaultValue>
+      <COptionI-DefaultValue />
+      <COptionLangC-DefaultValue>None</COptionLangC-DefaultValue>
+      <COptionMOrC-DefaultValue>-c</COptionMOrC-DefaultValue>
+      <COptionMemoryModel-DefaultValue>Auto</COptionMemoryModel-DefaultValue>
+      <COptionMisra-DefaultValue>Misra2012</COptionMisra-DefaultValue>
+      <COptionOenhance-DefaultValue>False</COptionOenhance-DefaultValue>
+      <COptionOsize-DefaultValue>Default</COptionOsize-DefaultValue>
+      <COptionPrnPath-DefaultValue>False</COptionPrnPath-DefaultValue>
+      <COptionStackProtector-DefaultValue>None</COptionStackProtector-DefaultValue>
+      <COptionAnsi-DefaultValue>False</COptionAnsi-DefaultValue>
+      <COptionAsmPathValue-DefaultValue>%BuildModeName%</COptionAsmPathValue-DefaultValue>
+      <COptionChangeMessageErrorNumber-DefaultValue />
+      <COptionFarRom-DefaultValue>False</COptionFarRom-DefaultValue>
+      <COptionGLine-DefaultValue>True</COptionGLine-DefaultValue>
+      <COptionISystem-DefaultValue />
+      <COptionMisra2004-DefaultValue>None</COptionMisra2004-DefaultValue>
+      <COptionPreCompileCommands-DefaultValue />
+      <COptionPrnPathValue-DefaultValue>%BuildModeName%</COptionPrnPathValue-DefaultValue>
+      <COptionSignedChar-DefaultValue>None</COptionSignedChar-DefaultValue>
+      <COptionControlFlowIntegrity-DefaultValue>None</COptionControlFlowIntegrity-DefaultValue>
+      <COptionMisra2004RuleFile-DefaultValue />
+      <COptionOdeleteStaticFunc-DefaultValue>None</COptionOdeleteStaticFunc-DefaultValue>
+      <COptionP-DefaultValue>False</COptionP-DefaultValue>
+      <COptionPostCompileCommands-DefaultValue />
+      <COptionPreinclude-DefaultValue />
+      <COptionSignedBitfield-DefaultValue>None</COptionSignedBitfield-DefaultValue>
+      <COptionStrictStd-DefaultValue>False</COptionStrictStd-DefaultValue>
+      <COptionD-DefaultValue />
+      <COptionMisra2004RuleNumberApply-DefaultValue />
+      <COptionOinlineLevel-DefaultValue>FitToOptimization</COptionOinlineLevel-DefaultValue>
+      <COptionOtherAdditionalOptions-DefaultValue />
+      <COptionPack-DefaultValue>False</COptionPack-DefaultValue>
+      <COptionPrepPath-DefaultValue>%BuildModeName%</COptionPrepPath-DefaultValue>
+      <COptionRefsWithoutDeclaration-DefaultValue>False</COptionRefsWithoutDeclaration-DefaultValue>
+      <COptionLargeVariable-DefaultValue>False</COptionLargeVariable-DefaultValue>
+      <COptionMisra2004RuleNumberIgnore-DefaultValue />
+      <COptionOinlineSize-DefaultValue>100</COptionOinlineSize-DefaultValue>
+      <COptionU-DefaultValue />
+      <COptionVolatile-DefaultValue>False</COptionVolatile-DefaultValue>
+      <COptionMisra2004RuleNumberRequiredAdd-DefaultValue />
+      <COptionNestComment-DefaultValue>False</COptionNestComment-DefaultValue>
+      <COptionOpipeline-DefaultValue>None</COptionOpipeline-DefaultValue>
+      <COptionPreprocessComment-DefaultValue>False</COptionPreprocessComment-DefaultValue>
+      <COptionSwitch-DefaultValue>Auto</COptionSwitch-DefaultValue>
+      <COptionMisra2004RuleNumberRequiredRemove-DefaultValue />
+      <COptionOtailCall-DefaultValue>None</COptionOtailCall-DefaultValue>
+      <COptionPreprocessLine-DefaultValue>False</COptionPreprocessLine-DefaultValue>
+      <COptionUnalignedPointerForCA78K0R-DefaultValue>False</COptionUnalignedPointerForCA78K0R-DefaultValue>
+      <COptionMisra2012-DefaultValue>None</COptionMisra2012-DefaultValue>
+      <COptionOintermodule-DefaultValue>None</COptionOintermodule-DefaultValue>
+      <COptionPassSource-DefaultValue>False</COptionPassSource-DefaultValue>
+      <COptionMergeString-DefaultValue>False</COptionMergeString-DefaultValue>
+      <COptionMisra2012RuleFile-DefaultValue />
+      <COptionOaliasAnsi-DefaultValue>False</COptionOaliasAnsi-DefaultValue>
+      <COptionMisra2012RuleNumberApply-DefaultValue />
+      <COptionOsameCode-DefaultValue>False</COptionOsameCode-DefaultValue>
+      <COptionStuffBSS-DefaultValue>False</COptionStuffBSS-DefaultValue>
+      <COptionMisra2012RuleNumberIgnore-DefaultValue />
+      <COptionOsameCode2-DefaultValue>None</COptionOsameCode2-DefaultValue>
+      <COptionStuffData-DefaultValue>False</COptionStuffData-DefaultValue>
+      <COptionMisra2012RuleNumberRequiredAdd-DefaultValue />
+      <COptionObranchChaining-DefaultValue>None</COptionObranchChaining-DefaultValue>
+      <COptionStuffConst-DefaultValue>False</COptionStuffConst-DefaultValue>
+      <COptionInsertNopWithLabel-DefaultValue>False</COptionInsertNopWithLabel-DefaultValue>
+      <COptionMisra2012RuleNumberRequiredRemove-DefaultValue />
+      <COptionOalign-DefaultValue>None</COptionOalign-DefaultValue>
+      <COptionGoptimize-DefaultValue>False</COptionGoptimize-DefaultValue>
+      <COptionIgnoreFilesMisra-DefaultValue />
+      <COptionInsertNopWithLabelParameters-DefaultValue />
+      <COptionCheckLanguageExtension-DefaultValue>False</COptionCheckLanguageExtension-DefaultValue>
+      <COptionMisraIntermodule-DefaultValue>False</COptionMisraIntermodule-DefaultValue>
+      <IsLockedByUser>False</IsLockedByUser>
+      <TimeTagModified--0>-8585485766729747459</TimeTagModified--0>
+      <COptionAsmPath-0>False</COptionAsmPath-0>
+      <COptionChangeMessageError-0>No</COptionChangeMessageError-0>
+      <COptionCharacterSet-0>Auto</COptionCharacterSet-0>
+      <COptionConvertCc-0>None</COptionConvertCc-0>
+      <COptionDblSize-0>True</COptionDblSize-0>
+      <COptionG-0>True</COptionG-0>
+      <COptionI-0>.
+</COptionI-0>
+      <COptionLangC-0>None</COptionLangC-0>
+      <COptionMOrC-0>-c</COptionMOrC-0>
+      <COptionMemoryModel-0>Auto</COptionMemoryModel-0>
+      <COptionMisra-0>Misra2012</COptionMisra-0>
+      <COptionOenhance-0>False</COptionOenhance-0>
+      <COptionOsize-0>Default</COptionOsize-0>
+      <COptionPrnPath-0>False</COptionPrnPath-0>
+      <COptionStackProtector-0>None</COptionStackProtector-0>
+      <COptionAnsi-0>False</COptionAnsi-0>
+      <COptionAsmPathValue-0>%BuildModeName%</COptionAsmPathValue-0>
+      <COptionChangeMessageErrorNumber-0 />
+      <COptionFarRom-0>True</COptionFarRom-0>
+      <COptionGLine-0>True</COptionGLine-0>
+      <COptionISystem-0 />
+      <COptionMisra2004-0>None</COptionMisra2004-0>
+      <COptionPreCompileCommands-0 />
+      <COptionPrnPathValue-0>%BuildModeName%</COptionPrnPathValue-0>
+      <COptionSignedChar-0>None</COptionSignedChar-0>
+      <COptionControlFlowIntegrity-0>None</COptionControlFlowIntegrity-0>
+      <COptionMisra2004RuleFile-0 />
+      <COptionOdeleteStaticFunc-0>None</COptionOdeleteStaticFunc-0>
+      <COptionP-0>False</COptionP-0>
+      <COptionPostCompileCommands-0 />
+      <COptionPreinclude-0 />
+      <COptionSignedBitfield-0>None</COptionSignedBitfield-0>
+      <COptionStrictStd-0>False</COptionStrictStd-0>
+      <COptionD-0 />
+      <COptionMisra2004RuleNumberApply-0 />
+      <COptionOinlineLevel-0>FitToOptimization</COptionOinlineLevel-0>
+      <COptionOtherAdditionalOptions-0 />
+      <COptionPack-0>False</COptionPack-0>
+      <COptionPrepPath-0>%BuildModeName%</COptionPrepPath-0>
+      <COptionRefsWithoutDeclaration-0>False</COptionRefsWithoutDeclaration-0>
+      <COptionLargeVariable-0>False</COptionLargeVariable-0>
+      <COptionMisra2004RuleNumberIgnore-0 />
+      <COptionOinlineSize-0>100</COptionOinlineSize-0>
+      <COptionU-0 />
+      <COptionVolatile-0>False</COptionVolatile-0>
+      <COptionMisra2004RuleNumberRequiredAdd-0 />
+      <COptionNestComment-0>False</COptionNestComment-0>
+      <COptionOpipeline-0>None</COptionOpipeline-0>
+      <COptionPreprocessComment-0>False</COptionPreprocessComment-0>
+      <COptionSwitch-0>Auto</COptionSwitch-0>
+      <COptionMisra2004RuleNumberRequiredRemove-0 />
+      <COptionOtailCall-0>None</COptionOtailCall-0>
+      <COptionPreprocessLine-0>False</COptionPreprocessLine-0>
+      <COptionUnalignedPointerForCA78K0R-0>False</COptionUnalignedPointerForCA78K0R-0>
+      <COptionMisra2012-0>None</COptionMisra2012-0>
+      <COptionOintermodule-0>None</COptionOintermodule-0>
+      <COptionPassSource-0>False</COptionPassSource-0>
+      <COptionMergeString-0>False</COptionMergeString-0>
+      <COptionMisra2012RuleFile-0 />
+      <COptionOaliasAnsi-0>False</COptionOaliasAnsi-0>
+      <COptionMisra2012RuleNumberApply-0 />
+      <COptionOsameCode-0>False</COptionOsameCode-0>
+      <COptionStuffBSS-0>False</COptionStuffBSS-0>
+      <COptionMisra2012RuleNumberIgnore-0 />
+      <COptionOsameCode2-0>None</COptionOsameCode2-0>
+      <COptionStuffData-0>False</COptionStuffData-0>
+      <COptionMisra2012RuleNumberRequiredAdd-0 />
+      <COptionObranchChaining-0>None</COptionObranchChaining-0>
+      <COptionStuffConst-0>False</COptionStuffConst-0>
+      <COptionInsertNopWithLabel-0>False</COptionInsertNopWithLabel-0>
+      <COptionMisra2012RuleNumberRequiredRemove-0 />
+      <COptionOalign-0>None</COptionOalign-0>
+      <COptionGoptimize-0>False</COptionGoptimize-0>
+      <COptionIgnoreFilesMisra-0 />
+      <COptionInsertNopWithLabelParameters-0 />
+      <COptionCheckLanguageExtension-0>False</COptionCheckLanguageExtension-0>
+      <COptionMisraIntermodule-0>False</COptionMisraIntermodule-0>
+    </Instance>
+    <Instance Guid="7a176a9a-9fa0-4b5e-9c2d-94265d8d049f">
+      <AsmOptionCharacterSet-DefaultValue>Auto</AsmOptionCharacterSet-DefaultValue>
+      <AsmOptionConvertAsm-DefaultValue>False</AsmOptionConvertAsm-DefaultValue>
+      <AsmOptionG-DefaultValue>True</AsmOptionG-DefaultValue>
+      <AsmOptionGoptimize-DefaultValue>False</AsmOptionGoptimize-DefaultValue>
+      <AsmOptionI-DefaultValue />
+      <AsmOptionMMOrC-DefaultValue>-c</AsmOptionMMOrC-DefaultValue>
+      <AsmOptionPrnPath-DefaultValue>False</AsmOptionPrnPath-DefaultValue>
+      <AsmOptionBaseNumber-DefaultValue>Prefix</AsmOptionBaseNumber-DefaultValue>
+      <AsmOptionISystem-DefaultValue />
+      <AsmOptionPreAssembleCommands-DefaultValue />
+      <AsmOptionPrnPathValue-DefaultValue>%BuildModeName%</AsmOptionPrnPathValue-DefaultValue>
+      <AsmOptionDefine-DefaultValue />
+      <AsmOptionPostAssembleCommands-DefaultValue />
+      <AsmOptionOtherAdditionalOptions-DefaultValue />
+      <AsmOptionUndefine-DefaultValue />
+      <IsLockedByUser>False</IsLockedByUser>
+      <TimeTagModified--0>-8585485826286795166</TimeTagModified--0>
+      <AsmOptionCharacterSet-0>Auto</AsmOptionCharacterSet-0>
+      <AsmOptionConvertAsm-0>False</AsmOptionConvertAsm-0>
+      <AsmOptionG-0>True</AsmOptionG-0>
+      <AsmOptionGoptimize-0>False</AsmOptionGoptimize-0>
+      <AsmOptionI-0 />
+      <AsmOptionMMOrC-0>-c</AsmOptionMMOrC-0>
+      <AsmOptionPrnPath-0>False</AsmOptionPrnPath-0>
+      <AsmOptionBaseNumber-0>Prefix</AsmOptionBaseNumber-0>
+      <AsmOptionISystem-0 />
+      <AsmOptionPreAssembleCommands-0 />
+      <AsmOptionPrnPathValue-0>%BuildModeName%</AsmOptionPrnPathValue-0>
+      <AsmOptionDefine-0 />
+      <AsmOptionPostAssembleCommands-0 />
+      <AsmOptionOtherAdditionalOptions-0 />
+      <AsmOptionUndefine-0 />
+    </Instance>
+    <Instance Guid="f9345ca1-8ed4-4d53-b89b-d7ee9698cd54">
+      <SMSAsmOptionCharacterSet-DefaultValue>None</SMSAsmOptionCharacterSet-DefaultValue>
+      <SMSAsmOptionI-DefaultValue />
+      <SMSAsmOptionNoWarning-DefaultValue />
+      <SMSAsmOptionPreSMSAssembleCommands-DefaultValue />
+      <SMSAsmOptionD-DefaultValue />
+      <SMSAsmOptionPostSMSAssembleCommands-DefaultValue />
+      <SMSAsmOptionOtherAdditionalOptions-DefaultValue />
+      <SMSAsmOptionU-DefaultValue />
+      <IsLockedByUser>False</IsLockedByUser>
+      <TimeTagModified--0>-8585485826286795166</TimeTagModified--0>
+      <SMSAsmOptionCharacterSet-0>None</SMSAsmOptionCharacterSet-0>
+      <SMSAsmOptionI-0 />
+      <SMSAsmOptionNoWarning-0 />
+      <SMSAsmOptionPreSMSAssembleCommands-0 />
+      <SMSAsmOptionD-0 />
+      <SMSAsmOptionPostSMSAssembleCommands-0 />
+      <SMSAsmOptionOtherAdditionalOptions-0 />
+      <SMSAsmOptionU-0 />
+    </Instance>
+    <Instance Guid="7ec2f657-357c-4418-bb9b-bbb98af0d62c">
+      <LinkOptionAutoSectionLayout-DefaultValue>True</LinkOptionAutoSectionLayout-DefaultValue>
+      <LinkOptionCpu-DefaultValue>False</LinkOptionCpu-DefaultValue>
+      <LinkOptionDebug-DefaultValue>Debug</LinkOptionDebug-DefaultValue>
+      <LinkOptionEntry-DefaultValue>False</LinkOptionEntry-DefaultValue>
+      <LinkOptionInput-DefaultValue />
+      <LinkOptionLibrary-DefaultValue />
+      <LinkOptionListShow-DefaultValue>List</LinkOptionListShow-DefaultValue>
+      <LinkOptionMessage-DefaultValue>False</LinkOptionMessage-DefaultValue>
+      <LinkOptionOcdbg-DefaultValue>True</LinkOptionOcdbg-DefaultValue>
+      <LinkOptionOptimize-DefaultValue>None</LinkOptionOptimize-DefaultValue>
+      <LinkOptionOutputFolder-DefaultValue>%BuildModeName%</LinkOptionOutputFolder-DefaultValue>
+      <LinkOptionStack-DefaultValue>False</LinkOptionStack-DefaultValue>
+      <LinkOptionVfinfo-DefaultValue>False</LinkOptionVfinfo-DefaultValue>
+      <LinkOptionBinary-DefaultValue />
+      <LinkOptionCompress-DefaultValue>False</LinkOptionCompress-DefaultValue>
+      <LinkOptionCpuInformation-DefaultValue />
+      <LinkOptionEntryPoint-DefaultValue />
+      <LinkOptionLibrarySystem-DefaultValue />
+      <LinkOptionMapFileName-DefaultValue>%ProjectName%.map</LinkOptionMapFileName-DefaultValue>
+      <LinkOptionMemory-DefaultValue>False</LinkOptionMemory-DefaultValue>
+      <LinkOptionNoMessageErrorNumber-DefaultValue />
+      <LinkOptionOcdbgValue-DefaultValue />
+      <LinkOptionOptimizeSymbolDelete-DefaultValue>False</LinkOptionOptimizeSymbolDelete-DefaultValue>
+      <LinkOptionOutputFileName-DefaultValue>%ProjectName%.abs</LinkOptionOutputFileName-DefaultValue>
+      <LinkOptionStart-DefaultValue />
+      <LinkOptionVfinfoFolder-DefaultValue>%BuildModeName%</LinkOptionVfinfoFolder-DefaultValue>
+      <LinkOptionCheckDevice-DefaultValue>False</LinkOptionCheckDevice-DefaultValue>
+      <LinkOptionDebugMonitorSetting-DefaultValue>None</LinkOptionDebugMonitorSetting-DefaultValue>
+      <LinkOptionDefine-DefaultValue />
+      <LinkOptionFSymbol-DefaultValue />
+      <LinkOptionHide-DefaultValue>False</LinkOptionHide-DefaultValue>
+      <LinkOptionLibraryStandard-DefaultValue>True</LinkOptionLibraryStandard-DefaultValue>
+      <LinkOptionMsgUnused-DefaultValue>False</LinkOptionMsgUnused-DefaultValue>
+      <LinkOptionOptimizeSameCode-DefaultValue>False</LinkOptionOptimizeSameCode-DefaultValue>
+      <LinkOptionPadding-DefaultValue>False</LinkOptionPadding-DefaultValue>
+      <LinkOptionShowSymbol-DefaultValue>False</LinkOptionShowSymbol-DefaultValue>
+      <LinkOptionTotalSize-DefaultValue>False</LinkOptionTotalSize-DefaultValue>
+      <LinkOptionVfinfoFileName-DefaultValue>%ProjectName%_vfi.h</LinkOptionVfinfoFileName-DefaultValue>
+      <LinkOptionChangeMessageInformation-DefaultValue>None</LinkOptionChangeMessageInformation-DefaultValue>
+      <LinkOptionCheck64KOnly-DefaultValue>False</LinkOptionCheck64KOnly-DefaultValue>
+      <LinkOptionDebugMonitor-DefaultValue>1E00-1FFF</LinkOptionDebugMonitor-DefaultValue>
+      <LinkOptionLibraryStandard2-DefaultValue>C90</LinkOptionLibraryStandard2-DefaultValue>
+      <LinkOptionLogo-DefaultValue>False</LinkOptionLogo-DefaultValue>
+      <LinkOptionRom-DefaultValue>.data=.dataR
+.sdata=.sdataR
+</LinkOptionRom-DefaultValue>
+      <LinkOptionSameSize-DefaultValue>1E</LinkOptionSameSize-DefaultValue>
+      <LinkOptionShowReference-DefaultValue>False</LinkOptionShowReference-DefaultValue>
+      <LinkOptionVectN-DefaultValue />
+      <LinkOptionVfinfoOutputType-DefaultValue />
+      <LinkOptionChangeMessageInformationNumber-DefaultValue />
+      <LinkOptionLibraryLibMalloc-DefaultValue>False</LinkOptionLibraryLibMalloc-DefaultValue>
+      <LinkOptionNoCheckSectionLayout-DefaultValue>False</LinkOptionNoCheckSectionLayout-DefaultValue>
+      <LinkOptionOptimizeBranch-DefaultValue>False</LinkOptionOptimizeBranch-DefaultValue>
+      <LinkOptionPreLinkCommands-DefaultValue />
+      <LinkOptionShowXreference-DefaultValue>False</LinkOptionShowXreference-DefaultValue>
+      <LinkOptionUserOptByte-DefaultValue>True</LinkOptionUserOptByte-DefaultValue>
+      <LinkOptionVect-DefaultValue />
+      <LinkOptionCFI-DefaultValue>False</LinkOptionCFI-DefaultValue>
+      <LinkOptionChangeMessageWarning-DefaultValue>None</LinkOptionChangeMessageWarning-DefaultValue>
+      <LinkOptionLibraryRuntime-DefaultValue>True</LinkOptionLibraryRuntime-DefaultValue>
+      <LinkOptionPostLinkCommands-DefaultValue />
+      <LinkOptionShowTotalSize-DefaultValue>False</LinkOptionShowTotalSize-DefaultValue>
+      <LinkOptionSymbolForbid-DefaultValue />
+      <LinkOptionUserOptByteValue-DefaultValue />
+      <LinkOptionCFIAddFunc-DefaultValue />
+      <LinkOptionChangeMessageWarningNumber-DefaultValue />
+      <LinkOptionOtherAdditionalOptions-DefaultValue />
+      <LinkOptionSameCodeForbid-DefaultValue />
+      <LinkOptionSelf-DefaultValue>None</LinkOptionSelf-DefaultValue>
+      <LinkOptionShowVector-DefaultValue>False</LinkOptionShowVector-DefaultValue>
+      <LinkOptionCFIIgnoreModule-DefaultValue />
+      <LinkOptionChangeMessageError-DefaultValue>None</LinkOptionChangeMessageError-DefaultValue>
+      <LinkOptionOcdTr-DefaultValue>None</LinkOptionOcdTr-DefaultValue>
+      <LinkOptionSectionForbid-DefaultValue />
+      <LinkOptionShowStruct-DefaultValue>False</LinkOptionShowStruct-DefaultValue>
+      <LinkOptionAbsoluteForbid-DefaultValue />
+      <LinkOptionChangeMessageErrorNumber-DefaultValue />
+      <LinkOptionOcdHpi-DefaultValue>None</LinkOptionOcdHpi-DefaultValue>
+      <LinkOptionShowRelocationAttribute-DefaultValue>False</LinkOptionShowRelocationAttribute-DefaultValue>
+      <LinkOptionSplitVect-DefaultValue>False</LinkOptionSplitVect-DefaultValue>
+      <LinkOptionRrm-DefaultValue>False</LinkOptionRrm-DefaultValue>
+      <LinkOptionShowCFI-DefaultValue>False</LinkOptionShowCFI-DefaultValue>
+      <LinkOptionRrmValue-DefaultValue />
+      <IsLockedByUser>False</IsLockedByUser>
+      <TimeTagModified--0>-8584850664709027733</TimeTagModified--0>
+      <LinkOptionAutoSectionLayout-0>True</LinkOptionAutoSectionLayout-0>
+      <LinkOptionCpu-0>False</LinkOptionCpu-0>
+      <LinkOptionDebug-0>Debug</LinkOptionDebug-0>
+      <LinkOptionEntry-0>False</LinkOptionEntry-0>
+      <LinkOptionInput-0 />
+      <LinkOptionLibrary-0 />
+      <LinkOptionListShow-0>List</LinkOptionListShow-0>
+      <LinkOptionMessage-0>False</LinkOptionMessage-0>
+      <LinkOptionOcdbg-0>True</LinkOptionOcdbg-0>
+      <LinkOptionOptimize-0>None</LinkOptionOptimize-0>
+      <LinkOptionOutputFolder-0>%BuildModeName%</LinkOptionOutputFolder-0>
+      <LinkOptionStack-0>False</LinkOptionStack-0>
+      <LinkOptionVfinfo-0>False</LinkOptionVfinfo-0>
+      <LinkOptionBinary-0 />
+      <LinkOptionCompress-0>False</LinkOptionCompress-0>
+      <LinkOptionCpuInformation-0 />
+      <LinkOptionEntryPoint-0 />
+      <LinkOptionLibrarySystem-0 />
+      <LinkOptionMapFileName-0>%ProjectName%.map</LinkOptionMapFileName-0>
+      <LinkOptionMemory-0>False</LinkOptionMemory-0>
+      <LinkOptionNoMessageErrorNumber-0 />
+      <LinkOptionOcdbgValue-0>04</LinkOptionOcdbgValue-0>
+      <LinkOptionOptimizeSymbolDelete-0>False</LinkOptionOptimizeSymbolDelete-0>
+      <LinkOptionOutputFileName-0>%ProjectName%.abs</LinkOptionOutputFileName-0>
+      <LinkOptionStart-0 />
+      <LinkOptionVfinfoFolder-0>%BuildModeName%</LinkOptionVfinfoFolder-0>
+      <LinkOptionCheckDevice-0>False</LinkOptionCheckDevice-0>
+      <LinkOptionDebugMonitorSetting-0>None</LinkOptionDebugMonitorSetting-0>
+      <LinkOptionDefine-0 />
+      <LinkOptionFSymbol-0 />
+      <LinkOptionHide-0>False</LinkOptionHide-0>
+      <LinkOptionLibraryStandard-0>True</LinkOptionLibraryStandard-0>
+      <LinkOptionMsgUnused-0>False</LinkOptionMsgUnused-0>
+      <LinkOptionOptimizeSameCode-0>False</LinkOptionOptimizeSameCode-0>
+      <LinkOptionPadding-0>False</LinkOptionPadding-0>
+      <LinkOptionShowSymbol-0>False</LinkOptionShowSymbol-0>
+      <LinkOptionTotalSize-0>False</LinkOptionTotalSize-0>
+      <LinkOptionVfinfoFileName-0>%ProjectName%_vfi.h</LinkOptionVfinfoFileName-0>
+      <LinkOptionChangeMessageInformation-0>None</LinkOptionChangeMessageInformation-0>
+      <LinkOptionCheck64KOnly-0>False</LinkOptionCheck64KOnly-0>
+      <LinkOptionDebugMonitor-0>1E00-1FFF</LinkOptionDebugMonitor-0>
+      <LinkOptionLibraryStandard2-0>C90</LinkOptionLibraryStandard2-0>
+      <LinkOptionLogo-0>False</LinkOptionLogo-0>
+      <LinkOptionRom-0>.data=.dataR
+.sdata=.sdataR
+</LinkOptionRom-0>
+      <LinkOptionSameSize-0>1E</LinkOptionSameSize-0>
+      <LinkOptionShowReference-0>False</LinkOptionShowReference-0>
+      <LinkOptionVectN-0 />
+      <LinkOptionVfinfoOutputType-0 />
+      <LinkOptionChangeMessageInformationNumber-0 />
+      <LinkOptionLibraryLibMalloc-0>False</LinkOptionLibraryLibMalloc-0>
+      <LinkOptionNoCheckSectionLayout-0>False</LinkOptionNoCheckSectionLayout-0>
+      <LinkOptionOptimizeBranch-0>False</LinkOptionOptimizeBranch-0>
+      <LinkOptionPreLinkCommands-0 />
+      <LinkOptionShowXreference-0>False</LinkOptionShowXreference-0>
+      <LinkOptionUserOptByte-0>True</LinkOptionUserOptByte-0>
+      <LinkOptionVect-0 />
+      <LinkOptionCFI-0>False</LinkOptionCFI-0>
+      <LinkOptionChangeMessageWarning-0>None</LinkOptionChangeMessageWarning-0>
+      <LinkOptionLibraryRuntime-0>True</LinkOptionLibraryRuntime-0>
+      <LinkOptionPostLinkCommands-0 />
+      <LinkOptionShowTotalSize-0>False</LinkOptionShowTotalSize-0>
+      <LinkOptionSymbolForbid-0 />
+      <LinkOptionUserOptByteValue-0>7A47E0</LinkOptionUserOptByteValue-0>
+      <LinkOptionCFIAddFunc-0 />
+      <LinkOptionChangeMessageWarningNumber-0 />
+      <LinkOptionOtherAdditionalOptions-0 />
+      <LinkOptionSameCodeForbid-0 />
+      <LinkOptionSelf-0>None</LinkOptionSelf-0>
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+      <LinkOptionCFIIgnoreModule-0 />
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+      <LinkOptionOcdTr-0>None</LinkOptionOcdTr-0>
+      <LinkOptionSectionForbid-0 />
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+      <LinkOptionAbsoluteForbid-0 />
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+      <HexOptionCheckOutputRomArea-DefaultValue>False</HexOptionCheckOutputRomArea-DefaultValue>
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+      <HexOptionCrcCalculationRange-DefaultValue />
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+&lt;/a1:UltraGridColumn&gt;
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+&lt;Header href="#ref-61"/&gt;
+&lt;Hidden&gt;true&lt;/Hidden&gt;
+&lt;Key id="ref-62"&gt;displayNumber&lt;/Key&gt;
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+&lt;ExcludeFromColumnChooser&gt;1&lt;/ExcludeFromColumnChooser&gt;
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+&lt;CellAppearanceHolder href="#ref-63"/&gt;
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+      <KEY_SAVE_DEVICE_CHANGED_COUNTER>0</KEY_SAVE_DEVICE_CHANGED_COUNTER>
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+      <CompulsorilyEnableDebugToolFunctions>False</CompulsorilyEnableDebugToolFunctions>
+      <IncludePrototypeDeclaration>True</IncludePrototypeDeclaration>
+      <RefreshAtProgramStop>Yes</RefreshAtProgramStop>
+      <UnitOfTime>Nanosecond</UnitOfTime>
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+      <DisplayRegisterForVariableList>False</DisplayRegisterForVariableList>
+      <DisplayFunctionWithoutDefinition>False</DisplayFunctionWithoutDefinition>
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+      <FreeMemoryWhenAllPanelClose>False</FreeMemoryWhenAllPanelClose>
+      <AskWhetherCancelTheResultByOutOfMemory>True</AskWhetherCancelTheResultByOutOfMemory>
+      <AnalyzeFilesSelectionType>FilesNotToAnalyze</AnalyzeFilesSelectionType>
+      <AnalyzeNotTargetFilesCount>0</AnalyzeNotTargetFilesCount>
+      <TraceAnalysisTargetPE>All</TraceAnalysisTargetPE>
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+      <ExportFunctionFileName>%ProjectName%.mtfl</ExportFunctionFileName>
+      <ExportVariableFileName>%ProjectName%.mtvl</ExportVariableFileName>
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+      <AnalysisMethod>RealtimeSampling</AnalysisMethod>
+      <AnalysisChartDataFileName />
+      <StartStopRealTimeSampling>Synchronized</StartStopRealTimeSampling>
+      <AutoAdjustForValueAndTime>AtProgramStop</AutoAdjustForValueAndTime>
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+      <ChartType>LineChart</ChartType>
+      <SpecifyForegroundColorAndBackgroundColor>False</SpecifyForegroundColorAndBackgroundColor>
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+      <Zoom1Color>40ff0a4f</Zoom1Color>
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+    </Instance>
+  </Class>
+  <Class Guid="67508d11-a84e-4956-9db4-04c1eefe9e7a">
+    <Instance Guid="67508d11-a84e-4956-9db4-04c1eefe9e7a">
+      <CodePartToolManager>cb4eebec-2381-4e77-8b34-fa8cd6f33b4c</CodePartToolManager>
+    </Instance>
+  </Class>
+  <Class Guid="cb4eebec-2381-4e77-8b34-fa8cd6f33b4c">
+    <Instance Guid="cb4eebec-2381-4e77-8b34-fa8cd6f33b4c">
+      <CodeGenerator>&lt;RL78G12&gt;
+  &lt;VAR&gt;
+    &lt;fCLK Name="fCLK" Value="24" Comment="4M" Trigger="fCLK"&gt;
+      &lt;Effect&gt;
+        &lt;ADC /&gt;
+        &lt;SAU0 /&gt;
+        &lt;IICA0 /&gt;
+        &lt;TAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fCLK&gt;
+    &lt;fIH Name="fIH" Value="24" Comment="32M" /&gt;
+    &lt;fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"&gt;
+      &lt;Effect&gt;
+        &lt;TAU0 /&gt;
+        &lt;PCLBUZ0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fSUB&gt;
+    &lt;fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"&gt;
+      &lt;Effect&gt;
+        &lt;RTC /&gt;
+        &lt;WDT /&gt;
+        &lt;TAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fIL&gt;
+    &lt;fRTC Name="fRTC" Value="0" Comment="0k" Trigger="fIT"&gt;
+      &lt;Effect&gt;
+        &lt;RTC /&gt;
+        &lt;IT /&gt;
+      &lt;/Effect&gt;
+    &lt;/fRTC&gt;
+    &lt;fMAIN Name="fMAIN" Value="24" Comment="32M" Trigger="fMAIN"&gt;
+      &lt;Effect&gt;
+        &lt;PCLBUZ0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fMAIN&gt;
+    &lt;fINTTM02 Name="fINTTM02" Value="0" Comment="0M" Trigger="INTTM02"&gt;
+      &lt;Effect&gt;
+        &lt;SAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fINTTM02&gt;
+    &lt;fCLKSource Name="fCLKSource" Text="fIH" /&gt;
+    &lt;RESET_pin Chip="RL78G12_20pin,RL78G12_24pin" Name="RESET_pin" Text="false" Trigger="RESET_pin"&gt;
+      &lt;Effect&gt;
+        &lt;PORT /&gt;
+      &lt;/Effect&gt;
+    &lt;/RESET_pin&gt;
+    &lt;VDD_MIN Name="VDD_MIN" Value="2.7" Comment="4.0V" Trigger="VDD"&gt;
+      &lt;Effect&gt;
+        &lt;PCLBUZ0 /&gt;
+        &lt;PCLBUZ1 /&gt;
+        &lt;IICA0 /&gt;
+        &lt;SAU0 /&gt;
+        &lt;SAU1 /&gt;
+      &lt;/Effect&gt;
+    &lt;/VDD_MIN&gt;
+    &lt;VDD_MAX Name="VDD_MAX" Value="3.6" Comment="5.5V" /&gt;
+    &lt;VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"&gt;
+      &lt;Effect&gt;
+        &lt;IICA0 /&gt;
+        &lt;SAU0 /&gt;
+        &lt;SAU1 /&gt;
+        &lt;ADC /&gt;
+      &lt;/Effect&gt;
+    &lt;/VDDValue&gt;
+    &lt;VDD Name="VDD" Text="false" Comment="used" /&gt;
+    &lt;AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="" /&gt;
+    &lt;ADC_ADS_VALUE Name="ADC_ADS_VALUE" Text="" /&gt;
+    &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC00&gt;
+    &lt;IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC01&gt;
+    &lt;IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC10&gt;
+    &lt;IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC11&gt;
+    &lt;IIC20 Name="IIC20" Text="false" Comment="unused" Trigger="IIC20"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC20&gt;
+    &lt;IIC21 Name="IIC21" Text="false" Comment="unused" Trigger="IIC21"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC21&gt;
+    &lt;IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IICA0&gt;
+    &lt;ProjectName Name="PrjName" Text="K80" /&gt;
+    &lt;ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\K80\code\K80_CODE" /&gt;
+    &lt;ProjectKind Name="PrjKind" Text="Project78K0R" /&gt;
+    &lt;DeviceName Name="DeviceName" Fixed="" Text="RL78G12" /&gt;
+    &lt;MCUName Name="MCUName" Text="RL78G12_20pin" /&gt;
+    &lt;ChipName Name="ChipName" Text="R5F10268" /&gt;
+    &lt;ChipID Name="ChipID" Text="R5F10268" /&gt;
+    &lt;MCUType Name="MCUType" Fixed="" Text="RL78" /&gt;
+    &lt;CPUCoreType Name="CPUCoreType" Fixed="" Text="0" /&gt;
+    &lt;Compiler Name="Compiler" Text="CCRL" /&gt;
+    &lt;UseSecurityId Name="GI" Text="0" /&gt;
+    &lt;SecurityId Name="GIValue" Text="00000000000000000000" /&gt;
+    &lt;LinkDirectiveFile Name="D0" Text="lk.dr" /&gt;
+    &lt;OnChipDebugOptionBytes Name="GO" Text="1" /&gt;
+    &lt;OnChipDebugOptionBytesValue Name="GOValue" Text="04" /&gt;
+    &lt;StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="1E00" /&gt;
+    &lt;SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /&gt;
+    &lt;UserOptionBytes Name="GB" Text="1" /&gt;
+    &lt;UserOptionBytesValue Name="GBValue" Text="7A47E0" /&gt;
+    &lt;RAMStartAddress Chip="R5F10268,R5F10278,R5F102A8" Name="RAMStartAddress" Fixed="" Text="000FFC00" /&gt;
+    &lt;RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /&gt;
+    &lt;ROMEndAddress Chip="R5F10268,R5F10278,R5F102A8" Name="ROMEndAddress" Fixed="" Text="00001FFF" /&gt;
+    &lt;MirrorROM Chip="R5F10266, R5F10366,R5F10267, R5F10277, R5F102A7,R5F10367, R5F10377, R5F103A7,R5F10268, R5F10278, R5F102A8,R5F10368, R5F10378, R5F103A8" Name="MirrorROM" Fixed="" Text="0" /&gt;
+    &lt;ADPC_AD Name="ADPC_AD" Value="-1" /&gt;
+    &lt;CodePath Name="CodePath" Text=".\" /&gt;
+    &lt;ReportType Name="ReportType" Text="Html" /&gt;
+    &lt;CreationDateType Name="CreationDateType" Text="OutputDate" /&gt;
+    &lt;GenerateType Name="GenerateType" Text="Merge" /&gt;
+    &lt;APIOutputType Name="APIOutputType" Text="Default" /&gt;
+    &lt;FileRegister Name="FileRegister" Text="Yes" /&gt;
+    &lt;PinReflect Name="PinReflect" Text="Reflected" /&gt;
+    &lt;PIOR0Value Name="PIOR0Value" Text="0" /&gt;
+    &lt;PIOR1Value Name="PIOR1Value" Text="1" /&gt;
+    &lt;PIOR2Value Name="PIOR2Value" Text="0" /&gt;
+    &lt;PIOR3Value Name="PIOR3Value" Text="0" /&gt;
+    &lt;PIOR4Value Name="PIOR4Value" Text="0" /&gt;
+    &lt;PIOR5Value Name="PIOR5Value" Text="0" /&gt;
+    &lt;GDataFlash Name="GDataFlash" Text="2" /&gt;
+    &lt;UseFDL Name="UseFDL" Text="no" /&gt;
+    &lt;DataFlash Name="DataFlash" Text="0" /&gt;
+    &lt;OCDROM Name="OCDROM" Text="Unused" /&gt;
+    &lt;OCDROM_Address Name="OCDROM_Address" Text="00001E00" /&gt;
+    &lt;OCDROM_Length Name="OCDROM_Length" Text="512" /&gt;
+    &lt;HasRRMRam Name="HasRRMRam" Text="" /&gt;
+    &lt;PrjVersion Name="PrjVersion" Text="1.2.0.1" /&gt;
+    &lt;ProductVersion Name="ProductVersion" Text="4.08.05.01" /&gt;
+    &lt;PIOR6Value Name="PIOR6Value" Text="0" /&gt;
+    &lt;TO02_PWM Name="TO02_PWM" Text="false" /&gt;
+    &lt;TO03_PWM Name="TO03_PWM" Text="false" /&gt;
+    &lt;LinkFileName Name="LinkFileName" Text="" /&gt;
+  &lt;/VAR&gt;
+  &lt;DIR&gt;
+    &lt;PIN&gt;
+      &lt;CGC&gt;
+        &lt;X1 Port="P121" Point="-" /&gt;
+        &lt;X2 Port="P122" Point="-" /&gt;
+        &lt;EXCLK Port="P122" Point="I" /&gt;
+        &lt;TOOL0 Port="P40" Point="I/O" /&gt;
+        &lt;_RESET Chip="RL78G12_20pin,RL78G12_24pin" Port="P125" RealName="_RESET" Point="I" /&gt;
+      &lt;/CGC&gt;
+      &lt;PORT&gt;
+        &lt;Port1 Chip="RL78G12_20pin,RL78G12_24pin" DIN="true" Pullup="true"&gt;
+          &lt;P10 Name="P10/ANI16/PCLBUZ0/_SCK00/SCL00" TTL="true" Nch="true" AltFunc="P10" Point="I/O" /&gt;
+          &lt;P11 Name="P11/ANI17/SI00/RXD0/SDA00/TOOLRXD" TTL="true" Nch="true" AltFunc="P11" Point="I/O" /&gt;
+          &lt;P12 Name="P12/ANI18/SO00/TXD0/TOOLTXD" Nch="true" AltFunc="P12" Point="I/O" /&gt;
+          &lt;P13 Name="P13/ANI19/TI00/TO00/INTP2" AltFunc="P13" Point="I/O" /&gt;
+          &lt;P14 Name="P14/ANI20/TI01/TO01/INTP3" AltFunc="P14" Point="I/O" /&gt;
+        &lt;/Port1&gt;
+        &lt;Port2 ADIN="true"&gt;
+          &lt;P20 Name="P20/ANI0/AVREFP" AltFunc="P20" Point="I/O" /&gt;
+          &lt;P21 Name="P21/ANI1/AVREFM" AltFunc="P21" Point="I/O" /&gt;
+          &lt;P22 Name="P22/ANI2" AltFunc="P22" Point="I/O" /&gt;
+          &lt;P23 Name="P23/ANI3" AltFunc="P23" Point="I/O" /&gt;
+        &lt;/Port2&gt;
+        &lt;Port4 Chip="RL78G12_20pin,RL78G12_24pin" Pullup="true"&gt;
+          &lt;P40 Name="P40/KR0/TOOL0" AltFunc="" Point="I/O" /&gt;
+          &lt;P41 Name="P41/ANI22/SO01/SDA01/TI02/TO02/INTP1" DIN="true" Nch="true" AltFunc="P41" Point="I/O" /&gt;
+          &lt;P42 Name="P42/ANI21/_SCK01/SCL01/TI03/TO03" DIN="true" AltFunc="P42" Point="I/O" /&gt;
+        &lt;/Port4&gt;
+        &lt;Port6 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+          &lt;P60 Name="P60/KR4/SCLA0" AltFunc="TXD0" Point="I/O" /&gt;
+          &lt;P61 Name="P61/KR5/SDAA0" AltFunc="RXD0" Point="I/O" /&gt;
+        &lt;/Port6&gt;
+        &lt;Port12 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+          &lt;P121 Name="P121/KR3/X1" AltFunc="" Point="I" /&gt;
+          &lt;P122 Name="P122/KR2/X2/EXCLK" AltFunc="P122" Point="I" /&gt;
+          &lt;P125 Name="P125/KR1/SI01/_RESET" Pullup="true" AltFunc="" Point="I" /&gt;
+        &lt;/Port12&gt;
+        &lt;Port13&gt;
+          &lt;P137 Name="P137/INTP0" AltFunc="P137" Point="I" /&gt;
+        &lt;/Port13&gt;
+      &lt;/PORT&gt;
+      &lt;INTC&gt;
+        &lt;INTP&gt;
+          &lt;INTP0 no="1" Point="I" /&gt;
+          &lt;INTP1 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /&gt;
+          &lt;INTP2 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P13" Point="I" /&gt;
+          &lt;INTP3 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P14" Point="I" /&gt;
+        &lt;/INTP&gt;
+        &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+          &lt;KR0 Port="P40" Point="I" /&gt;
+          &lt;KR1 Port="P125" Point="I" /&gt;
+          &lt;KR2 Port="P122" Point="I" /&gt;
+          &lt;KR3 Port="P121" Point="I" /&gt;
+          &lt;KR4 Port="P60" Point="I" /&gt;
+          &lt;KR5 Port="P61" Point="I" /&gt;
+        &lt;/KEY&gt;
+      &lt;/INTC&gt;
+      &lt;ADC&gt;
+        &lt;ANI0 Port="P20" Point="I" /&gt;
+        &lt;ANI1 Port="P21" Point="I" /&gt;
+        &lt;ANI2 Port="P22" Point="I" /&gt;
+        &lt;ANI3 Port="P23" Point="I" /&gt;
+        &lt;ANI16 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="I" /&gt;
+        &lt;ANI17 Chip="RL78G12_20pin,RL78G12_24pin" Port="P11" Point="I" /&gt;
+        &lt;ANI18 Chip="RL78G12_20pin,RL78G12_24pin" Port="P12" Point="I" /&gt;
+        &lt;ANI19 Chip="RL78G12_20pin,RL78G12_24pin" Port="P13" Point="I" /&gt;
+        &lt;ANI20 Chip="RL78G12_20pin,RL78G12_24pin" Port="P14" Point="I" /&gt;
+        &lt;ANI21 Chip="RL78G12_20pin,RL78G12_24pin" Port="P42" Point="I" /&gt;
+        &lt;ANI22 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /&gt;
+        &lt;AVREFP Port="P20" Point="I" /&gt;
+        &lt;AVREFM Port="P21" Point="I" /&gt;
+        &lt;ANALOG_0 Port="P20" RealName="ANI0/AVREFP" Point="I" /&gt;
+        &lt;ANALOG_1 Port="P21" RealName="ANI1/AVREFM" Point="I" /&gt;
+        &lt;ANALOG_2 Port="P22" RealName="ANI2" Point="I" /&gt;
+        &lt;ANALOG_3 Port="P23" RealName="ANI3" Point="I" /&gt;
+      &lt;/ADC&gt;
+      &lt;Serial&gt;
+        &lt;SAU0&gt;
+          &lt;UART0&gt;
+            &lt;RXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P61" RealName="RxD0" Point="I" /&gt;
+            &lt;TXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P60" RealName="TxD0" Point="O" /&gt;
+          &lt;/UART0&gt;
+          &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+            &lt;SO00 Port="P12" Point="O" /&gt;
+            &lt;SI00 Port="P11" Point="I" /&gt;
+            &lt;SCK00 Port="P10" RealName="_SCK00" Point="I/O" /&gt;
+          &lt;/CSI00&gt;
+          &lt;CSI01 Chip="RL78G12_20pin"&gt;
+            &lt;SO01 Port="P41" Point="O" /&gt;
+            &lt;SI01 Port="P125" Point="I" /&gt;
+            &lt;SCK01 Port="P42" RealName="_SCK01" Point="I/O" /&gt;
+          &lt;/CSI01&gt;
+          &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+            &lt;SCL00 Port="P10" Point="I/O" CheckNch="true" /&gt;
+            &lt;SDA00 Port="P11" Point="I/O" CheckNch="true" /&gt;
+          &lt;/IIC00&gt;
+          &lt;IIC01 Chip="RL78G12_20pin"&gt;
+            &lt;SCL01 Port="P42" Point="I/O" CheckNch="true" /&gt;
+            &lt;SDA01 Port="P41" Point="I/O" CheckNch="true" /&gt;
+          &lt;/IIC01&gt;
+        &lt;/SAU0&gt;
+        &lt;IICA0&gt;
+          &lt;SCLA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P60" Point="I/O" /&gt;
+          &lt;SDAA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P61" Point="I/O" /&gt;
+        &lt;/IICA0&gt;
+      &lt;/Serial&gt;
+      &lt;TAU&gt;
+        &lt;TAU0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR2="0"&gt;
+          &lt;Channel0&gt;
+            &lt;TI00 Port="P13" Point="I" /&gt;
+            &lt;TO00 Port="P13" Point="O" /&gt;
+          &lt;/Channel0&gt;
+          &lt;Channel1&gt;
+            &lt;TI01 Port="P14" Point="I" /&gt;
+            &lt;TO01 Port="P14" Point="O" /&gt;
+          &lt;/Channel1&gt;
+          &lt;Channel2&gt;
+            &lt;TI02 Port="P41" Point="I" /&gt;
+            &lt;TO02 Port="P41" Point="O" /&gt;
+          &lt;/Channel2&gt;
+          &lt;Channel3&gt;
+            &lt;TI03 Port="P42" Point="I" /&gt;
+            &lt;TO03 Port="P42" Point="O" /&gt;
+          &lt;/Channel3&gt;
+        &lt;/TAU0&gt;
+      &lt;/TAU&gt;
+      &lt;PCLBUZ&gt;
+        &lt;PCLBUZ0&gt;
+          &lt;PCLBUZ0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="O" /&gt;
+        &lt;/PCLBUZ0&gt;
+      &lt;/PCLBUZ&gt;
+      &lt;Others&gt;
+        &lt;VDD AltFunc="VDD" Point="-" /&gt;
+        &lt;VSS AltFunc="VSS" Point="-" /&gt;
+      &lt;/Others&gt;
+    &lt;/PIN&gt;
+    &lt;INT&gt;
+      &lt;INTC&gt;
+        &lt;INTP&gt;
+          &lt;INTP0 InUse="0" ISR="r_intc0_interrupt" /&gt;
+          &lt;INTP1 InUse="0" ISR="r_intc1_interrupt" /&gt;
+          &lt;INTP2 InUse="0" ISR="r_intc2_interrupt" /&gt;
+          &lt;INTP3 InUse="0" ISR="r_intc3_interrupt" /&gt;
+        &lt;/INTP&gt;
+        &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+          &lt;INTKR InUse="0" ISR="r_key_interrupt" /&gt;
+        &lt;/KEY&gt;
+      &lt;/INTC&gt;
+      &lt;Serial&gt;
+        &lt;SAU0&gt;
+          &lt;INTCSI00 InUse="0" ISR="r_csi00_interrupt" /&gt;
+          &lt;INTCSI01 InUse="0" ISR="r_csi01_interrupt" /&gt;
+          &lt;INTCSI10 InUse="0" ISR="r_csi10_interrupt" /&gt;
+          &lt;INTCSI11 InUse="0" ISR="r_csi11_interrupt" /&gt;
+          &lt;INTST0 InUse="1" ISR="r_uart0_interrupt_send" /&gt;
+          &lt;INTST1 InUse="0" ISR="r_uart1_interrupt_send" /&gt;
+          &lt;INTSRE0 InUse="0" ISR="r_uart0_interrupt_error" /&gt;
+          &lt;INTSRE1 InUse="0" ISR="r_uart1_interrupt_error" /&gt;
+          &lt;INTSR0 InUse="1" ISR="r_uart0_interrupt_receive" /&gt;
+          &lt;INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /&gt;
+          &lt;INTIIC00 InUse="0" ISR="r_iic00_interrupt" /&gt;
+          &lt;INTIIC01 InUse="0" ISR="r_iic01_interrupt" /&gt;
+          &lt;INTIIC10 InUse="0" ISR="r_iic10_interrupt" /&gt;
+          &lt;INTIIC11 InUse="0" ISR="r_iic11_interrupt" /&gt;
+        &lt;/SAU0&gt;
+        &lt;SAU1&gt;
+          &lt;INTCSI20 InUse="0" ISR="r_csi20_interrupt" /&gt;
+          &lt;INTCSI21 InUse="0" ISR="r_csi21_interrupt" /&gt;
+          &lt;INTCSI30 InUse="0" ISR="r_csi30_interrupt" /&gt;
+          &lt;INTCSI31 InUse="0" ISR="r_csi31_interrupt" /&gt;
+          &lt;INTST2 InUse="0" ISR="r_uart2_interrupt_send" /&gt;
+          &lt;INTST3 InUse="0" ISR="r_uart3_interrupt_send" /&gt;
+          &lt;INTSRE2 InUse="0" ISR="r_uart2_interrupt_error" /&gt;
+          &lt;INTSRE3 InUse="0" ISR="r_uart3_interrupt_error" /&gt;
+          &lt;INTSR2 InUse="0" ISR="r_uart2_interrupt_receive" /&gt;
+          &lt;INTSR3 InUse="0" ISR="r_uart3_interrupt_receive" /&gt;
+          &lt;INTIIC20 InUse="0" ISR="r_iic20_interrupt" /&gt;
+          &lt;INTIIC21 InUse="0" ISR="r_iic21_interrupt" /&gt;
+          &lt;INTIIC30 InUse="0" ISR="r_iic30_interrupt" /&gt;
+          &lt;INTIIC31 InUse="0" ISR="r_iic31_interrupt" /&gt;
+        &lt;/SAU1&gt;
+        &lt;IICA0&gt;
+          &lt;INTIICA0 InUse="0" ISR="r_iica0_interrupt" /&gt;
+        &lt;/IICA0&gt;
+      &lt;/Serial&gt;
+      &lt;ADC&gt;
+        &lt;INTAD InUse="0" ISR="r_adc_interrupt" IsDMATrigger="true" /&gt;
+      &lt;/ADC&gt;
+      &lt;TAU&gt;
+        &lt;TAU0&gt;
+          &lt;Channel0&gt;
+            &lt;INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /&gt;
+          &lt;/Channel0&gt;
+          &lt;Channel1&gt;
+            &lt;INTTM01 InUse="0" ISR="r_tau0_channel1_interrupt" /&gt;
+            &lt;INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /&gt;
+          &lt;/Channel1&gt;
+          &lt;Channel2&gt;
+            &lt;INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /&gt;
+          &lt;/Channel2&gt;
+          &lt;Channel3&gt;
+            &lt;INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /&gt;
+            &lt;INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /&gt;
+          &lt;/Channel3&gt;
+          &lt;Channel4&gt;
+            &lt;INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /&gt;
+          &lt;/Channel4&gt;
+          &lt;Channel5&gt;
+            &lt;INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /&gt;
+          &lt;/Channel5&gt;
+          &lt;Channel6&gt;
+            &lt;INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /&gt;
+          &lt;/Channel6&gt;
+          &lt;Channel7&gt;
+            &lt;INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /&gt;
+          &lt;/Channel7&gt;
+        &lt;/TAU0&gt;
+      &lt;/TAU&gt;
+      &lt;IT&gt;
+        &lt;INTIT InUse="0" ISR="r_it_interrupt" /&gt;
+      &lt;/IT&gt;
+      &lt;DMAC&gt;
+        &lt;DMA0&gt;
+          &lt;INTDMA0 InUse="0" ISR="r_dmac0_interrupt" /&gt;
+        &lt;/DMA0&gt;
+        &lt;DMA1&gt;
+          &lt;INTDMA1 InUse="0" ISR="r_dmac1_interrupt" /&gt;
+        &lt;/DMA1&gt;
+      &lt;/DMAC&gt;
+      &lt;WDT&gt;
+        &lt;INTWDTI InUse="0" ISR="r_wdt_interrupt" /&gt;
+      &lt;/WDT&gt;
+      &lt;LVD&gt;
+        &lt;INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /&gt;
+      &lt;/LVD&gt;
+    &lt;/INT&gt;
+    &lt;FUNC&gt;
+      &lt;Common&gt;
+        &lt;r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"&gt;
+          &lt;Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /&gt;
+          &lt;main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /&gt;
+          &lt;R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /&gt;
+        &lt;/r_main.c&gt;
+        &lt;r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"&gt;
+          &lt;Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /&gt;
+          &lt;R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /&gt;
+          &lt;hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /&gt;
+          &lt;__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /&gt;
+        &lt;/r_systeminit.c&gt;
+        &lt;r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"&gt;
+          &lt;Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /&gt;
+          &lt;R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /&gt;
+          &lt;HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /&gt;
+        &lt;/r_hardware_setup.c&gt;
+        &lt;r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"&gt;
+          &lt;Type R_Dummy="void R_Dummy(void)" /&gt;
+          &lt;R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /&gt;
+        &lt;/r_cg_vector_table.c&gt;
+        &lt;r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /&gt;
+        &lt;r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /&gt;
+        &lt;r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /&gt;
+        &lt;r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /&gt;
+        &lt;iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /&gt;
+      &lt;/Common&gt;
+      &lt;CGC&gt;
+        &lt;r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(clock_mode_t mode)" /&gt;
+          &lt;R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /&gt;
+          &lt;R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /&gt;
+        &lt;/r_cg_cgc.c&gt;
+        &lt;r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" /&gt;
+          &lt;R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /&gt;
+          &lt;R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /&gt;
+        &lt;/r_cg_cgc_user.c&gt;
+        &lt;r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /&gt;
+        &lt;r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"&gt;
+          &lt;Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /&gt;
+          &lt;R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /&gt;
+          &lt;R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /&gt;
+          &lt;R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /&gt;
+          &lt;R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /&gt;
+          &lt;R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /&gt;
+          &lt;R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /&gt;
+          &lt;R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /&gt;
+          &lt;R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /&gt;
+        &lt;/r_cg_pfdl.c&gt;
+        &lt;r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /&gt;
+      &lt;/CGC&gt;
+      &lt;PORT&gt;
+        &lt;r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_PORT_Create="void R_PORT_Create(void)" /&gt;
+          &lt;R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /&gt;
+        &lt;/r_cg_port.c&gt;
+        &lt;r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /&gt;
+          &lt;R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /&gt;
+        &lt;/r_cg_port_user.c&gt;
+        &lt;r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /&gt;
+      &lt;/PORT&gt;
+      &lt;INTC&gt;
+        &lt;r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /&gt;
+          &lt;INTP&gt;
+            &lt;R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="" Init="2" InitMode="" /&gt;
+            &lt;INTP0&gt;
+              &lt;R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP0&gt;
+            &lt;INTP1&gt;
+              &lt;R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP1&gt;
+            &lt;INTP2&gt;
+              &lt;R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP2&gt;
+            &lt;INTP3&gt;
+              &lt;R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP3&gt;
+          &lt;/INTP&gt;
+          &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+            &lt;R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /&gt;
+            &lt;R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /&gt;
+            &lt;R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /&gt;
+          &lt;/KEY&gt;
+        &lt;/r_cg_intc.c&gt;
+        &lt;r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" R_INTC0_Interrupt="__interrupt static void r_intc0_interrupt(void)" R_INTC1_Interrupt="__interrupt static void r_intc1_interrupt(void)" R_INTC2_Interrupt="__interrupt static void r_intc2_interrupt(void)" R_INTC3_Interrupt="__interrupt static void r_intc3_interrupt(void)" R_INTC4_Interrupt="__interrupt static void r_intc4_interrupt(void)" R_INTC5_Interrupt="__interrupt static void r_intc5_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" R_KEY_Interrupt="__interrupt static void r_key_interrupt(void)" /&gt;
+          &lt;INTP&gt;
+            &lt;R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="" /&gt;
+            &lt;r_intc0_interrupt UserName="r_intc0_interrupt" LibName="R_INTC0_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc1_interrupt UserName="r_intc1_interrupt" LibName="R_INTC1_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc2_interrupt UserName="r_intc2_interrupt" LibName="R_INTC2_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc3_interrupt UserName="r_intc3_interrupt" LibName="R_INTC3_Interrupt" INTHandle="" InUse="" /&gt;
+          &lt;/INTP&gt;
+          &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+            &lt;R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /&gt;
+            &lt;r_key_interrupt UserName="r_key_interrupt" LibName="R_KEY_Interrupt" INTHandle="" InUse="" /&gt;
+          &lt;/KEY&gt;
+        &lt;/r_cg_intc_user.c&gt;
+        &lt;r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="" /&gt;
+      &lt;/INTC&gt;
+      &lt;Serial&gt;
+        &lt;r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t * const rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t * const tx_buf, uint16_t tx_num, uint8_t * const rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" IICn_Init="void IICn_Init(void)" IICn_MasterSendStart="MD_STATUS IICn_MasterSendStart(uint8_t adr, uint8_t * const tx_buf, USHORT tx_num, uint8_t wait)" IICn_MasterReceiveStart="MD_STATUS IICn_MasterReceiveStart(uint8_t adr, uint8_t * const rx_buf, USHORT rx_num, uint8_t wait)" IICn_SlaveSendStart="void IICn_SlaveSendStart(uint8_t * const tx_buf, USHORT tx_num)" IICn_SlaveReceiveStart="void IICn_SlaveReceiveStart(uint8_t * const rx_buf, USHORT rx_num)" IICn_Stop="void IICn_Stop(void)" IICn_StopCondition="void IICn_StopCondition(void)" IICn_PowerOff="void IICn_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /&gt;
+          &lt;SAU0 InUse=""&gt;
+            &lt;R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="1" Init="1" InitMode="" /&gt;
+            &lt;R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /&gt;
+            &lt;R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /&gt;
+            &lt;R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /&gt;
+            &lt;UART0 InUse=""&gt;
+              &lt;R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="1" InitMode="" /&gt;
+              &lt;R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="1" /&gt;
+              &lt;R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="1" /&gt;
+              &lt;R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="1" /&gt;
+              &lt;R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="1" /&gt;
+            &lt;/UART0&gt;
+            &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /&gt;
+              &lt;R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /&gt;
+              &lt;R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /&gt;
+              &lt;R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /&gt;
+              &lt;R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /&gt;
+            &lt;/CSI00&gt;
+            &lt;CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /&gt;
+              &lt;R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /&gt;
+              &lt;R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /&gt;
+              &lt;R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /&gt;
+              &lt;R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /&gt;
+            &lt;/CSI01&gt;
+            &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /&gt;
+              &lt;R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /&gt;
+              &lt;R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /&gt;
+              &lt;R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /&gt;
+              &lt;R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /&gt;
+            &lt;/IIC00&gt;
+            &lt;IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /&gt;
+              &lt;R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /&gt;
+              &lt;R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /&gt;
+              &lt;R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /&gt;
+              &lt;R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /&gt;
+            &lt;/IIC01&gt;
+          &lt;/SAU0&gt;
+          &lt;IICA0 InUse=""&gt;
+            &lt;R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /&gt;
+            &lt;R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /&gt;
+            &lt;R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /&gt;
+            &lt;R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /&gt;
+            &lt;R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /&gt;
+            &lt;R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /&gt;
+            &lt;R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /&gt;
+            &lt;R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /&gt;
+            &lt;R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /&gt;
+          &lt;/IICA0&gt;
+        &lt;/r_cg_serial.c&gt;
+        &lt;r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" R_UARTn_Interrupt_Receive="__interrupt static void R_UARTn_Interrupt_Receive(void)" R_UARTn_Interrupt_Error="__interrupt static void R_UARTn_Interrupt_Error(void)" R_UARTn_Interrupt_Send="__interrupt static void R_UARTn_Interrupt_Send(void)" R_UARTn_Callback_SendEnd="static void R_UARTn_Callback_SendEnd(void)" R_UARTn_Callback_ReceiveEnd="static void R_UARTn_Callback_ReceiveEnd(void)" R_UARTn_Callback_Error="static void R_UARTn_Callback_Error(uint8_t err_type)" R_UARTn_Callback_SoftwareOverRun="static void R_UARTn_Callback_SoftwareOverRun(uint16_t rx_data)" R_CSIn_Interrupt="__interrupt static void R_CSIn_Interrupt(void)" R_CSIn_Callback_ReceiveEnd="static void R_CSIn_Callback_ReceiveEnd(void)" R_CSIn_Callback_Error="static void R_CSIn_Callback_Error(uint8_t err_type)" R_CSIn_Callback_SendEnd="static void R_CSIn_Callback_SendEnd(void)" R_IICn_Interrupt="__interrupt static void R_IICn_Interrupt(void)" R_IICn_Callback_Master_ReceiveEnd="static void R_IICn_Callback_Master_ReceiveEnd(void)" R_IICn_Callback_Master_SendEnd="static void R_IICn_Callback_Master_SendEnd(void)" R_IICn_Callback_Master_Error="static void R_IICn_Callback_Master_Error(MD_STATUS flag)" IICn_MasterSendEndCallback="static void IICn_MasterSendEndCallback(void)" IICn_MasterReceiveEndCallback="static void IICn_MasterReceiveEndCallback(void)" IICn_MasterErrorCallback="static void IICn_MasterErrorCallback(MD_STATUS flag)" IICn_SlaveErrorCallback="static void IICn_SlaveErrorCallback(MD_STATUS flag)" IICn_GetStopConditionCallback="static void IICn_GetStopConditionCallback(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static void r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /&gt;
+          &lt;SAU0 InUse=""&gt;
+            &lt;R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /&gt;
+            &lt;UART0 InUse=""&gt;
+              &lt;r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="R_UARTn_Interrupt_Receive" InUse="1" /&gt;
+              &lt;r_uart0_interrupt_error UserName="r_uart0_interrupt_error" INTHandle="" LibName="R_UARTn_Interrupt_Error" InUse="0" /&gt;
+              &lt;r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="R_UARTn_Interrupt_Send" InUse="1" /&gt;
+              &lt;r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="R_UARTn_Callback_ReceiveEnd" InUse="1" /&gt;
+              &lt;r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="R_UARTn_Callback_SendEnd" InUse="1" /&gt;
+              &lt;r_uart0_callback_error UserName="r_uart0_callback_error" LibName="R_UARTn_Callback_Error" InUse="1" /&gt;
+              &lt;r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="R_UARTn_Callback_SoftwareOverRun" InUse="1" /&gt;
+            &lt;/UART0&gt;
+            &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /&gt;
+              &lt;r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_csi00_callback_error UserName="r_csi00_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /&gt;
+              &lt;r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /&gt;
+            &lt;/CSI00&gt;
+            &lt;CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /&gt;
+              &lt;r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_csi01_callback_error UserName="r_csi01_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /&gt;
+              &lt;r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /&gt;
+            &lt;/CSI01&gt;
+            &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /&gt;
+            &lt;/IIC00&gt;
+            &lt;IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /&gt;
+            &lt;/IIC01&gt;
+          &lt;/SAU0&gt;
+          &lt;IICA0 InUse=""&gt;
+            &lt;R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /&gt;
+            &lt;r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /&gt;
+            &lt;r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /&gt;
+            &lt;r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /&gt;
+            &lt;r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /&gt;
+            &lt;r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /&gt;
+          &lt;/IICA0&gt;
+        &lt;/r_cg_serial_user.c&gt;
+        &lt;r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="1" /&gt;
+      &lt;/Serial&gt;
+      &lt;ADC&gt;
+        &lt;r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="0"&gt;
+          &lt;Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /&gt;
+          &lt;R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="0" Init="1" InitMode="" /&gt;
+          &lt;R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="0" /&gt;
+          &lt;R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="0" /&gt;
+          &lt;R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="0" /&gt;
+          &lt;R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="0" /&gt;
+          &lt;R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="0" /&gt;
+          &lt;R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /&gt;
+          &lt;R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /&gt;
+          &lt;R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /&gt;
+          &lt;R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /&gt;
+          &lt;R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /&gt;
+          &lt;R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /&gt;
+        &lt;/r_cg_adc.c&gt;
+        &lt;r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="0"&gt;
+          &lt;Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /&gt;
+          &lt;R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /&gt;
+          &lt;r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_adc_user.c&gt;
+        &lt;r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="0" /&gt;
+      &lt;/ADC&gt;
+      &lt;TAU&gt;
+        &lt;r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" /&gt;
+          &lt;TAU0&gt;
+            &lt;R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /&gt;
+            &lt;R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /&gt;
+            &lt;Channel0 InUse=""&gt;
+              &lt;R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /&gt;
+              &lt;R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /&gt;
+              &lt;R_TAU0_Channel0_Get_PulseWidth UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+              &lt;R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /&gt;
+            &lt;/Channel0&gt;
+            &lt;Channel1 InUse=""&gt;
+              &lt;R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+            &lt;/Channel1&gt;
+            &lt;Channel2 InUse=""&gt;
+              &lt;R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Get_PulseWidth UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /&gt;
+            &lt;/Channel2&gt;
+            &lt;Channel3 InUse=""&gt;
+              &lt;R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Get_PulseWidth UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+            &lt;/Channel3&gt;
+          &lt;/TAU0&gt;
+        &lt;/r_cg_timer.c&gt;
+        &lt;r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" /&gt;
+          &lt;TAU0&gt;
+            &lt;R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /&gt;
+            &lt;Channel0 InUse=""&gt;
+              &lt;r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /&gt;
+            &lt;/Channel0&gt;
+            &lt;Channel1 InUse=""&gt;
+              &lt;r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+              &lt;r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /&gt;
+            &lt;/Channel1&gt;
+            &lt;Channel2 InUse=""&gt;
+              &lt;r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+            &lt;/Channel2&gt;
+            &lt;Channel3 InUse=""&gt;
+              &lt;r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+              &lt;r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /&gt;
+            &lt;/Channel3&gt;
+          &lt;/TAU0&gt;
+        &lt;/r_cg_timer_user.c&gt;
+        &lt;r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /&gt;
+      &lt;/TAU&gt;
+      &lt;WDT&gt;
+        &lt;r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /&gt;
+          &lt;R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /&gt;
+          &lt;R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /&gt;
+        &lt;/r_cg_wdt.c&gt;
+        &lt;r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /&gt;
+          &lt;R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /&gt;
+          &lt;r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_wdt_user.c&gt;
+        &lt;r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /&gt;
+      &lt;/WDT&gt;
+      &lt;IT&gt;
+        &lt;r_cg_it.c UserName="r_cg_it.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_IT_Create="void R_IT_Create(void)" R_IT_Start="void R_IT_Start(void)" R_IT_Stop="void R_IT_Stop(void)" R_IT_Set_PowerOff="void R_IT_Set_PowerOff(void)" /&gt;
+          &lt;R_IT_Create UserName="R_IT_Create" LibName="R_IT_Create" InUse="" Init="1" InitMode="" /&gt;
+          &lt;R_IT_Start UserName="R_IT_Start" LibName="R_IT_Start" InUse="" /&gt;
+          &lt;R_IT_Stop UserName="R_IT_Stop" LibName="R_IT_Stop" InUse="" /&gt;
+          &lt;R_IT_Set_PowerOff UserName="R_IT_Set_PowerOff" LibName="R_IT_Set_PowerOff" InUse="" /&gt;
+        &lt;/r_cg_it.c&gt;
+        &lt;r_cg_it_user.c UserName="r_cg_it_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_IT_Create_UserInit="void R_IT_Create_UserInit(void)" r_it_interrupt="__interrupt static void r_it_interrupt(void)" /&gt;
+          &lt;R_IT_Create_UserInit UserName="R_IT_Create_UserInit" LibName="R_IT_Create_UserInit" InUse="" /&gt;
+          &lt;r_it_interrupt UserName="r_it_interrupt" INTHandle="" LibName="r_it_interrupt" InUse="" /&gt;
+        &lt;/r_cg_it_user.c&gt;
+        &lt;r_cg_it.h UserName="r_cg_it.h" LibName=".h" InUse="" /&gt;
+      &lt;/IT&gt;
+      &lt;PCLBUZ&gt;
+        &lt;r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /&gt;
+          &lt;PCLBUZ0 InUse=""&gt;
+            &lt;R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="" /&gt;
+            &lt;R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="" /&gt;
+          &lt;/PCLBUZ0&gt;
+        &lt;/r_cg_pclbuz.c&gt;
+        &lt;r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /&gt;
+          &lt;PCLBUZ0 InUse=""&gt;
+            &lt;R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="" Init="1" /&gt;
+          &lt;/PCLBUZ0&gt;
+        &lt;/r_cg_pclbuz_user.c&gt;
+        &lt;r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="" /&gt;
+      &lt;/PCLBUZ&gt;
+      &lt;DMAC&gt;
+        &lt;r_cg_dmac.c UserName="r_cg_dmac.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_DMACn_Create="void R_DMACn_Create(void)" R_DMACn_Start="void R_DMACn_Start(void)" R_DMACn_Stop="void R_DMACn_Stop(void)" R_DMACn_Set_SoftwareTriggerOn="void R_DMACn_Set_SoftwareTriggerOn(void)" /&gt;
+          &lt;DMA0 InUse=""&gt;
+            &lt;R_DMAC0_Create UserName="R_DMAC0_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_DMAC0_Start UserName="R_DMAC0_Start" LibName="R_DMACn_Start" InUse="" /&gt;
+            &lt;R_DMAC0_Stop UserName="R_DMAC0_Stop" LibName="R_DMACn_Stop" InUse="" /&gt;
+            &lt;R_DMAC0_Set_SoftwareTriggerOn UserName="R_DMAC0_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /&gt;
+          &lt;/DMA0&gt;
+          &lt;DMA1 InUse=""&gt;
+            &lt;R_DMAC1_Create UserName="R_DMAC1_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_DMAC1_Start UserName="R_DMAC1_Start" LibName="R_DMACn_Start" InUse="" /&gt;
+            &lt;R_DMAC1_Stop UserName="R_DMAC1_Stop" LibName="R_DMACn_Stop" InUse="" /&gt;
+            &lt;R_DMAC1_Set_SoftwareTriggerOn UserName="R_DMAC1_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /&gt;
+          &lt;/DMA1&gt;
+        &lt;/r_cg_dmac.c&gt;
+        &lt;r_cg_dmac_user.c UserName="r_cg_dmac_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_DMACn_Create_UserInit="void R_DMACn_Create_UserInit(void)" r_dmacn_interrupt="__interrupt static void r_dmacn_interrupt(void)" /&gt;
+          &lt;DMA0&gt;
+            &lt;R_DMAC0_Create_UserInit UserName="R_DMAC0_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /&gt;
+            &lt;r_dmac0_interrupt UserName="r_dmac0_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /&gt;
+          &lt;/DMA0&gt;
+          &lt;DMA1&gt;
+            &lt;R_DMAC1_Create_UserInit UserName="R_DMAC1_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /&gt;
+            &lt;r_dmac1_interrupt UserName="r_dmac1_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /&gt;
+          &lt;/DMA1&gt;
+        &lt;/r_cg_dmac_user.c&gt;
+        &lt;r_cg_dmac.h UserName="r_cg_dmac.h" LibName=".h" InUse="" /&gt;
+      &lt;/DMAC&gt;
+      &lt;LVD&gt;
+        &lt;r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"&gt;
+          &lt;Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /&gt;
+          &lt;R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /&gt;
+          &lt;R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /&gt;
+        &lt;/r_cg_lvd.c&gt;
+        &lt;r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"&gt;
+          &lt;Type R_LVD_Creat_UserInit="void R_LVD_Creat_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /&gt;
+          &lt;R_LVD_Creat_UserInit UserName="R_LVD_Creat_UserInit" LibName="R_LVD_Creat_UserInit" InUse="0" /&gt;
+          &lt;r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_lvd_user.c&gt;
+        &lt;r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /&gt;
+      &lt;/LVD&gt;
+    &lt;/FUNC&gt;
+    &lt;TAG&gt;
+      &lt;GlobleUserTag&gt;
+        &lt;cg_security9 Name="cg_security9" Value="00" /&gt;
+        &lt;cg_security7 Name="cg_security7" Value="00" /&gt;
+        &lt;cg_security5 Name="cg_security5" Value="00" /&gt;
+        &lt;ocdstart Name="ocdstart" Value="01E00" /&gt;
+        &lt;cg_security3 Name="cg_security3" Value="00" /&gt;
+        &lt;cg_security0 Name="cg_security0" Value="00" /&gt;
+        &lt;cg_security1 Name="cg_security1" Value="00" /&gt;
+        &lt;clock_option Name="clock_option" Value="E0" /&gt;
+        &lt;pior_value Name="pior_value" Value="02" /&gt;
+        &lt;cg_option Name="cg_option" Value="04" /&gt;
+        &lt;cg_security8 Name="cg_security8" Value="00" /&gt;
+        &lt;cg_security6 Name="cg_security6" Value="00" /&gt;
+        &lt;cg_security4 Name="cg_security4" Value="00" /&gt;
+        &lt;cg_security2 Name="cg_security2" Value="00" /&gt;
+        &lt;cg_iawctl_value Name="cg_iawctl_value" Value="00" /&gt;
+        &lt;lvi_option Name="lvi_option" Value="47" /&gt;
+        &lt;wdt_option Name="wdt_option" Value="7A" /&gt;
+      &lt;/GlobleUserTag&gt;
+    &lt;/TAG&gt;
+  &lt;/DIR&gt;
+  &lt;MACRO&gt;
+    &lt;CGC HelpID="CGC" Prepared="true" SetFlag="True" NeedRefresh="False"&gt;
+      &lt;CGC SetFlag="True" MacroName="cgc" /&gt;
+    &lt;/CGC&gt;
+    &lt;PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"&gt;
+      &lt;PORT SetFlag="True" MacroName="PORT" /&gt;
+    &lt;/PORT&gt;
+    &lt;INTC SetFlag="" HelpID="int" NeedRefresh="False"&gt;
+      &lt;INTP Accelerate="No" MacroName="INTP" /&gt;
+      &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin," MacroName="KEY" /&gt;
+    &lt;/INTC&gt;
+    &lt;Serial SetFlag="True" HelpID="serial" NeedRefresh="False"&gt;
+      &lt;SAU0 Chip="RL78G12_20pin,RL78G12_24pin" Accelerate="No" MacroName="SAU" Channel="0" SetFlag="True" TabEnable="True"&gt;
+        &lt;Channel0 UART="0" CSI="00" IIC="00" Channel="0" /&gt;
+        &lt;Channel1 UART="0" CSI="01" IIC="01" Channel="1" /&gt;
+      &lt;/SAU0&gt;
+      &lt;IICA0 Accelerate="No" MacroName="IICA" Channel="0" TabEnable="True" /&gt;
+    &lt;/Serial&gt;
+    &lt;ADC SetFlag="False" HelpID="adc" NeedRefresh="False"&gt;
+      &lt;ADC SetFlag="False" MacroName="ADC" /&gt;
+    &lt;/ADC&gt;
+    &lt;TAU SetFlag="True" HelpID="timer" NeedRefresh="False"&gt;
+      &lt;TAU0 Accelerate="No" Chip="RL78G12_20pin,RL78G12_24pin" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3" SetFlag="True" /&gt;
+    &lt;/TAU&gt;
+    &lt;WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"&gt;
+      &lt;WDT SetFlag="True" MacroName="WDT" /&gt;
+    &lt;/WDT&gt;
+    &lt;IT SetFlag="" HelpID="intervaltimer" NeedRefresh="False"&gt;
+      &lt;IT MacroName="IntervalTM" /&gt;
+    &lt;/IT&gt;
+    &lt;PCLBUZ SetFlag="" HelpID="PCLBUZ" NeedRefresh="False"&gt;
+      &lt;PCLBUZ0 MacroName="PCLBUZ" Channel="0" /&gt;
+    &lt;/PCLBUZ&gt;
+    &lt;DMAC HelpID="dmac" SetFlag="" NeedRefresh="False"&gt;
+      &lt;DMA0 MacroName="DMAC" Channel="0" TabEnable="True" /&gt;
+      &lt;DMA1 MacroName="DMAC" Channel="1" TabEnable="True" /&gt;
+    &lt;/DMAC&gt;
+    &lt;LVD SetFlag="True" Prepared="true" HelpID="lvi" NeedRefresh="False"&gt;
+      &lt;LVD MacroName="LVD" SetFlag="True" /&gt;
+    &lt;/LVD&gt;
+  &lt;/MACRO&gt;
+  &lt;SETTING&gt;
+    &lt;CGC&gt;
+      &lt;setting name="PIOR_Setting" value="FIX" /&gt;
+      &lt;setting name="PIOR6" value="1" /&gt;
+      &lt;setting name="PIOR5" value="1" /&gt;
+      &lt;setting name="PIOR4" value="1" /&gt;
+      &lt;setting name="PIOR3" value="1" /&gt;
+      &lt;setting name="PIOR2" value="1" /&gt;
+      &lt;setting name="PIOR1" value="0" /&gt;
+      &lt;setting name="PIOR0" value="1" /&gt;
+      &lt;setting name="PIOR10" value="1" /&gt;
+      &lt;setting name="PIOR11" value="1" /&gt;
+      &lt;setting name="PIOR12" value="1" /&gt;
+      &lt;setting name="PIOR13" value="1" /&gt;
+      &lt;setting name="VDD" value="VDD0" /&gt;
+      &lt;setting name="EVDD" value="EVDD2" /&gt;
+      &lt;setting name="Main_system_clock" value="high-speed internal clock" /&gt;
+      &lt;setting name="High_speed_internal_oscillator" value="operation" /&gt;
+      &lt;setting name="High_speed_internal_frequency" value="8" /&gt;
+      &lt;setting name="High_speed_system_clock" value="stop" /&gt;
+      &lt;setting name="High_speed_system_input" value="X1" /&gt;
+      &lt;setting name="HighSpeedSystemStable" value="7" /&gt;
+      &lt;setting name="High_speed_system_clock_frequency" value="5" /&gt;
+      &lt;setting name="Sub_clock_operation" value="XT1" /&gt;
+      &lt;setting name="SubclockFrequency" value="32.768" /&gt;
+      &lt;setting name="XT1_oscillator_oscillation_mode" value="0" /&gt;
+      &lt;setting name="SubClock" value="unused" /&gt;
+      &lt;setting name="Subclock_in_halt" value="0" /&gt;
+      &lt;setting name="CPU_clock" value="0" /&gt;
+      &lt;setting name="Internal_low-speed_clock" value="15" /&gt;
+      &lt;setting name="RTC_clcok_selection" value="0" /&gt;
+      &lt;setting name="RESET_PIN_USED" value="false" /&gt;
+      &lt;setting name="RESET_PIN_UNUSED" value="true" /&gt;
+      &lt;setting name="On_chip_debug" value="unused" /&gt;
+      &lt;setting name="RRM" value="used" /&gt;
+      &lt;setting name="Trace" value="Used" /&gt;
+      &lt;setting name="Erase_flash_memory" value="yes" /&gt;
+      &lt;setting name="Security_ID_setting" value="used" /&gt;
+      &lt;setting name="Security_ID" value="0x00000000000000000000" /&gt;
+      &lt;setting name="CG_ReadResetSource" value="generated" /&gt;
+      &lt;setting name="Accessoperation" value="unused" /&gt;
+      &lt;setting name="RAMoperation" value="unused" /&gt;
+      &lt;setting name="RAMArea" value="0" /&gt;
+      &lt;setting name="PORToperation" value="unused" /&gt;
+      &lt;setting name="INToperation" value="unused" /&gt;
+      &lt;setting name="CHIPoperation" value="unused" /&gt;
+      &lt;setting name="DataFlash" value="unused" /&gt;
+      &lt;setting name="ProgramFlash" value="unused" /&gt;
+      &lt;setting name="Monitor" value="unused" /&gt;
+      &lt;setting name="StartStop" value="unused" /&gt;
+      &lt;setting name="Emulator" value="E1" /&gt;
+    &lt;/CGC&gt;
+    &lt;PORT&gt;
+      &lt;PortP1&gt;
+        &lt;P10&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P10&gt;
+        &lt;P11&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P11&gt;
+        &lt;P12&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P12&gt;
+        &lt;P13&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P13&gt;
+        &lt;P14&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P14&gt;
+      &lt;/PortP1&gt;
+      &lt;PortP2&gt;
+        &lt;P20&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P20&gt;
+        &lt;P21&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P21&gt;
+        &lt;P22&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P22&gt;
+        &lt;P23&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P23&gt;
+      &lt;/PortP2&gt;
+      &lt;PortP4&gt;
+        &lt;P40&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="used" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P40&gt;
+        &lt;P41&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P41&gt;
+        &lt;P42&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P42&gt;
+      &lt;/PortP4&gt;
+      &lt;PortP6&gt;
+        &lt;P60&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P60&gt;
+        &lt;P61&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P61&gt;
+      &lt;/PortP6&gt;
+      &lt;PortP12&gt;
+        &lt;P121&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P121&gt;
+        &lt;P122&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P122&gt;
+        &lt;P125&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="used" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P125&gt;
+      &lt;/PortP12&gt;
+      &lt;PortP13&gt;
+        &lt;P137&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P137&gt;
+      &lt;/PortP13&gt;
+    &lt;/PORT&gt;
+    &lt;ADC&gt;
+      &lt;setting name="AD_convertion" value="unused" /&gt;
+      &lt;setting name="Comparator_operation" value="enable" /&gt;
+      &lt;setting name="Resolution" value="10bit" /&gt;
+      &lt;setting name="AD_Positive" value="VDD" /&gt;
+      &lt;setting name="AD_Negative" value="VSS" /&gt;
+      &lt;setting name="AD_Trigger" value="hardtrinowait" /&gt;
+      &lt;setting name="AD_Trigger_Timer" value="0" /&gt;
+      &lt;setting name="Mode" value="ONESELECT" /&gt;
+      &lt;setting name="InputPins" value="0" /&gt;
+      &lt;setting name="InputPinsAttach" value="ANI0 - ANI1" /&gt;
+      &lt;setting name="AD_Inputpin16" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin17" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin18" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin19" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin20" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin21" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin22" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin23" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin24" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin25" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin26" value="unused" /&gt;
+      &lt;setting name="SelectedChannel" value="0" /&gt;
+      &lt;setting name="SelectedChannelAttach" value="ANI0" /&gt;
+      &lt;setting name="ConvTimeMode" value="0" /&gt;
+      &lt;setting name="ConversionTime" value="0" /&gt;
+      &lt;setting name="AREAFunction" value="AREA1" /&gt;
+      &lt;setting name="AREAValue_ADUL" value="255" /&gt;
+      &lt;setting name="AREAValue_ADLL" value="0" /&gt;
+      &lt;setting name="Interrput_priority" value="3" /&gt;
+      &lt;setting name="AD_interrupt" value="used" /&gt;
+    &lt;/ADC&gt;
+    &lt;TAU0&gt;
+      &lt;Channel0&gt;
+        &lt;setting name="ChannelFunction" value="1" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+        &lt;TAUInterval0&gt;
+          &lt;setting name="OperationMode" value="16bits" /&gt;
+          &lt;setting name="Count_clock" value="MCK clock" /&gt;
+          &lt;setting name="Sub_clock_mode" value="-1" /&gt;
+          &lt;setting name="Interval_value" value="1000" /&gt;
+          &lt;setting name="Value_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_High8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_High8bits_scale" value="-1" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits_Scale" value="-1" /&gt;
+          &lt;setting name="Generate_interrupt_when_couting_started" value="no" /&gt;
+          &lt;setting name="Interrupt" value="used" /&gt;
+          &lt;setting name="Interrupt_priority" value="3" /&gt;
+          &lt;setting name="InterruptH_priority" value="3" /&gt;
+          &lt;setting name="InterruptH8" value="unused" /&gt;
+        &lt;/TAUInterval0&gt;
+      &lt;/Channel0&gt;
+      &lt;Channel1&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+        &lt;TAUInterval1&gt;
+          &lt;setting name="OperationMode" value="16bits" /&gt;
+          &lt;setting name="Count_clock" value="MCK clock" /&gt;
+          &lt;setting name="Sub_clock_mode" value="-1" /&gt;
+          &lt;setting name="Interval_value" value="1000" /&gt;
+          &lt;setting name="Value_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_High8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_High8bits_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits_Scale" value="1" /&gt;
+          &lt;setting name="Generate_interrupt_when_couting_started" value="no" /&gt;
+          &lt;setting name="Interrupt" value="used" /&gt;
+          &lt;setting name="Interrupt_priority" value="3" /&gt;
+          &lt;setting name="InterruptH_priority" value="3" /&gt;
+          &lt;setting name="InterruptH8" value="used" /&gt;
+        &lt;/TAUInterval1&gt;
+      &lt;/Channel1&gt;
+      &lt;Channel2&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+      &lt;/Channel2&gt;
+      &lt;Channel3&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+      &lt;/Channel3&gt;
+    &lt;/TAU0&gt;
+    &lt;WDT&gt;
+      &lt;setting name="Operation" value="used" /&gt;
+      &lt;setting name="Overflow_time" value="5" /&gt;
+      &lt;setting name="Window_opening_time" value="0" /&gt;
+      &lt;setting name="Standby_operation" value="stop" /&gt;
+      &lt;setting name="Interval_interrupt" value="not use" /&gt;
+      &lt;setting name="Interval_interrupt_priority" value="3" /&gt;
+    &lt;/WDT&gt;
+    &lt;LVD&gt;
+      &lt;setting name="Operation" value="used" /&gt;
+      &lt;setting name="Reset_only_level" value="5" /&gt;
+      &lt;setting name="InterruptReset_level" value="0" /&gt;
+      &lt;setting name="Interrupt_level" value="0" /&gt;
+      &lt;setting name="Interrupt_only_level" value="0" /&gt;
+      &lt;setting name="operation_mode" value="reset" /&gt;
+      &lt;setting name="Interrupt_priority" value="3" /&gt;
+      &lt;setting name="Interrupt_only_priority" value="3" /&gt;
+    &lt;/LVD&gt;
+    &lt;SAU0&gt;
+      &lt;IIC00 /&gt;
+      &lt;CSI00 /&gt;
+      &lt;UART0 /&gt;
+      &lt;Channel0&gt;
+        &lt;setting name="Channel_function_-i" value="1" /&gt;
+        &lt;setting name="Detail_function_-i" value="2" /&gt;
+        &lt;Both_UART0&gt;
+          &lt;setting name="Receive_data_direction" value="LSB" /&gt;
+          &lt;setting name="Receive_data_length" value="8 bits" /&gt;
+          &lt;setting name="Receive_parity" value="odd" /&gt;
+          &lt;setting name="RecBaudrate" value="9600" /&gt;
+          &lt;setting name="Receive_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Receive_error_callback_function" value="generated" /&gt;
+          &lt;setting name="Transfer_mode" value="single" /&gt;
+          &lt;setting name="Transmit_data_direction" value="LSB" /&gt;
+          &lt;setting name="Transmit_data_level" value="normal" /&gt;
+          &lt;setting name="Transmit_data_length" value="8 bits" /&gt;
+          &lt;setting name="Transmit_parity" value="odd" /&gt;
+          &lt;setting name="Transmit_stop_length" value="2 bits" /&gt;
+          &lt;setting name="TranBaudrate" value="9600" /&gt;
+          &lt;setting name="Transmit_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Transmit_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_error_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Reveive_Data_Level" value="Normal" /&gt;
+          &lt;setting name="Receive_error_interrupt" value="not used" /&gt;
+        &lt;/Both_UART0&gt;
+        &lt;Receive_UART0&gt;
+          &lt;setting name="Receive_data_direction" value="LSB" /&gt;
+          &lt;setting name="Receive_data_length" value="8 bits" /&gt;
+          &lt;setting name="Receive_parity" value="none" /&gt;
+          &lt;setting name="RecBaudrate" value="9600" /&gt;
+          &lt;setting name="Receive_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Receive_error_callback_function" value="generated" /&gt;
+          &lt;setting name="Transfer_mode" value="single" /&gt;
+          &lt;setting name="Transmit_data_direction" value="LSB" /&gt;
+          &lt;setting name="Transmit_data_level" value="normal" /&gt;
+          &lt;setting name="Transmit_data_length" value="8 bits" /&gt;
+          &lt;setting name="Transmit_parity" value="none" /&gt;
+          &lt;setting name="Transmit_stop_length" value="1 bit" /&gt;
+          &lt;setting name="TranBaudrate" value="9600" /&gt;
+          &lt;setting name="Transmit_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Transmit_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_error_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Reveive_Data_Level" value="Normal" /&gt;
+          &lt;setting name="Receive_error_interrupt" value="not used" /&gt;
+        &lt;/Receive_UART0&gt;
+      &lt;/Channel0&gt;
+      &lt;IIC01 /&gt;
+      &lt;CSI01 /&gt;
+      &lt;Channel1&gt;
+        &lt;setting name="Channel_function_-i" value="0" /&gt;
+        &lt;setting name="Detail_function_-i" value="-1" /&gt;
+      &lt;/Channel1&gt;
+    &lt;/SAU0&gt;
+    &lt;IICA0&gt;
+      &lt;setting name="Mode" value="Unused" /&gt;
+    &lt;/IICA0&gt;
+  &lt;/SETTING&gt;
+&lt;/RL78G12&gt;</CodeGenerator>
+      <FormatVersion>1.0</FormatVersion>
+      <ToolGUID>6c6bb60a-ffe1-4884-8dec-f255a2e58155</ToolGUID>
+      <CodeGeneratorItem>b8348788-df17-4b71-a9fa-eab0f1824fb1</CodeGeneratorItem>
+    </Instance>
+  </Class>
+  <Class Guid="2a2c2a43-ecdb-4e88-80bd-e75f3e33db90">
+    <Instance Guid="2a2c2a43-ecdb-4e88-80bd-e75f3e33db90">
+      <ProductVersion>9.07.00.00</ProductVersion>
+    </Instance>
+  </Class>
+</CubeSuiteProject>
\ No newline at end of file
diff --git a/K80.rcpe b/K80.rcpe
new file mode 100644
index 0000000..043a162
--- /dev/null
+++ b/K80.rcpe
@@ -0,0 +1,1340 @@
+<?xml version="1.0" encoding="utf-8" standalone="yes"?>
+<MicomToolCommonProjectFile Version="1.00">
+  <CreatorType Name="CubeSuite+" Version="V8.07.00  [01 Dec 2021]" />
+  <Placeholders>
+    <PlaceholderPrefix>%</PlaceholderPrefix>
+    <PlaceholderPostfix>%</PlaceholderPostfix>
+  </Placeholders>
+  <Project Name="K80" Type="Application">
+    <Files>
+      <Path>cstart.asm</Path>
+      <Path>stkinit.asm</Path>
+      <Path>iodefine.h</Path>
+      <Category Name="Code Generator">
+        <Path>r_main.c</Path>
+        <Path>r_systeminit.c</Path>
+        <Path>r_cg_cgc.c</Path>
+        <Path>r_cg_cgc_user.c</Path>
+        <Path>r_cg_port.c</Path>
+        <Path>r_cg_port_user.c</Path>
+        <Path>r_cg_serial.c</Path>
+        <Path>r_cg_serial_user.c</Path>
+        <Path>r_cg_timer.c</Path>
+        <Path>r_cg_timer_user.c</Path>
+        <Path>r_cg_wdt.c</Path>
+        <Path>r_cg_wdt_user.c</Path>
+        <Path>r_cg_macrodriver.h</Path>
+        <Path>r_cg_userdefine.h</Path>
+        <Path>r_cg_cgc.h</Path>
+        <Path>r_cg_port.h</Path>
+        <Path>r_cg_serial.h</Path>
+        <Path>r_cg_timer.h</Path>
+        <Path>r_cg_wdt.h</Path>
+      </Category>
+      <Path>appTask.c</Path>
+      <Path>event.c</Path>
+      <Path>hwCtrl.c</Path>
+    </Files>
+    <DebugOptions>
+      <DebugTool>Simulator</DebugTool>
+      <ConnectSettings>
+        <MainClock>4000000</MainClock>
+      </ConnectSettings>
+      <DebugToolSettings />
+    </DebugOptions>
+    <Device Series="RL78">R5F10268</Device>
+    <BuildOptions Name="CC-RL" Version="V1.11.00">
+      <BuildMode Name="DefaultBuild" Active="True">
+        <LinkOrder>
+          <Path>DefaultBuild\cstart.obj</Path>
+          <Path>DefaultBuild\stkinit.obj</Path>
+          <Path>DefaultBuild\r_main.obj</Path>
+          <Path>DefaultBuild\r_systeminit.obj</Path>
+          <Path>DefaultBuild\r_cg_cgc.obj</Path>
+          <Path>DefaultBuild\r_cg_cgc_user.obj</Path>
+          <Path>DefaultBuild\r_cg_port.obj</Path>
+          <Path>DefaultBuild\r_cg_port_user.obj</Path>
+          <Path>DefaultBuild\r_cg_serial.obj</Path>
+          <Path>DefaultBuild\r_cg_serial_user.obj</Path>
+          <Path>DefaultBuild\r_cg_timer.obj</Path>
+          <Path>DefaultBuild\r_cg_timer_user.obj</Path>
+          <Path>DefaultBuild\r_cg_wdt.obj</Path>
+          <Path>DefaultBuild\r_cg_wdt_user.obj</Path>
+          <Path>DefaultBuild\appTask.obj</Path>
+          <Path>DefaultBuild\event.obj</Path>
+          <Path>DefaultBuild\hwCtrl.obj</Path>
+        </LinkOrder>
+        <CommonOptions>
+          <IncludePathForC>.</IncludePathForC>
+        </CommonOptions>
+        <GeneralOptions>
+          <SimultaneouslyBuild>False</SimultaneouslyBuild>
+        </GeneralOptions>
+        <CompileOptions>
+          <Option>-cpu=S2</Option>
+          <Option>-obj_path=%BuildModeName%</Option>
+          <Option>-dev=%MicomToolPath%\Device\RL78\Devicefile\DR5F10268.DVF</Option>
+          <Option>-g</Option>
+          <Option>-g_line</Option>
+          <Option>-I .</Option>
+          <Option>-far_rom</Option>
+          <Option>-c</Option>
+        </CompileOptions>
+        <AssembleOptions>
+          <Option>-cpu=S2</Option>
+          <Option>-obj_path=%BuildModeName%</Option>
+          <Option>-dev=%MicomToolPath%\Device\RL78\Devicefile\DR5F10268.DVF</Option>
+          <Option>-g</Option>
+          <Option>-c</Option>
+        </AssembleOptions>
+        <LinkOptions>
+          <Option>-SECURITY_ID=00000000000000000000</Option>
+          <Option>-DEVICE=%MicomToolPath%\Device\RL78\Devicefile\DR5F10268.DVF</Option>
+          <Option>-DEBug</Option>
+          <Option>-NOCOmpress</Option>
+          <Option>-NOOPtimize</Option>
+          <Option>-OUtput=%BuildModeName%\%ProjectName%.abs</Option>
+          <Option>-LIBrary=%MicomToolPath%\CC-RL\V1.11.00\lib\rl78cm4s.lib</Option>
+          <Option>-LIBrary=%MicomToolPath%\CC-RL\V1.11.00\lib\malloc_n.lib</Option>
+          <Option>-LIBrary=%MicomToolPath%\CC-RL\V1.11.00\lib\rl78cm4r.lib</Option>
+          <Option>-OCDBG=04</Option>
+          <Option>-USER_OPT_BYTE=7A47E0</Option>
+          <Option>-LISt=%BuildModeName%\%ProjectName%.map</Option>
+          <Option>-AUTO_SECTION_LAYOUT</Option>
+          <Option>-ROm=.data=.dataR</Option>
+          <Option>-ROm=.sdata=.sdataR</Option>
+          <Option>-NOMessage</Option>
+          <Option>-MEMory=High</Option>
+          <Option>-NOLOgo</Option>
+          <Option>-END</Option>
+          <Option>-Input=%BuildModeName%\%ProjectName%.abs</Option>
+          <Option>-DEVICE=%MicomToolPath%\Device\RL78\Devicefile\DR5F10268.DVF</Option>
+          <Option>-OUtput=%BuildModeName%\%ProjectName%.mot</Option>
+          <Option>-FOrm=Stype</Option>
+          <Option>-NOMessage</Option>
+          <Option>-EXIt</Option>
+        </LinkOptions>
+        <IOHeaderGenerationOptions>
+          <Option>-df=%MicomToolPath%\Device\RL78\Devicefile\DR5F10268.DVF</Option>
+          <Option>-o=%ProjectDir%\iodefine.h</Option>
+          <Option>-f</Option>
+          <UpdateIOMode>None</UpdateIOMode>
+        </IOHeaderGenerationOptions>
+      </BuildMode>
+    </BuildOptions>
+    <Extension_CodePart2>
+      <CodeGeneratorData>&lt;RL78G12&gt;
+  &lt;VAR&gt;
+    &lt;fCLK Name="fCLK" Value="24" Comment="4M" Trigger="fCLK"&gt;
+      &lt;Effect&gt;
+        &lt;ADC /&gt;
+        &lt;SAU0 /&gt;
+        &lt;IICA0 /&gt;
+        &lt;TAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fCLK&gt;
+    &lt;fIH Name="fIH" Value="24" Comment="32M" /&gt;
+    &lt;fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"&gt;
+      &lt;Effect&gt;
+        &lt;TAU0 /&gt;
+        &lt;PCLBUZ0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fSUB&gt;
+    &lt;fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"&gt;
+      &lt;Effect&gt;
+        &lt;RTC /&gt;
+        &lt;WDT /&gt;
+        &lt;TAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fIL&gt;
+    &lt;fRTC Name="fRTC" Value="0" Comment="0k" Trigger="fIT"&gt;
+      &lt;Effect&gt;
+        &lt;RTC /&gt;
+        &lt;IT /&gt;
+      &lt;/Effect&gt;
+    &lt;/fRTC&gt;
+    &lt;fMAIN Name="fMAIN" Value="24" Comment="32M" Trigger="fMAIN"&gt;
+      &lt;Effect&gt;
+        &lt;PCLBUZ0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fMAIN&gt;
+    &lt;fINTTM02 Name="fINTTM02" Value="0" Comment="0M" Trigger="INTTM02"&gt;
+      &lt;Effect&gt;
+        &lt;SAU0 /&gt;
+      &lt;/Effect&gt;
+    &lt;/fINTTM02&gt;
+    &lt;fCLKSource Name="fCLKSource" Text="fIH" /&gt;
+    &lt;RESET_pin Chip="RL78G12_20pin,RL78G12_24pin" Name="RESET_pin" Text="false" Trigger="RESET_pin"&gt;
+      &lt;Effect&gt;
+        &lt;PORT /&gt;
+      &lt;/Effect&gt;
+    &lt;/RESET_pin&gt;
+    &lt;VDD_MIN Name="VDD_MIN" Value="2.7" Comment="4.0V" Trigger="VDD"&gt;
+      &lt;Effect&gt;
+        &lt;PCLBUZ0 /&gt;
+        &lt;PCLBUZ1 /&gt;
+        &lt;IICA0 /&gt;
+        &lt;SAU0 /&gt;
+        &lt;SAU1 /&gt;
+      &lt;/Effect&gt;
+    &lt;/VDD_MIN&gt;
+    &lt;VDD_MAX Name="VDD_MAX" Value="3.6" Comment="5.5V" /&gt;
+    &lt;VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"&gt;
+      &lt;Effect&gt;
+        &lt;IICA0 /&gt;
+        &lt;SAU0 /&gt;
+        &lt;SAU1 /&gt;
+        &lt;ADC /&gt;
+      &lt;/Effect&gt;
+    &lt;/VDDValue&gt;
+    &lt;VDD Name="VDD" Text="false" Comment="used" /&gt;
+    &lt;AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="" /&gt;
+    &lt;ADC_ADS_VALUE Name="ADC_ADS_VALUE" Text="" /&gt;
+    &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC00&gt;
+    &lt;IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC01&gt;
+    &lt;IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC10&gt;
+    &lt;IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC11&gt;
+    &lt;IIC20 Name="IIC20" Text="false" Comment="unused" Trigger="IIC20"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC20&gt;
+    &lt;IIC21 Name="IIC21" Text="false" Comment="unused" Trigger="IIC21"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IIC21&gt;
+    &lt;IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"&gt;
+      &lt;Effect&gt;
+        &lt;PORT Forcible="" /&gt;
+      &lt;/Effect&gt;
+    &lt;/IICA0&gt;
+    &lt;ProjectName Name="PrjName" Text="K80" /&gt;
+    &lt;ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\K80\code\K80_CODE" /&gt;
+    &lt;ProjectKind Name="PrjKind" Text="Project78K0R" /&gt;
+    &lt;DeviceName Name="DeviceName" Fixed="" Text="RL78G12" /&gt;
+    &lt;MCUName Name="MCUName" Text="RL78G12_20pin" /&gt;
+    &lt;ChipName Name="ChipName" Text="R5F10268" /&gt;
+    &lt;ChipID Name="ChipID" Text="R5F10268" /&gt;
+    &lt;MCUType Name="MCUType" Fixed="" Text="RL78" /&gt;
+    &lt;CPUCoreType Name="CPUCoreType" Fixed="" Text="0" /&gt;
+    &lt;Compiler Name="Compiler" Text="CCRL" /&gt;
+    &lt;UseSecurityId Name="GI" Text="0" /&gt;
+    &lt;SecurityId Name="GIValue" Text="00000000000000000000" /&gt;
+    &lt;LinkDirectiveFile Name="D0" Text="lk.dr" /&gt;
+    &lt;OnChipDebugOptionBytes Name="GO" Text="1" /&gt;
+    &lt;OnChipDebugOptionBytesValue Name="GOValue" Text="04" /&gt;
+    &lt;StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="1E00" /&gt;
+    &lt;SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /&gt;
+    &lt;UserOptionBytes Name="GB" Text="1" /&gt;
+    &lt;UserOptionBytesValue Name="GBValue" Text="7A47E0" /&gt;
+    &lt;RAMStartAddress Chip="R5F10268,R5F10278,R5F102A8" Name="RAMStartAddress" Fixed="" Text="000FFC00" /&gt;
+    &lt;RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /&gt;
+    &lt;ROMEndAddress Chip="R5F10268,R5F10278,R5F102A8" Name="ROMEndAddress" Fixed="" Text="00001FFF" /&gt;
+    &lt;MirrorROM Chip="R5F10266, R5F10366,R5F10267, R5F10277, R5F102A7,R5F10367, R5F10377, R5F103A7,R5F10268, R5F10278, R5F102A8,R5F10368, R5F10378, R5F103A8" Name="MirrorROM" Fixed="" Text="0" /&gt;
+    &lt;ADPC_AD Name="ADPC_AD" Value="-1" /&gt;
+    &lt;CodePath Name="CodePath" Text=".\" /&gt;
+    &lt;ReportType Name="ReportType" Text="Html" /&gt;
+    &lt;CreationDateType Name="CreationDateType" Text="OutputDate" /&gt;
+    &lt;GenerateType Name="GenerateType" Text="Merge" /&gt;
+    &lt;APIOutputType Name="APIOutputType" Text="Default" /&gt;
+    &lt;FileRegister Name="FileRegister" Text="Yes" /&gt;
+    &lt;PinReflect Name="PinReflect" Text="Reflected" /&gt;
+    &lt;PIOR0Value Name="PIOR0Value" Text="0" /&gt;
+    &lt;PIOR1Value Name="PIOR1Value" Text="1" /&gt;
+    &lt;PIOR2Value Name="PIOR2Value" Text="0" /&gt;
+    &lt;PIOR3Value Name="PIOR3Value" Text="0" /&gt;
+    &lt;PIOR4Value Name="PIOR4Value" Text="0" /&gt;
+    &lt;PIOR5Value Name="PIOR5Value" Text="0" /&gt;
+    &lt;GDataFlash Name="GDataFlash" Text="2" /&gt;
+    &lt;UseFDL Name="UseFDL" Text="no" /&gt;
+    &lt;DataFlash Name="DataFlash" Text="0" /&gt;
+    &lt;OCDROM Name="OCDROM" Text="Unused" /&gt;
+    &lt;OCDROM_Address Name="OCDROM_Address" Text="00001E00" /&gt;
+    &lt;OCDROM_Length Name="OCDROM_Length" Text="512" /&gt;
+    &lt;HasRRMRam Name="HasRRMRam" Text="" /&gt;
+    &lt;PrjVersion Name="PrjVersion" Text="1.2.0.1" /&gt;
+    &lt;ProductVersion Name="ProductVersion" Text="4.08.05.01" /&gt;
+    &lt;PIOR6Value Name="PIOR6Value" Text="0" /&gt;
+    &lt;TO02_PWM Name="TO02_PWM" Text="false" /&gt;
+    &lt;TO03_PWM Name="TO03_PWM" Text="false" /&gt;
+    &lt;LinkFileName Name="LinkFileName" Text="" /&gt;
+  &lt;/VAR&gt;
+  &lt;DIR&gt;
+    &lt;PIN&gt;
+      &lt;CGC&gt;
+        &lt;X1 Port="P121" Point="-" /&gt;
+        &lt;X2 Port="P122" Point="-" /&gt;
+        &lt;EXCLK Port="P122" Point="I" /&gt;
+        &lt;TOOL0 Port="P40" Point="I/O" /&gt;
+        &lt;_RESET Chip="RL78G12_20pin,RL78G12_24pin" Port="P125" RealName="_RESET" Point="I" /&gt;
+      &lt;/CGC&gt;
+      &lt;PORT&gt;
+        &lt;Port1 Chip="RL78G12_20pin,RL78G12_24pin" DIN="true" Pullup="true"&gt;
+          &lt;P10 Name="P10/ANI16/PCLBUZ0/_SCK00/SCL00" TTL="true" Nch="true" AltFunc="P10" Point="I/O" /&gt;
+          &lt;P11 Name="P11/ANI17/SI00/RXD0/SDA00/TOOLRXD" TTL="true" Nch="true" AltFunc="P11" Point="I/O" /&gt;
+          &lt;P12 Name="P12/ANI18/SO00/TXD0/TOOLTXD" Nch="true" AltFunc="P12" Point="I/O" /&gt;
+          &lt;P13 Name="P13/ANI19/TI00/TO00/INTP2" AltFunc="P13" Point="I/O" /&gt;
+          &lt;P14 Name="P14/ANI20/TI01/TO01/INTP3" AltFunc="P14" Point="I/O" /&gt;
+        &lt;/Port1&gt;
+        &lt;Port2 ADIN="true"&gt;
+          &lt;P20 Name="P20/ANI0/AVREFP" AltFunc="P20" Point="I/O" /&gt;
+          &lt;P21 Name="P21/ANI1/AVREFM" AltFunc="P21" Point="I/O" /&gt;
+          &lt;P22 Name="P22/ANI2" AltFunc="P22" Point="I/O" /&gt;
+          &lt;P23 Name="P23/ANI3" AltFunc="P23" Point="I/O" /&gt;
+        &lt;/Port2&gt;
+        &lt;Port4 Chip="RL78G12_20pin,RL78G12_24pin" Pullup="true"&gt;
+          &lt;P40 Name="P40/KR0/TOOL0" AltFunc="" Point="I/O" /&gt;
+          &lt;P41 Name="P41/ANI22/SO01/SDA01/TI02/TO02/INTP1" DIN="true" Nch="true" AltFunc="P41" Point="I/O" /&gt;
+          &lt;P42 Name="P42/ANI21/_SCK01/SCL01/TI03/TO03" DIN="true" AltFunc="P42" Point="I/O" /&gt;
+        &lt;/Port4&gt;
+        &lt;Port6 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+          &lt;P60 Name="P60/KR4/SCLA0" AltFunc="TXD0" Point="I/O" /&gt;
+          &lt;P61 Name="P61/KR5/SDAA0" AltFunc="RXD0" Point="I/O" /&gt;
+        &lt;/Port6&gt;
+        &lt;Port12 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+          &lt;P121 Name="P121/KR3/X1" AltFunc="" Point="I" /&gt;
+          &lt;P122 Name="P122/KR2/X2/EXCLK" AltFunc="P122" Point="I" /&gt;
+          &lt;P125 Name="P125/KR1/SI01/_RESET" Pullup="true" AltFunc="" Point="I" /&gt;
+        &lt;/Port12&gt;
+        &lt;Port13&gt;
+          &lt;P137 Name="P137/INTP0" AltFunc="P137" Point="I" /&gt;
+        &lt;/Port13&gt;
+      &lt;/PORT&gt;
+      &lt;INTC&gt;
+        &lt;INTP&gt;
+          &lt;INTP0 no="1" Point="I" /&gt;
+          &lt;INTP1 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /&gt;
+          &lt;INTP2 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P13" Point="I" /&gt;
+          &lt;INTP3 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P14" Point="I" /&gt;
+        &lt;/INTP&gt;
+        &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+          &lt;KR0 Port="P40" Point="I" /&gt;
+          &lt;KR1 Port="P125" Point="I" /&gt;
+          &lt;KR2 Port="P122" Point="I" /&gt;
+          &lt;KR3 Port="P121" Point="I" /&gt;
+          &lt;KR4 Port="P60" Point="I" /&gt;
+          &lt;KR5 Port="P61" Point="I" /&gt;
+        &lt;/KEY&gt;
+      &lt;/INTC&gt;
+      &lt;ADC&gt;
+        &lt;ANI0 Port="P20" Point="I" /&gt;
+        &lt;ANI1 Port="P21" Point="I" /&gt;
+        &lt;ANI2 Port="P22" Point="I" /&gt;
+        &lt;ANI3 Port="P23" Point="I" /&gt;
+        &lt;ANI16 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="I" /&gt;
+        &lt;ANI17 Chip="RL78G12_20pin,RL78G12_24pin" Port="P11" Point="I" /&gt;
+        &lt;ANI18 Chip="RL78G12_20pin,RL78G12_24pin" Port="P12" Point="I" /&gt;
+        &lt;ANI19 Chip="RL78G12_20pin,RL78G12_24pin" Port="P13" Point="I" /&gt;
+        &lt;ANI20 Chip="RL78G12_20pin,RL78G12_24pin" Port="P14" Point="I" /&gt;
+        &lt;ANI21 Chip="RL78G12_20pin,RL78G12_24pin" Port="P42" Point="I" /&gt;
+        &lt;ANI22 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /&gt;
+        &lt;AVREFP Port="P20" Point="I" /&gt;
+        &lt;AVREFM Port="P21" Point="I" /&gt;
+        &lt;ANALOG_0 Port="P20" RealName="ANI0/AVREFP" Point="I" /&gt;
+        &lt;ANALOG_1 Port="P21" RealName="ANI1/AVREFM" Point="I" /&gt;
+        &lt;ANALOG_2 Port="P22" RealName="ANI2" Point="I" /&gt;
+        &lt;ANALOG_3 Port="P23" RealName="ANI3" Point="I" /&gt;
+      &lt;/ADC&gt;
+      &lt;Serial&gt;
+        &lt;SAU0&gt;
+          &lt;UART0&gt;
+            &lt;RXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P61" RealName="RxD0" Point="I" /&gt;
+            &lt;TXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P60" RealName="TxD0" Point="O" /&gt;
+          &lt;/UART0&gt;
+          &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+            &lt;SO00 Port="P12" Point="O" /&gt;
+            &lt;SI00 Port="P11" Point="I" /&gt;
+            &lt;SCK00 Port="P10" RealName="_SCK00" Point="I/O" /&gt;
+          &lt;/CSI00&gt;
+          &lt;CSI01 Chip="RL78G12_20pin"&gt;
+            &lt;SO01 Port="P41" Point="O" /&gt;
+            &lt;SI01 Port="P125" Point="I" /&gt;
+            &lt;SCK01 Port="P42" RealName="_SCK01" Point="I/O" /&gt;
+          &lt;/CSI01&gt;
+          &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin"&gt;
+            &lt;SCL00 Port="P10" Point="I/O" CheckNch="true" /&gt;
+            &lt;SDA00 Port="P11" Point="I/O" CheckNch="true" /&gt;
+          &lt;/IIC00&gt;
+          &lt;IIC01 Chip="RL78G12_20pin"&gt;
+            &lt;SCL01 Port="P42" Point="I/O" CheckNch="true" /&gt;
+            &lt;SDA01 Port="P41" Point="I/O" CheckNch="true" /&gt;
+          &lt;/IIC01&gt;
+        &lt;/SAU0&gt;
+        &lt;IICA0&gt;
+          &lt;SCLA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P60" Point="I/O" /&gt;
+          &lt;SDAA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P61" Point="I/O" /&gt;
+        &lt;/IICA0&gt;
+      &lt;/Serial&gt;
+      &lt;TAU&gt;
+        &lt;TAU0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR2="0"&gt;
+          &lt;Channel0&gt;
+            &lt;TI00 Port="P13" Point="I" /&gt;
+            &lt;TO00 Port="P13" Point="O" /&gt;
+          &lt;/Channel0&gt;
+          &lt;Channel1&gt;
+            &lt;TI01 Port="P14" Point="I" /&gt;
+            &lt;TO01 Port="P14" Point="O" /&gt;
+          &lt;/Channel1&gt;
+          &lt;Channel2&gt;
+            &lt;TI02 Port="P41" Point="I" /&gt;
+            &lt;TO02 Port="P41" Point="O" /&gt;
+          &lt;/Channel2&gt;
+          &lt;Channel3&gt;
+            &lt;TI03 Port="P42" Point="I" /&gt;
+            &lt;TO03 Port="P42" Point="O" /&gt;
+          &lt;/Channel3&gt;
+        &lt;/TAU0&gt;
+      &lt;/TAU&gt;
+      &lt;PCLBUZ&gt;
+        &lt;PCLBUZ0&gt;
+          &lt;PCLBUZ0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="O" /&gt;
+        &lt;/PCLBUZ0&gt;
+      &lt;/PCLBUZ&gt;
+      &lt;Others&gt;
+        &lt;VDD AltFunc="VDD" Point="-" /&gt;
+        &lt;VSS AltFunc="VSS" Point="-" /&gt;
+      &lt;/Others&gt;
+    &lt;/PIN&gt;
+    &lt;INT&gt;
+      &lt;INTC&gt;
+        &lt;INTP&gt;
+          &lt;INTP0 InUse="0" ISR="r_intc0_interrupt" /&gt;
+          &lt;INTP1 InUse="0" ISR="r_intc1_interrupt" /&gt;
+          &lt;INTP2 InUse="0" ISR="r_intc2_interrupt" /&gt;
+          &lt;INTP3 InUse="0" ISR="r_intc3_interrupt" /&gt;
+        &lt;/INTP&gt;
+        &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+          &lt;INTKR InUse="0" ISR="r_key_interrupt" /&gt;
+        &lt;/KEY&gt;
+      &lt;/INTC&gt;
+      &lt;Serial&gt;
+        &lt;SAU0&gt;
+          &lt;INTCSI00 InUse="0" ISR="r_csi00_interrupt" /&gt;
+          &lt;INTCSI01 InUse="0" ISR="r_csi01_interrupt" /&gt;
+          &lt;INTCSI10 InUse="0" ISR="r_csi10_interrupt" /&gt;
+          &lt;INTCSI11 InUse="0" ISR="r_csi11_interrupt" /&gt;
+          &lt;INTST0 InUse="1" ISR="r_uart0_interrupt_send" /&gt;
+          &lt;INTST1 InUse="0" ISR="r_uart1_interrupt_send" /&gt;
+          &lt;INTSRE0 InUse="0" ISR="r_uart0_interrupt_error" /&gt;
+          &lt;INTSRE1 InUse="0" ISR="r_uart1_interrupt_error" /&gt;
+          &lt;INTSR0 InUse="1" ISR="r_uart0_interrupt_receive" /&gt;
+          &lt;INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /&gt;
+          &lt;INTIIC00 InUse="0" ISR="r_iic00_interrupt" /&gt;
+          &lt;INTIIC01 InUse="0" ISR="r_iic01_interrupt" /&gt;
+          &lt;INTIIC10 InUse="0" ISR="r_iic10_interrupt" /&gt;
+          &lt;INTIIC11 InUse="0" ISR="r_iic11_interrupt" /&gt;
+        &lt;/SAU0&gt;
+        &lt;SAU1&gt;
+          &lt;INTCSI20 InUse="0" ISR="r_csi20_interrupt" /&gt;
+          &lt;INTCSI21 InUse="0" ISR="r_csi21_interrupt" /&gt;
+          &lt;INTCSI30 InUse="0" ISR="r_csi30_interrupt" /&gt;
+          &lt;INTCSI31 InUse="0" ISR="r_csi31_interrupt" /&gt;
+          &lt;INTST2 InUse="0" ISR="r_uart2_interrupt_send" /&gt;
+          &lt;INTST3 InUse="0" ISR="r_uart3_interrupt_send" /&gt;
+          &lt;INTSRE2 InUse="0" ISR="r_uart2_interrupt_error" /&gt;
+          &lt;INTSRE3 InUse="0" ISR="r_uart3_interrupt_error" /&gt;
+          &lt;INTSR2 InUse="0" ISR="r_uart2_interrupt_receive" /&gt;
+          &lt;INTSR3 InUse="0" ISR="r_uart3_interrupt_receive" /&gt;
+          &lt;INTIIC20 InUse="0" ISR="r_iic20_interrupt" /&gt;
+          &lt;INTIIC21 InUse="0" ISR="r_iic21_interrupt" /&gt;
+          &lt;INTIIC30 InUse="0" ISR="r_iic30_interrupt" /&gt;
+          &lt;INTIIC31 InUse="0" ISR="r_iic31_interrupt" /&gt;
+        &lt;/SAU1&gt;
+        &lt;IICA0&gt;
+          &lt;INTIICA0 InUse="0" ISR="r_iica0_interrupt" /&gt;
+        &lt;/IICA0&gt;
+      &lt;/Serial&gt;
+      &lt;ADC&gt;
+        &lt;INTAD InUse="0" ISR="r_adc_interrupt" IsDMATrigger="true" /&gt;
+      &lt;/ADC&gt;
+      &lt;TAU&gt;
+        &lt;TAU0&gt;
+          &lt;Channel0&gt;
+            &lt;INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /&gt;
+          &lt;/Channel0&gt;
+          &lt;Channel1&gt;
+            &lt;INTTM01 InUse="0" ISR="r_tau0_channel1_interrupt" /&gt;
+            &lt;INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /&gt;
+          &lt;/Channel1&gt;
+          &lt;Channel2&gt;
+            &lt;INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /&gt;
+          &lt;/Channel2&gt;
+          &lt;Channel3&gt;
+            &lt;INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /&gt;
+            &lt;INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /&gt;
+          &lt;/Channel3&gt;
+          &lt;Channel4&gt;
+            &lt;INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /&gt;
+          &lt;/Channel4&gt;
+          &lt;Channel5&gt;
+            &lt;INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /&gt;
+          &lt;/Channel5&gt;
+          &lt;Channel6&gt;
+            &lt;INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /&gt;
+          &lt;/Channel6&gt;
+          &lt;Channel7&gt;
+            &lt;INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /&gt;
+          &lt;/Channel7&gt;
+        &lt;/TAU0&gt;
+      &lt;/TAU&gt;
+      &lt;IT&gt;
+        &lt;INTIT InUse="0" ISR="r_it_interrupt" /&gt;
+      &lt;/IT&gt;
+      &lt;DMAC&gt;
+        &lt;DMA0&gt;
+          &lt;INTDMA0 InUse="0" ISR="r_dmac0_interrupt" /&gt;
+        &lt;/DMA0&gt;
+        &lt;DMA1&gt;
+          &lt;INTDMA1 InUse="0" ISR="r_dmac1_interrupt" /&gt;
+        &lt;/DMA1&gt;
+      &lt;/DMAC&gt;
+      &lt;WDT&gt;
+        &lt;INTWDTI InUse="0" ISR="r_wdt_interrupt" /&gt;
+      &lt;/WDT&gt;
+      &lt;LVD&gt;
+        &lt;INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /&gt;
+      &lt;/LVD&gt;
+    &lt;/INT&gt;
+    &lt;FUNC&gt;
+      &lt;Common&gt;
+        &lt;r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"&gt;
+          &lt;Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /&gt;
+          &lt;main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /&gt;
+          &lt;R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /&gt;
+        &lt;/r_main.c&gt;
+        &lt;r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"&gt;
+          &lt;Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /&gt;
+          &lt;R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /&gt;
+          &lt;hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /&gt;
+          &lt;__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /&gt;
+        &lt;/r_systeminit.c&gt;
+        &lt;r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"&gt;
+          &lt;Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /&gt;
+          &lt;R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /&gt;
+          &lt;HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /&gt;
+        &lt;/r_hardware_setup.c&gt;
+        &lt;r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"&gt;
+          &lt;Type R_Dummy="void R_Dummy(void)" /&gt;
+          &lt;R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /&gt;
+        &lt;/r_cg_vector_table.c&gt;
+        &lt;r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /&gt;
+        &lt;r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /&gt;
+        &lt;r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /&gt;
+        &lt;r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /&gt;
+        &lt;iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /&gt;
+        &lt;mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /&gt;
+        &lt;r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /&gt;
+      &lt;/Common&gt;
+      &lt;CGC&gt;
+        &lt;r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(clock_mode_t mode)" /&gt;
+          &lt;R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /&gt;
+          &lt;R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /&gt;
+        &lt;/r_cg_cgc.c&gt;
+        &lt;r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" /&gt;
+          &lt;R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /&gt;
+          &lt;R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /&gt;
+        &lt;/r_cg_cgc_user.c&gt;
+        &lt;r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /&gt;
+        &lt;r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"&gt;
+          &lt;Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /&gt;
+          &lt;R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /&gt;
+          &lt;R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /&gt;
+          &lt;R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /&gt;
+          &lt;R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /&gt;
+          &lt;R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /&gt;
+          &lt;R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /&gt;
+          &lt;R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /&gt;
+          &lt;R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /&gt;
+        &lt;/r_cg_pfdl.c&gt;
+        &lt;r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /&gt;
+      &lt;/CGC&gt;
+      &lt;PORT&gt;
+        &lt;r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_PORT_Create="void R_PORT_Create(void)" /&gt;
+          &lt;R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /&gt;
+        &lt;/r_cg_port.c&gt;
+        &lt;r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /&gt;
+          &lt;R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /&gt;
+        &lt;/r_cg_port_user.c&gt;
+        &lt;r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /&gt;
+      &lt;/PORT&gt;
+      &lt;INTC&gt;
+        &lt;r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /&gt;
+          &lt;INTP&gt;
+            &lt;R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="" Init="2" InitMode="" /&gt;
+            &lt;INTP0&gt;
+              &lt;R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP0&gt;
+            &lt;INTP1&gt;
+              &lt;R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP1&gt;
+            &lt;INTP2&gt;
+              &lt;R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP2&gt;
+            &lt;INTP3&gt;
+              &lt;R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="" /&gt;
+              &lt;R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="" /&gt;
+            &lt;/INTP3&gt;
+          &lt;/INTP&gt;
+          &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+            &lt;R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /&gt;
+            &lt;R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /&gt;
+            &lt;R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /&gt;
+          &lt;/KEY&gt;
+        &lt;/r_cg_intc.c&gt;
+        &lt;r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" R_INTC0_Interrupt="__interrupt static void r_intc0_interrupt(void)" R_INTC1_Interrupt="__interrupt static void r_intc1_interrupt(void)" R_INTC2_Interrupt="__interrupt static void r_intc2_interrupt(void)" R_INTC3_Interrupt="__interrupt static void r_intc3_interrupt(void)" R_INTC4_Interrupt="__interrupt static void r_intc4_interrupt(void)" R_INTC5_Interrupt="__interrupt static void r_intc5_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" R_KEY_Interrupt="__interrupt static void r_key_interrupt(void)" /&gt;
+          &lt;INTP&gt;
+            &lt;R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="" /&gt;
+            &lt;r_intc0_interrupt UserName="r_intc0_interrupt" LibName="R_INTC0_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc1_interrupt UserName="r_intc1_interrupt" LibName="R_INTC1_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc2_interrupt UserName="r_intc2_interrupt" LibName="R_INTC2_Interrupt" INTHandle="" InUse="" /&gt;
+            &lt;r_intc3_interrupt UserName="r_intc3_interrupt" LibName="R_INTC3_Interrupt" INTHandle="" InUse="" /&gt;
+          &lt;/INTP&gt;
+          &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin,"&gt;
+            &lt;R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /&gt;
+            &lt;r_key_interrupt UserName="r_key_interrupt" LibName="R_KEY_Interrupt" INTHandle="" InUse="" /&gt;
+          &lt;/KEY&gt;
+        &lt;/r_cg_intc_user.c&gt;
+        &lt;r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="" /&gt;
+      &lt;/INTC&gt;
+      &lt;Serial&gt;
+        &lt;r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t * const rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t * const tx_buf, uint16_t tx_num, uint8_t * const rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" IICn_Init="void IICn_Init(void)" IICn_MasterSendStart="MD_STATUS IICn_MasterSendStart(uint8_t adr, uint8_t * const tx_buf, USHORT tx_num, uint8_t wait)" IICn_MasterReceiveStart="MD_STATUS IICn_MasterReceiveStart(uint8_t adr, uint8_t * const rx_buf, USHORT rx_num, uint8_t wait)" IICn_SlaveSendStart="void IICn_SlaveSendStart(uint8_t * const tx_buf, USHORT tx_num)" IICn_SlaveReceiveStart="void IICn_SlaveReceiveStart(uint8_t * const rx_buf, USHORT rx_num)" IICn_Stop="void IICn_Stop(void)" IICn_StopCondition="void IICn_StopCondition(void)" IICn_PowerOff="void IICn_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /&gt;
+          &lt;SAU0 InUse=""&gt;
+            &lt;R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="1" Init="1" InitMode="" /&gt;
+            &lt;R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /&gt;
+            &lt;R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /&gt;
+            &lt;R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /&gt;
+            &lt;UART0 InUse=""&gt;
+              &lt;R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="1" InitMode="" /&gt;
+              &lt;R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="1" /&gt;
+              &lt;R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="1" /&gt;
+              &lt;R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="1" /&gt;
+              &lt;R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="1" /&gt;
+            &lt;/UART0&gt;
+            &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /&gt;
+              &lt;R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /&gt;
+              &lt;R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /&gt;
+              &lt;R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /&gt;
+              &lt;R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /&gt;
+            &lt;/CSI00&gt;
+            &lt;CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /&gt;
+              &lt;R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /&gt;
+              &lt;R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /&gt;
+              &lt;R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /&gt;
+              &lt;R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /&gt;
+            &lt;/CSI01&gt;
+            &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /&gt;
+              &lt;R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /&gt;
+              &lt;R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /&gt;
+              &lt;R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /&gt;
+              &lt;R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /&gt;
+            &lt;/IIC00&gt;
+            &lt;IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /&gt;
+              &lt;R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /&gt;
+              &lt;R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /&gt;
+              &lt;R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /&gt;
+              &lt;R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /&gt;
+              &lt;R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /&gt;
+            &lt;/IIC01&gt;
+          &lt;/SAU0&gt;
+          &lt;IICA0 InUse=""&gt;
+            &lt;R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /&gt;
+            &lt;R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /&gt;
+            &lt;R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /&gt;
+            &lt;R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /&gt;
+            &lt;R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /&gt;
+            &lt;R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /&gt;
+            &lt;R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /&gt;
+            &lt;R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /&gt;
+            &lt;R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /&gt;
+          &lt;/IICA0&gt;
+        &lt;/r_cg_serial.c&gt;
+        &lt;r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" R_UARTn_Interrupt_Receive="__interrupt static void R_UARTn_Interrupt_Receive(void)" R_UARTn_Interrupt_Error="__interrupt static void R_UARTn_Interrupt_Error(void)" R_UARTn_Interrupt_Send="__interrupt static void R_UARTn_Interrupt_Send(void)" R_UARTn_Callback_SendEnd="static void R_UARTn_Callback_SendEnd(void)" R_UARTn_Callback_ReceiveEnd="static void R_UARTn_Callback_ReceiveEnd(void)" R_UARTn_Callback_Error="static void R_UARTn_Callback_Error(uint8_t err_type)" R_UARTn_Callback_SoftwareOverRun="static void R_UARTn_Callback_SoftwareOverRun(uint16_t rx_data)" R_CSIn_Interrupt="__interrupt static void R_CSIn_Interrupt(void)" R_CSIn_Callback_ReceiveEnd="static void R_CSIn_Callback_ReceiveEnd(void)" R_CSIn_Callback_Error="static void R_CSIn_Callback_Error(uint8_t err_type)" R_CSIn_Callback_SendEnd="static void R_CSIn_Callback_SendEnd(void)" R_IICn_Interrupt="__interrupt static void R_IICn_Interrupt(void)" R_IICn_Callback_Master_ReceiveEnd="static void R_IICn_Callback_Master_ReceiveEnd(void)" R_IICn_Callback_Master_SendEnd="static void R_IICn_Callback_Master_SendEnd(void)" R_IICn_Callback_Master_Error="static void R_IICn_Callback_Master_Error(MD_STATUS flag)" IICn_MasterSendEndCallback="static void IICn_MasterSendEndCallback(void)" IICn_MasterReceiveEndCallback="static void IICn_MasterReceiveEndCallback(void)" IICn_MasterErrorCallback="static void IICn_MasterErrorCallback(MD_STATUS flag)" IICn_SlaveErrorCallback="static void IICn_SlaveErrorCallback(MD_STATUS flag)" IICn_GetStopConditionCallback="static void IICn_GetStopConditionCallback(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static void r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /&gt;
+          &lt;SAU0 InUse=""&gt;
+            &lt;R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /&gt;
+            &lt;UART0 InUse=""&gt;
+              &lt;r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="R_UARTn_Interrupt_Receive" InUse="1" /&gt;
+              &lt;r_uart0_interrupt_error UserName="r_uart0_interrupt_error" INTHandle="" LibName="R_UARTn_Interrupt_Error" InUse="0" /&gt;
+              &lt;r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="R_UARTn_Interrupt_Send" InUse="1" /&gt;
+              &lt;r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="R_UARTn_Callback_ReceiveEnd" InUse="1" /&gt;
+              &lt;r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="R_UARTn_Callback_SendEnd" InUse="1" /&gt;
+              &lt;r_uart0_callback_error UserName="r_uart0_callback_error" LibName="R_UARTn_Callback_Error" InUse="1" /&gt;
+              &lt;r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="R_UARTn_Callback_SoftwareOverRun" InUse="1" /&gt;
+            &lt;/UART0&gt;
+            &lt;CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /&gt;
+              &lt;r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_csi00_callback_error UserName="r_csi00_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /&gt;
+              &lt;r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /&gt;
+            &lt;/CSI00&gt;
+            &lt;CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /&gt;
+              &lt;r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_csi01_callback_error UserName="r_csi01_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /&gt;
+              &lt;r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /&gt;
+            &lt;/CSI01&gt;
+            &lt;IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /&gt;
+              &lt;r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /&gt;
+            &lt;/IIC00&gt;
+            &lt;IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""&gt;
+              &lt;r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /&gt;
+              &lt;r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /&gt;
+            &lt;/IIC01&gt;
+          &lt;/SAU0&gt;
+          &lt;IICA0 InUse=""&gt;
+            &lt;R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /&gt;
+            &lt;r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /&gt;
+            &lt;r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /&gt;
+            &lt;r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /&gt;
+            &lt;r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /&gt;
+            &lt;r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /&gt;
+            &lt;r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /&gt;
+          &lt;/IICA0&gt;
+        &lt;/r_cg_serial_user.c&gt;
+        &lt;r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="1" /&gt;
+      &lt;/Serial&gt;
+      &lt;ADC&gt;
+        &lt;r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="0"&gt;
+          &lt;Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /&gt;
+          &lt;R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="0" Init="1" InitMode="" /&gt;
+          &lt;R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="0" /&gt;
+          &lt;R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="0" /&gt;
+          &lt;R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="0" /&gt;
+          &lt;R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="0" /&gt;
+          &lt;R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="0" /&gt;
+          &lt;R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /&gt;
+          &lt;R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /&gt;
+          &lt;R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /&gt;
+          &lt;R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /&gt;
+          &lt;R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /&gt;
+          &lt;R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /&gt;
+        &lt;/r_cg_adc.c&gt;
+        &lt;r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="0"&gt;
+          &lt;Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /&gt;
+          &lt;R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /&gt;
+          &lt;r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_adc_user.c&gt;
+        &lt;r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="0" /&gt;
+      &lt;/ADC&gt;
+      &lt;TAU&gt;
+        &lt;r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" /&gt;
+          &lt;TAU0&gt;
+            &lt;R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /&gt;
+            &lt;R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /&gt;
+            &lt;Channel0 InUse=""&gt;
+              &lt;R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /&gt;
+              &lt;R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /&gt;
+              &lt;R_TAU0_Channel0_Get_PulseWidth UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+              &lt;R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /&gt;
+            &lt;/Channel0&gt;
+            &lt;Channel1 InUse=""&gt;
+              &lt;R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+            &lt;/Channel1&gt;
+            &lt;Channel2 InUse=""&gt;
+              &lt;R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Get_PulseWidth UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+              &lt;R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /&gt;
+            &lt;/Channel2&gt;
+            &lt;Channel3 InUse=""&gt;
+              &lt;R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /&gt;
+              &lt;R_TAU0_Channel3_Get_PulseWidth UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /&gt;
+            &lt;/Channel3&gt;
+          &lt;/TAU0&gt;
+        &lt;/r_cg_timer.c&gt;
+        &lt;r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" /&gt;
+          &lt;TAU0&gt;
+            &lt;R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /&gt;
+            &lt;Channel0 InUse=""&gt;
+              &lt;r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /&gt;
+            &lt;/Channel0&gt;
+            &lt;Channel1 InUse=""&gt;
+              &lt;r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+              &lt;r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /&gt;
+            &lt;/Channel1&gt;
+            &lt;Channel2 InUse=""&gt;
+              &lt;r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+            &lt;/Channel2&gt;
+            &lt;Channel3 InUse=""&gt;
+              &lt;r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /&gt;
+              &lt;r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /&gt;
+            &lt;/Channel3&gt;
+          &lt;/TAU0&gt;
+        &lt;/r_cg_timer_user.c&gt;
+        &lt;r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /&gt;
+      &lt;/TAU&gt;
+      &lt;WDT&gt;
+        &lt;r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"&gt;
+          &lt;Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /&gt;
+          &lt;R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /&gt;
+          &lt;R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /&gt;
+        &lt;/r_cg_wdt.c&gt;
+        &lt;r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"&gt;
+          &lt;Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /&gt;
+          &lt;R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /&gt;
+          &lt;r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_wdt_user.c&gt;
+        &lt;r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /&gt;
+      &lt;/WDT&gt;
+      &lt;IT&gt;
+        &lt;r_cg_it.c UserName="r_cg_it.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_IT_Create="void R_IT_Create(void)" R_IT_Start="void R_IT_Start(void)" R_IT_Stop="void R_IT_Stop(void)" R_IT_Set_PowerOff="void R_IT_Set_PowerOff(void)" /&gt;
+          &lt;R_IT_Create UserName="R_IT_Create" LibName="R_IT_Create" InUse="" Init="1" InitMode="" /&gt;
+          &lt;R_IT_Start UserName="R_IT_Start" LibName="R_IT_Start" InUse="" /&gt;
+          &lt;R_IT_Stop UserName="R_IT_Stop" LibName="R_IT_Stop" InUse="" /&gt;
+          &lt;R_IT_Set_PowerOff UserName="R_IT_Set_PowerOff" LibName="R_IT_Set_PowerOff" InUse="" /&gt;
+        &lt;/r_cg_it.c&gt;
+        &lt;r_cg_it_user.c UserName="r_cg_it_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_IT_Create_UserInit="void R_IT_Create_UserInit(void)" r_it_interrupt="__interrupt static void r_it_interrupt(void)" /&gt;
+          &lt;R_IT_Create_UserInit UserName="R_IT_Create_UserInit" LibName="R_IT_Create_UserInit" InUse="" /&gt;
+          &lt;r_it_interrupt UserName="r_it_interrupt" INTHandle="" LibName="r_it_interrupt" InUse="" /&gt;
+        &lt;/r_cg_it_user.c&gt;
+        &lt;r_cg_it.h UserName="r_cg_it.h" LibName=".h" InUse="" /&gt;
+      &lt;/IT&gt;
+      &lt;PCLBUZ&gt;
+        &lt;r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /&gt;
+          &lt;PCLBUZ0 InUse=""&gt;
+            &lt;R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="" /&gt;
+            &lt;R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="" /&gt;
+          &lt;/PCLBUZ0&gt;
+        &lt;/r_cg_pclbuz.c&gt;
+        &lt;r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /&gt;
+          &lt;PCLBUZ0 InUse=""&gt;
+            &lt;R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="" Init="1" /&gt;
+          &lt;/PCLBUZ0&gt;
+        &lt;/r_cg_pclbuz_user.c&gt;
+        &lt;r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="" /&gt;
+      &lt;/PCLBUZ&gt;
+      &lt;DMAC&gt;
+        &lt;r_cg_dmac.c UserName="r_cg_dmac.c" LibName=".c" InUse=""&gt;
+          &lt;Type R_DMACn_Create="void R_DMACn_Create(void)" R_DMACn_Start="void R_DMACn_Start(void)" R_DMACn_Stop="void R_DMACn_Stop(void)" R_DMACn_Set_SoftwareTriggerOn="void R_DMACn_Set_SoftwareTriggerOn(void)" /&gt;
+          &lt;DMA0 InUse=""&gt;
+            &lt;R_DMAC0_Create UserName="R_DMAC0_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_DMAC0_Start UserName="R_DMAC0_Start" LibName="R_DMACn_Start" InUse="" /&gt;
+            &lt;R_DMAC0_Stop UserName="R_DMAC0_Stop" LibName="R_DMACn_Stop" InUse="" /&gt;
+            &lt;R_DMAC0_Set_SoftwareTriggerOn UserName="R_DMAC0_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /&gt;
+          &lt;/DMA0&gt;
+          &lt;DMA1 InUse=""&gt;
+            &lt;R_DMAC1_Create UserName="R_DMAC1_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /&gt;
+            &lt;R_DMAC1_Start UserName="R_DMAC1_Start" LibName="R_DMACn_Start" InUse="" /&gt;
+            &lt;R_DMAC1_Stop UserName="R_DMAC1_Stop" LibName="R_DMACn_Stop" InUse="" /&gt;
+            &lt;R_DMAC1_Set_SoftwareTriggerOn UserName="R_DMAC1_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /&gt;
+          &lt;/DMA1&gt;
+        &lt;/r_cg_dmac.c&gt;
+        &lt;r_cg_dmac_user.c UserName="r_cg_dmac_user.c" LibName="_user.c" InUse=""&gt;
+          &lt;Type R_DMACn_Create_UserInit="void R_DMACn_Create_UserInit(void)" r_dmacn_interrupt="__interrupt static void r_dmacn_interrupt(void)" /&gt;
+          &lt;DMA0&gt;
+            &lt;R_DMAC0_Create_UserInit UserName="R_DMAC0_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /&gt;
+            &lt;r_dmac0_interrupt UserName="r_dmac0_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /&gt;
+          &lt;/DMA0&gt;
+          &lt;DMA1&gt;
+            &lt;R_DMAC1_Create_UserInit UserName="R_DMAC1_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /&gt;
+            &lt;r_dmac1_interrupt UserName="r_dmac1_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /&gt;
+          &lt;/DMA1&gt;
+        &lt;/r_cg_dmac_user.c&gt;
+        &lt;r_cg_dmac.h UserName="r_cg_dmac.h" LibName=".h" InUse="" /&gt;
+      &lt;/DMAC&gt;
+      &lt;LVD&gt;
+        &lt;r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"&gt;
+          &lt;Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /&gt;
+          &lt;R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /&gt;
+          &lt;R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /&gt;
+        &lt;/r_cg_lvd.c&gt;
+        &lt;r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"&gt;
+          &lt;Type R_LVD_Creat_UserInit="void R_LVD_Creat_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /&gt;
+          &lt;R_LVD_Creat_UserInit UserName="R_LVD_Creat_UserInit" LibName="R_LVD_Creat_UserInit" InUse="0" /&gt;
+          &lt;r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /&gt;
+        &lt;/r_cg_lvd_user.c&gt;
+        &lt;r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /&gt;
+      &lt;/LVD&gt;
+    &lt;/FUNC&gt;
+    &lt;TAG&gt;
+      &lt;GlobleUserTag&gt;
+        &lt;cg_security9 Name="cg_security9" Value="00" /&gt;
+        &lt;cg_security7 Name="cg_security7" Value="00" /&gt;
+        &lt;cg_security5 Name="cg_security5" Value="00" /&gt;
+        &lt;ocdstart Name="ocdstart" Value="01E00" /&gt;
+        &lt;cg_security3 Name="cg_security3" Value="00" /&gt;
+        &lt;cg_security0 Name="cg_security0" Value="00" /&gt;
+        &lt;cg_security1 Name="cg_security1" Value="00" /&gt;
+        &lt;clock_option Name="clock_option" Value="E0" /&gt;
+        &lt;pior_value Name="pior_value" Value="02" /&gt;
+        &lt;cg_option Name="cg_option" Value="04" /&gt;
+        &lt;cg_security8 Name="cg_security8" Value="00" /&gt;
+        &lt;cg_security6 Name="cg_security6" Value="00" /&gt;
+        &lt;cg_security4 Name="cg_security4" Value="00" /&gt;
+        &lt;cg_security2 Name="cg_security2" Value="00" /&gt;
+        &lt;cg_iawctl_value Name="cg_iawctl_value" Value="00" /&gt;
+        &lt;lvi_option Name="lvi_option" Value="47" /&gt;
+        &lt;wdt_option Name="wdt_option" Value="7A" /&gt;
+      &lt;/GlobleUserTag&gt;
+    &lt;/TAG&gt;
+  &lt;/DIR&gt;
+  &lt;MACRO&gt;
+    &lt;CGC HelpID="CGC" Prepared="true" SetFlag="True" NeedRefresh="False"&gt;
+      &lt;CGC SetFlag="True" MacroName="cgc" /&gt;
+    &lt;/CGC&gt;
+    &lt;PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"&gt;
+      &lt;PORT SetFlag="True" MacroName="PORT" /&gt;
+    &lt;/PORT&gt;
+    &lt;INTC SetFlag="" HelpID="int" NeedRefresh="False"&gt;
+      &lt;INTP Accelerate="No" MacroName="INTP" /&gt;
+      &lt;KEY Chip="RL78G12_20pin,RL78G12_24pin," MacroName="KEY" /&gt;
+    &lt;/INTC&gt;
+    &lt;Serial SetFlag="True" HelpID="serial" NeedRefresh="False"&gt;
+      &lt;SAU0 Chip="RL78G12_20pin,RL78G12_24pin" Accelerate="No" MacroName="SAU" Channel="0" SetFlag="True" TabEnable="True"&gt;
+        &lt;Channel0 UART="0" CSI="00" IIC="00" Channel="0" /&gt;
+        &lt;Channel1 UART="0" CSI="01" IIC="01" Channel="1" /&gt;
+      &lt;/SAU0&gt;
+      &lt;IICA0 Accelerate="No" MacroName="IICA" Channel="0" TabEnable="True" /&gt;
+    &lt;/Serial&gt;
+    &lt;ADC SetFlag="False" HelpID="adc" NeedRefresh="False"&gt;
+      &lt;ADC SetFlag="False" MacroName="ADC" /&gt;
+    &lt;/ADC&gt;
+    &lt;TAU SetFlag="True" HelpID="timer" NeedRefresh="False"&gt;
+      &lt;TAU0 Accelerate="No" Chip="RL78G12_20pin,RL78G12_24pin" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3" SetFlag="True" /&gt;
+    &lt;/TAU&gt;
+    &lt;WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"&gt;
+      &lt;WDT SetFlag="True" MacroName="WDT" /&gt;
+    &lt;/WDT&gt;
+    &lt;IT SetFlag="" HelpID="intervaltimer" NeedRefresh="False"&gt;
+      &lt;IT MacroName="IntervalTM" /&gt;
+    &lt;/IT&gt;
+    &lt;PCLBUZ SetFlag="" HelpID="PCLBUZ" NeedRefresh="False"&gt;
+      &lt;PCLBUZ0 MacroName="PCLBUZ" Channel="0" /&gt;
+    &lt;/PCLBUZ&gt;
+    &lt;DMAC HelpID="dmac" SetFlag="" NeedRefresh="False"&gt;
+      &lt;DMA0 MacroName="DMAC" Channel="0" TabEnable="True" /&gt;
+      &lt;DMA1 MacroName="DMAC" Channel="1" TabEnable="True" /&gt;
+    &lt;/DMAC&gt;
+    &lt;LVD SetFlag="True" Prepared="true" HelpID="lvi" NeedRefresh="False"&gt;
+      &lt;LVD MacroName="LVD" SetFlag="True" /&gt;
+    &lt;/LVD&gt;
+  &lt;/MACRO&gt;
+  &lt;SETTING&gt;
+    &lt;CGC&gt;
+      &lt;setting name="PIOR_Setting" value="FIX" /&gt;
+      &lt;setting name="PIOR6" value="1" /&gt;
+      &lt;setting name="PIOR5" value="1" /&gt;
+      &lt;setting name="PIOR4" value="1" /&gt;
+      &lt;setting name="PIOR3" value="1" /&gt;
+      &lt;setting name="PIOR2" value="1" /&gt;
+      &lt;setting name="PIOR1" value="0" /&gt;
+      &lt;setting name="PIOR0" value="1" /&gt;
+      &lt;setting name="PIOR10" value="1" /&gt;
+      &lt;setting name="PIOR11" value="1" /&gt;
+      &lt;setting name="PIOR12" value="1" /&gt;
+      &lt;setting name="PIOR13" value="1" /&gt;
+      &lt;setting name="VDD" value="VDD0" /&gt;
+      &lt;setting name="EVDD" value="EVDD2" /&gt;
+      &lt;setting name="Main_system_clock" value="high-speed internal clock" /&gt;
+      &lt;setting name="High_speed_internal_oscillator" value="operation" /&gt;
+      &lt;setting name="High_speed_internal_frequency" value="8" /&gt;
+      &lt;setting name="High_speed_system_clock" value="stop" /&gt;
+      &lt;setting name="High_speed_system_input" value="X1" /&gt;
+      &lt;setting name="HighSpeedSystemStable" value="7" /&gt;
+      &lt;setting name="High_speed_system_clock_frequency" value="5" /&gt;
+      &lt;setting name="Sub_clock_operation" value="XT1" /&gt;
+      &lt;setting name="SubclockFrequency" value="32.768" /&gt;
+      &lt;setting name="XT1_oscillator_oscillation_mode" value="0" /&gt;
+      &lt;setting name="SubClock" value="unused" /&gt;
+      &lt;setting name="Subclock_in_halt" value="0" /&gt;
+      &lt;setting name="CPU_clock" value="0" /&gt;
+      &lt;setting name="Internal_low-speed_clock" value="15" /&gt;
+      &lt;setting name="RTC_clcok_selection" value="0" /&gt;
+      &lt;setting name="RESET_PIN_USED" value="false" /&gt;
+      &lt;setting name="RESET_PIN_UNUSED" value="true" /&gt;
+      &lt;setting name="On_chip_debug" value="unused" /&gt;
+      &lt;setting name="RRM" value="used" /&gt;
+      &lt;setting name="Trace" value="Used" /&gt;
+      &lt;setting name="Erase_flash_memory" value="yes" /&gt;
+      &lt;setting name="Security_ID_setting" value="used" /&gt;
+      &lt;setting name="Security_ID" value="0x00000000000000000000" /&gt;
+      &lt;setting name="CG_ReadResetSource" value="generated" /&gt;
+      &lt;setting name="Accessoperation" value="unused" /&gt;
+      &lt;setting name="RAMoperation" value="unused" /&gt;
+      &lt;setting name="RAMArea" value="0" /&gt;
+      &lt;setting name="PORToperation" value="unused" /&gt;
+      &lt;setting name="INToperation" value="unused" /&gt;
+      &lt;setting name="CHIPoperation" value="unused" /&gt;
+      &lt;setting name="DataFlash" value="unused" /&gt;
+      &lt;setting name="ProgramFlash" value="unused" /&gt;
+      &lt;setting name="Monitor" value="unused" /&gt;
+      &lt;setting name="StartStop" value="unused" /&gt;
+      &lt;setting name="Emulator" value="E1" /&gt;
+    &lt;/CGC&gt;
+    &lt;PORT&gt;
+      &lt;PortP1&gt;
+        &lt;P10&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P10&gt;
+        &lt;P11&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P11&gt;
+        &lt;P12&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P12&gt;
+        &lt;P13&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P13&gt;
+        &lt;P14&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P14&gt;
+      &lt;/PortP1&gt;
+      &lt;PortP2&gt;
+        &lt;P20&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P20&gt;
+        &lt;P21&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P21&gt;
+        &lt;P22&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P22&gt;
+        &lt;P23&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P23&gt;
+      &lt;/PortP2&gt;
+      &lt;PortP4&gt;
+        &lt;P40&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="used" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P40&gt;
+        &lt;P41&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P41&gt;
+        &lt;P42&gt;
+          &lt;setting name="Operation" value="output" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="1" /&gt;
+        &lt;/P42&gt;
+      &lt;/PortP4&gt;
+      &lt;PortP6&gt;
+        &lt;P60&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P60&gt;
+        &lt;P61&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P61&gt;
+      &lt;/PortP6&gt;
+      &lt;PortP12&gt;
+        &lt;P121&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P121&gt;
+        &lt;P122&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P122&gt;
+        &lt;P125&gt;
+          &lt;setting name="Operation" value="unused" /&gt;
+          &lt;setting name="Pull_up" value="used" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P125&gt;
+      &lt;/PortP12&gt;
+      &lt;PortP13&gt;
+        &lt;P137&gt;
+          &lt;setting name="Operation" value="input" /&gt;
+          &lt;setting name="Pull_up" value="unused" /&gt;
+          &lt;setting name="TTL_buffer" value="unused" /&gt;
+          &lt;setting name="N-ch_open-drain" value="unused" /&gt;
+          &lt;setting name="Output_value" value="0" /&gt;
+        &lt;/P137&gt;
+      &lt;/PortP13&gt;
+    &lt;/PORT&gt;
+    &lt;ADC&gt;
+      &lt;setting name="AD_convertion" value="unused" /&gt;
+      &lt;setting name="Comparator_operation" value="enable" /&gt;
+      &lt;setting name="Resolution" value="10bit" /&gt;
+      &lt;setting name="AD_Positive" value="VDD" /&gt;
+      &lt;setting name="AD_Negative" value="VSS" /&gt;
+      &lt;setting name="AD_Trigger" value="hardtrinowait" /&gt;
+      &lt;setting name="AD_Trigger_Timer" value="0" /&gt;
+      &lt;setting name="Mode" value="ONESELECT" /&gt;
+      &lt;setting name="InputPins" value="0" /&gt;
+      &lt;setting name="InputPinsAttach" value="ANI0 - ANI1" /&gt;
+      &lt;setting name="AD_Inputpin16" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin17" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin18" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin19" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin20" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin21" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin22" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin23" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin24" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin25" value="unused" /&gt;
+      &lt;setting name="AD_Inputpin26" value="unused" /&gt;
+      &lt;setting name="SelectedChannel" value="0" /&gt;
+      &lt;setting name="SelectedChannelAttach" value="ANI0" /&gt;
+      &lt;setting name="ConvTimeMode" value="0" /&gt;
+      &lt;setting name="ConversionTime" value="0" /&gt;
+      &lt;setting name="AREAFunction" value="AREA1" /&gt;
+      &lt;setting name="AREAValue_ADUL" value="255" /&gt;
+      &lt;setting name="AREAValue_ADLL" value="0" /&gt;
+      &lt;setting name="Interrput_priority" value="3" /&gt;
+      &lt;setting name="AD_interrupt" value="used" /&gt;
+    &lt;/ADC&gt;
+    &lt;TAU0&gt;
+      &lt;Channel0&gt;
+        &lt;setting name="ChannelFunction" value="1" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+        &lt;TAUInterval0&gt;
+          &lt;setting name="OperationMode" value="16bits" /&gt;
+          &lt;setting name="Count_clock" value="MCK clock" /&gt;
+          &lt;setting name="Sub_clock_mode" value="-1" /&gt;
+          &lt;setting name="Interval_value" value="1000" /&gt;
+          &lt;setting name="Value_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_High8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_High8bits_scale" value="-1" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits_Scale" value="-1" /&gt;
+          &lt;setting name="Generate_interrupt_when_couting_started" value="no" /&gt;
+          &lt;setting name="Interrupt" value="used" /&gt;
+          &lt;setting name="Interrupt_priority" value="3" /&gt;
+          &lt;setting name="InterruptH_priority" value="3" /&gt;
+          &lt;setting name="InterruptH8" value="unused" /&gt;
+        &lt;/TAUInterval0&gt;
+      &lt;/Channel0&gt;
+      &lt;Channel1&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+        &lt;TAUInterval1&gt;
+          &lt;setting name="OperationMode" value="16bits" /&gt;
+          &lt;setting name="Count_clock" value="MCK clock" /&gt;
+          &lt;setting name="Sub_clock_mode" value="-1" /&gt;
+          &lt;setting name="Interval_value" value="1000" /&gt;
+          &lt;setting name="Value_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_High8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_High8bits_scale" value="1" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits" value="100" /&gt;
+          &lt;setting name="Intervalvalue_Low8bits_Scale" value="1" /&gt;
+          &lt;setting name="Generate_interrupt_when_couting_started" value="no" /&gt;
+          &lt;setting name="Interrupt" value="used" /&gt;
+          &lt;setting name="Interrupt_priority" value="3" /&gt;
+          &lt;setting name="InterruptH_priority" value="3" /&gt;
+          &lt;setting name="InterruptH8" value="used" /&gt;
+        &lt;/TAUInterval1&gt;
+      &lt;/Channel1&gt;
+      &lt;Channel2&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+      &lt;/Channel2&gt;
+      &lt;Channel3&gt;
+        &lt;setting name="ChannelFunction" value="0" /&gt;
+        &lt;setting name="Pinselection" value="-1" /&gt;
+      &lt;/Channel3&gt;
+    &lt;/TAU0&gt;
+    &lt;WDT&gt;
+      &lt;setting name="Operation" value="used" /&gt;
+      &lt;setting name="Overflow_time" value="5" /&gt;
+      &lt;setting name="Window_opening_time" value="0" /&gt;
+      &lt;setting name="Standby_operation" value="stop" /&gt;
+      &lt;setting name="Interval_interrupt" value="not use" /&gt;
+      &lt;setting name="Interval_interrupt_priority" value="3" /&gt;
+    &lt;/WDT&gt;
+    &lt;LVD&gt;
+      &lt;setting name="Operation" value="used" /&gt;
+      &lt;setting name="Reset_only_level" value="5" /&gt;
+      &lt;setting name="InterruptReset_level" value="0" /&gt;
+      &lt;setting name="Interrupt_level" value="0" /&gt;
+      &lt;setting name="Interrupt_only_level" value="0" /&gt;
+      &lt;setting name="operation_mode" value="reset" /&gt;
+      &lt;setting name="Interrupt_priority" value="3" /&gt;
+      &lt;setting name="Interrupt_only_priority" value="3" /&gt;
+    &lt;/LVD&gt;
+    &lt;SAU0&gt;
+      &lt;IIC00 /&gt;
+      &lt;CSI00 /&gt;
+      &lt;UART0 /&gt;
+      &lt;Channel0&gt;
+        &lt;setting name="Channel_function_-i" value="1" /&gt;
+        &lt;setting name="Detail_function_-i" value="2" /&gt;
+        &lt;Both_UART0&gt;
+          &lt;setting name="Receive_data_direction" value="LSB" /&gt;
+          &lt;setting name="Receive_data_length" value="8 bits" /&gt;
+          &lt;setting name="Receive_parity" value="odd" /&gt;
+          &lt;setting name="RecBaudrate" value="9600" /&gt;
+          &lt;setting name="Receive_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Receive_error_callback_function" value="generated" /&gt;
+          &lt;setting name="Transfer_mode" value="single" /&gt;
+          &lt;setting name="Transmit_data_direction" value="LSB" /&gt;
+          &lt;setting name="Transmit_data_level" value="normal" /&gt;
+          &lt;setting name="Transmit_data_length" value="8 bits" /&gt;
+          &lt;setting name="Transmit_parity" value="odd" /&gt;
+          &lt;setting name="Transmit_stop_length" value="2 bits" /&gt;
+          &lt;setting name="TranBaudrate" value="9600" /&gt;
+          &lt;setting name="Transmit_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Transmit_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_error_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Reveive_Data_Level" value="Normal" /&gt;
+          &lt;setting name="Receive_error_interrupt" value="not used" /&gt;
+        &lt;/Both_UART0&gt;
+        &lt;Receive_UART0&gt;
+          &lt;setting name="Receive_data_direction" value="LSB" /&gt;
+          &lt;setting name="Receive_data_length" value="8 bits" /&gt;
+          &lt;setting name="Receive_parity" value="none" /&gt;
+          &lt;setting name="RecBaudrate" value="9600" /&gt;
+          &lt;setting name="Receive_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Receive_error_callback_function" value="generated" /&gt;
+          &lt;setting name="Transfer_mode" value="single" /&gt;
+          &lt;setting name="Transmit_data_direction" value="LSB" /&gt;
+          &lt;setting name="Transmit_data_level" value="normal" /&gt;
+          &lt;setting name="Transmit_data_length" value="8 bits" /&gt;
+          &lt;setting name="Transmit_parity" value="none" /&gt;
+          &lt;setting name="Transmit_stop_length" value="1 bit" /&gt;
+          &lt;setting name="TranBaudrate" value="9600" /&gt;
+          &lt;setting name="Transmit_end_callback_function" value="generated" /&gt;
+          &lt;setting name="Transmit_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_error_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Receive_end_interrupt_priority" value="3" /&gt;
+          &lt;setting name="Reveive_Data_Level" value="Normal" /&gt;
+          &lt;setting name="Receive_error_interrupt" value="not used" /&gt;
+        &lt;/Receive_UART0&gt;
+      &lt;/Channel0&gt;
+      &lt;IIC01 /&gt;
+      &lt;CSI01 /&gt;
+      &lt;Channel1&gt;
+        &lt;setting name="Channel_function_-i" value="0" /&gt;
+        &lt;setting name="Detail_function_-i" value="-1" /&gt;
+      &lt;/Channel1&gt;
+    &lt;/SAU0&gt;
+    &lt;IICA0&gt;
+      &lt;setting name="Mode" value="Unused" /&gt;
+    &lt;/IICA0&gt;
+  &lt;/SETTING&gt;
+&lt;/RL78G12&gt;</CodeGeneratorData>
+    </Extension_CodePart2>
+  </Project>
+</MicomToolCommonProjectFile>
\ No newline at end of file
diff --git a/OUTPUT/K53L_SW0101.mot b/OUTPUT/K53L_SW0101.mot
new file mode 100644
index 0000000..04617ba
--- /dev/null
+++ b/OUTPUT/K53L_SW0101.mot
@@ -0,0 +1,136 @@
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diff --git a/OUTPUT/K53R_SW0101.mot b/OUTPUT/K53R_SW0101.mot
new file mode 100644
index 0000000..24f22c8
--- /dev/null
+++ b/OUTPUT/K53R_SW0101.mot
@@ -0,0 +1,136 @@
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+S1130828F013BEF6F6BEF2BEF4CFE800818FE800FE
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diff --git a/OUTPUT/更改履历.txt b/OUTPUT/更改履历.txt
new file mode 100644
index 0000000..0c07c36
--- /dev/null
+++ b/OUTPUT/更改履历.txt
@@ -0,0 +1 @@
+SW0101 初版
\ No newline at end of file
diff --git a/appTask.c b/appTask.c
new file mode 100644
index 0000000..ae6c343
--- /dev/null
+++ b/appTask.c
@@ -0,0 +1,359 @@
+#include "r_cg_macrodriver.h"
+#include "appTask.h"
+#include "event.h"
+#include "r_cg_port.h"
+#include "r_cg_timer.h"
+//#include "r_cg_wdt.h"
+#include "hwCtrl.h"
+#include "r_cg_adc.h"
+#include "r_cg_serial.h"
+
+uint8_t g_rx_buf[3];
+
+extern uint16_t g_AdVal[3];
+
+
+void HardWare_Init(void)
+{
+    //ʱ����ʼ��
+    R_TAU0_Channel0_Start();
+
+    //LED��ʼ��
+    FanLED_Ctrl(0);
+    HeatLED_Ctrl(0);
+    //AnmoLED_Ctrl(0);
+
+    //AD ��ʼ��
+    //R_ADC_Start();
+    //R_ADC_Set_OperationOn();
+    //R_TAU0_Channel1_Start();
+
+    //UART��ʼ��
+    R_UART0_Start();
+    R_UART0_Receive(g_rx_buf,1);
+}
+uint8_t uart_sendend;
+void Variable_Init(void)
+{
+    uart_sendend = 1;
+}
+static uint8_t heat_txstate=0,fan_txstate=0,motor_txstate=0,heat_state=0,fan_state=0,motor_state=0;
+uint8_t g_tx_buf[7] = {0};
+
+void UART_Tx_Pro(uint8_t keyid)
+{
+    uint8_t uart_buf[7] = {0x5a,0xa5,0x04,0x00,0x00,0x00,0x00};
+    uint8_t i;
+
+    switch (keyid)
+    {
+    case KEY_JR:
+        uart_buf[3] = (0x03 + heat_txstate)<<4;
+        break;
+    case KEY_FAN:
+        uart_buf[3] = 0x03 + fan_txstate;
+        break;
+    case KEY_AM:
+        if (motor_txstate == 0)
+        {
+            uart_buf[4] = 0x0d;
+        }
+        else
+        {
+            uart_buf[4] = 0x09 + motor_txstate;
+        }
+        break;
+    default:
+        return;
+    }
+    //checksum
+    uart_buf[6] = uart_buf[3] + uart_buf[5] + uart_buf[4];
+
+    for ( i = 0; i < 7; i++)
+    {
+        g_tx_buf[i] = uart_buf[i];
+    }
+    if (uart_sendend == 1)
+    {
+        uart_sendend = 0;
+        R_UART0_Send(g_tx_buf,7);
+    }
+}
+
+uint8_t datacount=0;
+uint8_t RxTimeoutCount=0;
+static uint8_t Rxdata[10];
+uint8_t RxFlag=0;
+void UART_Rx_Pro(uint8_t data)
+{
+    static uint8_t last_data=0,datalen=0;
+    if (last_data == 0x5A && data == 0xA5)
+    {
+        RxFlag = 1;
+        datacount = 0;
+        datalen=0;
+        g_tx_buf[0] = 1;
+        //R_UART0_Send(g_tx_buf,1);
+    }
+    else
+    {
+        if (RxFlag == 1)
+        {
+            datalen = data;
+            RxFlag = 2;
+            g_tx_buf[0] = 2;
+            //R_UART0_Send(g_tx_buf,1);
+        }
+        else if (RxFlag == 2)
+        {
+            Rxdata[datacount++] = data;
+            if (datacount >= datalen)
+            {
+                MsgPro(datalen);
+            }
+            
+        }    
+    }
+    last_data = data;
+    RxTimeoutCount = 0;
+    
+}
+void MsgPro(uint8_t len)
+{
+    uint8_t i;
+    //���ô���Э��
+    uint8_t crc,crcRx;
+    if (len <= 3)
+    {
+        return;
+    }
+    crc = 0;
+    for(i=0;i<3;i++)
+    {
+        crc += Rxdata[i];
+    }
+    crcRx = Rxdata[3];
+    
+    if (crc == crcRx)
+    {
+        switch (Rxdata[0])
+        {
+        case 0x10:
+            heat_state = 0;
+            //fan_state = 0;
+            break;
+        case 0x20:
+            heat_state = 3;
+            fan_state = 0;
+            break;
+        case 0x70:
+            heat_state = 2;
+            fan_state = 0;
+            break;
+        case 0x80:
+            heat_state = 1;
+            fan_state = 0;
+            break;
+        case 0x01:
+            fan_state = 0;
+            //heat_state = 0;
+            break;
+        case 0x02:
+            fan_state = 3;
+            heat_state = 0;
+            break;
+        case 0x07:
+            fan_state = 2;
+            heat_state = 0;
+            break;
+        case 0x08:
+            fan_state = 1;
+            heat_state = 0;
+            break;
+        case 0x11:
+            fan_state = 0;
+            heat_state = 0;
+        default:
+            break;
+        }
+        switch (Rxdata[1])
+        {
+        case 0x1a:
+            motor_state = 1;
+            break;
+        case 0x1b:
+            motor_state = 2;
+            break;
+        case 0x1c:
+            motor_state = 3;
+            break;
+        case 0x1d:
+            motor_state = 0;
+            break;
+        default:
+            break;
+        }
+    }
+    
+    RxFlag = 0;
+    RxTimeoutCount = 0;
+    datacount = 0;
+}
+void keyLogic(uint8_t keyno)
+{
+    
+    switch (keyno)
+    {
+    case KEY_JR:
+        heat_txstate = heat_state + 1;
+        if (heat_txstate > 3)
+        {
+            heat_txstate = 0;
+        }
+        heat_state = heat_txstate;
+        fan_state = 0;
+
+        break;
+    case KEY_FAN:
+        fan_txstate = fan_state + 1;
+        if (fan_txstate > 3)
+        {
+            fan_txstate = 0;
+        }
+        fan_state = fan_txstate;
+        heat_state = 0;
+        
+        break;
+    case KEY_AM:
+        motor_txstate = motor_state + 1;
+        if (motor_txstate > 3)
+        {
+            motor_txstate = 0;
+        }
+        motor_state = motor_txstate;
+        
+        break;
+    default:
+        break;
+    }
+    
+    UART_Tx_Pro(keyno);
+}
+
+#define KEY_DELAY_TIME 6
+void keyScan(void)//5ms
+{
+    static uint16_t keydelay[KEY_NUM]={0};
+    static uint8_t keyflag[KEY_NUM]={0};
+    static uint8_t keep_count[KEY_NUM]={0};
+    uint8_t keyval,i;
+    for (i = 0; i < KEY_NUM; i++)
+    {
+        keyval = GetKeyState(i);
+        if (keyval == 1 && keyflag[i] == 0)
+        {
+            keydelay[i]++;
+            if (keydelay[i] > KEY_DELAY_TIME)//30ms
+            {   
+                keyflag[i] = 1;
+                keydelay[i] = KEY_DELAY_TIME;
+                keyLogic(i);
+                keep_count[i] = 0;
+            }
+            
+        }
+        else if (keyval == 0)
+        {
+            keyflag[i] = 0;
+            keydelay[i] = 0;
+        }
+        
+    }
+    //��������
+    
+}
+
+void LED_Ctrl(void)
+{
+    FanLED_Ctrl(fan_state);
+    HeatLED_Ctrl(heat_state);
+    AnmoLED_Ctrl(motor_state);
+}
+
+void AppTask(void)
+{
+    static uint8_t ledno = 1,last = 0;
+    if (TimeBase5msFlag == 1)
+    {
+        TimeBase5msFlag = 0;
+        keyScan();
+        if (RxFlag)
+        {
+            RxTimeoutCount++;
+            if (RxTimeoutCount > 6)
+            {
+                RxFlag = 0;
+            }
+            
+        }
+        else
+        {
+            RxTimeoutCount = 0;
+        }
+        
+    }
+    
+
+    if (TimeBase10msFlag == 1)
+    {
+        TimeBase10msFlag = 0;
+        LED_Ctrl();
+    }
+    
+    if (TimeBase100msFlag == 1)
+    {
+        TimeBase100msFlag = 0;
+        
+        R_WDT_Restart();
+
+    }
+    
+    if (TimeBase1000msFlag == 1)
+    {
+        TimeBase1000msFlag = 0;
+        //UART_Tx_Pro(1);
+
+    }
+    
+}
+
+#define		POLYNOMINAL		0xA001
+#define		PRESET_VALUE	0xFFFF
+
+unsigned int crc16_make(unsigned char *Buffer, unsigned char size)
+{
+	unsigned int 	Cur_CRC_Value;
+	unsigned char  	i,j;
+		
+	Cur_CRC_Value = PRESET_VALUE;
+	
+	for(i = 0x00; i < size; i++)
+	{
+		Cur_CRC_Value ^= *Buffer++;
+		
+		for(j = 0x00; j < 8; j++)
+		{
+			if(Cur_CRC_Value & 0x0001) 
+			{
+				Cur_CRC_Value = (Cur_CRC_Value >> 1) ^ POLYNOMINAL;
+			}
+			else
+			{
+				Cur_CRC_Value = (Cur_CRC_Value >> 1);
+			}
+		}
+	}
+	
+	return Cur_CRC_Value;
+
+}
diff --git a/appTask.h b/appTask.h
new file mode 100644
index 0000000..e170c07
--- /dev/null
+++ b/appTask.h
@@ -0,0 +1,18 @@
+#ifndef __APPTASK_H__
+#define __APPTASK_H__
+
+#define KEY_NUM         3
+
+#define KEY_JR      0
+#define KEY_FAN     1
+#define KEY_AM      2
+
+
+void HardWare_Init(void);
+void Variable_Init(void);
+void AppTask(void);
+void UART_Rx_Pro(uint8_t data);
+void MsgPro(uint8_t len);
+unsigned int crc16_make(unsigned char *Buffer, unsigned char size);
+
+#endif
diff --git a/cstart.asm b/cstart.asm
new file mode 100644
index 0000000..2542550
--- /dev/null
+++ b/cstart.asm
@@ -0,0 +1,229 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+$IFNDEF __RENESAS_VERSION__
+__RENESAS_VERSION__	.EQU	0x01000000
+$ENDIF
+
+	.public	_start
+	.public _exit
+
+;-----------------------------------------------------------------------------
+;	RAM section
+;-----------------------------------------------------------------------------
+.SECTION .dataR, DATA
+.SECTION .sdataR, DATA
+; .SECTION .datafR, DATAF
+; .SECTION .textfR, TEXTF
+
+$IF (__RENESAS_VERSION__ < 0x01010000)	; for CC-RL V1.00
+;-----------------------------------------------------------------------------
+;	stack area
+;-----------------------------------------------------------------------------
+; !!! [CAUTION] !!!
+; Set up stack size suitable for a project.
+.SECTION .stack_bss, BSS
+_stackend:
+	.DS     0x200
+_stacktop:
+$ENDIF
+
+;-----------------------------------------------------------------------------
+;	RESET vector
+;-----------------------------------------------------------------------------
+_start	.VECTOR	0
+
+;-----------------------------------------------------------------------------
+;	startup
+;-----------------------------------------------------------------------------
+.SECTION .text, TEXT
+_start:
+	;--------------------------------------------------
+	; setting register bank
+	;--------------------------------------------------
+;	SEL	RB0
+
+	;--------------------------------------------------
+	; setting mirror area
+	;--------------------------------------------------
+;	ONEB    !PMC		; mirror area = 10000-1FFFFH
+
+	;--------------------------------------------------
+	; setting the stack pointer
+	;--------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+	MOVW	SP,#LOWW(__STACK_ADDR_START)
+$ELSE	; for CC-RL V1.00
+	MOVW	SP,#LOWW(_stacktop)
+$ENDIF
+
+	;--------------------------------------------------
+	; initializing stack area
+	;--------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+	MOVW	AX,#LOWW(__STACK_ADDR_END)
+$ELSE	; for CC-RL V1.00
+	MOVW	AX,#LOWW(_stackend)
+$ENDIF
+	CALL	!!_stkinit
+
+	;--------------------------------------------------
+	; hardware initialization
+	;--------------------------------------------------
+	CALL	!!_hdwinit
+
+	;--------------------------------------------------
+	; initializing BSS
+	;--------------------------------------------------
+	; clear external variables which doesn't have initial value (near)
+	MOVW	HL,#LOWW(STARTOF(.bss))
+	MOVW	AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss))
+	BR	$.L2_BSS
+.L1_BSS:
+	MOV	[HL+0],#0
+	INCW	HL
+.L2_BSS:
+	CMPW	AX,HL
+	BNZ	$.L1_BSS
+
+	; clear saddr variables which doesn't have initial value
+	MOVW	HL,#LOWW(STARTOF(.sbss))
+	MOVW	AX,#LOWW(STARTOF(.sbss) + SIZEOF(.sbss))
+	BR	$.L2_SBSS
+.L1_SBSS:
+	MOV	[HL+0],#0
+	INCW	HL
+.L2_SBSS:
+	CMPW	AX,HL
+	BNZ	$.L1_SBSS
+
+	; clear external variables which doesn't have initial value (far)
+;	MOV	ES,#HIGHW(STARTOF(.bssf))
+;	MOVW	HL,#LOWW(STARTOF(.bssf))
+;	MOVW	AX,#LOWW(STARTOF(.bssf) + SIZEOF(.bssf))
+;	BR	$.L2_BSSF
+;.L1_BSSF:
+;	MOV	ES:[HL+0],#0
+;	INCW	HL
+;.L2_BSSF:
+;	CMPW	AX,HL
+;	BNZ	$.L1_BSSF
+
+	;--------------------------------------------------
+	; ROM data copy
+	;--------------------------------------------------
+	; copy external variables having initial value (near)
+	MOV	ES,#HIGHW(STARTOF(.data))
+	MOVW	BC,#LOWW(SIZEOF(.data))
+	BR	$.L2_DATA
+.L1_DATA:
+	DECW	BC
+	MOV	A,ES:LOWW(STARTOF(.data))[BC]
+	MOV	LOWW(STARTOF(.dataR))[BC],A
+.L2_DATA:
+	CLRW	AX
+	CMPW	AX,BC
+	BNZ	$.L1_DATA
+
+	; copy saddr variables having initial value
+	MOV	ES,#HIGHW(STARTOF(.sdata))
+	MOVW	BC,#LOWW(SIZEOF(.sdata))
+	BR	$.L2_SDATA
+.L1_SDATA:
+	DECW	BC
+	MOV	A,ES:LOWW(STARTOF(.sdata))[BC]
+	MOV	LOWW(STARTOF(.sdataR))[BC],A
+.L2_SDATA:
+	CLRW	AX
+	CMPW	AX,BC
+	BNZ	$.L1_SDATA
+
+	; copy external variables having initial value (far)
+;	MOVW	BC,#LOWW(SIZEOF(.dataf))
+;	BR	$.L2_DATAF
+;.L1_DATAF:
+;	DECW	BC
+;	MOV	ES,#HIGHW(STARTOF(.dataf))
+;	MOV	A,ES:LOWW(STARTOF(.dataf))[BC]
+;	MOV	ES,#HIGHW(STARTOF(.datafR))
+;	MOV	ES:LOWW(STARTOF(.datafR))[BC],A
+;.L2_DATAF:
+;	CLRW	AX
+;	CMPW	AX,BC
+;	BNZ	$.L1_DATAF
+
+	; copy .text to RAM
+;	MOV	C,#HIGHW(STARTOF(.textf))
+;	MOVW	HL,#LOWW(STARTOF(.textf))
+;	MOVW	DE,#LOWW(STARTOF(.textfR))
+;	BR	$.L2_TEXT
+;.L1_TEXT:
+;	MOV	A,C
+;	MOV	ES,A
+;	MOV	A,ES:[HL]
+;	MOV	[DE],A
+;	INCW	DE
+;	INCW	HL
+;	CLRW	AX
+;	CMPW	AX,HL
+;	SKNZ
+;	INC	C
+;.L2_TEXT:
+;	MOVW	AX,HL
+;	CMPW	AX,#LOWW(STARTOF(.text) + SIZEOF(.text))
+;	BNZ	$.L1_TEXT
+
+	;--------------------------------------------------
+	; call main function
+	;--------------------------------------------------
+	CALL	!!_main		; main();
+
+	;--------------------------------------------------
+	; call exit function
+	;--------------------------------------------------
+	CLRW	AX		; exit(0)
+_exit:
+	BR	$_exit
+
+;-----------------------------------------------------------------------------
+;	section
+;-----------------------------------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+.SECTION .RLIB, TEXTF
+.L_section_RLIB:
+.SECTION .SLIB, TEXTF
+.L_section_SLIB:
+$ENDIF
+.SECTION .textf, TEXTF
+.L_section_textf:
+.SECTION .constf, CONSTF
+.L_section_constf:
+.SECTION .data, DATA
+.L_section_data:
+;.SECTION .dataf, DATAF
+;.L_section_dataf:
+.SECTION .sdata, SDATA
+.L_section_sdata:
+.SECTION .bss, BSS
+.L_section_bss:
+;.SECTION .bssf, BSSF
+;.L_section_bssf:
+.SECTION .sbss, SBSS
+.L_section_sbss:
diff --git a/event.c b/event.c
new file mode 100644
index 0000000..53ec8ed
--- /dev/null
+++ b/event.c
@@ -0,0 +1,46 @@
+
+#include "event.h"
+
+static volatile uint16_t TimeBaseCounter;
+volatile uint8_t TimeBase1msFlag;
+volatile uint8_t TimeBase5msFlag;
+volatile uint8_t TimeBase10msFlag;
+volatile uint8_t TimeBase20msFlag;
+volatile uint8_t TimeBase50msFlag;
+volatile uint8_t TimeBase100msFlag;
+volatile uint8_t TimeBase1000msFlag;
+
+
+void TimeBaseCount(void)
+{
+    TimeBaseCounter++;
+    TimeBase1msFlag = 1;
+    if(TimeBaseCounter % 5 == 0)
+    {
+        TimeBase5msFlag = 1;
+    }
+    if(TimeBaseCounter % 10 == 0)
+    {
+        TimeBase10msFlag = 1;
+    }
+    if(TimeBaseCounter % 20 == 0)
+    {
+        TimeBase20msFlag = 1;
+    }
+    if(TimeBaseCounter % 50 == 0)
+    {
+        TimeBase50msFlag = 1;
+    }
+    if(TimeBaseCounter % 100 == 0)
+    {
+        TimeBase100msFlag = 1;
+    }
+    if(TimeBaseCounter % 1000 == 0)
+    {
+        TimeBase1000msFlag = 1;
+    }
+    if(TimeBaseCounter >= 60000)
+    {
+        TimeBaseCounter = 0;
+    }
+}
\ No newline at end of file
diff --git a/event.h b/event.h
new file mode 100644
index 0000000..8aab0ed
--- /dev/null
+++ b/event.h
@@ -0,0 +1,18 @@
+
+
+#ifndef __EVENT_H__
+#define __EVENT_H__
+#include "r_cg_macrodriver.h"
+
+extern volatile uint8_t TimeBase1msFlag;
+extern volatile uint8_t TimeBase5msFlag;
+extern volatile uint8_t TimeBase10msFlag;
+extern volatile uint8_t TimeBase20msFlag;
+extern volatile uint8_t TimeBase50msFlag;
+extern volatile uint8_t TimeBase100msFlag;
+extern volatile uint8_t TimeBase1000msFlag;
+
+
+extern void TimeBaseCount(void);
+
+#endif
diff --git a/hdwinit.asm b/hdwinit.asm
new file mode 100644
index 0000000..0b74c68
--- /dev/null
+++ b/hdwinit.asm
@@ -0,0 +1,35 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/;---------------------------------------------------------------------
+;	_hdwinit
+;
+;	void _hdwinit(void);
+;
+;	input:
+;		NONE
+;	output:
+;		NONE
+;---------------------------------------------------------------------
+
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+	.PUBLIC	_hdwinit
+
+.textf	.CSEG	TEXTF
+_hdwinit:
+	RET
diff --git a/hwCtrl.c b/hwCtrl.c
new file mode 100644
index 0000000..549b2a2
--- /dev/null
+++ b/hwCtrl.c
@@ -0,0 +1,241 @@
+
+#include "hwCtrl.h"
+#include "r_cg_port.h"
+#include "iodefine.h"
+#include "appTask.h"
+
+#define K74L    1
+#define K74R    2
+#define BOARD   K74L    
+
+
+
+#if BOARD == K74R
+//RIGHT
+#define LEDH1   P4_bit.no2
+#define LEDH2   P1_bit.no0
+#define LEDH3   P1_bit.no1
+
+#define LEDM1   P1_bit.no2
+#define LEDM2   P1_bit.no3
+#define LEDM3   P1_bit.no4
+
+#define LEDF1   P4_bit.no1
+#define LEDF2   P2_bit.no3
+#define LEDF3   P2_bit.no2
+
+#else
+//LEFT
+#define LEDH1   P4_bit.no2
+#define LEDH2   P1_bit.no0
+#define LEDH3   P1_bit.no1
+
+#define LEDF1   P1_bit.no2
+#define LEDF2   P1_bit.no3
+#define LEDF3   P1_bit.no4
+
+#define LEDM1   P4_bit.no1
+#define LEDM2   P2_bit.no3
+#define LEDM3   P2_bit.no2
+
+#endif
+
+#define IO_KEY1     P2_bit.no0
+#define IO_KEY2     P2_bit.no1
+#define IO_KEY5     P12_bit.no2
+#define IO_KEY6     P13_bit.no7
+
+
+
+
+
+extern uint16_t g_AdVal[3];
+
+#if BOARD == K74R
+void FanLED_Ctrl(uint8_t state)
+{
+    switch (state)
+    {
+    case 0:
+        LEDF1 = LED_OFF;
+        LEDF2 = LED_ON;
+        LEDF3 = LED_ON;
+        break;
+    case 3:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_ON;
+        LEDF3 = LED_ON;
+        break;
+    case 2:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_OFF;
+        LEDF3 = LED_ON;
+        break;
+    case 1:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_OFF;
+        LEDF3 = LED_OFF;
+        break;
+    default:
+        break;
+    }
+}
+void AnmoLED_Ctrl(uint8_t state)
+{
+    switch (state)
+    {
+    case 0:
+        LEDM1 = LED_OFF;
+        LEDM2 = LED_OFF;
+        LEDM3 = LED_OFF;
+        break;
+    case 3:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_OFF;
+        LEDM3 = LED_OFF;
+        break;
+    case 2:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_ON;
+        LEDM3 = LED_OFF;
+        break;
+    case 1:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_ON;
+        LEDM3 = LED_ON;
+        break;
+    default:
+        break;
+    }
+}
+#else
+void AnmoLED_Ctrl(uint8_t state)
+{
+    switch (state)
+    {
+    case 0:
+        LEDM1 = LED_OFF;
+        LEDM2 = LED_ON;
+        LEDM3 = LED_ON;
+        break;
+    case 3:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_ON;
+        LEDM3 = LED_ON;
+        break;
+    case 2:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_OFF;
+        LEDM3 = LED_ON;
+        break;
+    case 1:
+        LEDM1 = LED_ON;
+        LEDM2 = LED_OFF;
+        LEDM3 = LED_OFF;
+        break;
+    default:
+        break;
+    }
+}
+void FanLED_Ctrl(uint8_t state)
+{
+    switch (state)
+    {
+    case 0:
+        LEDF1 = LED_OFF;
+        LEDF2 = LED_OFF;
+        LEDF3 = LED_OFF;
+        break;
+    case 3:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_OFF;
+        LEDF3 = LED_OFF;
+        break;
+    case 2:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_ON;
+        LEDF3 = LED_OFF;
+        break;
+    case 1:
+        LEDF1 = LED_ON;
+        LEDF2 = LED_ON;
+        LEDF3 = LED_ON;
+        break;
+    default:
+        break;
+    }
+}
+#endif
+
+void HeatLED_Ctrl(uint8_t state)
+{
+    switch (state)
+    {
+    case 0:
+        LEDH1 = LED_OFF;
+        LEDH2 = LED_OFF;
+        LEDH3 = LED_OFF;
+        break;
+    case 3:
+        LEDH1 = LED_ON;
+        LEDH2 = LED_OFF;
+        LEDH3 = LED_OFF;
+        break;
+    case 2:
+        LEDH1 = LED_ON;
+        LEDH2 = LED_ON;
+        LEDH3 = LED_OFF;
+        break;
+    case 1:
+        LEDH1 = LED_ON;
+        LEDH2 = LED_ON;
+        LEDH3 = LED_ON;
+        break;
+    default:
+        break;
+    }
+}
+
+
+
+
+#define KEY_AD_V1   690
+#define KEY_AD_V2   510
+#define KEY_AD_TH   50
+#define KEY5_AD_V1   KEY_AD_TH //0
+#define KEY5_AD_V2   254
+#define KEY5_AD_V3   455
+#define KEY5_AD_V4   658
+#define KEY5_AD_V5   902
+uint8_t GetKeyState(uint8_t keyno)
+{
+    switch (keyno)
+    {
+#if BOARD == K74R
+    //RIGHT
+    case KEY_FAN:
+        return IO_KEY1==0?1:0;
+        break;
+    case KEY_JR:
+        return IO_KEY2==0?1:0;
+        break;
+    case KEY_AM:
+        return (IO_KEY5==0)?1:0;
+        break;
+#else
+    //left
+    case KEY_AM:
+        return IO_KEY1==0?1:0;
+        break;
+    case KEY_JR:
+        return IO_KEY2==0?1:0;
+        break;
+    case KEY_FAN:
+        return (IO_KEY5==0)?1:0;
+        break;
+#endif
+    default:
+        return 0;
+        break;
+    }
+}
\ No newline at end of file
diff --git a/hwCtrl.h b/hwCtrl.h
new file mode 100644
index 0000000..a642d51
--- /dev/null
+++ b/hwCtrl.h
@@ -0,0 +1,16 @@
+
+#ifndef __HWCTRL_H__
+#define __HWCTRL_H__
+#include "r_cg_macrodriver.h"
+
+#define LED_ON  0
+#define LED_OFF  1
+
+
+uint8_t GetKeyState(uint8_t keyno);
+
+void FanLED_Ctrl(uint8_t state);
+void HeatLED_Ctrl(uint8_t state);
+void AnmoLED_Ctrl(uint8_t state);
+
+#endif
diff --git a/iodefine.h b/iodefine.h
new file mode 100644
index 0000000..b1f35fb
--- /dev/null
+++ b/iodefine.h
@@ -0,0 +1,542 @@
+/******************************************************************************/
+/* DISCLAIMER                                                                 */
+/* This software is supplied by Renesas Electronics Corporation and is only   */
+/* intended for use with Renesas products. No other uses are authorized.This  */
+/* software is owned by Renesas Electronics Corporation and is protected      */
+/* under all applicable laws, including copyright laws.                       */
+/* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES          */
+/* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING  */
+/* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR */
+/* PURPOSE AND NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY           */
+/* DISCLAIMED.                                                                */
+/* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS     */
+/* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE       */
+/* LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL      */
+/* DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS    */
+/* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.           */
+/* Renesas reserves the right, without notice, to make changes to this        */
+/* software and to discontinue the availability of this software.             */
+/* By using this software, you agree to the additional terms and conditions   */
+/* found by accessing the following link:                                     */
+/* http://www.renesas.com/disclaimer                                          */
+/*                                                                            */
+/* Device     : RL78/R5F10268                                                 */
+/* File Name  : iodefine.h                                                    */
+/* Abstract   : Definition of Special Function Register (SFR)                 */
+/* History    : V1.12  [Device File version]                                  */
+/* Options    : -df=E:\Program Files (x86)\renesas\CS+\CC\Device\RL78\Devicef */
+/*              ile\DR5F10268.DVF -o=C:\Users\dm01\Documents\K67L\iodefine.h  */
+/*              -f                                                            */
+/* Date       : 2022/5/20                                                     */
+/* Version    : V1.15.00.01  [df2iodef.exe version]                           */
+/* This is a typical example.                                                 */
+/*                                                                            */
+/******************************************************************************/
+#ifndef __R5F10268IODEFINE_HEADER__
+#define __R5F10268IODEFINE_HEADER__
+
+typedef struct
+{
+    unsigned char no0:1;
+    unsigned char no1:1;
+    unsigned char no2:1;
+    unsigned char no3:1;
+    unsigned char no4:1;
+    unsigned char no5:1;
+    unsigned char no6:1;
+    unsigned char no7:1;
+} __bitf_T;
+
+typedef struct
+{
+    unsigned char no0:1;
+    unsigned char no1:1;
+    unsigned char no2:1;
+    unsigned char no3:1;
+    unsigned char no4:1;
+    unsigned char no5:1;
+    unsigned char no6:1;
+    unsigned char no7:1;
+    unsigned char no8:1;
+    unsigned char no9:1;
+    unsigned char no10:1;
+    unsigned char no11:1;
+    unsigned char no12:1;
+    unsigned char no13:1;
+    unsigned char no14:1;
+    unsigned char no15:1;
+} __bitf_T2;
+
+
+
+#define ADM2         (*(volatile __near unsigned char  *)0x10)
+#define ADM2_bit     (*(volatile __near __bitf_T *)0x10)
+#define ADTYP        (((volatile __near __bitf_T *)0x10)->no0)
+#define AWC          (((volatile __near __bitf_T *)0x10)->no2)
+#define ADRCK        (((volatile __near __bitf_T *)0x10)->no3)
+#define ADUL         (*(volatile __near unsigned char  *)0x11)
+#define ADLL         (*(volatile __near unsigned char  *)0x12)
+#define ADTES        (*(volatile __near unsigned char  *)0x13)
+#define PU1          (*(volatile __near unsigned char  *)0x31)
+#define PU1_bit      (*(volatile __near __bitf_T *)0x31)
+#define PU4          (*(volatile __near unsigned char  *)0x34)
+#define PU4_bit      (*(volatile __near __bitf_T *)0x34)
+#define PU12         (*(volatile __near unsigned char  *)0x3C)
+#define PU12_bit     (*(volatile __near __bitf_T *)0x3C)
+#define PIM1         (*(volatile __near unsigned char  *)0x41)
+#define PIM1_bit     (*(volatile __near __bitf_T *)0x41)
+#define POM1         (*(volatile __near unsigned char  *)0x51)
+#define POM1_bit     (*(volatile __near __bitf_T *)0x51)
+#define POM4         (*(volatile __near unsigned char  *)0x54)
+#define POM4_bit     (*(volatile __near __bitf_T *)0x54)
+#define PMC1         (*(volatile __near unsigned char  *)0x61)
+#define PMC1_bit     (*(volatile __near __bitf_T *)0x61)
+#define PMC4         (*(volatile __near unsigned char  *)0x64)
+#define PMC4_bit     (*(volatile __near __bitf_T *)0x64)
+#define NFEN0        (*(volatile __near unsigned char  *)0x70)
+#define NFEN0_bit    (*(volatile __near __bitf_T *)0x70)
+#define NFEN1        (*(volatile __near unsigned char  *)0x71)
+#define NFEN1_bit    (*(volatile __near __bitf_T *)0x71)
+#define ISC          (*(volatile __near unsigned char  *)0x73)
+#define ISC_bit      (*(volatile __near __bitf_T *)0x73)
+#define TIS0         (*(volatile __near unsigned char  *)0x74)
+#define ADPC         (*(volatile __near unsigned char  *)0x76)
+#define PIOR         (*(volatile __near unsigned char  *)0x77)
+#define IAWCTL       (*(volatile __near unsigned char  *)0x78)
+#define DFLCTL       (*(volatile __near unsigned char  *)0x90)
+#define DFLCTL_bit   (*(volatile __near __bitf_T *)0x90)
+#define DFLEN        (((volatile __near __bitf_T *)0x90)->no0)
+#define HIOTRM       (*(volatile __near unsigned char  *)0xA0)
+#define HOCODIV      (*(volatile __near unsigned char  *)0xA8)
+#define TEMPCAL0     (*(volatile __near unsigned char  *)0xAC)
+#define TEMPCAL1     (*(volatile __near unsigned char  *)0xAD)
+#define TEMPCAL2     (*(volatile __near unsigned char  *)0xAE)
+#define TEMPCAL3     (*(volatile __near unsigned char  *)0xAF)
+#define MDCL         (*(volatile __near unsigned short *)0xE0)
+#define MDCH         (*(volatile __near unsigned short *)0xE2)
+#define MDUC         (*(volatile __near unsigned char  *)0xE8)
+#define MDUC_bit     (*(volatile __near __bitf_T *)0xE8)
+#define DIVST        (((volatile __near __bitf_T *)0xE8)->no0)
+#define MACSF        (((volatile __near __bitf_T *)0xE8)->no1)
+#define MACOF        (((volatile __near __bitf_T *)0xE8)->no2)
+#define MDSM         (((volatile __near __bitf_T *)0xE8)->no3)
+#define MACMODE      (((volatile __near __bitf_T *)0xE8)->no6)
+#define DIVMODE      (((volatile __near __bitf_T *)0xE8)->no7)
+#define PER0         (*(volatile __near unsigned char  *)0xF0)
+#define PER0_bit     (*(volatile __near __bitf_T *)0xF0)
+#define TAU0EN       (((volatile __near __bitf_T *)0xF0)->no0)
+#define SAU0EN       (((volatile __near __bitf_T *)0xF0)->no2)
+#define IICA0EN      (((volatile __near __bitf_T *)0xF0)->no4)
+#define ADCEN        (((volatile __near __bitf_T *)0xF0)->no5)
+#define TMKAEN       (((volatile __near __bitf_T *)0xF0)->no7)
+#define OSMC         (*(volatile __near unsigned char  *)0xF3)
+#define RMC          (*(volatile __near unsigned char  *)0xF4)
+#define RMC_bit      (*(volatile __near __bitf_T *)0xF4)
+#define WDVOL        (((volatile __near __bitf_T *)0xF4)->no7)
+#define RPECTL       (*(volatile __near unsigned char  *)0xF5)
+#define RPECTL_bit   (*(volatile __near __bitf_T *)0xF5)
+#define RPEF         (((volatile __near __bitf_T *)0xF5)->no0)
+#define RPERDIS      (((volatile __near __bitf_T *)0xF5)->no7)
+#define BCDADJ       (*(volatile __near unsigned char  *)0xFE)
+#define SSR00        (*(volatile __near unsigned short *)0x100)
+#define SSR00L       (*(volatile __near unsigned char  *)0x100)
+#define SSR01        (*(volatile __near unsigned short *)0x102)
+#define SSR01L       (*(volatile __near unsigned char  *)0x102)
+#define SIR00        (*(volatile __near unsigned short *)0x108)
+#define SIR00L       (*(volatile __near unsigned char  *)0x108)
+#define SIR01        (*(volatile __near unsigned short *)0x10A)
+#define SIR01L       (*(volatile __near unsigned char  *)0x10A)
+#define SMR00        (*(volatile __near unsigned short *)0x110)
+#define SMR01        (*(volatile __near unsigned short *)0x112)
+#define SCR00        (*(volatile __near unsigned short *)0x118)
+#define SCR01        (*(volatile __near unsigned short *)0x11A)
+#define SE0          (*(volatile __near unsigned short *)0x120)
+#define SE0L         (*(volatile __near unsigned char  *)0x120)
+#define SE0L_bit     (*(volatile __near __bitf_T *)0x120)
+#define SS0          (*(volatile __near unsigned short *)0x122)
+#define SS0L         (*(volatile __near unsigned char  *)0x122)
+#define SS0L_bit     (*(volatile __near __bitf_T *)0x122)
+#define ST0          (*(volatile __near unsigned short *)0x124)
+#define ST0L         (*(volatile __near unsigned char  *)0x124)
+#define ST0L_bit     (*(volatile __near __bitf_T *)0x124)
+#define SPS0         (*(volatile __near unsigned short *)0x126)
+#define SPS0L        (*(volatile __near unsigned char  *)0x126)
+#define SO0          (*(volatile __near unsigned short *)0x128)
+#define SOE0         (*(volatile __near unsigned short *)0x12A)
+#define SOE0L        (*(volatile __near unsigned char  *)0x12A)
+#define SOE0L_bit    (*(volatile __near __bitf_T *)0x12A)
+#define SOL0         (*(volatile __near unsigned short *)0x134)
+#define SOL0L        (*(volatile __near unsigned char  *)0x134)
+#define SSC0         (*(volatile __near unsigned short *)0x138)
+#define SSC0L        (*(volatile __near unsigned char  *)0x138)
+#define TCR00        (*(volatile __near unsigned short *)0x180)
+#define TCR01        (*(volatile __near unsigned short *)0x182)
+#define TCR02        (*(volatile __near unsigned short *)0x184)
+#define TCR03        (*(volatile __near unsigned short *)0x186)
+#define TMR00        (*(volatile __near unsigned short *)0x190)
+#define TMR01        (*(volatile __near unsigned short *)0x192)
+#define TMR02        (*(volatile __near unsigned short *)0x194)
+#define TMR03        (*(volatile __near unsigned short *)0x196)
+#define TSR00        (*(volatile __near unsigned short *)0x1A0)
+#define TSR00L       (*(volatile __near unsigned char  *)0x1A0)
+#define TSR01        (*(volatile __near unsigned short *)0x1A2)
+#define TSR01L       (*(volatile __near unsigned char  *)0x1A2)
+#define TSR02        (*(volatile __near unsigned short *)0x1A4)
+#define TSR02L       (*(volatile __near unsigned char  *)0x1A4)
+#define TSR03        (*(volatile __near unsigned short *)0x1A6)
+#define TSR03L       (*(volatile __near unsigned char  *)0x1A6)
+#define TE0          (*(volatile __near unsigned short *)0x1B0)
+#define TE0L         (*(volatile __near unsigned char  *)0x1B0)
+#define TE0L_bit     (*(volatile __near __bitf_T *)0x1B0)
+#define TS0          (*(volatile __near unsigned short *)0x1B2)
+#define TS0L         (*(volatile __near unsigned char  *)0x1B2)
+#define TS0L_bit     (*(volatile __near __bitf_T *)0x1B2)
+#define TT0          (*(volatile __near unsigned short *)0x1B4)
+#define TT0L         (*(volatile __near unsigned char  *)0x1B4)
+#define TT0L_bit     (*(volatile __near __bitf_T *)0x1B4)
+#define TPS0         (*(volatile __near unsigned short *)0x1B6)
+#define TO0          (*(volatile __near unsigned short *)0x1B8)
+#define TO0L         (*(volatile __near unsigned char  *)0x1B8)
+#define TOE0         (*(volatile __near unsigned short *)0x1BA)
+#define TOE0L        (*(volatile __near unsigned char  *)0x1BA)
+#define TOE0L_bit    (*(volatile __near __bitf_T *)0x1BA)
+#define TOL0         (*(volatile __near unsigned short *)0x1BC)
+#define TOL0L        (*(volatile __near unsigned char  *)0x1BC)
+#define TOM0         (*(volatile __near unsigned short *)0x1BE)
+#define TOM0L        (*(volatile __near unsigned char  *)0x1BE)
+#define IICCTL00     (*(volatile __near unsigned char  *)0x230)
+#define IICCTL00_bit (*(volatile __near __bitf_T *)0x230)
+#define SPT0         (((volatile __near __bitf_T *)0x230)->no0)
+#define STT0         (((volatile __near __bitf_T *)0x230)->no1)
+#define ACKE0        (((volatile __near __bitf_T *)0x230)->no2)
+#define WTIM0        (((volatile __near __bitf_T *)0x230)->no3)
+#define SPIE0        (((volatile __near __bitf_T *)0x230)->no4)
+#define WREL0        (((volatile __near __bitf_T *)0x230)->no5)
+#define LREL0        (((volatile __near __bitf_T *)0x230)->no6)
+#define IICE0        (((volatile __near __bitf_T *)0x230)->no7)
+#define IICCTL01     (*(volatile __near unsigned char  *)0x231)
+#define IICCTL01_bit (*(volatile __near __bitf_T *)0x231)
+#define PRS0         (((volatile __near __bitf_T *)0x231)->no0)
+#define DFC0         (((volatile __near __bitf_T *)0x231)->no2)
+#define SMC0         (((volatile __near __bitf_T *)0x231)->no3)
+#define DAD0         (((volatile __near __bitf_T *)0x231)->no4)
+#define CLD0         (((volatile __near __bitf_T *)0x231)->no5)
+#define WUP0         (((volatile __near __bitf_T *)0x231)->no7)
+#define IICWL0       (*(volatile __near unsigned char  *)0x232)
+#define IICWH0       (*(volatile __near unsigned char  *)0x233)
+#define SVA0         (*(volatile __near unsigned char  *)0x234)
+#define CRCD         (*(volatile __near unsigned short *)0x2FA)
+#define P1           (*(volatile __near unsigned char  *)0xFF01)
+#define P1_bit       (*(volatile __near __bitf_T *)0xFF01)
+#define P2           (*(volatile __near unsigned char  *)0xFF02)
+#define P2_bit       (*(volatile __near __bitf_T *)0xFF02)
+#define P4           (*(volatile __near unsigned char  *)0xFF04)
+#define P4_bit       (*(volatile __near __bitf_T *)0xFF04)
+#define P6           (*(volatile __near unsigned char  *)0xFF06)
+#define P6_bit       (*(volatile __near __bitf_T *)0xFF06)
+#define P12          (*(volatile __near unsigned char  *)0xFF0C)
+#define P12_bit      (*(volatile __near __bitf_T *)0xFF0C)
+#define P13          (*(volatile __near unsigned char  *)0xFF0D)
+#define P13_bit      (*(volatile __near __bitf_T *)0xFF0D)
+#define SDR00        (*(volatile __near unsigned short *)0xFF10)
+#define SIO00        (*(volatile __near unsigned char  *)0xFF10)
+#define TXD0         (*(volatile __near unsigned char  *)0xFF10)
+#define SDR01        (*(volatile __near unsigned short *)0xFF12)
+#define RXD0         (*(volatile __near unsigned char  *)0xFF12)
+#define SIO01        (*(volatile __near unsigned char  *)0xFF12)
+#define TDR00        (*(volatile __near unsigned short *)0xFF18)
+#define TDR01        (*(volatile __near unsigned short *)0xFF1A)
+#define TDR01L       (*(volatile __near unsigned char  *)0xFF1A)
+#define TDR01H       (*(volatile __near unsigned char  *)0xFF1B)
+#define ADCR         (*(volatile __near unsigned short *)0xFF1E)
+#define ADCRH        (*(volatile __near unsigned char  *)0xFF1F)
+#define PM1          (*(volatile __near unsigned char  *)0xFF21)
+#define PM1_bit      (*(volatile __near __bitf_T *)0xFF21)
+#define PM2          (*(volatile __near unsigned char  *)0xFF22)
+#define PM2_bit      (*(volatile __near __bitf_T *)0xFF22)
+#define PM4          (*(volatile __near unsigned char  *)0xFF24)
+#define PM4_bit      (*(volatile __near __bitf_T *)0xFF24)
+#define PM6          (*(volatile __near unsigned char  *)0xFF26)
+#define PM6_bit      (*(volatile __near __bitf_T *)0xFF26)
+#define ADM0         (*(volatile __near unsigned char  *)0xFF30)
+#define ADM0_bit     (*(volatile __near __bitf_T *)0xFF30)
+#define ADCE         (((volatile __near __bitf_T *)0xFF30)->no0)
+#define ADCS         (((volatile __near __bitf_T *)0xFF30)->no7)
+#define ADS          (*(volatile __near unsigned char  *)0xFF31)
+#define ADS_bit      (*(volatile __near __bitf_T *)0xFF31)
+#define ADM1         (*(volatile __near unsigned char  *)0xFF32)
+#define ADM1_bit     (*(volatile __near __bitf_T *)0xFF32)
+#define KRCTL        (*(volatile __near unsigned char  *)0xFF34)
+#define KRCTL_bit    (*(volatile __near __bitf_T *)0xFF34)
+#define KRF          (*(volatile __near unsigned char  *)0xFF35)
+#define KRM0         (*(volatile __near unsigned char  *)0xFF37)
+#define KRM0_bit     (*(volatile __near __bitf_T *)0xFF37)
+#define EGP0         (*(volatile __near unsigned char  *)0xFF38)
+#define EGP0_bit     (*(volatile __near __bitf_T *)0xFF38)
+#define EGN0         (*(volatile __near unsigned char  *)0xFF39)
+#define EGN0_bit     (*(volatile __near __bitf_T *)0xFF39)
+#define IICA0        (*(volatile __near unsigned char  *)0xFF50)
+#define IICS0        (*(volatile __near unsigned char  *)0xFF51)
+#define IICS0_bit    (*(volatile __near __bitf_T *)0xFF51)
+#define SPD0         (((volatile __near __bitf_T *)0xFF51)->no0)
+#define STD0         (((volatile __near __bitf_T *)0xFF51)->no1)
+#define ACKD0        (((volatile __near __bitf_T *)0xFF51)->no2)
+#define TRC0         (((volatile __near __bitf_T *)0xFF51)->no3)
+#define COI0         (((volatile __near __bitf_T *)0xFF51)->no4)
+#define EXC0         (((volatile __near __bitf_T *)0xFF51)->no5)
+#define ALD0         (((volatile __near __bitf_T *)0xFF51)->no6)
+#define MSTS0        (((volatile __near __bitf_T *)0xFF51)->no7)
+#define IICF0        (*(volatile __near unsigned char  *)0xFF52)
+#define IICF0_bit    (*(volatile __near __bitf_T *)0xFF52)
+#define IICRSV0      (((volatile __near __bitf_T *)0xFF52)->no0)
+#define STCEN0       (((volatile __near __bitf_T *)0xFF52)->no1)
+#define IICBSY0      (((volatile __near __bitf_T *)0xFF52)->no6)
+#define STCF0        (((volatile __near __bitf_T *)0xFF52)->no7)
+#define TDR02        (*(volatile __near unsigned short *)0xFF64)
+#define TDR03        (*(volatile __near unsigned short *)0xFF66)
+#define TDR03L       (*(volatile __near unsigned char  *)0xFF66)
+#define TDR03H       (*(volatile __near unsigned char  *)0xFF67)
+#define ITMC         (*(volatile __near unsigned short *)0xFF90)
+#define CMC          (*(volatile __near unsigned char  *)0xFFA0)
+#define CSC          (*(volatile __near unsigned char  *)0xFFA1)
+#define CSC_bit      (*(volatile __near __bitf_T *)0xFFA1)
+#define HIOSTOP      (((volatile __near __bitf_T *)0xFFA1)->no0)
+#define MSTOP        (((volatile __near __bitf_T *)0xFFA1)->no7)
+#define OSTC         (*(volatile __near unsigned char  *)0xFFA2)
+#define OSTC_bit     (*(volatile __near __bitf_T *)0xFFA2)
+#define OSTS         (*(volatile __near unsigned char  *)0xFFA3)
+#define CKC          (*(volatile __near unsigned char  *)0xFFA4)
+#define CKC_bit      (*(volatile __near __bitf_T *)0xFFA4)
+#define MCM0         (((volatile __near __bitf_T *)0xFFA4)->no4)
+#define MCS          (((volatile __near __bitf_T *)0xFFA4)->no5)
+#define CKS0         (*(volatile __near unsigned char  *)0xFFA5)
+#define CKS0_bit     (*(volatile __near __bitf_T *)0xFFA5)
+#define PCLOE0       (((volatile __near __bitf_T *)0xFFA5)->no7)
+#define RESF         (*(volatile __near unsigned char  *)0xFFA8)
+#define LVIM         (*(volatile __near unsigned char  *)0xFFA9)
+#define LVIM_bit     (*(volatile __near __bitf_T *)0xFFA9)
+#define LVIF         (((volatile __near __bitf_T *)0xFFA9)->no0)
+#define LVIOMSK      (((volatile __near __bitf_T *)0xFFA9)->no1)
+#define LVISEN       (((volatile __near __bitf_T *)0xFFA9)->no7)
+#define LVIS         (*(volatile __near unsigned char  *)0xFFAA)
+#define LVIS_bit     (*(volatile __near __bitf_T *)0xFFAA)
+#define LVILV        (((volatile __near __bitf_T *)0xFFAA)->no0)
+#define LVIMD        (((volatile __near __bitf_T *)0xFFAA)->no7)
+#define WDTE         (*(volatile __near unsigned char  *)0xFFAB)
+#define CRCIN        (*(volatile __near unsigned char  *)0xFFAC)
+#define DSA0         (*(volatile __near unsigned char  *)0xFFB0)
+#define DSA1         (*(volatile __near unsigned char  *)0xFFB1)
+#define DRA0         (*(volatile __near unsigned short *)0xFFB2)
+#define DRA0L        (*(volatile __near unsigned char  *)0xFFB2)
+#define DRA0H        (*(volatile __near unsigned char  *)0xFFB3)
+#define DRA1         (*(volatile __near unsigned short *)0xFFB4)
+#define DRA1L        (*(volatile __near unsigned char  *)0xFFB4)
+#define DRA1H        (*(volatile __near unsigned char  *)0xFFB5)
+#define DBC0         (*(volatile __near unsigned short *)0xFFB6)
+#define DBC0L        (*(volatile __near unsigned char  *)0xFFB6)
+#define DBC0H        (*(volatile __near unsigned char  *)0xFFB7)
+#define DBC1         (*(volatile __near unsigned short *)0xFFB8)
+#define DBC1L        (*(volatile __near unsigned char  *)0xFFB8)
+#define DBC1H        (*(volatile __near unsigned char  *)0xFFB9)
+#define DMC0         (*(volatile __near unsigned char  *)0xFFBA)
+#define DMC0_bit     (*(volatile __near __bitf_T *)0xFFBA)
+#define DWAIT0       (((volatile __near __bitf_T *)0xFFBA)->no4)
+#define DS0          (((volatile __near __bitf_T *)0xFFBA)->no5)
+#define DRS0         (((volatile __near __bitf_T *)0xFFBA)->no6)
+#define STG0         (((volatile __near __bitf_T *)0xFFBA)->no7)
+#define DMC1         (*(volatile __near unsigned char  *)0xFFBB)
+#define DMC1_bit     (*(volatile __near __bitf_T *)0xFFBB)
+#define DWAIT1       (((volatile __near __bitf_T *)0xFFBB)->no4)
+#define DS1          (((volatile __near __bitf_T *)0xFFBB)->no5)
+#define DRS1         (((volatile __near __bitf_T *)0xFFBB)->no6)
+#define STG1         (((volatile __near __bitf_T *)0xFFBB)->no7)
+#define DRC0         (*(volatile __near unsigned char  *)0xFFBC)
+#define DRC0_bit     (*(volatile __near __bitf_T *)0xFFBC)
+#define DST0         (((volatile __near __bitf_T *)0xFFBC)->no0)
+#define DEN0         (((volatile __near __bitf_T *)0xFFBC)->no7)
+#define DRC1         (*(volatile __near unsigned char  *)0xFFBD)
+#define DRC1_bit     (*(volatile __near __bitf_T *)0xFFBD)
+#define DST1         (((volatile __near __bitf_T *)0xFFBD)->no0)
+#define DEN1         (((volatile __near __bitf_T *)0xFFBD)->no7)
+#define IF0          (*(volatile __near unsigned short *)0xFFE0)
+#define IF0L         (*(volatile __near unsigned char  *)0xFFE0)
+#define IF0L_bit     (*(volatile __near __bitf_T *)0xFFE0)
+#define IF0H         (*(volatile __near unsigned char  *)0xFFE1)
+#define IF0H_bit     (*(volatile __near __bitf_T *)0xFFE1)
+#define WDTIIF       (((volatile __near __bitf_T *)0xFFE0)->no0)
+#define LVIIF        (((volatile __near __bitf_T *)0xFFE0)->no1)
+#define PIF0         (((volatile __near __bitf_T *)0xFFE0)->no2)
+#define PIF1         (((volatile __near __bitf_T *)0xFFE0)->no3)
+#define PIF2         (((volatile __near __bitf_T *)0xFFE0)->no4)
+#define PIF3         (((volatile __near __bitf_T *)0xFFE0)->no5)
+#define DMAIF0       (((volatile __near __bitf_T *)0xFFE0)->no6)
+#define DMAIF1       (((volatile __near __bitf_T *)0xFFE0)->no7)
+#define CSIIF00      (((volatile __near __bitf_T *)0xFFE1)->no0)
+#define IICIF00      (((volatile __near __bitf_T *)0xFFE1)->no0)
+#define STIF0        (((volatile __near __bitf_T *)0xFFE1)->no0)
+#define CSIIF01      (((volatile __near __bitf_T *)0xFFE1)->no1)
+#define IICIF01      (((volatile __near __bitf_T *)0xFFE1)->no1)
+#define SRIF0        (((volatile __near __bitf_T *)0xFFE1)->no1)
+#define SREIF0       (((volatile __near __bitf_T *)0xFFE1)->no2)
+#define TMIF01H      (((volatile __near __bitf_T *)0xFFE1)->no3)
+#define TMIF03H      (((volatile __near __bitf_T *)0xFFE1)->no4)
+#define IICAIF0      (((volatile __near __bitf_T *)0xFFE1)->no5)
+#define TMIF00       (((volatile __near __bitf_T *)0xFFE1)->no6)
+#define TMIF01       (((volatile __near __bitf_T *)0xFFE1)->no7)
+#define IF1          (*(volatile __near unsigned short *)0xFFE2)
+#define IF1L         (*(volatile __near unsigned char  *)0xFFE2)
+#define IF1L_bit     (*(volatile __near __bitf_T *)0xFFE2)
+#define TMIF02       (((volatile __near __bitf_T *)0xFFE2)->no0)
+#define TMIF03       (((volatile __near __bitf_T *)0xFFE2)->no1)
+#define ADIF         (((volatile __near __bitf_T *)0xFFE2)->no2)
+#define TMKAIF       (((volatile __near __bitf_T *)0xFFE2)->no3)
+#define KRIF         (((volatile __near __bitf_T *)0xFFE2)->no4)
+#define MDIF         (((volatile __near __bitf_T *)0xFFE2)->no5)
+#define FLIF         (((volatile __near __bitf_T *)0xFFE2)->no6)
+#define MK0          (*(volatile __near unsigned short *)0xFFE4)
+#define MK0L         (*(volatile __near unsigned char  *)0xFFE4)
+#define MK0L_bit     (*(volatile __near __bitf_T *)0xFFE4)
+#define MK0H         (*(volatile __near unsigned char  *)0xFFE5)
+#define MK0H_bit     (*(volatile __near __bitf_T *)0xFFE5)
+#define WDTIMK       (((volatile __near __bitf_T *)0xFFE4)->no0)
+#define LVIMK        (((volatile __near __bitf_T *)0xFFE4)->no1)
+#define PMK0         (((volatile __near __bitf_T *)0xFFE4)->no2)
+#define PMK1         (((volatile __near __bitf_T *)0xFFE4)->no3)
+#define PMK2         (((volatile __near __bitf_T *)0xFFE4)->no4)
+#define PMK3         (((volatile __near __bitf_T *)0xFFE4)->no5)
+#define DMAMK0       (((volatile __near __bitf_T *)0xFFE4)->no6)
+#define DMAMK1       (((volatile __near __bitf_T *)0xFFE4)->no7)
+#define CSIMK00      (((volatile __near __bitf_T *)0xFFE5)->no0)
+#define IICMK00      (((volatile __near __bitf_T *)0xFFE5)->no0)
+#define STMK0        (((volatile __near __bitf_T *)0xFFE5)->no0)
+#define CSIMK01      (((volatile __near __bitf_T *)0xFFE5)->no1)
+#define IICMK01      (((volatile __near __bitf_T *)0xFFE5)->no1)
+#define SRMK0        (((volatile __near __bitf_T *)0xFFE5)->no1)
+#define SREMK0       (((volatile __near __bitf_T *)0xFFE5)->no2)
+#define TMMK01H      (((volatile __near __bitf_T *)0xFFE5)->no3)
+#define TMMK03H      (((volatile __near __bitf_T *)0xFFE5)->no4)
+#define IICAMK0      (((volatile __near __bitf_T *)0xFFE5)->no5)
+#define TMMK00       (((volatile __near __bitf_T *)0xFFE5)->no6)
+#define TMMK01       (((volatile __near __bitf_T *)0xFFE5)->no7)
+#define MK1          (*(volatile __near unsigned short *)0xFFE6)
+#define MK1L         (*(volatile __near unsigned char  *)0xFFE6)
+#define MK1L_bit     (*(volatile __near __bitf_T *)0xFFE6)
+#define TMMK02       (((volatile __near __bitf_T *)0xFFE6)->no0)
+#define TMMK03       (((volatile __near __bitf_T *)0xFFE6)->no1)
+#define ADMK         (((volatile __near __bitf_T *)0xFFE6)->no2)
+#define TMKAMK       (((volatile __near __bitf_T *)0xFFE6)->no3)
+#define KRMK         (((volatile __near __bitf_T *)0xFFE6)->no4)
+#define MDMK         (((volatile __near __bitf_T *)0xFFE6)->no5)
+#define FLMK         (((volatile __near __bitf_T *)0xFFE6)->no6)
+#define PR00         (*(volatile __near unsigned short *)0xFFE8)
+#define PR00L        (*(volatile __near unsigned char  *)0xFFE8)
+#define PR00L_bit    (*(volatile __near __bitf_T *)0xFFE8)
+#define PR00H        (*(volatile __near unsigned char  *)0xFFE9)
+#define PR00H_bit    (*(volatile __near __bitf_T *)0xFFE9)
+#define WDTIPR0      (((volatile __near __bitf_T *)0xFFE8)->no0)
+#define LVIPR0       (((volatile __near __bitf_T *)0xFFE8)->no1)
+#define PPR00        (((volatile __near __bitf_T *)0xFFE8)->no2)
+#define PPR01        (((volatile __near __bitf_T *)0xFFE8)->no3)
+#define PPR02        (((volatile __near __bitf_T *)0xFFE8)->no4)
+#define PPR03        (((volatile __near __bitf_T *)0xFFE8)->no5)
+#define DMAPR00      (((volatile __near __bitf_T *)0xFFE8)->no6)
+#define DMAPR01      (((volatile __near __bitf_T *)0xFFE8)->no7)
+#define CSIPR000     (((volatile __near __bitf_T *)0xFFE9)->no0)
+#define IICPR000     (((volatile __near __bitf_T *)0xFFE9)->no0)
+#define STPR00       (((volatile __near __bitf_T *)0xFFE9)->no0)
+#define CSIPR001     (((volatile __near __bitf_T *)0xFFE9)->no1)
+#define IICPR001     (((volatile __near __bitf_T *)0xFFE9)->no1)
+#define SRPR00       (((volatile __near __bitf_T *)0xFFE9)->no1)
+#define SREPR00      (((volatile __near __bitf_T *)0xFFE9)->no2)
+#define TMPR001H     (((volatile __near __bitf_T *)0xFFE9)->no3)
+#define TMPR003H     (((volatile __near __bitf_T *)0xFFE9)->no4)
+#define IICAPR00     (((volatile __near __bitf_T *)0xFFE9)->no5)
+#define TMPR000      (((volatile __near __bitf_T *)0xFFE9)->no6)
+#define TMPR001      (((volatile __near __bitf_T *)0xFFE9)->no7)
+#define PR01         (*(volatile __near unsigned short *)0xFFEA)
+#define PR01L        (*(volatile __near unsigned char  *)0xFFEA)
+#define PR01L_bit    (*(volatile __near __bitf_T *)0xFFEA)
+#define TMPR002      (((volatile __near __bitf_T *)0xFFEA)->no0)
+#define TMPR003      (((volatile __near __bitf_T *)0xFFEA)->no1)
+#define ADPR0        (((volatile __near __bitf_T *)0xFFEA)->no2)
+#define TMKAPR0      (((volatile __near __bitf_T *)0xFFEA)->no3)
+#define KRPR0        (((volatile __near __bitf_T *)0xFFEA)->no4)
+#define MDPR0        (((volatile __near __bitf_T *)0xFFEA)->no5)
+#define FLPR0        (((volatile __near __bitf_T *)0xFFEA)->no6)
+#define PR10         (*(volatile __near unsigned short *)0xFFEC)
+#define PR10L        (*(volatile __near unsigned char  *)0xFFEC)
+#define PR10L_bit    (*(volatile __near __bitf_T *)0xFFEC)
+#define PR10H        (*(volatile __near unsigned char  *)0xFFED)
+#define PR10H_bit    (*(volatile __near __bitf_T *)0xFFED)
+#define WDTIPR1      (((volatile __near __bitf_T *)0xFFEC)->no0)
+#define LVIPR1       (((volatile __near __bitf_T *)0xFFEC)->no1)
+#define PPR10        (((volatile __near __bitf_T *)0xFFEC)->no2)
+#define PPR11        (((volatile __near __bitf_T *)0xFFEC)->no3)
+#define PPR12        (((volatile __near __bitf_T *)0xFFEC)->no4)
+#define PPR13        (((volatile __near __bitf_T *)0xFFEC)->no5)
+#define DMAPR10      (((volatile __near __bitf_T *)0xFFEC)->no6)
+#define DMAPR11      (((volatile __near __bitf_T *)0xFFEC)->no7)
+#define CSIPR100     (((volatile __near __bitf_T *)0xFFED)->no0)
+#define IICPR100     (((volatile __near __bitf_T *)0xFFED)->no0)
+#define STPR10       (((volatile __near __bitf_T *)0xFFED)->no0)
+#define CSIPR101     (((volatile __near __bitf_T *)0xFFED)->no1)
+#define IICPR101     (((volatile __near __bitf_T *)0xFFED)->no1)
+#define SRPR10       (((volatile __near __bitf_T *)0xFFED)->no1)
+#define SREPR10      (((volatile __near __bitf_T *)0xFFED)->no2)
+#define TMPR101H     (((volatile __near __bitf_T *)0xFFED)->no3)
+#define TMPR103H     (((volatile __near __bitf_T *)0xFFED)->no4)
+#define IICAPR10     (((volatile __near __bitf_T *)0xFFED)->no5)
+#define TMPR100      (((volatile __near __bitf_T *)0xFFED)->no6)
+#define TMPR101      (((volatile __near __bitf_T *)0xFFED)->no7)
+#define PR11         (*(volatile __near unsigned short *)0xFFEE)
+#define PR11L        (*(volatile __near unsigned char  *)0xFFEE)
+#define PR11L_bit    (*(volatile __near __bitf_T *)0xFFEE)
+#define TMPR102      (((volatile __near __bitf_T *)0xFFEE)->no0)
+#define TMPR103      (((volatile __near __bitf_T *)0xFFEE)->no1)
+#define ADPR1        (((volatile __near __bitf_T *)0xFFEE)->no2)
+#define TMKAPR1      (((volatile __near __bitf_T *)0xFFEE)->no3)
+#define KRPR1        (((volatile __near __bitf_T *)0xFFEE)->no4)
+#define MDPR1        (((volatile __near __bitf_T *)0xFFEE)->no5)
+#define FLPR1        (((volatile __near __bitf_T *)0xFFEE)->no6)
+#define MDAL         (*(volatile __near unsigned short *)0xFFF0)
+#define MULA         (*(volatile __near unsigned short *)0xFFF0)
+#define MDAH         (*(volatile __near unsigned short *)0xFFF2)
+#define MULB         (*(volatile __near unsigned short *)0xFFF2)
+#define MDBH         (*(volatile __near unsigned short *)0xFFF4)
+#define MULOH        (*(volatile __near unsigned short *)0xFFF4)
+#define MDBL         (*(volatile __near unsigned short *)0xFFF6)
+#define MULOL        (*(volatile __near unsigned short *)0xFFF6)
+#define PMC          (*(volatile __near unsigned char  *)0xFFFE)
+#define PMC_bit      (*(volatile __near __bitf_T *)0xFFFE)
+#define MAA          (((volatile __near __bitf_T *)0xFFFE)->no0)
+
+
+#define INTWDTI                         0x0004
+#define INTLVI                          0x0006
+#define INTP0                           0x0008
+#define INTP1                           0x000A
+#define INTP2                           0x000C
+#define INTP3                           0x000E
+#define INTDMA0                         0x0010
+#define INTDMA1                         0x0012
+#define INTCSI00                        0x0014
+#define INTIIC00                        0x0014
+#define INTST0                          0x0014
+#define INTCSI01                        0x0016
+#define INTIIC01                        0x0016
+#define INTSR0                          0x0016
+#define INTSRE0                         0x0018
+#define INTTM01H                        0x001A
+#define INTTM03H                        0x001C
+#define INTIICA0                        0x001E
+#define INTTM00                         0x0020
+#define INTTM01                         0x0022
+#define INTTM02                         0x0024
+#define INTTM03                         0x0026
+#define INTAD                           0x0028
+#define INTIT                           0x002A
+#define INTKR                           0x002C
+#define INTMD                           0x002E
+#define INTFL                           0x0030
+
+#endif
diff --git a/r_cg_adc.c b/r_cg_adc.c
new file mode 100644
index 0000000..586a115
--- /dev/null
+++ b/r_cg_adc.c
@@ -0,0 +1,138 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2023-10-05
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_adc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Create
+* Description  : This function initializes the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Create(void)
+{    
+    ADCEN = 1U;  /* supply AD clock */
+    ADM0 = _00_AD_ADM0_INITIALVALUE;  /* disable AD conversion and clear ADM0 register */
+    ADMK = 1U;  /* disable INTAD interrupt */
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+    /* Set INTAD low priority */
+    ADPR1 = 1U;
+    ADPR0 = 1U;
+    /* The reset status of ADPC is analog input, so it's unnecessary to set. */
+    /* Set ANI0 - ANI1 pin as analog input */
+    PM2 |= 0x03U;
+    ADM0 = _08_AD_CONVERSION_CLOCK_32 | _00_AD_TIME_MODE_NORMAL_1 | _00_AD_OPERMODE_SELECT;
+    ADM1 = _80_AD_TRIGGER_HARDWARE_NOWAIT | _20_AD_CONVMODE_ONESELECT | _00_AD_TRIGGER_INTTM01;
+    ADM2 = _00_AD_POSITIVE_VDD | _00_AD_NEGATIVE_VSS | _00_AD_AREA_MODE_1 | _00_AD_RESOLUTION_10BIT;          
+    ADUL = _FF_AD_ADUL_VALUE;
+    ADLL = _00_AD_ADLL_VALUE;
+    ADS = _00_AD_INPUT_CHANNEL_0;
+    ADCE = 1U;  /* enable AD comparator */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Start
+* Description  : This function starts the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Start(void)
+{
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+    ADMK = 0U;  /* enable INTAD interrupt */
+    ADCS = 1U;  /* enable AD conversion */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Stop
+* Description  : This function stops the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Stop(void)
+{
+    ADCS = 0U;  /* disable AD conversion */
+    ADMK = 1U;  /* disable INTAD interrupt */
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Set_OperationOn
+* Description  : This function enables comparator operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Set_OperationOn(void)
+{
+    ADCE = 1U;  /* enable AD comparator */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Set_OperationOff
+* Description  : This function stops comparator operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Set_OperationOff(void)
+{
+    ADCE = 0U;  /* disable AD comparator */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Get_Result
+* Description  : This function returns the conversion result in the buffer.
+* Arguments    : buffer -
+*                    the address where to write the conversion result
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Get_Result(uint16_t * const buffer)
+{
+    *buffer = (uint16_t)(ADCR >> 6U);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_adc.h b/r_cg_adc.h
new file mode 100644
index 0000000..ab8ecf1
--- /dev/null
+++ b/r_cg_adc.h
@@ -0,0 +1,179 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2023-10-05
+***********************************************************************************************************************/
+
+#ifndef ADC_H
+#define ADC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Peripheral enable register 0 (PER0)
+*/
+/* Control of AD converter input clock (ADCEN) */
+#define _00_AD_CLOCK_STOP               (0x00U) /* stop supply of input clock */
+#define _20_AD_CLOCK_SUPPLY             (0x20U) /* supply input clock */
+
+/*
+    AD converter mode register 0 (ADM0)
+*/
+#define _00_AD_ADM0_INITIALVALUE        (0x00U)
+/* AD conversion operation control (ADCS) */
+#define _80_AD_CONVERSION_ENABLE        (0x80U) /* enable AD conversion operation control */
+#define _00_AD_CONVERSION_DISABLE       (0x00U) /* disable AD conversion operation control */
+/* Specification of AD conversion operation mode (ADMD) */
+#define _00_AD_OPERMODE_SELECT          (0x00U) /* select operation mode */
+#define _40_AD_OPERMODE_SCAN            (0x40U) /* scan operation mode */
+/* AD conversion clock selection (FR2 - FR0) */
+#define _00_AD_CONVERSION_CLOCK_64      (0x00U) /* fCLK/64 */
+#define _08_AD_CONVERSION_CLOCK_32      (0x08U) /* fCLK/32 */
+#define _10_AD_CONVERSION_CLOCK_16      (0x10U) /* fCLK/16 */
+#define _18_AD_CONVERSION_CLOCK_8       (0x18U) /* fCLK/8 */
+#define _20_AD_CONVERSION_CLOCK_6       (0x20U) /* fCLK/6 */
+#define _28_AD_CONVERSION_CLOCK_5       (0x28U) /* fCLK/5 */
+#define _30_AD_CONVERSION_CLOCK_4       (0x30U) /* fCLK/4 */
+#define _38_AD_CONVERSION_CLOCK_2       (0x38U) /* fCLK/2 */
+/* Specification AD conversion time mode (LV1, LV0) */
+#define _00_AD_TIME_MODE_NORMAL_1       (0x00U) /* normal 1 mode */
+#define _02_AD_TIME_MODE_NORMAL_2       (0x02U) /* normal 2 mode */
+#define _04_AD_TIME_MODE_LOWVOLTAGE_1   (0x04U) /* low-voltage 1 mode */
+#define _06_AD_TIME_MODE_LOWVOLTAGE_2   (0x06U) /* low-voltage 2 mode */
+/* AD comparator operation control (ADCE) */
+#define _01_AD_COMPARATOR_ENABLE        (0x01U) /* enable comparator operation control */
+#define _00_AD_COMPARATOR_DISABLE       (0x00U) /* disable comparator operation control */
+
+/*
+    Analog input channel specification register (ADS)
+*/
+/* Specification of analog input channel (ADISS, ADS4 - ADS0) */
+/* Select mode */
+#define _00_AD_INPUT_CHANNEL_0          (0x00U) /* ANI0 */
+#define _01_AD_INPUT_CHANNEL_1          (0x01U) /* ANI1 */
+#define _02_AD_INPUT_CHANNEL_2          (0x02U) /* ANI2 */
+#define _03_AD_INPUT_CHANNEL_3          (0x03U) /* ANI3 */
+#define _10_AD_INPUT_CHANNEL_16         (0x10U) /* ANI16 */
+#define _11_AD_INPUT_CHANNEL_17         (0x11U) /* ANI17 */
+#define _12_AD_INPUT_CHANNEL_18         (0x12U) /* ANI18 */
+#define _13_AD_INPUT_CHANNEL_19         (0x13U) /* ANI19 */
+#define _14_AD_INPUT_CHANNEL_20         (0x14U) /* ANI20 */
+#define _15_AD_INPUT_CHANNEL_21         (0x15U) /* ANI21 */
+#define _16_AD_INPUT_CHANNEL_22         (0x16U) /* ANI22 */
+#define _80_AD_INPUT_TEMPERSENSOR_0     (0x80U) /* temperature sensor 0 output is used to be the input channel */
+#define _81_AD_INPUT_INTERREFVOLT       (0x81U) /* internal reference voltage output is used to be the input channel */
+/* Scan mode */
+#define _00_AD_INPUT_CHANNEL_0_3        (0x00U) /* ANI0 - ANI3 */
+
+/*
+    AD converter mode register 1 (ADM1)
+*/
+/* AD trigger mode selection (ADTMD1, ADTMD0) */
+#define _00_AD_TRIGGER_SOFTWARE         (0x00U) /* software trigger mode */
+#define _80_AD_TRIGGER_HARDWARE_NOWAIT  (0x80U) /* hardware trigger mode (no wait) */
+#define _C0_AD_TRIGGER_HARDWARE_WAIT    (0xC0U) /* hardware trigger mode (wait) */
+/* AD convertion mode selection (ADSCM) */
+#define _00_AD_CONVMODE_CONSELECT       (0x00U) /* continuous convertion mode */
+#define _20_AD_CONVMODE_ONESELECT       (0x20U) /* oneshot convertion mode */
+/* Trigger signal selection (ADTRS1, ADTRS0) */
+#define _00_AD_TRIGGER_INTTM01          (0x00U) /* INTTM01 */
+#define _03_AD_TRIGGER_INTIT            (0x03U) /* INTIT */
+
+/*
+    AD converter mode register 2 (ADM2)
+*/
+/* AD VREF(+) selection (ADREFP1, ADREFP0) */
+#define _00_AD_POSITIVE_VDD             (0x00U) /* use VDD as VREF(+) */
+#define _40_AD_POSITIVE_AVREFP          (0x40U) /* use AVREFP as VREF(+) */
+#define _80_AD_POSITIVE_INTERVOLT       (0x80U) /* use internal voltage as VREF(+) */
+/* AD VREF(-) selection (ADREFM) */
+#define _00_AD_NEGATIVE_VSS             (0x00U) /* use VSS as VREF(-) */
+#define _20_AD_NEGATIVE_AVREFM          (0x20U) /* use AVREFM as VREF(-) */
+/* AD conversion result upper/lower bound value selection (ADRCK) */
+#define _00_AD_AREA_MODE_1              (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */
+#define _08_AD_AREA_MODE_2_3            (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */
+/* AD wakeup function selection (AWC) */
+#define _00_AD_WAKEUP_OFF               (0x00U) /* stop wakeup function */
+#define _04_AD_WAKEUP_ON                (0x04U) /* use wakeup function */
+/* AD resolution selection (ADTYP) */
+#define _00_AD_RESOLUTION_10BIT         (0x00U) /* 10 bits */
+#define _01_AD_RESOLUTION_8BIT          (0x01U) /* 8 bits */
+
+/*
+    AD test function register (ADTES)
+*/
+/* AD test mode signal (ADTES1, ADTES0) */
+#define _00_AD_NORMAL_INPUT             (0x00U) /* normal mode */
+#define _02_AD_TEST_AVREFM              (0x02U) /* use AVREFM as test signal */
+#define _03_AD_TEST_AVREFP              (0x03U) /* use AVREFP as test signal */
+
+/*
+    AD port configuration register (ADPC)
+*/
+/* Analog input/digital input switching (ADPC3 - ADPC0) */
+#define _00_AD_ADPC_4ANALOG             (0x00U) /* ANI0 - ANI3 */
+#define _04_AD_ADPC_3ANALOG             (0x04U) /* ANI0 - ANI2 */
+#define _03_AD_ADPC_2ANALOG             (0x03U) /* ANI0 - ANI1 */
+#define _02_AD_ADPC_1ANALOG             (0x02U) /* ANI0 */
+#define _01_AD_ADPC_0ANALOG             (0x01U) /* ANI0 - ANI4 (all digital) */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Upper bound (ADUL) value */
+#define _FF_AD_ADUL_VALUE               (0xFFU)
+/* Upper bound (ADLL) value */
+#define _00_AD_ADLL_VALUE               (0x00U)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef enum
+{
+    ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL16 = 16U, 
+    ADCHANNEL17, ADCHANNEL18, ADCHANNEL19, ADCHANNEL20, ADCHANNEL21, 
+    ADCHANNEL22, ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT
+} ad_channel_t;
+typedef enum
+{
+    ADNORMALINPUT,
+    ADAVREFM = 2U,
+    ADAVREFP
+} test_channel_t;
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_ADC_Create(void);
+void R_ADC_Start(void);
+void R_ADC_Stop(void);
+void R_ADC_Set_OperationOn(void);
+void R_ADC_Set_OperationOff(void);
+void R_ADC_Get_Result(uint16_t * const buffer);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_adc_user.c b/r_cg_adc_user.c
new file mode 100644
index 0000000..c4382c7
--- /dev/null
+++ b/r_cg_adc_user.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2023-10-05
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_adc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+#pragma interrupt r_adc_interrupt(vect=INTAD)
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+uint16_t g_AdVal[3];
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_adc_interrupt
+* Description  : This function is INTAD interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_adc_interrupt(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    switch (ADS)
+    {
+    case _00_AD_INPUT_CHANNEL_0:
+        R_ADC_Get_Result(g_AdVal);
+        ADS = _01_AD_INPUT_CHANNEL_1;
+        break;
+    case _01_AD_INPUT_CHANNEL_1:
+        R_ADC_Get_Result(g_AdVal+1);
+        ADS = _00_AD_INPUT_CHANNEL_0;
+        break;
+    default:
+        ADS = _00_AD_INPUT_CHANNEL_0;
+        break;
+    }
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_cgc.c b/r_cg_cgc.c
new file mode 100644
index 0000000..b7144ac
--- /dev/null
+++ b/r_cg_cgc.c
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description  : This function initializes the clock generator.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_CGC_Create(void)
+{
+    /* Set fMX */
+    CMC = _00_CGC_HISYS_PORT | _00_CGC_SYSOSC_DEFAULT;
+    MSTOP = 1U;
+    /* Set fMAIN */
+    MCM0 = 0U;
+    OSMC = _00_CGC_IT_CLK_NO;
+    /* Set fIH */
+    HIOSTOP = 0U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_cgc.h b/r_cg_cgc.h
new file mode 100644
index 0000000..a141060
--- /dev/null
+++ b/r_cg_cgc.h
@@ -0,0 +1,146 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef CGC_H
+#define CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Clock operation mode control register (CMC)
+*/
+/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */
+#define _C0_CGC_HISYS_PIN           (0xC0U)
+#define _00_CGC_HISYS_PORT          (0x00U) /* X1, X2 as I/O port */
+#define _40_CGC_HISYS_OSC           (0x40U) /* X1, X2 as crystal/ceramic resonator connection */
+#define _80_CGC_HISYS_PORT1         (0x80U) /* X1, X2 as I/O port */
+#define _C0_CGC_HISYS_EXT           (0xC0U) /* X1 as I/O port, X2 as external clock input */
+/* Control of X1 high-speed system clock oscillation frequency (AMPH) */
+#define _00_CGC_SYSOSC_DEFAULT      (0x00U)
+#define _00_CGC_SYSOSC_UNDER10M     (0x00U) /* fX <= 10MHz */
+#define _01_CGC_SYSOSC_OVER10M      (0x01U) /* fX > 10MHz */
+
+/*
+    Clock operation status control register (CSC)
+*/
+/* Control of high-speed system clock operation (MSTOP) */
+#define _00_CGC_HISYS_OPER          (0x00U) /* X1 oscillator/external clock operating */
+#define _80_CGC_HISYS_STOP          (0x80U) /* X1 oscillator/external clock stopped */
+/* High-speed OCO operation (HIOSTOP) */
+#define _00_CGC_HIO_OPER            (0x00U) /* high-speed OCO operating */
+#define _01_CGC_HIO_STOP            (0x01U) /* high-speed OCO stopped */
+
+/*
+    Oscillation stabilization time counter status register (OSTC)
+*/
+/* Oscillation stabilization time status (MOST18 - MOST8) */
+#define _00_CGC_OSCSTAB_STA0        (0x00U) /* < 2^8/fX */
+#define _80_CGC_OSCSTAB_STA8        (0x80U) /* 2^8/fX */
+#define _C0_CGC_OSCSTAB_STA9        (0xC0U) /* 2^9/fX */
+#define _E0_CGC_OSCSTAB_STA10       (0xE0U) /* 2^10/fX */
+#define _F0_CGC_OSCSTAB_STA11       (0xF0U) /* 2^11/fX */
+#define _F8_CGC_OSCSTAB_STA13       (0xF8U) /* 2^13/fX */
+#define _FC_CGC_OSCSTAB_STA15       (0xFCU) /* 2^15/fX */
+#define _FE_CGC_OSCSTAB_STA17       (0xFEU) /* 2^17/fX */
+#define _FF_CGC_OSCSTAB_STA18       (0xFFU) /* 2^18/fX */
+
+/*
+    Oscillation stabilization time select register (OSTS)
+*/
+/* Oscillation stabilization time selection (OSTS2 - OSTS0) */
+#define _00_CGC_OSCSTAB_SEL8        (0x00U) /* 2^8/fX */
+#define _01_CGC_OSCSTAB_SEL9        (0x01U) /* 2^9/fX */
+#define _02_CGC_OSCSTAB_SEL10       (0x02U) /* 2^10/fX */
+#define _03_CGC_OSCSTAB_SEL11       (0x03U) /* 2^11/fX */
+#define _04_CGC_OSCSTAB_SEL13       (0x04U) /* 2^13/fX */
+#define _05_CGC_OSCSTAB_SEL15       (0x05U) /* 2^15/fX */
+#define _06_CGC_OSCSTAB_SEL17       (0x06U) /* 2^17/fX */
+#define _07_CGC_OSCSTAB_SEL18       (0x07U) /* 2^18/fX */
+
+/*
+    System clock control register (CKC)
+*/
+/* Status of Main system clock fMAIN (MCS) */
+#define _00_CGC_MAINCLK_HIO         (0x00U) /* high-speed OCO clock (fIH) */
+#define _20_CGC_MAINCLK_HISYS       (0x20U) /* high-speed system clock (fMX) */
+/* Selection of Main system clock fMAIN (MCM0) */
+#define _00_CGC_MAINCLK_SELHIO      (0x00U) /* high-speed OCO clock (fIH) */
+#define _10_CGC_MAINCLK_SELHISYS    (0x10U) /* high-speed system clock (fMX) */
+
+/*
+    Operation speed mode control register (OSMC)
+*/
+/* Interval timer unit input clock supply (WUTMMCK0) */
+#define _00_CGC_IT_CLK_NO           (0x00U) /* stop */
+#define _10_CGC_IT_CLK_FIL          (0x10U) /* use fIL clcok */
+
+/*
+    Illegal memory access detection control register (IAWCTL)
+*/
+/* Illegal memory access detection control (IAWEN) */
+#define _00_CGC_ILLEGAL_ACCESS_OFF  (0x00U) /* disables illegal memory access detection */
+#define _80_CGC_ILLEGAL_ACCESS_ON   (0x80U) /* enables illegal memory access detection */
+/* RAM guard area (GRAM1, GRAM0) */
+#define _00_CGC_RAM_GUARD_OFF       (0x00U) /* invalid, it is possible to write RAM */
+#define _10_CGC_RAM_GUARD_ARAE0     (0x10U) /* 128 bytes from RAM bottom address */
+#define _20_CGC_RAM_GUARD_ARAE1     (0x20U) /* 256 bytes from RAM bottom address */
+#define _30_CGC_RAM_GUARD_ARAE2     (0x30U) /* 512 bytes from RAM bottom address */
+/* PORT register guard (GPORT) */
+#define _00_CGC_PORT_GUARD_OFF      (0x00U) /* invalid, it is possible to write PORT register */
+#define _04_CGC_PORT_GUARD_ON       (0x04U) /* valid, it is impossible to write PORT register, but possible for read */
+/* Interrupt register guard (GINT) */   
+#define _00_CGC_INT_GUARD_OFF       (0x00U) /* invalid, it is possible to write interrupt register */
+#define _02_CGC_INT_GUARD_ON        (0x02U) /* valid, impossible to write interrupt register, but possible for read */
+/* CSC register guard (GCSC) */         
+#define _00_CGC_CSC_GUARD_OFF       (0x00U) /* invalid, it is possible to write CSC register */
+#define _01_CGC_CSC_GUARD_ON        (0x01U) /* valid, it is impossible to write CSC register, but possible for read */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef enum
+{
+    HIOCLK, 
+    SYSX1CLK, 
+    SYSEXTCLK
+} clock_mode_t;
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Get_ResetSource(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_cgc_user.c b/r_cg_cgc_user.c
new file mode 100644
index 0000000..dee2715
--- /dev/null
+++ b/r_cg_cgc_user.c
@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Get_ResetSource
+* Description  : This function process of Reset.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_CGC_Get_ResetSource(void)
+{
+    uint8_t reset_flag = RESF;
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_macrodriver.h b/r_cg_macrodriver.h
new file mode 100644
index 0000000..1ced8ce
--- /dev/null
+++ b/r_cg_macrodriver.h
@@ -0,0 +1,88 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_macrodriver.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements general head file.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef STATUS_H
+#define STATUS_H
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "iodefine.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+#define DI      __DI
+#define EI      __EI
+#define HALT    __halt
+#define NOP     __nop
+#define STOP    __stop
+#define BRK     __brk
+
+/* Status list definition */
+#define MD_STATUSBASE       (0x00U)
+#define MD_OK               (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT              (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK             (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1            (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2            (MD_STATUSBASE + 0x04U) /* busy 2 */
+#define MD_OVERRUN           (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */
+
+/* Error list definition */
+#define MD_ERRORBASE        (0x80U)
+#define MD_ERROR            (MD_ERRORBASE + 0x00U)  /* error */
+#define MD_ARGERROR         (MD_ERRORBASE + 0x01U)  /* error agrument input error */
+#define MD_ERROR1           (MD_ERRORBASE + 0x02U)  /* error 1 */
+#define MD_ERROR2           (MD_ERRORBASE + 0x03U)  /* error 2 */
+#define MD_ERROR3           (MD_ERRORBASE + 0x04U)  /* error 3 */
+#define MD_ERROR4           (MD_ERRORBASE + 0x05U)  /* error 4 */
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+typedef signed char         int8_t;
+typedef unsigned char       uint8_t;
+typedef signed short        int16_t;
+typedef unsigned short      uint16_t;
+typedef signed long         int32_t;
+typedef unsigned long       uint32_t;
+typedef unsigned short      MD_STATUS;
+#define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+
+#endif
diff --git a/r_cg_port.c b/r_cg_port.c
new file mode 100644
index 0000000..b6f0f30
--- /dev/null
+++ b/r_cg_port.c
@@ -0,0 +1,71 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_PORT_Create
+* Description  : This function initializes the Port I/O.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_PORT_Create(void)
+{
+    P1 = _01_Pn0_OUTPUT_1 | _02_Pn1_OUTPUT_1 | _04_Pn2_OUTPUT_1 | _08_Pn3_OUTPUT_1 | _10_Pn4_OUTPUT_1;
+    P2 = _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0;
+    P4 = _02_Pn1_OUTPUT_1 | _04_Pn2_OUTPUT_1;
+    PMC1 = _00_PMCn0_DI_ON | _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _00_PMCn3_DI_ON | _00_PMCn4_DI_ON | _E0_PMC1_DEFAULT;
+    PMC4 = _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _F9_PMC4_DEFAULT;
+    ADPC = _01_ADPC_DI_ON;
+    PM1 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT |
+          _00_PMn4_MODE_OUTPUT | _E0_PM1_DEFAULT;
+    PM2 = _01_PMn0_MODE_INPUT | _02_PMn1_MODE_INPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _F0_PM2_DEFAULT;
+    PM4 = _01_PMn0_NOT_USE | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _F8_PM4_DEFAULT;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_port.h b/r_cg_port.h
new file mode 100644
index 0000000..89e2dfe
--- /dev/null
+++ b/r_cg_port.h
@@ -0,0 +1,200 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef PORT_H
+#define PORT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Port Mode Register (PMm)
+*/
+/* Pmn pin I/O mode selection (PMm7 - PMm0) */
+#define _01_PMn0_NOT_USE        (0x01U) /* not use Pn0 as digital I/O */
+#define _01_PMn0_MODE_INPUT     (0x01U) /* use Pn0 as input mode */
+#define _00_PMn0_MODE_OUTPUT    (0x00U) /* use Pn0 as output mode */
+#define _02_PMn1_NOT_USE        (0x02U) /* not use Pn1 as digital I/O */
+#define _02_PMn1_MODE_INPUT     (0x02U) /* use Pn1 as input mode */
+#define _00_PMn1_MODE_OUTPUT    (0x00U) /* use Pn1 as output mode */
+#define _04_PMn2_NOT_USE        (0x04U) /* not use Pn2 as digital I/O */
+#define _04_PMn2_MODE_INPUT     (0x04U) /* use Pn2 as input mode */
+#define _00_PMn2_MODE_OUTPUT    (0x00U) /* use Pn2 as output mode */
+#define _08_PMn3_NOT_USE        (0x08U) /* not use Pn3 as digital I/O */
+#define _08_PMn3_MODE_INPUT     (0x08U) /* use Pn3 as input mode */
+#define _00_PMn3_MODE_OUTPUT    (0x00U) /* use Pn3 as output mode */
+#define _10_PMn4_NOT_USE        (0x10U) /* not use Pn4 as digital I/O */
+#define _10_PMn4_MODE_INPUT     (0x10U) /* use Pn4 as input mode */
+#define _00_PMn4_MODE_OUTPUT    (0x00U) /* use Pn4 as output mode */
+#define _20_PMn5_NOT_USE        (0x20U) /* not use Pn5 as digital I/O */
+#define _20_PMn5_MODE_INPUT     (0x20U) /* use Pn5 as input mode */
+#define _00_PMn5_MODE_OUTPUT    (0x00U) /* use Pn5 as output mode */
+#define _40_PMn6_NOT_USE        (0x40U) /* not use Pn6 as digital I/O */
+#define _40_PMn6_MODE_INPUT     (0x40U) /* use Pn6 as input mode */
+#define _00_PMn6_MODE_OUTPUT    (0x00U) /* use Pn6 as output mode */
+#define _80_PMn7_NOT_USE        (0x80U) /* not use Pn7 as digital I/O */
+#define _80_PMn7_MODE_INPUT     (0x80U) /* use Pn7 as input mode */
+#define _00_PMn7_MODE_OUTPUT    (0x00U) /* use Pn7 as output mode */
+
+/*
+    Port Register (Pm)
+*/
+/* Pmn pin data (Pm0 to Pm7) */
+#define _00_Pn0_OUTPUT_0        (0x00U) /* Pn0 output 0 */
+#define _01_Pn0_OUTPUT_1        (0x01U) /* Pn0 output 1 */
+#define _00_Pn1_OUTPUT_0        (0x00U) /* Pn1 output 0 */
+#define _02_Pn1_OUTPUT_1        (0x02U) /* Pn1 output 1 */
+#define _00_Pn2_OUTPUT_0        (0x00U) /* Pn2 output 0 */
+#define _04_Pn2_OUTPUT_1        (0x04U) /* Pn2 output 1 */
+#define _00_Pn3_OUTPUT_0        (0x00U) /* Pn3 output 0 */
+#define _08_Pn3_OUTPUT_1        (0x08U) /* Pn3 output 1 */
+#define _00_Pn4_OUTPUT_0        (0x00U) /* Pn4 output 0 */
+#define _10_Pn4_OUTPUT_1        (0x10U) /* Pn4 output 1 */
+#define _00_Pn5_OUTPUT_0        (0x00U) /* Pn5 output 0 */
+#define _20_Pn5_OUTPUT_1        (0x20U) /* Pn5 output 1 */
+#define _00_Pn6_OUTPUT_0        (0x00U) /* Pn6 output 0 */
+#define _40_Pn6_OUTPUT_1        (0x40U) /* Pn6 output 1 */
+#define _00_Pn7_OUTPUT_0        (0x00U) /* Pn7 output 0 */
+#define _80_Pn7_OUTPUT_1        (0x80U) /* Pn7 output 1 */
+
+/*
+    Pull-up Resistor Option Register (PUm)
+*/
+/* Pmn pin on-chip pull-up resistor selection (PUmn) */
+#define _00_PUn0_PULLUP_OFF     (0x00U) /* Pn0 pull-up resistor not connected */
+#define _01_PUn0_PULLUP_ON      (0x01U) /* Pn0 pull-up resistor connected */
+#define _00_PUn1_PULLUP_OFF     (0x00U) /* Pn1 pull-up resistor not connected */
+#define _02_PUn1_PULLUP_ON      (0x02U) /* Pn1 pull-up resistor connected */
+#define _00_PUn2_PULLUP_OFF     (0x00U) /* Pn2 Pull-up resistor not connected */
+#define _04_PUn2_PULLUP_ON      (0x04U) /* Pn2 pull-up resistor connected */
+#define _00_PUn3_PULLUP_OFF     (0x00U) /* Pn3 pull-up resistor not connected */
+#define _08_PUn3_PULLUP_ON      (0x08U) /* Pn3 pull-up resistor connected */
+#define _00_PUn4_PULLUP_OFF     (0x00U) /* Pn4 pull-up resistor not connected */
+#define _10_PUn4_PULLUP_ON      (0x10U) /* Pn4 pull-up resistor connected */
+#define _00_PUn5_PULLUP_OFF     (0x00U) /* Pn5 pull-up resistor not connected */
+#define _20_PUn5_PULLUP_ON      (0x20U) /* Pn5 pull-up resistor connected */
+#define _00_PUn6_PULLUP_OFF     (0x00U) /* Pn6 pull-up resistor not connected */
+#define _40_PUn6_PULLUP_ON      (0x40U) /* Pn6 pull-up resistor connected */
+#define _00_PUn7_PULLUP_OFF     (0x00U) /* Pn7 pull-up resistor not connected */
+#define _80_PUn7_PULLUP_ON      (0x80U) /* Pn7 pull-up resistor connected */
+
+/*
+    Port Input Mode Register (PIMm)
+*/
+/* Pmn pin input buffer selection (PIMmn) */
+#define _00_PIMn0_TTL_OFF       (0x00U) /* set Pn0 normal input buffer */
+#define _01_PIMn0_TTL_ON        (0x01U) /* set Pn0 TTL input buffer */
+#define _00_PIMn1_TTL_OFF       (0x00U) /* set Pn1 normal input buffer */
+#define _02_PIMn1_TTL_ON        (0x02U) /* set Pn1 TTL input buffer */
+#define _00_PIMn2_TTL_OFF       (0x00U) /* set Pn2 normal input buffer */
+#define _04_PIMn2_TTL_ON        (0x04U) /* set Pn2 TTL input buffer */
+#define _00_PIMn3_TTL_OFF       (0x00U) /* set Pn3 normal input buffer */
+#define _08_PIMn3_TTL_ON        (0x08U) /* set Pn3 TTL input buffer */
+#define _00_PIMn4_TTL_OFF       (0x00U) /* set Pn4 normal input buffer */
+#define _10_PIMn4_TTL_ON        (0x10U) /* set Pn4 TTL input buffer */
+#define _00_PIMn5_TTL_OFF       (0x00U) /* set Pn5 normal input buffer */
+#define _20_PIMn5_TTL_ON        (0x20U) /* set Pn5 TTL input buffer */
+#define _00_PIMn6_TTL_OFF       (0x00U) /* set Pn6 normal input buffer */
+#define _40_PIMn6_TTL_ON        (0x40U) /* set Pn6 TTL input buffer */
+#define _00_PIMn7_TTL_OFF       (0x00U) /* set Pn7 normal input buffer */
+#define _80_PIMn7_TTL_ON        (0x80U) /* set Pn7 TTL input buffer */
+
+/*
+    Port Output Mode Register (POMm)
+*/
+/* Pmn pin output mode selection (POMmn) */
+#define _00_POMn0_NCH_OFF       (0x00U) /* set Pn0 output normal mode */
+#define _01_POMn0_NCH_ON        (0x01U) /* set Pn0 output N-ch open-drain mode */
+#define _00_POMn1_NCH_OFF       (0x00U) /* set Pn1 output normal mode */
+#define _02_POMn1_NCH_ON        (0x02U) /* set Pn1 output N-ch open-drain mode */
+#define _00_POMn2_NCH_OFF       (0x00U) /* set Pn2 output normal mode */
+#define _04_POMn2_NCH_ON        (0x04U) /* set Pn2 output N-ch open-drain mode */
+#define _00_POMn3_NCH_OFF       (0x00U) /* set Pn3 output normal mode */
+#define _08_POMn3_NCH_ON        (0x08U) /* set Pn3 output N-ch open-drain mode */
+#define _00_POMn4_NCH_OFF       (0x00U) /* set Pn4 output normal mode */
+#define _10_POMn4_NCH_ON        (0x10U) /* set Pn4 output N-ch open-drain mode */
+#define _00_POMn5_NCH_OFF       (0x00U) /* set Pn5 output normal mode */
+#define _20_POMn5_NCH_ON        (0x20U) /* set Pn5 output N-ch open-drain mode */
+#define _00_POMn6_NCH_OFF       (0x00U) /* set Pn6 output normal mode */
+#define _40_POMn6_NCH_ON        (0x40U) /* set Pn6 output N-ch open-drain mode */
+#define _00_POMn7_NCH_OFF       (0x00U) /* set Pn7 output normal mode */
+#define _80_POMn7_NCH_ON        (0x80U) /* set Pn7 output N-ch open-drain mode */
+
+/*
+    Port Operation Mode Register (PMCm)
+*/
+/* Pmn pin digital input buffer selection (PMCmn) */
+#define _01_PMCn0_NOT_USE       (0x01U) /* not use Pn0 digital input */
+#define _00_PMCn0_DI_ON         (0x00U) /* enable Pn0 digital input */
+#define _02_PMCn1_NOT_USE       (0x02U) /* not use Pn1 digital input */
+#define _00_PMCn1_DI_ON         (0x00U) /* enable Pn1 digital input */
+#define _04_PMCn2_NOT_USE       (0x04U) /* not use Pn2 digital input */
+#define _00_PMCn2_DI_ON         (0x00U) /* enable Pn2 digital input */
+#define _08_PMCn3_NOT_USE       (0x08U) /* not use Pn3 digital input */
+#define _00_PMCn3_DI_ON         (0x00U) /* enable Pn3 digital input */
+#define _10_PMCn4_NOT_USE       (0x10U) /* not use Pn4 digital input */
+#define _00_PMCn4_DI_ON         (0x00U) /* enable Pn4 digital input */
+#define _20_PMCn5_NOT_USE       (0x20U) /* not use Pn5 digital input */
+#define _00_PMCn5_DI_ON         (0x00U) /* enable Pn5 digital input */
+#define _40_PMCn6_NOT_USE       (0x40U) /* not use Pn6 digital input */
+#define _00_PMCn6_DI_ON         (0x00U) /* enable Pn6 digital input */
+#define _80_PMCn7_NOT_USE       (0x80U) /* not use Pn7 digital input */
+#define _00_PMCn7_DI_ON         (0x00U) /* enable Pn7 digital input */
+
+/*
+    AD port configuration register (ADPC)
+*/
+/* Analog input/digital input switching (ADPC3 - ADPC0) */
+#define _00_ADPC_DI_OFF         (0x00U) /* use P20 - P23 as analog input */
+#define _04_ADPC_DI_ON          (0x04U) /* use P23 as digital input */
+#define _03_ADPC_DI_ON          (0x03U) /* use P22 - P23 as digital input */
+#define _02_ADPC_DI_ON          (0x02U) /* use P21 - P23 as digital input */
+#define _01_ADPC_DI_ON          (0x01U) /* use P20 - P23 as digital input */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define _E0_PM1_DEFAULT         (0xE0U) /* PM1 default value */
+#define _F0_PM2_DEFAULT         (0xF0U) /* PM2 default value */
+#define _F8_PM4_DEFAULT         (0xF8U) /* PM4 default value */
+#define _FC_PM6_DEFAULT         (0xFCU) /* PM6 default value */
+#define _E0_PMC1_DEFAULT        (0xE0U) /* PMC1 default value */
+#define _F9_PMC4_DEFAULT        (0xF9U) /* PMC4 default value */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_PORT_Create(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_port_user.c b/r_cg_port_user.c
new file mode 100644
index 0000000..61653e1
--- /dev/null
+++ b/r_cg_port_user.c
@@ -0,0 +1,51 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_serial.c b/r_cg_serial.c
new file mode 100644
index 0000000..5a2845b
--- /dev/null
+++ b/r_cg_serial.c
@@ -0,0 +1,210 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+volatile uint8_t * gp_uart0_tx_address;        /* uart0 transmit buffer address */
+volatile uint16_t  g_uart0_tx_count;           /* uart0 transmit data number */
+volatile uint8_t * gp_uart0_rx_address;        /* uart0 receive buffer address */
+volatile uint16_t  g_uart0_rx_count;           /* uart0 receive data number */
+volatile uint16_t  g_uart0_rx_length;          /* uart0 receive data length */
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_SAU0_Create
+* Description  : This function initializes the SAU0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_SAU0_Create(void)
+{
+    SAU0EN = 1U;    /* supply SAU0 clock */
+    NOP();
+    NOP();
+    NOP();
+    NOP();
+    SPS0 = _0004_SAU_CK00_FCLK_4 | _0040_SAU_CK01_FCLK_4;
+    R_UART0_Create();
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Create
+* Description  : This function initializes the UART0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Create(void)
+{
+    ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART0 receive and transmit */
+    STMK0 = 1U;    /* disable INTST0 interrupt */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRMK0 = 1U;    /* disable INTSR0 interrupt */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+    SREMK0 = 1U;   /* disable INTSRE0 interrupt */
+    SREIF0 = 0U;   /* clear INTSRE0 interrupt flag */
+    /* Set INTST0 low priority */
+    STPR10 = 1U;
+    STPR00 = 1U;
+    /* Set INTSR0 low priority */
+    SRPR10 = 1U;
+    SRPR00 = 1U;
+    SMR00 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0000_SAU_TRIGGER_SOFTWARE |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR00 = _8000_SAU_TRANSMISSION | _0000_SAU_INTSRE_MASK | _0300_SAU_PARITY_ODD | _0080_SAU_LSB | _0020_SAU_STOP_2 |
+            _0007_SAU_LENGTH_8;
+    SDR00 = _9A00_UART0_TRANSMIT_DIVISOR;
+    NFEN0 |= _01_SAU_RXD0_FILTER_ON;
+    SIR01 = _0004_SAU_SIRMN_FECTMN | _0002_SAU_SIRMN_PECTMN | _0001_SAU_SIRMN_OVCTMN;    /* clear error flag */
+    SMR01 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0100_SAU_TRIGGER_RXD | _0000_SAU_EDGE_FALL |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR01 = _4000_SAU_RECEPTION | _0000_SAU_INTSRE_MASK | _0300_SAU_PARITY_ODD | _0080_SAU_LSB | _0010_SAU_STOP_1 |
+            _0007_SAU_LENGTH_8;
+    SDR01 = _9A00_UART0_RECEIVE_DIVISOR;
+    SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1;
+    SOL0 |= _0000_SAU_CHANNEL0_NORMAL;    /* output level normal */
+    SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART0 output */
+    /* Set RxD0 pin */
+    PM6 |= 0x02U;
+    /* Set TxD0 pin */
+    P6 |= 0x01U;
+    PM6 &= 0xFEU;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Start
+* Description  : This function starts the UART0 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Start(void)
+{
+    SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1;    /* output level normal */
+    SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART0 output */
+    SS0 |= _0002_SAU_CH1_START_TRG_ON | _0001_SAU_CH0_START_TRG_ON;    /* enable UART0 receive and transmit */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+    STMK0 = 0U;    /* enable INTST0 interrupt */
+    SRMK0 = 0U;    /* enable INTSR0 interrupt */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Stop
+* Description  : This function stops the UART0 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Stop(void)
+{
+    STMK0 = 1U;    /* disable INTST0 interrupt */
+    SRMK0 = 1U;    /* disable INTSR0 interrupt */
+    ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART0 receive and transmit */
+    SOE0 &= ~_0001_SAU_CH0_OUTPUT_ENABLE;    /* disable UART0 output */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+   
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Receive
+* Description  : This function receives UART0 data.
+* Arguments    : rx_buf -
+*                    receive buffer pointer
+*                rx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (rx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        g_uart0_rx_count = 0U;
+        g_uart0_rx_length = rx_num;
+        gp_uart0_rx_address = rx_buf;
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Send
+* Description  : This function sends UART0 data.
+* Arguments    : tx_buf -
+*                    transfer buffer pointer
+*                tx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (tx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        gp_uart0_tx_address = tx_buf;
+        g_uart0_tx_count = tx_num;
+        STMK0 = 1U;    /* disable INTST0 interrupt */
+        TXD0 = *gp_uart0_tx_address;
+        gp_uart0_tx_address++;
+        g_uart0_tx_count--;
+        STMK0 = 0U;    /* enable INTST0 interrupt */
+    }
+
+    return (status);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_serial.h b/r_cg_serial.h
new file mode 100644
index 0000000..69ed97d
--- /dev/null
+++ b/r_cg_serial.h
@@ -0,0 +1,399 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef SERIAL_H
+#define SERIAL_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Serial Clock Select Register m (SPSm)
+*/
+/* Section of operation clock (CKm0) (PRSm03 - PRSm00) */
+#define _0000_SAU_CK00_FCLK_0            (0x0000U)    /* ck00 - fCLK */
+#define _0001_SAU_CK00_FCLK_1            (0x0001U)    /* ck00 - fCLK/2^1 */
+#define _0002_SAU_CK00_FCLK_2            (0x0002U)    /* ck00 - fCLK/2^2 */
+#define _0003_SAU_CK00_FCLK_3            (0x0003U)    /* ck00 - fCLK/2^3 */
+#define _0004_SAU_CK00_FCLK_4            (0x0004U)    /* ck00 - fCLK/2^4 */
+#define _0005_SAU_CK00_FCLK_5            (0x0005U)    /* ck00 - fCLK/2^5 */
+#define _0006_SAU_CK00_FCLK_6            (0x0006U)    /* ck00 - fCLK/2^6 */
+#define _0007_SAU_CK00_FCLK_7            (0x0007U)    /* ck00 - fCLK/2^7 */
+#define _0008_SAU_CK00_FCLK_8            (0x0008U)    /* ck00 - fCLK/2^8 */
+#define _0009_SAU_CK00_FCLK_9            (0x0009U)    /* ck00 - fCLK/2^9 */
+#define _000A_SAU_CK00_FCLK_10           (0x000AU)    /* ck00 - fCLK/2^10 */
+#define _000B_SAU_CK00_FCLK_11           (0x000BU)    /* ck00 - fCLK/2^11 */
+#define _000C_SAU_CK00_FCLK_12           (0x000CU)    /* ck00 - fCLK/2^12 */
+#define _000D_SAU_CK00_FCLK_13           (0x000DU)    /* ck00 - fCLK/2^13 */
+#define _000E_SAU_CK00_FCLK_14           (0x000EU)    /* ck00 - fCLK/2^14 */
+#define _000F_SAU_CK00_FCLK_15           (0x000FU)    /* ck00 - fCLK/2^15 */
+/* Section of operation clock (CKm1) (PRSm13 - PRSm10) */
+#define _0000_SAU_CK01_FCLK_0            (0x0000U)    /* ck01 - fCLK */
+#define _0010_SAU_CK01_FCLK_1            (0x0010U)    /* ck01 - fCLK/2^1 */
+#define _0020_SAU_CK01_FCLK_2            (0x0020U)    /* ck01 - fCLK/2^2 */
+#define _0030_SAU_CK01_FCLK_3            (0x0030U)    /* ck01 - fCLK/2^3 */
+#define _0040_SAU_CK01_FCLK_4            (0x0040U)    /* ck01 - fCLK/2^4 */
+#define _0050_SAU_CK01_FCLK_5            (0x0050U)    /* ck01 - fCLK/2^5 */
+#define _0060_SAU_CK01_FCLK_6            (0x0060U)    /* ck01 - fCLK/2^6 */
+#define _0070_SAU_CK01_FCLK_7            (0x0070U)    /* ck01 - fCLK/2^7 */
+#define _0080_SAU_CK01_FCLK_8            (0x0080U)    /* ck01 - fCLK/2^8 */
+#define _0090_SAU_CK01_FCLK_9            (0x0090U)    /* ck01 - fCLK/2^9 */
+#define _00A0_SAU_CK01_FCLK_10           (0x00A0U)    /* ck01 - fCLK/2^10 */
+#define _00B0_SAU_CK01_FCLK_11           (0x00B0U)    /* ck01 - fCLK/2^11 */
+#define _00C0_SAU_CK01_FCLK_12           (0x00C0U)    /* ck01 - fCLK/2^12 */
+#define _00D0_SAU_CK01_FCLK_13           (0x00D0U)    /* ck01 - fCLK/2^13 */
+#define _00E0_SAU_CK01_FCLK_14           (0x00E0U)    /* ck01 - fCLK/2^14 */
+#define _00F0_SAU_CK01_FCLK_15           (0x00F0U)    /* ck01 - fCLK/2^15 */
+
+/*
+    Serial Mode Register mn (SMRmn)
+*/
+#define _0020_SAU_SMRMN_INITIALVALUE     (0x0020U)
+/* Selection of macro clock (MCK) of channel n (CKSmn) */
+#define _0000_SAU_CLOCK_SELECT_CK00      (0x0000U)    /* operation clock CK0 set by PRS register */ 
+#define _8000_SAU_CLOCK_SELECT_CK01      (0x8000U)    /* operation clock CK1 set by PRS register */
+/* Selection of transfer clock (TCLK) of channel n (CCSmn) */
+#define _0000_SAU_CLOCK_MODE_CKS         (0x0000U)    /* divided operation clock MCK specified by CKSmn bit */  
+#define _4000_SAU_CLOCK_MODE_TI0N        (0x4000U)    /* clock input from SCK pin (slave transfer in CSI mode) */
+/* Selection of start trigger source (STSmn) */
+#define _0000_SAU_TRIGGER_SOFTWARE       (0x0000U)    /* only software trigger is valid */
+#define _0100_SAU_TRIGGER_RXD            (0x0100U)    /* valid edge of RXD pin */
+/* Controls inversion of level of receive data of channel n in UART mode (SISmn0) */
+#define _0000_SAU_EDGE_FALL              (0x0000U)    /* falling edge is detected as the start bit */
+#define _0040_SAU_EDGE_RISING            (0x0040U)    /* rising edge is detected as the start bit */
+/* Setting of operation mode of channel n (MDmn2, MDmn1) */
+#define _0000_SAU_MODE_CSI               (0x0000U)    /* CSI mode */
+#define _0002_SAU_MODE_UART              (0x0002U)    /* UART mode */
+#define _0004_SAU_MODE_IIC               (0x0004U)    /* simplified IIC mode */
+/* Selection of interrupt source of channel n (MDmn0) */
+#define _0000_SAU_TRANSFER_END           (0x0000U)    /* transfer end interrupt */
+#define _0001_SAU_BUFFER_EMPTY           (0x0001U)    /* buffer empty interrupt */
+
+/*
+    Serial Communication Operation Setting Register mn (SCRmn)
+*/
+/* Setting of operation mode of channel n (TXEmn, RXEmn) */
+#define _0000_SAU_NOT_COMMUNICATION      (0x0000U)    /* does not start communication */
+#define _4000_SAU_RECEPTION              (0x4000U)    /* reception only */
+#define _8000_SAU_TRANSMISSION           (0x8000U)    /* transmission only */
+#define _C000_SAU_RECEPTION_TRANSMISSION (0xC000U)    /* reception and transmission */
+/* Selection of data and clock phase in CSI mode (DAPmn, CKPmn) */
+#define _0000_SAU_TIMING_1               (0x0000U)    /* type 1 */
+#define _1000_SAU_TIMING_2               (0x1000U)    /* type 2 */
+#define _2000_SAU_TIMING_3               (0x2000U)    /* type 3 */
+#define _3000_SAU_TIMING_4               (0x3000U)    /* type 4 */
+/* Selection of masking of error interrupt signal (EOCmn) */
+#define _0000_SAU_INTSRE_MASK            (0x0000U)    /* masks error interrupt INTSREx */
+#define _0400_SAU_INTSRE_ENABLE          (0x0400U)    /* enables generation of error interrupt INTSREx */
+/* Setting of parity bit in UART mode (PTCmn1 - PTCmn0) */
+#define _0000_SAU_PARITY_NONE            (0x0000U)    /* none parity */
+#define _0100_SAU_PARITY_ZERO            (0x0100U)    /* zero parity */
+#define _0200_SAU_PARITY_EVEN            (0x0200U)    /* even parity */
+#define _0300_SAU_PARITY_ODD             (0x0300U)    /* odd parity */
+/* Selection of data transfer sequence in CSI and UART modes (DIRmn) */
+#define _0000_SAU_MSB                    (0x0000U)    /* MSB */
+#define _0080_SAU_LSB                    (0x0080U)    /* LSB */
+/* Setting of stop bit in UART mode (SLCmn1, SLCmn0) */
+#define _0000_SAU_STOP_NONE              (0x0000U)    /* none stop bit */
+#define _0010_SAU_STOP_1                 (0x0010U)    /* 1 stop bit */
+#define _0020_SAU_STOP_2                 (0x0020U)    /* 2 stop bits */
+/* Setting of data length in CSI and UART modes (DLSmn2 - DLSmn0) */
+#define _0005_SAU_LENGTH_9               (0x0005U)    /* 9-bit data length */
+#define _0006_SAU_LENGTH_7               (0x0006U)    /* 7-bit data length */
+#define _0007_SAU_LENGTH_8               (0x0007U)    /* 8-bit data length */
+
+/*
+    Serial Output Level Register m (SOLm)
+*/
+/* Selects inversion of the level of the transmit data of channel n in UART mode */
+#define _0000_SAU_CHANNEL0_NORMAL        (0x0000U)    /* normal bit level */
+#define _0001_SAU_CHANNEL0_INVERTED      (0x0001U)    /* inverted bit level */
+#define _0000_SAU_CHANNEL1_NORMAL        (0x0000U)    /* normal bit level */
+#define _0002_SAU_CHANNEL1_INVERTED      (0x0002U)    /* inverted bit level */
+#define _0000_SAU_CHANNEL2_NORMAL        (0x0000U)    /* normal bit level */
+#define _0004_SAU_CHANNEL2_INVERTED      (0x0004U)    /* inverted bit level */
+#define _0000_SAU_CHANNEL3_NORMAL        (0x0000U)    /* normal bit level */
+#define _0008_SAU_CHANNEL3_INVERTED      (0x0008U)    /* inverted bit level */
+
+/*
+    Noise Filter Enable Register 0 (NFEN0)
+*/
+/* Use of noise filter */
+#define _00_SAU_RXD3_FILTER_OFF          (0x00U)      /* noise filter off */
+#define _40_SAU_RXD3_FILTER_ON           (0x40U)      /* noise filter on */
+#define _00_SAU_RXD2_FILTER_OFF          (0x00U)      /* noise filter off */
+#define _10_SAU_RXD2_FILTER_ON           (0x10U)      /* noise filter on */
+#define _00_SAU_RXD1_FILTER_OFF          (0x00U)      /* noise filter off */
+#define _04_SAU_RXD1_FILTER_ON           (0x04U)      /* noise filter on */
+#define _00_SAU_RXD0_FILTER_OFF          (0x00U)      /* noise filter off */
+#define _01_SAU_RXD0_FILTER_ON           (0x01U)      /* noise filter on */
+
+/*
+    Format of Serial Status Register mn (SSRmn)
+*/
+/* Communication status indication flag of channel n (TSFmn) */
+#define _0040_SAU_UNDER_EXECUTE          (0x0040U)    /* communication is under execution */
+/* Buffer register status indication flag of channel n (BFFmn) */
+#define _0020_SAU_VALID_STORED           (0x0020U)    /* valid data is stored in the SDRmn register */
+/* Framing error detection flag of channel n (FEFmn) */
+#define _0004_SAU_FRAM_ERROR             (0x0004U)    /* a framing error occurs during UART reception */
+/* Parity error detection flag of channel n (PEFmn) */
+#define _0002_SAU_PARITY_ERROR           (0x0002U)    /* a parity error occurs or ACK is not detected */
+/* Overrun error detection flag of channel n (OVFmn) */
+#define _0001_SAU_OVERRUN_ERROR          (0x0001U)    /* an overrun error occurs */
+
+/*
+    Serial Channel Start Register m (SSm)
+*/
+/* Operation start trigger of channel 0 (SSm0) */
+#define _0000_SAU_CH0_START_TRG_OFF      (0x0000U)    /* no trigger operation */
+#define _0001_SAU_CH0_START_TRG_ON       (0x0001U)    /* sets SEm0 to 1 and enters the communication wait status */
+/* Operation start trigger of channel 1 (SSm1) */
+#define _0000_SAU_CH1_START_TRG_OFF      (0x0000U)    /* no trigger operation */
+#define _0002_SAU_CH1_START_TRG_ON       (0x0002U)    /* sets SEm1 to 1 and enters the communication wait status */
+/* Operation start trigger of channel 2 (SSm2) */
+#define _0000_SAU_CH2_START_TRG_OFF      (0x0000U)    /* no trigger operation */
+#define _0004_SAU_CH2_START_TRG_ON       (0x0004U)    /* sets SEm2 to 1 and enters the communication wait status */
+/* Operation start trigger of channel 3 (SSm3) */
+#define _0000_SAU_CH3_START_TRG_OFF      (0x0000U)    /* no trigger operation */
+#define _0008_SAU_CH3_START_TRG_ON       (0x0008U)    /* sets SEm3 to 1 and enters the communication wait status */
+
+/*
+    Serial Channel Stop Register m (STm)
+*/
+/* Operation stop trigger of channel 0 (STm0) */
+#define _0000_SAU_CH0_STOP_TRG_OFF       (0x0000U)    /* no trigger operation */
+#define _0001_SAU_CH0_STOP_TRG_ON        (0x0001U)    /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 1 (STm1) */
+#define _0000_SAU_CH1_STOP_TRG_OFF       (0x0000U)    /* no trigger operation */
+#define _0002_SAU_CH1_STOP_TRG_ON        (0x0002U)    /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 2 (STm2) */
+#define _0000_SAU_CH2_STOP_TRG_OFF       (0x0000U)    /* no trigger operation */
+#define _0004_SAU_CH2_STOP_TRG_ON        (0x0004U)    /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 3 (STm3) */
+#define _0000_SAU_CH3_STOP_TRG_OFF       (0x0000U)    /* no trigger operation */
+#define _0008_SAU_CH3_STOP_TRG_ON        (0x0008U)    /* operation is stopped (stop trigger is generated) */
+
+/*
+    Format of Serial Flag Clear Trigger Register mn (SIRmn)
+*/
+/* Clear trigger of overrun error flag of channel n (OVCTmn) */
+#define _0001_SAU_SIRMN_OVCTMN           (0x0001U)
+/* Clear trigger of parity error flag of channel n (PECTmn) */
+#define _0002_SAU_SIRMN_PECTMN           (0x0002U)
+/* Clear trigger of framing error of channel n (FECTMN) */
+#define _0004_SAU_SIRMN_FECTMN           (0x0004U)
+
+/*
+    Serial Output Enable Register m (SOEm)
+*/
+/* Serial output enable/disable of channel 0 (SOEm0) */
+#define _0001_SAU_CH0_OUTPUT_ENABLE      (0x0001U)    /* enables output by serial communication operation */
+#define _0000_SAU_CH0_OUTPUT_DISABLE     (0x0000U)    /* stops output by serial communication operation */
+/* Serial output enable/disable of channel 1 (SOEm1) */
+#define _0002_SAU_CH1_OUTPUT_ENABLE      (0x0002U)    /* enables output by serial communication operation */
+#define _0000_SAU_CH1_OUTPUT_DISABLE     (0x0000U)    /* stops output by serial communication operation */
+/* Serial output enable/disable of channel 2 (SOEm2) */
+#define _0004_SAU_CH2_OUTPUT_ENABLE      (0x0004U)    /* enables output by serial communication operation */
+#define _0000_SAU_CH2_OUTPUT_DISABLE     (0x0000U)    /* stops output by serial communication operation */
+/* Serial output enable/disable of channel 3 (SOEm3) */
+#define _0008_SAU_CH3_OUTPUT_ENABLE      (0x0008U)    /* enables output by serial communication operation */
+#define _0000_SAU_CH3_OUTPUT_DISABLE     (0x0000U)    /* stops output by serial communication operation */
+
+/*
+    Serial Output Register m (SOm)
+*/
+/* Serial data output of channel 0 (SOm0) */
+#define _0000_SAU_CH0_DATA_OUTPUT_0      (0x0000U)    /* Serial data output value is "0" */
+#define _0001_SAU_CH0_DATA_OUTPUT_1      (0x0001U)    /* Serial data output value is "1" */
+/* Serial data output of channel 1 (SOm1) */
+#define _0000_SAU_CH1_DATA_OUTPUT_0      (0x0000U)    /* Serial data output value is "0" */
+#define _0002_SAU_CH1_DATA_OUTPUT_1      (0x0002U)    /* Serial data output value is "1" */
+/* Serial data output of channel 2 (SOm2) */
+#define _0000_SAU_CH2_DATA_OUTPUT_0      (0x0000U)    /* Serial data output value is "0" */
+#define _0004_SAU_CH2_DATA_OUTPUT_1      (0x0004U)    /* Serial data output value is "1" */
+/* Serial data output of channel 3 (SOm3) */
+#define _0000_SAU_CH3_DATA_OUTPUT_0      (0x0000U)    /* Serial data output value is "0" */
+#define _0008_SAU_CH3_DATA_OUTPUT_1      (0x0008U)    /* Serial data output value is "1" */
+/* Serial clock output of channel 0 (CKOm0) */
+#define _0000_SAU_CH0_CLOCK_OUTPUT_0     (0x0000U)    /* Serial clock output value is "0" */
+#define _0100_SAU_CH0_CLOCK_OUTPUT_1     (0x0100U)    /* Serial clock output value is "1" */
+/* Serial clock output of channel 1 (CKOm1) */
+#define _0000_SAU_CH1_CLOCK_OUTPUT_0     (0x0000U)    /* Serial clock output value is "0" */
+#define _0200_SAU_CH1_CLOCK_OUTPUT_1     (0x0200U)    /* Serial clock output value is "1" */
+/* Serial clock output of channel 2 (CKOm2) */
+#define _0000_SAU_CH2_CLOCK_OUTPUT_0     (0x0000U)    /* Serial clock output value is "0" */
+#define _0400_SAU_CH2_CLOCK_OUTPUT_1     (0x0400U)    /* Serial clock output value is "1" */
+/* Serial clock output of channel 3 (CKOm3) */
+#define _0000_SAU_CH3_CLOCK_OUTPUT_0     (0x0000U)    /* Serial clock output value is "0" */
+#define _0800_SAU_CH3_CLOCK_OUTPUT_1     (0x0800U)    /* Serial clock output value is "1" */
+
+/*
+    SAU Standby Control Register m (SSCm)
+*/
+/* SAU Standby Wakeup Control Bit (SWC) */
+#define _0000_SAU_CH0_SNOOZE_OFF         (0x0000U)    /* disable start function from STOP state of chip */
+#define _0001_SAU_CH0_SNOOZE_ON          (0x0001U)    /* enable start function from STOP state of chip */
+
+/* SAU used flag */
+#define _00_SAU_IIC_MASTER_FLAG_CLEAR    (0x00U)
+#define _01_SAU_IIC_SEND_FLAG            (0x01U)
+#define _02_SAU_IIC_RECEIVE_FLAG         (0x02U)
+#define _04_SAU_IIC_SENDED_ADDRESS_FLAG  (0x04U)
+
+/*
+    Input switch control register (ISC)
+*/
+/* Channel 0 SSI00 input setting in CSI communication and slave mode (SSIE00) */
+#define _00_SAU_SSI00_UNUSED             (0x00U)      /* disables SSI00 pin input */
+#define _80_SAU_SSI00_USED               (0x80U)      /* enables SSI00 pin input */
+
+/*
+    IICA Control Register (IICCTLn0)
+*/
+/* IIC operation enable (IICEn) */
+#define _00_IICA_OPERATION_DISABLE       (0x00U)    /* stop operation */
+#define _80_IICA_OPERATION_ENABLE        (0x80U)    /* enable operation */
+/* Exit from communications (LRELn) */
+#define _00_IICA_COMMUNICATION_NORMAL    (0x00U)    /* normal operation */
+#define _40_IICA_COMMUNICATION_EXIT      (0x40U)    /* exit from current communication */
+/* Wait cancellation (WRELn) */
+#define _00_IICA_WAIT_NOTCANCEL          (0x00U)    /* do not cancel wait */
+#define _20_IICA_WAIT_CANCEL             (0x20U)    /* cancel wait */
+/* Generation of interrupt when stop condition (SPIEn) */
+#define _00_IICA_STOPINT_DISABLE         (0x00U)    /* disable */
+#define _10_IICA_STOPINT_ENABLE          (0x10U)    /* enable */
+/* Wait and interrupt generation (WTIMn) */
+#define _00_IICA_WAITINT_CLK8FALLING     (0x00U)    /* generated at the eighth clock's falling edge */
+#define _08_IICA_WAITINT_CLK9FALLING     (0x08U)    /* generated at the ninth clock's falling edge */
+/* Acknowledgement control (ACKEn) */
+#define _00_IICA_ACK_DISABLE             (0x00U)    /* disable acknowledgement */
+#define _04_IICA_ACK_ENABLE              (0x04U)    /* enable acknowledgement */
+/* Start condition trigger (STTn) */
+#define _00_IICA_START_NOTGENERATE       (0x00U)    /* do not generate start condition */
+#define _02_IICA_START_GENERATE          (0x02U)    /* generate start condition */
+/* Stop condition trigger (SPTn) */
+#define _00_IICA_STOP_NOTGENERATE        (0x00U)    /* do not generate stop condition */
+#define _01_IICA_STOP_GENERATE           (0x01U)    /* generate stop condition */
+
+/*
+    IICA Status Register (IICSn)
+*/
+/* Master device status (MSTSn) */
+#define _00_IICA_STATUS_NOTMASTER        (0x00U)    /* slave device status or communication standby status */
+#define _80_IICA_STATUS_MASTER           (0x80U)    /* master device communication status */
+/* Detection of arbitration loss (ALDn) */
+#define _00_IICA_ARBITRATION_NO          (0x00U)    /* arbitration win or no arbitration */
+#define _40_IICA_ARBITRATION_LOSS        (0x40U)    /* arbitration loss */
+/* Detection of extension code reception (EXCn) */
+#define _00_IICA_EXTCODE_NOT             (0x00U)    /* extension code not received */
+#define _20_IICA_EXTCODE_RECEIVED        (0x20U)    /* extension code received */
+/* Detection of matching addresses (COIn) */
+#define _00_IICA_ADDRESS_NOTMATCH        (0x00U)    /* addresses do not match */
+#define _10_IICA_ADDRESS_MATCH           (0x10U)    /* addresses match */
+/* Detection of transmit/receive status (TRCn) */
+#define _00_IICA_STATUS_RECEIVE          (0x00U)    /* receive status */ 
+#define _08_IICA_STATUS_TRANSMIT         (0x08U)    /* transmit status */
+/* Detection of acknowledge signal (ACKDn) */
+#define _00_IICA_ACK_NOTDETECTED         (0x00U)    /* ACK signal was not detected */
+#define _04_IICA_ACK_DETECTED            (0x04U)    /* ACK signal was detected */
+/* Detection of start condition (STDn) */
+#define _00_IICA_START_NOTDETECTED       (0x00U)    /* start condition not detected */
+#define _02_IICA_START_DETECTED          (0x02U)    /* start condition detected */
+/* Detection of stop condition (SPDn) */
+#define _00_IICA_STOP_NOTDETECTED        (0x00U)    /* stop condition not detected */
+#define _01_IICA_STOP_DETECTED           (0x01U)    /* stop condition detected */
+
+/*
+    IICA Flag Register (IICFn)
+*/
+/* STT clear flag (STCFn) */
+#define _00_IICA_STARTFLAG_GENERATE      (0x00U)    /* generate start condition */
+#define _80_IICA_STARTFLAG_UNSUCCESSFUL  (0x80U)    /* start condition generation unsuccessful */
+/* IIC bus status flag (IICBSYn) */
+#define _00_IICA_BUS_RELEASE             (0x00U)    /* bus release status */
+#define _40_IICA_BUS_COMMUNICATION       (0x40U)    /* bus communication status */
+/* Initial start enable trigger (STCENn) */
+#define _00_IICA_START_WITHSTOP          (0x00U)    /* generate start condition upon detecting a stop condition */
+#define _02_IICA_START_WITHOUTSTOP       (0x02U)    /* generate start condition without detection of a stop condition */
+/* Communication reservation function disable bit (IICRSVn) */
+#define _00_IICA_RESERVATION_ENABLE      (0x00U)    /* enable communication reservation */
+#define _01_IICA_RESERVATION_DISABLE     (0x01U)    /* disable communication reservation */
+
+/*
+    IICA Control Register 1 (IICCTLn1)
+*/
+/* Control of address match wakeup (WUPn) */
+#define _00_IICA_WAKEUP_STOP             (0x00U)    /* stop address match wakeup function in STOP mode */
+#define _80_IICA_WAKEUP_ENABLE           (0x80U)    /* enable address match wakeup function in STOP mode */
+/* Detection of SCL0 pin level (CLDn) */
+#define _00_IICA_SCL_LOW                 (0x00U)    /* detect clock line at low level */
+#define _20_IICA_SCL_HIGH                (0x20U)    /* detect clock line at high level */
+/* Detection of SDA0 pin level (DADn) */
+#define _00_IICA_SDA_LOW                 (0x00U)    /* detect data line at low level */
+#define _10_IICA_SDA_HIGH                (0x10U)    /* detect data line at high level */
+/* Operation mode switching (SMCn) */
+#define _00_IICA_MODE_STANDARD           (0x00U)    /* operates in standard mode */
+#define _08_IICA_MODE_HIGHSPEED          (0x08U)    /* operates in high-speed mode */
+/* Digital filter operation control (DFCn) */
+#define _00_IICA_FILTER_OFF              (0x00U)    /* digital filter off */ 
+#define _04_IICA_FILTER_ON               (0x04U)    /* digital filter on */
+/* Operation of clock dividing frequency permission (PRSn) */
+#define _00_IICA_fCLK                    (0x00U)    /* clock of dividing frequency operation (fCLK) */ 
+#define _01_IICA_fCLK_HALF               (0x01U)    /* 2 clock of dividing frequency operation (fCLK/2) */
+/* IICA used flag */
+#define _80_IICA_ADDRESS_COMPLETE        (0x80U)
+#define _00_IICA_MASTER_FLAG_CLEAR       (0x00U)
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define _9A00_UART0_RECEIVE_DIVISOR      (0x9A00U)
+#define _9A00_UART0_TRANSMIT_DIVISOR     (0x9A00U)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_SAU0_Create(void);
+void R_UART0_Create(void);
+void R_UART0_Start(void);
+void R_UART0_Stop(void);
+MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num);
+MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num);
+static void r_uart0_callback_error(uint8_t err_type);
+static void r_uart0_callback_receiveend(void);
+static void r_uart0_callback_sendend(void);
+static void r_uart0_callback_softwareoverrun(uint16_t rx_data);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_serial_user.c b/r_cg_serial_user.c
new file mode 100644
index 0000000..03fb0a2
--- /dev/null
+++ b/r_cg_serial_user.c
@@ -0,0 +1,172 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+/* Start user code for include. Do not edit comment generated here */
+#include "appTask.h"
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+#pragma interrupt r_uart0_interrupt_send(vect=INTST0)
+#pragma interrupt r_uart0_interrupt_receive(vect=INTSR0)
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+extern volatile uint8_t * gp_uart0_tx_address;         /* uart0 send buffer address */
+extern volatile uint16_t  g_uart0_tx_count;            /* uart0 send data number */
+extern volatile uint8_t * gp_uart0_rx_address;         /* uart0 receive buffer address */
+extern volatile uint16_t  g_uart0_rx_count;            /* uart0 receive data number */
+extern volatile uint16_t  g_uart0_rx_length;           /* uart0 receive data length */
+/* Start user code for global. Do not edit comment generated here */
+extern uint8_t g_rx_buf[3];
+extern uint8_t uart_sendend;
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_interrupt_receive
+* Description  : This function is INTSR0 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart0_interrupt_receive(void)
+{
+    volatile uint8_t rx_data;
+    volatile uint8_t err_type;
+    
+    err_type = (uint8_t)(SSR01 & 0x0007U);
+    SIR01 = (uint16_t)err_type;
+
+    if (err_type != 0U)
+    {
+        r_uart0_callback_error(err_type);
+    }
+    
+    rx_data = RXD0;
+
+    if (g_uart0_rx_length > g_uart0_rx_count)
+    {
+        *gp_uart0_rx_address = rx_data;
+        gp_uart0_rx_address++;
+        g_uart0_rx_count++;
+
+        if (g_uart0_rx_length == g_uart0_rx_count)
+        {
+            r_uart0_callback_receiveend();
+        }
+    }
+    else
+    {
+        r_uart0_callback_softwareoverrun(rx_data);
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_interrupt_send
+* Description  : This function is INTST0 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart0_interrupt_send(void)
+{
+    if (g_uart0_tx_count > 0U)
+    {
+        TXD0 = *gp_uart0_tx_address;
+        gp_uart0_tx_address++;
+        g_uart0_tx_count--;
+    }
+    else
+    {
+        r_uart0_callback_sendend();
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_receiveend
+* Description  : This function is a callback function when UART0 finishes reception.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_receiveend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    UART_Rx_Pro(g_rx_buf[0]);
+    R_UART0_Receive(g_rx_buf,1);
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_softwareoverrun
+* Description  : This function is a callback function when UART0 receives an overflow data.
+* Arguments    : rx_data -
+*                    receive data
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_softwareoverrun(uint16_t rx_data)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_sendend
+* Description  : This function is a callback function when UART0 finishes transmission.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_sendend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    uart_sendend = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_error
+* Description  : This function is a callback function when UART0 reception error occurs.
+* Arguments    : err_type -
+*                    error type value
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_error(uint8_t err_type)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_timer.c b/r_cg_timer.c
new file mode 100644
index 0000000..218dbe9
--- /dev/null
+++ b/r_cg_timer.c
@@ -0,0 +1,120 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_timer.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for TAU module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_TAU0_Create
+* Description  : This function initializes the TAU0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_TAU0_Create(void)
+{
+    TAU0EN = 1U;    /* supplies input clock */
+    TPS0 = _0000_TAU_CKM0_FCLK_0 | _0000_TAU_CKM1_FCLK_0 | _0000_TAU_CKM2_FCLK_1 | _0000_TAU_CKM3_FCLK_8;
+    /* Stop all channels */
+    TT0 = _0001_TAU_CH0_STOP_TRG_ON | _0002_TAU_CH1_STOP_TRG_ON | _0004_TAU_CH2_STOP_TRG_ON |
+          _0008_TAU_CH3_STOP_TRG_ON | _0200_TAU_CH1_H8_STOP_TRG_ON | _0800_TAU_CH3_H8_STOP_TRG_ON;
+    /* Mask channel 0 interrupt */
+    TMMK00 = 1U;    /* disable INTTM00 interrupt */
+    TMIF00 = 0U;    /* clear INTTM00 interrupt flag */
+    /* Mask channel 1 interrupt */
+    TMMK01 = 1U;    /* disable INTTM01 interrupt */
+    TMIF01 = 0U;    /* clear INTTM01 interrupt flag */
+    /* Mask channel 1 higher 8 bits interrupt */
+    TMMK01H = 1U;    /* disable INTTM01H interrupt */
+    TMIF01H = 0U;    /* clear INTTM01H interrupt flag */
+    /* Mask channel 2 interrupt */
+    TMMK02 = 1U;    /* disable INTTM02 interrupt */
+    TMIF02 = 0U;    /* clear INTTM02 interrupt flag */
+    /* Mask channel 3 interrupt */
+    TMMK03 = 1U;    /* disable INTTM03 interrupt */
+    TMIF03 = 0U;    /* clear INTTM03 interrupt flag */
+    /* Mask channel 3 higher 8 bits interrupt */
+    TMMK03H = 1U;    /* disable INTTM03H interrupt */
+    TMIF03H = 0U;    /* clear INTTM03H interrupt flag */
+    /* Set INTTM00 low priority */
+    TMPR100 = 1U;
+    TMPR000 = 1U;
+    /* Channel 0 used as interval timer */
+    TMR00 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_COMBINATION_SLAVE |
+            _0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED;
+    TDR00 = _5DBF_TAU_TDR00_VALUE;
+    TO0 &= ~_0001_TAU_CH0_OUTPUT_VALUE_1;
+    TOE0 &= ~_0001_TAU_CH0_OUTPUT_ENABLE;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_TAU0_Channel0_Start
+* Description  : This function starts TAU0 channel 0 counter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_TAU0_Channel0_Start(void)
+{
+    TMIF00 = 0U;    /* clear INTTM00 interrupt flag */
+    TMMK00 = 0U;    /* enable INTTM00 interrupt */
+    TS0 |= _0001_TAU_CH0_START_TRG_ON;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_TAU0_Channel0_Stop
+* Description  : This function stops TAU0 channel 0 counter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_TAU0_Channel0_Stop(void)
+{
+    TT0 |= _0001_TAU_CH0_STOP_TRG_ON;
+    /* Mask channel 0 interrupt */
+    TMMK00 = 1U;    /* disable INTTM00 interrupt */
+    TMIF00 = 0U;    /* clear INTTM00 interrupt flag */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_timer.h b/r_cg_timer.h
new file mode 100644
index 0000000..aded12b
--- /dev/null
+++ b/r_cg_timer.h
@@ -0,0 +1,315 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_timer.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for TAU module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef TAU_H
+#define TAU_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Peripheral Enable Register 0 (PER0)
+*/
+/* Control of timer array unit 0 input clock (TAU0EN) */
+#define _00_TAU0_CLOCK_STOP                     (0x00U)   /* stops supply of input clock */
+#define _01_TAU0_CLOCK_SUPPLY                   (0x01U)   /* supplies input clock */
+
+/*
+    Timer Clock Select Register m (TPSm)
+*/
+/* Operating mode and clear mode selection (PRSm03 - PRSm00) */
+#define _0000_TAU_CKM0_FCLK_0                   (0x0000U) /* ckm0 - fCLK */
+#define _0001_TAU_CKM0_FCLK_1                   (0x0001U) /* ckm0 - fCLK/2^1 */
+#define _0002_TAU_CKM0_FCLK_2                   (0x0002U) /* ckm0 - fCLK/2^2 */
+#define _0003_TAU_CKM0_FCLK_3                   (0x0003U) /* ckm0 - fCLK/2^3 */
+#define _0004_TAU_CKM0_FCLK_4                   (0x0004U) /* ckm0 - fCLK/2^4 */
+#define _0005_TAU_CKM0_FCLK_5                   (0x0005U) /* ckm0 - fCLK/2^5 */
+#define _0006_TAU_CKM0_FCLK_6                   (0x0006U) /* ckm0 - fCLK/2^6 */
+#define _0007_TAU_CKM0_FCLK_7                   (0x0007U) /* ckm0 - fCLK/2^7 */
+#define _0008_TAU_CKM0_FCLK_8                   (0x0008U) /* ckm0 - fCLK/2^8 */
+#define _0009_TAU_CKM0_FCLK_9                   (0x0009U) /* ckm0 - fCLK/2^9 */
+#define _000A_TAU_CKM0_FCLK_10                  (0x000AU) /* ckm0 - fCLK/2^10 */
+#define _000B_TAU_CKM0_FCLK_11                  (0x000BU) /* ckm0 - fCLK/2^11 */
+#define _000C_TAU_CKM0_FCLK_12                  (0x000CU) /* ckm0 - fCLK/2^12 */
+#define _000D_TAU_CKM0_FCLK_13                  (0x000DU) /* ckm0 - fCLK/2^13 */
+#define _000E_TAU_CKM0_FCLK_14                  (0x000EU) /* ckm0 - fCLK/2^14 */
+#define _000F_TAU_CKM0_FCLK_15                  (0x000FU) /* ckm0 - fCLK/2^15 */
+/* Operating mode and clear mode selection (PRSm13 - PRSm10) */
+#define _0000_TAU_CKM1_FCLK_0                   (0x0000U) /* ckm1 - fCLK */
+#define _0010_TAU_CKM1_FCLK_1                   (0x0010U) /* ckm1 - fCLK/2^1 */
+#define _0020_TAU_CKM1_FCLK_2                   (0x0020U) /* ckm1 - fCLK/2^2 */
+#define _0030_TAU_CKM1_FCLK_3                   (0x0030U) /* ckm1 - fCLK/2^3 */
+#define _0040_TAU_CKM1_FCLK_4                   (0x0040U) /* ckm1 - fCLK/2^4 */
+#define _0050_TAU_CKM1_FCLK_5                   (0x0050U) /* ckm1 - fCLK/2^5 */
+#define _0060_TAU_CKM1_FCLK_6                   (0x0060U) /* ckm1 - fCLK/2^6 */
+#define _0070_TAU_CKM1_FCLK_7                   (0x0070U) /* ckm1 - fCLK/2^7 */
+#define _0080_TAU_CKM1_FCLK_8                   (0x0080U) /* ckm1 - fCLK/2^8 */
+#define _0090_TAU_CKM1_FCLK_9                   (0x0090U) /* ckm1 - fCLK/2^9 */
+#define _00A0_TAU_CKM1_FCLK_10                  (0x00A0U) /* ckm1 - fCLK/2^10 */
+#define _00B0_TAU_CKM1_FCLK_11                  (0x00B0U) /* ckm1 - fCLK/2^11 */
+#define _00C0_TAU_CKM1_FCLK_12                  (0x00C0U) /* ckm1 - fCLK/2^12 */
+#define _00D0_TAU_CKM1_FCLK_13                  (0x00D0U) /* ckm1 - fCLK/2^13 */
+#define _00E0_TAU_CKM1_FCLK_14                  (0x00E0U) /* ckm1 - fCLK/2^14 */
+#define _00F0_TAU_CKM1_FCLK_15                  (0x00F0U) /* ckm1 - fCLK/2^15 */
+/* Operating mode and clear mode selection (PRSm21 - PRSm20) */
+#define _0000_TAU_CKM2_FCLK_1                   (0x0000U) /* ckm2 - fCLK/2^1 */
+#define _0100_TAU_CKM2_FCLK_2                   (0x0100U) /* ckm2 - fCLK/2^2 */
+#define _0200_TAU_CKM2_FCLK_4                   (0x0200U) /* ckm2 - fCLK/2^4 */
+#define _0300_TAU_CKM2_FCLK_6                   (0x0300U) /* ckm2 - fCLK/2^6 */
+/* Operating mode and clear mode selection (PRSm31 - PRSm30) */
+#define _0000_TAU_CKM3_FCLK_8                   (0x0000U) /* ckm2 - fCLK/2^8 */
+#define _1000_TAU_CKM3_FCLK_10                  (0x1000U) /* ckm2 - fCLK/2^10 */
+#define _2000_TAU_CKM3_FCLK_12                  (0x2000U) /* ckm2 - fCLK/2^12 */
+#define _3000_TAU_CKM3_FCLK_14                  (0x3000U) /* ckm2 - fCLK/2^14 */
+
+/*
+    Timer Mode Register mn (TMRmn)
+*/
+/* Selection of macro clock (MCK) of channel n (CKSmn1 - CKSmn0) */
+#define _0000_TAU_CLOCK_SELECT_CKM0             (0x0000U) /* operation clock CK0 set by PRS register */ 
+#define _8000_TAU_CLOCK_SELECT_CKM1             (0x8000U) /* operation clock CK1 set by PRS register */
+#define _4000_TAU_CLOCK_SELECT_CKM2             (0x4000U) /* operation clock CK2 set by PRS register */
+#define _C000_TAU_CLOCK_SELECT_CKM3             (0xC000U) /* operation clock CK3 set by PRS register */
+/* Selection of count clock (CCK) of channel n (CCSmn) */
+#define _0000_TAU_CLOCK_MODE_CKS                (0x0000U) /* macro clock MCK specified by CKSmn bit */  
+#define _1000_TAU_CLOCK_MODE_TIMN               (0x1000U) /* valid edge of input signal input from TImn pin */
+/* Selection of slave/master of channel n (MASTERmn) */
+#define _0000_TAU_COMBINATION_SLAVE             (0x0000U) /* operates as slave channel */
+#define _0000_TAU_COMBINATION_MASTER            (0x0000U) /* channel0 operates as master channel */
+#define _0800_TAU_COMBINATION_MASTER            (0x0800U) /* channel2, 4, 6 operates as master channel */
+/* Operation explanation of channel 1 or 3 (SPLIT) */
+#define _0000_TAU_16BITS_MODE                   (0x0000U) /* operates as 16 bits timer */  
+#define _0800_TAU_8BITS_MODE                    (0x0800U) /* operates as 8 bits timer */
+/* Setting of start trigger or capture trigger of channel n (STSmn2 - STSmn0) */
+#define _0000_TAU_TRIGGER_SOFTWARE              (0x0000U) /* only software trigger start is valid */
+#define _0100_TAU_TRIGGER_TIMN_VALID            (0x0100U) /* TImn input edge is used as a start/capture trigger */
+#define _0200_TAU_TRIGGER_TIMN_BOTH             (0x0200U) /* TImn input edges are used as a start/capture trigger */
+#define _0400_TAU_TRIGGER_MASTER_INT            (0x0400U) /* interrupt signal of the master channel is used */
+/* Selection of TImn pin input valid edge (CISmn1 - CISmn0) */
+#define _0000_TAU_TIMN_EDGE_FALLING             (0x0000U) /* falling edge */
+#define _0040_TAU_TIMN_EDGE_RISING              (0x0040U) /* rising edge */
+#define _0080_TAU_TIMN_EDGE_BOTH_LOW            (0x0080U) /* both edges (when low-level width is measured) */
+#define _00C0_TAU_TIMN_EDGE_BOTH_HIGH           (0x00C0U) /* both edges (when high-level width is measured) */
+/* Operation mode of channel n (MDmn3 - MDmn0) */
+#define _0000_TAU_MODE_INTERVAL_TIMER           (0x0000U) /* interval timer mode */
+#define _0004_TAU_MODE_CAPTURE                  (0x0004U) /* capture mode */
+#define _0006_TAU_MODE_EVENT_COUNT              (0x0006U) /* event counter mode */
+#define _0008_TAU_MODE_ONE_COUNT                (0x0008U) /* one count mode */
+#define _000C_TAU_MODE_HIGHLOW_MEASURE          (0x000CU) /* high-/low-level width measurement mode */
+#define _0001_TAU_MODE_PWM_MASTER               (0x0001U) /* PWM Function (Master Channel) mode */
+#define _0009_TAU_MODE_PWM_SLAVE                (0x0009U) /* PWM Function (Slave Channel) mode */
+#define _0008_TAU_MODE_ONESHOT                  (0x0008U) /* one-shot pulse output mode */
+/* Setting of starting counting and interrupt (MDmn0) */
+#define _0000_TAU_START_INT_UNUSED              (0x0000U) /* interrupt is not generated when counting is started */
+#define _0001_TAU_START_INT_USED                (0x0001U) /* interrupt is generated when counting is started */
+
+/*
+    Timer Status Register mn (TSRmn)
+*/
+/* Counter overflow status of channel n (OVF) */
+#define _0000_TAU_OVERFLOW_NOT_OCCURS           (0x0000U) /* overflow does not occur */
+#define _0001_TAU_OVERFLOW_OCCURS               (0x0001U) /* overflow occurs */
+
+/*
+    Timer Channel Enable Status Register m (TEm)
+*/
+/* Indication of operation enable/stop status of channel 0 (TEm0) */
+#define _0000_TAU_CH0_OPERATION_STOP            (0x0000U) /* operation is stopped */
+#define _0001_TAU_CH0_OPERATION_ENABLE          (0x0001U) /* operation is enabled */
+/* Indication of operation enable/stop status of channel 1 (TEm1) */
+#define _0000_TAU_CH1_OPERATION_STOP            (0x0000U) /* operation is stopped */
+#define _0002_TAU_CH1_OPERATION_ENABLE          (0x0002U) /* operation is enabled */
+/* Indication of operation enable/stop status of channel 2 (TEm2) */
+#define _0000_TAU_CH2_OPERATION_STOP            (0x0000U) /* operation is stopped */
+#define _0004_TAU_CH2_OPERATION_ENABLE          (0x0004U) /* operation is enabled */
+/* Indication of operation enable/stop status of channel 3 (TEm3) */
+#define _0000_TAU_CH3_OPERATION_STOP            (0x0000U) /* operation is stopped */
+#define _0008_TAU_CH3_OPERATION_ENABLE          (0x0008U) /* operation is enabled */
+/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEHm1) */
+#define _0000_TAU_CH1_H8_OPERATION_STOP         (0x0000U) /* operation is stopped */
+#define _0200_TAU_CH1_H8_OPERATION_ENABLE       (0x0200U) /* operation is enabled */
+/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEHm3) */
+#define _0000_TAU_CH3_H8_OPERATION_STOP         (0x0000U) /* operation is stopped */
+#define _0800_TAU_CH3_H8_OPERATION_ENABLE       (0x0800U) /* operation is enabled */
+
+/*
+    Timer Channel Start Register m (TSm)
+*/
+/* Operation enable (start) trigger of channel 0 (TSm0) */
+#define _0000_TAU_CH0_START_TRG_OFF             (0x0000U) /* no trigger operation */
+#define _0001_TAU_CH0_START_TRG_ON              (0x0001U) /* operation is enabled (start trigger is generated) */
+/* Operation enable (start) trigger of channel 1 (TSm1) */
+#define _0000_TAU_CH1_START_TRG_OFF             (0x0000U) /* no trigger operation */
+#define _0002_TAU_CH1_START_TRG_ON              (0x0002U) /* operation is enabled (start trigger is generated) */
+/* Operation enable (start) trigger of channel 2 (TSm2) */
+#define _0000_TAU_CH2_START_TRG_OFF             (0x0000U) /* no trigger operation */
+#define _0004_TAU_CH2_START_TRG_ON              (0x0004U) /* operation is enabled (start trigger is generated) */
+/* Operation enable (start) trigger of channel 3 (TSm3) */
+#define _0000_TAU_CH3_START_TRG_OFF             (0x0000U) /* no trigger operation */
+#define _0008_TAU_CH3_START_TRG_ON              (0x0008U) /* operation is enabled (start trigger is generated) */
+/* Operation enable (start) trigger of channel 1 higher 8 bits (TSHm1) */
+#define _0000_TAU_CH1_H8_START_TRG_OFF          (0x0000U) /* no trigger operation */
+#define _0200_TAU_CH1_H8_START_TRG_ON           (0x0200U) /* operation is enabled (start trigger is generated) */
+/* Operation enable (start) trigger of channel 3 higher 8 bits (TSHm3) */
+#define _0000_TAU_CH3_H8_START_TRG_OFF          (0x0000U) /* no trigger operation */
+#define _0800_TAU_CH3_H8_START_TRG_ON           (0x0800U) /* operation is enabled (start trigger is generated) */
+
+/*
+    Timer Channel Stop Register m (TTm)
+*/
+/* Operation stop trigger of channel 0 (TTm0) */
+#define _0000_TAU_CH0_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0001_TAU_CH0_STOP_TRG_ON               (0x0001U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 1 (TTm1) */
+#define _0000_TAU_CH1_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0002_TAU_CH1_STOP_TRG_ON               (0x0002U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 2 (TTm2) */
+#define _0000_TAU_CH2_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0004_TAU_CH2_STOP_TRG_ON               (0x0004U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 3 (TTm3) */
+#define _0000_TAU_CH3_STOP_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0008_TAU_CH3_STOP_TRG_ON               (0x0008U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 1 higher 8 bits (TTHm1) */
+#define _0000_TAU_CH1_H8_STOP_TRG_OFF           (0x0000U) /* no trigger operation */
+#define _0200_TAU_CH1_H8_STOP_TRG_ON            (0x0200U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 3 higher 8 bits (TTHm3) */
+#define _0000_TAU_CH3_H8_STOP_TRG_OFF           (0x0000U) /* no trigger operation */
+#define _0800_TAU_CH3_H8_STOP_TRG_ON            (0x0800U) /* operation is stopped (stop trigger is generated) */
+
+/*
+    Timer Input Select Register m (TIS0)
+*/
+/* Selection of timer input used with channel 1 (TIS01 - TIS00) */
+#define _00_TAU_CH1_INPUT_TI01                  (0x00U)   /* input signal of timer input pin (TI01) */
+#define _01_TAU_CH1_INPUT_FIL                   (0x01U)   /* internal low speed oscillation colock (fIL) */
+#define _10_TAU_CH1_INPUT_TI01                  (0x10U)   /* input signal of timer input pin (TI01) */
+
+/*
+    Timer Output Enable Register m (TOEm)
+*/
+/* Timer output enable/disable of channel 0 (TOEm0) */
+#define _0001_TAU_CH0_OUTPUT_ENABLE             (0x0001U) /* the TOm0 operation enabled by count operation */
+#define _0000_TAU_CH0_OUTPUT_DISABLE            (0x0000U) /* the TOm0 operation stopped by count operation */
+/* Timer output enable/disable of channel 1 (TOEm1) */
+#define _0002_TAU_CH1_OUTPUT_ENABLE             (0x0002U) /* the TOm1 operation enabled by count operation */
+#define _0000_TAU_CH1_OUTPUT_DISABLE            (0x0000U) /* the TOm1 operation stopped by count operation */
+/* Timer output enable/disable of channel 2 (TOEm2) */
+#define _0004_TAU_CH2_OUTPUT_ENABLE             (0x0004U) /* the TOm2 operation enabled by count operation */
+#define _0000_TAU_CH2_OUTPUT_DISABLE            (0x0000U) /* the TOm2 operation stopped by count operation */
+/* Timer output enable/disable of channel 3 (TOEm3) */
+#define _0008_TAU_CH3_OUTPUT_ENABLE             (0x0008U) /* the TOm3 operation enabled by count operation */
+#define _0000_TAU_CH3_OUTPUT_DISABLE            (0x0000U) /* the TOm3 operation stopped by count operation */
+
+/*
+    Timer Output Register m (TOm)
+*/
+/* Timer output of channel 0 (TOm0) */
+#define _0000_TAU_CH0_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
+#define _0001_TAU_CH0_OUTPUT_VALUE_1            (0x0001U) /* timer output value is "1" */
+/* Timer output of channel 1 (TOm1) */
+#define _0000_TAU_CH1_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
+#define _0002_TAU_CH1_OUTPUT_VALUE_1            (0x0002U) /* timer output value is "1" */
+/* Timer output of channel 2 (TOm2) */
+#define _0000_TAU_CH2_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
+#define _0004_TAU_CH2_OUTPUT_VALUE_1            (0x0004U) /* timer output value is "1" */
+/* Timer output of channel 3 (TOm3) */
+#define _0000_TAU_CH3_OUTPUT_VALUE_0            (0x0000U) /* timer output value is "0" */
+#define _0008_TAU_CH3_OUTPUT_VALUE_1            (0x0008U) /* timer output value is "1" */
+
+/*
+    Timer Output Level Register 0 (TOLm)
+*/
+/* Control of timer output level of channel 1 (TOLm1) */
+#define _0000_TAU_CH1_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
+#define _0002_TAU_CH1_OUTPUT_LEVEL_L            (0x0002U) /* inverted output (active-low) */
+/* Control of timer output level of channel 2 (TOLm2) */
+#define _0000_TAU_CH2_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
+#define _0004_TAU_CH2_OUTPUT_LEVEL_L            (0x0004U) /* inverted output (active-low) */
+/* Control of timer output level of channel 3 (TOLm3) */
+#define _0000_TAU_CH3_OUTPUT_LEVEL_H            (0x0000U) /* positive logic output (active-high) */
+#define _0008_TAU_CH3_OUTPUT_LEVEL_L            (0x0008U) /* inverted output (active-low) */
+
+/*
+    Timer Output Mode Register m (TOMm)
+*/
+/* Control of timer output mode of channel 1 (TOMm1) */
+#define _0000_TAU_CH1_OUTPUT_TOGGLE             (0x0000U) /* toggle operation mode */
+#define _0002_TAU_CH1_OUTPUT_COMBIN             (0x0002U) /* combination operation mode */
+/* Control of timer output mode of channel 2 (TOMm2) */
+#define _0000_TAU_CH2_OUTPUT_TOGGLE             (0x0000U) /* toggle operation mode */
+#define _0004_TAU_CH2_OUTPUT_COMBIN             (0x0004U) /* combination operation mode */
+/* Control of timer output mode of channel 3 (TOMm3) */
+#define _0000_TAU_CH3_OUTPUT_TOGGLE             (0x0000U) /* toggle operation mode */
+#define _0008_TAU_CH3_OUTPUT_COMBIN             (0x0008U) /* combination operation mode */
+
+/*
+    Input Switch Control Register (ISC)
+*/
+/* Switching channel 7 input of timer array unit (ISC1) */
+#define _00_TAU_CH7_NO_INPUT                    (0x00U)   /* timer input is not used */
+#define _02_TAU_CH7_RXD3_INPUT                  (0x02U)   /* input signal of RxD3 pin is used as timer input */
+
+/*
+    Noise Filter Enable Register 1 (NFEN1)
+*/
+/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */
+#define _00_TAU_CH3_NOISE_OFF                   (0x00U)   /* noise filter OFF */
+#define _08_TAU_CH3_NOISE_ON                    (0x08U)   /* noise filter ON */
+/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */
+#define _00_TAU_CH2_NOISE_OFF                   (0x00U)   /* noise filter OFF */
+#define _04_TAU_CH2_NOISE_ON                    (0x04U)   /* noise filter ON */
+/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */
+#define _00_TAU_CH1_NOISE_OFF                   (0x00U)   /* noise filter OFF */
+#define _02_TAU_CH1_NOISE_ON                    (0x02U)   /* noise filter ON */
+/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */
+#define _00_TAU_CH0_NOISE_OFF                   (0x00U)   /* noise filter OFF */
+#define _01_TAU_CH0_NOISE_ON                    (0x01U)   /* noise filter ON */
+
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* 16-bit timer data register 00 (TDR00) */
+#define _5DBF_TAU_TDR00_VALUE                   (0x5DBFU)
+/* Clock divisor for TAU0 channel 0 */
+#define _0001_TAU0_CHANNEL0_DIVISOR             (0x0001U)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_TAU0_Create(void);
+void R_TAU0_Channel0_Start(void);
+void R_TAU0_Channel0_Stop(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_timer_user.c b/r_cg_timer_user.c
new file mode 100644
index 0000000..b8b2a7b
--- /dev/null
+++ b/r_cg_timer_user.c
@@ -0,0 +1,66 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_timer_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for TAU module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+#include "event.h"
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+#pragma interrupt r_tau0_channel0_interrupt(vect=INTTM00)
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_tau0_channel0_interrupt
+* Description  : This function is INTTM00 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_tau0_channel0_interrupt(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    TimeBaseCount();
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_userdefine.h b/r_cg_userdefine.h
new file mode 100644
index 0000000..c549e0a
--- /dev/null
+++ b/r_cg_userdefine.h
@@ -0,0 +1,38 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_userdefine.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file includes user definition.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef _USER_DEF_H
+#define _USER_DEF_H
+
+/***********************************************************************************************************************
+User definitions
+***********************************************************************************************************************/
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_wdt.c b/r_cg_wdt.c
new file mode 100644
index 0000000..5b43ee0
--- /dev/null
+++ b/r_cg_wdt.c
@@ -0,0 +1,74 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_WDT_Create
+* Description  : This function initializes the watchdogtimer.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_WDT_Create(void)
+{
+    WDTIMK = 1U;    /* disable INTWDTI interrupt */
+    WDTIIF = 0U;    /* clear INTWDTI interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_WDT_Restart
+* Description  : This function restarts the watchdog timer.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_WDT_Restart(void)
+{
+    WDTE = 0xACU;   /* restart watchdog timer */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_cg_wdt.h b/r_cg_wdt.h
new file mode 100644
index 0000000..99163f4
--- /dev/null
+++ b/r_cg_wdt.h
@@ -0,0 +1,52 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt.h
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+#ifndef WDT_H
+#define WDT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_WDT_Create(void);
+void R_WDT_Restart(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/r_cg_wdt_user.c b/r_cg_wdt_user.c
new file mode 100644
index 0000000..f1fa65e
--- /dev/null
+++ b/r_cg_wdt_user.c
@@ -0,0 +1,51 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt_user.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_main.c b/r_main.c
new file mode 100644
index 0000000..626a703
--- /dev/null
+++ b/r_main.c
@@ -0,0 +1,90 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_main.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements main function.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+#include "r_cg_port.h"
+#include "r_cg_serial.h"
+#include "r_cg_timer.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+#include "appTask.h"
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+void R_MAIN_UserInit(void);
+
+/***********************************************************************************************************************
+* Function Name: main
+* Description  : This function implements main function.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void main(void)
+{
+    R_MAIN_UserInit();
+    /* Start user code. Do not edit comment generated here */
+    HardWare_Init();
+    Variable_Init();
+    
+    while (1U)
+    {
+        AppTask();
+    }
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_MAIN_UserInit
+* Description  : This function adds user code before implementing main function.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_MAIN_UserInit(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    EI();
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/r_systeminit.c b/r_systeminit.c
new file mode 100644
index 0000000..a220cbb
--- /dev/null
+++ b/r_systeminit.c
@@ -0,0 +1,86 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_systeminit.c
+* Version      : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
+* Device(s)    : R5F10268
+* Tool-Chain   : CCRL
+* Description  : This file implements system initializing function.
+* Creation Date: 2024-05-24
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+#include "r_cg_port.h"
+#include "r_cg_serial.h"
+#include "r_cg_timer.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description  : This function initializes every macro.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_Systeminit(void)
+{
+    PIOR = 0x02U;
+    R_CGC_Get_ResetSource();
+    R_CGC_Create();
+    R_PORT_Create();
+    R_SAU0_Create();
+    R_TAU0_Create();
+    R_WDT_Create();
+    IAWCTL = 0x00U;
+}
+
+
+/***********************************************************************************************************************
+* Function Name: hdwinit
+* Description  : This function initializes hardware setting.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void hdwinit(void)
+{
+    DI();
+    R_Systeminit();
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/stkinit.asm b/stkinit.asm
new file mode 100644
index 0000000..ed79566
--- /dev/null
+++ b/stkinit.asm
@@ -0,0 +1,77 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/;---------------------------------------------------------------------
+;	_stkinit
+;
+;	void _stkinit(void __near * stackbss);
+;
+;	input:
+;		stackbss = AX (#LOWW(_stackend))
+;	output:
+;		NONE
+;---------------------------------------------------------------------
+
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+	.PUBLIC	_stkinit
+
+.textf	.CSEG	TEXTF
+_stkinit:
+	MOVW	HL,AX		; stack_end_addr
+	MOV	[SP+3],#0x00	; [SP+0]-[SP+2] for return address
+	MOVW	AX,SP
+	SUBW	AX,HL		; SUBW  AX,#LOWW _@STEND
+	BNH	$LSTINIT3	; goto end
+	SHRW	AX,5		; loop count for 32 byte transfer
+	MOVW	BC,AX
+	CLRW	AX
+LSTINIT1:
+	CMPW	AX,BC
+	BZ	$LSTINIT2
+	MOVW	[HL],AX
+	MOVW	[HL+2],AX
+	MOVW	[HL+4],AX
+	MOVW	[HL+6],AX
+	MOVW	[HL+8],AX
+	MOVW	[HL+10],AX
+	MOVW	[HL+12],AX
+	MOVW	[HL+14],AX
+	MOVW	[HL+16],AX
+	MOVW	[HL+18],AX
+	MOVW	[HL+20],AX
+	MOVW	[HL+22],AX
+	MOVW	[HL+24],AX
+	MOVW	[HL+26],AX
+	MOVW	[HL+28],AX
+	MOVW	[HL+30],AX
+	XCHW	AX,HL
+	ADDW	AX,#0x20
+	XCHW	AX,HL
+	DECW	BC
+	BR	$LSTINIT1
+LSTINIT2:
+	MOVW	AX,SP
+	CMPW	AX,HL
+	BZ	$LSTINIT3	; goto end
+	CLRW	AX
+	MOVW	[HL],AX
+	INCW	HL
+	INCW	HL
+	BR	$LSTINIT2
+LSTINIT3:
+	RET