From 49552b7d756e0626b8eb6b30732045c21a59d911 Mon Sep 17 00:00:00 2001 From: sunbeam Date: Tue, 16 Jan 2024 10:46:17 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0indie=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- app_Indie/.gitignore | 14 + app_Indie/application.ewd | 1476 ++++++++++++++++ app_Indie/application.ewp | 1384 +++++++++++++++ app_Indie/application.ewt | 1524 +++++++++++++++++ app_Indie/drivers/core/inc/flash_sfrs.h | 84 + app_Indie/drivers/core/inc/systick_sfrs.h | 99 ++ app_Indie/drivers/core/inc/verne.h | 59 + app_Indie/drivers/core/src/cstartup_M.c | 212 +++ app_Indie/drivers/core/src/low_level_init.c | 76 + app_Indie/drivers/hal/inc/adc_device.h | 168 ++ app_Indie/drivers/hal/inc/atomic.h | 21 + app_Indie/drivers/hal/inc/clock_device.h | 37 + app_Indie/drivers/hal/inc/crc32_device.h | 45 + app_Indie/drivers/hal/inc/errno.h | 21 + app_Indie/drivers/hal/inc/flash_device.h | 34 + app_Indie/drivers/hal/inc/gpio_device.h | 89 + app_Indie/drivers/hal/inc/gtimer_device.h | 60 + app_Indie/drivers/hal/inc/hwProtection.h | 148 ++ app_Indie/drivers/hal/inc/lin_device.h | 153 ++ app_Indie/drivers/hal/inc/math_div_device.h | 39 + app_Indie/drivers/hal/inc/pmu_device.h | 122 ++ app_Indie/drivers/hal/inc/pwm_aux_device.h | 45 + app_Indie/drivers/hal/inc/pwm_device.h | 67 + app_Indie/drivers/hal/inc/spi_device.h | 35 + app_Indie/drivers/hal/inc/systick_device.h | 49 + app_Indie/drivers/hal/inc/uart_device.h | 43 + app_Indie/drivers/hal/inc/wdt_device.h | 62 + app_Indie/drivers/hal/src/adc_device.c | 201 +++ app_Indie/drivers/hal/src/clock_device.c | 48 + app_Indie/drivers/hal/src/crc32_device.c | 3 + app_Indie/drivers/hal/src/flash_device.c | 36 + app_Indie/drivers/hal/src/gTimer_device.c | 103 ++ app_Indie/drivers/hal/src/gpio_device.c | 121 ++ app_Indie/drivers/hal/src/hwProtection.c | 153 ++ app_Indie/drivers/hal/src/lin_device.c | 373 ++++ app_Indie/drivers/hal/src/math_div_device.c | 3 + app_Indie/drivers/hal/src/pmu_device.c | 154 ++ app_Indie/drivers/hal/src/pwm_aux_device.c | 94 + app_Indie/drivers/hal/src/pwm_device.c | 240 +++ app_Indie/drivers/hal/src/spi_device.c | 4 + app_Indie/drivers/hal/src/systick_device.c | 52 + app_Indie/drivers/hal/src/uart_device.c | 2 + app_Indie/drivers/hal/src/wdt_device.c | 77 + app_Indie/drivers/hdf/meta.h | 66 + app_Indie/drivers/hdf/sfrs/bte_sfr.h | 88 + app_Indie/drivers/hdf/sfrs/crc_sfr.h | 94 + app_Indie/drivers/hdf/sfrs/crga_sfr.h | 241 +++ app_Indie/drivers/hdf/sfrs/ctt_sfr.h | 271 +++ app_Indie/drivers/hdf/sfrs/evthold_sfr.h | 75 + app_Indie/drivers/hdf/sfrs/flash_sfr.h | 162 ++ app_Indie/drivers/hdf/sfrs/gpio_sfr.h | 106 ++ app_Indie/drivers/hdf/sfrs/gtimer_sfr.h | 113 ++ app_Indie/drivers/hdf/sfrs/ioctrla_sfr.h | 239 +++ app_Indie/drivers/hdf/sfrs/lins_sfr.h | 294 ++++ app_Indie/drivers/hdf/sfrs/mathdiv_sfr.h | 142 ++ app_Indie/drivers/hdf/sfrs/meta_sfr.h | 31 + app_Indie/drivers/hdf/sfrs/pmua_sfr.h | 171 ++ app_Indie/drivers/hdf/sfrs/pwm_aux_sfr.h | 207 +++ app_Indie/drivers/hdf/sfrs/pwm_sfr.h | 412 +++++ app_Indie/drivers/hdf/sfrs/realplum_sfr.h | 27 + app_Indie/drivers/hdf/sfrs/sar_ctrl_sfr.h | 246 +++ app_Indie/drivers/hdf/sfrs/spi_sfr.h | 143 ++ app_Indie/drivers/hdf/sfrs/sram_sfr.h | 74 + app_Indie/drivers/hdf/sfrs/syscfg_sfr.h | 149 ++ app_Indie/drivers/hdf/sfrs/sysctrla_sfr.h | 187 ++ app_Indie/drivers/hdf/sfrs/trimhv_sfr.h | 250 +++ app_Indie/drivers/hdf/sfrs/uart0_sfr.h | 244 +++ app_Indie/drivers/hdf/sfrs/wdt1_sfr.h | 86 + app_Indie/drivers/hdf/sfrs/wdta_sfr.h | 140 ++ app_Indie/drivers/hdf/sfrs/wica_sfr.h | 103 ++ app_Indie/drivers/hwcfg/inc/hwcfg.h | 118 ++ app_Indie/drivers/hwcfg/src/hwcfg.c | 106 ++ app_Indie/metaLite.eww | 7 + app_Indie/metaLite_app.icf | 31 + .../settings/application.Release.cspy.bat | 40 + .../settings/application.Release.cspy.ps1 | 31 + .../settings/application.Release.driver.xcl | 25 + .../settings/application.Release.general.xcl | 13 + app_Indie/settings/application.crun | 13 + app_Indie/usr/common/appConfig.h | 58 + app_Indie/usr/common/applicationTask.c | 85 + app_Indie/usr/common/applicationTask.h | 44 + app_Indie/usr/common/crc32.c | 35 + app_Indie/usr/common/crc32.h | 26 + app_Indie/usr/common/isrfuncs.h | 77 + app_Indie/usr/common/linSlaveTask.h | 86 + app_Indie/usr/common/linsNodeCfgIdentify.c | 210 +++ app_Indie/usr/common/linsNodeCfgIdentify.h | 68 + .../usr/common/linsNodeCfgIdentify_J2602.c | 182 ++ app_Indie/usr/common/linslaveTask.c | 416 +++++ app_Indie/usr/common/linslaveTask_J2602.c | 465 +++++ app_Indie/usr/common/linslaveTask_Private.c | 234 +++ app_Indie/usr/common/measureTask.c | 295 ++++ app_Indie/usr/common/measureTask.h | 40 + app_Indie/usr/common/motorControlTask.c | 504 ++++++ app_Indie/usr/common/motorControlTask.h | 221 +++ app_Indie/usr/common/pdsTask.c | 252 +++ app_Indie/usr/common/pdsTask.h | 97 ++ app_Indie/usr/common/safetyMonitorTask.c | 177 ++ app_Indie/usr/common/safetyMonitorTask.h | 34 + app_Indie/usr/common/systemInit.c | 117 ++ app_Indie/usr/common/systemInit.h | 35 + app_Indie/usr/common/taskManager.c | 114 ++ app_Indie/usr/common/taskManager.h | 73 + app_Indie/usr/common/validation.c | 190 ++ app_Indie/usr/common/validation.h | 8 + app_Indie/usr/library/LinStackTask_metaLite.a | Bin 0 -> 111132 bytes .../usr/library/SoftTimerTask_metaLite.a | Bin 0 -> 5602 bytes app_Indie/usr/library/linStackTask.h | 526 ++++++ app_Indie/usr/library/softTimerTask.h | 78 + app_Indie/usr/main.c | 72 + 111 files changed, 17394 insertions(+) create mode 100644 app_Indie/.gitignore create mode 100644 app_Indie/application.ewd create mode 100644 app_Indie/application.ewp create mode 100644 app_Indie/application.ewt create mode 100644 app_Indie/drivers/core/inc/flash_sfrs.h create mode 100644 app_Indie/drivers/core/inc/systick_sfrs.h create mode 100644 app_Indie/drivers/core/inc/verne.h create mode 100644 app_Indie/drivers/core/src/cstartup_M.c create mode 100644 app_Indie/drivers/core/src/low_level_init.c create mode 100644 app_Indie/drivers/hal/inc/adc_device.h create mode 100644 app_Indie/drivers/hal/inc/atomic.h create mode 100644 app_Indie/drivers/hal/inc/clock_device.h create mode 100644 app_Indie/drivers/hal/inc/crc32_device.h create mode 100644 app_Indie/drivers/hal/inc/errno.h create mode 100644 app_Indie/drivers/hal/inc/flash_device.h create mode 100644 app_Indie/drivers/hal/inc/gpio_device.h create mode 100644 app_Indie/drivers/hal/inc/gtimer_device.h create mode 100644 app_Indie/drivers/hal/inc/hwProtection.h create mode 100644 app_Indie/drivers/hal/inc/lin_device.h create mode 100644 app_Indie/drivers/hal/inc/math_div_device.h create mode 100644 app_Indie/drivers/hal/inc/pmu_device.h create mode 100644 app_Indie/drivers/hal/inc/pwm_aux_device.h create mode 100644 app_Indie/drivers/hal/inc/pwm_device.h create mode 100644 app_Indie/drivers/hal/inc/spi_device.h create mode 100644 app_Indie/drivers/hal/inc/systick_device.h create mode 100644 app_Indie/drivers/hal/inc/uart_device.h create mode 100644 app_Indie/drivers/hal/inc/wdt_device.h create mode 100644 app_Indie/drivers/hal/src/adc_device.c create mode 100644 app_Indie/drivers/hal/src/clock_device.c create mode 100644 app_Indie/drivers/hal/src/crc32_device.c create mode 100644 app_Indie/drivers/hal/src/flash_device.c create mode 100644 app_Indie/drivers/hal/src/gTimer_device.c create mode 100644 app_Indie/drivers/hal/src/gpio_device.c create mode 100644 app_Indie/drivers/hal/src/hwProtection.c create mode 100644 app_Indie/drivers/hal/src/lin_device.c create mode 100644 app_Indie/drivers/hal/src/math_div_device.c create mode 100644 app_Indie/drivers/hal/src/pmu_device.c create mode 100644 app_Indie/drivers/hal/src/pwm_aux_device.c create mode 100644 app_Indie/drivers/hal/src/pwm_device.c create mode 100644 app_Indie/drivers/hal/src/spi_device.c create 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100644 app_Indie/usr/common/linslaveTask_Private.c create mode 100644 app_Indie/usr/common/measureTask.c create mode 100644 app_Indie/usr/common/measureTask.h create mode 100644 app_Indie/usr/common/motorControlTask.c create mode 100644 app_Indie/usr/common/motorControlTask.h create mode 100644 app_Indie/usr/common/pdsTask.c create mode 100644 app_Indie/usr/common/pdsTask.h create mode 100644 app_Indie/usr/common/safetyMonitorTask.c create mode 100644 app_Indie/usr/common/safetyMonitorTask.h create mode 100644 app_Indie/usr/common/systemInit.c create mode 100644 app_Indie/usr/common/systemInit.h create mode 100644 app_Indie/usr/common/taskManager.c create mode 100644 app_Indie/usr/common/taskManager.h create mode 100644 app_Indie/usr/common/validation.c create mode 100644 app_Indie/usr/common/validation.h create mode 100644 app_Indie/usr/library/LinStackTask_metaLite.a create mode 100644 app_Indie/usr/library/SoftTimerTask_metaLite.a create mode 100644 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$PROJ_DIR$\usr\common\applicationTask.c + + + $PROJ_DIR$\usr\common\linslaveTask.c + + + $PROJ_DIR$\usr\common\linslaveTask_J2602.c + + + $PROJ_DIR$\usr\common\linslaveTask_Private.c + + + $PROJ_DIR$\usr\common\linsNodeCfgIdentify.c + + + $PROJ_DIR$\usr\common\linsNodeCfgIdentify_J2602.c + + + $PROJ_DIR$\usr\common\measureTask.c + + + $PROJ_DIR$\usr\common\motorControlTask.c + + + $PROJ_DIR$\usr\common\pdsTask.c + + + $PROJ_DIR$\usr\common\safetyMonitorTask.c + + + + + crc + + include + + $PROJ_DIR$\usr\common\crc32.h + + + + src + + $PROJ_DIR$\usr\common\crc32.c + + + + + drivers + + core + + inc + + $PROJ_DIR$\drivers\core\inc\flash_sfrs.h + + + $PROJ_DIR$\drivers\core\inc\systick_sfrs.h + + + $PROJ_DIR$\drivers\core\inc\verne.h + + + + src + + $PROJ_DIR$\drivers\core\src\cstartup_M.c + + + $PROJ_DIR$\drivers\core\src\low_level_init.c + + + + + hal + + inc + + $PROJ_DIR$\drivers\hal\inc\adc_device.h + + + $PROJ_DIR$\drivers\hal\inc\atomic.h + + + $PROJ_DIR$\drivers\hal\inc\clock_device.h + + + $PROJ_DIR$\drivers\hal\inc\errno.h + + + $PROJ_DIR$\drivers\hal\inc\flash_device.h + + + $PROJ_DIR$\drivers\hal\inc\gpio_device.h + + + $PROJ_DIR$\drivers\hal\inc\hwProtection.h + + + $PROJ_DIR$\drivers\hal\inc\lin_device.h + + + $PROJ_DIR$\drivers\hal\inc\pmu_device.h + + + $PROJ_DIR$\drivers\hal\inc\pwm_aux_device.h + + + $PROJ_DIR$\drivers\hal\inc\pwm_device.h + + + $PROJ_DIR$\drivers\hal\inc\systick_device.h + + + $PROJ_DIR$\drivers\hal\inc\timer_device.h + + + $PROJ_DIR$\drivers\hal\inc\wdt_device.h + + + + src + + $PROJ_DIR$\drivers\hal\src\adc_device.c + + + $PROJ_DIR$\drivers\hal\src\clock_device.c + + + $PROJ_DIR$\drivers\hal\src\flash_device.c + + + $PROJ_DIR$\drivers\hal\src\gpio_device.c + + + $PROJ_DIR$\drivers\hal\src\gTimer_device.c + + + $PROJ_DIR$\drivers\hal\src\hwProtection.c + + + $PROJ_DIR$\drivers\hal\src\lin_device.c + + + $PROJ_DIR$\drivers\hal\src\pmu_device.c + + + $PROJ_DIR$\drivers\hal\src\pwm_aux_device.c + + + $PROJ_DIR$\drivers\hal\src\pwm_device.c + + + $PROJ_DIR$\drivers\hal\src\systick_device.c + + + $PROJ_DIR$\drivers\hal\src\wdt_device.c + + + + + hdf + + inc + + $PROJ_DIR$\drivers\hdf\sfrs\adc_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\bte_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\buck_trim_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\buckctrl_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\crga_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\evthold_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\flash_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\gpio_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\ioctrla_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\linm_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\lins_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pmua_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pwm_aux_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pwm_sfr.h + + + $PROJ_DIR$\drivers\hdf\realplumPro.h + + + $PROJ_DIR$\drivers\hdf\sfrs\realplumPro_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\spi_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\sysctrla_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer0_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer1_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer2_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\uart_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wdt1_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wdta_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wica_sfr.h + + + + + hwcfg + + inc + + $PROJ_DIR$\drivers\hwcfg\inc\hwcfg.h + + + + src + + $PROJ_DIR$\drivers\hwcfg\src\hwcfg.c + + + + + + library + + $PROJ_DIR$\usr\library\LinStackTask_metaLite.a + + + $PROJ_DIR$\usr\library\SoftTimerTask_metaLite.a + + + + tasks + + $PROJ_DIR$\usr\common\systemInit.c + + + $PROJ_DIR$\usr\common\taskManager.c + + + $PROJ_DIR$\usr\common\validation.c + + + + $PROJ_DIR$\usr\main.c + + diff --git a/app_Indie/application.ewt b/app_Indie/application.ewt new file mode 100644 index 0000000..18938c9 --- /dev/null +++ b/app_Indie/application.ewt @@ -0,0 +1,1524 @@ + + + 3 + + Release + + ARM + + 0 + + C-STAT + 261 + + 261 + + 0 + + 1 + 600 + 1 + 4 + 0 + 1 + 100 + + + 1.5.3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RuntimeChecking + 0 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + applications + + config + + $PROJ_DIR$\usr\common\appConfig.h + + + + include + + $PROJ_DIR$\usr\common\applicationTask.h + + + $PROJ_DIR$\usr\common\isrfuncs.h + + + $PROJ_DIR$\usr\leds\ledParamTables.h + + + $PROJ_DIR$\usr\common\linMasterTask.h + + + $PROJ_DIR$\usr\common\linslaveTask.h + + + $PROJ_DIR$\usr\common\linsNodeCfgIdentify.h + + + $PROJ_DIR$\usr\library\linStackTask.h + + + $PROJ_DIR$\usr\common\measureTask.h + + + $PROJ_DIR$\usr\common\motorControlTask.h + + + $PROJ_DIR$\usr\common\pdsTask.h + + + $PROJ_DIR$\usr\common\safetyMonitorTask.h + + + $PROJ_DIR$\usr\library\SoftTimerTask.h + + + $PROJ_DIR$\usr\common\systemInit.h + + + $PROJ_DIR$\usr\common\taskManager.h + + + + src + + $PROJ_DIR$\usr\common\applicationTask.c + + + $PROJ_DIR$\usr\common\linslaveTask.c + + + $PROJ_DIR$\usr\common\linslaveTask_J2602.c + + + $PROJ_DIR$\usr\common\linslaveTask_Private.c + + + $PROJ_DIR$\usr\common\linsNodeCfgIdentify.c + + + $PROJ_DIR$\usr\common\linsNodeCfgIdentify_J2602.c + + + $PROJ_DIR$\usr\common\measureTask.c + + + $PROJ_DIR$\usr\common\motorControlTask.c + + + $PROJ_DIR$\usr\common\pdsTask.c + + + $PROJ_DIR$\usr\common\safetyMonitorTask.c + + + + + crc + + include + + $PROJ_DIR$\usr\common\crc32.h + + + + src + + $PROJ_DIR$\usr\common\crc32.c + + + + + drivers + + core + + inc + + $PROJ_DIR$\drivers\core\inc\flash_sfrs.h + + + $PROJ_DIR$\drivers\core\inc\systick_sfrs.h + + + $PROJ_DIR$\drivers\core\inc\verne.h + + + + src + + $PROJ_DIR$\drivers\core\src\cstartup_M.c + + + $PROJ_DIR$\drivers\core\src\low_level_init.c + + + + + hal + + inc + + $PROJ_DIR$\drivers\hal\inc\adc_device.h + + + $PROJ_DIR$\drivers\hal\inc\atomic.h + + + $PROJ_DIR$\drivers\hal\inc\clock_device.h + + + $PROJ_DIR$\drivers\hal\inc\errno.h + + + $PROJ_DIR$\drivers\hal\inc\flash_device.h + + + $PROJ_DIR$\drivers\hal\inc\gpio_device.h + + + $PROJ_DIR$\drivers\hal\inc\hwProtection.h + + + $PROJ_DIR$\drivers\hal\inc\lin_device.h + + + $PROJ_DIR$\drivers\hal\inc\pmu_device.h + + + $PROJ_DIR$\drivers\hal\inc\pwm_aux_device.h + + + $PROJ_DIR$\drivers\hal\inc\pwm_device.h + + + $PROJ_DIR$\drivers\hal\inc\systick_device.h + + + $PROJ_DIR$\drivers\hal\inc\timer_device.h + + + $PROJ_DIR$\drivers\hal\inc\wdt_device.h + + + + src + + $PROJ_DIR$\drivers\hal\src\adc_device.c + + + $PROJ_DIR$\drivers\hal\src\clock_device.c + + + $PROJ_DIR$\drivers\hal\src\flash_device.c + + + $PROJ_DIR$\drivers\hal\src\gpio_device.c + + + $PROJ_DIR$\drivers\hal\src\gTimer_device.c + + + $PROJ_DIR$\drivers\hal\src\hwProtection.c + + + $PROJ_DIR$\drivers\hal\src\lin_device.c + + + $PROJ_DIR$\drivers\hal\src\pmu_device.c + + + $PROJ_DIR$\drivers\hal\src\pwm_aux_device.c + + + $PROJ_DIR$\drivers\hal\src\pwm_device.c + + + $PROJ_DIR$\drivers\hal\src\systick_device.c + + + $PROJ_DIR$\drivers\hal\src\wdt_device.c + + + + + hdf + + inc + + $PROJ_DIR$\drivers\hdf\sfrs\adc_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\bte_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\buck_trim_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\buckctrl_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\crga_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\evthold_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\flash_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\gpio_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\ioctrla_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\linm_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\lins_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pmua_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pwm_aux_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\pwm_sfr.h + + + $PROJ_DIR$\drivers\hdf\realplumPro.h + + + $PROJ_DIR$\drivers\hdf\sfrs\realplumPro_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\spi_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\sysctrla_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer0_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer1_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\timer2_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\uart_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wdt1_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wdta_sfr.h + + + $PROJ_DIR$\drivers\hdf\sfrs\wica_sfr.h + + + + + hwcfg + + inc + + $PROJ_DIR$\drivers\hwcfg\inc\hwcfg.h + + + + src + + $PROJ_DIR$\drivers\hwcfg\src\hwcfg.c + + + + + + library + + $PROJ_DIR$\usr\library\LinStackTask_metaLite.a + + + $PROJ_DIR$\usr\library\SoftTimerTask_metaLite.a + + + + tasks + + $PROJ_DIR$\usr\common\systemInit.c + + + $PROJ_DIR$\usr\common\taskManager.c + + + $PROJ_DIR$\usr\common\validation.c + + + + $PROJ_DIR$\usr\main.c + + diff --git a/app_Indie/drivers/core/inc/flash_sfrs.h b/app_Indie/drivers/core/inc/flash_sfrs.h new file mode 100644 index 0000000..a6450e2 --- /dev/null +++ b/app_Indie/drivers/core/inc/flash_sfrs.h @@ -0,0 +1,84 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file flash_sfrs.h + */ + +#ifndef FLASH_SFRS_H__ +#define FLASH_SFRS_H__ + +#include +#include +#include + +#define FLASH_WRITE_1_BYTE 0x01// +#define FLASH_WRITE_2_BYTE 0x01// +#define FLASH_WRITE_4_BYTE_L 0x0F// +#define FLASH_WRITE_4_BYTE_M_ECC 0x1F0// +#define FLASH_WRITE_8_BYTE 0xFF// +#define FLASH_WRITE_9_BYTE 0x1FF// + +#define E_FLASH_ERASE_SECTOR 0// +#define E_FLASH_ERASE_CHIP 1// + +#define E_FLASH_UNLOCK_WRITE 0x55555555U +#define E_FLASH_UNLOCK_ERASE 0x66666666U +#define E_FLASH_ERASE_START 0x99999999U +#define E_FLASH_WRITE_START 0xAAAAAAAAU +#define E_FLASH_UNLOCK_CTRL 0xACDC1972U + +#define NVR_FLASH_WRITE_START 0x502901FFU +#define NVR_FLASH_ERASE_START 0x502901FFU + +#define E_FLASH_CODE_PROTECT 0xF2E11047U +#define E_FLASH_WRITE_PROTECT 0x12100511U + + +/** +* @brief Flash memory erase sector function. +* +* @param address inside the sector to be erased. +*/ +static __INLINE void f_FLASH_EraseSector(__IO uint32_t address) +{ + /* load address */ + FLASH_SFRS->FLADDR.FLASHADDR = (uint32_t)(address>>3U); + FLASH_SFRS->UNLOCK_CTRL_OP = E_FLASH_UNLOCK_CTRL; + FLASH_SFRS->CTRL_OPR.CHIPSEL = E_FLASH_ERASE_SECTOR; + FLASH_SFRS-> UNLOCK_ERASE = E_FLASH_UNLOCK_ERASE; + FLASH_SFRS-> ERASE_START = E_FLASH_ERASE_START; + while(FLASH_SFRS->OPBSY != 0U); + + FLASH_SFRS->UNLOCK_CTRL_OP = 0; +} + +/** +* @brief Flash memory write word function. +* +* @param address and data (byte) to be programmed into flash. +* @param data and data (byte) to be programmed into flash. +*/ +static __INLINE void f_FLASH_Write2WordsWithECC(__IO uint32_t address, uint32_t dataL,uint32_t dataH) +{ + FLASH_SFRS->UNLOCK_CTRL_OP = E_FLASH_UNLOCK_CTRL; + FLASH_SFRS->CTRL_OPR.BYTESEL = FLASH_WRITE_9_BYTE; + + FLASH_SFRS->FLADDR.FLASHADDR = (uint32_t)(address >> 3); + FLASH_SFRS->DATAL = dataL; + FLASH_SFRS->DATAM = dataH; + + FLASH_SFRS->UNLOCK_WRITE = E_FLASH_UNLOCK_WRITE; + FLASH_SFRS->FLADDR.NVR = 0; + FLASH_SFRS->WRITE_START = E_FLASH_WRITE_START; + while(FLASH_SFRS->OPBSY != 0); + + FLASH_SFRS->UNLOCK_CTRL_OP = 0; +} + + +#endif /* __FLASH_SFRS_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/core/inc/systick_sfrs.h b/app_Indie/drivers/core/inc/systick_sfrs.h new file mode 100644 index 0000000..350f47f --- /dev/null +++ b/app_Indie/drivers/core/inc/systick_sfrs.h @@ -0,0 +1,99 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file systick_sfrs.h + */ + +#ifndef SYSTICK_SFRS_H__ +#define SYSTICK_SFRS_H__ + +#include +#include +/** + * @brief Enable SysTick timer. + */ +static __INLINE void f_SYSTICK_Enable(void) +{ + SysTick->CTRL |= (SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk); +} + +/** + * @brief Disable SysTick timer. + */ +static __INLINE void f_SYSTICK_Disable(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Check if SysTick timer enable. + * + * @return 0 if disable. + */ +static __INLINE uint8_t f_SYSTICK_IsEnabled(void) +{ + + return (uint8_t)(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk); +} + +/** + * @brief Enable SysTick timer interrupt. + */ +static __INLINE void f_SYSTICK_IntEnable(void) +{ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Disable SysTick timer interrupt. + */ +static __INLINE void f_SYSTICK_IntDisable(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Set Reload value of SysTick timer. + * + * @param ticks The tick number to be set. + */ +static __INLINE void f_SYSTICK_SetLoad(uint32_t ticks) +{ + SysTick->LOAD = ticks; +} + +/** + * @brief Set counter value of SysTick timer. + * + * @param ticks The tick number to be set. + */ +static __INLINE void f_SYSTICK_SetCount(uint32_t ticks) +{ + SysTick->VAL = ticks; +} + +/** + * @brief Get counter value of SysTick timer. + * + * @return The current counter of Systick timer. + */ +static __INLINE uint32_t f_SYSTICK_GetCount(void) +{ + return SysTick->VAL; +} + +/** + * @brief Get load value of SysTick timer. + * + * @return The load setting of Systick timer. + */ +static __INLINE uint32_t f_SYSTICK_GetLoad(void) +{ + return SysTick->LOAD; +} +#endif /* __SYSTICK_SFRS_H__ */ diff --git a/app_Indie/drivers/core/inc/verne.h b/app_Indie/drivers/core/inc/verne.h new file mode 100644 index 0000000..484d042 --- /dev/null +++ b/app_Indie/drivers/core/inc/verne.h @@ -0,0 +1,59 @@ +#ifndef FlashChipVerneBased_H +#define FlashChipVerneBased_H + +/********************************************************************************************************************/ +/* Number of IRQ priority level bits - must be defined before loading core_cm0.h*/ +/********************************************************************************************************************/ + +/* #define __NVIC_PRIO_BITS 2 */ + +/********************************************************************************************************************/ +/*Includes*/ +/********************************************************************************************************************/ +#include "core_cm0.h" +#include + +/* + end of define :obsoleted in future +*/ +/*Definition of the several memory segments defined in Heimdall Slave +Warning: DO NOT CHANGE definitions without careful consideration and +if at all possible contact Aydeekay LLC!*/ + +/*Flash Memory, addresses, sizes and blocks information*/ + + +#define FLASH_INITIAL_ADDRESS 0x0L +#define FLASH_FINAL_ADDRESS 0xBFFFU +#define FLASH_SIZE ( ( FLASH_FINAL_ADDRESS - FLASH_INITIAL_ADDRESS ) + 1 ) +#define FLASH_SECTOR_SIZE 0x200U +#define FLASH_SECTOR_SIZE_POS (9U) +#define NUMBER_FLASH_SECTORS (FLASH_SIZE/FLASH_SECTOR_SIZE) + + +/*SRAM Memory*/ +#define SRAM_INITIAL_ADDRESS 0x20000000U +#define SRAM_FINAL_ADDRESS 0x20003FFFU +#define SRAM_SIZE ( ( SRAM_FINAL_ADDRESS - SRAM_INITIAL_ADDRESS ) + 1 ) + +/************** ARM INTERNAL Registers *****************/ +/*WARNING: DO NOT TOUCH!*/ +/*******************************************************/ + + +/* +- 7K -bootlaoder +- 36K -app +- 4K -user param +- 1K -color lib param +*/ +#define FLASH_STRAT_ADDRESS_BOOTLOADER (0x0000U) +#define FLASH_START_ADDRESS_APPLICATION (0x1C08U) /* 7K */ +#define FLASH_START_ADDRESS_USER_DATA (0xAC00U) /* 7K + 36K*/ +#define FLASH_START_ADDRESS_SYSTEM_DATA (0xBC00U) /* 7K + 36K + +4K + 0.5K*/ +#define FLASH_START_ADDRESS_SYSTEM_DATA_BACK_UP (0xBE00U) /* 7K + 36K + +4K + 1.0K*/ +#define FLASH_END (0xBFFFU) +#define IMAGE_MAX_SIZE (FLASH_START_ADDRESS_USER_DATA - FLASH_START_ADDRESS_APPLICATION) + + +#endif diff --git a/app_Indie/drivers/core/src/cstartup_M.c b/app_Indie/drivers/core/src/cstartup_M.c new file mode 100644 index 0000000..ace922c --- /dev/null +++ b/app_Indie/drivers/core/src/cstartup_M.c @@ -0,0 +1,212 @@ +/************************************************** + * + * This file contains an interrupt vector + * KamCho. (Cortex-M written in C) + * The actual interrupt functions must be provided + * by the application developer. + * + * Copyright 2007 IAR Systems. All rights reserved. + * + * $Revision: 3998 $ + * + **************************************************/ + +#pragma language=extended +#pragma segment="CSTACK" + +#include + +typedef void( *intfunc_t )( void ); + +__weak void NMI_Handler(void){asm("nop");} +__weak void HardFault_Handler(void){while(1);} +__weak void MemManage_Handler(void){while(1);} +__weak void BusFault_Handler(void){while(1);} +__weak void UsageFault_Handler(void){while(1);} +__weak void SysTick_Handler(void){while(1);} + +__weak void IOCTRLA_Handler(void){while(1);} +__weak void OVTEMP_Handler(void){while(1);} +__weak void GPIO_Handler(void){while(1);} +__weak void PWM_AUX_Handler(void){while(1);} +__weak void GT4_5_Handler(void){while(1);} + +__weak void WUTIMER_Handler(void){while(1);} +__weak void WatchdogA_Handler(void){while(1);} +__weak void ADC_Handler(void){while(1);} +__weak void SPI_Handler(void){while(1);} +__weak void WULINS_Handler(void){while(1);} + +__weak void UART0_Handler(void){while(1);} +__weak void Divider_Handler(void){while(1);} +__weak void LIN_Handler(void){while(1);} +__weak void FlashEcc_Handler(void){while(1);} +__weak void RamEcc_Handler(void){while(1);} + +__weak void GT1_Handler(void){while(1);} +__weak void GT2_Handler(void){while(1);} +__weak void GT3_Handler(void){while(1);} +__weak void CT2_Handler(void){while(1);} +__weak void CT3_Handler(void){while(1);} + +__weak void CT4_Handler(void){while(1);} +__weak void CT5_Handler(void){while(1);} +__weak void CT6_Handler(void){while(1);} +__weak void CR_Handler(void){while(1);} +__weak void PWM_INTOL0_Handler(void){while(1);} + +__weak void PWM_INTOL1_Handler(void){while(1);} +__weak void PWM_INTOL2_Handler(void){while(1);} +__weak void PWM_INTOL3_Handler(void){while(1);} +__weak void BOR_Handler(void){while(1);} +__weak void UV_OV_Handler(void){while(1);} + +__weak void CSA_OCP_Handler(void){while(1);} +__weak void Lullaby_Handler(void){while(1);} + +__weak void error(void){while(1);} + + +void __iar_program_start( void ); + +typedef struct{ + void * __ptr; + intfunc_t _iar_program_start; + intfunc_t _NMI_Handler; + intfunc_t _HardFault_Handler; + intfunc_t _MemManage_Handler; + intfunc_t _BusFault_Handler; + intfunc_t _UsageFault_Handler; + intfunc_t _rsv0; + intfunc_t _rsv1; + intfunc_t _rsv2; + intfunc_t _rsv3; + intfunc_t _SVC_Handler; + intfunc_t _DebugMon_Handler; + intfunc_t _rsv4; + intfunc_t _PendSV_Handler; + intfunc_t _SysTick_Handler; + + intfunc_t _IOCTRLA_Handler; /* ASIC irq 0 - - IOCTRLA TXD Dominate */ + intfunc_t _OVTEMP_Handler; /* ASIC irq 1 - OVTEMP*/ + intfunc_t _GPIO_Handler; /* ASIC irq 2 - GPIO */ + intfunc_t _PWM_AUX_Handler; /* ASIC irq 3 - PWM_AUX */ + intfunc_t _GT4_5_Handler; /* ASIC irq 4 - GT4_5 */ + + intfunc_t _WUTIMER_Handler; /* ASIC irq 5 - Wake Up TIMER */ + intfunc_t _WatchdogA_Handler; /* ASIC irq 6 - Watchdog Timer*/ + intfunc_t _ADC_Handler; /* ASIC irq 7 - ADC data ready*/ + intfunc_t _SPI_Handler; /* ASIC irq 8 - SPI */ + intfunc_t _WULINS_Handler; /* ASIC irq 9 - WULIN */ + + intfunc_t _UART0_Handler; /* ASIC irq 10 - UART0*/ + intfunc_t _Divider_Handler; /* ASIC irq 11 - DIVIDER */ + intfunc_t _LIN_Handler; /* ASIC irq 12 - Lin */ + intfunc_t _FlashEcc_Handler; /* ASIC irq 13 - FLASH ECC and protect interrupt */ + intfunc_t _RamEcc_Handler; /* ASIC irq 14 - SRAM ECC interrupt */ + + intfunc_t _GT1_Handler; /* ASIC irq 15 - GT1 */ + intfunc_t _GT2_Handler; /* vern irq 16 - GT2*/ + intfunc_t _GT3_Handler; /* vern irq 17 - GT3*/ + intfunc_t _CT2_Handler; /* vern irq 18 - CT2*/ + intfunc_t _CT3_Handler; /* vern irq 19 - CT3*/ + + intfunc_t _CT4_Handler; /* vern irq 20 - CT4*/ + intfunc_t _CT5_Handler; /* vern irq 21 - CT5*/ + intfunc_t _CT6_Handler; /* vern irq 22 - CT6*/ + intfunc_t _CR_Handler; /* vern irq 23 - crirq interrupt*/ + intfunc_t _PWM_INTOL0_Handler; /* vern irq 24 - pwm 0 interrupt*/ + + intfunc_t _PWM_INTOL1_Handler; /* vern irq 25 - pwm 1 interrupt*/ + intfunc_t _PWM_INTOL2_Handler; /* vern irq 26 - pwm 2 interrupt*/ + intfunc_t _PWM_INTOL3_Handler; /* vern irq 27 - pwm 3 interrupt*/ + intfunc_t _BOR_Handler; /* vern irq 28 - BOR*/ + intfunc_t _UV_OV_Handler; /* vern irq 29 - Under Voltage Event*/ + + intfunc_t _CSA_OCP_Handler; /* vern irq 30 - CSA_OCP Event*/ + intfunc_t Lullaby_Handler; /* vern irq 31 - Software interrupt which will mask all the other interrupts*/ +}intvecTable_t; + +/* + The vector table is normally located at address 0. + When debugging in RAM, it can be located in RAM, aligned to at least 2^6. + If you need to define interrupt service routines, + make a copy of this file and include it in your project. + The name "__vector_table" has special meaning for C-SPY: + it is where the SP start value is found, and the NVIC vector + table register (VTOR) is initialized to this address if != 0. +*/ + +#pragma location = ".intvec" +static const intvecTable_t __vector_table = +{ + .__ptr = __sfe( "CSTACK" ), + ._iar_program_start = __iar_program_start, + ._NMI_Handler = NMI_Handler, + ._HardFault_Handler = HardFault_Handler, + ._MemManage_Handler = MemManage_Handler, + ._BusFault_Handler = BusFault_Handler, + ._UsageFault_Handler = UsageFault_Handler, + ._rsv0 = 0U, + ._rsv1 = 0U, + ._rsv2 = 0U, + ._rsv3 = 0U, + ._SVC_Handler = SVC_Handler, + ._DebugMon_Handler = error, + ._rsv4 = 0U, + ._PendSV_Handler = PendSV_Handler, + ._SysTick_Handler = SysTick_Handler, + + ._IOCTRLA_Handler = IOCTRLA_Handler, /* ASIC irq 0 - - IOCTRLA TXD Dominate */ + ._OVTEMP_Handler = OVTEMP_Handler, /* ASIC irq 1 - OVTEMP*/ + ._GPIO_Handler = GPIO_Handler, /* ASIC irq 2 - GPIO */ + ._PWM_AUX_Handler = PWM_AUX_Handler, /* ASIC irq 3 - PWM_AUX */ + ._GT4_5_Handler = GT4_5_Handler, /* ASIC irq 4 - GT4_5*/ + + ._WUTIMER_Handler = WUTIMER_Handler, /* ASIC irq 5 - Wake Up TIMER */ + ._WatchdogA_Handler = WatchdogA_Handler, /* ASIC irq 6 - Watchdog Timer*/ + ._ADC_Handler = ADC_Handler, /* ASIC irq 7 - ADC data ready*/ + ._SPI_Handler = SPI_Handler, /* ASIC irq 8 - SPI */ + ._WULINS_Handler = WULINS_Handler, /* ASIC irq 9 - WULIN */ + + ._UART0_Handler = UART0_Handler, /* ASIC irq 10 - UART0*/ + ._Divider_Handler = Divider_Handler, /* ASIC irq 11 - DIVIDER */ + ._LIN_Handler = LIN_Handler, /* ASIC irq 12 - Lin */ + ._FlashEcc_Handler = FlashEcc_Handler, /* ASIC irq 13 - FLASH ECC and protect interrupt */ + ._RamEcc_Handler = RamEcc_Handler, /* ASIC irq 14 - SRAM ECC interrupt */ + + ._GT1_Handler = GT1_Handler, /* ASIC irq 15 - GT1 */ + ._GT2_Handler = GT2_Handler, /* vern irq 16 - GT2*/ + ._GT3_Handler = GT3_Handler, /* vern irq 17 - GT3*/ + ._CT2_Handler = CT2_Handler, /* vern irq 18 - CT2*/ + ._CT3_Handler = CT3_Handler, /* vern irq 19 - CT3*/ + + ._CT4_Handler = CT4_Handler, /* vern irq 20 - CT4*/ + ._CT5_Handler = CT5_Handler, /* vern irq 21 - CT5*/ + ._CT6_Handler = CT6_Handler, /* vern irq 22 - CT6*/ + ._CR_Handler = CR_Handler, /* vern irq 23 - crirq interrupt*/ + ._PWM_INTOL0_Handler = PWM_INTOL0_Handler, /* vern irq 24 - pwm intol0 interrupt*/ + + ._PWM_INTOL1_Handler = PWM_INTOL1_Handler, /* vern irq 25 - pwm intol1 interrupt*/ + ._PWM_INTOL2_Handler = PWM_INTOL2_Handler, /* vern irq 26 - pwm intol2 interrupt*/ + ._PWM_INTOL3_Handler = PWM_INTOL3_Handler, /* vern irq 27 - pwm intol3 interrupt*/ + ._BOR_Handler = BOR_Handler, /* vern irq 28 - BOR*/ + ._UV_OV_Handler = UV_OV_Handler, /* vern irq 29 - Under Voltage Event*/ + + ._CSA_OCP_Handler = CSA_OCP_Handler, /* vern irq 30 - CSA_OCP Event*/ + .Lullaby_Handler = Lullaby_Handler, /* vern irq 31 - Software interrupt which will mask all the other interrupts*/ +}; + + +void __cmain( void ); + +__weak void __iar_init_core( void ); +__weak void __iar_init_vfp( void ); + +#pragma required=__vector_table +void __iar_program_start( void ) +{ + __iar_init_core(); + __iar_init_vfp(); + __cmain(); +} diff --git a/app_Indie/drivers/core/src/low_level_init.c b/app_Indie/drivers/core/src/low_level_init.c new file mode 100644 index 0000000..8e1f487 --- /dev/null +++ b/app_Indie/drivers/core/src/low_level_init.c @@ -0,0 +1,76 @@ +/************************************************** + * + * This module contains the function `__low_level_init', a function + * that is called before the `main' function of the program. Normally + * low-level initializations - such as setting the prefered interrupt + * level or setting the watchdog - can be performed here. + * + * Note that this function is called before the data segments are + * initialized, this means that this function cannot rely on the + * values of global or static variables. + * + * When this function returns zero, the startup code will inhibit the + * initialization of the data segments. The result is faster startup, + * the drawback is that neither global nor static data will be + * initialized. + * + * Copyright 1999-2004 IAR Systems. All rights reserved. + * + * $Revision: 2474 $ + * + **************************************************/ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#pragma language=extended + +__interwork int __low_level_init(void); + +__interwork int __low_level_init(void) +{ + /*==================================*/ + /* Initialize hardware. */ + /*==================================*/ + FLASH_SFRS->CTRL_OPR.FRWS = 2; + /* + Indie's Flash Initialization + For the Cortex M0 core (CM0160K8) + 0 Read/Write Wait-State Clock Cycles [2:0] + 0 Write/Erase Clock Divider [5:3] + */ +// /* Initial system clock to RC to allow faster boot up */ +// CRGA_SFRS->SYSCLKCTRL.HFRCENA = 1U; +// while(CRGA_SFRS->SYSCLKCTRL.HFRCSTS == 0U){} +// CRGA_SFRS->SYSCLKCTRL.SYSCLKSEL = 1U; + +// uint16_t rev = SYSCTRLA_SFRS->REV; +// if (SYSCTRLA_SFRS->NAME != 0x50454143U || (rev >> 8) != 0x42U){ /* 0x41='A', 0x42='B' */ +// /* invalid chip id*/ +// for(;;){} +// } + +// EVTHOLD_SFRS->HOLD = 0U; +// TRIMHV_SFRS->RETAIN.RETAIN1 |= 0x01U; /* figure out it's application mode */ +// /* Stop watchdog on ASIC */ +// WDTA_SFRS->STOPR.STOP = 0xC3U; +// /*==================================*/ +// /* Choose if segment initialization */ +// /* should be done or not. */ +// /* Return: 0 to omit seg_init */ +// /* 1 to run seg_init */ +// /*==================================*/ +FLASH_SFRS->FLSECCR.ECCCIE = 0; +FLASH_SFRS->FLSECCR.RDECCEN = 0; + return 1; +} + +#pragma language=default + +#ifdef __cplusplus +} +#endif diff --git a/app_Indie/drivers/hal/inc/adc_device.h b/app_Indie/drivers/hal/inc/adc_device.h new file mode 100644 index 0000000..2115ce9 --- /dev/null +++ b/app_Indie/drivers/hal/inc/adc_device.h @@ -0,0 +1,168 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file adc_device.h + */ + +#ifndef ADC_DEVICE_H__ +#define ADC_DEVICE_H__ + +#include +#include +#include +#include +#include +#include + +typedef enum { + ADC_REF_VBG = 0U, /* VBG = 1.22V */ + ADC_REF_VBG_2TIMES, /* 2* VBG */ + ADC_REF_VDD_3V3, +}AdcReference_t; + +typedef enum { + ADC_TRIGGER_SEL_GENERAL_TRIGSRC = 0x00U, + ADC_TRIGGER_SEL_PWM_AUX_TRIGSRC, +}AdcTriggerSEL_t; + +typedef enum { + ADC_PWMAUX_CHN0 = 0x00U, + ADC_PWMAUX_CHN1, + ADC_PWMAUX_CHN2, + ADC_PWMAUX_CHN3, + ADC_PWMAUX_CHN4, + ADC_PWMAUX_CHN5, +}AdcPwmAuxChannel_t; + +typedef enum { + ADC_PWMAUX_TRIG_SRC_PWM_RISING = 0x01U, + ADC_PWMAUX_TRIG_SRC_PWM_FALLING = 0x02U, + ADC_PWMAUX_TRIG_SRC_PWM_PERIOD0 = 0x04U, + ADC_PWMAUX_TRIG_SRC_PWM_PERIOD1 = 0x08U, +}AdcPwmAuxTriggerSRC_t; + +typedef enum { + ADC_TRIG_SRC_SOFT_INPUT = 0x00U, + ADC_TRIG_SRC_PWM_CMP0 = 0x08U, + ADC_TRIG_SRC_PWM_CMP1 = 0x09U, + ADC_TRIG_SRC_PWM_PCC3_1 = 0x0AU, + ADC_TRIG_SRC_PWM_CT6OUT = 0x0BU, + ADC_TRIG_SRC_PWM_CT3OUT = 0x0CU, + ADC_TRIG_SRC_GT1ADCTRIG = 0x0DU, + ADC_TRIG_SRC_GT2ADCTRIG = 0x0EU, + ADC_TRIG_SRC_GT3ADCTRIG = 0x0FU +}AdcGeneralTriggerSRC_t; + + +typedef enum { + ADC_AFE_GAIN_22_OF_32 = 0U, + ADC_AFE_GAIN_31_OF_32, +}AdcAfeGain_t; + +typedef enum { + ADC_AFE_INPUT_ALL_EXT = 0U, + ADC_AFE_INPUT_INP_BUFFERED_INN_EXT, + ADC_AFE_INPUT_INP_EXT_INN_BUFFERED, + ADC_AFE_INPUT_INP_BUFFERED_INN_BUFFERED, +}AdcAfeInputMode_t; + +typedef enum { + ADC_CH_SEL_NONE = 0U, + ADC_CH_SEL_REF_REF, + ADC_CH_SEL_REF_GND, + ADC_CH_SEL_GND_REF, + ADC_CH_SEL_TSENSOR_GND, + ADC_CH_SEL_1V5_GND, + ADC_CH_SEL_3V3_GND, /* 1/2 gain */ + ADC_CH_SEL_5V0_GND, /* 1/4 gain */ + ADC_CH_SEL_VBAT_GND, /* 1/14 gain */ + ADC_CH_SEL_CSA_Filter_OUT_GND, + ADC_CH_SEL_CSA_OUT_GND, + ADC_CH_SEL_PA2_GND, + ADC_CH_SEL_PA3_GND, + ADC_CH_SEL_PA4_GND, + ADC_CH_SEL_PA5_GND, + ADC_CH_SEL_PA6_GND, + ADC_CH_SEL_PC3_GND, + ADC_CH_SEL_PC4_GND, + ADC_CH_SEL_PB0_GND, + ADC_CH_SEL_PB1_GND, + ADC_CH_SEL_PB2_GND, + ADC_CH_SEL_PB3_GND, + ADC_CH_SEL_PB4_GND, + ADC_CH_SEL_PB5_GND, + ADC_CH_SEL_PB6_GND, + ADC_CH_SEL_PB7_GND, + ADC_CH_SEL_3V3_EXT_GND, /* 1/2 gain */ +}AdcChannelSelect_t; + + +typedef enum { + ADC_SQ_CH1_2_CH1 = 1U, + ADC_SQ_CH1_2_CH2 = 2U, + ADC_SQ_CH1_2_CH3 = 3U, + ADC_SQ_CH1_2_CH4 = 4U, + ADC_SQ_CH1_2_CH5 = 5U, + ADC_SQ_CH1_2_CH6 = 6U, + ADC_SQ_CH1_2_CH7 = 7U, + ADC_SQ_CH1_2_CH8 = 8U, + ADC_SQ_CH1_2_CH9 = 9U, + ADC_SQ_CH1_2_CH10= 10U +}AdcSequence_t; + + +typedef enum { + ADC_MEASURE_ITEM_NONE = 0U, + ADC_MEASURE_ITEM_VBG, + ADC_MEASURE_ITEM_VBAT, + ADC_MEASURE_ITEM_VDD1V5, + ADC_MEASURE_ITEM_VAMP, + ADC_MEASURE_ITEM_VBAT_VTEMP, + ADC_MEASURE_ITEM_PC3, + ADC_MEASURE_ITEM_LED, +}AdcMeasureItem_t; + +typedef struct{ + AdcMeasureItem_t item; + uint8_t channel; +}ADCMeasureParam_t; + + +//typedef struct{ +// AdcTriggerSEL_t selection; +// union{ +// AdcGeneralTriggerSRC_t general; +// AdcPwmAuxTriggerSRC_t pwmAux; +// }; +// AdcPwmAuxChannel_t channel; /* Only for pwm aux */ +//}ADCTriggerParam_t; + +typedef struct{ + AdcTriggerSEL_t selection; + AdcGeneralTriggerSRC_t general; + AdcPwmAuxTriggerSRC_t pwmAux; + AdcPwmAuxChannel_t channel; /* Only for pwm aux */ +}ADCTriggerParam_t; + +typedef void (*adc_cb_func_t)(ADCMeasureParam_t item, uint16_t *const result); + +uint16_t getcurrent(void); +uint16_t getpb3code(void); +uint16_t getpc4code(void); +uint16_t getpb4code(void); +uint8_t getgai(void); +void ADC_GeneralInit(void); +void ADC_Init(AdcMeasureItem_t item, uint8_t channel); +void ADC_UnInit(AdcMeasureItem_t item); +void ADC_RegisterIRQ(adc_cb_func_t callback); +void ADC_UnregisterIRQ(void); +void ADC_Start(void); +void ADC_Stop(void); +ADCMeasureParam_t ADC_GetadcMeasParamm(void); + +#endif /* __ADC_DEVICE_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/atomic.h b/app_Indie/drivers/hal/inc/atomic.h new file mode 100644 index 0000000..003c0ce --- /dev/null +++ b/app_Indie/drivers/hal/inc/atomic.h @@ -0,0 +1,21 @@ +#ifndef _ATOMIC_H +#define _ATOMIC_H + +#include + +typedef uint32_t atomic_t; +/****************************************************************************** + Disables global interrupt. Enter atomic section. +******************************************************************************/ +void halStartAtomic(atomic_t volatile *pAtomic); +/****************************************************************************** + Exit atomic section +******************************************************************************/ +void halEndAtomic(atomic_t volatile *pAtomic); +/** \brief Marks the begin of atomic section */ +#define __atomic_enter() __disable_irq(); +/** \brief Marks the end of atomic section */ +#define __atomic_exit() __enable_irq(); + +#endif + diff --git a/app_Indie/drivers/hal/inc/clock_device.h b/app_Indie/drivers/hal/inc/clock_device.h new file mode 100644 index 0000000..7e443ca --- /dev/null +++ b/app_Indie/drivers/hal/inc/clock_device.h @@ -0,0 +1,37 @@ +/** + * @copyright 2016 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file clock_device.h + */ + +#ifndef CLOCK_DEVICE_H__ +#define CLOCK_DEVICE_H__ + +#include +#include +#include + +typedef enum{ + CLOCK_RC_16KHz = 0U, + CLOCK_RC_16MHz +}ClockSource_t; + + +#define CLOCK_LF_RC_16KHz (0U) +#define CLOCK_LF_RC_256KHz (1U) + +#define CLOCK_DIV_1 (0U) +#define CLOCK_DIV_2 (1U) +#define CLOCK_DIV_4 (3U) + +#define CLOCK_DIV_8 (7U) + +void Clock_SystemMainClockInit(uint8_t divider); +uint32_t Clock_GetSystemClock(void); + +#endif /* __CLOCK_DEVICE_H__ */ diff --git a/app_Indie/drivers/hal/inc/crc32_device.h b/app_Indie/drivers/hal/inc/crc32_device.h new file mode 100644 index 0000000..a64ee62 --- /dev/null +++ b/app_Indie/drivers/hal/inc/crc32_device.h @@ -0,0 +1,45 @@ +#ifndef CRC32_DEVICE_H__ +#define CRC32_DEVICE_H__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/errno.h b/app_Indie/drivers/hal/inc/errno.h new file mode 100644 index 0000000..5b59ca2 --- /dev/null +++ b/app_Indie/drivers/hal/inc/errno.h @@ -0,0 +1,21 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file errno.h + */ + +#ifndef ERRNO_H__ +#define ERRNO_H__ + +#define EPERM 1U /*!< Operation not permitted */ +#define EAGAIN 2U /*!< Try again */ +#define EFAULT 3U /*!< Bad address */ +#define EBUSY 4U /*!< Device or resource busy */ +#define ENODEV 5U /*!< No such device */ +#define ETIMEOUT 6U /*!< Time out */ +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/flash_device.h b/app_Indie/drivers/hal/inc/flash_device.h new file mode 100644 index 0000000..2f68061 --- /dev/null +++ b/app_Indie/drivers/hal/inc/flash_device.h @@ -0,0 +1,34 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file flash_device.h + */ + +#ifndef FLASH_DEVICE_H__ +#define FLASH_DEVICE_H__ + +#include + +/** + * @brief Erase a sector flash memory and wait for completion + * + * @param addr: starting address of the block + * @return none + */ +void Flash_EraseSector(uint32_t sectorAddress); + +/** + * @brief write flash memory and wait for completion + * + * @param addr: starting address of the data + * @return none + */ +void FLASH_Write2WordsWithECC(uint32_t address,uint32_t dataL,uint32_t dataH); + + +#endif /* __FLASH_DEVICE_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/gpio_device.h b/app_Indie/drivers/hal/inc/gpio_device.h new file mode 100644 index 0000000..c202875 --- /dev/null +++ b/app_Indie/drivers/hal/inc/gpio_device.h @@ -0,0 +1,89 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file gpio_device.h + */ + +#ifndef GPIO_DEVICE_H__ +#define GPIO_DEVICE_H__ + +#include +#include +#include +#include +#include "errno.h" + +/* for IO control*/ +typedef enum{ + GPIO_PORT_0 = 0U, + GPIO_PORT_1, + GPIO_PORT_2, + GPIO_PORT_3, + GPIO_PORT_4, + GPIO_PORT_5, + GPIO_PORT_6, + GPIO_PORT_7, +}GpioPort_t; + +/* for IO init*/ +typedef enum{ + GROUP_GPIOA = 0, + GROUP_GPIOB, + GROUP_GPIOC, +}GpioGroup_t; + + +typedef enum{ + GPIO_DIR_INPUT = 0U, + GPIO_DIR_OUTPUT, +}GpioDir_t; + +/* 01: pull none, 00: pull up, 11: pull down, 10: pull up and down*/ +typedef enum{ + GPIO_PULL_UP = 0U, + GPIO_PULL_NONE = 1U, + GPIO_PULL_UP_DOWN = 2U, + GPIO_PULL_DOWN = 3U, +}GpioPullMode_t; + +typedef enum{ + GPIO_LOW = 0U, + GPIO_HIGH, +}GpioSetState_t; + +typedef enum{ + GPIO_MUX_GPIO = 0U, + GPIO_MUX_PWM, +}GpioMuxMode_t; + + +typedef enum{ + GPIO_PWM_CH1 = 0U, + GPIO_PWM_CH2, + GPIO_PWM_NONE, +}GpioPWMchannel_t; + +/* 00: disable, 01: rising, 10: falling, 11: both */ +typedef enum{ + GPIO_EDGE_NODE = 0U, + GPIO_EDGE_RISING, + GPIO_EDGE_FALLING, + GPIO_EDGE_BOTH, +}GpioISREdge_t; + + +typedef void (*gpio_cb_func_t)(void); + + +void GPIO_Init(GpioGroup_t group,GpioPort_t port, GpioDir_t dir,GpioPullMode_t pullMode); +void GPIO_RegisterIRQ(GpioGroup_t group,GpioPort_t port, GpioISREdge_t edge, gpio_cb_func_t callback); +void GPIO_UnRegisterIRQ(GpioGroup_t group,GpioPort_t port); +void GPIO_Set(GpioGroup_t group,GpioPort_t port, GpioSetState_t state); +uint8_t GPIO_Read(GpioGroup_t group,GpioPort_t port); + +#endif /* __GPIO_DEVICE_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/gtimer_device.h b/app_Indie/drivers/hal/inc/gtimer_device.h new file mode 100644 index 0000000..fded953 --- /dev/null +++ b/app_Indie/drivers/hal/inc/gtimer_device.h @@ -0,0 +1,60 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file timer_device.h + */ + +#ifndef TIMER_DEVICE_H__ +#define TIMER_DEVICE_H__ + +#include +#include + +/* Timer 2 have been used by lin stack ,please don't use !!! */ +#define HW_GP_TIMER_NUM 3U +typedef enum{ + TIMER0 = 0U, + TIMER1 = 1U, + TIMER2 = 2U, +}HwGpTimerId_t; + +typedef enum{ + GTIMER_CLK_DIV_1 = 0U, + GTIMER_CLK_DIV_2, + GTIMER_CLK_DIV_4, + GTIMER_CLK_DIV_8, + GTIMER_CLK_DIV_16, + GTIMER_CLK_DIV_32, + GTIMER_CLK_DIV_64, + GTIMER_CLK_DIV_256, + GTIMER_CLK_DIV_1024, + GTIMER_CLK_DIV_2048, + GTIMER_CLK_DIV_4096, +}GTimer_Prescaler_t; + + +typedef enum GlobalTimerMode_t{ + HW_TIMER_PERIODIC_MODE = 0U, + HW_TIMER_ONE_SHOT_MODE, +} HwGpTimeMode_t; + +typedef void (*TimeoutCallbackFunc_t)(void); + +typedef struct{ + /* Timer parameters */ + uint32_t timeReloadCnt; + uint32_t periodCount; + HwGpTimeMode_t mode; + TimeoutCallbackFunc_t handler; +} HwGpTimer_t; + + +void TIMER_Init(HwGpTimerId_t timerId, HwGpTimeMode_t mode, GTimer_Prescaler_t prescale, uint16_t timeoutTicks, TimeoutCallbackFunc_t callback); +void TIMER_Disable(HwGpTimerId_t timerId); + +#endif /* __TIMER_DEVICE_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/hwProtection.h b/app_Indie/drivers/hal/inc/hwProtection.h new file mode 100644 index 0000000..ce8409b --- /dev/null +++ b/app_Indie/drivers/hal/inc/hwProtection.h @@ -0,0 +1,148 @@ +#ifndef __HW_PROTECTION_H__ +#define __HW_PROTECTION_H__ +#include +#include + + +typedef enum{ + OVT_PROT_93C = 0, + OVT_PROT_98C, + OVT_PROT_104C, + OVT_PROT_109C, + OVT_PROT_115C, + OVT_PROT_121C, + OVT_PROT_127C, + OVT_PROT_133C, + OVT_PROT_139C, + OVT_PROT_146C, + OVT_PROT_153C, + OVT_PROT_160C, + OVT_PROT_168C, + OVT_PROT_176C, + OVT_PROT_185C, +}OverTempThres_t; + +typedef enum{ + OVT_ACTION_HW_RESET = 0, + OVT_ACTION_NONE, +}OverTempAction_t; + +typedef enum{ + OV_VOLT_14_7V = 0U, + OV_VOLT_15_2V, + OV_VOLT_15_6V, + OV_VOLT_16_4V, + OV_VOLT_16_8V, + OV_VOLT_17_6V, + OV_VOLT_18_3V, + OV_VOLT_19_0V, + OV_VOLT_20_0V, + OV_VOLT_20_7V, +}OverVoltThres_t; + +typedef enum{ + OV_VOLT_HYS_360mV = 0U, + OV_VOLT_HYS_720mV, + OV_VOLT_HYS_1080mV, + OV_VOLT_HYS_1440mV, +}OverVoltHysteresis_t; + + +typedef enum{ + UV_VOLT_4_6V = 0x0, + UV_VOLT_4_7V, + UV_VOLT_5_1V, + UV_VOLT_5_2V, + UV_VOLT_5_061V, + UV_VOLT_5_140V, + UV_VOLT_5_221V, + UV_VOLT_5_305V, + UV_VOLT_5_392V, + UV_VOLT_5_482V, + UV_VOLT_5_574V, + UV_VOLT_5_670V, + UV_VOLT_5_770V, + UV_VOLT_5_872V, + UV_VOLT_5_979V, + UV_VOLT_6_089V, + UV_VOLT_6_204V, + UV_VOLT_6_323V, + UV_VOLT_6_447V, + UV_VOLT_6_575V, + UV_VOLT_6_709V, + UV_VOLT_6_849V, + UV_VOLT_6_994V, + UV_VOLT_7_146V, + UV_VOLT_7_304V, + UV_VOLT_7_470V, + UV_VOLT_7_643V, + UV_VOLT_7_825V, + UV_VOLT_8_015V, + UV_VOLT_8_215V, + UV_VOLT_8_425V, + UV_VOLT_8_646V, + UV_VOLT_8_879V, + UV_VOLT_9_125V, + UV_VOLT_9_385V, + UV_VOLT_9_660V, + UV_VOLT_9_952V, + UV_VOLT_10_26V, + UV_VOLT_10_59V, + UV_VOLT_10_94V, +}UnderVoltThres_t; + +typedef enum{ + UNDER_VOLT_HYS_470mV = 0U, + UNDER_VOLT_HYS_830mV, + UNDER_VOLT_HYS_1220mV, + UNDER_VOLT_HYS_1630mV, +}UnderVoltHysteresis_t; + + +typedef enum{ + VOLT_DEBOUNCE_TIME_0ms = 0U, + VOLT_DEBOUNCE_TIME_1ms = 16U, + VOLT_DEBOUNCE_TIME_2ms = 32U, + VOLT_DEBOUNCE_TIME_3ms = 48U, + VOLT_DEBOUNCE_TIME_4ms = 64U, + VOLT_DEBOUNCE_TIME_5ms = 80U, + VOLT_DEBOUNCE_TIME_6ms = 96U, + VOLT_DEBOUNCE_TIME_7ms = 112U, + VOLT_DEBOUNCE_TIME_8ms = 128U, + VOLT_DEBOUNCE_TIME_9ms = 144U, + VOLT_DEBOUNCE_TIME_10ms = 160U, + VOLT_DEBOUNCE_TIME_11ms = 176U, + VOLT_DEBOUNCE_TIME_12ms = 192U, + VOLT_DEBOUNCE_TIME_13ms = 208U, + VOLT_DEBOUNCE_TIME_14ms = 224U, + VOLT_DEBOUNCE_TIME_15ms = 240U, +}VoltDebouceTime_t; + + + + + +typedef void (*hwProtIsrCallback_t)(void); + + +void HW_PROT_SetOverTmperature(OverTempThres_t threshold, OverTempAction_t action); +void HW_PROT_RegisterOVTemperatureIRQ(hwProtIsrCallback_t callback); +void HW_PROT_UnRegisterOVTemperatureIRQ(void); + +void HW_PROT_SetOverVoltage(OverVoltThres_t threshold,OverVoltHysteresis_t hys, VoltDebouceTime_t triggerTime, VoltDebouceTime_t releaseTime); +void HW_PROT_RegisterOverVoltageIRQ(hwProtIsrCallback_t callback); +void HW_PROT_UnRegisterOverVoltageIRQ(void); + +void HW_PROT_SetUnderVoltage(UnderVoltThres_t threshold,UnderVoltHysteresis_t hys, VoltDebouceTime_t triggerTime, VoltDebouceTime_t releaseTime); +void HW_PROT_RegisterUnderVoltageIRQ(hwProtIsrCallback_t callback); +void HW_PROT_UnRegisterUnderVoltageIRQ(void); + +/* return 0: normal , 1: low, 2:high */ +uint8_t HW_PROT_GetBattVoltState(void); +/* return 0: normal , others : over heat */ +uint8_t HW_PROT_ChipIsOverHeat(void); + + + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/lin_device.h b/app_Indie/drivers/hal/inc/lin_device.h new file mode 100644 index 0000000..54557af --- /dev/null +++ b/app_Indie/drivers/hal/inc/lin_device.h @@ -0,0 +1,153 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file lin_device.h + */ + +#ifndef LIN_DEVICE_H__ +#define LIN_DEVICE_H__ + +#include +#include +#include +#include "lins_sfr.h" + +#define E_LIN_STATUS_COMPLETE (1U << 0) +#define E_LIN_STATUS_WAKEUP (1U << 1) +#define E_LIN_STATUS_ERROR (1U << 2) +#define E_LIN_STATUS_INT_REQ (1U << 3) +#define E_LIN_STATUS_DATA_REQ (1U << 4) +#define E_LIN_STATUS_ABORT (1U << 5) +#define E_LIN_STATUS_IDLE_TIMEOUT (1U << 6) +#define E_LIN_STATUS_ACTIVE (1U << 7) + +#define E_LIN_ERROR_BIT (1U << 0) +#define E_LIN_ERROR_CHECKSUM (1U << 1) +#define E_LIN_ERROR_TIMEOUT (1U << 2) +#define E_LIN_ERROR_PARITY (1U << 3) + + +#define E_LIN_TIME_INACTIVE_SEC_4 (0U) +#define E_LIN_TIME_INACTIVE_SEC_6 (1U) +#define E_LIN_TIME_INACTIVE_SEC_8 (2U) +#define E_LIN_TIME_INACTIVE_SEC_10 (3U) +#define E_LIN_TIME_INACTIVE_MAX (3U) /*E_LIN_TIME_INACTIVE_SEC_10*/ + +#define E_LIN_TIME_WAKEUP_REPEAT_MS_180 (0U) +#define E_LIN_TIME_WAKEUP_REPEAT_MS_200 (1U) +#define E_LIN_TIME_WAKEUP_REPEAT_MS_220 (2U) +#define E_LIN_TIME_WAKEUP_REPEAT_MS_240 (3U) +#define E_LIN_TIME_WAKEUP_REPEAT_MAX (3U)/*E_LIN_TIME_WAKEUP_REPEAT_MS_240*/ + + +#define LIN_RX_FILTER_2_3_us (0U)/* LINS_RX_BIAS_BOOST */ +#define LIN_RX_FILTER_1_3_us (1U) +#define LIN_RX_FILTER_1_0_us (2U) +#define LIN_RX_FILTER_0_8_us (3U) + +#define LIN_TX_DRIVE_CURRENT_32_mA (0U)/* pull down capacity */ +#define LIN_TX_DRIVE_CURRENT_48_mA (1U) +#define LIN_TX_DRIVE_CURRENT_66_mA (2U) +#define LIN_TX_DRIVE_CURRENT_88_mA (3U) +#define LIN_TX_DRIVE_CURRENT_101_mA (4U) +#define LIN_TX_DRIVE_CURRENT_118_mA (5U) +#define LIN_TX_DRIVE_CURRENT_135_mA (6U) +#define LIN_TX_DRIVE_CURRENT_151_mA (7U) + +#define LIN_TX_SLEW_RATE_0_6V_PER_US (1U)/* Slew from 40%*Vbat to 60%*Vbat @Vbat=13V,Cbus=1nF */ +#define LIN_TX_SLEW_RATE_1_2V_PER_US (2U) +#define LIN_TX_SLEW_RATE_1_7V_PER_US (3U) +#define LIN_TX_SLEW_RATE_2_3V_PER_US (4U) +#define LIN_TX_SLEW_RATE_2_8V_PER_US (5U) +#define LIN_TX_SLEW_RATE_3_4V_PER_US (6U) +#define LIN_TX_SLEW_RATE_5_1V_PER_US (7U) + + +#define LIN_BUFF_SIZE 8U + +/* Defines for LIN device to handle message direction. */ +typedef enum{ + LIN_MSG_TYPE_RX = 0U, /*received data from sender for slave; */ + LIN_MSG_TYPE_TX, /*data request from sender for slave; */ + LIN_MSG_TYPE_TX_EVENT, /*event trigger data request from sender for slave; */ +}LinMessageType_t; + + +typedef enum{ + E_LIN_BAUDRATE_10417, + E_LIN_BAUDRATE_19200, + E_LIN_BAUDRATE_20000, +}LIN_BaudRate_t; + +#define E_LIN_BAUDRATE_MAX (3U)/*E_LIN_BAUDRATE_20000*/ + + +typedef enum{ + LIN_CHECKSUM_CLASSIC = 0U, /*!< classic checksum does not include ID Byte. */ + LIN_CHECKSUM_ENHANCED /*!< "enhanced" checksum includes ID Byte. */ +}ChecksumType_t; + + +typedef enum{ + AA_SWITCH_OFF = 0U, + AA_SWITCH_ON, +}AutoaddressingSwitchState_t; + +/** +* @brief A structure to represent LIN frame information. +*/ +typedef struct { + uint8_t frameTobeHandled :1; /*!< frame ID waiting to be handled */ + uint8_t reverved :7; + uint8_t frame_id; /*!< frame ID. */ + uint8_t msg_type :2; /*!< Type of message,LinMessageType_t rx,tx or event trigger. */ + uint8_t checksum :1; /*!< Type of checksum (enhanced or classic). */ + uint8_t length :5; /*!< Number of bytes in the data. */ + + uint8_t responseValid :1; + uint8_t frameIsValid :1; + uint8_t eventTriggered :1; /*!< event triggered when the msg_type is LIN_MSG_TYPE_TX_EVENT */ + uint8_t linkedEventTriggerFidTableIndex :5; /*!< event triggered when the msg_type is LIN_MSG_TYPE_TX_EVENT */ + + union{ + uint8_t data[LIN_BUFF_SIZE]; /*!< data buffer. */ + uint16_t data16[LIN_BUFF_SIZE/2]; + uint32_t data32[LIN_BUFF_SIZE/4]; + uint64_t data64; + }; +} LIN_Device_Frame_t; + + + +typedef void (*lin_cb_func_t)(LIN_Device_Frame_t const *frame); +typedef void (*lin_stack_cb_func_t)(void); +typedef void (*lin_wakeup_cb_func_t)(void); + +void LINS_Init(void); +void LINS_SetSlaveModuleToSleep(void); +void LINS_RegisterLINStack_IRQ(lin_stack_cb_func_t callback,lin_wakeup_cb_func_t wakeupCallback); + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_PRIVATE + +typedef void (*ls_DataReqCallback_t)(LIN_Device_Frame_t const *frame); +typedef void (*ls_DataRspCallback_t)(LIN_Device_Frame_t *const frame); +typedef void (*ls_SleepReqCallback_t)(void); + +typedef struct{ + ls_DataReqCallback_t dataReqCallback; /* received data from master */ + ls_DataRspCallback_t dataRspCallback; /* send data to master */ + ls_SleepReqCallback_t sleepReqCallback; +}ls_LinsPrivateFramesCallback_t; + +void LINS_RegisterPrivateServices(LIN_Device_Frame_t *frameTable, uint8_t tableSize, const ls_LinsPrivateFramesCallback_t *pFunCallback); +uint8_t getmotorrun(void); +uint16_t getposition(void); +#endif + + +#endif /* __LIN_DEVICE_H__ */ diff --git a/app_Indie/drivers/hal/inc/math_div_device.h b/app_Indie/drivers/hal/inc/math_div_device.h new file mode 100644 index 0000000..646b5dd --- /dev/null +++ b/app_Indie/drivers/hal/inc/math_div_device.h @@ -0,0 +1,39 @@ +#ifndef MATH_DIV_DEVICE_H__ +#define MATH_DIV_DEVICE_H__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/pmu_device.h b/app_Indie/drivers/hal/inc/pmu_device.h new file mode 100644 index 0000000..40a27d7 --- /dev/null +++ b/app_Indie/drivers/hal/inc/pmu_device.h @@ -0,0 +1,122 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pmu_device.h + */ + +#ifndef PMU_DEVICE_H__ +#define PMU_DEVICE_H__ + +#include +#include +#include +#include +#include + +typedef enum{ + POLARITY_NATIVE = 0, + POLARITY_FLIP, +}BattMonitorPolarity_t; + + +typedef enum{ + S_BOR_1P5V = 0, + BOR_1V5_THRS_1328mV, + BOR_1V5_THRS_1358mV, + BOR_1V5_THRS_1393mV, + BOR_1V5_THRS_1423mV, + BOR_1V5_THRS_1463mV, +}Bor1V5Thres_t; + + +typedef enum{ + BOR_3V3_THRS_2163mV = 0, + BOR_3V3_THRS_2228mV, + BOR_3V3_THRS_2292mV, + BOR_3V3_THRS_2363mV, + BOR_3V3_THRS_2433mV, + BOR_3V3_THRS_2513mV, + BOR_3V3_THRS_2598mV, + BOR_3V3_THRS_2688mV, + BOR_3V3_THRS_2783mV, + BOR_3V3_THRS_2883mV, + BOR_3V3_THRS_2998mV, + BOR_3V3_THRS_3118mV, + BOR_3V3_THRS_3248mV, +}Bor3V3Thres_t; + +/** + * @brief The enumeration of brownout mode. + */ +typedef enum { + PMU_BROWNOUT_RESET = 0U, + PMU_BROWNOUT_INTERRUPT, + PMU_BROWNOUT_NONE, +} PMU_BROWNOUT_MODE_t; + +/** + * @brief The enumeration of wake up timer mode. + */ +typedef enum { + WAKEUP_TIMEER_DISABLE = 0U, + WAKEUP_TIMEER_ENABLE, +} PMU_WAKEUP_TIMEER_MODE_t; + +/** + * @brief The enumeration of wake up timer mode. + */ +typedef enum { + WAKEUP_TIMEER_INTERVAL_100us = 0U, + WAKEUP_TIMEER_INTERVAL_200us, + WAKEUP_TIMEER_INTERVAL_400us, + WAKEUP_TIMEER_INTERVAL_800us, + WAKEUP_TIMEER_INTERVAL_16ms, + WAKEUP_TIMEER_INTERVAL_32ms, + WAKEUP_TIMEER_INTERVAL_64ms, + WAKEUP_TIMEER_INTERVAL_128ms, + WAKEUP_TIMEER_INTERVAL_256ms, + WAKEUP_TIMEER_INTERVAL_512ms, + WAKEUP_TIMEER_INTERVAL_1024ms, + WAKEUP_TIMEER_INTERVAL_2048ms, + WAKEUP_TIMEER_INTERVAL_4096ms, + WAKEUP_TIMEER_INTERVAL_8192ms, + WAKEUP_TIMEER_INTERVAL_16384ms, + WAKEUP_TIMEER_INTERVAL_32768ms +} PMU_WAKEUP_TIMEER_Interval_t; + + + + +#define MODUE_SOFT_RESET_ADC (0x001U) +#define MODUE_SOFT_RESET_PWM (0x002U) +#define MODUE_SOFT_RESET_CTT (0x004U) +#define MODUE_SOFT_RESET_GTM (0x008U) +#define MODUE_SOFT_RESET_SPIM (0x010U) +#define MODUE_SOFT_RESET_UART (0x011U) +#define MODUE_SOFT_RESET_MATHDIV (0x012U) +#define MODUE_SOFT_RESET_CRC (0x014U) +#define MODUE_SOFT_RESET_PWM_AUX (0x018U) +#define MODUE_SOFT_RESET_LINS (0x020U) + + + + + + + + + + +void PMU_BORInit(Bor1V5Thres_t lowThreshold, Bor3V3Thres_t highThreshold); +void PMU_WakeTimerInit(PMU_WAKEUP_TIMEER_MODE_t mode, PMU_WAKEUP_TIMEER_Interval_t interval); +void PMU_EnterDeepSleepMode(void); + + + + +#endif /* __PMU_DEVICE_H__ */ diff --git a/app_Indie/drivers/hal/inc/pwm_aux_device.h b/app_Indie/drivers/hal/inc/pwm_aux_device.h new file mode 100644 index 0000000..7368966 --- /dev/null +++ b/app_Indie/drivers/hal/inc/pwm_aux_device.h @@ -0,0 +1,45 @@ +#ifndef PWM_AUX_DEVICE_H__ +#define PWM_AUX_DEVICE_H__ + +#include +#include +#include +#include + +typedef void (*PwmAuxIsrCallback_t)(void); + +typedef enum{ + PWMAUX_CH0 = 0U, + PWMAUX_CH1 = 1U, + PWMAUX_CH2 = 2U, + PWMAUX_CH3 = 3U, + PWMAUX_CH4 = 4U, + PWMAUX_CH5 = 5U, +}PWMAUX_CH_t; + + +typedef enum{ + PWMAUX_BASE_0 = 0U, + PWMAUX_BASE_1, +}PWMAUX_ClockSource_t; + + +typedef enum{ + PWMAUX_CLK_DIV_1 = 0U, + PWMAUX_CLK_DIV_2, + PWMAUX_CLK_DIV_4, + PWMAUX_CLK_DIV_8, + PWMAUX_CLK_DIV_16, + PWMAUX_CLK_DIV_64, + PWMAUX_CLK_DIV_256, + PWMAUX_CLK_DIV_1024, +}PWMAUX_Prescaler_t; + + +void PWMAUX_Init(GpioGroup_t group,GpioPort_t port,PWMAUX_CH_t channel,PWMAUX_ClockSource_t source,PWMAUX_Prescaler_t divider,uint16_t peroid); +void PWMAUX_RegisterReloadIRQ(PWMAUX_ClockSource_t source, PwmAuxIsrCallback_t callback); +void PWMAUX_UnRegisterReloadIRQ(PWMAUX_ClockSource_t source); +void PWMAUX_SetMatchValue(PWMAUX_CH_t channel, uint16_t matchRisingValue, uint16_t matchFaillValue); + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/pwm_device.h b/app_Indie/drivers/hal/inc/pwm_device.h new file mode 100644 index 0000000..0b66692 --- /dev/null +++ b/app_Indie/drivers/hal/inc/pwm_device.h @@ -0,0 +1,67 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pwm_device.h + */ + +#ifndef PWM_DEVICE_H__ +#define PWM_DEVICE_H__ + +#include +#include +#include +#include +#include + +typedef enum{ + PWM_CH0_0 = 0U, + PWM_CH0_1 = 1U, + PWM_CH1_0 = 2U, + PWM_CH1_1 = 3U, + PWM_CH2_0 = 4U, + PWM_CH2_1 = 5U, + PWM_CH3_0 = 6U, + PWM_CH3_1 = 7U, +}PWM_CH_t; + +typedef enum{ + PWM_BASE_0 = 0U, + PWM_BASE_1, +}PWM_ClockSource_t; + +typedef enum{ + PWM_CLK_DIV_1 = 0U, + PWM_CLK_DIV_2, + PWM_CLK_DIV_4, + PWM_CLK_DIV_8, + PWM_CLK_DIV_16, + PWM_CLK_DIV_32, + PWM_CLK_DIV_64, + PWM_CLK_DIV_128, + PWM_CLK_DIV_256, + PWM_CLK_DIV_512, + PWM_CLK_DIV_1024, + PWM_CLK_DIV_2048, + PWM_CLK_DIV_4096, + PWM_CLK_DIV_8192, + PWM_CLK_DIV_16384, + PWM_CLK_DIV_32768, +}PWM_Prescaler_t; + +typedef enum{ + PULSE_0 = 0U, + PULSE_1, + PULSE_2, + PULSE_3, +}PWM_Pulse_t; + +void PWM_Init(GpioGroup_t group,GpioPort_t port,PWM_CH_t channel,PWM_ClockSource_t source,PWM_Prescaler_t divider,uint16_t peroid); +void PWM_SetMatchValue(PWM_ClockSource_t source,PWM_Pulse_t pulse,uint16_t matchRisingValue, uint16_t matchFaillValue); +void PWM_Listofotherparameters_Init(void); + +#endif /* __PWM_DEVICE_H__ */ \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/spi_device.h b/app_Indie/drivers/hal/inc/spi_device.h new file mode 100644 index 0000000..6994958 --- /dev/null +++ b/app_Indie/drivers/hal/inc/spi_device.h @@ -0,0 +1,35 @@ +#ifndef SPI_DEVICE_H__ +#define SPI_DEVICE_H__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/systick_device.h b/app_Indie/drivers/hal/inc/systick_device.h new file mode 100644 index 0000000..5f6459d --- /dev/null +++ b/app_Indie/drivers/hal/inc/systick_device.h @@ -0,0 +1,49 @@ +/** + * @copyright 2016 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file systick_device.h + */ + +#ifndef SYSTICK_DEVICE_H +#define SYSTICK_DEVICE_H + +#include + +typedef void (*sysTick_cb_func_t)(void); + + +void SysTick_Init(uint32_t ticks, sysTick_cb_func_t callback); +uint32_t SysTick_GetCount(void); +uint32_t SysTick_GetLoad(void); + + + + + + + + + + + + + + + + + + + + + + + + + +#endif /* ___SYSTICK_DEVICE_H__ */ + diff --git a/app_Indie/drivers/hal/inc/uart_device.h b/app_Indie/drivers/hal/inc/uart_device.h new file mode 100644 index 0000000..7d816f2 --- /dev/null +++ b/app_Indie/drivers/hal/inc/uart_device.h @@ -0,0 +1,43 @@ +#ifndef UART_DEVICE_H__ +#define UART_DEVICE_H__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/inc/wdt_device.h b/app_Indie/drivers/hal/inc/wdt_device.h new file mode 100644 index 0000000..8b452d2 --- /dev/null +++ b/app_Indie/drivers/hal/inc/wdt_device.h @@ -0,0 +1,62 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file wdt_device.h + */ + +#ifndef WDT_DEVICE_H__ +#define WDT_DEVICE_H__ + +#include +#include +#include +#include "errno.h" + + +typedef void (*wdt_cb_func_t)(void); + +typedef enum{ + WDT1_INTERVAL_E13 = 0U,/*0x0: 2^13 / System Clock 512us @16MHz*/ + WDT1_INTERVAL_E19, /*0x1: 2^19 / System Clock 32768us @16MHz*/ + WDT1_INTERVAL_E22, /*0x2: 2^22 / System Clock 262144us @16MHz*/ + WDT1_INTERVAL_E32, /*0x3: 2^32 / System Clock 268seconds @@16MHz*/ +}WDT1Interval_t; + +typedef enum{ + WDT1_MODE_RESET = 0U, + WDT1_MODE_INTERRUPT +}WDT1Mode_t; + +void WDT1_Enable(WDT1Mode_t mode, WDT1Interval_t interval, wdt_cb_func_t callback); +void WDT1_Clear(void); + +typedef enum{ + WDTA_INTERVAL_144MS = 0U,/*0x0: 2^11 * 62.5us ~= 128*(1+1/8) ms*/ + WDTA_INTERVAL_288MS, /*0x2: 2^12 * 62.5us ~= 256*(1+1/8) ms*/ + WDTA_INTERVAL_576MS, /*0x3: 2^13 * 62.5us ~= 512*(1+1/8) ms*/ + WDTA_INTERVAL_1152MS, /*0x4: 2^14 * 62.5us ~= 1.0*(1+1/8) s*/ + WDTA_INTERVAL_2304MS, /*0x5: 2^15 * 62.5us ~= 2.0*(1+1/8) s*/ + WDTA_INTERVAL_4608MS, /*0x6: 2^16 * 62.5us ~= 4.0*(1+1/8) s*/ + WDTA_INTERVAL_9216MS, /*0x7: 2^17 * 62.5us ~= 8.0*(1+1/8) s*/ + WDTA_INTERVAL_18432MS, /*0x7: 2^18 * 62.5us ~= 16.0*(1+1/8)s*/ +}WDTAInterval_t; + +typedef enum{ + WDTA_MODE_RESET = 0U, +}WDTAMode_t; + + +void WDTA_Enable(WDTAInterval_t interval); +void WDTA_Disable(void); +void WDTA_Clear(void); + + + + +#endif /* __WDT_DEVICE_H__ */ + diff --git a/app_Indie/drivers/hal/src/adc_device.c b/app_Indie/drivers/hal/src/adc_device.c new file mode 100644 index 0000000..ad7e5ee --- /dev/null +++ b/app_Indie/drivers/hal/src/adc_device.c @@ -0,0 +1,201 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file adc_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include +#include + +static ADCMeasureParam_t adcMeasParamm = {ADC_MEASURE_ITEM_NONE, 0}; +static adc_cb_func_t adcCallback = NULL; +static uint16_t adcResult[10]; + +void ADC_Handler(void) +{ + if (adcCallback !=NULL){ + if(adcMeasParamm.item == ADC_MEASURE_ITEM_VAMP){ + adcResult[0] = (uint16_t)(SAR_CTRL_SFRS->DATA[0].DATA & 0x07FFU);//VAMP + adcResult[1] = (uint16_t)(SAR_CTRL_SFRS->DATA[1].DATA & 0x0FFFU);//VBAT + adcResult[2] = (uint16_t)(SAR_CTRL_SFRS->DATA[2].DATA & 0x0FFFU);//VPB3 + adcResult[3] = (uint16_t)(SAR_CTRL_SFRS->DATA[3].DATA & 0x0FFFU);//VPC4 + }else{ + adcResult[1] = 160;//(uint16_t)(SAR_CTRL_SFRS->DATA[1].DATA & 0x0FFFU);//VBAT + adcResult[2] = 150;//(uint16_t)(SAR_CTRL_SFRS->DATA[2].DATA & 0x0FFFU);//VTEMP + } + adcCallback(adcMeasParamm, adcResult); + } + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1U; + SAR_CTRL_SFRS->SARCTRL.SARENAREQ = 1U; +} + +void ADC_GeneralInit(void) +{ +#if SYS_MAIN_CLOCK_DIV == CLOCK_DIV_1 + SAR_CTRL_SFRS->SARCLKDIV = 4U; +#elif SYS_MAIN_CLOCK_DIV == CLOCK_DIV_2 + SAR_CTRL_SFRS->SARCLKDIV = 2U; +#else + SAR_CTRL_SFRS->SARCLKDIV = 1U; +#endif + + for (uint8_t i = 0U; i < 10U; i++){ + + SAR_CTRL_SFRS->ADCCHCTRL2R.WORD &= ~((uint32_t)0x03UL << (i*2+8U));//clear + SAR_CTRL_SFRS->ADCCHCTRL2R.WORD |= ((uint32_t)ADC_REF_VBG_2TIMES << (i*2+8U));//set + + SAR_CTRL_SFRS->ADCCHCTRL0R.WORD &= ~((uint32_t)0x03UL << (i*2+0U)); + SAR_CTRL_SFRS->ADCCHCTRL0R.WORD |= ((uint32_t)ADC_AFE_INPUT_ALL_EXT << (i*2+0U)); + + SAR_CTRL_SFRS->ADCCHCTRL0R.WORD &= ~((uint32_t)0x01UL << (i*1+20U)); + SAR_CTRL_SFRS->ADCCHCTRL0R.WORD |= ((uint32_t)ADC_AFE_GAIN_31_OF_32 << (i*1+20U)); + } + + SAR_CTRL_SFRS->ADCCHCTRL0R.SARINPUTGAINCH4 = ADC_AFE_GAIN_22_OF_32; + + SAR_CTRL_SFRS->SARINT.ENABLE.INT_CONV_DONE_ENA = 0;//1:Convert Done Interrupt Enable. + SAR_CTRL_SFRS->SARINT.ENABLE.INT_TRIG_CLASH_ENA = 0;//1:Trigger Clash Interrupt Enable. + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1; + SAR_CTRL_SFRS->SARINT.CLEAR.INT_TRIG_CLASH_CLR = 1; +} + +void ADC_Init(AdcMeasureItem_t item, uint8_t channel) +{ + ADCTriggerParam_t source; + adcMeasParamm.item = item; + adcMeasParamm.channel = channel; + switch(item){ + case ADC_MEASURE_ITEM_VAMP:/* 1x */ + + SAR_CTRL_SFRS->SARCFG.TRIGDLY = 15U; + // SAR_CTRL_SFRS->SARCFG.TRIGSEL = 1U;//0x1: Select PWMAUX_TRIGSEL + // SAR_CTRL_SFRS->SARCFG.PWMAUXCHSEL = 0U;//0x0: Select PWMAUX Channel 0 + // SAR_CTRL_SFRS->SARCFG.PWMAUXTRIGSEL = 4U;// 0x4: Triggered by PWM AUX counter 0 period. 0x8: Triggered by PWM AUX counter 1 period. + // SAR_CTRL_SFRS->SARCFG.TRIGSRC = 8U;//Triggered through hardware, either select from TRIGSRC[2:0] or from PWMAUX_TRIGSEL.TRIGSRC[2:0]=0x0: Triggered by the PWM compare trigger0. + + source.selection = ADC_TRIGGER_SEL_PWM_AUX_TRIGSRC; + source.channel = ADC_PWMAUX_CHN0; + source.pwmAux = ADC_PWMAUX_TRIG_SRC_PWM_PERIOD0; + source.general = ADC_TRIG_SRC_PWM_CMP0; + + SYSCTRLA_SFRS->CSACTRLR.CSAGAINSEL = 0U;//5 gain + SYSCTRLA_SFRS->CSACTRLR.CSAZEROEN = 0U; + SYSCTRLA_SFRS->CSACTRLR.CSAPOWEN = 1U; + + SAR_CTRL_SFRS->AFECTRL.SARAFEEN = 1;//ADC AFE Enable. adc afe enable. If vinp, vinn and vin vcm all choose external, adc afe should be disabled: adc_adc_en=0, otherwise, adc afe must be enabled: adc_afe_en=1. + SAR_CTRL_SFRS->AFECTRL.ADCSELVINVCMEXT = 0;//Select External Inputs to ADC. choose ADC input common voltage. 0: choose internal vin_vcm, equals to (vinp+vinn)/2; 1: choose external vin_vcm, for PN detect. + SAR_CTRL_SFRS->AFECTRL.SARPREAMPEN = 1;// adc pre-amp enable. + + SAR_CTRL_SFRS->ADCCHCONF.CH1SEL = ADC_CH_SEL_CSA_Filter_OUT_GND;//0x9: adc_vinp=CSA_Filter_OUT , adc_vinn=vref_gnd + SAR_CTRL_SFRS->ADCCHCONF.CH2SEL = ADC_CH_SEL_VBAT_GND; + SAR_CTRL_SFRS->ADCCHCONF.CH3SEL = ADC_CH_SEL_PB3_GND; + SAR_CTRL_SFRS->ADCCHCONF.CH4SEL = ADC_CH_SEL_PC4_GND; + + SAR_CTRL_SFRS->ADCCHCTRL1R.SAMPCYCCH1 = 15U;//max 15 + SAR_CTRL_SFRS->SARCTRL.DIGRESET = 0X1U; + SAR_CTRL_SFRS->ADCCHCONF.SEQCNT = ADC_SQ_CH1_2_CH4;//0x3: CH1->CH2->CH3 + break; + case ADC_MEASURE_ITEM_VBAT_VTEMP:/* 1x */ + SAR_CTRL_SFRS->ADCCHCONF.CH2SEL = ADC_CH_SEL_VBAT_GND; + SAR_CTRL_SFRS->ADCCHCONF.CH3SEL = ADC_CH_SEL_TSENSOR_GND; + SAR_CTRL_SFRS->ADCCHCONF.SEQCNT = (uint8_t)ADC_SQ_CH1_2_CH3; + source.selection = ADC_TRIGGER_SEL_GENERAL_TRIGSRC; + source.general = ADC_TRIG_SRC_SOFT_INPUT; + + break; + + case ADC_MEASURE_ITEM_VBG: /*1x */ + SAR_CTRL_SFRS->ADCCHCONF.CH1SEL = ADC_CH_SEL_REF_GND; + SAR_CTRL_SFRS->ADCCHCONF.SEQCNT = (uint8_t)ADC_SQ_CH1_2_CH1; + source.selection = ADC_TRIGGER_SEL_GENERAL_TRIGSRC; + source.general = ADC_TRIG_SRC_SOFT_INPUT; + break; + + case ADC_MEASURE_ITEM_VBAT: /*1/16x */ + SAR_CTRL_SFRS->ADCCHCONF.CH1SEL = ADC_CH_SEL_VBAT_GND; + SAR_CTRL_SFRS->ADCCHCONF.SEQCNT = (uint8_t)ADC_SQ_CH1_2_CH1; + source.selection = ADC_TRIGGER_SEL_GENERAL_TRIGSRC; + source.general = ADC_TRIG_SRC_SOFT_INPUT; + break; + + case ADC_MEASURE_ITEM_VDD1V5: + SAR_CTRL_SFRS->ADCCHCONF.CH1SEL = ADC_CH_SEL_1V5_GND; + SAR_CTRL_SFRS->ADCCHCONF.SEQCNT = (uint8_t)ADC_SQ_CH1_2_CH1; + source.selection = ADC_TRIGGER_SEL_GENERAL_TRIGSRC; + source.general = ADC_TRIG_SRC_SOFT_INPUT; + break; + default: + + break; + } + SAR_CTRL_SFRS->SARCFG.TRIGSEL = source.selection; + if (source.selection == ADC_TRIGGER_SEL_GENERAL_TRIGSRC){ + SAR_CTRL_SFRS->SARCFG.TRIGSRC = source.general; + }else{ + + SAR_CTRL_SFRS->SARCFG.PWMAUXCHSEL = source.channel; + SAR_CTRL_SFRS->SARCFG.PWMAUXTRIGSEL = source.pwmAux; + SAR_CTRL_SFRS->SARCFG.TRIGSRC = source.general; + SAR_CTRL_SFRS->SARCFG.ROUND = 1U;//0x1: Negative code+1 + } +} + +void ADC_UnInit(AdcMeasureItem_t item) +{ + + +} + +/** + * @brief Register a callback function to ADC interrupt handler. + * + * @param dev Pointer to the ADC device. + * @param cb The callback function to be registered. + * @return 0 for success or error code upon a failure. + */ +void ADC_RegisterIRQ(adc_cb_func_t callback) +{ + adcCallback = callback; + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1U; + SAR_CTRL_SFRS->SARINT.ENABLE.INT_CONV_DONE_ENA = 1U; + NVIC_EnableIRQ(ADC_IRQn); + +} + +/** + * @brief Unregister a callback function to ADC interrupt handler. + * + * @param dev Pointer to the ADC device. + * @param cb The callback function to be unregistered. + * @return 0 for success or error code upon a failure. + */ +void ADC_UnregisterIRQ(void) +{ + adcCallback = NULL; + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1U; + SAR_CTRL_SFRS->SARINT.ENABLE.INT_CONV_DONE_ENA = 0U; + NVIC_DisableIRQ(ADC_IRQn); +} + +void ADC_Start(void) +{ + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1U; + SAR_CTRL_SFRS->SARCTRL.SARENAREQ = 1U; + SAR_CTRL_SFRS->SARCTRL.CONVERT = 1U; +} + +ADCMeasureParam_t ADC_GetadcMeasParamm(void){ + return adcMeasParamm; +} + diff --git a/app_Indie/drivers/hal/src/clock_device.c b/app_Indie/drivers/hal/src/clock_device.c new file mode 100644 index 0000000..f0eaf0b --- /dev/null +++ b/app_Indie/drivers/hal/src/clock_device.c @@ -0,0 +1,48 @@ +/** + * @copyright 2016 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file clock_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include + +#define SYSTEM_CLOCK_SUPER_HIGH_FREQ (48000U)/* KHz */ +#define SYSTEM_CLOCK_HIGH_FREQ (16000U)/* KHz */ +#define SYSTEM_CLOCK_LOW_FREQ (256U) /* KHz */ +static uint32_t systemClock = SYSTEM_CLOCK_HIGH_FREQ; + +void Clock_SystemMainClockInit(uint8_t divider) +{ +// CRGA_SFRS->SYSCLKCTRL.HFRCENA = 1U; +// while(CRGA_SFRS->SYSCLKCTRL.HFRCSTS == 0U){} + /* Enable trim access write enable */ +// SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU; +// SYSCTRLA_SFRS->HF_OSC_TRIM.TRIM_HF_RC= HWCFG_GetRCHFClockCalibValue(); +// +// CRGA_SFRS->LFCLKCTRL.CLKLFSEL = CLOCK_LF_RC_256KHz; +//// TRIMHV_SFRS->TRIM_LF_RC = HWCFG_GetRCLFClockCalibValue(); +// + CRGA_SFRS->SYSCLKCTRL.SYSCLKSEL = (uint8_t)CLOCK_RC_16MHz; + CRGA_SFRS->SYSCLKCTRL.DIVSYSCLK = (uint8_t)divider; +// /* frequency spread */ +// SYSCTRLA_SFRS->HF_OSC_TRIM.SSCDEEP = 7U; +// SYSCTRLA_SFRS->HF_OSC_TRIM.SSCDIV = 15U; +// SYSCTRLA_SFRS->HF_OSC_TRIM.SSCENA = 1U; + + systemClock = SYSTEM_CLOCK_HIGH_FREQ; + systemClock = systemClock >> (uint8_t)divider; + +} + +uint32_t Clock_GetSystemClock(void) +{ + return systemClock;/* KHz */ +} diff --git a/app_Indie/drivers/hal/src/crc32_device.c b/app_Indie/drivers/hal/src/crc32_device.c new file mode 100644 index 0000000..a4eb664 --- /dev/null +++ b/app_Indie/drivers/hal/src/crc32_device.c @@ -0,0 +1,3 @@ +#include + + diff --git a/app_Indie/drivers/hal/src/flash_device.c b/app_Indie/drivers/hal/src/flash_device.c new file mode 100644 index 0000000..381065d --- /dev/null +++ b/app_Indie/drivers/hal/src/flash_device.c @@ -0,0 +1,36 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file flash_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include + + +void Flash_EraseSector(uint32_t sectorAddress) +{ + /* Erase sector data */ + f_FLASH_EraseSector(sectorAddress); +} + +void FLASH_Write2WordsWithECC(uint32_t address,uint32_t dataL,uint32_t dataH) +{ + f_FLASH_Write2WordsWithECC(address, dataL,dataH); +} + + + + + + diff --git a/app_Indie/drivers/hal/src/gTimer_device.c b/app_Indie/drivers/hal/src/gTimer_device.c new file mode 100644 index 0000000..95c7c8e --- /dev/null +++ b/app_Indie/drivers/hal/src/gTimer_device.c @@ -0,0 +1,103 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file timer_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include +#include +#include +#include "errno.h" +#include +#include +#include +#include + +static TimeoutCallbackFunc_t timeoutCallbackFunc[HW_GP_TIMER_NUM] = {NULL,Timer1_INTTest,NULL}; + + +void GT1_Handler( void ) +{ + if (timeoutCallbackFunc[(uint8_t)TIMER0] != NULL){ + timeoutCallbackFunc[(uint8_t)TIMER0](); + } + GTIMER_SFRS->TIMER[TIMER0].GTINTCTRLR.GTTFC = 1U; +} + +void GT2_Handler( void ) +{ + if (timeoutCallbackFunc[(uint8_t)TIMER1] != NULL){ + timeoutCallbackFunc[(uint8_t)TIMER1](); + } + GTIMER_SFRS->TIMER[(uint8_t)TIMER1].GTINTCTRLR.GTTFC = 1U; +} + +void GT3_Handler( void ) +{ + if (timeoutCallbackFunc[(uint8_t)TIMER2] != NULL){ + timeoutCallbackFunc[(uint8_t)TIMER2](); + } + GTIMER_SFRS->TIMER[(uint8_t)TIMER2].GTINTCTRLR.GTTFC = 1U; +} + + + +void TIMER_Init(HwGpTimerId_t timerId, HwGpTimeMode_t mode, GTimer_Prescaler_t prescale, uint16_t timeoutTicks, TimeoutCallbackFunc_t callback) +{ + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTSSE = mode; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTEXTEN = 0U; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTCNTEN = 0U; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTCAPEN = 0U; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTHRSEL = 0U; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTDCEN = 0U; + + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTPRES = prescale; + GTIMER_SFRS->TIMER[timerId].GTRCV = 0xFFFFU - timeoutTicks; + GTIMER_SFRS->TIMER[timerId].GTCV = 0xFFFFU - timeoutTicks; + timeoutCallbackFunc[timerId] = callback; + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTR = 1U; + GTIMER_SFRS->TIMER[timerId].GTINTCTRLR.GTTFC = 1U; + GTIMER_SFRS->TIMER[timerId].GTINTCTRLR.GTTFIE = 1U; + NVIC_EnableIRQ((IRQn_Type)(GT1_IRQn + (uint8_t)timerId)); +} + + +void TIMER_Disable(HwGpTimerId_t timerId) +{ + GTIMER_SFRS->TIMER[timerId].GTCTRLR.GTR = 0U; + timeoutCallbackFunc[timerId] = NULL; + NVIC_DisableIRQ((IRQn_Type)(GT1_IRQn + (uint8_t)timerId)); +} + + + + + + + + + + + + + + + + + + + + + + diff --git a/app_Indie/drivers/hal/src/gpio_device.c b/app_Indie/drivers/hal/src/gpio_device.c new file mode 100644 index 0000000..8310a12 --- /dev/null +++ b/app_Indie/drivers/hal/src/gpio_device.c @@ -0,0 +1,121 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file gpio_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include +#include +#include + +#ifdef GPIO_SFRS +static gpio_cb_func_t gpioCallback[3][8]= {NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, + NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, + NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,}; +void GPIO_Handler(void) +{ + for (uint8_t i = (uint8_t)GPIO_PORT_0; i<= (uint8_t)GPIO_PORT_7; i++ ){ + if (GPIO_SFRS->GPIOA[i].ACTDET == 1U){ + if (gpioCallback[GROUP_GPIOA][i] !=NULL){ + gpioCallback[GROUP_GPIOA][i](); + } + GPIO_SFRS->GPIOA[i].CLR = 1U; + } + if (GPIO_SFRS->GPIOB[i].ACTDET == 1U){ + if (gpioCallback[GROUP_GPIOB][i] !=NULL){ + gpioCallback[GROUP_GPIOB][i](); + } + GPIO_SFRS->GPIOB[i].CLR = 1U; + } + if (GPIO_SFRS->GPIOC[i].ACTDET == 1U){ + if (gpioCallback[GROUP_GPIOC][i] !=NULL){ + gpioCallback[GROUP_GPIOC][i](); + } + GPIO_SFRS->GPIOC[i].CLR = 1U; + } + } +} + +void GPIO_Init(GpioGroup_t group,GpioPort_t port, GpioDir_t dir,GpioPullMode_t pullMode) +{ + IOCTRLA_SFRS->PORT_GROUP_MUX[group] &= ~(0x0FUL << (4U*(uint8_t)port)); + + if (pullMode == GPIO_PULL_NONE){ + IOCTRLA_SFRS->CTRL_MODE[group].PU &= ~(1U << (uint8_t)port); + IOCTRLA_SFRS->CTRL_MODE[group].PD &= ~(1U << (uint8_t)port); + }else if (pullMode == GPIO_PULL_UP){ + IOCTRLA_SFRS->CTRL_MODE[group].PU |= (1 << (uint8_t)port); + IOCTRLA_SFRS->CTRL_MODE[group].PD &= ~(1 << (uint8_t)port); + }else if (pullMode == GPIO_PULL_DOWN){ + IOCTRLA_SFRS->CTRL_MODE[group].PU &= ~(1 << (uint8_t)port); + IOCTRLA_SFRS->CTRL_MODE[group].PD |= (1 << (uint8_t)port); + }else{ + IOCTRLA_SFRS->CTRL_MODE[group].PU |= (1 << (uint8_t)port); + IOCTRLA_SFRS->CTRL_MODE[group].PD |= (1 << (uint8_t)port); + } + + IOCTRLA_SFRS->CTRL_MODE[group].RE |= (1 << (uint8_t)port); + + if (group == GROUP_GPIOA){ + GPIO_SFRS->GPIOA[port].DIR = dir; + }else if(group == GROUP_GPIOB){ + GPIO_SFRS->GPIOB[port].DIR = dir; + }else{ + GPIO_SFRS->GPIOC[port].DIR = dir; + } + +} + + +void GPIO_RegisterIRQ(GpioGroup_t group,GpioPort_t port, GpioISREdge_t edge, gpio_cb_func_t callback) +{ + gpioCallback[(uint8_t)group][(uint8_t)port] = callback; + if (group == GROUP_GPIOA){ + GPIO_SFRS->GPIOA[(uint8_t)port].EDGE = (uint8_t)edge; + GPIO_SFRS->GPIOA[(uint8_t)port].CLR = 1U; + GPIO_SFRS->GPIOA[(uint8_t)port].IE = 1U; + }else if (group == GROUP_GPIOB){ + GPIO_SFRS->GPIOB[(uint8_t)port].EDGE = (uint8_t)edge; + GPIO_SFRS->GPIOB[(uint8_t)port].CLR = 1U; + GPIO_SFRS->GPIOB[(uint8_t)port].IE = 1U; + }else{ + GPIO_SFRS->GPIOC[(uint8_t)port].EDGE = (uint8_t)edge; + GPIO_SFRS->GPIOC[(uint8_t)port].CLR = 1U; + GPIO_SFRS->GPIOC[(uint8_t)port].IE = 1U; + } + NVIC_EnableIRQ(GPIO_IRQn); +} + +void GPIO_UnRegisterIRQ(GpioGroup_t group,GpioPort_t port) +{ + gpioCallback[(uint8_t)group][(uint8_t)port] = NULL; +} + +void GPIO_Set(GpioGroup_t group,GpioPort_t port, GpioSetState_t state) +{ + if (state == GPIO_LOW){ + GPIO_SFRS->GPIO_SET[group].DATACLR = 1U << (uint8_t)port; + }else{ + GPIO_SFRS->GPIO_SET[group].DATASET = 1U << (uint8_t)port; + } + +} + +uint8_t GPIO_Read(GpioGroup_t group,GpioPort_t port) +{ + uint8_t data = GPIO_SFRS->GPIO_SET[group].DATA &(1U << (uint8_t)port); + return (uint8_t)(data != 0U); +} + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/src/hwProtection.c b/app_Indie/drivers/hal/src/hwProtection.c new file mode 100644 index 0000000..55ea517 --- /dev/null +++ b/app_Indie/drivers/hal/src/hwProtection.c @@ -0,0 +1,153 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file hwProtection.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include + +hwProtIsrCallback_t otCallback = NULL; +hwProtIsrCallback_t uvCallback = NULL; +hwProtIsrCallback_t ovCallback = NULL; + +/* !!!!UV OV are level interrupt */ +void UV_OV_Handler(void) +{ + if (PMUA_SFRS->PMUIRQ.STATUS.UV_STS){ + if (uvCallback != NULL){ + uvCallback(); + } + PMUA_SFRS->PMUIRQ.CLEAR.UV_CLR = 1U; + } + + if (PMUA_SFRS->PMUIRQ.STATUS.OV_STS){ + if (ovCallback != NULL){ + ovCallback(); + } + PMUA_SFRS->PMUIRQ.CLEAR.OV_CLR; + } + NVIC_DisableIRQ(UV_OV_IRQn); +} + +void OVTEMP_Handler(void) +{ + if (otCallback != NULL){ + otCallback(); + } + NVIC_DisableIRQ(OVTEMP_IRQn); + CRGA_SFRS->RESETCTRL.OVTEMPFLAGCLR = 1U; +} + + +void HW_PROT_SetOverTmperature(OverTempThres_t threshold, OverTempAction_t action) +{ + TRIMHV_SFRS->OVTEMPCONFIG.VTEMP_SEL = (uint8_t)threshold; + TRIMHV_SFRS->OVTEMPCONFIG.TEMPSENSE_EN = 1U; /* enable temperature sensor */ + + CRGA_SFRS->OVTEMPACTION.OVTEMP = (uint8_t)action; + CRGA_SFRS->OVTEMPACTION.OVERTEMP_EN = 1U; /* enable ov temperature action */ +} + +void HW_PROT_RegisterOVTemperatureIRQ(hwProtIsrCallback_t callback) +{ + otCallback = callback; + CRGA_SFRS->RESETCTRL.OVTEMPFLAGCLR = 1U; + NVIC_EnableIRQ(OVTEMP_IRQn); +} + +void HW_PROT_UnRegisterOVTemperatureIRQ(void) +{ + NVIC_DisableIRQ(OVTEMP_IRQn); + CRGA_SFRS->RESETCTRL.OVTEMPFLAGCLR = 1U; + otCallback = NULL; +} + +void HW_PROT_SetOverVoltage(OverVoltThres_t threshold,OverVoltHysteresis_t hys, VoltDebouceTime_t triggerTime, VoltDebouceTime_t releaseTime) +{ + TRIMHV_SFRS->VBATTRIM.OVLEVEL = (uint8_t)threshold; + TRIMHV_SFRS->VBATTRIM.OVHYS = (uint8_t)hys; + + PMUA_SFRS->VBATDBNC.OVSTRB0SEL = 1U; /* 16KHz source */ + PMUA_SFRS->VBATDBNC.OVSTRB1SEL = 1U; /* 16KHz source */ + + PMUA_SFRS->VBATDBNCTHRES.OVTHRES1 = (uint8_t)triggerTime;/* value*62.5us when 16Khz*/ + PMUA_SFRS->VBATDBNCTHRES.OVTHRES0 = (uint8_t)releaseTime;/* value*62.5us when 16Khz*/ + + TRIMHV_SFRS->VBATTRIM.BAT_OV_EN = 1U; + +} + +void HW_PROT_RegisterOverVoltageIRQ(hwProtIsrCallback_t callback) +{ + ovCallback = callback; + PMUA_SFRS->PMUIRQ.CLEAR.OV_CLR = 1U; + PMUA_SFRS->PMUIRQ.ENABLE.OV_ENA = 1U; + NVIC_EnableIRQ(UV_OV_IRQn); +} + +void HW_PROT_UnRegisterOverVoltageIRQ(void) +{ + NVIC_DisableIRQ(UV_OV_IRQn); + PMUA_SFRS->PMUIRQ.ENABLE.OV_ENA = 0U; + PMUA_SFRS->PMUIRQ.CLEAR.OV_CLR = 1U; + ovCallback = NULL; +} + + +void HW_PROT_SetUnderVoltage(UnderVoltThres_t threshold,UnderVoltHysteresis_t hys, VoltDebouceTime_t triggerTime, VoltDebouceTime_t releaseTime) +{ + TRIMHV_SFRS->VBATTRIM.UVLEVEL = (uint8_t)threshold; + TRIMHV_SFRS->VBATTRIM.UVHYS = (uint8_t)hys; + + PMUA_SFRS->VBATDBNC.UVSTRB0SEL = 1U; /* 16KHz source */ + PMUA_SFRS->VBATDBNC.UVSTRB1SEL = 1U; /* 16KHz source */ + + PMUA_SFRS->VBATDBNCTHRES.UVTHRES1 = (uint8_t)triggerTime; /* value*62.5us when 16Khz*/ + PMUA_SFRS->VBATDBNCTHRES.UVTHRES0 = (uint8_t)releaseTime; /* value*62.5us when 16Khz*/ + + TRIMHV_SFRS->VBATTRIM.BAT_UV_EN = 1U; + +} + +void HW_PROT_RegisterUnderVoltageIRQ(hwProtIsrCallback_t callback) +{ + uvCallback = callback; + PMUA_SFRS->PMUIRQ.CLEAR.UV_CLR = 1U; + PMUA_SFRS->PMUIRQ.ENABLE.UV_ENA = 1U; + NVIC_EnableIRQ(UV_OV_IRQn); +} + +void HW_PROT_UnRegisterUnderVoltageIRQ(void) +{ + NVIC_DisableIRQ(UV_OV_IRQn); + PMUA_SFRS->PMUIRQ.ENABLE.UV_ENA = 0U; + PMUA_SFRS->PMUIRQ.CLEAR.UV_CLR = 1U; + uvCallback = NULL; +} + + +uint8_t HW_PROT_GetBattVoltState(void) +{ + uint8_t result = PMUA_SFRS->VBATCTRL.BAT_STATE; + return result; +} + +uint8_t HW_PROT_ChipIsOverHeat(void) +{ + uint8_t result = (uint8_t)CRGA_SFRS->RESETCTRL.OVTEMPFLAG; + return result; +} + + + + diff --git a/app_Indie/drivers/hal/src/lin_device.c b/app_Indie/drivers/hal/src/lin_device.c new file mode 100644 index 0000000..8e192b2 --- /dev/null +++ b/app_Indie/drivers/hal/src/lin_device.c @@ -0,0 +1,373 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file lin_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include + +#include +#include +#include "gtimer_device.h" +#include "errno.h" +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_PRIVATE + static void LINS_SLAVE_ISR(void); + static lin_wakeup_cb_func_t lin_wakeup_callback = NULL; +#else + static lin_stack_cb_func_t lin_stack_callback = NULL; + static lin_wakeup_cb_func_t lin_wakeup_callback = NULL; +#endif + + uint8_t motorrun = 0; + uint16_t position = 0; + +typedef struct { + uint16_t divider; + uint16_t multiplier; + uint8_t prescale; +} lin_speed_setting_t; + +/********************************************************************** + * Local definitions + *********************************************************************/ + +/** + * At 16MHz clock, the clock divider settings for each LIN speed. + */ + +#if SYS_MAIN_CLOCK_DIV != CLOCK_DIV_1 +#error MAIN_CPU_CLOCK MUST BE at 16MHz system colck! +#endif + +#if SYS_MAIN_CLOCK_DIV == CLOCK_DIV_1 /* 16MHz */ + static const lin_speed_setting_t lins_speed_map[] = { + [E_LIN_BAUDRATE_10417] = {.divider = 200U, .multiplier = 0U, .prescale = 1U}, + [E_LIN_BAUDRATE_19200] = {.divider = 200U, .multiplier = 0U, .prescale = 1U}, + [E_LIN_BAUDRATE_20000] = {.divider = 416U, .multiplier = 0U, .prescale = 1U}, + }; +#elif SYS_MAIN_CLOCK_DIV == CLOCK_DIV_2 /* 8MHz */ + static const lin_speed_setting_t lins_speed_map[E_LIN_BAUDRATE_MAX] = { + [E_LIN_BAUDRATE_10417] = {.divider = 200U, .multiplier = 0U, .prescale = 1U}, + [E_LIN_BAUDRATE_19200] = {.divider = 200U, .multiplier = 0U, .prescale = 1U}, + [E_LIN_BAUDRATE_20000] = {.divider = 200U, .multiplier = 0U, .prescale = 1U}, + }; +#elif SYS_MAIN_CLOCK_DIV == CLOCK_DIV_4 /* 4MHz */ + static const lin_speed_setting_t lins_speed_map[E_LIN_BAUDRATE_MAX] = { + [E_LIN_BAUDRATE_10417] = {.divider = 200U, .multiplier = 0U, .prescale = 0U}, + [E_LIN_BAUDRATE_19200] = {.divider = 200U, .multiplier = 0U, .prescale = 0U}, + [E_LIN_BAUDRATE_20000] = {.divider = 200U, .multiplier = 0U, .prescale = 0U}, + }; +#else +#error invalid SYS_MAIN_CLOCK_DIV Settings! +#endif + +void lins_SetTiming(LIN_BaudRate_t BaudRate); + + void lins_SetTiming(LIN_BaudRate_t BaudRate) +{ + LINS_SFRS->BTDIVSYNC = lins_speed_map[BaudRate].divider; + LINS_SFRS->BITTIME.PRESCL = (uint8_t)lins_speed_map[BaudRate].prescale; +} + +void LINS_Init(void) +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0x05U; + SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0E; + SYSCTRLA_SFRS->PMU_ACCESS_KEY.PMU_ACCESS_KEY = 0x0AU; + TRIMHV_SFRS->LINS.LINS_SLEEP = 0U; /* wake up lins when init if sleep */ + +// IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOA] |= 0x1UL << 12;//ext_lins_rxd0 +// IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOA] |= 0x1UL << 16;//ext_lins_txd0 + + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOC] |= 0x1UL << 8; + + TRIMHV_SFRS->LINS.LINS_PU30K_ENA = 1U; + TRIMHV_SFRS->LINS.LINS_RXENA = 1U; + TRIMHV_SFRS->LINS.LINS_PUOFF_TIMEOUT = 1U; + + /* LINS Pullup Disable in dominant TimeOut condition. Set to disable LINS 30K pullup in case that lin bus is + shorted to ground(Bus idle dominant timeout is detected) for saving power. LINS Pullup will be recovered + automatically if bus idle dominant timeout is released by any bus activity. Only reset by power-on sequence. + */ + IOCTRLA_SFRS->LINTXDMONITOR.LINSTXDMONITORENA = 1U; /* LINS TxD Monitor enable */ + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_SAEJ2602 + LINS_SFRS->BUSTIME.BUSINACTIVE = E_LIN_TIME_INACTIVE_SEC_4; +#else + LINS_SFRS->BUSTIME.BUSINACTIVE = E_LIN_TIME_INACTIVE_SEC_6; +#endif +// LINS_SFRS->BUSTIME.WUPREPEAT = E_LIN_TIME_WAKEUP_REPEAT_MS_200; + + LINS_SFRS->CTRL.WORD = 0; + LINS_SFRS->CTRL.RST_INT_ERR = 0x03U; /* reset error,reset interrupt */ + + TRIMHV_SFRS->LINSTRIM.LINS_RX_BIAS_BOOST = 0U; + TRIMHV_SFRS->LINSTRIM.LINS_TX_BIAS_BOOST = 4U;// pull down ability + TRIMHV_SFRS->LINSTRIM.LINS_TX_SLOPE = LIN_TX_SLEW_RATE_5_1V_PER_US; + lins_SetTiming(E_LIN_BAUDRATE_20000); /* set the maximum supported baud rate */ + /* Enable wakeup detect and IRQ when LINS is in sleep mode(LINS_REG_CTRL.SLEEP = 1U;) */ +// WICA_SFRS->CTRL.LINS_IRQCLR = 1U; + WICA_SFRS->CTRL.LINS_IRQENA = 1U; + WICA_SFRS->CTRL.LINS_ENA = 1U; + WICA_SFRS->CTRL.LINS_WICA_SEL = 0; + + NVIC_EnableIRQ(WULIN_IRQn); + +} + + +void LINS_RegisterLINStack_IRQ(lin_stack_cb_func_t callback,lin_wakeup_cb_func_t wakeupCallback) +{ +#if LIN_STACK_TYPE != LIN_STACK_TYPE_PRIVATE + lin_stack_callback = callback; + lin_wakeup_callback = wakeupCallback; + NVIC_EnableIRQ(LIN_IRQn); +#endif +} + +void LINS_SetSlaveModuleToSleep(void) +{ + TRIMHV_SFRS->LINS.LINS_SLEEP = 0U; +} + + + +uint8_t bufflin[9]; +void LIN_Handler(void) +{ +#if LIN_STACK_TYPE == LIN_STACK_TYPE_PRIVATE + LINS_SLAVE_ISR(); +#else + if (lin_stack_callback != NULL){ + lin_stack_callback(); + } +#endif +} + + + +/* Please make sure here and don't delete these functions!!!! or it would cause severe error*/ + +void IOCTRLA_Handler(void) +{ + +} + + +void WULINS_Handler(void) +{ + if (WICA_SFRS->STATUS.LINS != 0U){ + TRIMHV_SFRS->LINS.LINS_SLEEP = 0U;/* wake up lins occurs when wake up signal detected */ + if (lin_wakeup_callback != NULL){ + lin_wakeup_callback(); + } + WICA_SFRS->CTRL.LINS_IRQCLR = 1U; + } +} + +/* Please make sure here and don't delete these functions!!!! or it would cause severe error*/ +/* wakeup timer wake up interrupt ISR */ +void WUTIMER_Handler(void) +{ + WICA_SFRS->CTRL.TIMER_IRQCLR = 1U; +} + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_PRIVATE + + + +static LIN_Device_Frame_t *privateFrameTable = NULL; +static uint8_t privateFrameTableCount = 0U; +static ls_DataReqCallback_t dataReceivedCallback = NULL; +static ls_DataRspCallback_t dataRspCallback = NULL; +static ls_SleepReqCallback_t sleepReqCallback = NULL; + +void LINS_RegisterPrivateServices(LIN_Device_Frame_t *frameTable, uint8_t tableSize, const ls_LinsPrivateFramesCallback_t *pFunCallback) +{ + privateFrameTable = frameTable; + privateFrameTableCount = tableSize; + dataReceivedCallback = pFunCallback->dataReqCallback; + dataRspCallback = pFunCallback->dataRspCallback; + sleepReqCallback = pFunCallback->sleepReqCallback; + NVIC_EnableIRQ(LIN_IRQn); +} + + +static __INLINE int8_t isValidFrame(LIN_Device_Frame_t *frameTable, uint8_t frameTableLength,uint8_t id) +{ + int8_t index = -1; + if (frameTable != NULL && id != 0xFFU){ + for (uint8_t i = 0U; i < frameTableLength; i++){ + if (frameTable[i].frame_id == id && frameTable[i].frameIsValid == TRUE){ + index = (int8_t)i; + break; + } + } + } + return index; +} + +static __INLINE void dataReceivedACK(uint8_t dataLength, ChecksumType_t checksumType) +{ +// LINS_REG_DL = dataLength + ((uint8_t)checksumType << LINS_DL_ENHCHK_POS) + (0U << LINS_DL_DISBITMON_POS) + (1U << LINS_DL_DISAUTOSLEEP_POS); +// LINS_REG_CTRL.DATAACK_TPYE = DATAACK_TPYE_RECEIVE;/* it's a data receive ack operation */ +// + LINS_SFRS->DL.WORD = dataLength + ((uint8_t)checksumType << LINS_DL_ENHCHK_POS) + (0 << LINS_DL_DISBITMON_POS); +// LINS_REG_DL = dataLength + ((uint8_t)checksumType << LINS_DL_ENHCHK_POS) + (disBitMonitor << LINS_DL_DISBITMON_POS) + (disAutoSleep << LINS_DL_DISAUTOSLEEP_POS); +// LINS_REG_CTRL.DATAACK_TPYE = DATAACK_TPYE_RECEIVE;/* it's a data receive ack operation */ + LINS_SFRS->CTRL.DATAACK_TPYE = DATAACK_TPYE_RECEIVE;/* it's a data receive ack operation */ +} + +static __INLINE void dataResponseACK(uint8_t* payload, uint8_t dataLength,ChecksumType_t checksumType) +{ +// LINS_REG_DL = dataLength + ((uint8_t)checksumType << LINS_DL_ENHCHK_POS) + (0U << LINS_DL_DISBITMON_POS) + (1U << LINS_DL_DISAUTOSLEEP_POS); +// for (uint8_t i = 0U; i < dataLength; i++){ +// LINS_REG_DATA(i) = payload[i]; +// } +// LINS_REG_CTRL.DATAACK_TPYE = DATAACK_TPYE_TRANSMIT;/* it's a data transmit ack operation */ + + LINS_SFRS->DL.WORD = dataLength + ((uint8_t)checksumType << LINS_DL_ENHCHK_POS) + (0 << LINS_DL_DISBITMON_POS); + for (uint8_t i = 0U; i < dataLength; i++){ + LINS_SFRS->DATABUFF[i].DATA = payload[i]; + } + LINS_SFRS->CTRL.DATAACK_TPYE = DATAACK_TPYE_TRANSMIT;/* it's a data transmit ack operation */ +} + + +static void LINS_SLAVE_ISR(void) +{ + static int8_t index = -1; + static uint8_t command = 0; + uint8_t status = (uint8_t)LINS_SFRS->STATUS.WORD; + + if ((status & E_LIN_STATUS_DATA_REQ) != 0U){ + command = LINS_SFRS->ID; + index = isValidFrame(privateFrameTable, privateFrameTableCount,command); +// index = 1; + if (index >= 0){ + if (privateFrameTable[index].msg_type == LIN_MSG_TYPE_RX){ + bufflin[0] = LINS_SFRS->DATABUFF[0].DATA; + bufflin[1] = LINS_SFRS->DATABUFF[1].DATA; + bufflin[2] = LINS_SFRS->DATABUFF[2].DATA; + bufflin[3] = LINS_SFRS->DATABUFF[3].DATA; + bufflin[4] = LINS_SFRS->DATABUFF[4].DATA; + bufflin[5] = LINS_SFRS->DATABUFF[5].DATA; + bufflin[6] = LINS_SFRS->DATABUFF[6].DATA; + bufflin[7] = LINS_SFRS->DATABUFF[7].DATA; + bufflin[8] = LINS_SFRS->ID; + if((bufflin[8] == 0x30) && (bufflin[1] == 0x01)){ + motorrun = 1; + position = bufflin[3]; + position <<= 8; + position += bufflin[2]; + }else if((bufflin[8] == 0x30) && (bufflin[1] == 0x00)){ + motorrun = 0; + } + dataReceivedACK(privateFrameTable[index].length, (ChecksumType_t)privateFrameTable[index].checksum); + }else{ + if (dataRspCallback != NULL){ + dataRspCallback(&privateFrameTable[index]);// feed data based on FID + } + index = 1; + privateFrameTable[index].length = 8; + privateFrameTable[index].checksum = LIN_CHECKSUM_ENHANCED; + dataResponseACK(privateFrameTable[index].data, privateFrameTable[index].length,(ChecksumType_t)privateFrameTable[index].checksum); + } + }else{ + LINS_SFRS->CTRL.STOP = 1U; + } + }else if ((status & E_LIN_STATUS_COMPLETE) != 0U){ + if (LINS_SFRS->TX_STATUS.COMPLETETX == 0U){ /*receive finished */ + if (index >= 0){ + for (uint8_t i = 0U; i < LIN_BUFF_SIZE; i++){ + privateFrameTable[index].data[i] = LINS_SFRS->DATABUFF[i].DATA; + } + if (dataReceivedCallback != NULL){ + dataReceivedCallback(&privateFrameTable[index]); + } + } + } + }else if ((status & E_LIN_STATUS_IDLE_TIMEOUT) != 0U){ +// LINS_SFRS->CTRL.SLEEP = 0; /* workaround for LIN IP would set sleep */ +// IOCTRLA_SFRS->LIN.UPDATE = 1U; +// while(IOCTRLA_SFRS->LIN.UPDATE == 1U); + if (sleepReqCallback != NULL){ + sleepReqCallback(); + } + }else if ((status & E_LIN_STATUS_ERROR) != 0U){ + /*intent to empty*/ + }else{ + /*intent to empty*/ + } + LINS_SFRS->CTRL.RST_INT_ERR = 0x03U; /*reset error,reset interrupt */ +} + +uint8_t getmotorrun(void) +{ + return motorrun; +} + +uint16_t getposition(void) +{ + return position; +} +#endif + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/app_Indie/drivers/hal/src/math_div_device.c b/app_Indie/drivers/hal/src/math_div_device.c new file mode 100644 index 0000000..29f9a59 --- /dev/null +++ b/app_Indie/drivers/hal/src/math_div_device.c @@ -0,0 +1,3 @@ +#include + + diff --git a/app_Indie/drivers/hal/src/pmu_device.c b/app_Indie/drivers/hal/src/pmu_device.c new file mode 100644 index 0000000..a557d35 --- /dev/null +++ b/app_Indie/drivers/hal/src/pmu_device.c @@ -0,0 +1,154 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pmu_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static __INLINE void WDTA_Start(void); + +void BOR_Handler(void) +{ + +} + +void PMU_BORInit(Bor1V5Thres_t lowThreshold, Bor3V3Thres_t highThreshold) +{ + TRIMHV_SFRS->BORCONFIG.S_BOR_1P5V = (uint8_t)lowThreshold; + TRIMHV_SFRS->BORCONFIG.S_BOR_3P3V = (uint8_t)highThreshold; + TRIMHV_SFRS->BORACTION.VDD1V5 = (uint8_t)PMU_BROWNOUT_RESET; + TRIMHV_SFRS->BORACTION.VDD3V3 = (uint8_t)PMU_BROWNOUT_RESET; + + TRIMHV_SFRS->BORACTION.BOR_1V5_LOCK = 1U; + TRIMHV_SFRS->BORACTION.BOR_3V3_LOCK = 1U; + TRIMHV_SFRS->OVTEMPCONFIG.TEMPSENSE_EN = 1U; /* enable temperature sensor */ + EVTHOLD_SFRS->HOLD = 0U; /* clear Lullaby_Handler after wake up */ + + +} + +void PMU_WakeTimerInit(PMU_WAKEUP_TIMEER_MODE_t mode, PMU_WAKEUP_TIMEER_Interval_t interval) +{ + if (mode == WAKEUP_TIMEER_DISABLE){ + WICA_SFRS->CTRL.TIMER_ENA = 0U; + }else{ + WICA_SFRS->CTRL.TIMER_TAPSEL = (uint8_t)interval; + WICA_SFRS->CTRL.TIMER_ENA = 1U; + } +} + +void PMU_EnterDeepSleepMode(void) +{ + StopMotor(); //Í£Ö¹µç»ú + userdatapds_store(); //±£´æλÖà + + CRGA_SFRS->MODULERSTREQ |= MODUE_SOFT_RESET_PWM; + /* Add GPIO function here for low power mode*/ + /* set gpios to input with power up resistor */ +// for (uint8_t i = (uint8_t)GPIO_INIT_PORT_1; i<= (uint8_t)GPIO_INIT_PORT_4; i++ ){ +// GPIO_Init((GpioInitPort_t)i,GPIO_MUX_GPIO,GPIO_DIR_INPUT,GPIO_PULL_UP); +// } + /* end of GPIO settigns */ + TRIMHV_SFRS->OVTEMPCONFIG.TEMPSENSE_EN = 0U; /* disbale temperature sensor when sleep */ + CRGA_SFRS->OVTEMPACTION.OVERTEMP_EN = 0U; + TRIMHV_SFRS->VBATTRIM.BAT_UV_EN = 0U; + TRIMHV_SFRS->VBATTRIM.BAT_OV_EN = 0U; + + +// SYSCTRLA_REG_PMU_ACCESS_KEY.PMU_ACCESS_KEY = 0x0A; +// PMUA_SFRS->CTRL.PD1V5_ENA_HIBERNATE = 1U; + + /*IOCTRLA_SFRS->LINSGFCONF.LINSRXGF3RD_ENA = 0U;*/ + /* clear all of wake up flags */ + /* Enable wakeup detect and IRQ when LINS is in sleep mode(LINS_REG_CTRL.SLEEP = 1U;) */ + WICA_SFRS->CTRL.LINS_IRQCLR = 1U; + WICA_SFRS->CTRL.LINS_IRQENA = 1U; + WICA_SFRS->CTRL.LINS_ENA = 1U; + WICA_SFRS->CTRL.LINS_IRQENA = 1U; + + NVIC_EnableIRQ(WULIN_IRQn); + NVIC_EnableIRQ(Lullaby_IRQn); /* Enable Lullaby interrupt*/ + EVTHOLD_SFRS->HOLD = 1U; /* Trigger ISR then entering sleep in ISR */ + /* Waiting to enter sleep mode */ + for(;;){ + } +} + +/* Please make sure here and don't delete these functions!!!! or it would cause severe error*/ +/* hibernate wake up interrupt ISR */ +void Lullaby_Handler(void) +{ + /* Set lin to sleep mode */ + TRIMHV_SFRS->LINS.LINS_SLEEP = 1U; + /* Enter sleep mode */ + PMUA_SFRS->CTRL.HIBERNATE = 1U; +} + +#pragma optimize=none +static __INLINE void WDTA_Start(void) +{ + CRGA_SFRS->WDTACTION.WDTBARKCNTCLR = 1U; + WDTA_SFRS->CTRL.TIMEOUTSEL = (uint8_t)WDTA_INTERVAL_9216MS; + WDTA_SFRS->CLEAR = 0x3c574ad6U; + WDTA_SFRS->STOPR.STOP = 0U;/* start wdt*/ +} + +uint32_t temp; +uint32_t temp1; +uint32_t t; +uint32_t ICSR_T; + + +void NMI_Handler(void) +{ + temp = FLASH_SFRS->FLSECCR.ADDRECC; + FLASH_SFRS->FLSECCR.ECCD = 1; + FLASH_SFRS->FLSECCR.ECCC = 1; + + SYSCFG_SFRS->SRAMCFGR.SRAMECCD = 1; + SYSCFG_SFRS->SRAMCFGR.SRAMECCC = 1; + + while(1); + +} + + +void HardFault_Handler(void) +{ + WDTA_Start(); + for(;;){} +} + +void SVC_Handler(void) +{ + WDTA_Start(); + for(;;){} +} + +void PendSV_Handler(void) +{ + WDTA_Start(); + for(;;){} +} + + + diff --git a/app_Indie/drivers/hal/src/pwm_aux_device.c b/app_Indie/drivers/hal/src/pwm_aux_device.c new file mode 100644 index 0000000..4e3b789 --- /dev/null +++ b/app_Indie/drivers/hal/src/pwm_aux_device.c @@ -0,0 +1,94 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pwmAux_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/03/18 + */ + +#include +#include +#include + +static PwmAuxIsrCallback_t pwmAuxReloadCallback[2] = {NULL,NULL}; + + +void PWMAUX_Handler(void) +{ + uint8_t status = PWM_AUX_SFRS->INTPERIOD.STATUS.PERIOD; + + if ((status & (1U << (uint8_t)PWMAUX_BASE_0)) == (1U << (uint8_t)PWMAUX_BASE_0)){ + if (pwmAuxReloadCallback[(uint8_t)PWMAUX_BASE_0]!= NULL){ + pwmAuxReloadCallback[(uint8_t)PWMAUX_BASE_0](); + } + PWM_AUX_SFRS->INTPERIOD.CLEAR.PERIOD = (1U << (uint8_t)PWMAUX_BASE_0); + } + + if ((status & (1U << (uint8_t)PWMAUX_BASE_1)) == (1U << (uint8_t)PWMAUX_BASE_1)){ + if (pwmAuxReloadCallback[(uint8_t)PWMAUX_BASE_1]!= NULL){ + pwmAuxReloadCallback[(uint8_t)PWMAUX_BASE_1](); + } + PWM_AUX_SFRS->INTPERIOD.CLEAR.PERIOD = (1U << (uint8_t)PWMAUX_BASE_1); + } +} + + +void PWMAUX_Init(GpioGroup_t group,GpioPort_t port,PWMAUX_CH_t channel,PWMAUX_ClockSource_t source,PWMAUX_Prescaler_t divider,uint16_t peroid) +{ + /* IO configuration */ + + IOCTRLA_SFRS->PORT_GROUP_MUX[group] |= ((uint32_t)0x0FU << (port*4U)); + + IOCTRLA_SFRS->CTRL_MODE[group].PU &= ~(1U << port); + IOCTRLA_SFRS->CTRL_MODE[group].PD &= ~(1U << port); + IOCTRLA_SFRS->CTRL_MODE[group].RE |= (1 << (uint8_t)port); + + if (group == GROUP_GPIOA){ + GPIO_SFRS->GPIOA[port].DIR = GPIO_DIR_OUTPUT; + }else if(group == GROUP_GPIOB){ + GPIO_SFRS->GPIOB[port].DIR = GPIO_DIR_OUTPUT; + }else{ + GPIO_SFRS->GPIOC[port].DIR = GPIO_DIR_OUTPUT; + } + + PWM_AUX_SFRS->PWM_AUX[(uint8_t)source].BASE.PRESCALESEL = (uint8_t)divider; + PWM_AUX_SFRS->PWM_AUX[(uint8_t)source].BASE.PERIOD = peroid; + + uint8_t temp = PWM_AUX_SFRS->BASE_SEL; + temp = temp & (~(1U << (uint8_t)channel)); + temp |= (uint8_t)source << (uint8_t)channel; /* channel connected to which clock source */ + PWM_AUX_SFRS->BASE_SEL = temp; + PWM_AUX_SFRS->ENAREQ.ENAREQ |= 1U << (uint8_t)channel; /* enable PWMAUX channel:0-5 */ +} + + +void PWMAUX_RegisterReloadIRQ(PWMAUX_ClockSource_t source, PwmAuxIsrCallback_t callback) +{ + PWM_AUX_SFRS->INTPERIOD.CLEAR.PERIOD = 1U << (uint8_t)source; + PWM_AUX_SFRS->INTPERIOD.ENABLE.PERIOD |= 1U << (uint8_t)source; + pwmAuxReloadCallback[(uint8_t)source] = callback; + NVIC_EnableIRQ(PWM_AUX_IRQn); +} + +void PWMAUX_UnRegisterReloadIRQ(PWMAUX_ClockSource_t source) +{ + PWM_AUX_SFRS->INTPERIOD.CLEAR.PERIOD = 1U << (uint8_t)source; + PWM_AUX_SFRS->INTPERIOD.ENABLE.PERIOD &= ~(1U << (uint8_t)source); + pwmAuxReloadCallback[(uint8_t)source] = NULL; + NVIC_DisableIRQ(PWM_AUX_IRQn); +} + + +void PWMAUX_SetMatchValue(PWMAUX_CH_t channel, uint16_t matchRisingValue, uint16_t matchFaillValue) +{ + PWM_AUX_SFRS->PULSE[((uint8_t)channel)].WORD = (uint32_t)matchFaillValue + ((uint32_t)matchRisingValue << 16); + PWM_AUX_SFRS->UPDATE = 0x03U; +} + + diff --git a/app_Indie/drivers/hal/src/pwm_device.c b/app_Indie/drivers/hal/src/pwm_device.c new file mode 100644 index 0000000..6d0c544 --- /dev/null +++ b/app_Indie/drivers/hal/src/pwm_device.c @@ -0,0 +1,240 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pwm_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined PWM_SFRS + +void PWM_INTOL0_Handler(void) +{ + + +} + + +void PWM_INTOL1_Handler(void) +{ + + +} + + +void PWM_INTOL2_Handler(void) +{ + + +} + + +void PWM_INTOL3_Handler(void) +{ + + +} + +void PWM_Init(GpioGroup_t group,GpioPort_t port,PWM_CH_t channel,PWM_ClockSource_t source,PWM_Prescaler_t divider,uint16_t peroid) +{ + /* IO configuration */ + + switch(channel) + { + case PWM_CH0_0: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_0){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x03; // PB0 0x3: PWM0_0. + }else if(port==GPIO_PORT_5){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02 << 20; // PB5 0x2: PWM0_0. + }else{ + + } + }else if(group==GROUP_GPIOC){ + if(port==GPIO_PORT_0){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOC] |= (uint32_t)0x03; // PC0 0x3: PWM0_0. + } + }else{ + + } + break; + case PWM_CH0_1: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_6 || port==GPIO_PORT_7){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02<<(port * 4U); // PB6/PB7 0x2: PWM0_1. + } + }else if(group==GROUP_GPIOC){ + if(port==GPIO_PORT_1){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOC] |= (uint32_t)0x02<<(port * 4U); // PC1 0x2: PWM0_1. + } + }else{ + + } + break; + case PWM_CH1_0: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_1){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x03<<(port * 4U); // PB1 0x3: PWM1_0. + } + }else if(group==GROUP_GPIOC){ + if(port==GPIO_PORT_3){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOC] |= (uint32_t)0x02<<(port * 4U); // PC3 0x2: PWM1_0. + } + }else{ + + } + break; + case PWM_CH1_1: + if(group==GROUP_GPIOC){ + if(port==GPIO_PORT_4){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOC] |= (uint32_t)0x02<<(port * 4U); // PC4 0x2: PWM1_1. + } + } + break; + case PWM_CH2_0: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_1){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02<<(port * 4U); // PB1 0x2: PWM2_0. + }else if(port==GPIO_PORT_2){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x03<<(port * 4U); // PB2 0x3: PWM2_0. + }else{ + + } + } + break; + case PWM_CH2_1: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_2){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02<<(port * 4U); // PB2 0x2: PWM2_1. + } + } + break; + case PWM_CH3_0: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_3){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02<<(port * 4U); // PB3 0x2: PWM3_0. + } + } + break; + case PWM_CH3_1: + if(group==GROUP_GPIOB){ + if(port==GPIO_PORT_4){ + IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (uint32_t)0x02<<(port * 4U); // PB4 0x2: PWM3_1. + } + } + break; + default: + break; + } + + IOCTRLA_SFRS->CTRL_MODE[group].PU &= ~(1U << port); + IOCTRLA_SFRS->CTRL_MODE[group].PD &= ~(1U << port); + IOCTRLA_SFRS->CTRL_MODE[group].RE |= (1 << (uint8_t)port); + + if (group == GROUP_GPIOA){ + GPIO_SFRS->GPIOA[port].DIR = GPIO_DIR_OUTPUT; + }else if(group == GROUP_GPIOB){ + GPIO_SFRS->GPIOB[port].DIR = GPIO_DIR_OUTPUT; + }else{ + GPIO_SFRS->GPIOC[port].DIR = GPIO_DIR_OUTPUT; + } + + if(source == PWM_BASE_0){ + PWM_SFRS->PT0PERIOD = peroid; + PWM_SFRS->CTRL1R.PT0PRES = (uint8_t)divider; + }else{ + PWM_SFRS->PT1PERIOD = peroid; + PWM_SFRS->CTRL1R.PT1PRES = (uint8_t)divider; + } +} + +void PWM_SetMatchValue(PWM_ClockSource_t source,PWM_Pulse_t pulse,uint16_t matchRisingValue, uint16_t matchFaillValue) +{ + PWM_SFRS->MODCTRLR.MCEN = 0;//0x1: ENABLED: The modulation of the corresponding output signal by the multi-channel pattern according to bit field MCPTN is enabled + PWM_SFRS->MODCTRLR.CCXMODEN = 0XFF;//0x1: ENABLED: The modulation of the corresponding output signal by CC0~3 pattern is enabled + + PWM_SFRS->MCOUTR.MCUPR= 1;//0x1: By_software: Bit field MCPTN is updated by MCPTNS immediately + PWM_SFRS->MCOUTR.MCPTNS = 0XFF; + + if(source == PWM_BASE_0){ + PWM_SFRS->CTRL0R.PT0RC = 1U;//0x1: PT0R is cleared, PT0 stops counting + }else{ + PWM_SFRS->CTRL0R.PT1RC = 1U;//0x1: PT0R is cleared, PT0 stops counting + } + + if(pulse == PULSE_0){ + PWM_SFRS->PULSE0R.PRISE0 = matchRisingValue; + PWM_SFRS->PULSE0R.PFALL0 = matchFaillValue; + }else if(pulse == PULSE_1){ + PWM_SFRS->PULSE1R.PRISE1 = matchRisingValue; + PWM_SFRS->PULSE1R.PFALL1 = matchFaillValue; + }else if(pulse == PULSE_2){ + PWM_SFRS->PULSE2R.PRISE2 = matchRisingValue; + PWM_SFRS->PULSE2R.PFALL2 = matchFaillValue; + }else if(pulse == PULSE_3){ + PWM_SFRS->PULSE3R.PRISE3 = matchRisingValue; + PWM_SFRS->PULSE3R.PFALL3 = matchFaillValue; + }else{ + + } + if(source == PWM_BASE_0){ + PWM_SFRS->CTRL0R.PT0UPES = 1;//0x1: PT0UPE is set, enabling update + PWM_SFRS->CTRL0R.PT0RS = 1;//0x1: PT0R is set, PT0 start counting + }else{ + PWM_SFRS->CTRL0R.PT1UPES = 1;//0x1: PT0UPE is set, enabling update + PWM_SFRS->CTRL0R.PT1RS = 1;//0x1: PT0R is set, PT0 start counting + } + +} + +void PWM_Listofotherparameters_Init(void) +{ + PWM_SFRS->CTRL1R.CC1CNTS = 0; + PWM_SFRS->CTRL1R.CC2CNTS = 0; + PWM_SFRS->CTRL1R.CC3CNTS = 0; + PWM_SFRS->CTRL1R.PT0MODE = 0;//0x0: Edge_aligned_mode: + + PWM_SFRS->DTCR.CCXDTE = 0;//0x0: DISABLED: Dead-time generation is disabled. + PWM_SFRS->DTCR.PT1DT = 0; + PWM_SFRS->DTCR.PT0DT = 0; + + PWM_SFRS->CHREMAPR.PWM0RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM1RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM2RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM3RMP = 0;//0x0: Select CC0 + + PWM_SFRS->CMPSTATR.CC00PS = 0;//0x0: CC0_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC01PS = 0; + PWM_SFRS->CMPSTATR.CC10PS = 0;//0x0: CC1_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC11PS = 0; + PWM_SFRS->CMPSTATR.CC20PS = 0;//0x0: CC2_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC21PS = 0; + PWM_SFRS->CMPSTATR.CC30PS = 0;//0x0: CC3_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC31PS = 0; + + PWM_SFRS->PSL = 0X0;//0x0: Level_0: The passive level is 0 + + PWM_SFRS->MODCTRLR.MCEN = 0;//0x1: ENABLED: The modulation of the corresponding output signal by the multi-channel pattern according to bit field MCPTN is enabled + PWM_SFRS->MODCTRLR.CCXMODEN = 0XFF;//0x1: ENABLED: The modulation of the corresponding output signal by CC0~3 pattern is enabled + + PWM_SFRS->MCOUTR.MCUPR= 1;//0x1: By_software: Bit field MCPTN is updated by MCPTNS immediately + PWM_SFRS->MCOUTR.MCPTNS = 0XFF; +} + +#endif \ No newline at end of file diff --git a/app_Indie/drivers/hal/src/spi_device.c b/app_Indie/drivers/hal/src/spi_device.c new file mode 100644 index 0000000..64907c0 --- /dev/null +++ b/app_Indie/drivers/hal/src/spi_device.c @@ -0,0 +1,4 @@ +#include + + + diff --git a/app_Indie/drivers/hal/src/systick_device.c b/app_Indie/drivers/hal/src/systick_device.c new file mode 100644 index 0000000..a2a7038 --- /dev/null +++ b/app_Indie/drivers/hal/src/systick_device.c @@ -0,0 +1,52 @@ +/** + * @copyright 2016 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file systick_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include "errno.h" +#include +#include "systick_sfrs.h" +#include "systick_device.h" +#include "clock_device.h" +#include + +static sysTick_cb_func_t sysTickCallback = NULL; + +void SysTick_Handler(void) +{ + if (sysTickCallback != NULL){ + sysTickCallback(); + } +} + +void SysTick_Init(uint32_t ticks, sysTick_cb_func_t callback) +{ + SysTick->VAL = 0U; + SysTick->LOAD = ticks; + sysTickCallback = callback; + SysTick->CTRL |= (SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk); +} + +uint32_t SysTick_GetCount(void) +{ + uint32_t count = SysTick->VAL; + return count; +} + +uint32_t SysTick_GetLoad(void) +{ + uint32_t count = SysTick->LOAD; + return count; +} + + diff --git a/app_Indie/drivers/hal/src/uart_device.c b/app_Indie/drivers/hal/src/uart_device.c new file mode 100644 index 0000000..1f5392a --- /dev/null +++ b/app_Indie/drivers/hal/src/uart_device.c @@ -0,0 +1,2 @@ +#include + diff --git a/app_Indie/drivers/hal/src/wdt_device.c b/app_Indie/drivers/hal/src/wdt_device.c new file mode 100644 index 0000000..2b055e2 --- /dev/null +++ b/app_Indie/drivers/hal/src/wdt_device.c @@ -0,0 +1,77 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file wdt_device.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include "wdt_device.h" +#include "errno.h" +#include +/** + * @brief The instance of WDT device + */ + +void WatchdogA_Handler(void) +{ + +} + +void WDTA_Enable(WDTAInterval_t interval) +{ + WDTA_SFRS->CTRL.TIMEOUTSEL = (uint8_t)interval; + CRGA_SFRS->WDTACTION.WDTBARKCNT = 5; + WDTA_SFRS->CTRL.UPDATE = 1U; + WDTA_SFRS->CLEAR = 0x3c574ad6U; + WDTA_SFRS->STOPR.STOP = 0U;/* start wdt*/ + +} + +void WDTA_Disable(void) +{ + WDTA_SFRS->STOPR.STOP = 0xC3U;/* stop wdt*/ +} + +void WDTA_Clear(void) +{ + WDTA_SFRS->CLEAR = 0x3c574ad6U; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/app_Indie/drivers/hdf/meta.h b/app_Indie/drivers/hdf/meta.h new file mode 100644 index 0000000..ce1ccd0 --- /dev/null +++ b/app_Indie/drivers/hdf/meta.h @@ -0,0 +1,66 @@ +#ifndef META_H__ +#define META_H__ + +// declare an enumerated type that can be used to refer to interrupts by name, e.g. in calls to the NVIC configuration +// functions - the definitions here must match the vector table positions, offset so that IRQ0 (the 1st ASIC IRQ) has +// the value 0... +// +typedef enum IRQn +{ + // Cortex-M0 core exceptions... + Reset_IRQn = -15, + NMI_IRQn = -14, + HardFault_IRQn = -13, + SVC_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + // ASIC-specific IRQs... (should match the vector defined in dig_meta_top.sv) + IOCTRLA_IRQn = 0, + OVTEMP_IRQn = 1, + GPIO_IRQn = 2, + PWM_AUX_IRQn = 3, + GT4_5_IRQn = 4, + WUTIMER_IRQn = 5, + WatchdogA_IRQn = 6, + ADC_IRQn = 7, + SPI_IRQn = 8, + WULIN_IRQn = 9, + UART0_IRQn = 10, + DIV_IRQn = 11, + LIN_IRQn = 12, + FLASH_IRQn = 13, + SRAM_ECCC_IQn = 14, + GT1_IRQn = 15, + GT2_IRQn = 16, + GT3_IRQn = 17, + CT2_IRQn = 18, + CT3_IRQn = 19, + CT4_IRQn = 20, + CT5_IRQn = 21, + CT6_IRQn = 22, + CR_IRQn = 23, + PWM_INTOL0_IRQn = 24, + PWM_INTOL1_IRQn = 25, + PWM_INTOL2_IRQn = 26, + PWM_INTOL3_IRQn = 27, + BOR_IRQn = 28, + UV_OV_IRQn = 29, + CSP_OCP_IRQn = 30, + Lullaby_IRQn = 31 + +} IRQn_Type; +// +// and define a tell-tale macro that will prevent the clough.h header from attempting to re-define this with the +// default (non-ASIC-specific) version... +// +#define __IRQn_Type + +#define TRUE (1U) +#define FALSE (0U) + +#include +#include "sfrs/meta_sfr.h" +#include "verne.h" + +#endif + diff --git a/app_Indie/drivers/hdf/sfrs/bte_sfr.h b/app_Indie/drivers/hdf/sfrs/bte_sfr.h new file mode 100644 index 0000000..c009940 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/bte_sfr.h @@ -0,0 +1,88 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file bte_sfr.h + */ + +#ifndef BTE_SFR_H__ +#define BTE_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for BTE. + */ +typedef struct { + + union { + struct { + uint16_t BXADD : 16; /*!< Address of the ASIC die (LSB) */ + uint8_t BXNUM : 8; /*!< Number of 32-bit words to transfer */ + uint8_t INC_ADDR : 1; + uint8_t TX_DIR : 1; + uint8_t BLOCKING : 1; + uint8_t START : 1; + uint8_t : 4; /* (reserved) */ + }; + uint32_t WORD; + } BTE_CTRL; /* +0x000 */ + + uint16_t BXSRAMADDR; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of BTE SFRS. + */ +#define BTE_SFRS ((__IO BTE_SFRS_t *)0x50000080) + +#endif /* end of __BTE_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/crc_sfr.h b/app_Indie/drivers/hdf/sfrs/crc_sfr.h new file mode 100644 index 0000000..cf75158 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/crc_sfr.h @@ -0,0 +1,94 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file crc_sfr.h + */ + +#ifndef CRC_SFR_H__ +#define CRC_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for CRC. + */ +typedef struct { + + union { + struct { + uint8_t CRCDATA0 : 8; /*!< CRC data bits */ + uint8_t CRCDATA1 : 8; /*!< CRC data bits */ + uint8_t CRCDATA2 : 8; /*!< CRC data bits */ + uint8_t CRCDATA3 : 8; /*!< CRC data bits */ + }; + uint32_t WORD; + } CRCDR; /* +0x000 */ + + uint32_t CRCINIT; /*CRC initial value +0x004 */ + + union { + struct { + uint8_t REVIN : 2; /*!< Reverse input data */ + uint8_t REVOUT : 1; /*!< Reverse output data */ + uint8_t : 5; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } CRCCR; /* +0x008 */ + +} CRC_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of CRC SFRS. + */ +#define CRC_SFRS ((__IO CRC_SFRS_t *)0x40021c00) + +#endif /* end of __CRC_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/crga_sfr.h b/app_Indie/drivers/hdf/sfrs/crga_sfr.h new file mode 100644 index 0000000..caf4ff3 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/crga_sfr.h @@ -0,0 +1,241 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file crga_sfr.h + */ + +#ifndef CRGA_SFR_H__ +#define CRGA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for CRGA. + */ +typedef struct { + + union { + struct { + uint8_t LFRCSTS : 8; /*!< Slow oscillator status */ + uint8_t CLKLFSEL : 8; /*!< LF Clock Source select */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } LFCLKCTRL; /* +0x000 */ + + union { + struct { + uint8_t HFRCENA : 1; /*!< Fast oscillator enable */ + uint8_t HFRCSTS : 1; /*!< Fast oscillator status */ + uint8_t UHFRCENA : 1; /*!< Ultra high frequency oscillator enable */ + uint8_t UHFRCHIGHBWEN : 1; /*!< Ultra high frequency oscillator comparator high bandwidth enable */ + uint8_t : 4; /* (reserved) */ + uint8_t SYSCLKSEL : 1; /*!< System clock select */ + uint8_t SELFASTCLK : 1; /*!< Fast clock select */ + uint8_t : 6; /* (reserved) */ + uint8_t DIVSYSCLK : 3; /*!< Clock div select */ + uint8_t : 1; /* (reserved) */ + uint8_t HF_RC_LDO_VSEL : 2; + uint8_t UHFRCLDOVSEL : 2; + uint8_t CLKSOFTSTRTEN : 1; + uint8_t : 1; /* (reserved) */ + uint8_t CLKSOFTSTRTDLY : 3; + uint8_t : 3; /* (reserved) */ + }; + uint32_t WORD; + } SYSCLKCTRL; /* +0x004 */ + + union { + struct { + uint8_t PORFLAG : 1; /*!< Power on reset flag */ + uint8_t OVFLAG : 1; /*!< Over Voltage Monitor flag */ + uint8_t BOR3V3FLAG : 1; /*!< BOR 3v3 flag */ + uint8_t UVFLAG : 1; /*!< Under Voltage Monitor flag */ + uint8_t BOR1V5FLAG : 1; /*!< BOR 1v5 flag */ + uint8_t WDTFLAG : 1; /*!< Watchdog bark flag */ + uint8_t OVTEMPFLAG : 1; /*!< Over Temp Violation flag */ + uint8_t FSSOFLAG : 1; /*!< FSSO flag */ + uint8_t PORFLAGCLR : 1; /*!< POR flag clear */ + uint8_t OVFLAGCLR : 1; /*!< OV flag clear */ + uint8_t : 1; /* (reserved) */ + uint8_t UVFLAGCLR : 1; /*!< UV flag clear */ + uint8_t : 1; /* (reserved) */ + uint8_t WDTFLAGCLR : 1; /*!< WDT flag clear */ + uint8_t OVTEMPFLAGCLR : 1; /*!< OVTEMP flag clear */ + uint8_t FSSOFLAGCLR : 1; /*!< FSSO flag clear */ + uint8_t HARDRSTREQ : 1; /*!< Hard reset request */ + uint8_t SAFEMODEREQ : 1; /*!< Safe Mode request */ + uint8_t : 2; /* (reserved) */ + uint8_t SAFEMODEENA : 1; /*!< Safe Mode enable */ + uint8_t : 3; /* (reserved) */ + uint8_t SOFTRSTREQ : 8; /*!< Soft reset request */ + }; + uint32_t WORD; + } RESETCTRL; /* +0x008 */ + + union { + struct { + uint8_t ADCSTOP : 1; /*!< ADC Stop */ + uint8_t PWMSTOP : 1; /*!< PWM Stop */ + uint8_t CTTSTOP : 1; /*!< CTT Stop */ + uint8_t GTMSTOP : 1; /*!< GTM Stop */ + uint8_t SPISTOP : 1; /*!< SPI Stop */ + uint8_t UARTSTOP : 1; /*!< UART Stop */ + uint8_t MATHDIVSTOP : 1; /*!< MATHDIV Stop */ + uint8_t CRCSTOP : 1; /*!< CRC Stop */ + uint8_t PWMAUXSTOP : 8; /*!< PWMAUX Stop */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } MODUCLKSTOP; /* +0x00C */ + + union { + struct { + uint8_t ADCSLEEPEN : 1; /*!< ADC Sleep Enable */ + uint8_t PWMSLEEPEN : 1; /*!< PWM Sleep Enable */ + uint8_t CTTSLEEPEN : 1; /*!< CTT Sleep Enable */ + uint8_t GTMSLEEPEN : 1; /*!< GTM Sleep Enable */ + uint8_t SPISLEEPEN : 1; /*!< SPI Sleep Enable */ + uint8_t UARTSLEEPEN : 1; /*!< UART Sleep Enable */ + uint8_t MATHDIVSLEEPEN : 1; /*!< MATHDIV Sleep Enable */ + uint8_t CRCSLEEPEN : 1; /*!< CRC Sleep Enable */ + uint8_t PWMAUXSLEEPEN : 1; /*!< PWMAUX Sleep Enable */ + uint8_t : 6; /* (reserved) */ + uint8_t FLASHSLEEPEN : 1; /*!< Flash Sleep Enable */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } MODUSLEEPEN; /* +0x010 */ + + union { + struct { + uint8_t ADCDEEPSLEEPEN : 1; /*!< ADC Deep Sleep Enable */ + uint8_t PWMDEEPSLEEPEN : 1; /*!< PWM Deep Sleep Enable */ + uint8_t CTTDEEPSLEEPEN : 1; /*!< CTT Deep Sleep Enable */ + uint8_t GTMDEEPSLEEPEN : 1; /*!< GTM Deep Sleep Enable */ + uint8_t SPIDEEPSLEEPEN : 1; /*!< SPI Deep Sleep Enable */ + uint8_t UARTDEEPSLEEPEN : 1; /*!< UART Deep Sleep Enable */ + uint8_t MATHDIVDEEPSLEEPEN : 1; /*!< MATHDIV Deep Sleep Enable */ + uint8_t CRCDEEPSLEEPEN : 1; /*!< CRC Deep Sleep Enable */ + uint8_t PWMAUXDEEPSLEEPEN : 1; /*!< PWMAUX Deep Sleep Enable */ + uint8_t : 6; /* (reserved) */ + uint8_t FLASHDEEPSLEEPEN : 1; /*!< Flash Deep Sleep Enable */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } MODUDEEPSLEEPEN; /* +0x014 */ + + uint16_t MODULERSTREQ; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of CRGA SFRS. + */ +#define CRGA_SFRS ((__IO CRGA_SFRS_t *)0x40000000) + +#endif /* end of __CRGA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/ctt_sfr.h b/app_Indie/drivers/hdf/sfrs/ctt_sfr.h new file mode 100644 index 0000000..ed284bc --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/ctt_sfr.h @@ -0,0 +1,271 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file ctt_sfr.h + */ + +#ifndef CTT_SFR_H__ +#define CTT_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for CTT. + */ +typedef struct { + + union { + struct { + uint8_t SELCT2IN : 1; /*!< Select for CT2IN */ + uint8_t SELCT2EUD : 1; /*!< Select for CT2EUD */ + uint8_t SELCT3IN : 2; /*!< Select for CT3IN */ + uint8_t SELCT3EUD : 1; /*!< Select for CT3EUD */ + uint8_t : 1; /* (reserved) */ + uint8_t SELCT4IN : 2; /*!< Select for CT4IN */ + uint8_t SELCT4EUD : 1; /*!< Select for CT4EUD */ + uint8_t : 1; /* (reserved) */ + uint8_t SELCT5IN : 1; /*!< Select for CT5IN */ + uint8_t SELCT5EUD : 1; /*!< Select for CT5EUD */ + uint8_t SELCT6IN : 1; /*!< Select for CT6IN */ + uint8_t SELCT6EUD : 1; /*!< Select for CT6EUD */ + uint8_t SELCAPIN : 2; /*!< Select for CAPIN */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } CTTINSR; /* +0x000 */ + + union { + struct { + uint8_t CT2I : 3; /*!< Timer CT2 Input Parameter Selection */ + uint8_t CT2M : 3; /*!< Timer CT2 Mode Control */ + uint8_t CT2R : 1; /*!< Timer CT2 Run Bit */ + uint8_t CT2UD : 1; /*!< Timer CT2 Up/Down Control */ + uint8_t CT2EUDE : 1; /*!< Timer CT2 External Up/Down Enable */ + uint8_t CT2RC : 1; /*!< Timer CT2 Remote Control */ + uint8_t : 2; /* (reserved) */ + uint8_t CT2IIMIDIS : 1; /*!< Timer CT2 Incrmental Interrupt Disable */ + uint8_t CT2EDGE : 1; /*!< Timer CT2 Edge Detection */ + uint8_t CT2DIRCH : 1; /*!< Timer CT2 Count Direction Change */ + uint8_t CT2DIR : 1; /*!< Timer CT2 Count Direction */ + uint8_t CT2PRESHI : 1; /*!< Timer CT2 Prescaler High Bit */ + uint8_t : 1; /* (reserved) */ + uint8_t CT2EDGEC : 1; /*!< Timer CT2 Edge Detection Clear */ + uint8_t : 1; /* (reserved) */ + uint8_t CT2DIRCHC : 1; /*!< Timer CT2 Count Direction Change Clear */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CT2CTRLR; /* +0x004 */ + + union { + struct { + uint8_t CT3I : 3; /*!< Timer CT3 Input Parameter Selection */ + uint8_t CT3M : 3; /*!< Timer CT3 Mode Control */ + uint8_t CT3R : 1; /*!< Timer CT3 Run Bit */ + uint8_t CT3UD : 1; /*!< Timer CT3 Up/Down Control */ + uint8_t CT3EUDE : 1; /*!< Timer CT3 External Up/Down Enable */ + uint8_t CT3OE : 1; /*!< Timer CT3 Output Enable */ + uint8_t CT3OTL : 1; /*!< Timer CT3 Overflow/underflow Toggle Latch */ + uint8_t : 1; /* (reserved) */ + uint8_t CT3IIMIDIS : 1; /*!< Timer CT3 Incrmental Interrupt Disable */ + uint8_t CT3EDGE : 1; /*!< Timer CT3 Edge Detection */ + uint8_t CT3DIRCH : 1; /*!< Timer CT3 Count Direction Change */ + uint8_t CT3DIR : 1; /*!< Timer CT3 Count Direction */ + uint8_t CT3PRESHI : 1; /*!< Timer CT3 Prescaler High Bit */ + uint8_t : 1; /* (reserved) */ + uint8_t CT3EDGEC : 1; /*!< Timer CT3 Edge Detection Clear */ + uint8_t : 1; /* (reserved) */ + uint8_t CT3DIRCHC : 1; /*!< Timer CT3 Count Direction Change Clear */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CT3CTRLR; /* +0x008 */ + + union { + struct { + uint8_t CT4I : 3; /*!< Timer CT4 Input Parameter Selection */ + uint8_t CT4M : 3; /*!< Timer CT4 Mode Control */ + uint8_t CT4R : 1; /*!< Timer CT4 Run Bit */ + uint8_t CT4UD : 1; /*!< Timer CT4 Up/Down Control */ + uint8_t CT4EUDE : 1; /*!< Timer CT4 External Up/Down Enable */ + uint8_t CT4RC : 1; /*!< Timer CT4 Remote Control */ + uint8_t CLRCT2EN : 1; /*!< Clear Timer CT2 Enable */ + uint8_t CLRCT3EN : 1; /*!< Clear Timer CT3 Enable */ + uint8_t CT4IIMIDIS : 1; /*!< Timer CT4 Incrmental Interrupt Disable */ + uint8_t CT4EDGE : 1; /*!< Timer CT4 Edge Detection */ + uint8_t CT4DIRCH : 1; /*!< Timer CT4 Count Direction Change */ + uint8_t CT4DIR : 1; /*!< Timer CT4 Count Direction */ + uint8_t CT4PRESHI : 1; /*!< Timer CT4 Prescaler High Bit */ + uint8_t : 1; /* (reserved) */ + uint8_t CT4EDGEC : 1; /*!< Timer CT4 Edge Detection Clear */ + uint8_t : 1; /* (reserved) */ + uint8_t CT4DIRCHC : 1; /*!< Timer CT4 Count Direction Change Clear */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CT4CTRLR; /* +0x00C */ + + union { + struct { + uint8_t CT5I : 3; /*!< Timer CT5 Input Parameter Selection */ + uint8_t CT5M : 2; /*!< Timer CT5 Mode Control */ + uint8_t : 1; /* (reserved) */ + uint8_t CT5R : 1; /*!< Timer CT5 Run Bit */ + uint8_t CT5UD : 1; /*!< Timer CT5 Up/Down Control */ + uint8_t CT5EUDE : 1; /*!< Timer CT5 External Up/Down Enable */ + uint8_t CT5RC : 1; /*!< Timer CT5 Remote Control */ + uint8_t CT3CTS : 1; /*!< Capture Trigger Selection */ + uint8_t : 1; /* (reserved) */ + uint8_t CTS : 2; /*!< Register CAPRLD Capture Trigger Selection */ + uint8_t CT5CLRE : 1; /*!< Timer CT5 Clear Enable Bit */ + uint8_t CT5DIR : 1; /*!< Timer CT5 Count Direction */ + uint8_t CT5PRESHI : 1; /*!< Timer CT5 Prescaler High Bit */ + uint8_t CT5CE : 1; /*!< Timer CT5 Capture Mode Enable */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CT5CTRLR; /* +0x010 */ + + union { + struct { + uint8_t CT6I : 3; /*!< Timer CT6 Input Parameter Selection */ + uint8_t CT6M : 2; /*!< Timer CT6 Mode Control */ + uint8_t : 1; /* (reserved) */ + uint8_t CT6R : 1; /*!< Timer CT6 Run Bit */ + uint8_t CT6UD : 1; /*!< Timer CT6 Up/Down Control */ + uint8_t CT6EUDE : 1; /*!< Timer CT6 External Up/Down Enable */ + uint8_t CT6OE : 1; /*!< Timer CT6 Output Enable */ + uint8_t CT6OTL : 1; /*!< Timer CT6 Overflow/underflow Toggle Latch */ + uint8_t : 3; /* (reserved) */ + uint8_t CT6CLRE : 1; /*!< Timer CT6 Clear Enable Bit */ + uint8_t CT6DIR : 1; /*!< Timer CT6 Count Direction */ + uint8_t CT6PRESHI : 1; /*!< Timer CT6 Prescaler High Bit */ + uint8_t CT6RE : 1; /*!< Timer CT6 Reload Mode Enable */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CT6CTRLR; /* +0x014 */ + + uint16_t CAPRLD; /*Reload value or Captured value +0x018 */ + uint8_t _RESERVED_1A[2]; /* +0x01A */ + + uint16_t CT2CV; /*Timer CT2 Current Value +0x01C */ + uint8_t _RESERVED_1E[2]; /* +0x01E */ + + uint16_t CT3CV; /*Timer CT3 Current Value +0x020 */ + uint8_t _RESERVED_22[2]; /* +0x022 */ + + uint16_t CT4CV; /*Timer CT4 Current Value +0x024 */ + uint8_t _RESERVED_26[2]; /* +0x026 */ + + uint16_t CT5CV; /*Timer CT5 Current Value +0x028 */ + uint8_t _RESERVED_2A[2]; /* +0x02A */ + + uint16_t CT6CV; /*Timer CT6 Current Value +0x02C */ + uint8_t _RESERVED_2E[2]; /* +0x02E */ + + union { + struct { + uint8_t CT2IE : 1; /*!< CT2 interrupt enable */ + uint8_t CT3IE : 1; /*!< CT3 interrupt enable */ + uint8_t CT4IE : 1; /*!< CT4 interrupt enable */ + uint8_t CT5IE : 1; /*!< CT5 interrupt enable */ + uint8_t CT6IE : 1; /*!< CT6 interrupt enable */ + uint8_t CRIE : 1; /*!< CAPREL capture interrupt enable */ + uint8_t : 2; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t CT2IC : 1; /*!< CT2 interrupt clear */ + uint8_t CT3IC : 1; /*!< CT3 interrupt clear */ + uint8_t CT4IC : 1; /*!< CT4 interrupt clear */ + uint8_t CT5IC : 1; /*!< CT5 interrupt clear */ + uint8_t CT6IC : 1; /*!< CT6 interrupt clear */ + uint8_t CRIC : 1; /*!< CAPREL capture interrupt clear */ + uint8_t : 2; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTCTRLR; /* +0x030 */ + + union { + struct { + uint8_t CT2IF : 1; /*!< CT2 interrupt flag */ + uint8_t CT3IF : 1; /*!< CT3 interrupt flag */ + uint8_t CT4IF : 1; /*!< CT4 interrupt flag */ + uint8_t CT5IF : 1; /*!< CT5 interrupt flag */ + uint8_t CT6IF : 1; /*!< CT6 interrupt flag */ + uint8_t CRIF : 1; /*!< CAPREL capture interrupt flag */ + uint8_t : 2; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t CT2IRQ : 1; /*!< CT2 interrupt active */ + uint8_t CT3IRQ : 1; /*!< CT3 interrupt active */ + uint8_t CT4IRQ : 1; /*!< CT4 interrupt active */ + uint8_t CT5IRQ : 1; /*!< CT5 interrupt active */ + uint8_t CT6IRQ : 1; /*!< CT6 interrupt active */ + uint8_t CRIRQ : 1; /*!< CAPREL capture interrupt active */ + uint8_t : 2; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTSTATR; /* +0x034 */ + +} CTT_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of CTT SFRS. + */ +#define CTT_SFRS ((__IO CTT_SFRS_t *)0x40010400) + +#endif /* end of __CTT_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/evthold_sfr.h b/app_Indie/drivers/hdf/sfrs/evthold_sfr.h new file mode 100644 index 0000000..2c3009a --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/evthold_sfr.h @@ -0,0 +1,75 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file evthold_sfr.h + */ + +#ifndef EVTHOLD_SFR_H__ +#define EVTHOLD_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for EVTHOLD. + */ +typedef struct { + + uint8_t HOLD; /* +0x000 */ + uint8_t _RESERVED_01[3]; /* +0x001 */ + +} EVTHOLD_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of EVTHOLD SFRS. + */ +#define EVTHOLD_SFRS ((__IO EVTHOLD_SFRS_t *)0x40013000) + +#endif /* end of __EVTHOLD_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/flash_sfr.h b/app_Indie/drivers/hdf/sfrs/flash_sfr.h new file mode 100644 index 0000000..6fa2d2c --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/flash_sfr.h @@ -0,0 +1,162 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file flash_sfr.h + */ + +#ifndef FLASH_SFR_H__ +#define FLASH_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for FLASH. + */ +typedef struct { + + union { + struct { + uint8_t : 3; /* (reserved) */ + uint16_t FLASHADDR : 13; + uint8_t NVR : 8; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } FLADDR; /* +0x000 */ + + uint32_t DATAL; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of FLASH SFRS. + */ +#define FLASH_SFRS ((__IO FLASH_SFRS_t *)0x40020800) + +#endif /* end of __FLASH_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/gpio_sfr.h b/app_Indie/drivers/hdf/sfrs/gpio_sfr.h new file mode 100644 index 0000000..d59030d --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/gpio_sfr.h @@ -0,0 +1,106 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file gpio_sfr.h + */ + +#ifndef GPIO_SFR_H__ +#define GPIO_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for GPIO. + */ + +typedef struct { + uint8_t DATA : 8; /*!< Port A data */ + uint8_t : 8; /* (reserved) */ + uint8_t DATASET : 8; + uint8_t DATACLR : 8; +}GpioSet_t; + + +typedef struct { + uint8_t DIR : 1; /*!< GPIO PIN output enable */ + uint8_t IE : 1; /*!< GPIO PIN interrupt mask */ + uint8_t EDGE : 2; /* 00: disable, 01: rising, 10: falling, 11: both */ + uint8_t CLR : 1; /*!< GPIO PIN interrupt clear */ + uint8_t ACTDET : 1; /*!< GPIO PIN activity interrupt */ + uint8_t ACTDETRE : 1; /*!< GPIO PIN activity rise status */ + uint8_t ACTDETFE : 1; /*!< GPIO PIN activity fall status */ +} GPIO_Cfg_t; /* +0x1000 */ + + +typedef struct { + GpioSet_t GPIO_SET[3]; + GPIO_Cfg_t GPIOA[8]; + GPIO_Cfg_t GPIOB[8]; + GPIO_Cfg_t GPIOC[8]; + union { + struct { + uint8_t GPAENA : 1; + uint8_t GPBENA : 1; + uint8_t GPCENA : 1; + uint8_t : 5; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } GPENA; /* +0x03C */ + +} GPIO_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of GPIO SFRS. + */ +#define GPIO_SFRS ((__IO GPIO_SFRS_t *)0x40004400) + +#endif /* end of __GPIO_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/gtimer_sfr.h b/app_Indie/drivers/hdf/sfrs/gtimer_sfr.h new file mode 100644 index 0000000..15cbe0d --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/gtimer_sfr.h @@ -0,0 +1,113 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file gtimer_sfr.h + */ + +#ifndef GTIMER_SFR_H__ +#define GTIMER_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +typedef struct { + union { + struct { + uint8_t GTDCEN : 1; /*!< GT1 Direction Control Enable */ + uint8_t GTPRES : 4; /*!< Prescaler select */ + uint8_t GTEDGE : 1; /*!< GT1 Edge select in capture mode/reload mode */ + uint8_t GTHRSEL : 2; /*!< GT1 hardware run selection */ + uint8_t GTCAPEN : 1; /*!< GT1 Capture Enable */ + uint8_t GTCNTEN : 1; /*!< GT1 Counter Mode Enable */ + uint8_t GTR : 1; /*!< Timer GT1 run bit */ + uint8_t GTEXTEN : 1; /*!< GT1 external enable control */ + uint8_t GTSSE : 1; /*!< GT1 single shot enable */ + uint8_t : 1; /* (reserved) */ + uint8_t GTEXTF : 1; /*!< GT1 external flag */ + uint8_t GTTF : 1; /*!< GT1 overflow/underflow flag */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } GTCTRLR; /* +0x000 */ + + union { + struct { + uint8_t : 6; /* (reserved) */ + uint8_t GTEXTFIE : 1; /*!< External interrupt enable */ + uint8_t GTTFIE : 1; /*!< Overflow/underflow interrupt enable */ + uint8_t : 6; /* (reserved) */ + uint8_t GTEXTFC : 1; /*!< GT1EXTF Clear */ + uint8_t GTTFC : 1; /*!< GT1TF Clear */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } GTINTCTRLR; /* +0x004 */ + uint16_t GTRCV; /*GT1 Reload/Capture Value +0x008 */ + uint8_t _RESERVED_0A[2]; /* +0x00A */ + uint16_t GTCV; /* +0x00C */ + uint8_t _RESERVED_0E[2]; /* +0x00E */ +}GTimer_t; + + + + +/** + * @brief A structure to represent Special Function Registers for GTIMER. + */ +typedef struct { + GTimer_t TIMER[5]; +} GTIMER_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of GTIMER SFRS. + */ +#define GTIMER_SFRS ((__IO GTIMER_SFRS_t *)0x40010c00) + +#endif /* end of __GTIMER_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/ioctrla_sfr.h b/app_Indie/drivers/hdf/sfrs/ioctrla_sfr.h new file mode 100644 index 0000000..21a3b37 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/ioctrla_sfr.h @@ -0,0 +1,239 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file ioctrla_sfr.h + */ + +#ifndef IOCTRLA_SFR_H__ +#define IOCTRLA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for IOCTRLA. + */ + + +typedef struct { + uint8_t PU : 8; /*!< Pull-up enable */ + uint8_t PD : 8; /*!< Pull-down enable */ + uint8_t RE : 8; /*!< Read enable */ + uint8_t : 8; /* (reserved) */ +}PortGroupCtrlMode_t; + + +typedef struct { + uint32_t PORT_GROUP_MUX[3]; + PortGroupCtrlMode_t CTRL_MODE[3]; + union { + struct { + uint8_t TESTMUX0 : 8; + uint8_t TESTMUX1 : 8; + uint8_t TESTMUX2 : 8; + uint8_t TESTMUX3 : 8; + }; + uint32_t WORD; + } TESTMUX; /* +0x018 */ + + union { + struct { + uint8_t LINSRXGFENA : 2; /*!< LINS RXD Glitch Filter enables */ + uint8_t LINS_RX_GF_ENA_1ST : 1; /*!< LINS RXD 1st Glitch Filter enables */ + uint8_t LINS_RX_GF_ENA_2ND : 1; /*!< LINS RXD 2nd Glitch Filter enables */ + uint8_t LINS_DBNC_PRESCALE_EN : 1; /*!< LINS Debounce prescale enable */ + uint8_t LINS_DBNC_PRESCALE : 2; /*!< LINS Debounce prescaler select */ + uint8_t : 1; /* (reserved) */ + uint8_t LINSDBNCTHRES0 : 8; /*!< 3rd Stage LINS Debounce Threshold for 1 to 0 */ + uint8_t LINSDBNCTHRES1 : 8; /*!< 3rd Stage LINS Debounce Threshold for 0 to 1 */ + uint8_t LINS_RX_GF_SEL_1ST : 8; /*!< LINS RXD 1st Glitch Filter select dualedge or single-edge */ + }; + uint32_t WORD; + } LINSGFCONF; /* +0x01C */ + + union { + struct { + uint8_t LINS_DBNC_THRES0_1ST : 8; /*!< 1st Stage LINS Debounce Threshold for 1 to 0 */ + uint8_t LINS_DBNC_THRES1_1ST : 8; /*!< 1st Stage LINS Debounce Threshold for 0 to 1 */ + uint8_t LINS_DBNC_THRES0_2ND : 8; /*!< 2nd Stage LINS Debounce Threshold for 1 to 0 */ + uint8_t LINS_DBNC_THRES1_2ND : 8; /*!< 2nd Stage LINS Debounce Threshold for 0 to 1 */ + }; + uint32_t WORD; + } LINSGFCONF1; /* +0x020 */ + + union { + struct { + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t FILT_UNLOCK : 1; + }; + uint32_t WORD; + } FILT_ACCESS; /* +0x024 */ + + union { + struct { + uint8_t LINSTXDMONITORENA : 8; /*!< LINS TxD Monitor enable */ + uint8_t LINSTXDTIMEOUTDOMINANT : 8; /*!< Tx Dominant Timeout */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } LINTXDMONITOR; /* +0x028 */ + + union { + struct { + union { + struct { + uint8_t LINS_TXD_DOM : 8; /*!< LINS TXD Dominant Monitor interrupt enable */ + }; + uint8_t BYTE; + } ENABLE; + union { + struct { + uint8_t LINS_TXD_DOM : 8; /*!< LINS TXD Dominant Monitor interrupt clear */ + }; + uint8_t BYTE; + } CLEAR; + union { + struct { + uint8_t LINS_TXD_DOM : 8; /*!< LINS TXD Dominant Monitor interrupt status */ + }; + uint8_t BYTE; + } STATUS; + union { + struct { + uint8_t LINS_TXD_DOM : 8; /*!< LINS TXD Dominant Monitor interrupt active */ + }; + uint8_t BYTE; + } IRQ; + }; + uint32_t WORD; + } IRQ; /* +0x02C */ + + union { + struct { + uint8_t GPIOCONSEL : 1; /*!< Hardware/Firmware Select */ + uint8_t : 2; /* (reserved) */ + uint16_t GPIOCONREG : 13; /*!< Analog test MUX select */ + uint16_t ANASELREG : 16; /*!< Analog Select Control */ + }; + uint32_t WORD; + } ANALOGTESTMUXOVERRIDE; /* +0x030 */ + + union { + struct { + uint8_t PRESCALE_EN : 1; /*!< prescale enable */ + uint8_t PRESCALE : 2; /*!< prescaler select */ + uint8_t : 5; /* (reserved) */ + uint32_t IODBNCEN : 17; /*!< IO Debounce Enable */ + uint8_t : 7; /* (reserved) */ + }; + uint32_t WORD; + } IODBNC; /* +0x034 */ + + union { + struct { + uint8_t IOGRP0_DBNC_THRES0 : 8; /*!< IO Group0 Debounce Threshold for 1 to 0 */ + uint8_t IOGRP0_DBNC_THRES1 : 8; /*!< IO Group0 Debounce Threshold for 0 to 1 */ + uint8_t IOGRP1_DBNC_THRES0 : 8; /*!< IO Group1 Debounce Threshold for 1 to 0 */ + uint8_t IOGRP1_DBNC_THRES1 : 8; /*!< IO Group1 Debounce Threshold for 0 to 1 */ + }; + uint32_t WORD; + } IOGFCONF0; /* +0x038 */ + + union { + struct { + uint8_t IOGRP2_DBNC_THRES0 : 8; /*!< IO Group2 Debounce Threshold for 1 to 0 */ + uint8_t IOGRP2_DBNC_THRES1 : 8; /*!< IO Group2 Debounce Threshold for 0 to 1 */ + uint8_t IOGRP3_DBNC_THRES0 : 8; /*!< IO Group3 Debounce Threshold for 1 to 0 */ + uint8_t IOGRP3_DBNC_THRES1 : 8; /*!< IO Group3 Debounce Threshold for 0 to 1 */ + }; + uint32_t WORD; + } IOGFCONF1; /* +0x03C */ + + union { + struct { + uint8_t ID_GRPS_PA2 : 2; /*!< PA2 debounce Group Selection */ + uint8_t ID_GRPS_PA3 : 2; /*!< PA3 debounce Group Selection */ + uint8_t ID_GRPS_PA4 : 2; /*!< PA4 debounce Group Selection */ + uint8_t ID_GRPS_PA5 : 2; /*!< PA5 debounce Group Selection */ + uint8_t ID_GRPS_PA6 : 8; /*!< PA6 debounce Group Selection */ + uint8_t ID_GRPS_PB0 : 2; /*!< PB0 debounce Group Selection */ + uint8_t ID_GRPS_PB1 : 2; /*!< PB1 debounce Group Selection */ + uint8_t ID_GRPS_PB2 : 2; /*!< PB2 debounce Group Selection */ + uint8_t ID_GRPS_PB3 : 2; /*!< PB3 debounce Group Selection */ + uint8_t ID_GRPS_PB4 : 2; /*!< PB4 debounce Group Selection */ + uint8_t ID_GRPS_PB5 : 2; /*!< PB5 debounce Group Selection */ + uint8_t ID_GRPS_PB6 : 2; /*!< PB6 debounce Group Selection */ + uint8_t ID_GRPS_PB7 : 2; /*!< PB7 debounce Group Selection */ + }; + uint32_t WORD; + } IODBNCGRPS0; /* +0x040 */ + + union { + struct { + uint8_t ID_GRPS_SWDIO : 2; /*!< SWDIO debounce Group Selection */ + uint8_t ID_GRPS_SWCLK : 2; /*!< SWCLK debounce Group Selection */ + uint8_t ID_GRPS_PC3 : 2; /*!< PC3 debounce Group Selection */ + uint8_t ID_GRPS_PC4 : 2; /*!< PC4 debounce Group Selection */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } IODBNCGRPS1; /* +0x044 */ + +} IOCTRLA_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of IOCTRLA SFRS. + */ +#define IOCTRLA_SFRS ((__IO IOCTRLA_SFRS_t *)0x40000c00) + +#endif /* end of __IOCTRLA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/lins_sfr.h b/app_Indie/drivers/hdf/sfrs/lins_sfr.h new file mode 100644 index 0000000..6cb9cdc --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/lins_sfr.h @@ -0,0 +1,294 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file lins_sfr.h + */ + +#ifndef LINS_SFR_H__ +#define LINS_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#define LINS_DL_LENGTH_POS (0) +#define LINS_DL_DISAUTOSLEEP_POS (5) +#define LINS_DL_DISBITMON_POS (6) +#define LINS_DL_ENHCHK_POS (7) + +#define DATAACK_TPYE_RECEIVE (0x01) +#define DATAACK_TPYE_TRANSMIT (0x03) +/** + * @brief A structure to represent Special Function Registers for LINS. + */ +typedef union{ + struct{ + uint8_t DATA; /*CTRL.PD1V5_ENA_HIBERNATE=0x0), the write operation of this register takes effect by IOCTRLA_SFRS->LIN.UPDATE */ + uint8_t _RESERVED_45[3]; /* +0x045 */ + LINS_CONF_t CONF; + UARTINTENA_t UARTINTENA; + UARTINTCLR_t UARTINTCLR; + UARTINTSTATUS_t UARTINTSTATUS; +} LINS_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of LINS SFRS. + */ +/* +#define LINS_REG_DATA_LOW_4BYTES (*(__IO uint32_t *)(0x50010700)) +#define LINS_REG_DATA_HIGH_4BYTES (*(__IO uint32_t *)(0x50010710)) +#define LINS_REG_DATA(index) (*(__IO uint8_t *)(0x50010700 + index*4)) + +#define LINS_REG_CTRL (*(__IO LINS_CTRL_T2_t *)(0x50010720)) +#define LINS_REG_STATUS (*(__IO uint8_t *)(0x50010724)) +#define LINS_REG_ERROR (*(__IO LINS_ERROR_t *)(0x50010728)) +#define LINS_REG_DL (*(__IO uint8_t *)(0x5001072C)) +#define LINS_REG_BTDIV07 (*(__IO uint8_t *)(0x50010730)) +#define LINS_REG_BITTIME (*(__IO LINS_BITTIME_t *)(0x50010734)) +#define LINS_REG_ID (*(__IO uint8_t *)(0x50010738)) +#define LINS_REG_BUSTIME (*(__IO LINS_BUSTIME_t *)(0x5001073C)) +#define LINS_REG_TX_STATUS (*(__IO LINS_TX_STATUS_t *)(0x50010740)) +#define LINS_REG_WUPDETECTTHRES (*(__IO uint8_t *)(0x50010744)) +#define LINS_REG_CONF (*(__IO LINS_CONF_t *)(0x50010748)) +*/ +/** + * @brief The starting address of LINS SFRS. + */ +#define LINS_SFRS ((__IO LINS_SFRS_t *)0x40001C00) + +#endif /* end of __LINS_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/mathdiv_sfr.h b/app_Indie/drivers/hdf/sfrs/mathdiv_sfr.h new file mode 100644 index 0000000..bb5e141 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/mathdiv_sfr.h @@ -0,0 +1,142 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file mathdiv_sfr.h + */ + +#ifndef MATHDIV_SFR_H__ +#define MATHDIV_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for MATHDIV. + */ +typedef struct { + + union { + struct { + uint8_t DVDRC : 2; /*!< Dividend Register Result Chaining */ + uint8_t : 1; /* (reserved) */ + uint8_t DVSRC : 2; /*!< Dividend Register Result Chaining */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t SUSCFG : 8; /*!< Suspend Mode Configuration */ + uint8_t : 7; /* (reserved) */ + uint8_t MATHEN : 1; /*!< Enable Math Module */ + }; + uint32_t WORD; + } GLBCON; /* +0x000 */ + + union { + struct { + uint8_t DIVEOCQ : 1; + uint8_t DIVERRQ : 1; + uint8_t : 6; /* (reserved) */ + uint8_t DIVEOC : 1; + uint8_t DIVERR : 1; + uint8_t : 6; /* (reserved) */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } DIVINTSTATR; /* +0x004 */ + + union { + struct { + uint8_t DIVEOCS : 1; + uint8_t DIVERRS : 1; + uint8_t : 6; /* (reserved) */ + uint8_t DIVEOCC : 1; + uint8_t DIVERRC : 1; + uint8_t : 6; /* (reserved) */ + uint8_t DIVEOCIE : 1; + uint8_t DIVERRIE : 1; + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } DIVINTPROCR; /* +0x008 */ + + uint32_t DVDVAL; /* +0x00C */ + + uint32_t DVSVAL; /* +0x010 */ + + uint32_t QUOTVAL; /* +0x014 */ + + uint32_t RMDVAL; /* +0x018 */ + + uint8_t BUSY; /* +0x01C */ + uint8_t _RESERVED_1D[3]; /* +0x01D */ + + union { + struct { + uint8_t ST : 1; /*!< Start Bit */ + uint8_t STMODE : 1; /*!< Start Mode */ + uint8_t USIGN : 1; /*!< Unsigned Division Enable */ + uint8_t DIVMODE : 2; /*!< Division Mode */ + uint8_t : 3; /* (reserved) */ + uint8_t QSCNT : 5; /*!< Quotient Shift Count */ + uint8_t : 2; /* (reserved) */ + uint8_t QSDIR : 1; /*!< Quotient Shift Direction */ + uint8_t DVDSLC : 8; /*!< Dividend Shift Left Count */ + uint8_t DVSSRC : 8; /*!< Divisor Shift Right Count */ + }; + uint32_t WORD; + } DIVCON; /* +0x020 */ + +} MATHDIV_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of MATHDIV SFRS. + */ +#define MATHDIV_SFRS ((__IO MATHDIV_SFRS_t *)0x40021800) + +#endif /* end of __MATHDIV_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/meta_sfr.h b/app_Indie/drivers/hdf/sfrs/meta_sfr.h new file mode 100644 index 0000000..488a7ed --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/meta_sfr.h @@ -0,0 +1,31 @@ +/* this header brings in the individual files that define the + * struct typdefs for all the special function registers of META + */ + +#ifndef META_SFR_H__ +#define META_SFR_H__ + +#include "sram_sfr.h" +#include "crga_sfr.h" +#include "pmua_sfr.h" +#include "sysctrla_sfr.h" +#include "trimhv_sfr.h" +#include "ioctrla_sfr.h" +#include "wica_sfr.h" +#include "wdta_sfr.h" +#include "lins_sfr.h" +#include "gpio_sfr.h" +#include "pwm_sfr.h" +#include "ctt_sfr.h" +#include "pwm_aux_sfr.h" +#include "gtimer_sfr.h" +#include "evthold_sfr.h" +#include "sar_ctrl_sfr.h" +#include "spi_sfr.h" +#include "uart0_sfr.h" +#include "syscfg_sfr.h" +#include "flash_sfr.h" +#include "mathdiv_sfr.h" +#include "crc_sfr.h" + +#endif diff --git a/app_Indie/drivers/hdf/sfrs/pmua_sfr.h b/app_Indie/drivers/hdf/sfrs/pmua_sfr.h new file mode 100644 index 0000000..045e1b2 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/pmua_sfr.h @@ -0,0 +1,171 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file pmua_sfr.h + */ + +#ifndef PMUA_SFR_H__ +#define PMUA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for PMUA. + */ +typedef struct { + + union { + struct { + uint8_t HIBERNATE : 1; + uint8_t FASTBOOT : 1; /*!< Fast boot */ + uint8_t : 6; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } CTRL; /* +0x000 */ + + union { + struct { + uint8_t ENABLE_1V5 : 4; /*!< Enable 1.5V dwell time */ + uint8_t ATTACH_1V5 : 4; /*!< Attach 1.5V dwell time */ + uint8_t ATTACH_3V3 : 4; /*!< Attach 3.3V dwell time */ + uint8_t POWER_DOWN_MCU : 4; /*!< Power down MCU dwell time */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } DWELL; /* +0x004 */ + + union { + struct { + uint8_t : 2; /* (reserved) */ + uint8_t UV_POL : 1; /*!< Battery Voltage Monitor Under Voltage Interrupt Event Polarity */ + uint8_t OV_POL : 1; /*!< Battery Voltage Monitor Over Voltage Interrupt Event Polarity */ + uint8_t : 4; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t LOW : 1; /*!< Battery Voltage Low Status */ + uint8_t HIGH : 1; /*!< Battery Voltage High Status */ + uint8_t BAT_STATE : 2; + uint8_t : 4; /* (reserved) */ + }; + uint32_t WORD; + } VBATCTRL; /* +0x008 */ + + union { + struct { + uint8_t UV : 1; /*!< under voltage signal debounce enable */ + uint8_t OV : 1; /*!< over voltage signal debounce enable */ + uint8_t UVSTRB0SEL : 1; /*!< Low frequency strobing select for debouncing */ + uint8_t UVSTRB1SEL : 1; /*!< Low frequency strobing select for debouncing */ + uint8_t OVSTRB0SEL : 1; /*!< Low frequency strobing select for debouncing */ + uint8_t OVSTRB1SEL : 1; /*!< Low frequency strobing select for debouncing */ + uint8_t : 2; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } VBATDBNC; /* +0x00C */ + + union { + struct { + uint8_t UVTHRES1 : 8; /*!< Under Voltage debouncing threshold for 0to1 Transition */ + uint8_t OVTHRES1 : 8; /*!< Over Voltage debouncing threshold for 0to1 Transition */ + uint8_t UVTHRES0 : 8; /*!< Under Voltage debouncing threshold for 1to0 Transition */ + uint8_t OVTHRES0 : 8; /*!< Over Voltage debouncing threshold for 1to0 Transition */ + }; + uint32_t WORD; + } VBATDBNCTHRES; /* +0x010 */ + + union { + struct { + union { + struct { + uint8_t UV_ENA : 1; /*!< under voltage interrupt enable */ + uint8_t OV_ENA : 1; /*!< over voltage interrupt enable */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } ENABLE; + union { + struct { + uint8_t UV_CLR : 1; /*!< under voltage interrupt clear */ + uint8_t OV_CLR : 1; /*!< over voltage interrupt clear */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } CLEAR; + union { + struct { + uint8_t UV_STS : 1; /*!< under voltage interrupt status */ + uint8_t OV_STS : 1; /*!< over voltage interrupt status */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } STATUS; + union { + struct { + uint8_t UV_ACT : 1; /*!< under voltage interrupt active */ + uint8_t OV_ACT : 1; /*!< over voltage interrupt active */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } IRQ; + }; + uint32_t WORD; + } PMUIRQ; /* +0x014 */ + +} PMUA_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of PMUA SFRS. + */ +#define PMUA_SFRS ((__IO PMUA_SFRS_t *)0x40000400) + +#endif /* end of __PMUA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/pwm_aux_sfr.h b/app_Indie/drivers/hdf/sfrs/pwm_aux_sfr.h new file mode 100644 index 0000000..8af9d58 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/pwm_aux_sfr.h @@ -0,0 +1,207 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file pwm_aux_sfr.h + */ + +#ifndef PWM_AUX_SFR_H__ +#define PWM_AUX_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for PWM_AUX. + */ + +typedef struct { + struct { + uint8_t : 8; /* (reserved) */ + uint8_t PRESCALESEL : 8; /*!< Prescaler select */ + uint16_t PERIOD : 16; /*!< Period */ + }BASE; /* +0x000 */ + uint16_t PWMCNT; /* +0x004 */ + uint8_t _RESERVED[2]; /* +0x006 */ +}PWM_AUX_t; + + +typedef union { + struct { + uint16_t PFALL : 16; /*!< Pulse Fall */ + uint16_t PRISE : 16; /*!< Pulse Rise */ + }; + uint32_t WORD; +}PWM_AUX_PULSE_t; /* +0x028 */ + + +typedef struct { + PWM_AUX_t PWM_AUX[2]; + uint8_t BASE_SEL; /* +0x010 */ + uint8_t _RESERVED_11[3]; /* +0x011 */ + + union { + struct { + uint8_t ENAREQ : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t ENAREQALL : 1; + uint8_t CLRREQALL : 1; + uint8_t FORCEINACTIVE : 1; + uint8_t : 5; /* (reserved) */ + }; + uint32_t WORD; + } ENAREQ; /* +0x014 */ + + uint8_t ENASTS; /* +0x018 */ + uint8_t _RESERVED_19[3]; /* +0x019 */ + + uint8_t INIT; /* +0x01C */ + uint8_t _RESERVED_1D[3]; /* +0x01D */ + + uint8_t INVERT; /* +0x020 */ + uint8_t _RESERVED_21[3]; /* +0x021 */ + + uint8_t UPDATE; /* +0x024 */ + uint8_t _RESERVED_25[3]; /* +0x025 */ + + PWM_AUX_PULSE_t PULSE[6]; + + uint8_t INTPOSEDGENA; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of PWM_AUX SFRS. + */ +#define PWM_AUX_SFRS ((__IO PWM_AUX_SFRS_t *)0x40010800) + +#endif /* end of __PWM_AUX_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/pwm_sfr.h b/app_Indie/drivers/hdf/sfrs/pwm_sfr.h new file mode 100644 index 0000000..62958bc --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/pwm_sfr.h @@ -0,0 +1,412 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file pwm_sfr.h + */ + +#ifndef PWM_SFR_H__ +#define PWM_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for PWM. + */ +typedef struct { + + uint16_t PT0PERIOD; /*Period +0x000 */ + uint8_t _RESERVED_02[2]; /* +0x002 */ + + uint16_t PT0CV; /* +0x004 */ + uint8_t _RESERVED_06[2]; /* +0x006 */ + + uint16_t PT1PERIOD; /*Period +0x008 */ + uint8_t _RESERVED_0A[2]; /* +0x00A */ + + uint16_t PT1CV; /* +0x00C */ + uint8_t _RESERVED_0E[2]; /* +0x00E */ + + union { + struct { + uint8_t PT0RC : 1; + uint8_t PT0RS : 1; + uint8_t PT0RST : 1; /*!< PT0 reset */ + uint8_t PT0DTR : 1; /*!< PT0 dead-time counter reset */ + uint8_t : 1; /* (reserved) */ + uint8_t PT0CEVT : 1; /*!< PT0 count event */ + uint8_t PT0UPEC : 1; + uint8_t PT0UPES : 1; + uint8_t : 8; /* (reserved) */ + uint8_t PT1RC : 1; + uint8_t PT1RS : 1; + uint8_t PT1RST : 1; /*!< PT1 reset */ + uint8_t PT1DTR : 1; /*!< PT1 dead-time counter reset */ + uint8_t : 1; /* (reserved) */ + uint8_t PT1CEVT : 1; /*!< PT1 count event */ + uint8_t PT1UPEC : 1; + uint8_t PT1UPES : 1; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CTRL0R; /* +0x010 */ + + union { + struct { + uint8_t PT0PRES : 4; /*!< Prescaler select */ + uint8_t PT0R : 1; /*!< Timer PT0 run bit */ + uint8_t PT0UPE : 1; /*!< Timer PT0 update enable */ + uint8_t PT0CDWN : 1; /*!< Count direction of timer PT0 */ + uint8_t PT0MODE : 1; /*!< PT0 operating mode */ + uint8_t PT0CIN : 2; /*!< Input event select for PT0 counting */ + uint8_t PT0SSE : 1; /*!< PT0 single shot enable */ + uint8_t PT0HRSEL : 2; /*!< PT0 hardware run selection */ + uint8_t : 3; /* (reserved) */ + uint8_t PT1PRES : 4; /*!< Prescaler select */ + uint8_t PT1R : 1; /*!< Timer PT1 run bit */ + uint8_t PT1UPE : 1; /*!< Timer PT1 update enable */ + uint8_t PT1CDWN : 1; /*!< Count direction of timer PT1 */ + uint8_t PT1MODE : 1; /*!< PT1 operating mode */ + uint8_t PT1CIN : 2; /*!< Input event select for PT1 counting */ + uint8_t PT1SSE : 1; /*!< PT1 single shot enable */ + uint8_t PT1HRSEL : 2; /*!< PT1 hardware run selection */ + uint8_t CC1CNTS : 1; /*!< Compare Channel 1 counter selection */ + uint8_t CC2CNTS : 1; /*!< Compare Channel 2 counter selection */ + uint8_t CC3CNTS : 1; /*!< Compare Channel 3 counter selection */ + }; + uint32_t WORD; + } CTRL1R; /* +0x014 */ + + union { + struct { + uint8_t PT1TES : 4; + uint8_t PT1TED : 2; + uint8_t : 2; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } TRIGR; /* +0x018 */ + + union { + struct { + uint8_t PT0DT : 8; + uint8_t PT1DT : 8; + uint8_t CCXDTE : 8; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } DTCR; /* +0x01C */ + + union { + struct { + uint16_t PFALL0 : 16; /*!< State Pulse Fall CC0 */ + uint16_t PRISE0 : 16; /*!< State Pulse Rise CC0 */ + }; + uint32_t WORD; + } PULSE0R; /* +0x020 */ + + union { + struct { + uint16_t PFALL1 : 16; /*!< State Pulse Fall CC1 */ + uint16_t PRISE1 : 16; /*!< State Pulse Rise CC1 */ + }; + uint32_t WORD; + } PULSE1R; /* +0x024 */ + + union { + struct { + uint16_t PFALL2 : 16; /*!< State Pulse Fall CC2 */ + uint16_t PRISE2 : 16; /*!< State Pulse Rise CC2 */ + }; + uint32_t WORD; + } PULSE2R; /* +0x028 */ + + union { + struct { + uint16_t PFALL3 : 16; /*!< State Pulse Fall CC3 */ + uint16_t PRISE3 : 16; /*!< State Pulse Rise CC3 */ + }; + uint32_t WORD; + } PULSE3R; /* +0x02C */ + + union { + struct { + uint8_t CCXCS : 8; + uint8_t CC00PS : 1; + uint8_t CC01PS : 1; + uint8_t CC10PS : 1; + uint8_t CC11PS : 1; + uint8_t CC20PS : 1; + uint8_t CC21PS : 1; + uint8_t CC30PS : 1; + uint8_t CC31PS : 1; + uint8_t CC30IM : 8; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CMPSTATR; /* +0x030 */ + + union { + struct { + uint8_t CCXCSS : 8; + uint8_t CCXCSC : 8; + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } CMPMDFIR; /* +0x034 */ + + uint8_t PSL; /* +0x038 */ + uint8_t _RESERVED_39[3]; /* +0x039 */ + + union { + struct { + uint8_t SWSEL : 3; + uint8_t : 1; /* (reserved) */ + uint8_t SWSYNC : 2; + uint8_t : 2; /* (reserved) */ + uint8_t MCUPEPT0U : 1; + uint8_t MCUPEPT0D : 1; + uint8_t MCUPEPT1U : 1; + uint8_t MCUPEPT1D : 1; + uint8_t : 4; /* (reserved) */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } MCCTRLR; /* +0x03C */ + + union { + struct { + uint8_t MCPTN : 8; + uint8_t : 1; /* (reserved) */ + uint8_t NTIF : 1; + uint8_t : 6; /* (reserved) */ + uint8_t MCPTNS : 8; + uint8_t MCUPR : 8; + }; + uint32_t WORD; + } MCOUTR; /* +0x040 */ + + union { + struct { + uint8_t TRPSCM : 2; + uint8_t TRPFCM : 1; + uint8_t : 5; /* (reserved) */ + uint8_t TRPEN : 8; + uint8_t TRPPEN : 1; + uint8_t OCPFAST : 1; + uint8_t : 2; /* (reserved) */ + uint8_t OCPFILTS : 4; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } TRPCTRLR; /* +0x044 */ + + union { + struct { + uint8_t CCXMODEN : 8; + uint8_t PT1MODEN : 8; + uint8_t MCEN : 8; + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } MODCTRLR; /* +0x048 */ + + union { + struct { + uint8_t PWM0RMP : 2; /*!< PWM0 remap selection */ + uint8_t : 2; /* (reserved) */ + uint8_t PWM1RMP : 2; /*!< PWM1 remap selection */ + uint8_t : 2; /* (reserved) */ + uint8_t PWM2RMP : 2; /*!< PWM2 remap selection */ + uint8_t : 2; /* (reserved) */ + uint8_t PWM3RMP : 2; /*!< PWM3 remap selection */ + uint8_t : 2; /* (reserved) */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } CHREMAPR; /* +0x04C */ + + union { + struct { + uint16_t CMPTRIG0V : 16; /*!< Trigger0 Compare Value */ + uint8_t TRIG0PT : 1; /*!< Trigger0 Compare Counter Selection */ + uint8_t : 3; /* (reserved) */ + uint8_t TRIG0MD : 1; /*!< Trigger0 Compare Mode */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CMPTRIG0R; /* +0x050 */ + + union { + struct { + uint16_t CMPTRIG1V : 16; /*!< Trigger1 Compare Value */ + uint8_t TRIG1PT : 1; /*!< Trigger1 Compare Counter Selection */ + uint8_t : 3; /* (reserved) */ + uint8_t TRIG1MD : 1; /*!< Trigger1 Compare Mode */ + uint8_t : 3; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } CMPTRIG1R; /* +0x054 */ + + union { + struct { + uint8_t CC0INTOL : 2; /*!< CC0 interrupt output line selection */ + uint8_t CC1INTOL : 2; /*!< CC1 interrupt output line selection */ + uint8_t CC2INTOL : 2; /*!< CC2 interrupt output line selection */ + uint8_t CC3INTOL : 2; /*!< CC3 interrupt output line selection */ + uint8_t PT0INTOL : 2; /*!< PT0 interrupt output line selection */ + uint8_t PT1INTOL : 2; /*!< PT1 interrupt output line selection */ + uint8_t MCUPFINTOL : 2; /*!< MCUPF interrupt output line selection */ + uint8_t TRPINTOL : 2; /*!< TRPIS interrupt output line selection */ + uint8_t CT0FINTOL : 2; /*!< CT0F interrupt output line selection */ + uint8_t CT1FINTOL : 2; /*!< CT1F interrupt output line selection */ + uint8_t : 4; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTOLR; /* +0x058 */ + + union { + struct { + uint8_t CCXRIE : 4; /*!< CCx Rise-Match interrupt enable */ + uint8_t CCXFIE : 4; /*!< CCx Fall-Match interrupt enable */ + uint8_t PTXOMIE : 2; /*!< PTx One-Match interrupt enable */ + uint8_t PTXPMIE : 2; /*!< PTx Period-Match interrupt enable */ + uint8_t MCUPFIE : 1; /*!< Multi-channel mode updated interrupt enable */ + uint8_t : 2; /* (reserved) */ + uint8_t TRPIE : 1; /*!< Trap interrupt enable */ + uint8_t CT0IE : 1; /*!< Compare Trigger0 interrupt enable */ + uint8_t CT1IE : 1; /*!< Compare Trigger1 interrupt enable */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTCTRLR; /* +0x05C */ + + union { + struct { + uint8_t CCXRS : 4; /*!< CCx Rise-Match Flag Set */ + uint8_t CCXFS : 4; /*!< CCx Fall-Match Flag Set */ + uint8_t PTXOMS : 2; /*!< PTx One-Match Flag Set */ + uint8_t PTXPMS : 2; /*!< PTx Period-Match Flag Set */ + uint8_t MCUPFS : 1; /*!< Multi-channel mode updated Flag Set */ + uint8_t : 2; /* (reserved) */ + uint8_t TRPISS : 1; /*!< Trap Interrupt Status Set */ + uint8_t CT0FS : 1; /*!< Compare Trigger0 Interrupt Status Set */ + uint8_t CT1FS : 1; /*!< Compare Trigger1 Interrupt Status Set */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTSETR; /* +0x060 */ + + union { + struct { + uint8_t CCXRC : 4; /*!< CCx Rise-Match Flag Clear */ + uint8_t CCXFC : 4; /*!< CCx Fall-Match Flag Clear */ + uint8_t PTXOMC : 2; /*!< PTx One-Match Flag Clear */ + uint8_t PTXPMC : 2; /*!< PTx Period-Match Flag Clear */ + uint8_t MCUPFC : 1; /*!< Multi-channel mode updated Flag Clear */ + uint8_t TRPFC : 1; /*!< Trap Flag Clear */ + uint8_t : 1; /* (reserved) */ + uint8_t TRPISC : 1; /*!< Trap Interrupt Status Clear */ + uint8_t CT0FC : 1; /*!< Compare Trigger0 Interrupt Status Clear */ + uint8_t CT1FC : 1; /*!< Compare Trigger1 Interrupt Status Clear */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTCLRR; /* +0x064 */ + + union { + struct { + uint8_t CCXR : 4; /*!< CCx Rise-Match Flag */ + uint8_t CCXF : 4; /*!< CCx Fall-Match Flag */ + uint8_t PTXOM : 2; /*!< PTx One-Match Flag */ + uint8_t PTXPM : 2; /*!< PTx Period-Match Flag */ + uint8_t MCUPF : 1; /*!< Multi-channel mode updated Flag */ + uint8_t TRPF : 1; /*!< Trap Flag */ + uint8_t TRPS : 1; /*!< Trap State */ + uint8_t TRPIS : 1; /*!< Trap Interrupt Status */ + uint8_t CT0F : 1; /*!< Compare trigger0 Flag */ + uint8_t CT1F : 1; /*!< Compare trigger1 Flag */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTRAWSTATR; /* +0x068 */ + + union { + struct { + uint8_t CCXRIRQ : 4; /*!< Corresponding CCx Rise-Match interrupt active */ + uint8_t CCXFIRQ : 4; /*!< Corresponding CCx Fall-Match interrupt active */ + uint8_t PTXOMIRQ : 2; /*!< Corresponding PTx One-Match interrupt active */ + uint8_t PTXPMIRQ : 2; /*!< Corresponding PTx Period-Match interrupt active */ + uint8_t MCUPFIRQ : 1; /*!< Multi-channel mode updated interrupt active */ + uint8_t : 2; /* (reserved) */ + uint8_t TRPIRQ : 1; /*!< Trap interrupt active */ + uint8_t CT0IRQ : 1; /*!< Compare trigger0 interrupt active */ + uint8_t CT1IRQ : 1; /*!< Compare trigger1 interrupt active */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } INTACTSTATR; /* +0x06C */ + +} PWM_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of PWM SFRS. + */ +#define PWM_SFRS ((__IO PWM_SFRS_t *)0x40010000) + +#endif /* end of __PWM_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/realplum_sfr.h b/app_Indie/drivers/hdf/sfrs/realplum_sfr.h new file mode 100644 index 0000000..b1df7cb --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/realplum_sfr.h @@ -0,0 +1,27 @@ +/* this header brings in the individual files that define the + * struct typdefs for all the special function registers of META + */ + +#ifndef __META_SFR_H__ +#define __META_SFR_H__ + +#include "crga_sfr.h" +#include "pmua_sfr.h" +#include "evthold_sfr.h" +#include "bte_sfr.h" +#include "wica_sfr.h" +#include "wdta_sfr.h" +#include "pwm_sfr.h" +#include "lins_sfr.h" +#include "linm_sfr.h" +#include "adc_sfr.h" +#include "ioctrla_sfr.h" +#include "sysctrla_sfr.h" +#include "gpio_sfr.h" +#include "timer0_sfr.h" +#include "timer1_sfr.h" +#include "timer2_sfr.h" +#include "wdt1_sfr.h" +#include "flash_sfr.h" + +#endif diff --git a/app_Indie/drivers/hdf/sfrs/sar_ctrl_sfr.h b/app_Indie/drivers/hdf/sfrs/sar_ctrl_sfr.h new file mode 100644 index 0000000..6896b27 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/sar_ctrl_sfr.h @@ -0,0 +1,246 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file sar_ctrl_sfr.h + */ + +#ifndef SAR_CTRL_SFR_H__ +#define SAR_CTRL_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for SAR_CTRL. + */ + +typedef struct { + uint16_t DATA; /* +0x000 */ + uint16_t _RESERVED; /* +0x002 */ +}SAR_Data_t; + +typedef struct { + SAR_Data_t DATA[10]; /* +0x000 */ + union { + struct { + uint8_t : 7; /* (reserved) */ + uint8_t ROUND : 1; /*!< ADC round enable */ + uint8_t TRIGSRC : 8; /*!< SAR Converion Trigger Source Selects */ + uint8_t PWMAUXTRIGSEL : 4; /*!< SAR Converion Trigger Selects of PWMAUX */ + uint8_t PWMAUXCHSEL : 3; /*!< PWMAUX Trigger Channel Selects */ + uint8_t TRIGSEL : 1; /*!< SAR Trigger Signal Selects */ + uint8_t TRIGDLY : 8; /*!< trigger delay */ + }; + uint32_t WORD; + } SARCFG; /* +0x028 */ + + union { + struct { + uint8_t ADCSELVINVCMEXT : 1; /*!< Select External Inputs to ADC */ + uint8_t : 6; /* (reserved) */ + uint8_t SARAFEEN : 1; /*!< ADC AFE Enable */ + uint8_t SARPREAMPEN : 8; /*!< adc pre-amp enable */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } AFECTRL; /* +0x02C */ + + union { + struct { + uint8_t SARENAREQ : 8; /*!< SAR ADC Enable */ + uint8_t : 2; /* (reserved) */ + uint8_t DIGRESET : 1; /*!< SAR Digital Part Reset */ + uint8_t : 5; /* (reserved) */ + uint8_t CONVERT : 1; /*!< ADC START/STATUS Register */ + uint8_t : 1; /* (reserved) */ + uint8_t CONT : 1; /*!< Continuous Conversion Enable */ + uint8_t : 5; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } SARCTRL; /* +0x030 */ + + union { + struct { + uint8_t SEQCNT : 4; /*!< Channel Sequence count */ + uint8_t : 1; /* (reserved) */ + uint32_t CH1SEL : 5; /*!< Channel1 Selection !!misaligned!! */ + uint8_t CH2SEL : 5; /*!< Channel2 Selection */ + uint8_t : 1; /* (reserved) */ + uint8_t CH3SEL : 8; /*!< Channel3 Selection */ + uint8_t CH4SEL : 5; /*!< Channel4 Selection */ + uint8_t : 2; /* (reserved) */ + uint8_t TESTBATTERYGAINCHOOSE : 1; /*!< VBAT Gain Select */ + }; + uint32_t WORD; + } ADCCHCONF; /* +0x034 */ + + union { + struct { + uint8_t CH5SEL : 5; /*!< Channel5 Selection */ + uint32_t CH6SEL : 5; /*!< Channel6 Selection !!misaligned!! */ + uint8_t CH7SEL : 5; /*!< Channel7 Selection */ + uint32_t CH8SEL : 5; /*!< Channel8 Selection !!misaligned!! */ + uint32_t CH9SEL : 5; /*!< Channel9 Selection !!misaligned!! */ + uint8_t CH10SEL : 5; /*!< Channel10 Selection */ + uint8_t : 2; /* (reserved) */ + }; + uint32_t WORD; + } ADCCHSELR; /* +0x038 */ + + union { + struct { + uint8_t SAR_INPUT_MODE_CH1 : 2; /*!< CH1 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH2 : 2; /*!< CH2 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH3 : 2; /*!< CH3 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH4 : 2; /*!< CH4 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH5 : 2; /*!< CH5 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH6 : 2; /*!< CH6 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH7 : 2; /*!< CH7 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH8 : 2; /*!< CH8 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH9 : 2; /*!< CH9 AFE Input Modes */ + uint8_t SAR_INPUT_MODE_CH10 : 2; /*!< CH10 AFE Input Modes */ + uint8_t SARINPUTGAINCH1 : 1; /*!< ADC Channel1 input gain */ + uint8_t SARINPUTGAINCH2 : 1; /*!< ADC Channel2 input gain */ + uint8_t SARINPUTGAINCH3 : 1; /*!< ADC Channel3 input gain */ + uint8_t SARINPUTGAINCH4 : 1; /*!< ADC Channel4 input gain */ + uint8_t SARINPUTGAINCH5 : 1; /*!< ADC Channel5 input gain */ + uint8_t SARINPUTGAINCH6 : 1; /*!< ADC Channel6 input gain */ + uint8_t SARINPUTGAINCH7 : 1; /*!< ADC Channel7 input gain */ + uint8_t SARINPUTGAINCH8 : 1; /*!< ADC Channel8 input gain */ + uint8_t SARINPUTGAINCH9 : 1; /*!< ADC Channel9 input gain */ + uint8_t SARINPUTGAINCH10 : 1; /*!< ADC Channel10 input gain */ + uint8_t : 2; /* (reserved) */ + }; + uint32_t WORD; + } ADCCHCTRL0R; /* +0x03C */ + + union { + struct { + uint8_t SAMPCYCCH1 : 4; /*!< Channel1 Sample cycle */ + uint8_t SAMPCYCCH2 : 4; /*!< Channel2 Sample cycle */ + uint8_t SAMPCYCCH3 : 4; /*!< Channel3 Sample cycle */ + uint8_t SAMPCYCCH4 : 4; /*!< Channel4 Sample cycle */ + uint8_t SAMPCYCCH5 : 4; /*!< Channel5 Sample cycle */ + uint8_t SAMPCYCCH6 : 4; /*!< Channel6 Sample cycle */ + uint8_t SAMPCYCCH7 : 4; /*!< Channel7 Sample cycle */ + uint8_t SAMPCYCCH8 : 4; /*!< Channel8 Sample cycle */ + }; + uint32_t WORD; + } ADCCHCTRL1R; /* +0x040 */ + + union { + struct { + uint8_t SAMPCYCCH9 : 4; /*!< Channel9 Sample cycle */ + uint8_t SAMPCYCCH10 : 4; /*!< Channel10 Sample cycle */ + uint8_t ADCVREFSELCH1 : 2; /*!< Channel1 adc vref select */ + uint8_t ADCVREFSELCH2 : 2; /*!< Channel2 adc vref select */ + uint8_t ADCVREFSELCH3 : 2; /*!< Channel3 adc vref select */ + uint8_t ADCVREFSELCH4 : 2; /*!< Channel4 adc vref select */ + uint8_t ADCVREFSELCH5 : 2; /*!< Channel5 adc vref select */ + uint8_t ADCVREFSELCH6 : 2; /*!< Channel6 adc vref select */ + uint8_t ADCVREFSELCH7 : 2; /*!< Channel7 adc vref select */ + uint8_t ADCVREFSELCH8 : 2; /*!< Channel8 adc vref select */ + uint8_t ADCVREFSELCH9 : 2; /*!< Channel9 adc vref select */ + uint8_t ADCVREFSELCH10 : 2; /*!< Channel10 adc vref select */ + uint8_t : 4; /* (reserved) */ + }; + uint32_t WORD; + } ADCCHCTRL2R; /* +0x044 */ + + union { + struct { + union { + struct { + uint8_t INT_CONV_DONE_ENA : 1; /*!< Convert Done Interrupt Enable */ + uint8_t INT_TRIG_CLASH_ENA : 1; /*!< Trigger Clash Interrupt Enable */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } ENABLE; + union { + struct { + uint8_t INT_CONV_DONE_CLR : 1; /*!< Convert Done Interrupt Clear */ + uint8_t INT_TRIG_CLASH_CLR : 1; /*!< Trigger Clash Interrupt Clear */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } CLEAR; + union { + struct { + uint8_t CONV_DONE : 1; /*!< Convert Done */ + uint8_t TRIG_CLASH : 1; /*!< Trigger Clash */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } STATUS; + union { + struct { + uint8_t INT_CONV_DONE : 1; /*!< Convert Done Interrupt */ + uint8_t INT_TRIG_CLASH : 1; /*!< Trigger Clash Interrupt */ + uint8_t : 6; /* (reserved) */ + }; + uint8_t BYTE; + } IRQ; + }; + uint32_t WORD; + } SARINT; /* +0x048 */ + + uint8_t SARCLKDIV; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of SAR_CTRL SFRS. + */ +#define SAR_CTRL_SFRS ((__IO SAR_CTRL_SFRS_t *)0x40013400) + +#endif /* end of __SAR_CTRL_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/spi_sfr.h b/app_Indie/drivers/hdf/sfrs/spi_sfr.h new file mode 100644 index 0000000..6fbd323 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/spi_sfr.h @@ -0,0 +1,143 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file spi_sfr.h + */ + +#ifndef SPI_SFR_H__ +#define SPI_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for SPI. + */ +typedef struct { + + uint8_t RXDATA; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of SPI SFRS. + */ +#define SPI_SFRS ((__IO SPI_SFRS_t *)0x40015000) + +#endif /* end of __SPI_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/sram_sfr.h b/app_Indie/drivers/hdf/sfrs/sram_sfr.h new file mode 100644 index 0000000..6c3c44b --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/sram_sfr.h @@ -0,0 +1,74 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file sram_sfr.h + */ + +#ifndef SRAM_SFR_H__ +#define SRAM_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for SRAM. + */ +typedef struct { + + uint32_t DATA; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of SRAM SFRS. + */ +#define SRAM_SFRS ((__IO SRAM_SFRS_t *)0x20000000) + +#endif /* end of __SRAM_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/syscfg_sfr.h b/app_Indie/drivers/hdf/sfrs/syscfg_sfr.h new file mode 100644 index 0000000..60a19ca --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/syscfg_sfr.h @@ -0,0 +1,149 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file syscfg_sfr.h + */ + +#ifndef SYSCFG_SFR_H__ +#define SYSCFG_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for SYSCFG. + */ +typedef struct { + + union { + struct { + uint8_t GT1INS : 1; /*!< GT1IN Selection */ + uint8_t GT2INS : 1; /*!< GT2IN Selection */ + uint8_t GT3INS : 1; /*!< GT3IN Selection */ + uint8_t GT4INS : 1; /*!< GT4IN Selection */ + uint8_t GT5INS : 1; /*!< GT5IN Selection */ + uint8_t : 3; /* (reserved) */ + uint8_t GT1EXTS : 2; /*!< GT1EXT Selection */ + uint8_t GT2EXTS : 1; /*!< GT2EXT Selection */ + uint8_t GT3EXTS : 1; /*!< GT3EXT Selection */ + uint8_t GT4EXTS : 1; /*!< GT4EXT Selection */ + uint8_t GT5EXTS : 1; /*!< GT5EXT Selection */ + uint8_t : 2; /* (reserved) */ + uint8_t GT1EXTC : 1; /*!< GT1EXT Input Control */ + uint8_t GT2EXTC : 1; /*!< GT2EXT Input Control */ + uint8_t GT3EXTC : 1; /*!< GT3EXT Input Control */ + uint8_t : 5; /* (reserved) */ + uint8_t GT3TRIGS : 8; /*!< GT3 Trigger Select */ + }; + uint32_t WORD; + } GTINSR; /* +0x000 */ + + union { + struct { + uint8_t PT0HRS : 1; /*!< PT0HR Selection */ + uint8_t PT1HRS : 1; /*!< PT1HR Selection */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t PT0HRC : 1; /*!< PT0HR Input Control */ + uint8_t PT1HRC : 1; /*!< PT1HR Input Control */ + uint8_t : 6; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } PWMINSR; /* +0x004 */ + + uint8_t CTINS; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of SYSCFG SFRS. + */ +#define SYSCFG_SFRS ((__IO SYSCFG_SFRS_t *)0x40020000) + +#endif /* end of __SYSCFG_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/sysctrla_sfr.h b/app_Indie/drivers/hdf/sfrs/sysctrla_sfr.h new file mode 100644 index 0000000..e4a3f9c --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/sysctrla_sfr.h @@ -0,0 +1,187 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file sysctrla_sfr.h + */ + +#ifndef SYSCTRLA_SFR_H__ +#define SYSCTRLA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for SYSCTRLA. + */ +typedef struct { + + union { + struct { + uint8_t DEBUG_ACCESS_KEY : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t DEBUG_LOCK : 1; + }; + uint32_t WORD; + } DEBUG_ACCESS_KEY; /* +0x000 */ + + uint8_t DEBUG_ACCESS_ENABLED; /* +0x004 */ + uint8_t _RESERVED_05[3]; /* +0x005 */ + + union { + struct { + uint8_t TRIM_ACCESS_KEY : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t TRIM_LOCK : 1; + }; + uint32_t WORD; + } TRIM_ACCESS_KEY; /* +0x008 */ + + uint8_t TRIM_ACCESS_ENABLED; /* +0x00C */ + uint8_t _RESERVED_0D[3]; /* +0x00D */ + + union { + struct { + uint8_t PMU_ACCESS_KEY : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t PMU_LOCK : 1; + }; + uint32_t WORD; + } PMU_ACCESS_KEY; /* +0x010 */ + + uint8_t PMU_ACCESS_ENABLED; /* +0x014 */ + uint8_t _RESERVED_15[3]; /* +0x015 */ + + union { + struct { + uint8_t TRIM_HF_RC : 8; /*!< High Frequency RC Oscillator trim */ + uint8_t SSCENA : 1; /*!< SSC Enable */ + uint8_t SSCDEEP : 3; /*!< SSC Depth Configuration */ + uint8_t : 4; /* (reserved) */ + uint8_t SSCDIV : 8; /*!< SSC Clock Divider */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } HF_OSC_TRIM; /* +0x018 */ + + union { + struct { + uint8_t TRIM_UHF_RC : 8; /*!< Ultra High Frequency RC Oscillator trim */ + uint8_t UHFSSCENA : 8; /*!< UHF Oscillator SSC Enable */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } UHF_OSC_TRIM; /* +0x01C */ + + union { + struct { + uint8_t CSAPOWEN : 1; /*!< Current sensor amplifier enable */ + uint8_t CSAZEROEN : 1; /*!< Current sensor amplifier offset measure enable */ + uint8_t : 2; /* (reserved) */ + uint8_t CSAGBWSEL : 2; /*!< Current sensor amplifier bandwidth select */ + uint8_t CSAGAINSEL : 2; /*!< Current sensor amplifier gain select */ + uint8_t CSOCPPOWEN : 1; /*!< Current sensor over current protect enable */ + uint8_t CSOCPBWSEL : 1; /*!< Current sensor over current protect comparator high bandwidth enable */ + uint8_t : 2; /* (reserved) */ + uint8_t CSOCPHYSSEL : 2; /*!< Current sensor over current protect comparator hysteresis select */ + uint8_t CS_OCP_DAC_POW_EN : 1; /*!< Current sensor DAC enable */ + uint8_t : 1; /* (reserved) */ + uint8_t CS_OCP_DAC : 8; /*!< Current sensor over current protect threshold level select */ + uint8_t CS_OCP_STS : 1; /*!< Current Sensor Over Current Protetion Status */ + uint8_t : 6; /* (reserved) */ + uint8_t CSOCPIE : 1; /*!< Current Sensor Over Current Protetion interrupt enable */ + }; + uint32_t WORD; + } CSACTRLR; /* +0x020 */ + + union { + struct { + uint8_t DFTCODE : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t DFT_LOCK : 1; + }; + uint32_t WORD; + } DFTCODE; /* +0x024 */ + + uint8_t DFT_ACCESS_ENABLED; /* +0x028 */ + uint8_t _RESERVED_29[3]; /* +0x029 */ + + union { + struct { + uint8_t : 1; /* (reserved) */ + uint8_t FLASHTESTMODESTART : 1; + uint8_t FLASHOSCTESTMODESTART : 1; + uint8_t SRAMBISTMODESTART : 1; + uint8_t : 4; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } DFTTESTMODESTART; /* +0x02C */ + + uint32_t NAME; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of SYSCTRLA SFRS. + */ +#define SYSCTRLA_SFRS ((__IO SYSCTRLA_SFRS_t *)0x40000800) + +#endif /* end of __SYSCTRLA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/trimhv_sfr.h b/app_Indie/drivers/hdf/sfrs/trimhv_sfr.h new file mode 100644 index 0000000..80aa5b4 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/trimhv_sfr.h @@ -0,0 +1,250 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file trimhv_sfr.h + */ + +#ifndef TRIMHV_SFR_H__ +#define TRIMHV_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for TRIMHV. + */ +typedef struct { + + union { + struct { + uint8_t RETAIN0 : 8; /*!< Firmware scratch register 0 */ + uint8_t RETAIN1 : 8; /*!< Firmware scratch register 1 */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } RETAIN; /* +0x000 */ + + uint8_t TRIM_LF_RC; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of TRIMHV SFRS. + */ +#define TRIMHV_SFRS ((__IO TRIMHV_SFRS_t *)0x40000900) + +#endif /* end of __TRIMHV_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/uart0_sfr.h b/app_Indie/drivers/hdf/sfrs/uart0_sfr.h new file mode 100644 index 0000000..ca7dcb4 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/uart0_sfr.h @@ -0,0 +1,244 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file uart0_sfr.h + */ + +#ifndef UART0_SFR_H__ +#define UART0_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for UART0. + */ +typedef struct { + + union { + struct { + uint8_t BYTE : 8; /*!< Data */ + uint8_t DUMMY0 : 8; /*!< Data */ + uint8_t DUMMY1 : 8; /*!< Data */ + uint8_t DUMMY2 : 8; /*!< Data */ + }; + uint32_t WORD; + } DATA; /* +0x000 */ + + union { + struct { + uint8_t FRAMEERROR : 1; /*!< Framing Error */ + uint8_t PARITYERROR : 1; /*!< Parity Error */ + uint8_t BREAKERROR : 1; /*!< Break Error */ + uint8_t : 5; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } UARTDATARECEIVESTATUS; /* +0x004 */ + + union { + struct { + uint8_t ENABLE : 1; + uint8_t ENABLE_STS : 1; /*!< Enable status */ + uint8_t UFIFOSOFTRESET : 1; /*!< FIFO SOFT RESET */ + uint8_t RXXFERCNTCLR : 1; /*!< RX Transfer Counter Clear */ + uint8_t TXXFERCNTCLR : 1; /*!< TX Transfer Counter Clear */ + uint8_t : 3; /* (reserved) */ + uint8_t SIZE : 2; /*!< Transmission word size */ + uint8_t STOP : 1; /*!< Stop bit control */ + uint8_t PARENA : 1; /*!< Parity enable */ + uint8_t PARODD : 1; /*!< Odd parity */ + uint8_t STICKENA : 1; /*!< Sticky parity enable */ + uint8_t : 2; /* (reserved) */ + uint8_t : 6; /* (reserved) */ + uint8_t BREAKENA : 1; /*!< Break enable */ + uint8_t LOOPENA : 1; /*!< Loopback enable */ + uint8_t : 8; /* (reserved) */ + }; + uint32_t WORD; + } MSGCTRL; /* +0x008 */ + + union { + struct { + union { + struct { + uint8_t RXDONE : 1; /*!< Rx Data ready Interrupt Enable */ + uint8_t OVRUNERR : 1; /*!< RX FIFO overflow error Interrupt Enable */ + uint8_t FRMERR : 1; /*!< Framing error Interrupt Enable */ + uint8_t PRTYERR : 1; /*!< Parity Error Interrupt Enable */ + uint8_t BREAKKERR : 1; /*!< Break Error Interrupt Enable */ + uint8_t TXDONE : 1; /*!< Transmission done Interrupt Enable */ + uint8_t RXMULTDONE : 1; /*!< Multiple Receive Transactions Done Interrupt Enable */ + uint8_t TXMULTDONE : 1; /*!< Multiple Transmit Transactions Done Interrupt Enable */ + }; + uint8_t BYTE; + } ENABLE; + union { + struct { + uint8_t RXDONE : 1; /*!< Rx Data ready Interrupt Clear */ + uint8_t OVRUNERR : 1; /*!< RX FIFO overflow error Interrupt Clear */ + uint8_t FRMERR : 1; /*!< Framing error Interrupt Clear */ + uint8_t PRTYERR : 1; /*!< Parity Error Interrupt Clear */ + uint8_t BREAKKERR : 1; /*!< Break Error Interrupt Clear */ + uint8_t TXDONE : 1; /*!< Transmission done Interrupt Clear */ + uint8_t RXMULTDONE : 1; /*!< Multiple Receive Transactions Done Interrupt Clear */ + uint8_t TXMULTDONE : 1; /*!< Multiple Transmit Transactions Done Interrupt Clear */ + }; + uint8_t BYTE; + } CLEAR; + union { + struct { + uint8_t RXDONE : 1; /*!< Rx Data ready */ + uint8_t OVRUNERR : 1; /*!< RX FIFO overflow error */ + uint8_t FRMERR : 1; /*!< Framing error */ + uint8_t PRTYERR : 1; /*!< Parity Error */ + uint8_t BREAKKERR : 1; /*!< Break IRQ */ + uint8_t TXDONE : 1; /*!< Transmission is done */ + uint8_t RXMULTDONE : 1; /*!< Multiple Receive Transactions Done */ + uint8_t TXMULTDONE : 1; /*!< Multiple Transmit Transactions Done */ + }; + uint8_t BYTE; + } STATUS; + union { + struct { + uint8_t RXDONE : 1; /*!< Rx Data ready Interrupt */ + uint8_t OVRUNERR : 1; /*!< RX FIFO overflow error Interrupt */ + uint8_t FRMERR : 1; /*!< Framing error Interrupt */ + uint8_t PRTYERR : 1; /*!< Parity Error Interrupt */ + uint8_t BREAKKERR : 1; /*!< Break Error Interrupt */ + uint8_t TXDONE : 1; /*!< Transmission done Interrupt */ + uint8_t RXMULTDONE : 1; /*!< Multiple Receive Transactions Done Interrupt */ + uint8_t TXMULTDONE : 1; /*!< Multiple Transmit Transactions Done Interrupt */ + }; + uint8_t BYTE; + } IRQ; + }; + uint32_t WORD; + } UARTINT; /* +0x00C */ + + union { + struct { + union { + struct { + uint8_t RXTOUT : 1; /*!< Rx Time-out Interrupt Enable */ + uint8_t UNRUNERR : 1; /*!< RX FIFO underflow error Interrupt Enable */ + uint8_t OVERRUNERR : 1; /*!< TX FIFO overflow error Interrupt Enable */ + uint8_t : 5; /* (reserved) */ + }; + uint8_t BYTE; + } ENABLE; + union { + struct { + uint8_t RXTOUT : 1; /*!< Rx Time-out Interrupt Clear */ + uint8_t UNRUNERR : 1; /*!< RX FIFO underflow error Interrupt Clear */ + uint8_t OVERRUNERR : 1; /*!< TX FIFO overflow error Interrupt Clear */ + uint8_t : 5; /* (reserved) */ + }; + uint8_t BYTE; + } CLEAR; + union { + struct { + uint8_t RXTOUT : 1; /*!< Rx Time-out */ + uint8_t UNRUNERR : 1; /*!< RX FIFO underflow error */ + uint8_t OVERRUNERR : 1; /*!< TX FIFO overflow error */ + uint8_t : 5; /* (reserved) */ + }; + uint8_t BYTE; + } STATUS; + union { + struct { + uint8_t RXTOUT : 1; /*!< Rx Time-out Interrupt */ + uint8_t UNRUNERR : 1; /*!< RX FIFO underflow error Interrupt */ + uint8_t OVERRUNERR : 1; /*!< TX FIFO overflow error Interrupt */ + uint8_t : 5; /* (reserved) */ + }; + uint8_t BYTE; + } IRQ; + }; + uint32_t WORD; + } UARTINT2; /* +0x010 */ + + union { + struct { + uint8_t FDIV : 3; /*!< Fractional divider */ + uint32_t BAUDDIV : 16; /*!< Baud rate divider !!misaligned!! */ + uint8_t : 5; /* (reserved) */ + uint8_t OSR : 5; /*!< Over-sampling ratio */ + uint8_t UADVANCE : 1; /*!< Advance Register */ + uint8_t URETARD : 1; /*!< Retard Register */ + uint8_t : 1; /* (reserved) */ + }; + uint32_t WORD; + } UARTBAUD; /* +0x014 */ + + union { + struct { + uint8_t : 1; /* (reserved) */ + uint8_t RXEMPTY : 1; /*!< Reception FIFO empty */ + uint8_t RXFULL : 1; /*!< Reception FIFO full */ + uint8_t RXCOUNT : 5; /*!< Reception FIFO current count */ + uint8_t : 1; /* (reserved) */ + uint8_t TXEMPTY : 1; /*!< Transmit FIFO empty */ + uint8_t TXFULL : 1; /*!< Transmit FIFO full */ + uint8_t TXCOUNT : 5; /*!< Transmit FIFO current count */ + uint8_t RXMULTIPLEXFERDONECNT : 8; /*!< Receive Data Count Interrupt */ + uint8_t TXMULTIPLEXFERDONECNT : 8; /*!< Transmit Data Count Interrupt */ + }; + uint32_t WORD; + } UARTFIFO; /* +0x018 */ + +} UART0_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of UART0 SFRS. + */ +#define UART0_SFRS ((__IO UART0_SFRS_t *)0x40015400) + +#endif /* end of __UART0_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/wdt1_sfr.h b/app_Indie/drivers/hdf/sfrs/wdt1_sfr.h new file mode 100644 index 0000000..fe39fc0 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/wdt1_sfr.h @@ -0,0 +1,86 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file wdt1_sfr.h + */ + +#ifndef WDT1_SFR_H__ +#define WDT1_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for WDT1. + */ +typedef struct { + + union { + struct { + uint8_t ENA : 1; /*!< WDT Enable */ + uint8_t RSTEN : 1; /*!< Reset enable */ + uint8_t RSTFLAG : 1; /*!< Reset flag */ + uint8_t PRESET : 3; + uint8_t : 2; /* (reserved) */ + uint32_t : 24; /* (reserved) */ + }; + uint32_t WORD; + } CFG; /* +0x000 */ + + uint32_t KEY; /* +0x004 */ + +} WDT1_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of WDT1 SFRS. + */ +#define WDT1_SFRS ((__IO WDT1_SFRS_t *)0x50021030) + +#endif /* end of __WDT1_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/wdta_sfr.h b/app_Indie/drivers/hdf/sfrs/wdta_sfr.h new file mode 100644 index 0000000..81f893c --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/wdta_sfr.h @@ -0,0 +1,140 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file wdta_sfr.h + */ + +#ifndef WDTA_SFR_H__ +#define WDTA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for WDTA. + */ +typedef struct { + + union { + struct { + uint8_t UPDATE : 1; /*!< Window Mode Enable */ + uint8_t RUNNING : 1; /*!< Running status */ + uint8_t : 6; /* (reserved) */ + uint8_t TIMEOUTSEL : 3; /*!< Timeout select */ + uint8_t WINOPENENA : 1; /*!< Window Mode Enable */ + uint8_t WINOPENSEL : 2; /*!< Window Mode open select */ + uint8_t WINOPENFLAG : 1; /*!< Window open flag */ + uint8_t : 1; /* (reserved) */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } CTRL; /* +0x000 */ + + union { + struct { + uint8_t STOP : 8; + uint8_t : 8; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint8_t : 7; /* (reserved) */ + uint8_t STOP_LOCK : 1; + }; + uint32_t WORD; + } STOPR; /* +0x004 */ + + uint32_t CLEAR; /* +0x008 */ + + uint32_t CNTVAL; /*= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of WDTA SFRS. + */ +#define WDTA_SFRS ((__IO WDTA_SFRS_t *)0x40001400) + +#endif /* end of __WDTA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hdf/sfrs/wica_sfr.h b/app_Indie/drivers/hdf/sfrs/wica_sfr.h new file mode 100644 index 0000000..c2c0b34 --- /dev/null +++ b/app_Indie/drivers/hdf/sfrs/wica_sfr.h @@ -0,0 +1,103 @@ +/** + * @copyright 2022 indie Semiconductor + * + * This file is proprietary to indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of indie Semiconductor. + * + * @file wica_sfr.h + */ + +#ifndef WICA_SFR_H__ +#define WICA_SFR_H__ + +#include + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief A structure to represent Special Function Registers for WICA. + */ +typedef struct { + + union { + struct { + uint8_t LINS_ENA : 1; /*!< LIN Slave Wakeup Enable */ + uint8_t LINS_WICA_SEL : 1; /*!< LIN Slave Wakeup Source Select at Deepsleep mode */ + uint8_t TIMER_ENA : 1; /*!< Wakeup Timer Enable */ + uint8_t : 2; /* (reserved) */ + uint32_t TIMER_TAPSEL : 4; /*!< WakeUp Timer Tap Select !!misaligned!! */ + uint8_t LINS_IRQENA : 1; /*!< LIN Slave Wakeup Interrupt Enable */ + uint8_t TIMER_IRQENA : 1; /*!< Timer Wakeup Interrupt Enable */ + uint8_t : 1; /* (reserved) */ + uint8_t LINS_IRQCLR : 1; /*!< clear the wulin_irq */ + uint8_t : 1; /* (reserved) */ + uint8_t TIMER_IRQCLR : 1; /*!< clear the wutimer_irq */ + uint8_t : 1; /* (reserved) */ + uint16_t : 16; /* (reserved) */ + }; + uint32_t WORD; + } CTRL; /* +0x000 */ + + union { + struct { + uint8_t LINS : 1; /*!< LIN Slave Wakeup Status */ + uint8_t : 1; /* (reserved) */ + uint8_t TIMER : 1; /*!< Wakeup Timer Status */ + uint8_t : 5; /* (reserved) */ + uint8_t : 8; /* (reserved) */ + uint16_t TIMERCNT : 16; /*!< Wakeup Timer Counter Value */ + }; + uint32_t WORD; + } STATUS; /* +0x004 */ + +} WICA_SFRS_t; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + * @brief The starting address of WICA SFRS. + */ +#define WICA_SFRS ((__IO WICA_SFRS_t *)0x40001000) + +#endif /* end of __WICA_SFR_H__ section */ + + diff --git a/app_Indie/drivers/hwcfg/inc/hwcfg.h b/app_Indie/drivers/hwcfg/inc/hwcfg.h new file mode 100644 index 0000000..aded0ba --- /dev/null +++ b/app_Indie/drivers/hwcfg/inc/hwcfg.h @@ -0,0 +1,118 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file hwcfg.h + */ + +#ifndef HWCFG_H__ +#define HWCFG_H__ + +#include + +typedef struct{ + uint16_t LED_2mA_TRIMCODE; + uint16_t LED_2mA_Current_Value;/* uA */ + uint16_t LED_30mA_TRIMCODE; + uint16_t LED_30mA_Current_Value;/* uA */ + uint16_t LED_PN1P5V_VOLT; + uint16_t LED_PN1P5V_CODE; + uint16_t LED_PN4P0V_VOLT; + uint16_t LED_PN4P0V_CODE; +}LedChannelParam_t; + + +/** + * @brief A structure to represent the data in hardware config block. + */ +typedef union { + struct { + struct { + uint32_t crc32; + struct { + uint8_t NAME[4]; + uint8_t VERSION; + uint8_t LOT_NO[3]; + uint32_t ATPR; + uint32_t CHIPID; + uint32_t TP_SVN_R; + }CHIP;/*20*/ + uint8_t CUSTOMER_INFO[24]; + uint8_t BANDGAP_CODE_UNUSED; + uint8_t RESVED0; + uint16_t BANDGAP_VOLT_mV; /* in mV */ + uint16_t ADC_0V5_CODE; /* ADC count @0.5V */ + uint16_t ADC_1V0_CODE; /* ADC count @1.0V */ + uint16_t TSENSOR_mV_25C; + uint16_t TSENSOR_CODE_25C__UNUSED; + uint16_t VBAT_CODE_13V5; /* ADC count @VBAT=13.5V*/ + uint16_t VBAT_CODE_8V0; /* ADC count @VBAT=8.0V */ + uint8_t CLK_RC_LF_32KHz_TRIMCODE; + uint8_t RESVED1; + uint8_t CLK_RC_LF_256KHz_TRIMCODE; + uint8_t RESVED2; + uint8_t CLK_RC_HF_16MHz_TRIMCODE; + uint8_t RESVED3; + uint16_t V2I_TRIMCODE; + uint16_t CLK_RC_HF_16MHz_FREQ; /* KHz */ + uint8_t RESVED4[6]; + }; + LedChannelParam_t LED[3]; + }; + uint8_t payload[512]; + +} HWCFG_SFRS_t; + +/** + * @brief The starting address of hardware config block. + */ +//#define HWCFG_SFRS ((__IO HWCFG_SFRS_t *) (0x00010200)) +#define HWCFG_SFRS ((__IO HWCFG_SFRS_t *) (0x00000000)) + +#define E_HWCFG_ADC_RANGE_FULL 255 +#define E_HWCFG_ADC_RANGE_ZERO 0 +#define E_HWCFG_ADC_VBG 1220U /* 1.22V */ + +/** + * @brief Get High Frequency RC clock trim value. + * + * @return The trim value stored in flash memory. + */ +uint8_t HWCFG_GetRCHFClockCalibValue(void); + +/** + * @brief Get Low Frequency RC clock trim value. + * + * @return The trim value stored in flash memory. + */ +uint8_t HWCFG_GetRCLFClockCalibValue(void); + +/** + * @brief Get band gap voltage. + * + * @return The trim value stored in flash memory. + */ +uint16_t HWCFG_GetVBG(void); + +/** + * @brief Get the version of calibration data. + * + * @return The version for this calibration data block. + */ +uint32_t HWCFG_GetCalibrationVersion(void); + +uint8_t HWCFG_GetV2ITrimValue(void); +uint16_t HWCFG_GetLEDTrimValue(uint8_t ledIndex); +uint8_t HWCFG_GetOffLEDTrimValue(void); + + +void HWCFG_TrimAccessUnlock(void); +void HWCFG_TrimAccessLockUntilReset(void); + + +#endif /* __HWCFG_H__ */ + diff --git a/app_Indie/drivers/hwcfg/src/hwcfg.c b/app_Indie/drivers/hwcfg/src/hwcfg.c new file mode 100644 index 0000000..744a93f --- /dev/null +++ b/app_Indie/drivers/hwcfg/src/hwcfg.c @@ -0,0 +1,106 @@ +/** + * @copyright 2017 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file hwcfg.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include "hwcfg.h" + + +uint8_t HWCFG_GetRCHFClockCalibValue(void) +{ + uint8_t trim = HWCFG_SFRS->CLK_RC_HF_16MHz_TRIMCODE; + if (trim == 0xFFU){ + trim = 0xB6; + } + return trim; +} + + +uint8_t HWCFG_GetRCLFClockCalibValue(void) +{ + uint8_t trim = HWCFG_SFRS->CLK_RC_LF_256KHz_TRIMCODE; + if (trim == 0xFFU){ + trim = 0xAAU; + } + return trim; +} + + +uint16_t HWCFG_GetVBG(void) +{ + uint16_t volt = HWCFG_SFRS->BANDGAP_VOLT_mV; + + if (volt == 0xFFU){ + volt = E_HWCFG_ADC_VBG; + } + return volt; +} + +/** + * @brief Get the version of calibration data. + * + * @return The version for this calibration data block. + */ +uint32_t HWCFG_GetCalibrationVersion(void) +{ + uint32_t version = HWCFG_SFRS->CHIP.VERSION; + return version; + +} + +uint8_t HWCFG_GetV2ITrimValue(void) +{ + uint8_t trimValue = (uint8_t)HWCFG_SFRS->V2I_TRIMCODE; + if (trimValue == 0xFFU){ + trimValue = 0x80U; + } + return trimValue; +} + + +uint16_t HWCFG_GetLEDTrimValue(uint8_t ledIndex) +{ + uint16_t trimValue = HWCFG_SFRS->LED[ledIndex].LED_30mA_TRIMCODE; + if (trimValue > 0x1FFU){ + trimValue = 250U; /* 120uA*250 = 30mA */ + } + return trimValue; +} + + +uint8_t HWCFG_GetOffLEDTrimValue(void) +{ + uint16_t trimValue = HWCFG_SFRS->LED[0].LED_2mA_TRIMCODE; + + if (trimValue >= 255U){ + trimValue = 200U; + } + return (uint8_t)trimValue; +} + + +void HWCFG_TrimAccessUnlock(void) +{ + SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU; +} + + +void HWCFG_TrimAccessLockUntilReset(void) +{ + SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_LOCK = 1U; +} + + + diff --git a/app_Indie/metaLite.eww b/app_Indie/metaLite.eww new file mode 100644 index 0000000..3604857 --- /dev/null +++ b/app_Indie/metaLite.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\application.ewp + + + diff --git a/app_Indie/metaLite_app.icf b/app_Indie/metaLite_app.icf new file mode 100644 index 0000000..b5a3a1e --- /dev/null +++ b/app_Indie/metaLite_app.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000080; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000BFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/app_Indie/settings/application.Release.cspy.bat b/app_Indie/settings/application.Release.cspy.bat new file mode 100644 index 0000000..3108c56 --- /dev/null +++ b/app_Indie/settings/application.Release.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.general.xcl" --backend -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.general.xcl" "--debug_file=%~1" --backend -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/app_Indie/settings/application.Release.cspy.ps1 b/app_Indie/settings/application.Release.cspy.ps1 new file mode 100644 index 0000000..32f1ff1 --- /dev/null +++ b/app_Indie/settings/application.Release.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.general.xcl" --backend -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.driver.xcl" +} +else +{ +& "E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.general.xcl" --debug_file=$debugfile --backend -f "F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\settings\application.Release.driver.xcl" +} diff --git a/app_Indie/settings/application.Release.driver.xcl b/app_Indie/settings/application.Release.driver.xcl new file mode 100644 index 0000000..ec2c577 --- /dev/null +++ b/app_Indie/settings/application.Release.driver.xcl @@ -0,0 +1,25 @@ +"--endian=little" + +"--cpu=Cortex-M0" + +"--fpu=None" + +"--drv_verify_download" + +"--semihosting=none" + +"--device=metaLite" + +"--drv_communication=USB0" + +"--drv_interface_speed=1000" + +"--jlink_reset_strategy=0,0" + +"--drv_interface=SWD" + +"--drv_catch_exceptions=0x000" + + + + diff --git a/app_Indie/settings/application.Release.general.xcl b/app_Indie/settings/application.Release.general.xcl new file mode 100644 index 0000000..9981adf --- /dev/null +++ b/app_Indie/settings/application.Release.general.xcl @@ -0,0 +1,13 @@ +"E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armproc.dll" + +"E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armjlink2.dll" + +"F:\FCB_project\temp\K74\K74B_CODE\libdev_metaLite_app.00.00.00.00.0003_liu\Release\Exe\realplumPro_app.out" + +--plugin="E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armbat.dll" + +--flash_loader="E:\IAR Systems\Embedded Workbench 8.3\arm\config\flashloader\IndieSemi\FlashLoader_metaLite.board" + + + + diff --git a/app_Indie/settings/application.crun b/app_Indie/settings/application.crun new file mode 100644 index 0000000..d71ea55 --- /dev/null +++ b/app_Indie/settings/application.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/app_Indie/usr/common/appConfig.h b/app_Indie/usr/common/appConfig.h new file mode 100644 index 0000000..a883d87 --- /dev/null +++ b/app_Indie/usr/common/appConfig.h @@ -0,0 +1,58 @@ +#ifndef APP_CONFIG_H__ +#define APP_CONFIG_H__ + +#include +#include +#include + +#define PRAGMA(x) _Pragma(#x) +#define BEGIN_PACK PRAGMA(pack(push, 1)) +#define END_PACK PRAGMA(pack(pop)) + +#define LIN_STACK_TYPE_LIN2_2A (0U) +#define LIN_STACK_TYPE_SAEJ2602 (1U) +#define LIN_STACK_TYPE_PRIVATE (2U) + +#define LIN_STACK_TYPE LIN_STACK_TYPE_LIN2_2A + +#define Divide_2 (0U) +#define Divide_6 (1U) + +#define control_type Divide_6 + + +#define SDK_APPL_VERSION (0x0001U) +/* ************************hardware config ********************************/ +#define MAIN_CPU_CLOCK 16U /*MHz*/ + +#if MAIN_CPU_CLOCK == 16U + #define SYS_MAIN_CLOCK_DIV CLOCK_DIV_1 +#else + #error MAIN_CPU_CLOCK MUST BE 16MHz!*/ +#endif + +#define ROOM_TEMPERATURE (24) /*Celsius degree*/ + + +/* ************************PWMs config ********************************/ +/* pwm resolution settings*/ +#define PWM_VALUE_MAX_POS (16U) +#define PWM_VALUE_MAX ((1UL << PWM_VALUE_MAX_POS) -1UL) + + +#define WATCH_DOG_EN (0U) + +/* ************************debug config *******************************/ +#define ENABLE_FUNCTION_VALIDATION (0U) +#define CODE_DEBUG_EN 1 + +#if CODE_DEBUG_EN == 1 + #include + #include + #include + #define DEBUG_OUT(...) printf(__VA_ARGS__) +#else + #define DEBUG_OUT(...) +#endif + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/applicationTask.c b/app_Indie/usr/common/applicationTask.c new file mode 100644 index 0000000..5542710 --- /dev/null +++ b/app_Indie/usr/common/applicationTask.c @@ -0,0 +1,85 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file applicationTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include + +/*static uint8_t ledNum = LED0;*/ +static TaskState_t applState = TASK_STATE_INIT; +void ApplTimerExpired(SoftTimer_t *timer); + + +static uint8_t LED_State = 0U; + + +uint8_t APPL_GetLEDState(void) +{ + return LED_State; +} + + + +static SoftTimer_t ApplTimer = { + .mode = TIMER_PERIODIC_MODE, + .interval = 50U, + .handler = ApplTimerExpired +}; + + +void ApplTimerExpired(SoftTimer_t *timer) +{ + static uint8_t index = 0U; + if (index == 0U){ + index = 1U; + }else{ + index = 0; + + } +} + +void APPL_TaskHandler(void) +{ + switch(applState){ + case TASK_STATE_INIT: + SoftTimer_Start(&ApplTimer); + applState = TASK_STATE_ACTIVE; + break; + case TASK_STATE_ACTIVE: + break; + default: + break; + } +} + + +void APPL_HandleControlCommands(LIN_Device_Frame_t const *frame) +{ + +} + +/***************************************************************/ + +static SoftTimer_t KeyScanTimer = { + .mode = TIMER_PERIODIC_MODE, + .interval = 5U, + .handler = KeyScanTimerExpired +}; + +void KeyScanTimerExpired(SoftTimer_t *timer) +{ + + +} diff --git a/app_Indie/usr/common/applicationTask.h b/app_Indie/usr/common/applicationTask.h new file mode 100644 index 0000000..2c5b28b --- /dev/null +++ b/app_Indie/usr/common/applicationTask.h @@ -0,0 +1,44 @@ +#ifndef _APPLICATION_H +#define _APPLICATION_H +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define APP_DIAG_GET_SDK_VERSION (0x0FU) + +BEGIN_PACK + +typedef struct{ + uint16_t sdkApplication; + lin_stack_version_t linStack; +}CommVersion_t; + +typedef struct{ + uint16_t command; + union{ + CommVersion_t Version; + }; +}CommLedParamInfo_t; + +END_PACK + + +uint8_t APPL_GetLEDState(void); +uint8_t TransferMotorPhyParamtobuffBy3C(uint16_t *buff,uint8_t leng); +void Transfer3CdataToPDS(uint16_t *buff,uint8_t leng); +void APPL_TaskHandler(void); +void APPL_HandleControlCommands(LIN_Device_Frame_t const *frame); +/* Response enable */ +uint8_t APPL_PrepareLedParamRequest(uint8_t reqSid,uint8_t *const dataBuff, DiagPublishInfo_t *const diagRsp); +uint8_t APPL_HandleLedParamConfigRequest(uint8_t reqSid,uint8_t *const dataBuff,DiagPublishInfo_t *const diagRsp); + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/crc32.c b/app_Indie/usr/common/crc32.c new file mode 100644 index 0000000..3dafa53 --- /dev/null +++ b/app_Indie/usr/common/crc32.c @@ -0,0 +1,35 @@ +#include + + +static uint32_t CRC32_Table[256U]; + + +void CRC32_Init(void) +{ + uint32_t c; + + for (uint32_t i = 0U; i < 256U; i++) { + c = i; + for (uint32_t j = 0U; j < 8U; j++) { + if ((c & 0x01U)!= 0U){ + c = 0xEDB88320UL ^ (c >> 1U); + }else{ + c = c >> 1U; + } + } + CRC32_Table[i] = c; + } +} + + +uint32_t CRC32_GetRunTimeCRC32(uint8_t *pBuf ,uint16_t length) +{ + uint32_t retCRCValue = 0xFFFFFFFFU; + for (uint16_t i = 0; i < length; i++){ + retCRCValue=CRC32_Table[(retCRCValue ^ pBuf[i]) & 0xFFU] ^ (retCRCValue >> 8U); + } + return (retCRCValue^0xFFFFFFFFU); +} + + + diff --git a/app_Indie/usr/common/crc32.h b/app_Indie/usr/common/crc32.h new file mode 100644 index 0000000..10e3d15 --- /dev/null +++ b/app_Indie/usr/common/crc32.h @@ -0,0 +1,26 @@ +#ifndef CRC32_H_ +#define CRC32_H_ + +#include +#include +#include + + +void CRC32_Init(void); +uint32_t CRC32_GetRunTimeCRC32(uint8_t *pBuf ,uint16_t length); + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/isrfuncs.h b/app_Indie/usr/common/isrfuncs.h new file mode 100644 index 0000000..7597bad --- /dev/null +++ b/app_Indie/usr/common/isrfuncs.h @@ -0,0 +1,77 @@ +#ifndef ISR_FUNCS_H_ +#define ISR_FUNCS_H_ + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void IOCTRLA_Handler(void); +void OVTEMP_Handler(void); +void GPIO_Handler(void); +void PWM_AUX_Handler(void); +void GT4_5_Handler(void); + +void WUTIMER_Handler(void); +void WatchdogA_Handler(void); +void ADC_Handler(void); +void SPI_Handler(void); +void WULINS_Handler(void); + +void UART0_Handler(void); +void Divider_Handler(void); +void LIN_Handler(void); +void FlashEcc_Handler(void); +void RamEcc_Handler(void); + +void GT1_Handler(void); +void GT2_Handler(void); +void GT3_Handler(void); +void CT2_Handler(void); +void CT3_Handler(void); + +void CT4_Handler(void); +void CT5_Handler(void); +void CT6_Handler(void); +void CR_Handler(void); +void PWM_INTOL0_Handler(void); + +void PWM_INTOL1_Handler(void); +void PWM_INTOL2_Handler(void); +void PWM_INTOL3_Handler(void); +void BOR_Handler(void); +void UV_OV_Handler(void); + +void CSA_OCP_Handler(void); +void Lullaby_Handler(void); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linSlaveTask.h b/app_Indie/usr/common/linSlaveTask.h new file mode 100644 index 0000000..5c2f321 --- /dev/null +++ b/app_Indie/usr/common/linSlaveTask.h @@ -0,0 +1,86 @@ +#ifndef _LINS_TASK_H +#define _LINS_TASK_H + +#include +#include + + +/** +* @brief A structure to represent LIN frame information. +*/ + +#define N_AS (1000) +#define N_CR (1000) + +#define LINS_FUNCTION_ID_SNPD_FORCE_SWITCH_ON (0xAA00U) +#define LINS_FUNCTION_ID_SNPD_INIT (0xAA01U) +#define LINS_FUNCTION_ID_SNPD_ASSIGN_NAD (0xAA02U) +#define LINS_FUNCTION_ID_SNPD_STORAGE (0xAA03U) +#define LINS_FUNCTION_ID_SNPD_EXIT (0xAA04U) + +#define LINS_SUPPLIER_ID (0x0123U) +#define LINS_FUNCTION_ID (0x0123U) +#define LINS_VARIANT (0x01U) +#define LINS_SERIAL_NO (0x01234567U) +#define LINS_FW_VERSION (0x0123U) +#define LINS_HW_VERSION (0x0001U) + +#define LIN_SID_APP_DIAG_MOTOR_GET_CONFIG (0xBAU) /* single pdu receive, multi pdu response */ +#define LIN_SID_APP_DIAG_MOTOR_SET_CONFIG (0xBBU) /* multi pdu receive, single pdu response */ +#define LIN_SID_APP_DIAG_SINGLE_PDU_RECV_MULTI_RSP (0x22U) +#define LIN_SID_APP_DIAG_MULTI_PDU_RECV_SINGLE_RSP (0x2EU) +#define LIN_SID_APP_DIAG_MULTI_PDU_RECV_MULTI_RSP (0x2FU) + + +#define LIN_SID_APP_DIAG_BOOT_MODE (0x20U) +#define BOOT_MODE_HANDSHAKE (0x00U) +#define BOOT_MODE_MAGIC_KEY_HANDSHAKE (0x5A5A55AAU) + +/* *****************LIN configuration default value **************************/ +#if LIN_STACK_TYPE == LIN_STACK_TYPE_SAEJ2602 + #define INIT_LINS_NAD_ADDR (0x6FU) /* NAD range is 0x60-0x6D,defalut*/ + #if (INIT_LINS_NAD_ADDR>0x6FU) + #error INIT_LINS_NAD_ADDR must be within 0x60U-0x6FU!!! + #endif + + #define MESSAGE_ID_BLOCK_COUNT (0x08U) /* MESSAGE_ID_BLOCK_COUNT = 2^n n= 2,3,4.. */ + #if (MESSAGE_ID_BLOCK_COUNT != 4U && MESSAGE_ID_BLOCK_COUNT != 8U && MESSAGE_ID_BLOCK_COUNT != 16U) + #error Invalid MESSAGE_ID_BLOCK_COUNT count !!! + #elif ((INIT_LINS_NAD_ADDR == 0x6CU || INIT_LINS_NAD_ADDR == 0x6DU) && MESSAGE_ID_BLOCK_COUNT != 4U) + #error MESSAGE_ID_BLOCK_COUNT must be 4 when NAD is 0x6C or 0x6D!!! + #endif + + /* it's only a reference, the real FID number is based on NAD according to SAEJ2602 */ + #define DEFAULT_LINS_FID0 (0x00U) + #define DEFAULT_LINS_FID1 (0x01U) + #define DEFAULT_LINS_FID2 (0x02U) + #define DEFAULT_LINS_FID3 (0x03U) + #define DEFAULT_LINS_FID4 (0x04U) + #define DEFAULT_LINS_FID5 (0x05U) + #define DEFAULT_LINS_FID6 (0x06U) + #define DEFAULT_LINS_FID7 (0x07U) + +#else + + #define INIT_LINS_NAD_ADDR (0x01U) + #define DEFAULT_LINS_FID_SIZE (0x03U) /* count number defined by user */ + + /* FID number is set by user */ + #define DEFAULT_LINS_FID0 (0x00U) + #define DEFAULT_LINS_FID1 (0x06U) + #define DEFAULT_LINS_FID2 (0x08U) + + + void LINS_EventTriggered_ISR(void); +#endif + + +void LINS_TaskHandler(void); +LIN_Device_Frame_t volatile *LINS_GetUcndFramesTable(uint8_t *tableItemsCount); +void LINS_SendWakeUpSignal_ISR(void); +uint8_t LINS_GetPIDFromFID(uint8_t frameId); +void LINS_SetDeviceUnconfigured(void); +uint8_t LINS_TransferMotorPhyParamtobuffBy3C(uint16_t *buff,uint8_t leng); +void LINS_Transfer3CdataToPDS(uint16_t *buff,uint8_t leng); + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linsNodeCfgIdentify.c b/app_Indie/usr/common/linsNodeCfgIdentify.c new file mode 100644 index 0000000..9f25325 --- /dev/null +++ b/app_Indie/usr/common/linsNodeCfgIdentify.c @@ -0,0 +1,210 @@ +/** + * @copyright 2021 Indie microcontroller. + * + * This file is proprietary to Indie microcontroller. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie microcontroller. + * + * @file linsNodeCfgIdentify.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2021/07/06 + */ + +#include +#include +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_LIN2_2A + +static LINClusterParams_t *linParams = NULL; +static LIN_Device_Frame_t volatile *frameTable = NULL; + + +void LNCI_Init(void) +{ + uint8_t tableItemsCount; + /* get lin information from flash storage */ + linParams = PDS_GetLINParam(); + /* get frame table information */ + frameTable = LINS_GetUcndFramesTable(&tableItemsCount); + + for (uint8_t i = 0U; i < tableItemsCount; i++){ + frameTable[i].frame_id = linParams->frameInfo[i].frameId; + frameTable[i].frameIsValid = linParams->frameInfo[i].frameIsValid; + } +} + +uint8_t LNCI_HandleNodeCfgIdentifyRequest(const DiagSubscribeInfo_t *const diagReq,DiagPublishInfo_t *const diagRsp) +{ + uint8_t response = FALSE; + if (diagReq->sid == LIN_SID_ASSIGN_NAD && diagReq->packLength == sizeof(AssignNAD_t)){/* Assign NAD */ + /* + 4.2.5.1 Assign NAD + Assign NAD is used to resolve conflicting NADs in LIN clusters built using off-theshelves slave nodes or reused slave nodes. + This request uses the initial NAD (or the NAD wildcard); this is to avoid the risk of losing the address of a slave node. The NAD + used for the response shall be the same as in the request, i.e. the initial NAD. + */ + uint8_t nad = ls_read_nad_from_master(); + if (nad == INIT_LINS_NAD_ADDR || nad == LIN_NAD_WILDCARD){ + AssignNAD_t *assignNAD = (AssignNAD_t *)((void *)diagReq->payload); + if ((assignNAD->supplierID == LINS_SUPPLIER_ID || assignNAD->supplierID == LIN_SUPPLIER_ID_WILDCARD)&& + (assignNAD->functionID == LINS_FUNCTION_ID || assignNAD->functionID == LIN_FUNCTION_ID_WILDCARD)){ + /* A response shall only be sent if the NAD, the Supplier ID and the Function ID match. If successful */ + if (assignNAD->newNAD > 0U){ + diagRsp->packLength = 0U; + linParams->nad = assignNAD->newNAD; + ls_set_nad(assignNAD->newNAD); /* set nad to lin stack */ + response = TRUE; + } + } + } + }else if (diagReq->sid == LIN_SID_SAVE_CONFIGURATION && diagReq->packLength == 0x00U){ /* Save Configuration */ + /* + 4.2.5.4 Save Configuration + This service tells the slave node(s) that the slave application shall save the current + configuration. The save configuration request shall be structured as shown in + Table 4.14. This service is used to notify a slave node to store its configuration. + A configuration in the slave node may be valid even without the master node using this + request (i.e. the slave node does not have to wait for this request to have a valid configuration). + */ + diagRsp->packLength = 0U; + response = TRUE; + //TM_PostTask(TASK_ID_PDS); /*start persistance data storage (PDS )task */ + }else if (diagReq->sid == LIN_SID_READ_BY_ID && diagReq->packLength == sizeof(ReadByIdReq_t)){ /* Read by Identifier */ + ReadByIdReq_t *readById = (ReadByIdReq_t *)((void*)diagReq->payload); + if ((readById->supplierID == LINS_SUPPLIER_ID || readById->supplierID == LIN_SUPPLIER_ID_WILDCARD)&& + (readById->functionID == LINS_FUNCTION_ID || readById->functionID == LIN_FUNCTION_ID_WILDCARD)){ + /* + 4.2.6.1 Read by identifier + It is possible to read the supplier identity and other properties from a slave node using + the request in Table 4.18. + */ + if (readById->identifier == 0U){ + /* LIN Product Identification */ + ReadByIdProductIdRsp_t *rsp = (ReadByIdProductIdRsp_t *)((void *)diagRsp->payload); + rsp->supplierID = LINS_SUPPLIER_ID; + rsp->functionID = LINS_FUNCTION_ID; + rsp->variant = LINS_VARIANT; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdProductIdRsp_t); + response = TRUE; + }else if (readById->identifier == 1U){ + /* Serial number */ + ReadByIdSerialNoRsp_t *rsp = (ReadByIdSerialNoRsp_t *)((void *)diagRsp->payload); + rsp->serialNo = LINS_SERIAL_NO; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdSerialNoRsp_t); + response = TRUE; + }else{ + /* + If the slave is not supporting this request or could not process the request it will + respond according to Table 4.21. + */ + ReadByIdNakRsp_t *rsp = (ReadByIdNakRsp_t *)((void *)diagRsp->payload); + diagRsp->sid = 0x7FU; + rsp->sid = LIN_SID_READ_BY_ID; + rsp->errorCode = 0x12U; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdNakRsp_t); + response = TRUE; + } + } + }else if (diagReq->sid == LIN_SID_ASSIGN_FRAME_ID_RANGE && diagReq->packLength == sizeof(AssignFrameIDRange_t)){ /* Assign frame identifier range */ + AssignFrameIDRange_t *assignFrameIDRng = (AssignFrameIDRange_t *)((void *)diagReq->payload); + uint8_t pid; + uint8_t invalid = 0U; + /* + 4.2.5.5 Assign frame ID range + It is important to notice that the request provides the protected identifier, i.e. the frame + identifier and its parity. Furthermore, frames with frame identifiers 60 (0x3C) to 63 + (0x3F) can not be changed (diagnostic frames and reserved frames) + */ + for (uint8_t i = 0U; i< 4U;i++){ + if (assignFrameIDRng->pid[i] != LIN_FRAME_ID_DONOTCARE){ + pid = assignFrameIDRng->pid[i] & 0x3FU; + if (pid >= 0x3CU && pid <= 0x3FU){ + /* the request is fail for the FID is invalid*/ + invalid = 1U; + break; + } + } + } + /* PID is not in the range from 0x3C to 0x3D */ + if (invalid == 0U){ + uint8_t tableItemsCount; + LIN_Device_Frame_t volatile *unconditionalTable = LINS_GetUcndFramesTable(&tableItemsCount); + /* startIndex should be less then unconditional Table size */ + if (assignFrameIDRng->startIndex < tableItemsCount){ + /* + 4.2.5.5 Assign frame ID range + Example 2 + A slave node has only two frames {status_frame, response_frame}. To assign PIDs to + these two frames the master application will setup the following request: start index + set to 0 and PID (index 0..3) set to {0xC4, 0x85, 0xFF, 0xFF}. Since the slave node + has only two frames the last two must be set to do not care, otherwise the request will fail. + */ + uint8_t maxConfigurableFrameIndex = assignFrameIDRng->startIndex + 4U; + if (maxConfigurableFrameIndex > tableItemsCount){/* overlap with frame table */ + uint8_t coutOffset = 4U - (maxConfigurableFrameIndex - tableItemsCount); + for (uint8_t i = coutOffset; i < 4U;i++){ + /* configurable out of range PID should be 0xFF */ + if (assignFrameIDRng->pid[i] != LIN_FRAME_ID_DONOTCARE){ + /* the request is fail */ + invalid = 1U; + break; + } + } + if (invalid == 0U){ + /* Configurable out of range PID setting is corrent, copy PID to frame table */ + for (uint8_t i = 0U; i< (tableItemsCount - assignFrameIDRng->startIndex);i++){ + if (assignFrameIDRng->pid[i] == LIN_FRAME_ID_UNASSIGN){ + /* set PID to 0xFF to invalid this frame */ + unconditionalTable[assignFrameIDRng->startIndex + i].frameIsValid = FALSE; + }else{ + if (assignFrameIDRng->pid[i] != LIN_FRAME_ID_DONOTCARE){ + /* + 4.2.5.5 Assign frame ID range: + The slave node will not validate the given PIDs (i.e. validating the parity flags), the + slave node relies on that the master sets the correct PIDs. + copy PID to frame table: + */ + unconditionalTable[assignFrameIDRng->startIndex + i].frame_id = assignFrameIDRng->pid[i] & 0x3FU; + unconditionalTable[assignFrameIDRng->startIndex + i].frameIsValid = TRUE; + } + } + } + diagRsp->packLength = 0U; + response = TRUE; + } + }else{/* no overlap frame table */ + for (uint8_t i = 0U; i < 4U;i++){ + if (assignFrameIDRng->pid[i] == LIN_FRAME_ID_UNASSIGN){ + /* set PID to 0xFF to invalid this frame */ + unconditionalTable[assignFrameIDRng->startIndex + i].frameIsValid = FALSE; + }else{ + if (assignFrameIDRng->pid[i] != LIN_FRAME_ID_DONOTCARE){ + /* + 4.2.5.5 Assign frame ID range: + The slave node will not validate the given PIDs (i.e. validating the parity flags), the + slave node relies on that the master sets the correct PIDs. + copy PID to frame table: + */ + unconditionalTable[assignFrameIDRng->startIndex + i].frame_id = assignFrameIDRng->pid[i] & 0x3FU; + unconditionalTable[assignFrameIDRng->startIndex + i].frameIsValid = TRUE; + } + } + } + for (uint8_t i = 0U; i < tableItemsCount; i++){ + linParams->frameInfo[i].frameId = frameTable[i].frame_id; + linParams->frameInfo[i].frameIsValid = frameTable[i].frameIsValid; + } + diagRsp->packLength = 0U; + response = TRUE; + } + } + } + } + return response; +} +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linsNodeCfgIdentify.h b/app_Indie/usr/common/linsNodeCfgIdentify.h new file mode 100644 index 0000000..56f536a --- /dev/null +++ b/app_Indie/usr/common/linsNodeCfgIdentify.h @@ -0,0 +1,68 @@ +#ifndef LINS_NODE_CFG_IDENTIFY_H__ +#define LINS_NODE_CFG_IDENTIFY_H__ +#include + +BEGIN_PACK + +typedef struct{ + uint8_t initNAD; + uint8_t pci; + uint8_t sid; +}nodeConfig_t; + +typedef struct{ + uint16_t supplierID; + uint16_t functionID; + uint8_t newNAD; +}AssignNAD_t; + +typedef struct{ + uint16_t supplierID; + uint16_t functionID; + uint8_t newNAD; +}SNPD_t; + +typedef struct{ + uint8_t startIndex; + uint8_t pid[4]; +}AssignFrameIDRange_t; + +typedef struct{ + uint8_t command; + uint32_t magicKey; +}EnterBootloaderFrame_t; + +typedef struct{ + uint8_t identifier; + uint16_t supplierID; + uint16_t functionID; +}ReadByIdReq_t; + +typedef struct{ + uint8_t sid; + uint8_t errorCode; +}ReadByIdNakRsp_t; + +typedef struct{ + uint16_t supplierID; + uint16_t functionID; + uint8_t variant; +}ReadByIdProductIdRsp_t; + +typedef struct{ + uint32_t serialNo; +}ReadByIdSerialNoRsp_t; + +typedef struct{ + uint8_t nad; + uint32_t magicKey; +}SaeJ2602_3C3ECfg_t; + +END_PACK + + + +void LNCI_Init(void); +uint8_t LNCI_HandleNodeCfgIdentifyRequest(const DiagSubscribeInfo_t *const diagReq,DiagPublishInfo_t *const diagRsp); + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linsNodeCfgIdentify_J2602.c b/app_Indie/usr/common/linsNodeCfgIdentify_J2602.c new file mode 100644 index 0000000..8ff3e44 --- /dev/null +++ b/app_Indie/usr/common/linsNodeCfgIdentify_J2602.c @@ -0,0 +1,182 @@ +/** + * @copyright 2021 Indie microcontroller. + * + * This file is proprietary to Indie microcontroller. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie microcontroller. + * + * @file linsNodeCfgIdentify.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2021/07/06 + */ + +#include +#include +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_SAEJ2602 + +static LINClusterParams_t *linParams = NULL; +static LIN_Device_Frame_t volatile *frameTable = NULL; + +void HardwareResetTimerExpired(SoftTimer_t *timer); + +static SoftTimer_t hardwareResetTimer = { + .mode = TIMER_ONE_SHOT_MODE, + .interval = 50U, + .handler = HardwareResetTimerExpired +}; + +void HardwareResetTimerExpired(SoftTimer_t *timer) +{ + CRGA_SFRS->RESETCTRL.HARDRSTREQ = 1U; +} + +void LNCI_Init(void) +{ + uint8_t frameIsValid = TRUE; + uint8_t tableItemsCount; + /* get lin information from flash storage */ + linParams = PDS_GetLINParam(); + /* get frame table information */ + frameTable = LINS_GetUcndFramesTable(&tableItemsCount); + + /* + 5.7.2.2 Message ID Assignment + Devices with a DNN of $E or $F will have the protected identifiers marked as + invalid as described in of the LIN Diagnostic and Configuration Specification + */ + if (linParams->nad >= 0x6EU && linParams->nad <= 0x6FU){ + frameIsValid = FALSE; + } + for (uint8_t i = 0U; i < tableItemsCount; i++){ + frameTable[i].frame_id = i + (linParams->nad & 0x0FU)*4U; + frameTable[i].frameIsValid = frameIsValid; + } +} + +uint8_t LNCI_HandleNodeCfgIdentifyRequest(const DiagSubscribeInfo_t *const diagReq,DiagPublishInfo_t *const diagRsp) +{ + uint8_t frameIsValid = TRUE; + uint8_t response = FALSE; + if (diagReq->sid == LIN_SID_J2602_HARDWARE_RST && diagReq->packLength == 0U){ /* 0xB5 is hardware reset command in SAEJ2602 */ + /* LIN Product Identification */ + ReadByIdProductIdRsp_t *rsp = (ReadByIdProductIdRsp_t *)((void *)diagRsp->payload); + rsp->supplierID = LINS_SUPPLIER_ID; + rsp->functionID = LINS_FUNCTION_ID; + rsp->variant = LINS_VARIANT; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdProductIdRsp_t); + + if(linParams->nad == ls_read_nad_from_master()){ + response = TRUE; + } + ls_set_J2602_hardware_reset(TRUE); + LINS_SetDeviceUnconfigured(); + //SoftTimer_Stop(&hardwareResetTimer); + //SoftTimer_Start(&hardwareResetTimer); + }else if (diagReq->sid == LIN_SID_ASSIGN_NAD && diagReq->packLength == sizeof(AssignNAD_t)){/* Assign NAD */ + /* + 4.2.5.1 Assign NAD + Assign NAD is used to resolve conflicting NADs in LIN clusters built using off-theshelves slave nodes or reused slave nodes. + This request uses the initial NAD (or the NAD wildcard); this is to avoid the risk of losing the address of a slave node. The NAD + used for the response shall be the same as in the request, i.e. the initial NAD. + */ + uint8_t nad = ls_read_nad_from_master(); + if (nad == INIT_LINS_NAD_ADDR || nad == LIN_NAD_WILDCARD){ + AssignNAD_t *assignNAD = (AssignNAD_t *)((void *)diagReq->payload); + if ((assignNAD->supplierID == LINS_SUPPLIER_ID || assignNAD->supplierID == LIN_SUPPLIER_ID_WILDCARD)&& + (assignNAD->functionID == LINS_FUNCTION_ID || assignNAD->functionID == LIN_FUNCTION_ID_WILDCARD)){ + /* A response shall only be sent if the NAD, the Supplier ID and the Function ID match. If successful */ + if (assignNAD->newNAD >= 0x60U && assignNAD->newNAD <= 0x6FU){ + if ( (((assignNAD->newNAD & 0x0FU)%(MESSAGE_ID_BLOCK_COUNT/4U) ) == 0U) || (assignNAD->newNAD == 0x6FU) ){ + /* + 5.7.2.2 Message ID Assignment + Devices with a DNN of $E or $F will have the protected identifiers marked as + invalid as described in of the LIN Diagnostic and Configuration Specification + */ +#if MESSAGE_ID_BLOCK_COUNT == 8U + if (assignNAD->newNAD >= 0x6DU && assignNAD->newNAD <= 0x6FU){ + frameIsValid = FALSE; + } +#else + if (assignNAD->newNAD >= 0x6EU && assignNAD->newNAD <= 0x6FU){ + frameIsValid = FALSE; + } +#endif + diagRsp->packLength = 0U; + linParams->nad = assignNAD->newNAD; + ls_set_nad(assignNAD->newNAD); /* set nad to lin stack */ + /* adatper Frame ID according to NAD */ + uint8_t tableItemsCount; + frameTable = LINS_GetUcndFramesTable(&tableItemsCount); + linParams->frameIDSize = tableItemsCount; + + for (uint8_t i = 0U; i < tableItemsCount; i++){ + frameTable[i].frame_id = i + (linParams->nad & 0x0FU)*4U; + frameTable[i].frameIsValid = frameIsValid; + linParams->frameInfo[i].frameId = frameTable[i].frame_id; + linParams->frameInfo[i].frameIsValid = frameIsValid; + } + response = TRUE; + /*TM_PostTask(TASK_ID_PDS); start persistance data storage (PDS )task */ + } + } + } + } + }else if (diagReq->sid == LIN_SID_SAVE_CONFIGURATION && diagReq->packLength == 0x00U){ /* Save Configuration */ + /* + 4.2.5.4 Save Configuration + This service tells the slave node(s) that the slave application shall save the current + configuration. The save configuration request shall be structured as shown in + Table 4.14. This service is used to notify a slave node to store its configuration. + A configuration in the slave node may be valid even without the master node using this + request (i.e. the slave node does not have to wait for this request to have a valid configuration). + */ + diagRsp->packLength = 0U; + response = TRUE; + TM_PostTask(TASK_ID_PDS); /*start persistance data storage (PDS )task */ + }else if (diagReq->sid == LIN_SID_READ_BY_ID && diagReq->packLength == sizeof(ReadByIdReq_t)){ /* Read by Identifier */ + ReadByIdReq_t *readById = (ReadByIdReq_t *)((void*)diagReq->payload); + if ((readById->supplierID == LINS_SUPPLIER_ID || readById->supplierID == LIN_SUPPLIER_ID_WILDCARD)&& + (readById->functionID == LINS_FUNCTION_ID || readById->functionID == LIN_FUNCTION_ID_WILDCARD)){ + /* + 4.2.6.1 Read by identifier + It is possible to read the supplier identity and other properties from a slave node using + the request in Table 4.18. + */ + if (readById->identifier == 0U){ + /* LIN Product Identification */ + ReadByIdProductIdRsp_t *rsp = (ReadByIdProductIdRsp_t *)((void *)diagRsp->payload); + rsp->supplierID = LINS_SUPPLIER_ID; + rsp->functionID = LINS_FUNCTION_ID; + rsp->variant = LINS_VARIANT; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdProductIdRsp_t); + response = TRUE; + }else if (readById->identifier == 1U){ + /* Serial number */ + ReadByIdSerialNoRsp_t *rsp = (ReadByIdSerialNoRsp_t *)((void *)diagRsp->payload); + rsp->serialNo = LINS_SERIAL_NO; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdSerialNoRsp_t); + response = TRUE; + }else{ + /* + If the slave is not supporting this request or could not process the request it will + respond according to Table 4.21. + */ + ReadByIdNakRsp_t *rsp = (ReadByIdNakRsp_t *)((void *)diagRsp->payload); + diagRsp->sid = 0x7FU; + rsp->sid = LIN_SID_READ_BY_ID; + rsp->errorCode = 0x12U; + diagRsp->packLength = (uint16_t)sizeof(ReadByIdNakRsp_t); + response = TRUE; + } + } + } + return response; +} + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linslaveTask.c b/app_Indie/usr/common/linslaveTask.c new file mode 100644 index 0000000..95776b2 --- /dev/null +++ b/app_Indie/usr/common/linslaveTask.c @@ -0,0 +1,416 @@ +/** + * @copyright 2021 Indie microcontroller. + * + * This file is proprietary to Indie microcontroller. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie microcontroller. + * + * @file linSlaveTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2021/07/06 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_LIN2_2A + +#define FID_LED_CTRL DEFAULT_LINS_FID0 +#define FID_TFJR DEFAULT_LINS_FID1 +#define FID_KEY DEFAULT_LINS_FID2 + +#define DIAG_RECV_DATA_BUFF_SIZE (128U) +#define DIAG_SEND_DATA_BUFF_SIZE (128U) + +#define FID_TABLE_INDEX_0 (0) +#define FID_TABLE_INDEX_1 (0) +#define FID_TABLE_INDEX_2 (0) + +#define FID_LED_CTRL_INDEX (0) +#define FID_TFJR_INDEX (1) +#define FID_KEY_INDEX (2) + +/* ******************internal function declarations****************************/ +void DiagnosticSubscribedCmdsHandleISR(const DiagSubscribeInfo_t * const frameInfo); +void UnconditionalSubscribedCmdsHandle(LIN_Device_Frame_t const *frame); +void UnconditionalPublishedCmdsISR(LIN_Device_Frame_t *const frame); +void UnconditionalPublishedCmdsTxFinishedISR(uint8_t fid, uint8_t resvd); +void DiagnosticSleepRequestHandle(SleepRequestType_t type); +void BusWakeUpRequestHandle(BusWakeUpRequestResult_t result); + + +/* *******************global variants declarations*****************************/ +static TaskState_t linsTaskState = TASK_STATE_INIT; +static uint8_t diagDataRspBuff[DIAG_SEND_DATA_BUFF_SIZE]; +static uint8_t diagDataRecvBuff[DIAG_RECV_DATA_BUFF_SIZE]; + +static DiagMultiPduInfo_t diagMultiPduInfo = { + .buffLength = sizeof(diagDataRecvBuff)/sizeof(diagDataRecvBuff[0]), + .buff = diagDataRecvBuff, +}; + +static uint8_t busWakeupRetryCount = 0U; + +void busWakeupRetryTimerExpired(SoftTimer_t *timer); + +static SoftTimer_t busWakeupRetryTimer = { + .mode = TIMER_ONE_SHOT_MODE, + .interval = 2250U, + .handler = busWakeupRetryTimerExpired +}; + +static uint8_t eventTriggeredLedOn = FALSE; +static SystemParams_t systemParam; +static uint8_t By3CSetMotorParam_State = 0U; +static uint16_t SetMotorPhyParam[6]; +static uint32_t crcValue ; + +/* LIN command handle callbacks declarations */ +static ls_LinsFramesCallback_t linsFramesCallback ={ + UnconditionalSubscribedCmdsHandle, /* received data from master */ + UnconditionalPublishedCmdsISR, /* send data to master, it's an interrupt function, please fill the data as fast as possible */ + UnconditionalPublishedCmdsTxFinishedISR, /* send data to master finished, it's an interrupt function, please fill the data as fast as possible */ + DiagnosticSubscribedCmdsHandleISR, /* Diagnostic sigle PDU and MultiPDU received data from master,it's an interrupt function, please fill the data as fast as possible */ + NULL, /* special functional NAD (0x7E) handler*/ + DiagnosticSleepRequestHandle, /* Diagnostic sleep request from master */ + BusWakeUpRequestHandle, /* Get the bus wake up result this would take effects after call API: ls_send_wake_up_bus_signal()*/ + NULL, /* SAE J2602 -1 Configuration Messages */ + NULL, /* 5.7.2.5 DNN Based Broadcast Messages */ +}; + +/* **FID table declarations****/ +static LIN_Device_Frame_t UnconditionalCmdsTable[DEFAULT_LINS_FID_SIZE] = { + [FID_LED_CTRL_INDEX] = { + .frame_id = FID_LED_CTRL, + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = 2, + .frameIsValid = TRUE, + }, + [FID_TFJR_INDEX] = { + .frame_id = FID_TFJR, /* status management frame */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = 2, + .frameIsValid = TRUE, + }, + [FID_KEY_INDEX] = { + .frame_id = FID_KEY, /* user data report */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = 8, + .frameIsValid = TRUE, + }, +}; + + + +/* please don't do any changes for it would be used by lin stack */ +LIN_Device_Frame_t volatile *LINS_GetUcndFramesTable(uint8_t *tableItemsCount) +{ + *tableItemsCount = (uint8_t)(sizeof(UnconditionalCmdsTable)/sizeof(LIN_Device_Frame_t)); + return UnconditionalCmdsTable; +} + +/* + Diagnostic subscribed frame received from LIN master +*/ +void DiagnosticSubscribedCmdsHandleISR(const DiagSubscribeInfo_t *const diagReq) +{ + DiagPublishInfo_t diagRsp={ + .sid = diagReq->sid, + .type = diagReq->type, + .payload = diagDataRspBuff, + }; + if (diagReq->type == PDU_TYPE_SINGLE_PDU){ + if (diagReq->sid >= LIN_SID_ASSIGN_NAD && diagReq->sid <= LIN_SID_ASSIGN_FRAME_ID_RANGE){ + /* handle Node configuration and Identification commands*/ + diagRsp.type = PDU_TYPE_SINGLE_PDU; + if (LNCI_HandleNodeCfgIdentifyRequest(diagReq,&diagRsp)== TRUE){ + ls_handle_diagnostic_response(&diagRsp); + } + }else{ + if (diagReq->sid == LIN_SID_APP_DIAG_SINGLE_PDU_RECV_MULTI_RSP){ + /* handle diagnostic single pdu, multi response, user defined diagnostic frame here for example: */ + for (uint16_t i = 0U; i < 15U; i++){ + diagDataRspBuff[i] = (uint8_t)i; + } + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + }else if(diagReq->sid == LIN_SID_APP_DIAG_MOTOR_GET_CONFIG){ + diagRsp.sid = diagReq->sid; + + /*Read set paramers from flash*/ + + CRC32_Init(); + SystemParams_t *param = (SystemParams_t *)FLASH_START_ADDRESS_SYSTEM_DATA; + crcValue = CRC32_GetRunTimeCRC32((uint8_t *)¶m->info ,(uint16_t)sizeof(param->info)); + if (crcValue == param->head.crc32){ + + systemParam = *param; + diagDataRspBuff[2] = (uint8_t)systemParam.info.motorParams.Constantspeed; + diagDataRspBuff[3] = (uint8_t)(systemParam.info.motorParams.Constantspeed >> 8); + + diagDataRspBuff[4] = (uint8_t)systemParam.info.motorParams.startspeed; + diagDataRspBuff[5] = (uint8_t)(systemParam.info.motorParams.startspeed >> 8); + + diagDataRspBuff[6] = (uint8_t)systemParam.info.motorParams.Slowspeed; + diagDataRspBuff[7] = (uint8_t)(systemParam.info.motorParams.Slowspeed >> 8); + + diagDataRspBuff[8] = (uint8_t)systemParam.info.motorParams.MotorlockAcoilvoltage; + diagDataRspBuff[9] = (uint8_t)(systemParam.info.motorParams.MotorlockAcoilvoltage >> 8); + + diagDataRspBuff[10] = (uint8_t)systemParam.info.motorParams.MotorlockBcoilvoltage; + diagDataRspBuff[11] = (uint8_t)(systemParam.info.motorParams.MotorlockBcoilvoltage >> 8); + + diagDataRspBuff[12] = (uint8_t)systemParam.info.motorParams.ClimbTime; + diagDataRspBuff[13] = (uint8_t)systemParam.info.motorParams.SlowTime; + + } + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + } +#ifdef BOOTLOADER_EN + else if (diagReq->sid == LIN_SID_APP_DIAG_BOOT_MODE && diagReq->packLength == sizeof(EnterBootloaderFrame_t)){ + EnterBootloaderFrame_t *boot = (EnterBootloaderFrame_t *)((void*)diagReq->payload); + if ( boot->command == BOOT_MODE_HANDSHAKE && boot->magicKey == BOOT_MODE_MAGIC_KEY_HANDSHAKE){ + /* Reset Chip */ + TRIMHV_SFRS->RETAIN.RETAIN0 = 0x05U; + CRGA_SFRS->RESETCTRL.HARDRSTREQ = 1U; + } + } +#endif + } + }else{ + /* handle diagnostic multi pdu received sigle pdu response, user defined diagnostic frame here */ + if (diagReq->sid == LIN_SID_APP_DIAG_MULTI_PDU_RECV_SINGLE_RSP){ + /* handle diagnostic multi pdu received single pdu response, user defined diagnostic frame here */ + /* handle response data here */ + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 5U;/* Valid data length not includes sid*/ + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + }else if (diagReq->sid == LIN_SID_APP_DIAG_MULTI_PDU_RECV_MULTI_RSP){ + /* handle diagnostic multi pdu received multi pdu response, user defined diagnostic frame here */ + /* Package received finished */ + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; /* Valid data length not includes sid*/ + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + }else if (diagReq->sid == LIN_SID_APP_DIAG_MOTOR_SET_CONFIG){ + /* handle diagnostic multi pdu received multi pdu response, user defined diagnostic frame here */ + /* Package received finished */ + for (uint16_t i = 0; i < diagReq->packLength; i++){// + diagDataRspBuff[i] = diagReq->payload[i]; + } + //info->motorPhysicalParam.Constantspeed;//Constantspeed us/step + SetMotorPhyParam[0] = diagDataRecvBuff[3]; + SetMotorPhyParam[0] = ((SetMotorPhyParam[0]<<8)+diagDataRecvBuff[2]); + //info->motorPhysicalParam.startspeed;//Motorlock startspeed us/step + SetMotorPhyParam[1] = diagDataRecvBuff[5]; + SetMotorPhyParam[1] = ((SetMotorPhyParam[1]<<8)+diagDataRecvBuff[4]); + //info->motorPhysicalParam.Slowspeed;//Motorlock Slowspeed us/step + SetMotorPhyParam[2] = diagDataRecvBuff[7]; + SetMotorPhyParam[2] = ((SetMotorPhyParam[2]<<8)+diagDataRecvBuff[6]); + //info->motorPhysicalParam.MotorlockAcoilvoltage;//Motorlock Acoil voltage + SetMotorPhyParam[3] = diagDataRecvBuff[9]; + SetMotorPhyParam[3] = ((SetMotorPhyParam[3]<<8)+diagDataRecvBuff[8]); + //info->motorPhysicalParam.MotorlockBcoilvoltage;//Motorlock Bcoil voltage + SetMotorPhyParam[4] = diagDataRecvBuff[11]; + SetMotorPhyParam[4] = ((SetMotorPhyParam[4]<<8)+diagDataRecvBuff[10]); + //info->motorPhysicalParam.SlowTime;//ClimbTime: ms low8bit, SlowTime: ms high8bit + SetMotorPhyParam[5] = diagDataRecvBuff[12]; + SetMotorPhyParam[5] = (SetMotorPhyParam[5] << 8) + diagDataRecvBuff[12];//info->motorPhysicalParam.ClimbTime; + By3CSetMotorParam_State = 1; + + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; /* Valid data length not includes sid*/ + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + } + else{ + /* intent to empty */ + } + } +} + +/* + Received sleep command from lin master or bus idle timeout occurs +*/ +void DiagnosticSleepRequestHandle(SleepRequestType_t type) +{ +// (void)ls_clr_go_to_sleep_flag(); +// /* Set system to hibranate mode*/ +// PMU_EnterDeepSleepMode(); +} + +void busWakeupRetryTimerExpired(SoftTimer_t *timer) +{ + ls_send_wake_up_bus_signal(); +} + +/* Called timeout after bus wake up 3 tries, or called when bus recovery */ +void BusWakeUpRequestHandle(BusWakeUpRequestResult_t result) +{ + if (result == BUS_WAKEUP_REQ_RESULT_REQ_TIMEOUT){ + if (busWakeupRetryCount == 1U){ + busWakeupRetryCount++; + SoftTimer_Start(&busWakeupRetryTimer); + }else{ + busWakeupRetryCount = 0U; + } + }else{ + busWakeupRetryCount = 0U; + SoftTimer_Stop(&busWakeupRetryTimer); + } +} + + +void UnconditionalPublishedCmdsTxFinishedISR(uint8_t fid, uint8_t resvd) +{ + if ( fid == UnconditionalCmdsTable[FID_TFJR_INDEX].frame_id){ + (void)ls_ifc_clear_error_status(); + (void)ls_clr_error_code_log(); + (void)ls_clr_overrun_flag(); + } +} +/* + User defined published frame callback function which from LINS ISR + please fill frame data[0-7] only, please don't do any changes on the left info except data[x]!!!! +*///TODO +void UnconditionalPublishedCmdsISR(LIN_Device_Frame_t *const frame) +{ + /* feed buffer to frame */ + if (frame->frame_id == UnconditionalCmdsTable[FID_TFJR_INDEX].frame_id){ + /* status management frame */ +// lin_status_t status = ls_ifc_read_status(); +// frame->data[0] = (uint8_t)status.payload; +// frame->data[1] = LINS_GetPIDFromFID(status.pid); +// frame->data[2] = ls_read_error_code_log(); +// for (uint8_t i = 2U; i < 8U; i++){ +// frame->data[i] = 0xFFU; +// } + lin_status_t status = ls_ifc_read_status(); + frame->data[0] = (uint8_t)status.payload; + frame->data[1] = SAFM_TransferState(); + frame->data[2] = (uint8_t)SAFM_GetMotorcurrent(); + frame->data[3] = (uint8_t)SAFM_GetMotorcurrent()>>8; + frame->data[4] = (uint8_t)SAFM_GetMotorcurrent(); + frame->data[5] = (uint8_t)SAFM_GetMotorcurrent()>>8; + frame->data[6] = Motor_GetCurrentPosition(); + frame->data[7] = Motor_GetCurrentPosition() >> 8; + + }else if (frame->frame_id == UnconditionalCmdsTable[FID_KEY_INDEX].frame_id){ + /* user defined data report */ + frame->data[0] = (APPL_GetLEDState()) | (eventTriggeredLedOn << 1U) | 0xF8U; + for (uint8_t i = 1U; i < LIN_BUFF_SIZE; i++){ + frame->data[i] = 0xFFU; + } + }else{ + /* intent to empty */ + } +} + + +void LINS_EventTriggered_ISR(void) +{ + if (eventTriggeredLedOn == TRUE){ + eventTriggeredLedOn = FALSE; + }else{ + eventTriggeredLedOn = TRUE; + } + //UnconditionalCmdsTable[EVENT_TRIGGERED_INDEX].eventTriggered = TRUE; +} + +uint8_t LINS_GetPIDFromFID(uint8_t frameId) +{ + uint8_t id = frameId; + uint8_t P0,P1; + P0 = (uint8_t)(((id >> 0)&0x01U)^((id >> 1)&0x01U)^((id >> 2)&0x01U) ^ ((id>> 4)&0x01U)); + P1 = (uint8_t)(~(((id >> 1)&0x01U)^((id >> 3)&0x01U)^((id >> 4)&0x01U) ^ ((id>> 5)&0x01U))) & 0x01U; + id = frameId | (P0 << 6) | (P1 << 7); + return id; +} + + +void LINS_SendWakeUpSignal_ISR(void) +{ + if (busWakeupRetryCount == 0U){ + busWakeupRetryCount++; + ls_send_wake_up_bus_signal(); + } +} + +/* + User defined subscribed frame received from LIN master +*/ + +void UnconditionalSubscribedCmdsHandle(LIN_Device_Frame_t const *frame) +{ + /* + if (frame->frame_id == UnconditionalCmdsTable[FID_COLOR_CTRL_INDEX].frame_id){ + Get_MotorprafromLINM(frame); + } + */ +} + +void LINS_TaskHandler(void) +{ + switch(linsTaskState){ + case TASK_STATE_ACTIVE: + break; + case TASK_STATE_INIT: + ls_register_services(LIN_PROTOCOL_LIN2_2A,UnconditionalCmdsTable, (l_u8)(sizeof(UnconditionalCmdsTable)/sizeof(LIN_Device_Frame_t)),diagMultiPduInfo,&linsFramesCallback); + (void)ls_set_tp_timeout(N_AS, N_CR); + /* Note that please don't change the following glitch configuration!!!!*/ + (void)ls_set_lins_rx_glitch_filter_1st(0x00U,0x08U); + (void)ls_set_lins_rx_glitch_filter_2nd(0x0AU,0x10U); + (void)ls_set_lins_rx_glitch_filter_3rd(0x30U,0x30U); + (void)l_sys_init(); + (void)ls_disable_lin_auto_sleep(TRUE); + linsTaskState = TASK_STATE_ACTIVE; + break; + default: + break; + } +} + +uint8_t LINS_TransferMotorPhyParamtobuffBy3C(uint16_t *buff,uint8_t leng) +{ + static uint8_t resault = 0u; + resault = By3CSetMotorParam_State; + if(By3CSetMotorParam_State == 1U){ + for (uint8_t i = 0U; i < leng; i++){ + *buff = SetMotorPhyParam[i]; + buff++; + } + By3CSetMotorParam_State = 0; + } + return resault; +} +void LINS_Transfer3CdataToPDS(uint16_t *buff,uint8_t leng) +{ + for (uint8_t i = 0U; i < leng; i++){ + *buff = SetMotorPhyParam[i]; + buff++; + } +} + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linslaveTask_J2602.c b/app_Indie/usr/common/linslaveTask_J2602.c new file mode 100644 index 0000000..688575e --- /dev/null +++ b/app_Indie/usr/common/linslaveTask_J2602.c @@ -0,0 +1,465 @@ +/** + * @copyright 2021 Indie microcontroller. + * + * This file is proprietary to Indie microcontroller. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie microcontroller. + * + * @file linSlaveTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2021/07/06 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_SAEJ2602 + + +BEGIN_PACK + +typedef struct{ + uint8_t reserved; + uint32_t calibPartNumber; + uint8_t dateLength; + uint8_t smallCalibCfgIndex; +}SmallCalibCfgParam_t; + +END_PACK + +static SmallCalibCfgParam_t smallCalibCfg = {0U,0x00000000U,16U,0U}; + +#define SLAVE_PN_REPORT_STRING_NUM (15U) +#define SLAVE_PN_REPORT_PACK_NUM (SLAVE_PN_REPORT_STRING_NUM/6U + 1U) +static const uint8_t slavePartNumberReporting[SLAVE_PN_REPORT_STRING_NUM] = {'I','N','D','8','3','2','0','9',' ','F','W',':','2','.','0'}; +static uint8_t slavePartNumberReportingIndex = 0U; + +#define LARGE_CALIB_RECV_NUM (14U) +static uint8_t largeCalibDataRecvBuff[LARGE_CALIB_RECV_NUM]; +static uint8_t largeCalibIsRunning = FALSE; + +#define FID_LED_CTRL DEFAULT_LINS_FID0 +#define FID_LED_REPORT DEFAULT_LINS_FID1 +#define FID_SMALL_CAL DEFAULT_LINS_FID2 +#define FID_CAL_PN_REPORT DEFAULT_LINS_FID3 +#define FID_LARGE_CAL DEFAULT_LINS_FID4 +#define FID_SLAVE_PN_REPORT DEFAULT_LINS_FID5 + +#define FID_RESVD0 DEFAULT_LINS_FID6 +#define FID_RESVD1 DEFAULT_LINS_FID7 + +#define DIAG_RECV_DATA_BUFF_SIZE (128U) +#define DIAG_SEND_DATA_BUFF_SIZE (128U) + +#define FID_LED_CTRL_INDEX (0) +#define FID_LED_REPORT_INDEX (1) +#define FID_SMALL_CAL_INDEX (2) +#define FID_CAL_PN_REPORT_INDEX (3) +#define FID_LARGE_CAL_INDEX (4) +#define FID_SLAVE_PN_REPORT_INDEX (5) + +/* ******************internal function declarations****************************/ +void DiagnosticSubscribedCmdsHandleISR(const DiagSubscribeInfo_t * const frameInfo); +void UnconditionalSubscribedCmdsHandle(LIN_Device_Frame_t const *frame); +void PublishedCmdsTxFinishedISR(uint8_t frameID,uint8_t j2602CfgRsp); +void UnconditionalPublishedCmdsISR(LIN_Device_Frame_t *const frame); +void DiagnosticSleepRequestHandle(SleepRequestType_t type); +void BusWakeUpRequestHandle(BusWakeUpRequestResult_t result); +void SAEJ2602CfgSubscribedCmdsHandle(uint8_t fid,uint8_t const *payload, uint8_t length); +void SAEJ2602DNNBroadcastSubscribedCmdsHandle(uint8_t fid,uint8_t const *payload, uint8_t length); + +/* *******************global variants declarations*****************************/ +static TaskState_t linsTaskState = TASK_STATE_INIT; +static uint8_t diagDataRspBuff[DIAG_SEND_DATA_BUFF_SIZE]; +static uint8_t diagDataRecvBuff[DIAG_RECV_DATA_BUFF_SIZE]; + +static DiagMultiPduInfo_t diagMultiPduInfo = { + .buffLength = DIAG_RECV_DATA_BUFF_SIZE, + .buff = diagDataRecvBuff, +}; +static uint8_t busWakeupRetryCount = 0U; + +static J2602StatusByte_t j2602StatusByte = { + .appInfo0 = 0U, + .appInfo1 = 0U, + .appInfo2 = 0U, + .appInfo3 = 1U, + .appInfo4 = 1U, + .err = 0U, + +}; + +void busWakeupRetryTimerExpired(SoftTimer_t *timer); + +static SoftTimer_t busWakeupRetryTimer = { + .mode = TIMER_ONE_SHOT_MODE, + .interval = 2250U, + .handler = busWakeupRetryTimerExpired +}; + + +/* LIN command handle callbacks declarations */ +static ls_LinsFramesCallback_t linsFramesCallback ={ + UnconditionalSubscribedCmdsHandle, /* received data from master */ + UnconditionalPublishedCmdsISR, /* send data to master, it's an interrupt function, please fill the data as fast as possible */ + PublishedCmdsTxFinishedISR, /* send data to master finished, it's an interrupt function, please fill the data as fast as possible */ + DiagnosticSubscribedCmdsHandleISR, /* Diagnostic sigle PDU and MultiPDU received data from master,it's an interrupt function, please fill the data as fast as possible */ + NULL, /* special functional NAD (0x7E) handler*/ + DiagnosticSleepRequestHandle, /* Diagnostic sleep request from master */ + BusWakeUpRequestHandle, /* Get the bus wake up result this would take effects after call API: ls_send_wake_up_bus_signal()*/ + SAEJ2602CfgSubscribedCmdsHandle, /* SAE J2602 -1 Configuration Messages */ + SAEJ2602DNNBroadcastSubscribedCmdsHandle, /* 5.7.2.5 DNN Based Broadcast Messages */ +}; + +/* **FID table declarations****/ +static LIN_Device_Frame_t UnconditionalCmdsTable[] = { + [FID_LED_CTRL_INDEX] = { /* frame_id: LED Control */ + .frame_id = FID_LED_CTRL, + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_LED_REPORT_INDEX] = { + .frame_id = FID_LED_REPORT, /* frame_id: LED state report */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_SMALL_CAL_INDEX] = { + .frame_id = FID_SMALL_CAL, /* frame_id: Small Calibration/Configuration */ + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_CAL_PN_REPORT_INDEX] = { + .frame_id = FID_CAL_PN_REPORT, /* frame_id: Slave Application Calibration Part Number */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_LARGE_CAL_INDEX] = { + .frame_id = FID_LARGE_CAL, /* frame_id: Large Calibration/Configuration */ + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_SLAVE_PN_REPORT_INDEX] = { + .frame_id = FID_SLAVE_PN_REPORT, /* frame_id: Slave Part Number Reporting */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, +}; + + +/* please don't do any changes for it would be used by lin stack */ +LIN_Device_Frame_t volatile *LINS_GetUcndFramesTable(uint8_t *tableItemsCount) +{ + *tableItemsCount = (uint8_t)(sizeof(UnconditionalCmdsTable)/sizeof(LIN_Device_Frame_t)); + return UnconditionalCmdsTable; +} + +/* + Diagnostic subscribed frame received from LIN master +*/ +void DiagnosticSubscribedCmdsHandleISR(const DiagSubscribeInfo_t *const diagReq) +{ + DiagPublishInfo_t diagRsp={ + .sid = diagReq->sid, + .type = diagReq->type, + .payload = diagDataRspBuff, + }; + if (diagReq->type == PDU_TYPE_SINGLE_PDU){ + if (diagReq->sid >= LIN_SID_ASSIGN_NAD && diagReq->sid <= LIN_SID_ASSIGN_FRAME_ID_RANGE){ + /* handle Node configuration and Identification commands*/ + diagRsp.type = PDU_TYPE_SINGLE_PDU; + if (LNCI_HandleNodeCfgIdentifyRequest(diagReq,&diagRsp)== TRUE){ + ls_handle_diagnostic_response(&diagRsp); + } + }else{ + if (diagReq->sid == LIN_SID_APP_DIAG_SINGLE_PDU_RECV_MULTI_RSP){ + /* handle diagnostic single pdu, multi response, user defined diagnostic frame here for example: */ + for (uint16_t i = 0U; i < 15U; i++){ + diagDataRspBuff[i] = (uint8_t)i; + } + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + } +#ifdef BOOTLOADER_EN + else if (diagReq->sid == LIN_SID_APP_DIAG_BOOT_MODE && diagReq->packLength == sizeof(EnterBootloaderFrame_t)){ + EnterBootloaderFrame_t *boot = (EnterBootloaderFrame_t *)((void*)diagReq->payload); + if ( boot->command == BOOT_MODE_HANDSHAKE && boot->magicKey == BOOT_MODE_MAGIC_KEY_HANDSHAKE){ + /* Reset Chip */ + CRGA_REG_RESETCTRL.HARDRSTREQ = 1U; + } + } +#endif + } + }else{ + /* handle diagnostic multi pdu received sigle pdu response, user defined diagnostic frame here */ + if (diagReq->sid == LIN_SID_APP_DIAG_MULTI_PDU_RECV_SINGLE_RSP){ + /* handle diagnostic multi pdu received single pdu response, user defined diagnostic frame here */ + /* handle response data here */ + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 5U;/* Valid data length not includes sid*/ + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + }else if (diagReq->sid == LIN_SID_APP_DIAG_MULTI_PDU_RECV_MULTI_RSP){ + /* handle diagnostic multi pdu received multi pdu response, user defined diagnostic frame here */ + /* Package received finished */ + diagRsp.sid = diagReq->sid; + diagRsp.packLength = 15U; /* Valid data length not includes sid*/ + diagRsp.type = (diagRsp.packLength > SF_MAX_DATA_LENGTH)? PDU_TYPE_MULTI_PDU:PDU_TYPE_SINGLE_PDU; + ls_handle_diagnostic_response(&diagRsp); + }else{ + /* intent to empty */ + } + } +} + +/* + Received sleep command from lin master or bus idle timeout occurs +*/ +void DiagnosticSleepRequestHandle(SleepRequestType_t type) +{ + /* Set lin to sleep mode */ + /* LINS_SetSlaveModuleToSleep(); */ + /* Set system to hibranate mode */ + PMU_EnterDeepSleepMode(); +} + + +void PublishedCmdsTxFinishedISR(uint8_t frameID,uint8_t j2602CfgRsp) +{ + if ( (frameID != LIN_FRAME_ID_DIAG_SLAVER_RSP) || (frameID == LIN_FRAME_ID_DIAG_SLAVER_RSP && j2602CfgRsp == TRUE)){ + ls_reset_J2602_error_code((J2602ErrCode_t)j2602StatusByte.err); /* clear error when response successfully */ + } +} + +void LINS_SetDeviceUnconfigured(void) +{ + j2602StatusByte.appInfo4 = 1U; + j2602StatusByte.appInfo3 = 1U; + smallCalibCfg.calibPartNumber = 0U; +} + +/* + User defined published frame callback function which from LINS ISR + please fill frame data[0-7] only, please don't do any changes on the left info except data[x]!!!! +*/ +void UnconditionalPublishedCmdsISR(LIN_Device_Frame_t *const frame) +{ + j2602StatusByte.err = (uint8_t)ls_read_J2602_error_code(); /* read error but not clear automatically */ + /* feed buffer to frame */ + if (frame->frame_id == UnconditionalCmdsTable[FID_LED_REPORT_INDEX].frame_id){ + /* LED status report */ + frame->data[0] = j2602StatusByte.payload; + frame->data[1] = APPL_GetLEDState(); + frame->data[2] = 0xFFU; + frame->data[3] = ((uint8_t)SAFM_GetBatteryState() << 2) | ((uint8_t)SAFM_GetChipTemperatureState() << 4); + for (uint8_t i = 4U; i < LIN_BUFF_SIZE; i++){ + frame->data[i] = 0xFFU; + } + }else if (frame->frame_id == UnconditionalCmdsTable[FID_CAL_PN_REPORT_INDEX].frame_id){ + /* Calibration Part Number report*/ + frame->data[0] = j2602StatusByte.payload; + ((SmallCalibCfgParam_t *)frame->data)->calibPartNumber = smallCalibCfg.calibPartNumber; + for (uint8_t i = 5U; i < LIN_BUFF_SIZE; i++){ + frame->data[i] = 0xFFU; + } + smallCalibCfg.smallCalibCfgIndex = 0U; + }else if (frame->frame_id == UnconditionalCmdsTable[FID_SLAVE_PN_REPORT_INDEX].frame_id){ + j2602StatusByte.appInfo4 = 1U; /* I'm not configured */ + frame->data[0] = j2602StatusByte.payload; + frame->data[1] = slavePartNumberReportingIndex; + for (uint8_t i = 0U; i < LIN_BUFF_SIZE -2U; i++){ + if ( (slavePartNumberReportingIndex*6U + i)>= SLAVE_PN_REPORT_STRING_NUM){ + frame->data[i+2U] = 0x00U; + }else{ + frame->data[i+2U] = slavePartNumberReporting[slavePartNumberReportingIndex*6U + i]; + } + } + if (++slavePartNumberReportingIndex >= SLAVE_PN_REPORT_PACK_NUM){ + slavePartNumberReportingIndex = 0U; + } + }else{ + /* intent to empty */ + } +} + + +void SAEJ2602CfgSubscribedCmdsHandle(uint8_t fid,uint8_t const *payload, uint8_t length) +{ + uint8_t databuff[7]={0xFFU,0xFFU,0xFFU,0xFFU,0xFFU,0xFFU,0xFFU}; + SaeJ2602_3C3ECfg_t const *cfg = (SaeJ2602_3C3ECfg_t const*)((void const*)payload); + j2602StatusByte.err = (uint8_t)ls_read_J2602_error_code(); + if (fid == 0x3CU){/* 0x3C */ + if ( cfg->magicKey == 0x55555555U){ + databuff[0] = (cfg->nad & 0x70U) >> 4U; + ls_handle_SAEJ2602Cfg_response(j2602StatusByte.payload, databuff); + } + }else{/* 0x3E */ + if ( cfg->magicKey == 0xAAAAAAAAU){ + databuff[0] = (cfg->nad & 0xF0U) >> 4U; + ls_handle_SAEJ2602Cfg_response(j2602StatusByte.payload, databuff); + } + } +} + +/* SAEJ2602 -1 :5.7.2.5 DNN Based Broadcast Messages: 0x38,0x39,0x3A,0x3B based on MESSAGE_ID_BLOCK_COUNT and NAD*/ +void SAEJ2602DNNBroadcastSubscribedCmdsHandle(uint8_t fid,uint8_t const *payload, uint8_t length) +{ +#if MESSAGE_ID_BLOCK_COUNT == 4U || MESSAGE_ID_BLOCK_COUNT == 8U || MESSAGE_ID_BLOCK_COUNT == 16U + uint32_t broadcaseContent = 0U; + uint8_t dnn = (ls_read_nad()&0x0FU); + + if (fid == 0x38U || fid == 0x3AU){ + for (uint8_t i = 0U; i < (MESSAGE_ID_BLOCK_COUNT/4U); i++){ + broadcaseContent += (uint32_t)payload[dnn+i] << (8U*i); + } + }else{ + for (uint8_t i = 0U; i < (MESSAGE_ID_BLOCK_COUNT/4U); i++){ + broadcaseContent += (uint32_t)payload[dnn + i - 8U] << (8U*i); + } + } +#else + #error invalid MESSAGE_ID_BLOCK_COUNT !! +#endif + +} + +/* + User defined subscribed frame received from LIN master +*/ +void UnconditionalSubscribedCmdsHandle(LIN_Device_Frame_t const *frame) +{ + if (frame->frame_id == UnconditionalCmdsTable[FID_LED_CTRL_INDEX].frame_id){ + APPL_HandleControlCommands(frame); + }else if (frame->frame_id == UnconditionalCmdsTable[FID_SMALL_CAL_INDEX].frame_id){ + smallCalibCfg.calibPartNumber = 0U; + j2602StatusByte.appInfo3 = 1U; + for (uint8_t i = 0U; i < LIN_BUFF_SIZE; i++){ + diagDataRecvBuff[smallCalibCfg.smallCalibCfgIndex*LIN_BUFF_SIZE + i] = frame->data[i]; + } + smallCalibCfg.smallCalibCfgIndex++; + if ( (smallCalibCfg.smallCalibCfgIndex*LIN_BUFF_SIZE) >= smallCalibCfg.dateLength ){ + /* do checksum calculating */ + uint8_t checksum = 0U; + for (uint8_t i = 0U; i < smallCalibCfg.dateLength; i++){ + checksum += diagDataRecvBuff[i]; + } + if (checksum == 0xFFU){ + smallCalibCfg.calibPartNumber = ((SmallCalibCfgParam_t*)diagDataRecvBuff)->calibPartNumber; + j2602StatusByte.appInfo3 = 0U; + } + smallCalibCfg.smallCalibCfgIndex = 0U; + } + }else if (frame->frame_id == UnconditionalCmdsTable[FID_LARGE_CAL_INDEX].frame_id){ + + if (largeCalibIsRunning == TRUE && frame->data[0] == 0U){ /* Calibration/Configuration Mode has finished */ + largeCalibIsRunning = FALSE; + j2602StatusByte.appInfo4 = 0U; + }else if (largeCalibIsRunning == FALSE && frame->data[0] == 0U){/* Calibration/Configuration Mode has started */ + largeCalibIsRunning = TRUE; + j2602StatusByte.appInfo4 = 1U; + for (uint8_t i = 0; i < 7U; i++){ + largeCalibDataRecvBuff[i] = frame->data[1U+ i]; + } + }else{ + for (uint8_t i = 0; i < 7U; i++){ + if ((frame->data[0]*7U+i) < LARGE_CALIB_RECV_NUM){ + largeCalibDataRecvBuff[frame->data[0]*7U+i] = frame->data[1U+ i]; + } + } + } + } +} + + +void busWakeupRetryTimerExpired(SoftTimer_t *timer) +{ + ls_send_wake_up_bus_signal(); +} + +/* Called timeout after bus wake up 3 tries, or called when bus recovery */ +void BusWakeUpRequestHandle(BusWakeUpRequestResult_t result) +{ + if (result == BUS_WAKEUP_REQ_RESULT_REQ_TIMEOUT){ + if (busWakeupRetryCount == 1U){ + busWakeupRetryCount++; + SoftTimer_Start(&busWakeupRetryTimer); + }else{ + busWakeupRetryCount = 0U; + } + }else{ + busWakeupRetryCount = 0U; + SoftTimer_Stop(&busWakeupRetryTimer); + } +} + + +uint8_t LINS_GetPIDFromFID(uint8_t frameId) +{ + uint8_t id = frameId; + uint8_t P0,P1; + P0 = (uint8_t)(((id >> 0)&0x01U)^((id >> 1)&0x01U)^((id >> 2)&0x01U) ^ ((id>> 4)&0x01U)); + P1 = (uint8_t)(~(((id >> 1)&0x01U)^((id >> 3)&0x01U)^((id >> 4)&0x01U) ^ ((id>> 5)&0x01U))) & 0x01U; + id = frameId | (P0 << 6) | (P1 << 7); + return id; +} + + +void LINS_SendWakeUpSignal_ISR(void) +{ + if (busWakeupRetryCount == 0U){ + busWakeupRetryCount++; + ls_send_wake_up_bus_signal(); + } +} + +void LINS_TaskHandler(void) +{ + switch(linsTaskState){ + case TASK_STATE_ACTIVE: + break; + case TASK_STATE_INIT: + ls_register_services(LIN_PROTOCOL_LIN2_2A,UnconditionalCmdsTable, (l_u8)(sizeof(UnconditionalCmdsTable)/sizeof(LIN_Device_Frame_t)),diagMultiPduInfo,&linsFramesCallback); + (void)ls_set_tp_timeout(N_AS, N_CR); + /* Note that please don't change the following glitch configuration!!!!*/ + (void)ls_set_lins_rx_glitch_filter_1st(0x00U,0x08U); + (void)ls_set_lins_rx_glitch_filter_2nd(0x0AU,0x10U); + (void)ls_set_lins_rx_glitch_filter_3rd(0x30U,0x30U); + (void)l_sys_init(); + (void)ls_disable_lin_auto_sleep(TRUE); + ls_set_J2602_hardware_reset(TRUE);/* It's a hardreset init */ +// if(GPIO_SFRS->GPIO_CFG[(uint8_t)GPIO_PORT_2].ACTDET != 0U){ +// GPIO_SFRS->GPIO_CFG[(uint8_t)GPIO_PORT_2].CLR = 1U; +// LINS_SendWakeUpSignal_ISR(); +// } +// GPIO_RegisterIRQ(GPIO_PORT_2, GPIO_EDGE_FALLING, LINS_SendWakeUpSignal_ISR); + linsTaskState = TASK_STATE_ACTIVE; + break; + default: + break; + } +} + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/linslaveTask_Private.c b/app_Indie/usr/common/linslaveTask_Private.c new file mode 100644 index 0000000..afe4151 --- /dev/null +++ b/app_Indie/usr/common/linslaveTask_Private.c @@ -0,0 +1,234 @@ +/** + * @copyright 2021 Indie microcontroller. + * + * This file is proprietary to Indie microcontroller. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie microcontroller. + * + * @file linSlaveTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2021/07/06 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LIN_STACK_TYPE == LIN_STACK_TYPE_PRIVATE + +BEGIN_PACK + +typedef struct{ + uint8_t nad; + uint8_t pci; + uint8_t sid; + uint8_t command; + uint32_t magicKey; +}bootloaderHandshake_t; + +END_PACK + + + +#define FID_MOTOR_CTRL DEFAULT_LINS_FID0 +#define FID_STATUS_FRAME DEFAULT_LINS_FID1 +#define DIAG_SEND_FRAME_3C (0x3CU) +#define DIAG_REQ_FRAME_3D (0x3DU) + + +#define FID_COLOR_CTRL_INDEX (0) +#define FID_STATUS_FRAME_INDEX (1) +#define FID_DIAG_SEND_3C_INDEX (2) +#define FID_DIAG_REQ_3D_INDEX (3) + +/* ******************internal function declarations****************************/ +void SubscribedCmdsHandleISR(LIN_Device_Frame_t const *frame); +void PublishedCmdsISR(LIN_Device_Frame_t *const frame); +void SleepRequestHandle(void); +void DiagCmdsHandle(LIN_Device_Frame_t const *frame); +LIN_Device_Frame_t receivedFrame; + +/* *******************global variants declarations*****************************/ +static TaskState_t linsTaskState = TASK_STATE_INIT; + +/* LIN command handle callbacks declarations */ +static ls_LinsPrivateFramesCallback_t linsFramesCallback ={ + SubscribedCmdsHandleISR, /* received data from master,it's an interrupt function, please fill the data as fast as possible*/ + PublishedCmdsISR, /* send data to master, it's an interrupt function, please fill the data as fast as possible */ + SleepRequestHandle, /* sleep request*/ +}; + +/* **FID table declarations****/ +static LIN_Device_Frame_t CmdsTable[DEFAULT_LINS_FID_SIZE] = { + [FID_COLOR_CTRL_INDEX] = { + .frame_id = FID_MOTOR_CTRL, + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_STATUS_FRAME_INDEX] = { + .frame_id = FID_STATUS_FRAME, /* status management frame */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_ENHANCED, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_DIAG_SEND_3C_INDEX] = { + .frame_id = DIAG_SEND_FRAME_3C, /* 0x3C */ + .msg_type = LIN_MSG_TYPE_RX, + .checksum = LIN_CHECKSUM_CLASSIC, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, + [FID_DIAG_REQ_3D_INDEX] = { + .frame_id = DIAG_REQ_FRAME_3D, /* 0x3D */ + .msg_type = LIN_MSG_TYPE_TX, + .checksum = LIN_CHECKSUM_CLASSIC, + .length = LIN_BUFF_SIZE, + .frameIsValid = TRUE, + }, +}; + +/* + Received sleep command from lin master or bus idle timeout occurs +*/ +void SleepRequestHandle(void) +{ + /* Set lin to sleep mode */ +/* LINS_SetSlaveModuleToSleep();*/ + /* Set system to hibranate mode*/ + //PMU_EnterDeepSleepMode(); +} + +/* + User defined published frame callback function which from LINS ISR + please fill frame data[0-7] only, please don't do any changes on the left info except data[x]!!!! +*/ +void PublishedCmdsISR(LIN_Device_Frame_t *const frame) +{ + /* feed buffer to frame */ + if (frame->frame_id == CmdsTable[FID_STATUS_FRAME_INDEX].frame_id){ + /* status management frame */ +// uint16_t status = ls_read_sys_status(); +// frame->data[0] = (uint8_t)status; +// frame->data[1] = LINS_GetPIDFromFID((uint8_t)(status >> 8)); +// frame->data[2] = ls_read_error_code(); +// frame->data[3] = 0;// ((uint8_t)SAFM_GetBatteryState() << 2) | ((uint8_t)SAFM_GetChipTemperatureState() << 4); + + /* MUST BE 4 bytes Aligned */ +// uint32_t *ledPNState = (uint32_t *)(frame->data+4U); +// *ledPNState = 0U; +// for (uint8_t i = 0; i < LED_NUM; i++){ +// // (*ledPNState) |= ((uint8_t)SAFM_GetLedPNStateState((LedNum_t)i) << (i*2)); +// } + + frame->data[0] = (uint8_t)(getpb3code()>>8); + frame->data[1] = (uint8_t)(getpb3code()); + frame->data[2] = (uint8_t)(getpc4code()>>8); + frame->data[3] = (uint8_t)(getpc4code()); + frame->data[4] = (uint8_t)(getcurrent()>>8); + frame->data[5] = (uint8_t)(getcurrent()); + frame->data[6] = getgai(); + frame->data[7] = getgai(); + } +} + + +/* + User defined subscribed frame received from LIN master +*/ +void SubscribedCmdsHandleISR(LIN_Device_Frame_t const *frame) +{ + receivedFrame = *frame; + TM_PostTask(TASK_ID_LINS); + +} + +void DiagCmdsHandle(LIN_Device_Frame_t const *frame) +{ +#ifdef BOOTLOADER_EN + bootloaderHandshake_t *hand = (bootloaderHandshake_t*)frame->data; + if ( hand->nad == INIT_LINS_NAD_ADDR && hand->pci == 0x06U && hand->sid == LIN_SID_APP_DIAG_BOOT_MODE && hand->command == BOOT_MODE_HANDSHAKE && hand->magicKey == BOOT_MODE_MAGIC_KEY_HANDSHAKE){ + /* Reset Chip */ + SYSCTRLA_REG_RETAIN0 = 0x05U; + PMUA_REG_CTRL.UPDATE = 1U; + while(PMUA_REG_CTRL.UPDATE == 1U); + CRGA_REG_RESETCTRL.HARDRSTREQ = 1U; + } +#endif + +} + +void LINS_TaskHandler(void) +{ + switch(linsTaskState){ + case TASK_STATE_ACTIVE: + if (receivedFrame.frame_id == CmdsTable[FID_COLOR_CTRL_INDEX].frame_id){ + APPL_HandleControlCommands(&receivedFrame); + }else if (receivedFrame.frame_id == CmdsTable[FID_DIAG_SEND_3C_INDEX].frame_id){ + DiagCmdsHandle(&receivedFrame); + } + break; + case TASK_STATE_INIT: + LINS_Init(); + LINS_RegisterPrivateServices(CmdsTable, (l_u8)(sizeof(CmdsTable)/sizeof(LIN_Device_Frame_t)), &linsFramesCallback); + /* Note that please don't change the following glitch configuration!!!!*/ + (void)ls_set_lins_rx_glitch_filter_1st(0x00U,0x08U); + (void)ls_set_lins_rx_glitch_filter_2nd(0x0AU,0x10U); + (void)ls_set_lins_rx_glitch_filter_3rd(0x30U,0x30U); + linsTaskState = TASK_STATE_ACTIVE; + break; + default: + break; + } +} + + +uint8_t LINS_GetPIDFromFID(uint8_t frameId) +{ + uint8_t id = frameId; + uint8_t P0,P1; + P0 = (uint8_t)(((id >> 0)&0x01U)^((id >> 1)&0x01U)^((id >> 2)&0x01U) ^ ((id>> 4)&0x01U)); + P1 = (uint8_t)(~(((id >> 1)&0x01U)^((id >> 3)&0x01U)^((id >> 4)&0x01U) ^ ((id>> 5)&0x01U))) & 0x01U; + id = frameId | (P0 << 6) | (P1 << 7); + return id; +} + + +/* please don't do any changes for it would be used by lin stack */ +LIN_Device_Frame_t volatile *LINS_GetUcndFramesTable(uint8_t *tableItemsCount) +{ + *tableItemsCount = (uint8_t)(sizeof(CmdsTable)/sizeof(LIN_Device_Frame_t)); + return CmdsTable; +} + + +static LINClusterParams_t *linParams = NULL; +static LIN_Device_Frame_t volatile *frameTable = NULL; + +void LNCI_Init(void) +{ + uint8_t tableItemsCount; + /* get lin information from flash storage */ + linParams = PDS_GetLINParam(); + /* get frame table information */ + frameTable = LINS_GetUcndFramesTable(&tableItemsCount); + + for (uint8_t i = 0U; i < tableItemsCount; i++){ + frameTable[i].frame_id = linParams->frameInfo[i].frameId; + frameTable[i].frameIsValid = linParams->frameInfo[i].frameIsValid; + } +} + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/measureTask.c b/app_Indie/usr/common/measureTask.c new file mode 100644 index 0000000..0dd2b60 --- /dev/null +++ b/app_Indie/usr/common/measureTask.c @@ -0,0 +1,295 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file measureTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ +#include +#include +#include +#include + +#define AVERAGE_MEASURE_POS (4U) +#define AVERAGE_MEASURE_GAIN (1U << AVERAGE_MEASURE_POS) + +#define MEASURE_GAIN_POS 12U +#define MEASURE_GAIN 4096 /*(1UL << MEASURE_GAIN_POS)*/ + +#define MEASURE_TEMP_GAIN_POS 14U +#define MEASURE_TEMP_GAIN 7208 /*16384*0.43994*/ + + +#define RAW_PN_VOLT_SAMPLE_NUM_POS 4U +#define RAW_PN_VOLT_SAMPLE_NUM (1U << RAW_PN_VOLT_SAMPLE_NUM_POS) + +#if RAW_PN_VOLT_SAMPLE_NUM_POS <=0U + #error RAW_PN_VOLT_SAMPLE_NUM_POS >= 1U +#endif + +typedef struct{ + int32_t coefficient; + int32_t offset; +}coeffParam_t; + +typedef struct{ + uint32_t currCode; + uint16_t vampbuff[255];//vampbuff[24][10];ÐУºÒ»¸öÖÜÆڵIJ½Êý ÁУº£¨²½Óë²½Ö®¼äµÄʱ¼ä £©¡Â£¨PWMÖÜÆÚ£© + uint16_t count; + coeffParam_t coeff; + int16_t target; +}AdcDatabuff_t; + + +typedef struct{ + AdcDatabuff_t vBatt; + AdcDatabuff_t vChipTemp; + AdcDatabuff_t vAmp; + AdcDatabuff_t vPB3; + AdcDatabuff_t vPC4; + coeffParam_t tChip; + int16_t chipTemperature; +}AdcResult_t; + + +typedef struct{ + uint8_t CoilAOpencnt; + uint8_t CoilAShortcnt; + uint8_t CoilBOpencnt; + uint8_t CoilBShortcnt; + uint8_t MotorOCcnt; +}ErrorCnt_t; + + +static TaskState_t adcTaskState = TASK_STATE_INIT; +static AdcResult_t adcResult; + +static AdcGeneralTriggerSRC_t measSyncMode = ADC_TRIG_SRC_SOFT_INPUT; +static ADCMeasureParam_t measItem; +static volatile uint32_t measStart = 0U; +static volatile uint32_t updateSystemInfoStart = 0U; +static volatile uint32_t updatarow = 0U; +void add_data_to_vampbuff(uint32_t *original, uint16_t newData, uint16_t *bufferIndex,uint16_t *buff); +void add_data_to_buff(uint32_t *original, uint16_t newData, uint16_t *bufferIndex,uint16_t *buff); +void measureDoneISR(ADCMeasureParam_t item, uint16_t *const result); +void measureParamInit(void); + +void updateTimerExpired(SoftTimer_t *timer); + +static volatile uint32_t adcConvertDone = 0U; +static volatile uint16_t measGeneralAdcCode[4]; +static uint16_t vAmpbuff[24]; +static uint8_t SamplesNum = 0U; +static uint8_t updateSystemInfocnt = 0U; +void add_data_to_vampbuff(uint32_t *original, uint16_t newData, uint16_t *bufferIndex,uint16_t *buff) +{ + *original = newData; + uint16_t row= 0U; + + if(measItem.item == ADC_MEASURE_ITEM_VAMP){ + + SamplesNum = Motor_GetOnestep_csa_adcnt();//£¨²½Óë²½Ö®¼äµÄʱ¼ä £©¡Â£¨PWMÖÜÆÚ£© + row = Motor_GetMotorStep(); + + if (*original == INVALID_PARAM){ + for (uint8_t i = 0U; i < SamplesNum; i++){ + buff[(row*SamplesNum)+i] = newData; + } + }else{ + buff[(*bufferIndex) + (row*SamplesNum)] = newData; + } + (*bufferIndex) ++; + if ((*bufferIndex) >= SamplesNum){ + (*bufferIndex) = 0U; + updatarow = row; + updateSystemInfoStart = 1U; + } + } +} + + +void measureDoneISR(ADCMeasureParam_t param, uint16_t *const result) +{ + measGeneralAdcCode[0] = (result[0]>=0x800U)? 0U: result[0]; + measGeneralAdcCode[1] = (result[1]>=0x800U)? 0U: result[1]; + measGeneralAdcCode[2] = (result[2]>=0x800U)? 0U: result[2]; + measGeneralAdcCode[3] = (result[3]>=0x800U)? 0U: result[3]; + measItem = ADC_GetadcMeasParamm(); + + adcConvertDone = 1U; + measStart = 1U; + TM_PostTask(TASK_ID_ADC_MEASURE); +} + +void measureParamStart(void) +{ + switch(measItem.item){ + case ADC_MEASURE_ITEM_VBAT_VTEMP: +// add_data_to_buff(&adcResult.vBatt.currCode, measGeneralAdcCode[1], &adcResult.vBatt.count,adcResult.vBatt.buff); +// add_data_to_buff(&adcResult.vChipTemp.currCode, measGeneralAdcCode[2], &adcResult.vChipTemp.count,adcResult.vChipTemp.buff); + break; + case ADC_MEASURE_ITEM_VAMP: + add_data_to_vampbuff(&adcResult.vAmp.currCode, measGeneralAdcCode[0], &adcResult.vAmp.count,adcResult.vAmp.vampbuff); + add_data_to_vampbuff(&adcResult.vBatt.currCode, measGeneralAdcCode[1], &adcResult.vBatt.count,adcResult.vBatt.vampbuff); + add_data_to_vampbuff(&adcResult.vPB3.currCode, measGeneralAdcCode[2], &adcResult.vPB3.count,adcResult.vPB3.vampbuff); + add_data_to_vampbuff(&adcResult.vPC4.currCode, measGeneralAdcCode[3], &adcResult.vPC4.count,adcResult.vPC4.vampbuff); + + break; + default: + break; + } +} + +int16_t get_volt(AdcDatabuff_t *const param) +{ + int16_t volt = (int16_t)INVALID_VOLT; + int32_t sVolt; + uint32_t uVolt; + uint32_t sum = 0; + + if (param->currCode != INVALID_PARAM){ + if(measItem.item == ADC_MEASURE_ITEM_VBAT_VTEMP){ + + + }else if(measItem.item == ADC_MEASURE_ITEM_VAMP){ //ÇóÒ»²½ÒÔÄÚµÄĸÏßµçÁ÷¡¢VBAT¡¢PB3¡¢PC4 + sum = 0; + SamplesNum = Motor_GetOnestep_csa_adcnt();//£¨²½Óë²½Ö®¼äµÄʱ¼ä £©¡Â£¨PWMÖÜÆÚ£© + for (uint8_t i = 0U; i < SamplesNum; i++){ + sum += param->vampbuff[updatarow*SamplesNum + i]; + } + sVolt = param->coeff.coefficient * (int32_t)sum/SamplesNum + param->coeff.offset; + uVolt = (uint32_t)sVolt; + uVolt = uVolt/4096; + volt = (int16_t)uVolt; + } + } + return volt; +} + +int16_t get_chip_temperature(int16_t vTemp) +{ + int32_t stemp; + uint32_t uTemp; + uint8_t negative = 0U; + stemp = adcResult.tChip.coefficient*vTemp + adcResult.tChip.offset; + if (stemp < 0){ + stemp = -stemp; + negative = 1U; + } + uTemp = (uint32_t)stemp; + uTemp = uTemp >> MEASURE_TEMP_GAIN_POS; + stemp = (int32_t)uTemp; + if (negative != 0U){ + stemp = -stemp; + } + return (int16_t)stemp; +} + +void updateSystemInfo(void) +{ + /* calculate chip temperature */ + adcResult.vChipTemp.target = get_volt(&adcResult.vChipTemp); + adcResult.chipTemperature = get_chip_temperature(adcResult.vChipTemp.target); + adcResult.vBatt.target = get_volt(&adcResult.vBatt); + adcResult.vPB3.target = get_volt(&adcResult.vPB3); + adcResult.vPC4.target = get_volt(&adcResult.vPC4); + adcResult.vAmp.target = get_volt(&adcResult.vAmp); + vAmpbuff[Motor_GetMotorStep()] = adcResult.vAmp.target; + +// TM_PostTask(TASK_ID_SAFETY_MONITOR); + updateSystemInfocnt++; + if(updateSystemInfocnt > 23U){ + updateSystemInfocnt = 0; + TM_PostTask(TASK_ID_SAFETY_MONITOR); + } +} +void MES_TaskHandler(void) +{ + switch(adcTaskState){ + case TASK_STATE_INIT: + measureParamInit(); + ADC_GeneralInit();/* init ADC */ + ADC_RegisterIRQ(measureDoneISR); + adcTaskState = TASK_STATE_ACTIVE; + break; + case TASK_STATE_ACTIVE: + /* Start parameters measuring */ + + if (updateSystemInfoStart == 1U){ + updateSystemInfo(); + updateSystemInfoStart = 0U; + } + + if (measStart != 0U){ + measStart = 0U; + measureParamStart(); + } + break; + default: + break; + } +} + + +void measureParamInit(void) +{ + uint16_t adc0V5 = 426;//HWCFG_SFRS->ADC_0V5_CODE;//816 + uint16_t adc1V0 = 853;//HWCFG_SFRS->ADC_1V0_CODE;//1652 + + uint16_t adc0V2 = 1773;//HWCFG_SFRS->ADC_1V0_CODE;//1652 + uint16_t adc0V0 = 975;//5gain 31/32 + + uint16_t batt13V5 = 802;// + uint16_t batt8V0 = 468;// + + adcResult.vChipTemp.coeff.coefficient = (1000 -500)*MEASURE_GAIN/((int32_t)adc1V0 - (int32_t)adc0V5); + adcResult.vChipTemp.coeff.offset = 500*MEASURE_GAIN - adcResult.vChipTemp.coeff.coefficient*(int32_t)adc0V5; + adcResult.vChipTemp.currCode = INVALID_PARAM; + /* v = a*t + b; a = 2.273, t = v/a - b/a; gain = 1/a, offset = - b/a*/ + adcResult.tChip.coefficient = MEASURE_TEMP_GAIN; + adcResult.tChip.offset = 25*(int32_t)(1UL << MEASURE_TEMP_GAIN_POS) - MEASURE_TEMP_GAIN*(int32_t)HWCFG_SFRS->TSENSOR_mV_25C; + /*vAmp 5gain 31/32 200mv 20mv*/ + adcResult.vAmp.coeff.coefficient = (200 -0)*MEASURE_GAIN/((int32_t)adc0V2 - (int32_t)adc0V0); + adcResult.vAmp.coeff.offset = 0*MEASURE_GAIN - adcResult.vAmp.coeff.coefficient*(int32_t)adc0V0; + adcResult.vAmp.currCode = INVALID_PARAM; + /* battery volt*/ + adcResult.vBatt.coeff.coefficient = (int32_t)(13500 - 8000)*MEASURE_GAIN/((int32_t)batt13V5 - (int32_t)batt8V0); + adcResult.vBatt.coeff.offset = (int32_t)(8000*MEASURE_GAIN) - adcResult.vBatt.coeff.coefficient*(int32_t)batt8V0; + adcResult.vBatt.currCode = INVALID_PARAM; + /* PB3 volt*/ + adcResult.vPB3.coeff.coefficient = (int32_t)(1000 - 500)*MEASURE_GAIN/((int32_t)adc1V0 - (int32_t)adc0V5); + adcResult.vPB3.coeff.offset = (int32_t)(500*MEASURE_GAIN) - adcResult.vPB3.coeff.coefficient*(int32_t)adc0V5; + adcResult.vPB3.currCode = INVALID_PARAM; + /* PC4 volt*/ + adcResult.vPC4.coeff.coefficient = (int32_t)(1000 - 500)*MEASURE_GAIN*32/((int32_t)adc1V0 - (int32_t)adc0V5)/22; + adcResult.vPC4.coeff.offset = (int32_t)(500*MEASURE_GAIN) - adcResult.vPC4.coeff.coefficient*(int32_t)adc0V5; + adcResult.vPC4.currCode = INVALID_PARAM; +} + +int16_t Get_vAmp(void){ + return adcResult.vAmp.target; +} + +uint16_t *MEAGet_vAmpbuff(void){ + +return vAmpbuff; + +} +uint16_t MEA_GetVbat(void) +{ + return adcResult.vBatt.target; +} + + + + + + + + diff --git a/app_Indie/usr/common/measureTask.h b/app_Indie/usr/common/measureTask.h new file mode 100644 index 0000000..df20bb0 --- /dev/null +++ b/app_Indie/usr/common/measureTask.h @@ -0,0 +1,40 @@ +#ifndef _ADC_MEASUREMENT_TASK_H +#define _ADC_MEASUREMENT_TASK_H + +#include +#include +#include "systick_device.h" +#include +#include +#include "hwcfg.h" + +#define INVALID_PARAM (0x7FFFU) +#define INVALID_VOLT (0x7FFFU) +#define INVALID_TEMP (-127) + +/* + * Get battery voltage in mV + * @param [out] battVolt: 0-32678 + * @return 0: get voltage success, other : failed + */ +int8_t MES_GetBatteryVolt(uint16_t *battVolt); + +/* + * Get chip temperature in 1C + * @param [out] chipTemperature: -127-127C + * @return 0: get voltage success, other : failed + */ +int16_t MES_GetChipTemperature(int16_t *chipTemperature); + +/* + * measurement Task handle + * @return none + */ +void MES_TaskHandler(void); + + +int16_t Get_vAmp(void); +uint16_t *MEAGet_vAmpbuff(void); +uint16_t MEA_GetVbat(void); + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/motorControlTask.c b/app_Indie/usr/common/motorControlTask.c new file mode 100644 index 0000000..264ac91 --- /dev/null +++ b/app_Indie/usr/common/motorControlTask.c @@ -0,0 +1,504 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static TaskState_t motorState = TASK_STATE_INIT; +static ADCMeasureParam_t motoradcItem; + +/*Data sent from LIN host, including setting parameters and control parameters*/ +static M_Re_pra_t M_Re_pra = { + .M_ON = 0, + .Constantspeed = 500U, + .Startspeed = 1000U, + .Slowspeed = 1000U, + .LockACoilValtage = 500U, + .LockBCoilValtage = 500U, + .ClimbTime = 120U, + .SlowTime = 120U, + .Position = 0, +}; + +static uint8_t SysPowerup = 0; +static uint16_t MotorPosition = 0; +static uint8_t Motor_runnstatuschanged = 0; +static uint8_t Onestep_csa_adcnt = 0U; +static uint16_t Count_20ms = 0; +static uint16_t MotorOCstop10s = 0; + +static Motorpra_t motorpra; +static Motor_and_ChipPar_t motorandchippar = { + .state.byte[0] = 0, + .state.byte[1] = 0, +}; + +static uint16_t bufftemp[TransferCNT]; + +void delay(uint32_t delay)//1000000 1s +{ + for (uint32_t i = 0; i < delay; i++){ + for (uint32_t j = 0; j < 3; j++){ + __asm("NOP"); + } + } +} + +void Get_MotorprafromLINM(LIN_Device_Frame_t const *frame) +{ + MotorCtrlFrame_t const *motor = (MotorCtrlFrame_t const*)((void const*)frame->data); +// if ( (motor->nodeAddress == ls_read_nad()) || (motor->nodeAddress == LIN_NAD_WILDCARD)) +// { + M_Re_pra.M_ON = (motor->data[1])&0x01U ; //0X01 ON + M_Re_pra.Position = motor->data[3]; + M_Re_pra.Position = (M_Re_pra.Position << 8U) + motor->data[2]; + + if((M_Re_pra.M_ON != Motor_runnstatuschanged) || (MotorPosition != M_Re_pra.Position)){ +/*The position has changed*/ + motorpra.ClimbTime = 0U; + motorpra.SlowTime = 0U; + } + MotorPosition = M_Re_pra.Position; + Motor_runnstatuschanged = M_Re_pra.M_ON; + motorandchippar.MotorErrorState10s = 10000000U/M_Re_pra.Constantspeed; +// } +} + +void StopMotor(void) +{ + MotorPower_OFF; + VDD3V3EXT_OFF; + Twobridge_OFF; + + motorpra.ClimbTime = 0U; + motorpra.SlowTime = 0U; + + motorandchippar.state.Motor_runsta = (uint8_t)MotorStop; + motorandchippar.state.Motor_runstage = (uint8_t)Climbstage; + + if(SysPowerup == 0U){ + + PDS_PowerONRead_MotorParamfromFlash(bufftemp,TransferCNT); + motorpra.stepn = PDS_GetMotorstepnfromflash();/*From flash*/ + + M_Re_pra.Constantspeed = bufftemp[0]; + M_Re_pra.Startspeed = bufftemp[1]; + M_Re_pra.Slowspeed = bufftemp[2]; + M_Re_pra.LockACoilValtage = bufftemp[3]; + M_Re_pra.LockBCoilValtage = bufftemp[4]; + M_Re_pra.ClimbTime = (uint8_t)bufftemp[5]; + M_Re_pra.SlowTime = (uint8_t)(bufftemp[5]>>8U); + + motorpra.ClimbSteper = (uint16_t)((uint32_t)(M_Re_pra.ClimbTime)*1000U*2U/((uint32_t)(M_Re_pra.Startspeed )+ (uint32_t)(M_Re_pra.Constantspeed))); + motorpra.SlowSteper = (uint16_t)((uint32_t)(M_Re_pra.SlowTime)*1000U*2U/((uint32_t)(M_Re_pra.Slowspeed) + (uint32_t)(M_Re_pra.Constantspeed))); + Onestep_csa_adcnt = M_Re_pra.Constantspeed*16 / PWMAUX_Period; //¼ÆËãÒ»²½ÄڵIJÉÑù´ÎÊý + SysPowerup = 1u; + } + if(LINS_TransferMotorPhyParamtobuffBy3C(bufftemp,TransferCNT) == 1U){//3C + + M_Re_pra.Constantspeed = bufftemp[0]; + M_Re_pra.Startspeed = bufftemp[1]; + M_Re_pra.Slowspeed = bufftemp[2]; + M_Re_pra.LockACoilValtage = bufftemp[3]; + M_Re_pra.LockBCoilValtage = bufftemp[4]; + M_Re_pra.ClimbTime = (uint8_t)bufftemp[5]; + M_Re_pra.SlowTime = (uint8_t)(bufftemp[5]>>8U); + + motorpra.ClimbSteper = (uint16_t)((uint32_t)(M_Re_pra.ClimbTime)*1000U*2U/((uint32_t)(M_Re_pra.Startspeed )+ (uint32_t)(M_Re_pra.Constantspeed))); + motorpra.SlowSteper = (uint16_t)((uint32_t)(M_Re_pra.SlowTime)*1000U*2U/((uint32_t)(M_Re_pra.Slowspeed) + (uint32_t)(M_Re_pra.Constantspeed))); + Onestep_csa_adcnt = M_Re_pra.Constantspeed*16 / PWMAUX_Period; + } + +} + + +void Calculation_position(void){ + + if(M_Re_pra.M_ON == 1U){ + + VDD3V3EXT_ON; + if(M_Re_pra.Position > (uint16_t)(motorpra.stepn)){ + + if((SAFM_TransferState() & 0xFFU) == 0U){ + + motorpra.s = M_Re_pra.Position - motorpra.stepn; + + if(motorpra.s>0u){ + + MotorPower_ON; + + if(motorpra.ClimbTime < motorpra.ClimbSteper){ + motorpra.ClimbTime++; + }else{ + if(motorpra.s <= motorpra.SlowSteper){ + motorpra.SlowTime++; + } + } + if(motorpra.ClimbTime < motorpra.ClimbSteper){ + TIMER_Disable(TIMER1); + motorpra.T1timercnt = (uint32_t)(M_Re_pra.Startspeed)*16U-(uint32_t)(16U*((uint32_t)(M_Re_pra.Startspeed)-(uint32_t)(M_Re_pra.Constantspeed))*(uint32_t)(motorpra.ClimbTime))/(uint32_t)(motorpra.ClimbSteper); + + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, motorpra.T1timercnt, Timer1_INTTest); + motorandchippar.state.Motor_runstage = (uint8_t)Climbstage; + }else if((motorpra.SlowTime motorpra.s)){ + TIMER_Disable(TIMER1); + motorpra.T1timercnt = (uint32_t)((uint32_t)(M_Re_pra.Constantspeed)*16U+(16U*(((uint32_t)(M_Re_pra.Slowspeed)-(uint32_t)(M_Re_pra.Constantspeed)))*(uint32_t)(motorpra.SlowTime))/(uint32_t)(motorpra.SlowSteper)); + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, motorpra.T1timercnt, Timer1_INTTest); + motorandchippar.state.Motor_runstage = (uint8_t)Slowstage; + }else{ + if(motorandchippar.state.Motor_runstage != (uint8_t)Constantstage){ + TIMER_Disable(TIMER1); + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, (uint32_t)M_Re_pra.Constantspeed*16U, Timer1_INTTest); + } + motorandchippar.state.Motor_runstage = (uint8_t)Constantstage; + } + #if control_type == Divide_2 + motorpra.MM_Step=(uint8_t)(motorpra.stepn % 8U); + #elif control_type == Divide_6 + motorpra.MM_Step=(uint8_t)(motorpra.stepn % 24U); + #endif + motorpra.stepn++; + motorandchippar.state.Motor_runsta = (uint8_t)MotorRun; + } + } + }else if(M_Re_pra.Position < (uint16_t)(motorpra.stepn)){ + if((SAFM_TransferState() & 0xffu) == 0U){ + motorpra.s = motorpra.stepn - M_Re_pra.Position; + + if(motorpra.s>0U) + { + MotorPower_ON; + + if(motorpra.ClimbTime < motorpra.ClimbSteper){ + motorpra.ClimbTime++; + }else{ + if(motorpra.s <= motorpra.SlowSteper){ + motorpra.SlowTime++; + } + } + if(motorpra.ClimbTime < motorpra.ClimbSteper){ + TIMER_Disable(TIMER1); + motorpra.T1timercnt = (uint32_t)((uint32_t)M_Re_pra.Startspeed*16U-(16U*((uint32_t)M_Re_pra.Startspeed-(uint32_t)M_Re_pra.Constantspeed)*motorpra.ClimbTime)/motorpra.ClimbSteper); + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, motorpra.T1timercnt, Timer1_INTTest); + motorandchippar.state.Motor_runstage = (uint8_t)Climbstage; + }else if((motorpra.SlowTime < motorpra.SlowSteper)&&(motorpra.SlowSteper > motorpra.s)){ + TIMER_Disable(TIMER1); + motorpra.T1timercnt = (uint32_t)((uint32_t)M_Re_pra.Constantspeed*16U+(16U*((uint32_t)M_Re_pra.Slowspeed-(uint32_t)M_Re_pra.Constantspeed)*motorpra.SlowTime)/motorpra.SlowSteper); + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, motorpra.T1timercnt, Timer1_INTTest); + motorandchippar.state.Motor_runstage = (uint8_t)Slowstage; + }else{ + if(motorandchippar.state.Motor_runstage != (uint8_t)Constantstage){ + TIMER_Disable(TIMER1); + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1, (uint32_t)M_Re_pra.Constantspeed*16U, Timer1_INTTest); + } + motorandchippar.state.Motor_runstage = (uint8_t)Constantstage; + } + + #if control_type == Divide_2 + motorpra.MM_Step=(uint8_t)(motorpra.stepn % 8U); + #elif control_type == Divide_6 + motorpra.MM_Step=(uint8_t)(motorpra.stepn % 24U); + #endif + motorpra.stepn--; + motorandchippar.state.Motor_runsta = (uint8_t)MotorRun; + } + } + }else{ + StopMotor(); + } + } + else{ + StopMotor(); + } + motorandchippar.Motor_position = motorpra.stepn; +} + +#if control_type == Divide_2 + +void MOTORunP_8(uint8_t motorstep){ + switch(motorstep){ + case 0://1000 Phase B zero crossing, detect reverse electromotive force of B phase + Twobridge_OFF; + + Downpwm_APhasePos_High_ON; //PA3 ON(Upper bridge arm) + Downpwm_APhaseNeg_Low_ON;//PA5 OFF(Lower bridge arm) + break; + case 1://1010 + Twobridge_OFF; + + Downpwm_APhasePos_High_ON; + Downpwm_APhaseNeg_Low_ON; + + Downpwm_BPhasePos_High_ON; + Downpwm_BPhaseNeg_Low_ON; + break; + case 2://0010 Phase A zero crossing, detect reverse electromotive force of A phase + Twobridge_OFF; + + Downpwm_BPhasePos_High_ON; + Downpwm_BPhaseNeg_Low_ON; + break; + case 3://0110 + Twobridge_OFF; + + Downpwm_APhaseNeg_High_ON; + Downpwm_APhasePos_Low_ON; + + Downpwm_BPhasePos_High_ON; + Downpwm_BPhaseNeg_Low_ON; + break; + case 4://0100 Phase B zero crossing, detect reverse electromotive force of B phase + Twobridge_OFF; + + Downpwm_APhaseNeg_High_ON; + Downpwm_APhasePos_Low_ON; + break; + case 5://0101 + Twobridge_OFF; + + Downpwm_APhaseNeg_High_ON; + Downpwm_APhasePos_Low_ON; + + Downpwm_BPhaseNeg_High_ON; + Downpwm_BPhasePos_Low_ON; + break; + case 6://0001 Phase A zero crossing, detect reverse electromotive force of A phase + Twobridge_OFF; + + Downpwm_BPhaseNeg_High_ON; + Downpwm_BPhasePos_Low_ON; + break; + case 7://1001 + Twobridge_OFF; + + Downpwm_APhasePos_High_ON; + Downpwm_APhaseNeg_Low_ON; + + Downpwm_BPhaseNeg_High_ON; + Downpwm_BPhasePos_Low_ON; + break; + default: + Twobridge_OFF; + break; + } +} +#elif control_type == Divide_6 + +const uint16_t Downpwm_ACoil[24] = {247U,221U,181U,128U,66U,0U,66U,128U,181U,221U,247U,256U,247U,221U,181U,128U,66U,0U,66U,128U,181U,221U,247U,256U}; +const uint16_t Downpwm_BCoil[24] = {66U,128U,181U,221U,247U,256U,247U,221U,181U,128U,66U,0U,66U,128U,181U,221U,247U,256U,247U,221U,181U,128U,66U,0U}; + +void MOTORunP_24(uint8_t motorstep){ + + uint16_t temp1; + uint16_t temp2; + + temp1 = (uint16_t)(((uint32_t)PWM_AUX_SFRS->PWM_AUX[PWMAUX_BASE_0].BASE.PERIOD * Downpwm_ACoil[motorstep])>>8U); + temp2 = (uint16_t)(((uint32_t)PWM_AUX_SFRS->PWM_AUX[PWMAUX_BASE_0].BASE.PERIOD * Downpwm_BCoil[motorstep])>>8U); + PWM_AUX_SFRS->INVERT = 0X3FU; + + switch(motorstep){ + case 0:// + case 1: + case 2: + case 3: + case 4: + case 5://AÏàµçÁ÷ÓÉÕýÏòÍù¸ºÏòµÄ¹ýÁãµã + Downpwm_BPhasePos_Low_OFF;//PB1 + Downpwm_BPhaseNeg_High_OFF;//PA4 OFF(Upper bridge arm) + Downpwm_APhasePos_Low_OFF;//PA2 PWMAUX0 + Downpwm_APhaseNeg_High_OFF;//PA6 + delay(25); + + Downpwm_BPhasePos_High_ON; //PB2 ON(Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH1, 0, temp2);//PB0 PWMAUX1 + Downpwm_APhasePos_High_ON; //PA3 ON(Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH0, 0, temp1);//PA5 PWMAUX0 + break; + case 6: + case 7: + case 8: + case 9: + case 10: + case 11://BÏàµçÁ÷ÓÉÕýÏòÍù¸ºÏòµÄ¹ýÁãµã + Downpwm_BPhasePos_Low_OFF;//PB2 + Downpwm_BPhaseNeg_High_OFF;//PA4 OFF(Upper bridge arm) + Downpwm_APhasePos_High_OFF; //PA3 ON(Upper bridge arm) + Downpwm_APhaseNeg_Low_OFF;//PA5 PWMAUX0 + delay(25); + + Downpwm_BPhasePos_High_ON; //PB2 ON(B phase Upper bridge arm) + //Downpwm_BPhasePos_High_OFF; //PB2 ON(B phase Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH1, 0, temp2);//PB0 PWMAUX1 + PWMAUX_SetMatchValue(PWMAUX_CH5, 0, temp1);//PA2 PWMAUX5 + Downpwm_APhaseNeg_High_ON;//PA6 + break; + + case 12: + case 13: + case 14: + case 15: + case 16: + case 17://AÏàµçÁ÷ÓɸºÏòÍùÕýÏòµÄ¹ýÁãµã + Downpwm_BPhasePos_High_OFF; //PB2(Upper bridge arm) + Downpwm_BPhaseNeg_Low_OFF;//PB0 PWMAUX1 + Downpwm_APhasePos_High_OFF; //PA3 ON(Upper bridge arm) + Downpwm_APhaseNeg_Low_OFF;//PA5 PWMAUX0 + delay(25); + + PWMAUX_SetMatchValue(PWMAUX_CH2, 0, temp2);//PB1 PWMAUX2 + Downpwm_BPhaseNeg_High_ON;//PA4(Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH5, 0, temp1);//PA2 PWMAUX5 + Downpwm_APhaseNeg_High_ON;//PA6 + break; + case 18: + case 19: + case 20: + case 21: + case 22: +// case 23://BÏàµçÁ÷ÓɸºÏòÍùÕýÏòµÄ¹ýÁãµã + Downpwm_BPhasePos_High_OFF; //PB2(Upper bridge arm) + Downpwm_BPhaseNeg_Low_OFF;//PB0 PWMAUX1 + Downpwm_APhasePos_Low_OFF;//PA2 PWMAUX0 + Downpwm_APhaseNeg_High_OFF;//PA6 + delay(25); + + PWMAUX_SetMatchValue(PWMAUX_CH2, 0, temp2);//PB1 PWMAUX2 + Downpwm_BPhaseNeg_High_ON;//PA4(Upper bridge arm) + Downpwm_APhasePos_High_ON; //PA3 ON(Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH0, 0, temp1);//PA5 PWMAUX0 + break; + case 23://BÏàµçÁ÷ÓɸºÏòÍùÕýÏòµÄ¹ýÁãµã + Downpwm_BPhasePos_High_OFF; //PB2(Upper bridge arm) + Downpwm_BPhaseNeg_Low_OFF;//PB0 PWMAUX1 + Downpwm_APhasePos_Low_OFF;//PA2 PWMAUX0 + Downpwm_APhaseNeg_High_OFF;//PA6 + delay(25); + + PWMAUX_SetMatchValue(PWMAUX_CH2, 0, temp2);//PB1 PWMAUX2 + Downpwm_BPhaseNeg_High_OFF;//PA4(Upper bridge arm) + Downpwm_BPhasePos_High_ON; + + Downpwm_APhasePos_High_ON; //PA3 ON(Upper bridge arm) + PWMAUX_SetMatchValue(PWMAUX_CH0, 0, temp1);//PA5 PWMAUX0 + break; + + default: + + break; + } +} + +uint8_t Motor_GetMotorState(void){ + return motorandchippar.state.Motor_runsta ; +} + +uint8_t Motor_GetMotorRunStage(void){ + return motorandchippar.state.Motor_runstage ;; +} + +uint32_t Motor_GetMotorErrorState10s(void){ + return motorandchippar.MotorErrorState10s; +} + +uint8_t Motor_GetMotorStep(void){ + return motorpra.MM_Step; +} + +/*Invoke all set parameters of the motor*/ +M_Re_pra_t Motor_GetALLMotorSetparameters (void){ + return M_Re_pra; +} + +uint16_t Motor_GetMotorConstantspeed(void){ + return M_Re_pra.Constantspeed*16U; +} + +void Motor_GetSETLockCurrent(uint16_t *data1,uint16_t *data2){ + *data1 = M_Re_pra.LockACoilValtage; + *data2 = M_Re_pra.LockBCoilValtage; +} + +uint16_t Motor_GetCurrentPosition(void){ + return motorandchippar.Motor_position; +} + +uint8_t Motor_GetOnestep_csa_adcnt(void){ + static uint8_t adcnt = 0; + adcnt = Onestep_csa_adcnt; + if(adcnt == 0){ + adcnt = 10u; + } + return adcnt; +} + +#endif + +#if control_type == Divide_2 + +void Timer1_INTTest(void) +{ + +} +#elif control_type == Divide_6 +//uint32_t *flashdata = (uint32_t *)0xAC00U; +//uint32_t dataflash; +//uint32_t dataflash_b; +void Timer1_INTTest(void) +{ + uint8_t Motosteper = 0; + Count_20ms++; + + Calculation_position(); + + if(Motor_GetMotorState() == (uint8_t)MotorRun){ + motoradcItem = ADC_GetadcMeasParamm(); + if(motoradcItem.item != ADC_MEASURE_ITEM_VAMP){ + ADC_Init(ADC_MEASURE_ITEM_VAMP, 0); + SAR_CTRL_SFRS->SARINT.CLEAR.INT_CONV_DONE_CLR = 1U; + SAR_CTRL_SFRS->SARCTRL.SARENAREQ = 1U; + SAR_CTRL_SFRS->SARCTRL.CONVERT = 1U; + } + Motosteper = Motor_GetMotorStep(); + MOTORunP_24(Motosteper); + + } + + if((SAFM_TransferState() & 0xffu) != 0U) { + MotorOCstop10s++; + if(MotorOCstop10s > Motor_GetMotorErrorState10s()){ + MotorOCstop10s = 0U; + ClearMotorandchipparstate(); + } + } +// if(Count_20ms > 2000U){ +// Count_20ms = 0; +// f_FLASH_EraseSector(0xAC00U); +// FLASH_Write2WordsWithECC(0xAC00U,0XAAAAAAAA,0X55555555); +// dataflash = *flashdata; +// flashdata+=1; +// dataflash_b = *flashdata; +// } +} +#endif + +void MotorCtrl_TaskHandler(void) +{ + switch(motorState){ + case TASK_STATE_INIT: + /* Motor control initialization */ + StopMotor(); + /* End of Motor control initialization */ + motorState = TASK_STATE_ACTIVE; + break; + case TASK_STATE_ACTIVE: + break; + default: + break; + } +} \ No newline at end of file diff --git a/app_Indie/usr/common/motorControlTask.h b/app_Indie/usr/common/motorControlTask.h new file mode 100644 index 0000000..44c1b9e --- /dev/null +++ b/app_Indie/usr/common/motorControlTask.h @@ -0,0 +1,221 @@ +#ifndef MOTOR_CONTROL_TASK_H__ +#define MOTOR_CONTROL_TASK_H__ + +#include +#include +#include +#include +#include +#include + +//#define Time1_timing 8000U //500*16 :500us +#define ADC_period 20000U*48U/Time1_timing + +#if control_type == Divide_2 + +#define VAMP_Cnt 8 +#define ADC_period 20000U*48U/Time1_timing + +#define Downpwm_APhasePos_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x08U //PA3 ON(Upper bridge arm) +#define Downpwm_APhasePos_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x08U //PA3 OFF(Upper bridge arm) +#define Downpwm_APhasePos_Low_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x04U //PA2 OFF(Lower bridge arm) +#define Downpwm_APhasePos_Low_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x04U //PA2 ON(Lower bridge arm) + +#define Downpwm_APhaseNeg_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x40U //PA6 ON(Upper bridge arm) +#define Downpwm_APhaseNeg_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x40U //PA6 OFF(Upper bridge arm) +#define Downpwm_APhaseNeg_Low_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x20U //PA5 OFF(Lower bridge arm) +#define Downpwm_APhaseNeg_Low_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x20U //PA5 ON(Lower bridge arm) + +#define Downpwm_BPhasePos_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATASET |= 0x04U //PB2 ON(Upper bridge arm) +#define Downpwm_BPhasePos_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATACLR |= 0x04U //PB2 OFF(Upper bridge arm) +#define Downpwm_BPhasePos_Low_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATACLR |= 0x02U //PB1 OFF(Lower bridge arm) +#define Downpwm_BPhasePos_Low_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATASET |= 0x02U //PB1 ON(Lower bridge arm) + +#define Downpwm_BPhaseNeg_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x10U//PA4 ON(Upper bridge arm) +#define Downpwm_BPhaseNeg_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x10U //PA4 OFF(Upper bridge arm) +#define Downpwm_BPhaseNeg_Low_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATACLR |= 0x01U //PB0 OFF(Lower bridge arm) +#define Downpwm_BPhaseNeg_Low_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATASET |= 0x01U //PB0 ON(Lower bridge arm) + +#define Abridge_OFF do{ Downpwm_APhasePos_High_OFF;Downpwm_APhasePos_Low_OFF;Downpwm_APhaseNeg_High_OFF;Downpwm_APhaseNeg_Low_OFF;}while(0) +#define Bbridge_OFF do{ Downpwm_BPhasePos_High_OFF;Downpwm_BPhasePos_Low_OFF;Downpwm_BPhaseNeg_High_OFF;Downpwm_BPhaseNeg_Low_OFF;}while(0) +#define Twobridge_OFF do{ Abridge_OFF;Bbridge_OFF;}while(0) + +#elif control_type == Divide_6 + + #define VAMP_Cnt 24U + #define PWMAUX_Period 100U*16U + +#define Downpwm_APhasePos_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x08U //PA3 ON(Upper bridge arm) +#define Downpwm_APhasePos_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x08U //PA3 OFF(Upper bridge arm) +#define Downpwm_APhasePos_Low_ON do{PWMAUX_SetMatchValue(PWMAUX_CH5, 0, PWMAUX_Period);}while(0) //PA2 OFF(Lower bridge arm) +#define Downpwm_APhasePos_Low_OFF do{PWMAUX_SetMatchValue(PWMAUX_CH5, 0, 0);}while(0) //PA2 ON(Lower bridge arm) + +#define Downpwm_APhaseNeg_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x40U //PA6 ON(Upper bridge arm) +#define Downpwm_APhaseNeg_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x40U //PA6 OFF(Upper bridge arm) +#define Downpwm_APhaseNeg_Low_ON do{PWMAUX_SetMatchValue(PWMAUX_CH0, 0, PWMAUX_Period);}while(0) //PA5 OFF(Lower bridge arm) +#define Downpwm_APhaseNeg_Low_OFF do{PWMAUX_SetMatchValue(PWMAUX_CH0, 0, 0);}while(0) //PA5 ON(Lower bridge arm) + +#define Downpwm_BPhasePos_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATASET |= 0x04U //PB2 ON(Upper bridge arm) +#define Downpwm_BPhasePos_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOB].DATACLR |= 0x04U //PB2 OFF(Upper bridge arm) +#define Downpwm_BPhasePos_Low_ON do{PWMAUX_SetMatchValue(PWMAUX_CH2, 0, PWMAUX_Period);}while(0) //PB1 OFF(Lower bridge arm) +#define Downpwm_BPhasePos_Low_OFF do{PWMAUX_SetMatchValue(PWMAUX_CH2, 0, 0);}while(0) //PB1 ON(Lower bridge arm) + +#define Downpwm_BPhaseNeg_High_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATASET |= 0x10U//PA4 ON(Upper bridge arm) +#define Downpwm_BPhaseNeg_High_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOA].DATACLR |= 0x10U //PA4 OFF(Upper bridge arm) +#define Downpwm_BPhaseNeg_Low_ON do{PWMAUX_SetMatchValue(PWMAUX_CH1, 0, PWMAUX_Period);}while(0) //PB0 OFF(Lower bridge arm) +#define Downpwm_BPhaseNeg_Low_OFF do{PWMAUX_SetMatchValue(PWMAUX_CH1, 0, 0);}while(0) //PB0 ON(Lower bridge arm) + +#define Abridge_OFF do{ Downpwm_APhasePos_High_OFF;Downpwm_APhasePos_Low_OFF;Downpwm_APhaseNeg_High_OFF;Downpwm_APhaseNeg_Low_OFF;}while(0) +#define Bbridge_OFF do{ Downpwm_BPhasePos_High_OFF;Downpwm_BPhasePos_Low_OFF;Downpwm_BPhaseNeg_High_OFF;Downpwm_BPhaseNeg_Low_OFF;}while(0) +#define Twobridge_OFF do{ Abridge_OFF;Bbridge_OFF;}while(0) + +#endif + +#define MotorPower_ON GPIO_SFRS->GPIO_SET[GROUP_GPIOC].DATASET |= 0x08U +#define MotorPower_OFF GPIO_SFRS->GPIO_SET[GROUP_GPIOC].DATACLR |= 0x08U + +#define VDD3V3EXT_ON do{TRIMHV_SFRS->BORTESTMODE.VDD33EXT_EN = 1U;}while(0) +#define VDD3V3EXT_OFF do{TRIMHV_SFRS->BORTESTMODE.VDD33EXT_EN = 0U;}while(0) + + + +typedef enum{ + MotorStop = 0U, + MotorRun, +}MotorRunState_t; + +typedef enum{ + MotorNoOC= 0U, + MotorOC, +}MotorOCState_t; + +typedef enum{ + CoilNomal = 0U, + CoilOpen, + CoilShort, +}CoilState_t; + +typedef enum{ + Constantstage = 0U, + Climbstage, + Slowstage, +}RunStage_t; + +typedef struct{ + uint32_t T1timercnt; + uint16_t SlowSteper; + uint16_t ClimbSteper; + uint16_t ClimbTime; + uint16_t SlowTime; + uint8_t MM_Step; + uint32_t stepr; + uint32_t stepn; + uint32_t s; + +}Motorpra_t; + +typedef struct{ + uint8_t M_ON; + uint16_t Constantspeed; + uint16_t Startspeed; + uint16_t Slowspeed; + uint16_t LockACoilValtage; + uint16_t LockBCoilValtage; + uint8_t ClimbTime; + uint8_t SlowTime; + uint16_t Position; +}M_Re_pra_t; + +//Response master +typedef struct{ + int16_t Tchip; //chip temperature 1C + uint16_t vbat; //vbat mv + + union{ + struct{ + uint8_t tchipstate :1; //0 Õý³£ 1 ³¬Î + uint8_t Motor_overcur :1;//0£ºÎ´³¬ÔØ 1:³¬ÔØ + uint8_t Motor_coilAsta :2;//0£ºÕý³££»1£º¿ªÂ·£»2£º¶Ì·£» + uint8_t Motor_coilBsta :2;//0£ºÕý³££»1£º¿ªÂ·£»2£º¶Ì·£» + uint8_t VBAT_sta :2;//VBATµçѹ 0£ºÕý³£ 1£ºµÍѹ±¨¾¯ 2£º¸ßѹ±¨¾¯ + + uint8_t Motor_runsta :1;//1£ºÔËÐУ¬0£ºÍ£Ö¹ + uint8_t Motor_runstage :2;//0£ºÔÈËٽ׶Σ»1£º¼ÓËٽ׶Σ»2£º¼õËٽ׶Π+ + }; + uint8_t byte[2]; + }state; + uint32_t MotorErrorState10s; + uint16_t Motor_lockAcoilcurrent; //´¥·¢¶Âתֹͣ¹¦ÄÜʱµÄAcoilÔË·ÅÊä³ö¶Ëµçѹ mv + uint16_t Motor_lockBcoilcurrent; //´¥·¢¶Âתֹͣ¹¦ÄÜʱµÄBcoilÔË·ÅÊä³ö¶Ëµçѹ mv + uint16_t Motor_position; //µ±Ç°ÔËÐÐλÖà ²½ +}Motor_and_ChipPar_t; + + +typedef union{ + struct{ + uint8_t nodeAddress; + uint8_t ON :1; //1:ÔËÐÐÔËת ÆäËü£º½ûÖ¹ + uint8_t reserve :7; + uint16_t Position; + uint8_t reserve1; + uint8_t reserve2; + uint8_t reserve3; + uint8_t reserve4; + }; + uint8_t data[LIN_BUFF_SIZE]; /*!< data buffer. */ + uint16_t data16[LIN_BUFF_SIZE/2]; +}MotorCtrlFrame_t; + + + +void delay(uint32_t delayus); +void MOTORunP_24(uint8_t motorstep); +void StopMotor(void); + +uint8_t ReturnClearT1cntFlag(void); +uint8_t Motor_GetMotorState(void); +uint8_t Motor_GetMotorRunStage(void); + +uint32_t Motor_GetMotorErrorState10s(void); + +void Get_MotorprafromLINM(LIN_Device_Frame_t const *frame); +void Calculation_position(void); +void Motor_GetSETLockCurrent(uint16_t *data1,uint16_t *data2); +uint8_t Motor_GetMotorStep(void); +M_Re_pra_t Motor_GetALLMotorSetparameters (void); +uint16_t Motor_GetMotorConstantspeed(void); +uint16_t Motor_GetCurrentPosition(void); +uint8_t Motor_GetOnestep_csa_adcnt(void); +void MOTOR_TaskHandler(void); + +void MotorCtrl_TaskHandler(void); + +void MOTORunP_8(uint8_t motorstep); +void MOTORunP_24(uint8_t motorstep); + + + +void Timer1_INTTest(void); +uint8_t GetVAMPCNT(void); +void ClearVAMPCNT(void); +uint8_t GetVBATCNT(void); +void ClearVBATCNT(void); + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/pdsTask.c b/app_Indie/usr/common/pdsTask.c new file mode 100644 index 0000000..f857254 --- /dev/null +++ b/app_Indie/usr/common/pdsTask.c @@ -0,0 +1,252 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file pdsTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uint8_t pds_store(uint8_t index); + +static SystemParams_t systemParam; +static Userdata_t userdata; +static TaskState_t pdsState = TASK_STATE_INIT; +static PdsStatus_t pdsStatus = PDS_STATUS_USING_NORMAL; + +#define PDS_ACTIVE_DATA_INDEX (0U) +#define PDS_ACTIVE_DATA_BACKUP_INDEX (1U) + +void PDS_PowerONRead_MotorParamfromFlash(uint16_t *buff,uint16_t leng) +{ + for (uint16_t i = 0U; i < leng; i++){ + *buff = systemParam.info.motorParams.data16[i]; + buff++; + } +} + +void PDS_Init(void) +{ + uint32_t crcValue; + uint32_t crcValueuserdata; + CRC32_Init(); + + Userdata_t *Motorstep= (Userdata_t *)FLASH_START_ADDRESS_USER_DATA; + crcValueuserdata = CRC32_GetRunTimeCRC32((uint8_t *)&Motorstep->info ,(uint16_t)sizeof(Motorstep->info)); + + if(crcValueuserdata == Motorstep->head.crc32){ + userdata = *Motorstep; + }else{ + userdata.info.data[0] = 0; + userdata.info.data[1] = 0; + } + + CRC32_Init(); + SystemParams_t *param = (SystemParams_t *)FLASH_START_ADDRESS_SYSTEM_DATA; + crcValue = CRC32_GetRunTimeCRC32((uint8_t *)¶m->info ,(uint16_t)sizeof(param->info)); + if (crcValue == param->head.crc32){ + systemParam = *param; + pdsStatus = PDS_STATUS_USING_NORMAL; + }else{ + param = (SystemParams_t *)FLASH_START_ADDRESS_SYSTEM_DATA_BACK_UP; + crcValue = CRC32_GetRunTimeCRC32((uint8_t *)¶m->info ,(uint16_t)sizeof(param->info)); + if (crcValue == param->head.crc32){ + systemParam = *param; + pdsStatus = PDS_STATUS_USING_BACKUP; + }else{ + pdsStatus = PDS_STATUS_USING_DEFAULT; + } + } + pdsStatus = PDS_STATUS_USING_DEFAULT; + if (pdsStatus == PDS_STATUS_USING_DEFAULT){ +/* **********************fix LIN configuration default value ************************************/ + systemParam.head.index = 0U; + systemParam.info.linParams.nad = INIT_LINS_NAD_ADDR; + systemParam.info.linParams.supplierID = LINS_SUPPLIER_ID; + systemParam.info.linParams.functionID = LINS_FUNCTION_ID; + systemParam.info.linParams.variant = LINS_VARIANT; + systemParam.info.linParams.serialNo = LINS_SERIAL_NO; + systemParam.info.linParams.fwVersion = LINS_FW_VERSION; + systemParam.info.linParams.hwVersion = LINS_HW_VERSION; + + systemParam.info.motorParams.Constantspeed = DEFAULT_CONSTANTSPEED; + systemParam.info.motorParams.startspeed = DEFAULT_STARTSPEED; + systemParam.info.motorParams.Slowspeed = DEFAULT_SLOWSPEED; + systemParam.info.motorParams.MotorlockAcoilvoltage = DEFAULT_ACOILVOLTAGE; + systemParam.info.motorParams.MotorlockBcoilvoltage = DEFAULT_BCOILVOLTAGE; + systemParam.info.motorParams.ClimbTime = DEFAULT_CLIMBTIME; + systemParam.info.motorParams.SlowTime = DEFAULT_SLOWTIME; + +// GetMotorPhyParam[0] = systemParam.info.motorParams.Constantspeed;//Constantspeed us/step +// GetMotorPhyParam[1] = systemParam.info.motorParams.startspeed;//Motorlock startspeed us/step +// GetMotorPhyParam[2] = systemParam.info.motorParams.Slowspeed;//Motorlock Slowspeed us/step +// GetMotorPhyParam[3] = systemParam.info.motorParams.MotorlockAcoilvoltage;//Motorlock Acoil voltage +// GetMotorPhyParam[4] = systemParam.info.motorParams.MotorlockBcoilvoltage;//Motorlock Bcoil voltage +// GetMotorPhyParam[5] = systemParam.info.motorParams.ClimbTime + (uint16_t)systemParam.info.motorParams.SlowTime << 8;//ClimbTime: ms low8bit, SlowTime: ms high8bit + + + LIN_Device_Frame_t volatile *frame = LINS_GetUcndFramesTable(&systemParam.info.linParams.frameIDSize); + for (uint8_t i = 0; i < systemParam.info.linParams.frameIDSize; i++){ + systemParam.info.linParams.frameInfo[i].frameId = frame[i].frame_id; + systemParam.info.linParams.frameInfo[i].frameIsValid = TRUE; + } + } + ls_set_initialNad(INIT_LINS_NAD_ADDR); + ls_set_nad(INIT_LINS_NAD_ADDR); + /* must be call here for init LIN param */ + LNCI_Init(); +} + + +uint8_t pds_store(uint8_t index) +{ +/****************************************************************************************************************/ + static uint16_t motorbuffdata[TransferCNT]; +/*Take out new parameters for the motor through the 3C command*/ + LINS_Transfer3CdataToPDS(motorbuffdata,TransferCNT); + for(uint8_t n=0;n> 2U); + + pdsStatus = PDS_STATUS_USING_NORMAL; + + if (index == PDS_ACTIVE_DATA_INDEX){ + /*write sys data normal*/ + f_FLASH_EraseSector(FLASH_START_ADDRESS_SYSTEM_DATA); + for (uint32_t i = 0; i < wordLength; i+=2){ + f_FLASH_Write2WordsWithECC(FLASH_START_ADDRESS_SYSTEM_DATA +i*4U, pWord[i],pWord[i+1]); + } + }else{ + /*write sys data back up*/ + f_FLASH_EraseSector(FLASH_START_ADDRESS_SYSTEM_DATA_BACK_UP); + for (uint32_t i = 0; i < wordLength; i++){ + f_FLASH_Write2WordsWithECC(FLASH_START_ADDRESS_SYSTEM_DATA_BACK_UP +i*4U, pWord[i],pWord[i+1]); + } + } + return 0U; +} + +void userdatapds_store(void)//½øÐÝÃßʱ±£´æÒ»´Î +{ +/****************************************************************************************************************/ + + userdata.info.data[0] = Motor_GetCurrentPosition(); + userdata.info.data[1] = Motor_GetCurrentPosition() >> 16U; + + uint16_t wordLength; + uint32_t *pWord = (uint32_t *)((void *)&userdata); + uint32_t crcValue = CRC32_GetRunTimeCRC32((uint8_t *)(&userdata.info) ,(uint16_t)sizeof(userdata.info)); + userdata.head.crc32 = crcValue; + userdata.head.index ++; + + Flash_EraseSector(FLASH_START_ADDRESS_USER_DATA); + + /* sizeof(Userdata_t) is the timers of word */ + wordLength = ((uint32_t)sizeof(Userdata_t) >> 2U); + + /*write sys data normal*/ + for (uint32_t i = 0; i < wordLength; i++){ + FLASH_Write2WordsWithECC(FLASH_START_ADDRESS_USER_DATA+i*8U,pWord[i*2],pWord[i*2+1]); + } + +// CRC32_Init(); + +// Userdata_t *Motorstep= (Userdata_t *)FLASH_START_ADDRESS_USER_DATA; +// uint32_t crcValueuserdata = CRC32_GetRunTimeCRC32((uint8_t *)&Motorstep->info ,(uint16_t)sizeof(Motorstep->info)); + +// if(crcValueuserdata == Motorstep->head.crc32){ +// userdata = *Motorstep; +// }else{ +// userdata.info.data[0] = 0; +// userdata.info.data[1] = 0; +// } +} + +MotorClusterParams_t *PDS_GetMotorParam(void) +{ + return &systemParam.info.motorParams; +} + +LINClusterParams_t *PDS_GetLINParam(void) +{ + return &systemParam.info.linParams; +} + +PdsStatus_t PDS_GetPdsStatus(void) +{ + return pdsStatus; +} + +uint32_t PDS_GetMotorstepnfromflash(void) +{ + uint32_t motorstepn = 0; + motorstepn = userdata.info.data[1]; + motorstepn <<= 16U; + motorstepn += userdata.info.data[0]; + + return motorstepn; +} + +void PDS_TaskHandler(void) +{ + switch(pdsState){ + case TASK_STATE_INIT: + pdsState = TASK_STATE_ACTIVE; + break; + case TASK_STATE_ACTIVE: + /* storage system parameters */ + (void)pds_store(PDS_ACTIVE_DATA_INDEX); + pdsState = TASK_STATE_PROCESSING; + //TM_PostTask(TASK_ID_PDS); + break; + case TASK_STATE_PROCESSING: + /* storage system parameters backup*/ + (void)pds_store(PDS_ACTIVE_DATA_BACKUP_INDEX); + /* set save parameters flag for lin stack*/ + (void)ls_save_configuration(); + pdsState = TASK_STATE_ACTIVE; + break; + default: + break; + } +} + + + + + + + + + + + + + + + diff --git a/app_Indie/usr/common/pdsTask.h b/app_Indie/usr/common/pdsTask.h new file mode 100644 index 0000000..b7d7250 --- /dev/null +++ b/app_Indie/usr/common/pdsTask.h @@ -0,0 +1,97 @@ +#ifndef PDS_H__ +#define PDS_H__ + +#include +#include +#include + +/**************************************************************************************************/ +#define DEFAULT_CONSTANTSPEED (700U) +#define DEFAULT_STARTSPEED (1500U) +#define DEFAULT_SLOWSPEED (1500U) +#define DEFAULT_ACOILVOLTAGE (60U) +#define DEFAULT_BCOILVOLTAGE (60U) +#define DEFAULT_CLIMBTIME (200U) +#define DEFAULT_SLOWTIME (200U) + +#define TransferCNT (6U) + +typedef union{ + struct{ + uint16_t Constantspeed; + uint16_t startspeed; + uint16_t Slowspeed; + uint16_t MotorlockAcoilvoltage; + uint16_t MotorlockBcoilvoltage; + uint8_t ClimbTime; + uint8_t SlowTime; + uint16_t reservedata[4]; + }; + uint16_t data16[10]; + uint32_t data32[5]; +}MotorClusterParams_t; + +typedef struct{ + uint8_t frameId; + uint8_t frameIsValid; +}FrameID_t; + +/**************************************************************************************************/ +/* lin parameters */ +typedef union{ + /* 16 + 32*2 = 80 */ + struct{ + uint16_t fwVersion; /* Reserved should be LINS_FW_VERSION */ + uint16_t hwVersion; /* Reserved should be LINS_HW_VERSION */ + uint32_t serialNo; /* Reserved should be LINS_SERIAL_NO */ + uint16_t supplierID; /* Reserved should be LINS_SUPPLIER_ID */ + uint16_t functionID; /* Reserved should be LINS_FUNCTION_ID */ + uint8_t variant; /* Reserved should be LINS_VARIANT */ + uint8_t nad; + uint8_t frameIDSize; + FrameID_t frameInfo[32]; + }; + uint8_t payload[96U]; +}LINClusterParams_t; +/**************************************************************************************************/ + +typedef enum{ + PDS_STATUS_USING_NORMAL, + PDS_STATUS_USING_BACKUP, + PDS_STATUS_USING_DEFAULT, +}PdsStatus_t; + + + +typedef struct{ + struct{ + uint32_t crc32; + uint32_t index; + }head; /* size = 8 bytes */ + struct{ + LINClusterParams_t linParams; /* size = 96 bytes */ + MotorClusterParams_t motorParams; /* size = 20bytes */ + }info; +}SystemParams_t; + +typedef struct{ + struct{ + uint32_t crc32; + uint32_t index; + }head; + struct{ + uint16_t data[2]; /* size = 4 bytes */ + }info; +}Userdata_t; + +MotorClusterParams_t *PDS_GetMotorParam(void); +uint32_t PDS_GetMotorstepnfromflash(void); +void PDS_PowerONRead_MotorParamfromFlash(uint16_t *buff,uint16_t leng); +void userdatapds_store(void); + +LINClusterParams_t *PDS_GetLINParam(void); +PdsStatus_t PDS_GetPdsStatus(void); +void PDS_Init(void); +void PDS_TaskHandler(void); + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/safetyMonitorTask.c b/app_Indie/usr/common/safetyMonitorTask.c new file mode 100644 index 0000000..390458f --- /dev/null +++ b/app_Indie/usr/common/safetyMonitorTask.c @@ -0,0 +1,177 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file safetyMonitorTask.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include + +#define OVER_TEMPERATURE_HIGH (130) /*celsius degree */ +#define OVER_TEMPERATURE_RELEASE (OVER_TEMPERATURE_HIGH - 10U) /*celsius degree */ + + +#define MotorLocked 230u //mA + +static void UnderVoltageProtection_ISR(void); +static void OverVoltageProtection_ISR(void); +static void safetyHandle(void); +static void safetyInit(void); + +//static int16_t vCurrentMotor; +uint16_t *p; +static int16_t vAmp[24]; +static uint32_t sum=0; +static uint16_t Motorcurrent=0; +static uint32_t VbatMotorcurrent=0; +static uint16_t Lockcnt=0; + +static TaskState_t safeMonitorState = TASK_STATE_INIT; +static BatteryState_t battState = BATT_STATE_NORMAL; +static BatteryState_t battLastState = BATT_STATE_NORMAL; +static ChipTemperatureState_t chipTemperatureState = CHIP_TEMPERATURE_STATE_NORMAL; +static ChipTemperatureState_t chipTemperatureLastState = CHIP_TEMPERATURE_STATE_NORMAL; + +static void UnderVoltageProtection_ISR(void); +static void OverVoltageProtection_ISR(void); +static void safetyHandle(void); +static void safetyInit(void); +static void safeMonitorTimerExpired(SoftTimer_t *timer); +static Motor_and_ChipPar_t motorandchipstate; + +static SoftTimer_t safeMonitorTimer = { + .mode = TIMER_PERIODIC_MODE, + .interval = 200U, + .handler = safeMonitorTimerExpired +}; + + +static void safeMonitorTimerExpired(SoftTimer_t *timer) +{ + TM_PostTask(TASK_ID_SAFETY_MONITOR); +} + +void SAFM_TaskHandler(void) +{ + switch(safeMonitorState){ + case TASK_STATE_INIT: + safetyInit(); +// SoftTimer_Start(&safeMonitorTimer); + safeMonitorState = TASK_STATE_ACTIVE; + break; + case TASK_STATE_ACTIVE: + safetyHandle(); + break; + default: + break; + } +} + +static void safetyHandle(void) +{ + /* Battery Voltage Protection Handling */ + battState = (BatteryState_t)HW_PROT_GetBattVoltState(); + if ((chipTemperatureLastState != chipTemperatureState) || (battLastState != battState)){ + chipTemperatureLastState = chipTemperatureState; + battLastState = battState; + if (battState == BATT_STATE_LOW){ + StopMotor(); + }else{ + if (chipTemperatureState == CHIP_TEMPERATURE_STATE_HIGH){ + StopMotor(); + }else{ + } + /* Restart OV UV ISR */ + PMUA_SFRS->PMUIRQ.CLEAR.OV_CLR = 1U; + PMUA_SFRS->PMUIRQ.CLEAR.UV_CLR = 1U; + NVIC_ClearPendingIRQ(UV_OV_IRQn); + NVIC_EnableIRQ(UV_OV_IRQn); + } + } + if(Motor_GetMotorRunStage() == (uint8_t)Constantstage){ + +// vCurrentMotor = MEAGet_vAmp(); + p = MEAGet_vAmpbuff(); + sum = 0; + for(uint8_t i=0;i<24;i++){ + vAmp[i]=*p; + if(vAmp[i]<0){ + vAmp[i] = 0-vAmp[i]; + } + sum += vAmp[i]; + p++; + } + Motorcurrent = sum*4/24; +// DEBUG_OUT("Current\t%3d\n",Motorcurrent); + VbatMotorcurrent = MEA_GetVbat(); + VbatMotorcurrent = (VbatMotorcurrent*176-120460)/10000;// + if(Motorcurrent > VbatMotorcurrent){ + Lockcnt++; + if(Lockcnt>2){ +// StopMotor(); +// motorandchipstate.state.Motor_overcur = (uint8_t)MotorOC; + } + }else{ + Lockcnt = 0; + motorandchipstate.state.Motor_overcur = (uint8_t)MotorNoOC; + } + } +} + + +static void UnderVoltageProtection_ISR(void) +{ + TM_PostTask(TASK_ID_SAFETY_MONITOR); +} + +static void OverVoltageProtection_ISR(void) +{ + TM_PostTask(TASK_ID_SAFETY_MONITOR); +} + + +static void safetyInit(void) +{ + HW_PROT_SetUnderVoltage(UV_VOLT_5_1V,UNDER_VOLT_HYS_830mV, VOLT_DEBOUNCE_TIME_10ms, VOLT_DEBOUNCE_TIME_10ms); + HW_PROT_RegisterUnderVoltageIRQ(UnderVoltageProtection_ISR); + + HW_PROT_SetOverVoltage(OV_VOLT_20_0V, OV_VOLT_HYS_1440mV, VOLT_DEBOUNCE_TIME_10ms, VOLT_DEBOUNCE_TIME_10ms); + HW_PROT_RegisterOverVoltageIRQ(OverVoltageProtection_ISR); + +} + + +BatteryState_t SAFM_GetBatteryState(void) +{ + return battState; +} + +ChipTemperatureState_t SAFM_GetChipTemperatureState(void) +{ + return chipTemperatureState; +} +uint16_t SAFM_GetMotorcurrent(void) +{ + return Motorcurrent; +} +/*Call this function when you need to use the status value*/ +uint8_t SAFM_TransferState(void) +{ + motorandchipstate.state.VBAT_sta = (uint8_t)HW_PROT_GetBattVoltState(); + motorandchipstate.state.tchipstate = (uint8_t)HW_PROT_ChipIsOverHeat(); + return motorandchipstate.state.byte[0]; +} + +void ClearMotorandchipparstate(void){ + motorandchipstate.state.byte[0] = 0; +} + diff --git a/app_Indie/usr/common/safetyMonitorTask.h b/app_Indie/usr/common/safetyMonitorTask.h new file mode 100644 index 0000000..601e74a --- /dev/null +++ b/app_Indie/usr/common/safetyMonitorTask.h @@ -0,0 +1,34 @@ +#ifndef SAFETY_MONITOR_TASK_H +#define SAFETY_MONITOR_TASK_H + +#include +#include +#include +#include +#include +#include +#include + + +typedef enum { + BATT_STATE_NORMAL = 0U, + BATT_STATE_LOW, + BATT_STATE_HIGH, + BATT_STATE_RESVD, +}BatteryState_t; + +typedef enum { + CHIP_TEMPERATURE_STATE_NORMAL = 0U, + CHIP_TEMPERATURE_STATE_LOW, + CHIP_TEMPERATURE_STATE_HIGH, +}ChipTemperatureState_t; + + +BatteryState_t SAFM_GetBatteryState(void); +ChipTemperatureState_t SAFM_GetChipTemperatureState(void); +uint16_t SAFM_GetMotorcurrent(void); +void SAFM_TaskHandler(void); +uint8_t SAFM_TransferState(void); +void ClearMotorandchipparstate(void); + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/systemInit.c b/app_Indie/usr/common/systemInit.c new file mode 100644 index 0000000..d3df03a --- /dev/null +++ b/app_Indie/usr/common/systemInit.c @@ -0,0 +1,117 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file systemInit.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void gpios_init(void); +void pmu_init(void); + + + +void gpios_init(void) +{ +#if control_type == Divide_2 + GPIO_Init(GROUP_GPIOA,GPIO_PORT_3, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); //Downpwm_ACoil Pos side upper arm: GPIO + GPIO_Init(GROUP_GPIOA,GPIO_PORT_2, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_ACoil Pos side down arm: PWM + + GPIO_Init(GROUP_GPIOA,GPIO_PORT_6, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_ACoil NEG side upper arm: GPIO + GPIO_Init(GROUP_GPIOA,GPIO_PORT_5, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); //Downpwm_ACoil Neg side down arm: PWM + + + GPIO_Init(GROUP_GPIOB,GPIO_PORT_2, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_BCoil Pos side upper arm: GPIO + GPIO_Init(GROUP_GPIOB,GPIO_PORT_1, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_BCoil Pos side down arm: PWM + + GPIO_Init(GROUP_GPIOA,GPIO_PORT_4, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); //Downpwm_BCoil Neg side upper arm: GPIO + GPIO_Init(GROUP_GPIOB,GPIO_PORT_0, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_BCoil Neg side down arm: PWM + +#elif control_type == Divide_6 + + GPIO_Init(GROUP_GPIOA,GPIO_PORT_3, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); //Downpwm_ACoil Pos side upper arm: GPIO + GPIO_Init(GROUP_GPIOA,GPIO_PORT_6, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_ACoil NEG side upper arm: GPIO + GPIO_Init(GROUP_GPIOB,GPIO_PORT_2, GPIO_DIR_OUTPUT,GPIO_PULL_NONE);//Downpwm_BCoil Pos side upper arm: GPIO + GPIO_Init(GROUP_GPIOA,GPIO_PORT_4, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); //Downpwm_BCoil Neg side upper arm: GPIO + + PWMAUX_Init(GROUP_GPIOA,GPIO_PORT_2,PWMAUX_CH5,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,PWMAUX_Period); //Downpwm_ACoil Pos side down arm: PWMAUX5 + PWMAUX_Init(GROUP_GPIOA,GPIO_PORT_5,PWMAUX_CH0,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,PWMAUX_Period); //Downpwm_ACoil Neg side down arm: PWMAUX0 + + PWMAUX_Init(GROUP_GPIOB,GPIO_PORT_1,PWMAUX_CH2,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,PWMAUX_Period); //Downpwm_BCoil Neg side down arm: PWMAUX2 + PWMAUX_Init(GROUP_GPIOB,GPIO_PORT_0,PWMAUX_CH1,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,PWMAUX_Period); //Downpwm_BCoil Pos side down arm: PWMAUX1 + +// PWM_AUX_SFRS->INVERT = 0X3FU; +// +// PWMAUX_SetMatchValue(PWMAUX_CH5, 0, PWMAUX_Period/2);//PWMAUX5:PA2 +// PWMAUX_SetMatchValue(PWMAUX_CH0, 0, PWMAUX_Period/4);//PWMAUX0:PA5 +// PWMAUX_SetMatchValue(PWMAUX_CH2, 0, PWMAUX_Period/6);//PWMAUX2:PB1 +// PWMAUX_SetMatchValue(PWMAUX_CH1, 0, PWMAUX_Period/8);//PWMAUX1:PB0 + +#endif + + GPIO_Init(GROUP_GPIOB,GPIO_PORT_3, GPIO_DIR_INPUT,GPIO_PULL_NONE);//ADC Postion: Full scale + GPIO_Init(GROUP_GPIOC,GPIO_PORT_4, GPIO_DIR_INPUT,GPIO_PULL_NONE);//ADC Postion: Resistance partial voltage value + GPIO_Init(GROUP_GPIOC,GPIO_PORT_3, GPIO_DIR_OUTPUT,GPIO_PULL_DOWN); +} + +void pmu_init(void) +{ +// /* Init set BOR voltage level for cpu low voltage safety*/ +// PMU_BORInit(S_BOR_1P5V, BOR_3V3_THRS_2998mV); +// /* Disable wake up timer */ +// PMU_WakeTimerInit(WAKEUP_TIMEER_DISABLE, WAKEUP_TIMEER_INTERVAL_32768ms); +} + + +void SYS_Init(void) +{ + /* Enable trim revise access enable*/ + HWCFG_TrimAccessUnlock(); + + TRIMHV_SFRS->PMUTRIM.VDD1V5_LDO_TRIM = 3U; + + CRGA_SFRS->MODULERSTREQ = 0xFFU; + /* Init system clock */ + Clock_SystemMainClockInit(SYS_MAIN_CLOCK_DIV); + pmu_init(); + /* Init global timer engine for driving soft timer */ + SysTick_Init(SOFT_TIMER_INTERVAL *1000U * MAIN_CPU_CLOCK, SoftTimer_ExpireCallback); +#if WATCH_DOG_EN == 1U + WDTA_Enable(WDTA_INTERVAL_18432MS); /* 8s */ +#endif + /* Init gpios settings */ + gpios_init(); + /*HWCFG_TrimAccessLockUntilReset();*/ + + ADC_GeneralInit(); + + TIMER_Init(TIMER1, HW_TIMER_PERIODIC_MODE, GTIMER_CLK_DIV_1,1000*16, Timer1_INTTest);//Time1_timing + + /* tasks init must be called before use. */ + TM_PostTask(TASK_ID_SOFT_TIMER); + TM_PostTask(TASK_ID_SAFETY_MONITOR); + TM_PostTask(TASK_ID_LINS); + //TM_PostTask(TASK_ID_PDS); + TM_PostTask(TASK_ID_ADC_MEASURE); + TM_PostTask(TASK_ID_APPL); +} + + + diff --git a/app_Indie/usr/common/systemInit.h b/app_Indie/usr/common/systemInit.h new file mode 100644 index 0000000..46e4911 --- /dev/null +++ b/app_Indie/usr/common/systemInit.h @@ -0,0 +1,35 @@ +#ifndef _SYSTEM_INIT_H + +#include +#include "systick_device.h" +#include +#include "flash_device.h" + +#include +#include +#include +#include + +void SYS_Init(void); + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/taskManager.c b/app_Indie/usr/common/taskManager.c new file mode 100644 index 0000000..fd62aed --- /dev/null +++ b/app_Indie/usr/common/taskManager.c @@ -0,0 +1,114 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file taskManager.c + * @Author: Jack.Pan + * @E-mail:jack.pan@indiemicro.com + * @Date: 2020/09/10 + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static volatile uint16_t taskFlags = 0U; +static uint16_t tasksMask = 0xFFFFU; +void IdleTask(void); + +typedef void (*taskHandler_t)(void); + +static taskHandler_t taskHandlers[] = { + [TASK_ID_SOFT_TIMER] = SoftTimer_TaskHandler, /* Global Timer task */ + [TASK_ID_LIN_STACK] = LinStack_TaskHandler, /* LIN stack task */ + [TASK_ID_LINS] = LINS_TaskHandler, /* LIN Slave task */ + //[TASK_ID_PDS] = PDS_TaskHandler, /*!< Task ID of persistance data storage*/ + [TASK_ID_ADC_MEASURE] = MES_TaskHandler, /* ADC measurement, chip temperature, Led PN volt, Battery Volt etc. */ + [TASK_ID_SAFETY_MONITOR] = SAFM_TaskHandler, /* safe monitor task */ + [TASK_ID_APPL] = APPL_TaskHandler, /* design for debug and demo */ +}; + +void IdleTask(void) +{ + + +} + +void TM_RunTasks(void) +{ + uint8_t taskId; + for (taskId = 0U; taskId < (uint8_t)(sizeof(taskHandlers) / sizeof(taskHandlers[0])); taskId++){ + if ( (((uint16_t)1UL << taskId) & (taskFlags & tasksMask)) != 0U ){ + __atomic_enter() + taskFlags &= ~((uint16_t)1UL << taskId); + __atomic_exit() + if (taskHandlers[taskId] != NULL){ + taskHandlers[taskId](); + } + break; + } + } + +#if WATCH_DOG_EN == 1U + WDTA_Clear(); /* Feeding Watch dog */ +#endif + + if (taskFlags == 0U){ + IdleTask(); + } +} + +/* + * Disables specified task. + * @param [in] taskId - task to be disabled. + * @return none + */ +void TM_DisableTask(TM_TaskId_t taskId) +{ + tasksMask &= ~(uint16_t)(1UL << taskId); +} + +/* + * brief Enables specified task. + * @param [in] taskId - task to be enabled. + * @return none + */ +void TM_EnableTask(TM_TaskId_t taskId) +{ + tasksMask |= (uint16_t)(1UL << taskId); +} + +/* + * brief runs specified task. + * @param [in] taskId - task to be run. + * @return none + */ +void TM_PostTask(TM_TaskId_t taskId) +{ + __atomic_enter() + taskFlags |= (uint16_t)(1UL << taskId); + __atomic_exit() +} + +uint8_t TM_TaskIsPending(TM_TaskId_t taskId) +{ + uint16_t flags = taskFlags; + uint16_t tasks = (uint16_t)1U << taskId; + if ( (tasks & flags)!= 0U ){ + return 1U; + }else{ + return 0U; + } +} \ No newline at end of file diff --git a/app_Indie/usr/common/taskManager.h b/app_Indie/usr/common/taskManager.h new file mode 100644 index 0000000..5b8d34e --- /dev/null +++ b/app_Indie/usr/common/taskManager.h @@ -0,0 +1,73 @@ +#ifndef TASK_MANAGER_H__ +#define TASK_MANAGER_H__ + +#include +#include +#include +#include + + + +/*! The list of task IDs. The IDs are sorted according to descending +priority. For each task ID there is the corresponding task handler function. */ +typedef enum +{ + TASK_ID_SOFT_TIMER = 0U, /*!< Task ID of Global timer*/ + TASK_ID_LIN_STACK, /*!< Task ID of LIN stack*/ + TASK_ID_LINS, /*!< Task ID of LIN slave*/ + //TASK_ID_PDS, /*!< Task ID of persistance data storage*/ + TASK_ID_ADC_MEASURE, /*!< Task ID of ADC measurement*/ + TASK_ID_SAFETY_MONITOR, /*!< Task ID of Safety protection*/ + TASK_ID_APPL, /*!< Task ID of APPlication purpose for debug and demo*/ +} TM_TaskId_t; + +typedef enum{ + TASK_STATE_INIT = 0U, + TASK_STATE_ACTIVE, + TASK_STATE_PROCESSING, + TASK_STATE_IDLE, +}TaskState_t; + + +/* + * brief runs specified task. + * @param [in] taskId - task to be run. + * @return none + */ +void TM_PostTask(TM_TaskId_t taskId); + +/* + * brief Enables specified task. + * @param [in] taskId - task to be enabled. + * @return none + */ +void TM_EnableTask(TM_TaskId_t taskId); + +/* + * Disables specified task. + * @param [in] taskId - task to be disabled. + * @return none + */ +void TM_DisableTask(TM_TaskId_t taskId); + +/* + * get the state of specified task. + * @param [in] taskId - task to be disabled. + * @return 0: task is not pending, other: task is pending to be handle + */ +uint8_t TM_TaskIsPending(TM_TaskId_t taskId); + +/* + * brief task manager. + * @return none + */ +void TM_RunTasks(void); + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/common/validation.c b/app_Indie/usr/common/validation.c new file mode 100644 index 0000000..476422a --- /dev/null +++ b/app_Indie/usr/common/validation.c @@ -0,0 +1,190 @@ +#include +#if ENABLE_FUNCTION_VALIDATION == 1 + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +SYSCTRLA_SFRS_t sysCtrl; +void PWM0_0(void); +void SPI(void); +void UART0(void); +void CT3_COUNTER(void); + +uint16_t PT0data=0; +uint16_t Rdata_SPI=0; +uint16_t Tdata_UART0=0X55,Rdata_UART0=0; +uint16_t CT3CV_data=0; +void PWM0_0(void) +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U; + + IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02<<20; // PB5 0x2: PWM0_0. + IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02<<24; //PB6 0x2: PWM0_1. + + PWM_SFRS->CTRL0R.PT0RC = 1U;//0x1: PT0R is cleared, PT0 stops counting + + PWM_SFRS->CTRL1R.CC1CNTS = 0; + PWM_SFRS->CTRL1R.CC2CNTS = 0; + PWM_SFRS->CTRL1R.CC3CNTS = 0; + PWM_SFRS->CTRL1R.PT0PRES = 1;//0x1: Divide by 2 48Mhz/2 = 24Mhz + PWM_SFRS->CTRL1R.PT0MODE = 0;//0x0: Edge_aligned_mode: + + PWM_SFRS->PT0PERIOD = 100U*48U; //100us*2 = 5Khz + PWM_SFRS->DTCR.CCXDTE = 0;//0x0: DISABLED: Dead-time generation is disabled. + PWM_SFRS->DTCR.PT1DT = 0; + PWM_SFRS->DTCR.PT0DT = 0; + + PWM_SFRS->CHREMAPR.PWM0RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM1RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM2RMP = 0;//0x0: Select CC0 + PWM_SFRS->CHREMAPR.PWM3RMP = 0;//0x0: Select CC0 + + PWM_SFRS->CMPSTATR.CC00PS = 0;//0x0: CC0_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC01PS = 0; + PWM_SFRS->CMPSTATR.CC10PS = 0;//0x0: CC1_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC11PS = 0; + PWM_SFRS->CMPSTATR.CC20PS = 0;//0x0: CC2_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC21PS = 0; + PWM_SFRS->CMPSTATR.CC30PS = 0;//0x0: CC3_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS + PWM_SFRS->CMPSTATR.CC31PS = 0; + + PWM_SFRS->PSL = 0X0;//0x0: Level_0: The passive level is 0 + + PWM_SFRS->MODCTRLR.MCEN = 0;//0x1: ENABLED: The modulation of the corresponding output signal by the multi-channel pattern according to bit field MCPTN is enabled + PWM_SFRS->MODCTRLR.CCXMODEN = 0XFF;//0x1: ENABLED: The modulation of the corresponding output signal by CC0~3 pattern is enabled + + PWM_SFRS->MCOUTR.MCUPR= 1;//0x1: By_software: Bit field MCPTN is updated by MCPTNS immediately + PWM_SFRS->MCOUTR.MCPTNS = 0XFF; + + PWM_SFRS->PULSE0R.PRISE0 = 0U; + PWM_SFRS->PULSE0R.PFALL0 = 2000U; + + PWM_SFRS->CTRL0R.PT0UPES = 1;//0x1: PT0UPE is set, enabling update + PWM_SFRS->CTRL0R.PT0RS = 1;//0x1: PT0R is set, PT0 start counting + while(1){ + PT0data = PWM_SFRS->PT0CV; + } +} + +void SPI(void) +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U; + + IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<20; //PA5 0x3: SCK. + IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<16; //PA4 0x3: MOSI. + IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<12; //PA3 0x3: MISO + + SPI_SFRS->SPICTRL.FIFOSOFTRESET = 1; + while(SPI_SFRS->SPICTRL.FIFOSOFTRESET == 1); + + SPI_SFRS->SPICTRL.SCKEXT = 2; + SPI_SFRS->SPICTRL.SPR = 3;//{10, 11}: System Clock / 4096 11.718KHZ + + SPI_SFRS->SPICTRL.LPBK = 1;//0x1: Loopback enable. Set to enable loopback + SPI_SFRS->SPICTRL.ICNT = 0;//0x0: Interrupt is set after every completed transfer + SPI_SFRS->SPICTRL.CPOL = 0;// + SPI_SFRS->SPICTRL.CPHA = 0;//CPHA + SPI_SFRS->SPICTRL.ENA_REQ = 1; + + while(SPI_SFRS->SPISTATUS.TXFIFOEMPTY == 1) + { + SPI_SFRS->TXDATA = 0x55; + } + if(SPI_SFRS->SPISTATUS.RXFIFOEMPTY == 0){ + Rdata_SPI = SPI_SFRS->RXDATA; + } +} + +void UART0(void)//¿ªloop¹¦ÄÜʱÔÚTX¶ËÎÞÊý¾ÝÐźţ¬¹Ø±ÕʱÓÐ +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U; + + IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02U; //PB0 0x2: TXD. + IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x03U<<12; //PB3 0x3: RXD. + + UART0_SFRS->MSGCTRL.ENABLE = 0U;//0:Disable UART0 + UART0_SFRS->MSGCTRL.LOOPENA = 0U;//Loopback enable. Set to enable loopback + UART0_SFRS->MSGCTRL.BREAKENA = 0U; + UART0_SFRS->MSGCTRL.STICKENA = 0U; + UART0_SFRS->MSGCTRL.PARODD = 0U;//0x0: ODD Parity + UART0_SFRS->MSGCTRL.PARENA = 1U;//Parity enable. + UART0_SFRS->MSGCTRL.STOP = 0U;//0x0: One stop bit + UART0_SFRS->MSGCTRL.SIZE = 3U;//Transmission word size.0x3: 8-bit + UART0_SFRS->MSGCTRL.TXXFERCNTCLR = 1U;// + UART0_SFRS->MSGCTRL.RXXFERCNTCLR = 1U; + UART0_SFRS->MSGCTRL.UFIFOSOFTRESET = 1U; + + //Baud_rate = Fclk/OSR/(BAUDDIV+1+FDIV/8) + //48000000/16/(311+1+4/8)= 9600 + UART0_SFRS->UARTBAUD.URETARD = 1; + UART0_SFRS->UARTBAUD.UADVANCE = 1; + UART0_SFRS->UARTBAUD.OSR = 16;//Over-sampling ratio. Valid OSR Range: 6 to 16. + UART0_SFRS->UARTBAUD.BAUDDIV = 311;//Baud rate divider.16bits + UART0_SFRS->UARTBAUD.FDIV = 4;//Fractional divider.3bits + + UART0_SFRS->UARTFIFO.TXMULTIPLEXFERDONECNT = 4;//Transmit Data Count Interrupt. Valid Range: 1 to 16 + + UART0_SFRS->MSGCTRL.ENABLE = 1U; + while(UART0_SFRS->MSGCTRL.ENABLE_STS == 0); + + Tdata_UART0 = 0X55; + UART0_SFRS->DATA.BYTE = Tdata_UART0; + while(UART0_SFRS->UARTINT.STATUS.TXDONE == 0U){} + UART0_SFRS->UARTINT.CLEAR.TXDONE = 1U; + +// Tdata_UART0 = 0X56; +// UART0_SFRS->DATA.BYTE = Tdata_UART0; + + if(UART0_SFRS->UARTINT.STATUS.RXDONE == 1) + { + Rdata_UART0 = UART0_SFRS->DATA.BYTE; + } +} + + +void CT3_COUNTER(void) +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U; + + IOCTRLA_SFRS->PORT_GROUP_MUX[2] |= (uint32_t)0x07U << 12; //PC3 0x7: PAUX[1] + IOCTRLA_SFRS->PORT_GROUP_MUX[2] |= (uint32_t)0x04U << 16; //PC4 0x4: CT3EUDB + + CTT_SFRS->CTTINSR.SELCT3EUD = 1U;//0x1: Signal CT3EUDB is selected + + CTT_SFRS->CT3CTRLR.CT3R = 0;//0x0: Timer CT3 stops + CTT_SFRS->CT3CTRLR.CT3EUDE = 0U;//0x0: Count direction is controlled by bit CT3UD; input CT3EUD is ignored + CTT_SFRS->CT3CTRLR.CT3UD = 0U;//0x0: Up: Timer CT3 counts up + CTT_SFRS->CT3CTRLR.CT3M = 7U;//0x7: Incremental Interface Mode (Edge Detection Mode) + CTT_SFRS->CT3CTRLR.CT3I = 2U;//Any transition (rising or falling edge) on CT3EUD + + PWMAUX_Init(GROUP_GPIOC,GPIO_PORT_3,PWMAUX_CH1,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,1000*48);//1ms + PWMAUX_SetMatchValue(PWMAUX_CH1, 0, 1000*48/2);//PWMAUX1:PC3 + + CTT_SFRS->CT3CTRLR.CT3R = 1;//0x0: Timer CT3 stops + while(1) + { + CT3CV_data = CTT_SFRS->CT3CV; + } +} + + +void validation_main(void) +{ + SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U; + //SYSCTRLA_REG_TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU; + SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU; + Clock_SystemMainClockInit(SYS_MAIN_CLOCK_DIV); + + while(1); +} + + +#endif diff --git a/app_Indie/usr/common/validation.h b/app_Indie/usr/common/validation.h new file mode 100644 index 0000000..f0efc66 --- /dev/null +++ b/app_Indie/usr/common/validation.h @@ -0,0 +1,8 @@ +#ifndef VALIDATION_H_ +#define VALIDATION_H_ + +void validation_main(void); + + + +#endif \ No newline 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Y`@t;e0p3CV8}OTkj`8rzC5Z9<3B0k5zyJUM literal 0 HcmV?d00001 diff --git a/app_Indie/usr/library/linStackTask.h b/app_Indie/usr/library/linStackTask.h new file mode 100644 index 0000000..d850aea --- /dev/null +++ b/app_Indie/usr/library/linStackTask.h @@ -0,0 +1,526 @@ +/** + * @copyright 2015 Indie Semiconductor. + * + * This file is proprietary to Indie Semiconductor. + * All rights reserved. Reproduction or distribution, in whole + * or in part, is forbidden except by express written permission + * of Indie Semiconductor. + * + * @file lin_stack.h + */ + +#ifndef LIN_STACK_H__ +#define LIN_STACK_H__ + +#include +#include +#include + +/** + * @brief The definitions and enumerations used in the API function in LIN stack. + */ +typedef uint8_t l_bool; +typedef uint8_t l_ioctl_op; +typedef uint8_t l_irqmask; +typedef uint8_t l_u8; +typedef uint16_t l_u16; +typedef uint32_t l_u32; + +typedef uint8_t l_signal_handle; +typedef uint8_t l_flag_handle; +typedef uint8_t l_ifc_handle; +typedef uint8_t l_schedule_handle; + +typedef enum{ + LIN_PCI_SF = 0U, + LIN_PCI_FF, + LIN_PCI_CF +}PCI_Types_t; + +typedef enum{ + PDU_TYPE_SINGLE_PDU = 0U, + PDU_TYPE_MULTI_PDU, +}PDU_Types_t; + +typedef enum{ + TX_IDLE = 0U, + TX_SENDING, + TX_FINISHED, + TX_FAILED +}TxStatus_t; + +typedef enum{ + LIN_PROTOCOL_LIN2_2A = 0U, + LIN_PROTOCOL_SAE_J2602, +}LinProtocolType_t; + +typedef enum{ + J2602_ERROR_NO_DETECTED_FAULT = 0, + J2602_ERROR_RESET, + J2602_ERROR_RESERVED0, + J2602_ERROR_RESERVED1, + J2602_ERROR_DATA_ERROR, + J2602_ERROR_CHECKSUM_ERROR, + J2602_ERROR_BYTE_FIELD_FRAMING_ERROR, + J2602_ERROR_ID_PARITY_ERROR, +}J2602ErrCode_t; + + +#define SF_MAX_DATA_LENGTH (5U) + +#define LIN_NAD_FUNCTION (0x7EU) +#define LIN_NAD_WILDCARD (0x7FU) +#define LIN_SUPPLIER_ID_WILDCARD (0x7FFFU) +#define LIN_FUNCTION_ID_WILDCARD (0xFFFFU) +#define LIN_SERIALNO_WILDCARD (0x01234567U) + +/** + * @brief The enumerations of frame identifiers. + */ +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_START (0x38U) +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_END (0x3BU) + + +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_38 (0x38U) +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_39 (0x39U) +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_3A (0x3AU) +#define LIN_FRAME_ID_J2602_DNN_BROADCAST_3B (0x3BU) + + +#define LIN_FRAME_ID_DIAG_MASTER_REQ (0x3CU) +#define LIN_FRAME_ID_DIAG_SLAVER_RSP (0x3DU) +#define LIN_FRAME_ID_DIAG_MASTER_REQ_3E (0x3EU) + +#define LIN_FRAME_ID_FUNCTIONAL (0x7EU) +#define LIN_FRAME_ID_UNASSIGN (0x00U) +#define LIN_FRAME_ID_DONOTCARE (0xFFU) + +/** + * @brief The enumerations of service IDs. + */ +#define LIN_SID_ASSIGN_NAD (0xB0U) +#define LIN_SID_ASSIGN_FRAME_ID (0xB1U) +#define LIN_SID_READ_BY_ID (0xB2U) +#define LIN_SID_CONDITIONAL_CHANGE_NAD (0xB3U) +#define LIN_SID_DATA_DUMP (0xB4U) +#define LIN_SID_RESERVED (0xB5U) +#define LIN_SID_SAVE_CONFIGURATION (0xB6U) +#define LIN_SID_ASSIGN_FRAME_ID_RANGE (0xB7U) + +#define LIN_SID_SNPD LIN_SID_RESERVED +#define LIN_SID_J2602_HARDWARE_RST LIN_SID_RESERVED + +typedef union{ + struct{ + uint8_t appInfo0 :1; + uint8_t appInfo1 :1; + uint8_t appInfo2 :1; + uint8_t appInfo3 :1; + uint8_t appInfo4 :1; + uint8_t err :3; + }; + uint8_t payload; +}J2602StatusByte_t; + +typedef union{ + struct{ + uint8_t nad; + union{ + uint8_t pci; + struct{ + uint8_t pci_extInfo :4; + uint8_t pci_type :4; + }; + }; + union{ + uint8_t sid; + uint8_t length; + uint8_t rsid; + struct{ + uint8_t length_ff; + uint8_t sid_rsid_ff; + }; + uint8_t payload[6]; + }; + }; + uint8_t data[8]; + uint64_t data64; +}NodeStruct_t; + +typedef struct{ + PDU_Types_t type; /* pdu type single or multi pdu */ + uint8_t sid; /* sid */ + uint16_t packLength; /* the complete valid data buffer length except the length of sid */ +// uint16_t packCurrIndex; /* the current data position index in the complete data buffer */ + uint8_t *payload; /* data in received buffer */ +}DiagSubscribeInfo_t; + + +typedef struct{ + PDU_Types_t type; /* pdu type single or multi pdu */ + uint8_t sid; /* sid */ + uint16_t packLength; /* the complete valid data buffer length except the length of SID */ + uint8_t *payload; /* data buffer to be sent except SID*/ +}DiagPublishInfo_t; + + +typedef struct{ + uint16_t buffLength; /* the complete valid data buffer length except the length of SID */ + uint8_t *buff; /* data buffer to be sent except SID*/ +}DiagMultiPduInfo_t; + + +typedef enum{ + SLEEP_REQ_TYPE_NONE = 0U, /* none of sleep request */ + SLEEP_REQ_TYPE_MASTER_REQ, /* sleep request with filled with 0xFF in buff[1-7] */ + SLEEP_REQ_TYPE_MASTER_REQ_INFORMAL, /* sleep request without filled with 0xFF in buff[1-7] */ + SLEEP_REQ_TYPE_BUS_IDLE_TIMEROUT, +}SleepRequestType_t; + +typedef enum{ + BUS_WAKEUP_REQ_RESULT_MASTER_ACTIVE = 0, /* wakeup bus successfully, master send frame ID after wake up */ + BUS_WAKEUP_REQ_RESULT_REQ_TIMEOUT, /* wakeup bus failed after 3 tries */ +}BusWakeUpRequestResult_t; + +typedef void (*ls_UnconditionalReqCallback_t)(LIN_Device_Frame_t const *frame); +typedef void (*ls_UnconditionalRspCallback_t)(LIN_Device_Frame_t *const frame); +typedef void (*ls_PublisherTxFinishedCallback_t)(uint8_t fid, uint8_t j2602CfgRsp); +typedef void (*ls_DiagReqCallback_t)(const DiagSubscribeInfo_t * const frameInfo); +typedef void (*ls_DiagFunctionalNADCallback_t)(const NodeStruct_t * const frame); +typedef void (*ls_DiagSleepReqCallback_t)(SleepRequestType_t type); +typedef void (*ls_BusWakeUpRequestCallback_t)(BusWakeUpRequestResult_t result); + +typedef void (*ls_DiagReqLogCallback_t)(const LIN_Device_Frame_t * const frame); +typedef void (*ls_FrameIdLogCallback_t)(uint8_t frameId); + +typedef void (*ls_SAEJ2602CfgReqCallback_t)(uint8_t fid,uint8_t const *payload, uint8_t length); +typedef void (*ls_SAEJ2602DNNBroadcastReqCallback_t)(uint8_t fid,uint8_t const *payload, uint8_t length); + +typedef struct{ + ls_UnconditionalReqCallback_t unconditionalSubscribedCallback; /* received data from master */ + ls_UnconditionalRspCallback_t unconditionalPublishedCallback; /* send data to master */ + ls_PublisherTxFinishedCallback_t publisherTxFinishedCallback; /* send data to master finished */ + ls_DiagReqCallback_t diagnosticSubscribedCallback; /* Diagnostic and MultiPDU received data from master */ + ls_DiagFunctionalNADCallback_t diagFunctionalNADCallback; /* special functional NAD (0x7E) handler*/ + ls_DiagSleepReqCallback_t diagnosticSleepRequestCallback; /* Diagnostic sleep request from master */ + ls_BusWakeUpRequestCallback_t busWakeUpRequestCallback; /* got the bus state after slave sending wake up signal.*/ + ls_SAEJ2602CfgReqCallback_t SAEJ2602CfgReqCallback; /* refers to SAEJ2602-1 5.7.2.3 Configuration Messages */ + ls_SAEJ2602DNNBroadcastReqCallback_t SAEJ2602DNNBroadcastReqCallback; /* DNN Based Broadcast Messages */ +}ls_LinsFramesCallback_t; + +typedef struct{ + l_u8 device; /* 1: means realplum(IND83205) , 2: rugby(IND83204) 3: realplumPro(IND82209),4: rugbyPro(IND83211),5: realplumLite(IND83212)*/ + l_u8 protocol; /* 0:with LIN stack V2.2A ,1: with LIN stack SAE_J2602, 2: with LIN stack V2.2A_SAE_J2602 */ + l_u16 version; /* 0x0101 means V1.01 */ +}lin_stack_version_t; + +/** +* @brief A structure to represent LIN status information. +*/ +typedef union { + struct{ + l_u8 error_in_resp :1; + l_u8 success_in_transfer :1; + l_u8 overrun :1; + l_u8 goto_sleep :1; + l_u8 bus_activity :1; + l_u8 event_trig_frame_collision :1; + l_u8 save_config :1; + l_u8 parity_error :1; /* FID parity error bit */ + l_u8 pid; + }; + l_u16 payload; +}lin_status_t; + + +typedef enum{ + LD_SET_OK = 0, + LD_LENGTH_NOT_CORRECT, + LD_DATA_ERROR +}ld_set_status_t; + +typedef enum{ + LD_READ_OK = 0, + LD_LENGTH_TOO_SHORT, +}ld_read_status_t; + +/* + * Lin stack main task which was called by task manager, please don't use for other purpose!!!: + * @param [in] none + * @return none + */ +void LinStack_TaskHandler(void); + +/* + * Get current Lin stack version: + * @param [in] none + * @return lin_stack_version: majorVer: main version; subVer: branch version + */ +lin_stack_version_t ls_get_lin_version(void); + +/* + * Lin stack initialization: + * @param [in] none + * @return 0 + */ +l_bool l_sys_init(void); + +/* + * Set Lin transport layer timeout parameters: + * @param [in] n_as: N_As, refer to LIN spec 2.2A + * @param [in] n_cr: N_Cr, refer to LIN spec 2.2A + * @return 0 + */ +l_u8 ls_set_tp_timeout(uint16_t n_as, uint16_t n_cr); + +/* + * Set Lin lin tx bit monitor: + * @param [in] enable: TRUE: enable bit monitor; FALSE: disable bit monitor + * @return 0 + */ +l_u8 ls_set_tx_bit_monitor(l_u8 enable); + +/* + * Disable LIN auto sleep when LIN timeout: + * @param [in] TRUE: disable auto sleep; FALSE: enable auto sleep + * @return 0 + */ +l_u8 ls_disable_lin_auto_sleep(l_u8 disable); + +/* + * Set Lin phy 1st rx glitch signal filter timing : + * @param [in] risingTime: level 0 -> level1 delay time; range 0-127 unit: 62.5us + * @param [in] fallingTime:level 0 -> level 1 delay time, range 0-127 unit: 62.5us + * @return 0, successfully , others: failed + */ +l_u8 ls_set_lins_rx_glitch_filter_1st(l_u8 risingTime,l_u8 fallingTime); + +/* + * Set Lin phy 2nd rx glitch signal filter timing : + * @param [in] risingTime: level 0 -> level1 delay time; range 0-127 unit: 62.5us + * @param [in] fallingTime:level 0 -> level 1 delay time, range 0-127 unit: 62.5us + * @return 0, successfully , others: failed + */ +l_u8 ls_set_lins_rx_glitch_filter_2nd(l_u8 risingTime,l_u8 fallingTime); + +/* + * Set Lin phy 3rd rx glitch signal filter timing : + * @param [in] risingTime: level 0 -> level1 delay time; range 0-127 unit: 62.5us + * @param [in] fallingTime:level 0 -> level 1 delay time, range 0-127 unit: 62.5us + * @return 0, successfully , others: failed + */ +l_u8 ls_set_lins_rx_glitch_filter_3rd(l_u8 risingTime,l_u8 fallingTime); + + +/* + * Reqister supported unconditional frame table + * @param [in] protocol: LIN protocol type 0: LIN_PROTOCOL_LIN2_2A, 1: LIN_PROTOCOL_SAE_J2602. + * @param [in] frameTable: frame table location + * @param [in] tableSize: frame table size + * @param [in] diagPDUSubscriberBuffLength: diagnostic multi pdu max supported data length, this value should be within 7-4095 + * @param [in] pFunCallback: callback fucntions for diagnostic frame and unconditional frames. + * @return none + */ +void ls_register_services(LinProtocolType_t protocol,LIN_Device_Frame_t *frameTable, l_u8 tableSize, DiagMultiPduInfo_t multiPduInfo,const ls_LinsFramesCallback_t *pFunCallback); + +/* + * Diagnostic frame response function which is used to send back data to LIN master. + * @param [in] rsp: refer to description of structure DiagPublishInfo_t definition. + * @return none + */ +void ls_handle_diagnostic_response(DiagPublishInfo_t *rsp); + +/* + * SAEJ2602 CFG 0x3C or 0x3E frame response function which is used to send back data to LIN master. + * @param [in] rsp: refer to SAEJ2602-1 5.7.2.4 Response Message to Options 2 and 3 in 5.7.2.3. + * @param [in] statusByte:J2602-1 Status Byte(defined in 5.8.6) + * @param [in] payload: databuff 0-6 the paylad length should be 7 by default. + * @return none + */ +void ls_handle_SAEJ2602Cfg_response(l_u8 statusByte, l_u8 *payload); + +/* + *!!!!!!!!!!!!!!!!!!!Note that obsolete not recommended for future use!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * frame response send status. + * @return TxStatus_t. + */ +TxStatus_t ls_tx_status(void); + +/* + * Set device initial NAD to LIN stack for assigning NAD command. + * @param [in] nad: initial NAD of device. + * @return none + */ +void ls_set_initialNad(l_u8 nad); +/* + * Set device NAD to LIN stack. + * @param [in] nad: current NAD of device. + * @return none + */ +void ls_set_nad(l_u8 nad); + +/* + * Red NAD of LIN stack. + * @param [in] none. + * @return current NAD of LIN stack. + */ +l_u8 ls_read_nad(void); + +/* + * Red NAD of current diagnostic frame sent from LIN master, there are only probably 2 values: current NAD or 0x7FU(NAD wildcard). + * @param [in] none. + * @return NAD of current diagnostic frame. + */ +l_u8 ls_read_nad_from_master(void); + +/* + * Save current LIN Stack parameters such as NAD, PIDs etc. refer to pdsTask for more information. + * @param [in] none. + * @return 0. + */ +l_u8 ls_save_configuration(void); + +/* + * clear save_configuration flag. + * @param [in] none. + * @return 0. + */ +l_u8 ls_clr_save_configuration_flag(void); + +/* + * !!!!!!!!!!!!!!!!!!!Note that obsolete not recommended for future use!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * replace with function ls_ifc_read_status() and ls_ifc_read_status() + * Read current error flag and system information, refer to struture lin_status_t for more information. + * @param [in] none. + * @return: + l_u8 error_in_resp :1; + l_u8 success_in_transfer :1; + l_u8 overrun :1; + l_u8 goto_sleep :1; + l_u8 bus_activity :1; + l_u8 event_trig_frame_collision :1; + l_u8 save_config :1; + l_u8 parity_error :1; + l_u8 pid; + */ +l_u16 ls_read_sys_status(void); + +/* + * !!!!!!!!!!!!!!!!!!!Note that obsolete not recommended for future use!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * replace with function ls_ifc_read_status() and ls_ifc_read_status() + * Read current error flag and system information, simulate with ls_read_sys_status + * @return: + l_u8 error_in_resp :1; + l_u8 success_in_transfer :1; + l_u8 overrun :1; + l_u8 goto_sleep :1; + l_u8 bus_activity :1; + l_u8 event_trig_frame_collision :1; + l_u8 save_config :1; + l_u8 parity_error :1; + l_u8 pid; +*/ +lin_status_t ls_read_sys_status_ext(void); + +/* + * Read current error flag and system information, simulate with ls_read_sys_status not don't clear the status + * @return: + l_u8 error_in_resp :1; + l_u8 success_in_transfer :1; + l_u8 overrun :1; + l_u8 goto_sleep :1; + l_u8 bus_activity :1; + l_u8 event_trig_frame_collision :1; + l_u8 save_config :1; + l_u8 parity_error :1; + l_u8 pid; +*/ +lin_status_t ls_ifc_read_status(void); + +/* + * reset lin error status. + * @param [in] errCode. + * @return: 0U; + */ +l_u8 ls_ifc_clear_error_status(void); + +/* + * !!!!!!!!!!!!!!!!!!!Note that obsolete not recommended for future use!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * replace with function : ls_read_error_code_log() and ls_clr_error_code_log() + * Read current lin stack communication error reasons, this is only for internal use. + * @param [in] none. + * @return: ((1U << ERROR_BITERR_POS) | (1U << ERROR_CHK_POS) | (1U << ERROR_BITMON_POS) | (1U << ERROR_FRAMEERR_POS)) refer to LINS->ERROR register + */ +l_u8 ls_read_error_code(void); + +/* + * Read current lin stack communication error reasons, this is only for internal use and don't clear the error log + * @param [in] none. + * @return: ((1U << ERROR_BITERR_POS) | (1U << ERROR_CHK_POS) | (1 << ERROR_PARITY_POS) | (1U << ERROR_BITMON_POS) | (1U << ERROR_FRAMEERR_POS))refer to LINS->ERROR register + */ +l_u8 ls_read_error_code_log(void); + +/* + * clear the erroe code log. + * @param [in] none. + * @return: 0; + */ +l_u8 ls_clr_error_code_log(void); + +/* + * Read SAEJ2602 communication error state. + * @param [in] none. + * @return: J2602ErrCode_t + */ +J2602ErrCode_t ls_read_J2602_error_code(void); + +/* + * reset SAEJ2602 communication error state when response successfully. + * @param [in] errCode. + * @return: none + */ +void ls_reset_J2602_error_code(J2602ErrCode_t errCode); + +/* + * Notice lin stack it's a hardware reset operation. + * @param [in] 0: hardware reset is false, 1: hardware reset is true. + * @return: none + */ +void ls_set_J2602_hardware_reset(uint8_t hardwareReset); + + +/* + * read go_to_sleep flag + * @param [in] none. + * @return: state: 1: got go_to_sleep command, 0: not got go_to_sleep command + */ +l_u8 ls_read_go_to_sleep_flag(void); +/* + * Clear go_to_sleep flag + * @param [in] none. + * @return: 0U + */ +l_u8 ls_clr_go_to_sleep_flag(void); + +/* + * Clear overrun flag + * @param [in] none. + * @return: 0U + */ +l_u8 ls_clr_overrun_flag(void); + +/* + * Read current LIN BUS Status. + * @param [in] none. + * @return: 1: active, 0: IDLE;, refer to "bus_activity" in function:ls_ifc_read_status(); + */ +l_u32 ls_linbus_activity(void); + +/* + * Slave trigger to send wake up signal on LIN bus for 3 times if there is no LIN frame on the LIN bus after wake up signal. + * @param [in] none. + * @return: none; + */ +void ls_send_wake_up_bus_signal(void); + +#endif /* __LIN_STACK_H__ */ \ No newline at end of file diff --git a/app_Indie/usr/library/softTimerTask.h b/app_Indie/usr/library/softTimerTask.h new file mode 100644 index 0000000..9e174e5 --- /dev/null +++ b/app_Indie/usr/library/softTimerTask.h @@ -0,0 +1,78 @@ +#ifndef GLOBAL_TIMER_H +#define GLOBAL_TIMER_H + +#include +#include +#include + +#define SOFT_TIMER_INTERVAL_POS 3U +#define SOFT_TIMER_INTERVAL (1UL << SOFT_TIMER_INTERVAL_POS) /* ms, must be 2^SOFT_TIMER_INTERVAL_POS*/ + +/*- Types ------------------------------------------------------------------*/ +typedef enum{ + TIMER_ONE_SHOT_MODE, /*this a one time timer, when timming expired, timer would be killed automatically*/ + TIMER_PERIODIC_MODE, /*this a period timer, timer would keep running unitl execute SoftTimer_Stop(), or change the mode by manual.*/ +}SoftTimerMode_t; + + +/* Note that: the SoftTimer_t entity MUST be global/static variable!! */ +typedef struct SoftTimer { + struct SoftTimer *next; /* Internal data don't use!! */ + uint32_t timeout; /* Internal data don't use!! */ + + uint32_t interval; /* Timer parameters unit : ms*/ + SoftTimerMode_t mode; + uint32_t param; /* variables for user use*/ + void (*handler)(struct SoftTimer *timer); +}SoftTimer_t; + +/* + * Start running target timer + * @param [in] timer: target defined global/ static timer + * @return none + */ +void SoftTimer_Start(SoftTimer_t *timer); +/* + * Stop target timer + * @param [in] timer: target defined global/ static timer + * @return none + */ +void SoftTimer_Stop(SoftTimer_t *timer); +/* + * query whether target timer has been started + * @param [in] timer: target defined global/ static timer + * @return 0: not start, other: statred. + */ +uint8_t SoftTimer_Started(SoftTimer_t *timer); + + +/* Soft time handle task only for internal use*/ +void SoftTimer_TaskHandler(void); +/* Soft time base callback function only for internal use*/ +void SoftTimer_ExpireCallback(void); + + + + + + + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/app_Indie/usr/main.c b/app_Indie/usr/main.c new file mode 100644 index 0000000..4d1e99d --- /dev/null +++ b/app_Indie/usr/main.c @@ -0,0 +1,72 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wdt_device.h" + +uint8_t trim1V5 = 0; + + +void main(void) +{ +#if ENABLE_FUNCTION_VALIDATION == 1 + // validation_main(); +#endif + + + + /* !!!!!!!MUST BE called firstly here for initializing system parameters !!!!*/ + PDS_Init(); + /* System init for hardwre init */ + SYS_Init(); + /* system main infinite loop */ +// WDTA_Enable(WDTA_INTERVAL_2304MS); + WDTA_Disable(); +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.ANASELREG = 0x4000;//0x4000: PB7 analog connection is switched on +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.GPIOCONREG = 0X400;//0x400: Select CSA_Filter_OUT to PB7 +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.GPIOCONSEL = 1;// 0x1: GPIO_CON_REG controls analog test MUX. +// delay(100); +// SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0x05; +// while(SYSCTRLA_SFRS->DEBUG_ACCESS_ENABLED == 0); +// +// SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0E; +// while(SYSCTRLA_SFRS->TRIM_ACCESS_ENABLED == 0); +// +// TRIMHV_SFRS->TRIM_LF_RC = 0XB0; +// +// +// SYSCTRLA_SFRS->PMU_ACCESS_KEY.PMU_ACCESS_KEY = 0x0A; +// while(SYSCTRLA_SFRS->PMU_ACCESS_ENABLED == 0); +// +// TRIMHV_SFRS->PMUTRIM.VDD1V5_LDO_TRIM = 3U; +// trim1V5 = TRIMHV_SFRS->PMUTRIM.VDD1V5_LDO_TRIM; +// +// if(trim1V5 == 3){ +// IOCTRLA_SFRS->CTRL_MODE[GROUP_GPIOB].PU &= ~(1U << (uint8_t)GPIO_PORT_7); +// IOCTRLA_SFRS->CTRL_MODE[GROUP_GPIOB].PD &= ~(1U << (uint8_t)GPIO_PORT_7); +// //mode config 1 +// IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] &= ~(0x0FUL << (4U*(uint8_t)GPIO_PORT_7)); +// IOCTRLA_SFRS->PORT_GROUP_MUX[GROUP_GPIOB] |= (0x01UL << (4U*(uint8_t)GPIO_PORT_7)); +// //select output signal +// IOCTRLA_SFRS->TESTMUX.TESTMUX3 = 8U; +// +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.ANASELREG = 0x800;//0x800: PB4 analog connection is switched on +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.GPIOCONREG = 2;//0x2: Select VDD1V5 to PB4 +// IOCTRLA_SFRS->ANALOGTESTMUXOVERRIDE.GPIOCONSEL = 1;// 0x1: GPIO_CON_REG controls analog test MUX. +// } +// WDTA_Enable(WDTA_INTERVAL_2304MS); +// VDD3V3EXT_ON; + + for(;;){ + TM_RunTasks(); + } +} + + + +