/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _SIM_REG_H_
#define _SIM_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the SIM (System Integration Module) Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* CHIP Bit Fields */
#define SIM_CHIP_SRAM_INIT_ST_MASK       (0x20u)
#define SIM_CHIP_SRAM_INIT_ST_SHIFT      (5u)
#define SIM_CHIP_SRAM_INIT_ST_WIDTH      (1u)
#define SIM_CHIP_SRAM_INIT_MASK          (0x08u)
#define SIM_CHIP_SRAM_INIT_SHIFT         (3u)
#define SIM_CHIP_SRAM_INIT_WIDTH         (1u)
#define SIM_CHIP_SRAM_RETEN_MASK         (0x02u)
#define SIM_CHIP_SRAM_RETEN_SHIFT        (1u)
#define SIM_CHIP_SRAM_RETEN_WIDTH        (1u)

/* PWM_CTRL0 Bit Fields */
#define SIM_PWM_CTRL0_PWM_FUNC3_MASK     (0xF000000u)
#define SIM_PWM_CTRL0_PWM_FUNC3_SHIFT    (24u)
#define SIM_PWM_CTRL0_PWM_FUNC3_WIDTH    (4u)
#define SIM_PWM_CTRL0_PWM_FUNC2_MASK     (0xF0000u)
#define SIM_PWM_CTRL0_PWM_FUNC2_SHIFT    (16u)
#define SIM_PWM_CTRL0_PWM_FUNC2_WIDTH    (4u)
#define SIM_PWM_CTRL0_PWM_FUNC1_MASK     (0xF00u)
#define SIM_PWM_CTRL0_PWM_FUNC1_SHIFT    (8u)
#define SIM_PWM_CTRL0_PWM_FUNC1_WIDTH    (4u)
#define SIM_PWM_CTRL0_PWM_FUNC0_MASK     (0x0Fu)
#define SIM_PWM_CTRL0_PWM_FUNC0_SHIFT    (0u)
#define SIM_PWM_CTRL0_PWM_FUNC0_WIDTH    (4u)

/* PWM_CTRL1 Bit Fields */
#define SIM_PWM_CTRL1_PWM_FUNC5_MASK     (0xF00u)
#define SIM_PWM_CTRL1_PWM_FUNC5_SHIFT    (8u)
#define SIM_PWM_CTRL1_PWM_FUNC5_WIDTH    (4u)
#define SIM_PWM_CTRL1_PWM_FUNC4_MASK     (0x0Fu)
#define SIM_PWM_CTRL1_PWM_FUNC4_SHIFT    (0u)
#define SIM_PWM_CTRL1_PWM_FUNC4_WIDTH    (4u)

/* ADC Bit Fields */
#define SIM_ADC_TRG_SRC_MASK             (0x20u)
#define SIM_ADC_TRG_SRC_SHIFT            (5u)
#define SIM_ADC_TRG_SRC_WIDTH            (1u)
#define SIM_ADC_PRETRG_SW_SRC_MASK       (0x1Cu)
#define SIM_ADC_PRETRG_SW_SRC_SHIFT      (2u)
#define SIM_ADC_PRETRG_SW_SRC_WIDTH      (3u)
#define SIM_ADC_PRETRG_SRC_MASK          (0x03u)
#define SIM_ADC_PRETRG_SRC_SHIFT         (0u)
#define SIM_ADC_PRETRG_SRC_WIDTH         (2u)

/* I2S Bit Fields */
#define SIM_I2S_SLV_DMA_IRQ_MASK         (0x04u)
#define SIM_I2S_SLV_DMA_IRQ_SHIFT        (2u)
#define SIM_I2S_SLV_DMA_IRQ_WIDTH        (1u)
#define SIM_I2S_MST_DMA_IRQ_MASK         (0x02u)
#define SIM_I2S_MST_DMA_IRQ_SHIFT        (1u)
#define SIM_I2S_MST_DMA_IRQ_WIDTH        (1u)
#define SIM_I2S_MODE_MASK                (0x01u)
#define SIM_I2S_MODE_SHIFT               (0u)
#define SIM_I2S_MODE_WIDTH               (1u)

/* MFT_CTRL0 Bit Fields */
#define SIM_MFT_CTRL0_MFT1_FLT_SEL_MASK  (0x700000u)
#define SIM_MFT_CTRL0_MFT1_FLT_SEL_SHIFT (20u)
#define SIM_MFT_CTRL0_MFT1_FLT_SEL_WIDTH (3u)
#define SIM_MFT_CTRL0_MFT0_FLT_SEL_MASK  (0x70000u)
#define SIM_MFT_CTRL0_MFT0_FLT_SEL_SHIFT (16u)
#define SIM_MFT_CTRL0_MFT0_FLT_SEL_WIDTH (3u)
#define SIM_MFT_CTRL0_GLDOK_MASK         (0x01u)
#define SIM_MFT_CTRL0_GLDOK_SHIFT        (0u)
#define SIM_MFT_CTRL0_GLDOK_WIDTH        (1u)

/* MFT_CTRL1 Bit Fields */
#define SIM_MFT_CTRL1_MFT1SYNCBIT_MASK   (0x2000000u)
#define SIM_MFT_CTRL1_MFT1SYNCBIT_SHIFT  (25u)
#define SIM_MFT_CTRL1_MFT1SYNCBIT_WIDTH  (1u)
#define SIM_MFT_CTRL1_MFT0SYNCBIT_MASK   (0x1000000u)
#define SIM_MFT_CTRL1_MFT0SYNCBIT_SHIFT  (24u)
#define SIM_MFT_CTRL1_MFT0SYNCBIT_WIDTH  (1u)
#define SIM_MFT_CTRL1_MFT1CH0SEL_MASK    (0x80000u)
#define SIM_MFT_CTRL1_MFT1CH0SEL_SHIFT   (19u)
#define SIM_MFT_CTRL1_MFT1CH0SEL_WIDTH   (1u)
#define SIM_MFT_CTRL1_MFT0_OUTSEL_MASK   (0xFF00u)
#define SIM_MFT_CTRL1_MFT0_OUTSEL_SHIFT  (8u)
#define SIM_MFT_CTRL1_MFT0_OUTSEL_WIDTH  (8u)

/* FLASH Bit Fields */
#define SIM_FLASH_EEERST_MASK             (0x800u)
#define SIM_FLASH_EEERST_SHIFT            (11u)
#define SIM_FLASH_EEERST_WIDTH            (1u)
#define SIM_FLASH_EEEVLD_MASK             (0x400u)
#define SIM_FLASH_EEEVLD_SHIFT            (10u)
#define SIM_FLASH_EEEVLD_WIDTH            (1u)
#define SIM_FLASH_LOAD_DONE_MASK         (0x200u)
#define SIM_FLASH_LOAD_DONE_SHIFT        (9u)
#define SIM_FLASH_LOAD_DONE_WIDTH        (1u)
#define SIM_FLASH_VIRGIN_FLAG_MASK       (0x100u)
#define SIM_FLASH_VIRGIN_FLAG_SHIFT      (8u)
#define SIM_FLASH_VIRGIN_FLAG_WIDTH      (1u)
#define SIM_FLASH_DFLS_FLUSH_EN_MASK     (0x08u)
#define SIM_FLASH_DFLS_FLUSH_EN_SHIFT    (3u)
#define SIM_FLASH_DFLS_FLUSH_EN_WIDTH    (1u)
#define SIM_FLASH_PFLS_FLUSH_EN_MASK     (0x04u)
#define SIM_FLASH_PFLS_FLUSH_EN_SHIFT    (2u)
#define SIM_FLASH_PFLS_FLUSH_EN_WIDTH    (1u)
#define SIM_FLASH_DFLS_PFB_EN_MASK       (0x02u)
#define SIM_FLASH_DFLS_PFB_EN_SHIFT      (1u)
#define SIM_FLASH_DFLS_PFB_EN_WIDTH      (1u)
#define SIM_FLASH_PFLS_PFB_EN_MASK       (0x01u)
#define SIM_FLASH_PFLS_PFB_EN_SHIFT      (0u)
#define SIM_FLASH_PFLS_PFB_EN_WIDTH      (1u)

/* UDIDH Bit Fields */
#define SIM_UDIDH_H_MASK                 (0xFFFFFFFFu)
#define SIM_UDIDH_H_SHIFT                (0u)
#define SIM_UDIDH_H_WIDTH                (32u)

/* UDIDMH Bit Fields */
#define SIM_UDIDMH_MH_MASK               (0xFFFFFFFFu)
#define SIM_UDIDMH_MH_SHIFT              (0u)
#define SIM_UDIDMH_MH_WIDTH              (32u)

/* UDIDML Bit Fields */
#define SIM_UDIDML_ML_MASK               (0xFFFFFFFFu)
#define SIM_UDIDML_ML_SHIFT              (0u)
#define SIM_UDIDML_ML_WIDTH              (32u)

/* UDIDL Bit Fields */
#define SIM_UDIDL_L_MASK                 (0xFFFFFFFFu)
#define SIM_UDIDL_L_SHIFT                (0u)
#define SIM_UDIDL_L_WIDTH                (32u)

/* SDID Bit Fields */
#define SIM_SDID_ID_MASK                 (0xFFFFFFFFu)
#define SIM_SDID_ID_SHIFT                (0u)
#define SIM_SDID_ID_WIDTH                (32u)

/* SW_TRG Bit Fields */
#define SIM_SW_TRG_SW_TRG_MASK           (0x01u)
#define SIM_SW_TRG_SW_TRG_SHIFT          (0u)
#define SIM_SW_TRG_SW_TRG_WIDTH          (1u)

/* CAN Bit Fields */
#define SIM_CAN_WAK_INT_MASK             (0x40000u)
#define SIM_CAN_WAK_INT_SHIFT            (18u)
#define SIM_CAN_WAK_INT_WIDTH            (1u)
#define SIM_CAN_SLF_WAK_MASK             (0x20000u)
#define SIM_CAN_SLF_WAK_SHIFT            (17u)
#define SIM_CAN_SLF_WAK_WIDTH            (1u)
#define SIM_CAN_LPM_ACK_MASK             (0x10000u)
#define SIM_CAN_LPM_ACK_SHIFT            (16u)
#define SIM_CAN_LPM_ACK_WIDTH            (1u)
#define SIM_CAN_IPG_STOP_MASK            (0x08u)
#define SIM_CAN_IPG_STOP_SHIFT           (3u)
#define SIM_CAN_IPG_STOP_WIDTH           (1u)
#define SIM_CAN_SOFT_RESET_MASK          (0x04u)
#define SIM_CAN_SOFT_RESET_SHIFT         (2u)
#define SIM_CAN_SOFT_RESET_WIDTH         (1u)
#define SIM_CAN_IPG_DOZE_MASK            (0x02u)
#define SIM_CAN_IPG_DOZE_SHIFT           (1u)
#define SIM_CAN_IPG_DOZE_WIDTH           (1u)
#define SIM_CAN_WKUP_SRC_SEL_MASK        (0x01u)
#define SIM_CAN_WKUP_SRC_SEL_SHIFT       (0u)
#define SIM_CAN_WKUP_SRC_SEL_WIDTH       (1u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of SIM registers
 */
typedef struct _SimRegType_
{
    uint32_t                RESERVED0[1]; /*!< Reserverd block, offset: 0x00 */
    volatile uint32_t       CHIP;         /*!< system chip register, offset: 0x04 */
    uint32_t                RESERVED1[2]; /*!< Reserverd block, offset: 0x08 */
    volatile uint32_t       PWM_CTRL0;    /*!< system PWM register 0, offset: 0x10 */
    volatile uint32_t       PWM_CTRL1;    /*!< system PWM register 1, offset: 0x14 */
    volatile uint32_t       ADC;          /*!< system ADC register, offset: 0x18 */
    uint32_t                RESERVED2[1]; /*!< Reserverd block, offset: 0x1C */
    volatile uint32_t       I2S;          /*!< system I2S register, offset: 0x20 */
    volatile uint32_t       MFT_CTRL0;    /*!< system MFT register 0, offset: 0x24 */
    volatile uint32_t       MFT_CTRL1;    /*!< system MFT register 1, offset: 0x28 */
    volatile uint32_t       FLASH;        /*!< system flash controller register, offset: 0x2C */
    const volatile uint32_t UDIDH;        /*!< system UD ID high register, offset: 0x30 */
    const volatile uint32_t UDIDMH;       /*!< system UD ID medium high register, offset: 0x34 */
    const volatile uint32_t UDIDML;       /*!< system UD ID medium low register, offset: 0x38 */
    const volatile uint32_t UDIDL;        /*!< system UD ID low register, offset: 0x3C */
    const volatile uint32_t SDID;         /*!< system SDID high register, offset: 0x40 */
    volatile uint32_t       SW_TRG;       /*!< system software trigger register, offset: 0x44 */
    volatile uint32_t       CAN;          /*!< system CAN configure register, offset: 0x48 */
} SimRegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the SRAM initialization status
 *
 * This function gets the current SRAM initialization status.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return SRAM initialization status
 *         - 0b : SRAM initialization is in progress
 *         - 1b : SRAM initialization is done or not started
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetChipSRamInitSt(const SimRegType *obj)
{
    return ((obj->CHIP & SIM_CHIP_SRAM_INIT_ST_MASK) >> SIM_CHIP_SRAM_INIT_ST_SHIFT);
}

/*! \brief Sets the SRAM initial command
 *
 * This function sets the SRAM initial command.
 * SRAM initialization start trigger. Invalid when SRAM_RETEN is 0
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of SRAM initial command
 *                    - 0b : not start SRAM initialization
 *                    - 1b : start SRAM initialization
 */
__attribute__((always_inline)) static inline void SimReg_SetChipSRamInit(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CHIP;

    tmp &= ~SIM_CHIP_SRAM_INIT_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CHIP_SRAM_INIT_SHIFT)) & SIM_CHIP_SRAM_INIT_MASK);
    obj->CHIP = tmp;
}

/*! \brief Gets the SRAM retention
 *
 * This function gets the current SRAM retention.
 * It is reseted by power up and standby exit only.
 *
 * \note If this bit is set to 0 and system reset happens, program heap operation might malfunction.
 *       Use this bit with caution.
 * 
 * \param[in] obj : pointer to SIM register instance
 * \return SRAM retention
 *         - 0b : memory contents are retained across resets.
 *         - 1b : No memory contents retention.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetChipSRamReten(const SimRegType *obj)
{
    return ((obj->CHIP & SIM_CHIP_SRAM_RETEN_MASK) >> SIM_CHIP_SRAM_RETEN_SHIFT);
}

/*! \brief Sets the SRAM retention
 *
 * This function sets the SRAM retention.
 * It is reseted by power up and standby exit only.
 * 
 * \note If this bit is set to 0 and system reset happens, program heap operation might malfunction.
 *       Use this bit with caution.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of SRAM retention
 *                    - 0b : memory contents are retained across resets.
 *                    - 1b : No memory contents retention.
 */
__attribute__((always_inline)) static inline void SimReg_SetChipSRamReten(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CHIP;

    tmp &= ~SIM_CHIP_SRAM_RETEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CHIP_SRAM_RETEN_SHIFT)) & SIM_CHIP_SRAM_RETEN_MASK);
    obj->CHIP = tmp;
}

/*! \brief Gets the PWM3 output channel select
 *
 * This function gets the current PWM3 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM3 output channel select
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl0PwmFunc3(const SimRegType *obj)
{
    return ((obj->PWM_CTRL0 & SIM_PWM_CTRL0_PWM_FUNC3_MASK) >> SIM_PWM_CTRL0_PWM_FUNC3_SHIFT);
}

/*! \brief Sets the PWM3 output channel select
 *
 * This function sets the PWM3 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM3 output channel select
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl0PwmFunc3(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL0;

    tmp &= ~SIM_PWM_CTRL0_PWM_FUNC3_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL0_PWM_FUNC3_SHIFT)) & SIM_PWM_CTRL0_PWM_FUNC3_MASK);
    obj->PWM_CTRL0 = tmp;
}

/*! \brief Gets the PWM2 output channel select
 *
 * This function gets the current PWM2 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM2 output channel select
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl0PwmFunc2(const SimRegType *obj)
{
    return ((obj->PWM_CTRL0 & SIM_PWM_CTRL0_PWM_FUNC2_MASK) >> SIM_PWM_CTRL0_PWM_FUNC2_SHIFT);
}

/*! \brief Sets the PWM2 output channel select
 *
 * This function sets the PWM2 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM2 output channel select
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl0PwmFunc2(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL0;

    tmp &= ~SIM_PWM_CTRL0_PWM_FUNC2_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL0_PWM_FUNC2_SHIFT)) & SIM_PWM_CTRL0_PWM_FUNC2_MASK);
    obj->PWM_CTRL0 = tmp;
}

/*! \brief Gets the PWM1 output channel select
 *
 * This function gets the current PWM1 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM1 output channel select
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl0PwmFunc1(const SimRegType *obj)
{
    return ((obj->PWM_CTRL0 & SIM_PWM_CTRL0_PWM_FUNC1_MASK) >> SIM_PWM_CTRL0_PWM_FUNC1_SHIFT);
}

/*! \brief Sets the PWM1 output channel select
 *
 * This function sets the PWM1 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM1 output channel select
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl0PwmFunc1(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL0;

    tmp &= ~SIM_PWM_CTRL0_PWM_FUNC1_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL0_PWM_FUNC1_SHIFT)) & SIM_PWM_CTRL0_PWM_FUNC1_MASK);
    obj->PWM_CTRL0 = tmp;
}

/*! \brief Gets the PWM0 output channel select
 *
 * This function gets the current PWM0 output channel select.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM0 output channel select
 *         - 0d : PWM0[0]
 *         - 1d : PWM0[1]
 *         - 2d : PWM0[2]
 *         - 3d : PWM0[3]
 *         - 4d : PWM0[4]
 *         - 5d : PWM0[5]
 *         - 6d : PWM1[0]
 *         - 7d : PWM1[1]
 *         - 8d : PWM1[2]
 *         - 9d : PWM1[3]
 *         - 10d : PWM1[4]
 *         - 11d : PWM1[5]
 *         - others : reserved
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl0PwmFunc0(const SimRegType *obj)
{
    return ((obj->PWM_CTRL0 & SIM_PWM_CTRL0_PWM_FUNC0_MASK) >> SIM_PWM_CTRL0_PWM_FUNC0_SHIFT);
}

/*! \brief Sets the PWM0 output channel select
 *
 * This function sets the PWM0 output channel select.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM0 output channel select
 *                    - 0d : PWM0[0]
 *                    - 1d : PWM0[1]
 *                    - 2d : PWM0[2]
 *                    - 3d : PWM0[3]
 *                    - 4d : PWM0[4]
 *                    - 5d : PWM0[5]
 *                    - 6d : PWM1[0]
 *                    - 7d : PWM1[1]
 *                    - 8d : PWM1[2]
 *                    - 9d : PWM1[3]
 *                    - 10d : PWM1[4]
 *                    - 11d : PWM1[5]
 *                    - others : reserved
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl0PwmFunc0(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL0;

    tmp &= ~SIM_PWM_CTRL0_PWM_FUNC0_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL0_PWM_FUNC0_SHIFT)) & SIM_PWM_CTRL0_PWM_FUNC0_MASK);
    obj->PWM_CTRL0 = tmp;
}

/*! \brief Gets the PWM5 output channel select
 *
 * This function gets the current PWM5 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM5 output channel select
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl1PwmFunc5(const SimRegType *obj)
{
    return ((obj->PWM_CTRL1 & SIM_PWM_CTRL1_PWM_FUNC5_MASK) >> SIM_PWM_CTRL1_PWM_FUNC5_SHIFT);
}

/*! \brief Sets the PWM5 output channel select
 *
 * This function sets the PWM5 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM5 output channel select
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl1PwmFunc5(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL1;

    tmp &= ~SIM_PWM_CTRL1_PWM_FUNC5_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL1_PWM_FUNC5_SHIFT)) & SIM_PWM_CTRL1_PWM_FUNC5_MASK);
    obj->PWM_CTRL1 = tmp;
}

/*! \brief Gets the PWM4 output channel select
 *
 * This function gets the current PWM4 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \return PWM4 output channel select
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetPwmCtrl1PwmFunc4(const SimRegType *obj)
{
    return ((obj->PWM_CTRL1 & SIM_PWM_CTRL1_PWM_FUNC4_MASK) >> SIM_PWM_CTRL1_PWM_FUNC4_SHIFT);
}

/*! \brief Sets the PWM4 output channel select
 *
 * This function sets the PWM4 output channel select.
 * channel details are same with SIM_PWM_CTRL0[PWM_FUNC0]
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of PWM4 output channel select
 */
__attribute__((always_inline)) static inline void SimReg_SetPwmCtrl1PwmFunc4(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM_CTRL1;

    tmp &= ~SIM_PWM_CTRL1_PWM_FUNC4_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_PWM_CTRL1_PWM_FUNC4_SHIFT)) & SIM_PWM_CTRL1_PWM_FUNC4_MASK);
    obj->PWM_CTRL1 = tmp;
}

/*! \brief Gets the ADC trigger source
 *
 * This function gets the current ADC trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return ADC trigger source
 *         -  0b : PDB trigger out
 *         -  1b : TRGMUX output
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetAdcTrgSrc(const SimRegType *obj)
{
    return ((obj->ADC & SIM_ADC_TRG_SRC_MASK) >> SIM_ADC_TRG_SRC_SHIFT);
}

/*! \brief Sets the ADC trigger source
 *
 * This function sets the ADC trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of ADC trigger source
 *                    -  0b : PDB trigger out 
 *                    -  1b : TRGMUX output
 */
__attribute__((always_inline)) static inline void SimReg_SetAdcTrgSrc(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SIM_ADC_TRG_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_ADC_TRG_SRC_SHIFT)) & SIM_ADC_TRG_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Gets the ADC software pre trigger source
 *
 * This function gets the current ADC software pre trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return ADC software pre trigger source
 *         - 100b : pretrigger 0
 *         - 101b : pretrigger 1
 *         - 110b : pretrigger 2
 *         - 111b : pretrigger 3
 *         - others : reserved
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetAdcPreTrgSwSrc(const SimRegType *obj)
{
    return ((obj->ADC & SIM_ADC_PRETRG_SW_SRC_MASK) >> SIM_ADC_PRETRG_SW_SRC_SHIFT);
}

/*! \brief Sets the ADC software pre trigger source
 *
 * This function sets the ADC software pre trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of ADC software pre trigger source
 *                    - 100b : pretrigger 0
 *                    - 101b : pretrigger 1
 *                    - 110b : pretrigger 2
 *                    - 111b : pretrigger 3
 *                    - others : reserved
 */
__attribute__((always_inline)) static inline void SimReg_SetAdcPreTrgSwSrc(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SIM_ADC_PRETRG_SW_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_ADC_PRETRG_SW_SRC_SHIFT)) & SIM_ADC_PRETRG_SW_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Gets the ADC pre trigger source
 *
 * This function gets the current ADC pre trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return ADC pre trigger source
 *         - 00b : PDB trigger out
 *         - 01b : TRGMUX output
 *         - 10b : software configure PRETRG1_SW_SRC
 *         - 11b : no hardware trigger
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetAdcPreTrgSrc(const SimRegType *obj)
{
    return ((obj->ADC & SIM_ADC_PRETRG_SRC_MASK) >> SIM_ADC_PRETRG_SRC_SHIFT);
}

/*! \brief Sets the ADC pre trigger source
 *
 * This function sets the ADC pre trigger source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of ADC pre trigger source
 *                    - 00b : PDB trigger out
 *                    - 01b : TRGMUX output
 *                    - 10b : software configure PRETRG1_SW_SRC
 *                    - 11b : no hardware trigger
 */
__attribute__((always_inline)) static inline void SimReg_SetAdcPreTrgSrc(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SIM_ADC_PRETRG_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_ADC_PRETRG_SRC_SHIFT)) & SIM_ADC_PRETRG_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Gets the I2S Slave dma or interrupt mode
 *
 * This function gets the current I2S Slave dma or interrupt mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return I2S Slave dma or interrupt mode
 *         - 0b : interrupt
 *         - 1b : dma
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetI2sSlvDmaIrq(const SimRegType *obj)
{
    return ((obj->I2S & SIM_I2S_SLV_DMA_IRQ_MASK) >> SIM_I2S_SLV_DMA_IRQ_SHIFT);
}

/*! \brief Sets the I2S Slave dma or interrupt mode
 *
 * This function sets the I2S Slave dma or interrupt mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of I2S Slave dma or interrupt mode
 *                    - 0b : interrupt
 *                    - 1b : dma
 */
__attribute__((always_inline)) static inline void SimReg_SetI2sSlvDmaIrq(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2S;

    tmp &= ~SIM_I2S_SLV_DMA_IRQ_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_I2S_SLV_DMA_IRQ_SHIFT)) & SIM_I2S_SLV_DMA_IRQ_MASK);
    obj->I2S = tmp;
}

/*! \brief Gets the I2S Master dma or interrupt mode
 *
 * This function gets the current I2S Master dma or interrupt mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return I2S Master dma or interrupt mode
 *         - 0b : interrupt
 *         - 1b : dma
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetI2sMstDmaIrq(const SimRegType *obj)
{
    return ((obj->I2S & SIM_I2S_MST_DMA_IRQ_MASK) >> SIM_I2S_MST_DMA_IRQ_SHIFT);
}

/*! \brief Sets the I2S Master dma or interrupt mode
 *
 * This function sets the I2S Master dma or interrupt mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of I2S Master dma or interrupt mode
 *                    - 0b : interrupt
 *                    - 1b : dma
 */
__attribute__((always_inline)) static inline void SimReg_SetI2sMstDmaIrq(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2S;

    tmp &= ~SIM_I2S_MST_DMA_IRQ_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_I2S_MST_DMA_IRQ_SHIFT)) & SIM_I2S_MST_DMA_IRQ_MASK);
    obj->I2S = tmp;
}

/*! \brief Gets the I2S mode
 *
 * This function gets the current I2S mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return I2S mode
 *         - 0b : slave
 *         - 1b : master
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetI2sMode(const SimRegType *obj)
{
    return ((obj->I2S & SIM_I2S_MODE_MASK) >> SIM_I2S_MODE_SHIFT);
}

/*! \brief Sets the I2S mode
 *
 * This function sets the I2S mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of I2S mode
 *                    - 0b : slave
 *                    - 1b : master
 */
__attribute__((always_inline)) static inline void SimReg_SetI2sMode(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2S;

    tmp &= ~SIM_I2S_MODE_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_I2S_MODE_SHIFT)) & SIM_I2S_MODE_MASK);
    obj->I2S = tmp;
}

/*! \brief Gets the MFT1 Fault X Select
 *
 * This function gets the current MFT1 Fault X Select.
 * Selects the source of the MFT1 fault.
 * Every bit means one fault input, respectively.
 * If there is no pin assigned to the specific FAULT signal, logic zero is used as input source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT1 Fault X Select
 *         - 0b : MFT1_FLTx pin
 *         - 1b : TRGMUX_MFT1 out
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl0Mft1FltSel(const SimRegType *obj)
{
    return ((obj->MFT_CTRL0 & SIM_MFT_CTRL0_MFT1_FLT_SEL_MASK) >> SIM_MFT_CTRL0_MFT1_FLT_SEL_SHIFT);
}

/*! \brief Sets the MFT1 Fault X Select
 *
 * This function sets the MFT1 Fault X Select.
 * Selects the source of the MFT1 fault.
 * Every bit means one fault input, respectively.
 * If there is no pin assigned to the specific FAULT signal, logic zero is used as input source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT1 Fault X Select
 *                    - 0b : MFT1_FLTx pin
 *                    - 1b : TRGMUX_MFT1 out
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl0Mft1FltSel(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL0;

    tmp &= ~SIM_MFT_CTRL0_MFT1_FLT_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL0_MFT1_FLT_SEL_SHIFT)) & SIM_MFT_CTRL0_MFT1_FLT_SEL_MASK);
    obj->MFT_CTRL0 = tmp;
}

/*! \brief Gets the MFT0 Fault X Select
 *
 * This function gets the current MFT0 Fault X Select.
 * Selects the source of the MFT0 fault.
 * Every bit means one fault input, respectively.
 * If there is no pin assigned to the specific FAULT signal, logic zero is used as input source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT0 Fault X Select
 *         - 0b : MFT0_FLTx pin
 *         - 1b : TRGMUX_MFT0 out
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl0Mft0FltSel(const SimRegType *obj)
{
    return ((obj->MFT_CTRL0 & SIM_MFT_CTRL0_MFT0_FLT_SEL_MASK) >> SIM_MFT_CTRL0_MFT0_FLT_SEL_SHIFT);
}

/*! \brief Sets the MFT0 Fault X Select
 *
 * This function sets the MFT0 Fault X Select.
 * Selects the source of the MFT0 fault.
 * Every bit means one fault input, respectively.
 * If there is no pin assigned to the specific FAULT signal, logic zero is used as input source.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT0 Fault X Select
 *                    - 0b : MFT0_FLTx pin
 *                    - 1b : TRGMUX_MFT0 out
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl0Mft0FltSel(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL0;

    tmp &= ~SIM_MFT_CTRL0_MFT0_FLT_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL0_MFT0_FLT_SEL_SHIFT)) & SIM_MFT_CTRL0_MFT0_FLT_SEL_MASK);
    obj->MFT_CTRL0 = tmp;
}

/*! \brief Gets the MFT global load enable
 *
 * This function gets the current MFT global load enable.
 * This bit is not self-clearing.
 * For subsequent reload operations, it should be cleared and then set.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT global load enable
 *         - 0b : MFT Global load mechanism disabled.
 *         - 1b : MFT Global load mechanism enabled
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl0GldOk(const SimRegType *obj)
{
    return ((obj->MFT_CTRL0 & SIM_MFT_CTRL0_GLDOK_MASK) >> SIM_MFT_CTRL0_GLDOK_SHIFT);
}

/*! \brief Sets the MFT global load enable
 *
 * This function sets the MFT global load enable.
 * This bit is not self-clearing.
 * For subsequent reload operations, it should be cleared and then set.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT global load enable
 *                    - 0b : MFT Global load mechanism disabled.
 *                    - 1b : MFT Global load mechanism enabled
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl0GldOk(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL0;

    tmp &= ~SIM_MFT_CTRL0_GLDOK_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL0_GLDOK_SHIFT)) & SIM_MFT_CTRL0_GLDOK_MASK);
    obj->MFT_CTRL0 = tmp;
}

/*! \brief Gets the MFT1 Sync Bit
 *
 * This function gets the current MFT1 Sync Bit.
 * This is used as a synchronization trigger source for MFT
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT1 Sync Bit
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl1Mft1SyncBit(const SimRegType *obj)
{
    return ((obj->MFT_CTRL1 & SIM_MFT_CTRL1_MFT1SYNCBIT_MASK) >> SIM_MFT_CTRL1_MFT1SYNCBIT_SHIFT);
}

/*! \brief Sets the MFT1 Sync Bit
 *
 * This function sets the MFT1 Sync Bit.
 * This is used as a synchronization trigger source for MFT
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT1 Sync Bit
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl1Mft1SyncBit(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL1;

    tmp &= ~SIM_MFT_CTRL1_MFT1SYNCBIT_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL1_MFT1SYNCBIT_SHIFT)) & SIM_MFT_CTRL1_MFT1SYNCBIT_MASK);
    obj->MFT_CTRL1 = tmp;
}

/*! \brief Gets the MFT0 Sync Bit
 *
 * This function gets the current MFT0 Sync Bit.
 * This is used as a synchronization trigger source for MFT
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT0 Sync Bit
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl1Mft0SyncBit(const SimRegType *obj)
{
    return ((obj->MFT_CTRL1 & SIM_MFT_CTRL1_MFT0SYNCBIT_MASK) >> SIM_MFT_CTRL1_MFT0SYNCBIT_SHIFT);
}

/*! \brief Sets the MFT0 Sync Bit
 *
 * This function sets the MFT0 Sync Bit.
 * This is used as a synchronization trigger source for MFT
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT0 Sync Bit
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl1Mft0SyncBit(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL1;

    tmp &= ~SIM_MFT_CTRL1_MFT0SYNCBIT_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL1_MFT0SYNCBIT_SHIFT)) & SIM_MFT_CTRL1_MFT0SYNCBIT_MASK);
    obj->MFT_CTRL1 = tmp;
}

/*! \brief Gets the MFT1 CH0 Select
 *
 * This function gets the current MFT1 CH0 Select.
 * Selects MFT1 Channel0's input
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT1 CH0 Select
 *         - 0b : MFT1_CH0 input from PAD
 *         - 1b : CMP0 output
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl1Mft1Ch0Sel(const SimRegType *obj)
{
    return ((obj->MFT_CTRL1 & SIM_MFT_CTRL1_MFT1CH0SEL_MASK) >> SIM_MFT_CTRL1_MFT1CH0SEL_SHIFT);
}

/*! \brief Sets the MFT1 CH0 Select
 *
 * This function sets the MFT1 CH0 Select.
 * Selects MFT1 Channel0's input
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT1 CH0 Select
 *                    - 0b : MFT1_CH0 input from PAD
 *                    - 1b : CMP0 output
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl1Mft1Ch0Sel(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL1;

    tmp &= ~SIM_MFT_CTRL1_MFT1CH0SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL1_MFT1CH0SEL_SHIFT)) & SIM_MFT_CTRL1_MFT1CH0SEL_MASK);
    obj->MFT_CTRL1 = tmp;
}

/*! \brief Gets the MFT0 channel modulation select with MFT1_CH1
 *
 * This function gets the current MFT0 channel modulation select with MFT1_CH1.
 * Bits 7 to 0 of this field are for channel 7 to 0, respectively. For each channel,
 *
 * \param[in] obj : pointer to SIM register instance
 * \return MFT0 channel modulation select with MFT1_CH1
 *         - 0b : No modulation with MFT1_CH1
 *         - 1b : Modulation with MFT1_CH1
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetMftCtrl1Mft0OutSel(const SimRegType *obj)
{
    return ((obj->MFT_CTRL1 & SIM_MFT_CTRL1_MFT0_OUTSEL_MASK) >> SIM_MFT_CTRL1_MFT0_OUTSEL_SHIFT);
}

/*! \brief Sets the MFT0 channel modulation select with MFT1_CH1
 *
 * This function sets the MFT0 channel modulation select with MFT1_CH1.
 * Bits 7 to 0 of this field are for channel 7 to 0, respectively. For each channel,
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of MFT0 channel modulation select with MFT1_CH1
 *                    - 0b : No modulation with MFT1_CH1
 *                    - 1b : Modulation with MFT1_CH1
 */
__attribute__((always_inline)) static inline void SimReg_SetMftCtrl1Mft0OutSel(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT_CTRL1;

    tmp &= ~SIM_MFT_CTRL1_MFT0_OUTSEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_MFT_CTRL1_MFT0_OUTSEL_SHIFT)) & SIM_MFT_CTRL1_MFT0_OUTSEL_MASK);
    obj->MFT_CTRL1 = tmp;
}

/*! \brief Gets the flash eee restore config status
 *
 * This function gets the current Flash eee restore config status.
 * Indicates the restore settings of emulated eeprom
 *
 * \param[in] obj : pointer to SIM register instance
 * \return flash eee restore config status.
 *         - 0b : emulated eeprom is configured as not restore after reset
 *         - 1b : emulated eeprom is configured as restore after reset
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashEeeRst(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_EEERST_MASK) >> SIM_FLASH_EEERST_SHIFT);
}

/*! \brief Gets the flash eee valid
 *
 * This function gets the current flash eee valid.
 * emulated eeprom is valid
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Flash eee Valid
 *         - 0b : invalid
 *         - 1b : valid
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashEeeVld(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_EEEVLD_MASK) >> SIM_FLASH_EEEVLD_SHIFT);
}

/*! \brief Gets the flash load is done
 *
 * This function gets the current flash load is done.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return flash load is done
 *         - 0b : during load progress
 *         - 1b : load done
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashLoadDone(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_LOAD_DONE_MASK) >> SIM_FLASH_LOAD_DONE_SHIFT);
}

/*! \brief Gets the flash is blank
 *
 * This function gets the current flash is blank.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return flash is blank
 *         - 0b : flash is not blank
 *         - 1b : flash is blank
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashVirginFlag(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_VIRGIN_FLAG_MASK) >> SIM_FLASH_VIRGIN_FLAG_SHIFT);
}

/*! \brief Gets the dflash prefetch buffer flush
 *
 * This function gets the current dflash prefetch buffer flush.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return dflash prefetch buffer flush
 *         - 0b : do not flush dflash prefetch buffer;
 *         - 1b : flush dflash prefetch buffer;
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashDFlsFlushEn(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_DFLS_FLUSH_EN_MASK) >> SIM_FLASH_DFLS_FLUSH_EN_SHIFT);
}

/*! \brief Sets the dflash prefetch buffer flush
 *
 * This function sets the dflash prefetch buffer flush.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of dflash prefetch buffer flush
 *                    - 0b : do not flush dflash prefetch buffer;
 *                    - 1b : flush dflash prefetch buffer;
 */
__attribute__((always_inline)) static inline void SimReg_SetFlashDFlsFlushEn(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLASH;

    tmp &= ~SIM_FLASH_DFLS_FLUSH_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_FLASH_DFLS_FLUSH_EN_SHIFT)) & SIM_FLASH_DFLS_FLUSH_EN_MASK);
    obj->FLASH = tmp;
}

/*! \brief Gets the pflash prefetch buffer flush
 *
 * This function gets the current pflash prefetch buffer flush.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return pflash prefetch buffer flush
 *         - 0b : do not flush pflash prefetch buffer;
 *         - 1b : flush pflash prefetch buffer;
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashPFlsFlushEn(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_PFLS_FLUSH_EN_MASK) >> SIM_FLASH_PFLS_FLUSH_EN_SHIFT);
}

/*! \brief Sets the pflash prefetch buffer flush
 *
 * This function sets the pflash prefetch buffer flush.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of pflash prefetch buffer flush
 *                    - 0b : do not flush pflash prefetch buffer;
 *                    - 1b : flush pflash prefetch buffer;
 */
__attribute__((always_inline)) static inline void SimReg_SetFlashPFlsFlushEn(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLASH;

    tmp &= ~SIM_FLASH_PFLS_FLUSH_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_FLASH_PFLS_FLUSH_EN_SHIFT)) & SIM_FLASH_PFLS_FLUSH_EN_MASK);
    obj->FLASH = tmp;
}

/*! \brief Gets the dflash prefetch enable
 *
 * This function gets the current dflash prefetch enable.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return dflash prefetch enable
 *         - 0b : disable dflash prefetch;
 *         - 1b : enable dflash prefetch;
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashDFlsPfbEn(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_DFLS_PFB_EN_MASK) >> SIM_FLASH_DFLS_PFB_EN_SHIFT);
}

/*! \brief Sets the dflash prefetch enable
 *
 * This function sets the dflash prefetch enable.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of dflash prefetch enable
 *                    - 0b : disable dflash prefetch;
 *                    - 1b : enable dflash prefetch;
 */
__attribute__((always_inline)) static inline void SimReg_SetFlashDFlsPfbEn(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLASH;

    tmp &= ~SIM_FLASH_DFLS_PFB_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_FLASH_DFLS_PFB_EN_SHIFT)) & SIM_FLASH_DFLS_PFB_EN_MASK);
    obj->FLASH = tmp;
}

/*! \brief Gets the pflash prefetch enable
 *
 * This function gets the current pflash prefetch enable.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return pflash prefetch enable
 *         - 0b : disable pflash prefetch;
 *         - 1b : enable pflash prefetch;
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetFlashPFlsPfbEn(const SimRegType *obj)
{
    return ((obj->FLASH & SIM_FLASH_PFLS_PFB_EN_MASK) >> SIM_FLASH_PFLS_PFB_EN_SHIFT);
}

/*! \brief Sets the pflash prefetch enable
 *
 * This function sets the pflash prefetch enable.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of pflash prefetch enable
 *                    - 0b : disable pflash prefetch;
 *                    - 1b : enable pflash prefetch;
 */
__attribute__((always_inline)) static inline void SimReg_SetFlashPFlsPfbEn(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLASH;

    tmp &= ~SIM_FLASH_PFLS_PFB_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_FLASH_PFLS_PFB_EN_SHIFT)) & SIM_FLASH_PFLS_PFB_EN_MASK);
    obj->FLASH = tmp;
}

/*! \brief Gets the Unique Identification[127:96]
 *
 * This function gets the current Unique Identification[127:96].
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Unique Identification[127:96]
 */
__attribute__((always_inline)) static inline uint32_t SimReg_GetUdidH(const SimRegType *obj)
{
    return ((obj->UDIDH & SIM_UDIDH_H_MASK) >> SIM_UDIDH_H_SHIFT);
}

/*! \brief Gets the Unique Identification[95:64]
 *
 * This function gets the current Unique Identification[95:64].
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Unique Identification[95:64]
 */
__attribute__((always_inline)) static inline uint32_t SimReg_GetUdidMH(const SimRegType *obj)
{
    return ((obj->UDIDMH & SIM_UDIDMH_MH_MASK) >> SIM_UDIDMH_MH_SHIFT);
}

/*! \brief Gets the Unique Identification[63:32]
 *
 * This function gets the current Unique Identification[63:32].
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Unique Identification[63:32]
 */
__attribute__((always_inline)) static inline uint32_t SimReg_GetUdidML(const SimRegType *obj)
{
    return ((obj->UDIDML & SIM_UDIDML_ML_MASK) >> SIM_UDIDML_ML_SHIFT);
}

/*! \brief Gets the Unique Identification[31:0]
 *
 * This function gets the current Unique Identification[31:0].
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Unique Identification[31:0]
 */
__attribute__((always_inline)) static inline uint32_t SimReg_GetUdidL(const SimRegType *obj)
{
    return ((obj->UDIDL & SIM_UDIDL_L_MASK) >> SIM_UDIDL_L_SHIFT);
}

/*! \brief Gets the System Device Identification
 *
 * This function gets the current System Device Identification.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return System Device Identification
 */
__attribute__((always_inline)) static inline uint32_t SimReg_GetSdId(const SimRegType *obj)
{
    return ((obj->SDID & SIM_SDID_ID_MASK) >> SIM_SDID_ID_SHIFT);
}

/*! \brief Gets the Software trigger to TRGMUX
 *
 * This function gets the current Software trigger to TRGMUX.
 * Writing to this bit generates software trigger to peripheral
 *
 * \param[in] obj : pointer to SIM register instance
 * \return Software trigger to TRGMUX
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetSwTrg(const SimRegType *obj)
{
    return ((obj->SW_TRG & SIM_SW_TRG_SW_TRG_MASK) >> SIM_SW_TRG_SW_TRG_SHIFT);
}

/*! \brief Sets the Software trigger to TRGMUX
 *
 * This function sets the Software trigger to TRGMUX.
 * Writing to this bit generates software trigger to peripheral
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of Software trigger to TRGMUX
 */
__attribute__((always_inline)) static inline void SimReg_SetSwTrg(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SW_TRG;

    tmp &= ~SIM_SW_TRG_SW_TRG_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_SW_TRG_SW_TRG_SHIFT)) & SIM_SW_TRG_SW_TRG_MASK);
    obj->SW_TRG = tmp;
}

/*! \brief Gets the unmasked wake up interrupt flag
 *
 * This function gets the current unmasked wake up interrupt flag.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return unmasked wake up interrupt flag
 *         - 0b : there haven't wake up interrupt.
 *         - 1b : wake up interrrupt.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanWakInt(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_WAK_INT_MASK) >> SIM_CAN_WAK_INT_SHIFT);
}

/*! \brief Gets the FlexCAN self wakeup enable
 *
 * This function gets the current FlexCAN self wakeup enable.
 * Indicates that the FlexCAN self wake up mechanism is enabled.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return FlexCAN self wakeup enable
 *         - 0b : the self wake up mechanism is not enabled.
 *         - 1b : the self wake up mechanism enabled.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanSlfWak(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_SLF_WAK_MASK) >> SIM_CAN_SLF_WAK_SHIFT);
}

/*! \brief Gets the FlexCAN  low power mode flag
 *
 * This function gets the current FlexCAN low power mode flag.
 * Indicates that the FlexCAN is in either Doze mode or stop mode.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return FlexCAN  low power mode flag
 *         - 0b : the state is normal work mode.
 *         - 1b : the state is in low power mode.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanLpmAck(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_LPM_ACK_MASK) >> SIM_CAN_LPM_ACK_SHIFT);
}

/*! \brief Gets the CAN stop mode request
 *
 * This function gets the current CAN stop mode request.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return CAN stop mode request
 *         - 0b : not request.
 *         - 1b : stop mode request.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanIpgStop(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_IPG_STOP_MASK) >> SIM_CAN_IPG_STOP_SHIFT);
}

/*! \brief Sets the CAN stop mode request
 *
 * This function sets the CAN stop mode request.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of CAN stop mode request
 *                    - 0b : not request.
 *                    - 1b : stop mode request.
 */
__attribute__((always_inline)) static inline void SimReg_SetCanIpgStop(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~SIM_CAN_IPG_STOP_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CAN_IPG_STOP_SHIFT)) & SIM_CAN_IPG_STOP_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the CAN soft reset
 *
 * This function gets the current CAN soft reset.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return CAN soft reset
 *         - 0b : not reset.
 *         - 1b : reset.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanSoftReset(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_SOFT_RESET_MASK) >> SIM_CAN_SOFT_RESET_SHIFT);
}

/*! \brief Sets the CAN soft reset
 *
 * This function sets the CAN soft reset.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of CAN soft reset
 *                    - 0b : not reset.
 *                    - 1b : reset.
 */
__attribute__((always_inline)) static inline void SimReg_SetCanSoftReset(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~SIM_CAN_SOFT_RESET_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CAN_SOFT_RESET_SHIFT)) & SIM_CAN_SOFT_RESET_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the CAN doze mode request
 *
 * This function gets the current CAN doze mode request.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \return CAN doze mode request
 *         - 0b : not request.
 *         - 1b : doze request.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanIpgDoze(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_IPG_DOZE_MASK) >> SIM_CAN_IPG_DOZE_SHIFT);
}

/*! \brief Sets the CAN doze mode request
 *
 * This function sets the CAN doze mode request.
 * high active.
 *
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of CAN doze mode request
 *                    - 0b : not request.
 *                    - 1b : doze request.
 */
__attribute__((always_inline)) static inline void SimReg_SetCanIpgDoze(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~SIM_CAN_IPG_DOZE_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CAN_IPG_DOZE_SHIFT)) & SIM_CAN_IPG_DOZE_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the CAN wake up function select signal 
 *
 * This function gets the current CAN wake up function select signal .
 *           
 * \param[in] obj : pointer to SIM register instance
 * \return CAN wake up function select signal 
 *         - 1b : support stop and doze mode.           
 *         - 0b : select not support stop and doze mode.
 */
__attribute__((always_inline)) static inline uint8_t SimReg_GetCanWkupSrcSel(const SimRegType *obj)
{
    return ((obj->CAN & SIM_CAN_WKUP_SRC_SEL_MASK) >> SIM_CAN_WKUP_SRC_SEL_SHIFT);
}

/*! \brief Sets the CAN wake up function select signal 
 *
 * This function sets the CAN wake up function select signal .
 *           
 * \param[in] obj : pointer to SIM register instance
 * \param[in] value : the value of CAN wake up function select signal 
 *                    - 1b : support stop and doze mode.           
 *                    - 0b : select not support stop and doze mode.
 */
__attribute__((always_inline)) static inline void SimReg_SetCanWkupSrcSel(SimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~SIM_CAN_WKUP_SRC_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SIM_CAN_WKUP_SRC_SEL_SHIFT)) & SIM_CAN_WKUP_SRC_SEL_MASK);
    obj->CAN = tmp;
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _SIM_REG_H_ */
