commit 43711614de6d52e12304c3498de6caeab50fb622 Author: sunbeam Date: Fri Jan 5 16:19:49 2024 +0800 初版 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..6a39688 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +DefaultBuild +SmartManual Docs +/app/QualityReport(M12,DefaultBuild).txt diff --git a/app/.vscode/c_cpp_properties.json b/app/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..1bafd4f --- /dev/null +++ b/app/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${workspaceFolder}/**" + ], + "defines": [ + "_DEBUG", + "UNICODE", + "_UNICODE", + "__near= " + ], + "windowsSdkVersion": "10.0.18362.0", + "compilerPath": "C:\\Program Files (x86)\\Microsoft Visual Studio\\2019\\Community\\VC\\Tools\\MSVC\\14.28.29333\\bin\\Hostx64\\x64\\cl.exe", + "cStandard": "c17", + "cppStandard": "c++17", + "intelliSenseMode": "windows-msvc-x64" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/app/.vscode/settings.json b/app/.vscode/settings.json new file mode 100644 index 0000000..54210bb --- /dev/null +++ b/app/.vscode/settings.json @@ -0,0 +1,13 @@ +{ + "files.associations": { + "r_cg_macrodriver.h": "c", + "r_cg_userdefine.h": "c", + "r_cg_timer.h": "c", + "r_cg_port.h": "c", + "event.h": "c", + "r_cg_wdt.h": "c", + "hwctrl.h": "c", + "apptask.h": "c", + "r_cg_serial.h": "c" + } +} \ No newline at end of file diff --git a/app/M12.dm01.mtud b/app/M12.dm01.mtud new file mode 100644 index 0000000..735707c --- /dev/null +++ b/app/M12.dm01.mtud @@ -0,0 +1,579 @@ + + + + 0 + R5F10268 + SymbolOffset + Yes + + + + + Header=True,LineEditor=True,SelectionEditor=True,Out of Date Module Indicator=True,Coverage=True,Address=True,Event=True,MainDebug=True,Main=True,OpCode=True,Label=True, + + + 0 + + + + + True + NonStopOverwriteMemory + ST10US + All + False + OverThreshold + False + False + + + + + 12.2.20122.2006 + + + + + 12.2.20122.2006 + 9.07.00.06 + F o r m a t V e r s i o n : 1 . 0  
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   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 6 7 6 1 0 5 2 - 9 7 c 4 - 4 2 f 3 - b c a 7 - 1 a 6 2 5 b 9 9 3 b 4 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : c 2 2 2 5 7 3 2 - 0 5 2 5 - 4 f 5 e - a 2 8 c - 1 6 d 5 a c c 5 5 8 c 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 1 3 f f 2 5 7 - c 5 1 a - 4 c f a - 9 2 1 3 - a 7 d 0 2 f c 5 4 e 3 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d d c d 5 d 9 a - d 2 d b - 4 2 1 6 - 8 8 2 b - 8 0 2 3 0 0 d d b a 6 c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d e e 4 e 6 3 5 - b d c d - 4 b 8 b - 8 5 5 e - e 3 6 2 f 1 9 5 7 b 1 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 f e e c 6 5 b - 5 0 d e - 4 8 8 3 - 9 6 9 2 - 7 e e 0 8 1 3 5 2 9 5 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 6 3 4 7 5 7 9 - 4 4 8 9 - 4 b 9 8 - 8 e 6 5 - a c 7 8 c 9 3 2 f 4 0 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 5 1 7 9 1 6 3 - 5 9 0 0 - 4 8 c 7 - a a 3 a - 5 9 3 a 6 5 9 4 a 7 2 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e b u g C o n s o l e P a n e l  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 5 6 f 8 0 8 1 - 8 5 0 f - 4 7 f 7 - 9 1 4 0 - 4 5 0 7 9 8 6 6 c 4 a 3  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l F u n c t i o n L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : a 6 8 2 6 9 7 9 - e a a 0 - 4 0 1 8 - 9 e 0 e - 8 7 d d d 1 7 9 c 8 3 4  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V a r i a b l e L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : a 0 0 7 2 5 7 2 - f 9 8 f - 4 c 2 6 - 9 c 8 4 - a 6 b e 2 0 e 2 0 f f 8  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l A n a l y s i s C h a r t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b a 2 f a f 6 9 - 7 e 6 a - 4 6 b c - 9 d 1 3 - 3 0 3 b e 8 c 4 d e 2 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C a l l G r a p h  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : a f 4 7 d 8 7 b - 1 a 1 a - 4 d 8 6 - a 7 1 6 - b a 3 0 6 c 1 1 a 5 c 0  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C a n R e c P r o c T i m e  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d L e f t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 6 9 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1 2  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 b 0 e c e a 0 - e 6 a 5 - 4 0 1 1 - 9 0 4 4 - 8 5 3 f 5 0 b a 5 3 8 4  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l I n C a r T o o l s C a t e l o g  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 f 8 b f 4 f 6 - 6 b 5 5 - 4 2 5 2 - 8 9 b 5 - c 0 6 b c 4 4 a f 8 7 3  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S t a r t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 5 f 1 a 3 c 7 - 0 b 9 1 - 4 7 9 4 - 9 d 4 a - c 2 8 a 9 b 1 f e 7 e 5  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 9 5 ,   6 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o j e c t T r e e  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 3 8 7 2 8 3 3 - 3 f 3 1 - 4 a c c - 8 8 9 2 - 7 7 d 4 7 7 0 a e a 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t M a n u a l  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 2 8 f 4 2 9 3 - e b f 0 - 4 2 4 3 - 9 d 0 0 - 9 a 1 2 6 5 c 2 9 b 9 b  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o p e r t y G r i d  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 a 5 8 5 c 8 c - 0 2 4 d - 4 4 1 1 - 8 3 b d - 6 5 5 d e 7 3 9 f 1 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y M a p p i n g P r o f i l e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 7 9 d 4 9 2 4 - a 5 a 8 - 4 3 d 1 - b c 4 9 - 6 7 6 c c 7 b 8 c 6 0 4  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 b 0 c 7 8 6 a - 8 3 f c - 4 b b 9 - b e 8 e - f 9 b 9 8 e 1 4 0 7 b 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 8 5 6 6 b b 9 - 6 7 b 1 - 4 9 1 d - b a 9 e - 7 5 4 a 9 c d f 4 e 4 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 f e 5 5 d d b - 4 e f 1 - 4 c f 1 - 9 e 7 8 - 8 e c f a 5 0 e e a 7 e  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 7 9 a 5 5 a 9 - 8 7 d 7 - 4 1 1 a - 9 3 a e - 9 7 c 1 5 5 b 9 7 4 c 4  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C l a s s M e m b e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 a b 8 5 2 4 0 - a 1 7 1 - 4 6 b 3 - b 8 4 4 - e 3 c b 2 3 b 7 8 6 f f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O r t h o g o n a l A n a l y s i s  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 3 7 ,   5 7 8  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 8 4 5 ,   6 4 3  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : H o r i z o n t a l S p l i t  
 D o c k A r e a P a n e . P a n e s . C o u n t : 0  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d B o t t o m  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 1 2 4 1 ,   2 0 2  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 8 4 5 ,   6 4 3  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 4  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 3 2 f 6 e 3 d - 2 0 f b - 4 0 b 8 - 8 b 3 d - a 6 4 4 d 4 7 6 b 3 4 0  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O u t p u t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 c 5 f 6 5 9 c - 5 b 3 4 - 4 8 f 6 - a 8 3 7 - 0 8 a a 3 2 2 f 9 e 4 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t B r o w s e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 6 b d 1 a 9 9 - 1 6 8 8 - 4 2 d 8 - 8 a c 6 - 1 7 3 a 1 5 0 9 e 2 d c  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l E r r o r L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b 5 4 d c b b a - 3 b b 5 - 4 3 f 4 - b 9 6 a - 9 6 9 9 b 4 b 0 d 3 6 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P y t h o n C o n s o l e  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c a 1 c b 8 1 f - 7 9 1 0 - 4 b 3 7 - b c 8 5 - 9 6 a 4 1 d b d e 4 7 2  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 5 6 ,   2 5 6  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 9 2 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 3 8 1 4 d 2 e - 5 2 5 8 - 4 3 2 e - 8 1 4 7 - e 2 e a 2 9 a e a 3 7 5  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : c a 1 c b 8 1 f - 7 9 1 0 - 4 b 3 7 - b c 8 5 - 9 6 a 4 1 d b d e 4 7 2  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D e b u g M a n a g e r  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 1 e e 1 2 c 2 0 - c 3 0 4 - 4 1 e 7 - 8 3 1 a - f 3 8 a b 2 7 6 9 7 2 6  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b a 0 4 c 1 9 8 - d a e f - 4 e e c - 8 0 1 b - 0 3 d 0 9 9 4 c 3 7 e 2  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 e e 1 2 c 2 0 - c 3 0 4 - 4 1 e 7 - 8 3 1 a - f 3 8 a b 2 7 6 9 7 2 6  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 4 e f 1 9 0 7 a - 4 d e 5 - 4 3 d 1 - 9 3 9 6 - b 4 0 d a 9 f d 0 6 3 5  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : e 7 5 e 7 a 9 b - 2 e 5 1 - 4 d a 8 - b 0 7 e - b 2 2 a d 4 4 8 f 6 b 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 4 e f 1 9 0 7 a - 4 d e 5 - 4 3 d 1 - 9 3 9 6 - b 4 0 d a 9 f d 0 6 3 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e L i s t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 1 0 1 1 9 8 f - a b 9 d - 4 e 5 7 - 9 3 a 0 - 1 c 2 1 4 d 6 7 b 1 9 0  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 8 c 4 4 9 a 3 - 5 0 9 c - 4 b 6 5 - 9 3 6 0 - a a d 7 2 6 1 5 a 0 e b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 1 0 1 1 9 8 f - a b 9 d - 4 e 5 7 - 9 3 a 0 - 1 c 2 1 4 d 6 7 b 1 9 0  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : M a c r o P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 7 c d 1 a e d - d c 3 4 - 4 6 e b - 9 6 1 5 - 5 2 c a 4 7 a c f 0 b 8  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 3 8 c 0 0 e f - 2 a 8 f - 4 2 d 7 - 9 2 b 5 - 7 7 4 a 0 4 a b 8 b f a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 9 7 c d 1 a e d - d c 3 4 - 4 6 e b - 9 6 1 5 - 5 2 c a 4 7 a c f 0 b 8  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : T e x t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 6 2 1 b b 0 4 c - 5 7 0 5 - 4 9 e b - 9 a b c - a 6 5 9 2 d 1 2 a 4 7 1  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   6 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 9 a c 1 b 4 7 - 4 a 3 d - 4 5 6 c - 9 0 8 9 - e 4 b a 5 5 b 6 5 3 8 0  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 6 2 1 b b 0 4 c - 5 7 0 5 - 4 9 e b - 9 a b c - a 6 5 9 2 d 1 2 a 4 7 1  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V i r t u a l B o a r d  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : b 1 4 d 3 0 b c - 4 d 7 a - 4 2 a 5 - b d a 8 - 6 3 1 e d c 8 7 b 5 5 5  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 a 1 e 7 8 4 c - f 2 8 9 - 4 8 6 0 - a 4 0 c - a d 7 a e c f 2 c 8 5 f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : b 1 4 d 3 0 b c - 4 d 7 a - 4 2 a 5 - b d a 8 - 6 3 1 e d c 8 7 b 5 5 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e P i n L i s t F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 1 8 0 e 3 4 f b - d 7 0 4 - 4 5 9 2 - a 7 1 8 - f e e 9 5 f a 4 d c 2 6  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 f d 0 5 4 5 9 - f 1 7 b - 4 5 0 5 - b 0 2 0 - 3 c 5 6 5 6 7 9 0 c b f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 8 0 e 3 4 f b - d 7 0 4 - 4 5 9 2 - a 7 1 8 - f e e 9 5 f a 4 d c 2 6  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p V i e w F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 3 1 4 2 5 4 7 - 4 2 f b - 4 4 9 3 - 9 d 6 a - f 6 3 4 f 5 9 1 f 8 d 6  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 a 6 c 5 6 7 1 - b f 3 1 - 4 0 a d - 8 0 a 4 - 4 8 0 c 8 9 5 0 d a 8 9  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 9 3 1 4 2 5 4 7 - 4 2 f b - 4 4 9 3 - 9 d 6 a - f 6 3 4 f 5 9 1 f 8 d 6  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 2 4 5 5 f 5 6 6 - 5 b 8 9 - 4 3 f e - b 8 0 8 - a f 8 8 6 4 1 8 b d a 8  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 f 3 2 6 7 0 4 - 1 9 d 0 - 4 0 7 e - a f 5 9 - b 0 a 8 1 5 9 6 0 4 2 e  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 2 4 5 5 f 5 6 6 - 5 b 8 9 - 4 3 f e - b 8 0 8 - a f 8 8 6 4 1 8 b d a 8  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t P r e v i e w  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 0 d 0 6 b 1 f a - d b b f - 4 a 4 8 - a 7 6 6 - 6 9 5 1 2 2 7 b 2 e 9 1  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 6 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 2 4 8 9 5 d 5 - d 5 4 e - 4 2 b f - 8 f a 2 - 7 d f b a 2 8 8 c a 6 e  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 0 d 0 6 b 1 f a - d b b f - 4 a 4 8 - a 7 6 6 - 6 9 5 1 2 2 7 b 2 e 9 1  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P s e u d o E r r o r D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 7 6 9 4 3 8 1 4 - 1 b d 2 - 4 c 3 8 - 8 f 9 f - b f 3 8 0 1 a 4 b 4 5 a  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 5 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 1 0 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 c 4 f 7 1 8 b - 7 3 b f - 4 4 9 b - 8 7 4 d - 8 e 3 4 3 4 8 0 8 2 9 f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 7 6 9 4 3 8 1 4 - 1 b d 2 - 4 c 3 8 - 8 f 9 f - b f 3 8 0 1 a 4 b 4 5 a  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C A N R e c e i v e D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 4 5 c 2 9 1 8 4 - 4 3 3 d - 4 1 e 4 - a 0 0 7 - f 2 d 9 2 c a 4 b 1 c 7  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 2 5 c 4 3 9 f 3 - 6 3 9 4 - 4 b 2 1 - 8 b 2 6 - a a 4 d 0 b 8 2 7 f 2 9  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 4 5 c 2 9 1 8 4 - 4 3 3 d - 4 1 e 4 - a 0 0 7 - f 2 d 9 2 c a 4 b 1 c 7  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C u r C o n s u m p t i o n  
  + < S O A P - E N V : E n v e l o p e   x m l n s : x s i = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a - i n s t a n c e "   x m l n s : x s d = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a "   x m l n s : S O A P - E N C = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / "   x m l n s : S O A P - E N V = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n v e l o p e / "   x m l n s : c l r = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / s o a p / e n c o d i n g / c l r / 1 . 0 "   S O A P - E N V : e n c o d i n g S t y l e = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / " >  
 < S O A P - E N V : B o d y >  
 < a 1 : O b j e c t S t r e a m e r   i d = " r e f - 1 "   x m l n s : a 1 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i " >  
 < O b j e c t S t r e a m e r A s s e m b l y N a m e   i d = " r e f - 5 " > I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i < / O b j e c t S t r e a m e r A s s e m b l y N a m e >  
 < T a b S e t t i n g s   h r e f = " # r e f - 6 " / >  
 < H i d d e n T a b s   h r e f = " # r e f - 7 " / >  
 < T a b G r o u p s   h r e f = " # r e f - 8 " / >  
 < M a x T a b G r o u p s > 4 < / M a x T a b G r o u p s >  
 < A c t i v e T a b G r o u p I n d e x > 0 < / A c t i v e T a b G r o u p I n d e x >  
 < S p l i t t e r A p p e a r a n c e   h r e f = " # r e f - 9 " / >  
 < S p l i t t e r B o r d e r S t y l e > 6 < / S p l i t t e r B o r d e r S t y l e >  
 < V i e w S t y l e > 4 < / V i e w S t y l e >  
 < T a b G r o u p S e t t i n g s   h r e f = " # r e f - 1 0 " / >  
 < / a 1 : O b j e c t S t r e a m e r >  
 < a 2 : M d i T a b S e t t i n g s   i d = " r e f - 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < A c t i v e T a b A p p e a r a n c e   h r e f = " # r e f - 1 1 " / >  
 < D i s p l a y F o r m I c o n > 1 < / D i s p l a y F o r m I c o n >  
 < H o t T r a c k > 1 < / H o t T r a c k >  
 < S e l e c t e d T a b A p p e a r a n c e   h r e f = " # r e f - 1 2 " / >  
 < T a b A p p e a r a n c e   h r e f = " # r e f - 1 3 " / >  
 < / a 2 : M d i T a b S e t t i n g s >  
 < a 2 : H i d d e n M d i T a b s C o l l e c t i o n   i d = " r e f - 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 7 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 1 4 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 1 5 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 1 6 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 1 7 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 1 8 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 1 9 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 2 0 " / >  
 < _ x 0 0 3 7 _   h r e f = " # r e f - 2 1 " / >  
 < _ x 0 0 3 8 _   h r e f = " # r e f - 2 2 " / >  
 < _ x 0 0 3 9 _   h r e f = " # r e f - 2 3 " / >  
 < _ x 0 0 3 1 _ 0   h r e f = " # r e f - 2 4 " / >  
 < _ x 0 0 3 1 _ 1   h r e f = " # r e f - 2 5 " / >  
 < _ x 0 0 3 1 _ 2   h r e f = " # r e f - 2 6 " / >  
 < _ x 0 0 3 1 _ 3   h r e f = " # r e f - 2 7 " / >  
 < _ x 0 0 3 1 _ 4   h r e f = " # r e f - 2 8 " / >  
 < _ x 0 0 3 1 _ 5   h r e f = " # r e f - 2 9 " / >  
 < _ x 0 0 3 1 _ 6   h r e f = " # r e f - 3 0 " / >  
 < / a 2 : H i d d e n M d i T a b s C o l l e c t i o n >  
 < a 2 : M d i T a b G r o u p s C o l l e c t i o n   i d = " r e f - 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 3 1 " / >  
 < / a 2 : M d i T a b G r o u p s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 9 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 2 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b G r o u p S e t t i n g s   i d = " r e f - 1 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C l o s e B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 3 " / >  
 < T a b L i s t B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 4 " / >  
 < S c r o l l B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 5 " / >  
 < T a b A r e a A p p e a r a n c e   h r e f = " # r e f - 3 6 " / >  
 < S h o w T a b L i s t B u t t o n > 1 < / S h o w T a b L i s t B u t t o n >  
 < T a b B u t t o n S t y l e > 1 6 < / T a b B u t t o n S t y l e >  
 < S c r o l l A r r o w S t y l e > 2 < / S c r o l l A r r o w S t y l e >  
 < S c r o l l B u t t o n s > 3 < / S c r o l l B u t t o n s >  
 < T a b S t y l e > 2 < / T a b S t y l e >  
 < T a b A r e a M a r g i n s   h r e f = " # r e f - 3 7 " / >  
 < C l o s e B u t t o n L o c a t i o n > 2 < / C l o s e B u t t o n L o c a t i o n >  
 < / a 2 : M d i T a b G r o u p S e t t i n g s >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 1 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 8 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 9 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 0 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b   i d = " r e f - 1 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 8 7 1 4 4 3 1 9 0 < / _ a >  
 < _ b > 2 7 4 7 7 < / _ b >  
 < _ c > 1 6 9 7 8 < / _ c >  
 < _ d > 1 3 7 < / _ d >  
 < _ e > 1 8 1 < / _ e >  
 < _ f > 1 9 2 < / _ f >  
 < _ g > 1 0 7 < / _ g >  
 < _ h > 1 9 6 < / _ h >  
 < _ i > 7 4 < / _ i >  
 < _ j > 2 4 8 < / _ j >  
 < _ k > 1 1 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 7 5 1 2 9 9 8 0 4 < / _ a >  
 < _ b > - 2 3 1 2 8 < / _ b >  
 < _ c > 1 7 3 6 1 < / _ c >  
 < _ d > 1 8 8 < / _ d >  
 < _ e > 7 3 < / _ e >  
 < _ f > 1 0 3 < / _ f >  
 < _ g > 1 0 8 < / _ g >  
 < _ h > 1 9 9 < / _ h >  
 < _ i > 1 8 4 < / _ i >  
 < _ j > 1 9 8 < / _ j >  
 < _ k > 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 9 9 0 6 7 3 0 0 2 < / _ a >  
 < _ b > - 3 1 7 4 8 < / _ b >  
 < _ c > 1 9 3 8 5 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 4 2 < / _ e >  
 < _ f > 2 4 9 < / _ f >  
 < _ g > 1 8 5 < / _ g >  
 < _ h > 1 4 2 < / _ h >  
 < _ i > 2 0 < / _ i >  
 < _ j > 7 < / _ j >  
 < _ k > 1 8 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 2 8 5 5 4 0 5 5 < / _ a >  
 < _ b > 2 6 5 4 5 < / _ b >  
 < _ c > 1 8 7 1 7 < / _ c >  
 < _ d > 1 8 6 < / _ d >  
 < _ e > 1 5 8 < / _ e >  
 < _ f > 1 1 7 < / _ f >  
 < _ g > 7 4 < / _ g >  
 < _ h > 1 5 6 < / _ h >  
 < _ i > 2 2 3 < / _ i >  
 < _ j > 7 8 < / _ j >  
 < _ k > 7 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 2 1 4 5 7 3 8 2 0 3 < / _ a >  
 < _ b > 2 0 2 0 9 < / _ b >  
 < _ c > 1 9 6 9 7 < / _ c >  
 < _ d > 1 5 8 < / _ d >  
 < _ e > 1 2 0 < / _ e >  
 < _ f > 1 4 2 < / _ f >  
 < _ g > 2 0 7 < / _ g >  
 < _ h > 1 6 5 < / _ h >  
 < _ i > 1 4 < / _ i >  
 < _ j > 2 3 4 < / _ j >  
 < _ k > 1 2 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 9 7 3 9 2 0 6 2 8 < / _ a >  
 < _ b > 5 8 9 < / _ b >  
 < _ c > 1 7 4 2 5 < / _ c >  
 < _ d > 1 3 1 < / _ d >  
 < _ e > 1 8 9 < / _ e >  
 < _ f > 1 0 1 < / _ f >  
 < _ g > 9 3 < / _ g >  
 < _ h > 2 3 1 < / _ h >  
 < _ i > 5 7 < / _ i >  
 < _ j > 2 4 1 < / _ j >  
 < _ k > 7 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 1 7 4 0 9 3 4 1 6 < / _ a >  
 < _ b > - 9 4 8 9 < / _ b >  
 < _ c > 2 0 2 0 4 < / _ c >  
 < _ d > 1 2 8 < / _ d >  
 < _ e > 2 7 < / _ e >  
 < _ f > 3 < / _ f >  
 < _ g > 2 0 8 < / _ g >  
 < _ h > 1 5 3 < / _ h >  
 < _ i > 7 6 < / _ i >  
 < _ j > 5 5 < / _ j >  
 < _ k > 2 2 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 4 1 3 2 3 8 6 2 9 < / _ a >  
 < _ b > 1 1 8 5 7 < / _ b >  
 < _ c > 1 9 8 8 0 < / _ c >  
 < _ d > 1 7 6 < / _ d >  
 < _ e > 1 2 6 < / _ e >  
 < _ f > 1 7 8 < / _ f >  
 < _ g > 4 2 < / _ g >  
 < _ h > 2 1 2 < / _ h >  
 < _ i > 7 2 < / _ i >  
 < _ j > 2 4 6 < / _ j >  
 < _ k > 1 8 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 0 0 0 4 0 2 0 1 3 < / _ a >  
 < _ b > 2 0 6 3 6 < / _ b >  
 < _ c > 1 9 3 0 1 < / _ c >  
 < _ d > 1 4 7 < / _ d >  
 < _ e > 9 6 < / _ e >  
 < _ f > 1 7 0 < / _ f >  
 < _ g > 2 1 5 < / _ g >  
 < _ h > 3 8 < / _ h >  
 < _ i > 2 1 < / _ i >  
 < _ j > 1 6 0 < / _ j >  
 < _ k > 2 3 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 0 8 9 2 8 5 2 9 < / _ a >  
 < _ b > 1 0 8 9 5 < / _ b >  
 < _ c > 1 7 1 1 1 < / _ c >  
 < _ d > 1 4 6 < / _ d >  
 < _ e > 1 8 1 < / _ e >  
 < _ f > 1 1 9 < / _ f >  
 < _ g > 7 4 < / _ g >  
 < _ h > 4 < / _ h >  
 < _ i > 1 7 1 < / _ i >  
 < _ j > 1 3 9 < / _ j >  
 < _ k > 2 5 0 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 6 1 0 1 4 4 3 9 8 < / _ a >  
 < _ b > - 1 6 4 9 < / _ b >  
 < _ c > 1 9 4 9 4 < / _ c >  
 < _ d > 1 5 6 < / _ d >  
 < _ e > 1 3 2 < / _ e >  
 < _ f > 1 6 6 < / _ f >  
 < _ g > 1 9 0 < / _ g >  
 < _ h > 3 2 < / _ h >  
 < _ i > 2 2 6 < / _ i >  
 < _ j > 1 5 < / _ j >  
 < _ k > 2 4 8 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 4 5 3 9 5 5 2 3 2 < / _ a >  
 < _ b > - 6 4 9 1 < / _ b >  
 < _ c > 1 6 4 0 1 < / _ c >  
 < _ d > 1 4 4 < / _ d >  
 < _ e > 6 8 < / _ e >  
 < _ f > 1 3 3 < / _ f >  
 < _ g > 6 3 < / _ g >  
 < _ h > 8 0 < / _ h >  
 < _ i > 1 8 6 < / _ i >  
 < _ j > 8 3 < / _ j >  
 < _ k > 1 3 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 7 9 8 5 1 8 4 0 < / _ a >  
 < _ b > - 2 4 2 0 7 < / _ b >  
 < _ c > 1 8 0 9 9 < / _ c >  
 < _ d > 1 8 4 < / _ d >  
 < _ e > 6 8 < / _ e >  
 < _ f > 2 2 7 < / _ f >  
 < _ g > 2 0 3 < / _ g >  
 < _ h > 3 5 < / _ h >  
 < _ i > 1 8 3 < / _ i >  
 < _ j > 1 3 4 < / _ j >  
 < _ k > 2 5 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 1 7 1 2 8 0 0 2 3 < / _ a >  
 < _ b > 3 2 3 6 2 < / _ b >  
 < _ c > 1 8 1 0 8 < / _ c >  
 < _ d > 1 5 7 < / _ d >  
 < _ e > 1 9 < / _ e >  
 < _ f > 4 8 < / _ f >  
 < _ g > 5 9 < / _ g >  
 < _ h > 2 3 2 < / _ h >  
 < _ i > 1 9 6 < / _ i >  
 < _ j > 2 2 2 < / _ j >  
 < _ k > 4 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 8 7 5 9 2 4 0 5 7 < / _ a >  
 < _ b > - 3 7 1 7 < / _ b >  
 < _ c > 1 7 6 6 9 < / _ c >  
 < _ d > 1 7 6 < / _ d >  
 < _ e > 3 2 < / _ e >  
 < _ f > 6 0 < / _ f >  
 < _ g > 8 6 < / _ g >  
 < _ h > 8 6 < / _ h >  
 < _ i > 1 2 1 < / _ i >  
 < _ j > 1 2 < / _ j >  
 < _ k > 1 9 1 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 5 2 3 3 9 6 8 6 8 < / _ a >  
 < _ b > 6 6 0 8 < / _ b >  
 < _ c > 1 6 5 1 0 < / _ c >  
 < _ d > 1 7 5 < / _ d >  
 < _ e > 8 9 < / _ e >  
 < _ f > 1 7 6 < / _ f >  
 < _ g > 1 6 8 < / _ g >  
 < _ h > 2 1 < / _ h >  
 < _ i > 1 5 0 < / _ i >  
 < _ j > 4 < / _ j >  
 < _ k > 4 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 3 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 5 1 1 9 4 6 3 1 6 < / _ a >  
 < _ b > - 3 4 4 7 < / _ b >  
 < _ c > 1 8 5 2 8 < / _ c >  
 < _ d > 1 6 4 < / _ d >  
 < _ e > 1 2 < / _ e >  
 < _ f > 1 7 3 < / _ f >  
 < _ g > 1 2 2 < / _ g >  
 < _ h > 2 3 6 < / _ h >  
 < _ i > 2 4 2 < / _ i >  
 < _ j > 2 0 0 < / _ j >  
 < _ k > 9 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b G r o u p   i d = " r e f - 3 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < T a b s   h r e f = " # r e f - 4 2 " / >  
 < E x t e n t > 4 7 0 < / E x t e n t >  
 < F i r s t D i s p l a y T a b I n d e x > 0 < / F i r s t D i s p l a y T a b I n d e x >  
 < S e l e c t e d T a b I n d e x > 6 < / S e l e c t e d T a b I n d e x >  
 < / a 2 : M d i T a b G r o u p >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 5 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 6 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 4 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 5 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 6 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 6 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 7 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : M a r g i n s   i d = " r e f - 3 7 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < L e f t D e f a u l t > 0 < / L e f t D e f a u l t >  
 < T o p D e f a u l t > 0 < / T o p D e f a u l t >  
 < R i g h t D e f a u l t > 0 < / R i g h t D e f a u l t >  
 < B o t t o m D e f a u l t > 0 < / B o t t o m D e f a u l t >  
 < B o t t o m > 4 < / B o t t o m >  
 < / a 3 : M a r g i n s >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 8 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 8 2 0 8 9 7 0 9 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 8 1 4 2 8 6 7 7 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 9 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 0 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b s C o l l e c t i o n   i d = " r e f - 4 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 7 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 4 8 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 4 9 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 5 0 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 5 1 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 5 2 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 5 3 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 5 4 " / >  
 < / a 2 : M d i T a b s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 6 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 7 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b   i d = " r e f - 4 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 1 0 4 5 4 0 5 2 5 < / _ a >  
 < _ b > - 5 1 3 6 < / _ b >  
 < _ c > 1 6 9 6 3 < / _ c >  
 < _ d > 1 5 7 < / _ d >  
 < _ e > 0 < / _ e >  
 < _ f > 1 5 4 < / _ f >  
 < _ g > 1 8 < / _ g >  
 < _ h > 1 0 1 < / _ h >  
 < _ i > 1 9 4 < / _ i >  
 < _ j > 1 5 5 < / _ j >  
 < _ k > 1 5 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 4 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 5 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 c 9 1 1 9 b 1 - 7 3 0 d - 4 1 9 1 - a 5 8 7 - 8 d 2 b 3 e 7 8 6 e 9 1 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 6 " > F : \ F C B _ p r o j e c t \ t e m p \ M 1 2 \ M 1 2 - 0 5 P \ c o d e \ a p p \ r _ m a i n . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 1 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 7 4 8 7 2 1 7 7 < / _ a >  
 < _ b > - 1 6 5 9 1 < / _ b >  
 < _ c > 1 6 5 5 7 < / _ c >  
 < _ d > 1 2 8 < / _ d >  
 < _ e > 1 6 4 < / _ e >  
 < _ f > 7 2 < / _ f >  
 < _ g > 1 2 < / _ g >  
 < _ h > 1 3 7 < / _ h >  
 < _ i > 8 0 < / _ i >  
 < _ j > 2 1 8 < / _ j >  
 < _ k > 1 3 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 7 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 1 3 4 3 c a 8 - 0 f 7 c - 4 d 7 9 - 9 0 d 3 - a 6 3 c 1 8 1 d 5 e 8 c < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 8 " > F : \ F C B _ p r o j e c t \ t e m p \ M 1 2 \ M 1 2 - 0 5 P \ c o d e \ a p p \ u s e r \ M o t o r C t r l . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 9 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > e 1 2 5 2 7 3 5 - 6 4 f f - 4 1 f a - a 5 e 2 - e 2 b f 4 f 6 3 4 a c e < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 0 " > F : \ F C B _ p r o j e c t \ t e m p \ M 1 2 \ M 1 2 - 0 5 P \ c o d e \ a p p \ r _ c g _ a d c _ u s e r . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 1 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 7 6 3 d 6 7 e 3 - 1 e 2 a - 4 f b 4 - 8 9 9 d - 8 f e 8 e 2 e 1 a 7 e f < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 2 " > F : \ F C B _ p r o j e c t \ t e m p \ M 1 2 \ M 1 2 - 0 5 P \ c o d e \ a p p \ u s e r \ h w C t r l . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 3 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > a 2 9 8 2 4 b d - 2 d 9 5 - 4 6 6 4 - 8 a 9 5 - 2 4 3 0 f 2 a 2 9 0 3 4 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 4 " > F : \ F C B _ p r o j e c t \ t e m p \ M 1 2 \ M 1 2 - 0 5 P \ c o d e \ a p p \ u s e r \ e v e n t . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < / S O A P - E N V : B o d y >  
 < / S O A P - E N V : E n v e l o p e >  
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+ + + + + 12.2.20122.2006 + 9.07.00.06 + + + + + COM1 + 0 + enable + enable + + + + + PanelWatch1 + 0 + 0 + 0 + 0 + 0 + None + + + PanelWatch2 + 0 + 0 + 0 + 0 + 0 + None + + + PanelWatch3 + 0 + 0 + 0 + 0 + 0 + None + + + PanelWatch4 + 0 + 0 + 0 + 0 + 0 + None + + + + + PanelIORegister + 0 + 0 + 0 + 0 + 0 + + + + + PanelCpuRegister + 0 + 0 + 0 + 0 + 0 + + + + + PanelLocalVariable + 0 + 0 + 0 + 0 + 0 + False + Decimal + Decimal + 20127 + + + + + PanelCallStack + Auto + Decimal + 20127 + True + True + 50 + 500 + + + + + PanelTrace + False + False + Decimal + Mixed + + + + + PanelMemory1 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + PanelMemory2 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + PanelMemory3 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + PanelMemory4 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + + + False + False + False + False + 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0:112:112,1:245:245,2:42:42,3:44:44,4:121:121,5:114:114,6:96:85 + 0:112:112,1:77:77,2:77:77,3:216:216,4:61:61,5:40:40,6:50:50,7:160:160,8:210:210,9:219:219,10:210:210,11:100:100 + 0:112:112,1:100:100,2:43:43,3:182:150 + 0:112:112,1:78:78,2:77:77,3:216:216,4:61:61,5:40:40,6:50:50,7:160:160,8:210:210,9:219:219,10:210:210 + True + 0 + + + + + 7d577131-4ec1-4e88-968d-89381f6c178a + + + + + 1.1 + + + False + False + False + True + Yes + Nanosecond + False + False + False + False + False + True + FilesNotToAnalyze + 0 + All + 0 + False + %ProjectName%.mtfl + %ProjectName%.mtvl + 10 + + + RealtimeSampling + + Synchronized + AtProgramStop + 20 + 1000000 + LineChart + False + PaleGreen + PaleTurquoise + 40ff0a4f + 405be416 + 40056def + 40ff541c + False + Auto + Channel01 + 0 + Rising + 0 + Orange + 10 + None + + + + + + + + + + + + + + + + + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + Auto + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 25.5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + c0ff0a4f + c05be416 + c0056dff + c0ff541c + c04fc1ff + c0a932ff + c0ffd91c + c0ff30a5 + c0bee02f + c05510ff + c0ff97e4 + c0913a37 + c0c68e15 + c0317f0c + c060493e + c072808e + + + + + cb4eebec-2381-4e77-8b34-fa8cd6f33b4c + + + + + <RL78G12> + <VAR> + <fCLK Name="fCLK" Value="24" Comment="4M" Trigger="fCLK"> + <Effect> + <ADC /> + <SAU0 /> + <IICA0 /> + <TAU0 /> + </Effect> + </fCLK> + <fIH Name="fIH" Value="24" Comment="32M" /> + <fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"> + <Effect> + <TAU0 /> + <PCLBUZ0 /> + </Effect> + </fSUB> + <fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"> + <Effect> + <RTC /> + <WDT /> + <TAU0 /> + </Effect> + </fIL> + <fRTC Name="fRTC" Value="0" Comment="0k" Trigger="fIT"> + <Effect> + <RTC /> + <IT /> + </Effect> + </fRTC> + <fMAIN Name="fMAIN" Value="24" Comment="32M" Trigger="fMAIN"> + <Effect> + <PCLBUZ0 /> + </Effect> + </fMAIN> + <fINTTM02 Name="fINTTM02" Value="0" Comment="0M" Trigger="INTTM02"> + <Effect> + <SAU0 /> + </Effect> + </fINTTM02> + <fCLKSource Name="fCLKSource" Text="fIH" /> + <RESET_pin Chip="RL78G12_20pin,RL78G12_24pin" Name="RESET_pin" Text="false" Trigger="RESET_pin"> + <Effect> + <PORT /> + </Effect> + </RESET_pin> + <VDD_MIN Name="VDD_MIN" Value="2.7" Comment="4.0V" Trigger="VDD"> + <Effect> + <PCLBUZ0 /> + <PCLBUZ1 /> + <IICA0 /> + <SAU0 /> + <SAU1 /> + </Effect> + </VDD_MIN> + <VDD_MAX Name="VDD_MAX" Value="3.6" Comment="5.5V" /> + <VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"> + <Effect> + <IICA0 /> + <SAU0 /> + <SAU1 /> + <ADC /> + </Effect> + </VDDValue> + <VDD Name="VDD" Text="false" Comment="used" /> + <AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="ANI0,ANI1," /> + <ADC_ADS_VALUE Name="ADC_ADS_VALUE" Text="ANI1," /> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC00> + <IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC01> + <IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC10> + <IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC11> + <IIC20 Name="IIC20" Text="false" Comment="unused" Trigger="IIC20"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC20> + <IIC21 Name="IIC21" Text="false" Comment="unused" Trigger="IIC21"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC21> + <IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IICA0> + <ProjectName Name="PrjName" Text="M12" /> + <ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\M12\M12-05P\code\app" /> + <ProjectKind Name="PrjKind" Text="Project78K0R" /> + <DeviceName Name="DeviceName" Fixed="" Text="RL78G12" /> + <MCUName Name="MCUName" Text="RL78G12_20pin" /> + <ChipName Name="ChipName" Text="R5F10268" /> + <ChipID Name="ChipID" Text="R5F10268" /> + <MCUType Name="MCUType" Fixed="" Text="RL78" /> + <CPUCoreType Name="CPUCoreType" Fixed="" Text="0" /> + <Compiler Name="Compiler" Text="CCRL" /> + <UseSecurityId Name="GI" Text="0" /> + <SecurityId Name="GIValue" Text="00000000000000000000" /> + <LinkDirectiveFile Name="D0" Text="lk.dr" /> + <OnChipDebugOptionBytes Name="GO" Text="1" /> + <OnChipDebugOptionBytesValue Name="GOValue" Text="04" /> + <StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="1E00" /> + <SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /> + <UserOptionBytes Name="GB" Text="1" /> + <UserOptionBytesValue Name="GBValue" Text="7A47E0" /> + <RAMStartAddress Chip="R5F10268,R5F10278,R5F102A8" Name="RAMStartAddress" Fixed="" Text="000FFC00" /> + <RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /> + <ROMEndAddress Chip="R5F10268,R5F10278,R5F102A8" Name="ROMEndAddress" Fixed="" Text="00001FFF" /> + <MirrorROM Chip="R5F10266, R5F10366,R5F10267, R5F10277, R5F102A7,R5F10367, R5F10377, R5F103A7,R5F10268, R5F10278, R5F102A8,R5F10368, R5F10378, R5F103A8" Name="MirrorROM" Fixed="" Text="0" /> + <ADPC_AD Name="ADPC_AD" Value="1" /> + <CodePath Name="CodePath" Text=".\" /> + <ReportType Name="ReportType" Text="Html" /> + <CreationDateType Name="CreationDateType" Text="OutputDate" /> + <GenerateType Name="GenerateType" Text="Merge" /> + <APIOutputType Name="APIOutputType" Text="Default" /> + <FileRegister Name="FileRegister" Text="Yes" /> + <PinReflect Name="PinReflect" Text="Reflected" /> + <PIOR0Value Name="PIOR0Value" Text="0" /> + <PIOR1Value Name="PIOR1Value" Text="1" /> + <PIOR2Value Name="PIOR2Value" Text="0" /> + <PIOR3Value Name="PIOR3Value" Text="0" /> + <PIOR4Value Name="PIOR4Value" Text="0" /> + <PIOR5Value Name="PIOR5Value" Text="0" /> + <GDataFlash Name="GDataFlash" Text="2" /> + <UseFDL Name="UseFDL" Text="no" /> + <DataFlash Name="DataFlash" Text="0" /> + <OCDROM Name="OCDROM" Text="Unused" /> + <OCDROM_Address Name="OCDROM_Address" Text="00001E00" /> + <OCDROM_Length Name="OCDROM_Length" Text="512" /> + <HasRRMRam Name="HasRRMRam" Text="" /> + <PrjVersion Name="PrjVersion" Text="1.2.0.1" /> + <ProductVersion Name="ProductVersion" Text="4.08.05.01" /> + <PIOR6Value Name="PIOR6Value" Text="0" /> + <TO02_PWM Name="TO02_PWM" Text="false" /> + <TO03_PWM Name="TO03_PWM" Text="false" /> + <LinkFileName Name="LinkFileName" Text="" /> + </VAR> + <DIR> + <PIN> + <CGC> + <X1 Port="P121" Point="-" /> + <X2 Port="P122" Point="-" /> + <EXCLK Port="P122" Point="I" /> + <TOOL0 Port="P40" Point="I/O" /> + <_RESET Chip="RL78G12_20pin,RL78G12_24pin" Port="P125" RealName="_RESET" Point="I" /> + </CGC> + <PORT> + <Port1 Chip="RL78G12_20pin,RL78G12_24pin" DIN="true" Pullup="true"> + <P10 Name="P10/ANI16/PCLBUZ0/_SCK00/SCL00" TTL="true" Nch="true" AltFunc="P10" Point="I/O" /> + <P11 Name="P11/ANI17/SI00/RXD0/SDA00/TOOLRXD" TTL="true" Nch="true" AltFunc="P11" Point="I/O" /> + <P12 Name="P12/ANI18/SO00/TXD0/TOOLTXD" Nch="true" AltFunc="P12" Point="I/O" /> + <P13 Name="P13/ANI19/TI00/TO00/INTP2" AltFunc="P13" Point="I/O" /> + <P14 Name="P14/ANI20/TI01/TO01/INTP3" AltFunc="P14" Point="I/O" /> + </Port1> + <Port2 ADIN="true"> + <P20 Name="P20/ANI0/AVREFP" AltFunc="ANALOG_0" Point="I/O" /> + <P21 Name="P21/ANI1/AVREFM" AltFunc="ANI1" Point="I/O" /> + <P22 Name="P22/ANI2" AltFunc="" Point="I/O" /> + <P23 Name="P23/ANI3" AltFunc="P23" Point="I/O" /> + </Port2> + <Port4 Chip="RL78G12_20pin,RL78G12_24pin" Pullup="true"> + <P40 Name="P40/KR0/TOOL0" AltFunc="" Point="I/O" /> + <P41 Name="P41/ANI22/SO01/SDA01/TI02/TO02/INTP1" DIN="true" Nch="true" AltFunc="" Point="I/O" /> + <P42 Name="P42/ANI21/_SCK01/SCL01/TI03/TO03" DIN="true" AltFunc="" Point="I/O" /> + </Port4> + <Port6 Chip="RL78G12_20pin,RL78G12_24pin"> + <P60 Name="P60/KR4/SCLA0" AltFunc="" Point="I/O" /> + <P61 Name="P61/KR5/SDAA0" AltFunc="" Point="I/O" /> + </Port6> + <Port12 Chip="RL78G12_20pin,RL78G12_24pin"> + <P121 Name="P121/KR3/X1" AltFunc="" Point="I" /> + <P122 Name="P122/KR2/X2/EXCLK" AltFunc="" Point="I" /> + <P125 Name="P125/KR1/SI01/_RESET" Pullup="true" AltFunc="" Point="I" /> + </Port12> + <Port13> + <P137 Name="P137/INTP0" AltFunc="" Point="I" /> + </Port13> + </PORT> + <INTC> + <INTP> + <INTP0 no="1" Point="I" /> + <INTP1 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /> + <INTP2 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P13" Point="I" /> + <INTP3 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P14" Point="I" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <KR0 Port="P40" Point="I" /> + <KR1 Port="P125" Point="I" /> + <KR2 Port="P122" Point="I" /> + <KR3 Port="P121" Point="I" /> + <KR4 Port="P60" Point="I" /> + <KR5 Port="P61" Point="I" /> + </KEY> + </INTC> + <ADC> + <ANI0 Port="P20" Point="I" /> + <ANI1 Port="P21" Point="I" /> + <ANI2 Port="P22" Point="I" /> + <ANI3 Port="P23" Point="I" /> + <ANI16 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="I" /> + <ANI17 Chip="RL78G12_20pin,RL78G12_24pin" Port="P11" Point="I" /> + <ANI18 Chip="RL78G12_20pin,RL78G12_24pin" Port="P12" Point="I" /> + <ANI19 Chip="RL78G12_20pin,RL78G12_24pin" Port="P13" Point="I" /> + <ANI20 Chip="RL78G12_20pin,RL78G12_24pin" Port="P14" Point="I" /> + <ANI21 Chip="RL78G12_20pin,RL78G12_24pin" Port="P42" Point="I" /> + <ANI22 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /> + <AVREFP Port="P20" Point="I" /> + <AVREFM Port="P21" Point="I" /> + <ANALOG_0 Port="P20" RealName="ANI0/AVREFP" Point="I" /> + <ANALOG_1 Port="P21" RealName="ANI1/AVREFM" Point="I" /> + <ANALOG_2 Port="P22" RealName="ANI2" Point="I" /> + <ANALOG_3 Port="P23" RealName="ANI3" Point="I" /> + </ADC> + <Serial> + <SAU0> + <UART0> + <RXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P61" RealName="RxD0" Point="I" /> + <TXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P60" RealName="TxD0" Point="O" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin"> + <SO00 Port="P12" Point="O" /> + <SI00 Port="P11" Point="I" /> + <SCK00 Port="P10" RealName="_SCK00" Point="I/O" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin"> + <SO01 Port="P41" Point="O" /> + <SI01 Port="P125" Point="I" /> + <SCK01 Port="P42" RealName="_SCK01" Point="I/O" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin"> + <SCL00 Port="P10" Point="I/O" CheckNch="true" /> + <SDA00 Port="P11" Point="I/O" CheckNch="true" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin"> + <SCL01 Port="P42" Point="I/O" CheckNch="true" /> + <SDA01 Port="P41" Point="I/O" CheckNch="true" /> + </IIC01> + </SAU0> + <IICA0> + <SCLA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P60" Point="I/O" /> + <SDAA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P61" Point="I/O" /> + </IICA0> + </Serial> + <TAU> + <TAU0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR2="0"> + <Channel0> + <TI00 Port="P13" Point="I" /> + <TO00 Port="P13" Point="O" /> + </Channel0> + <Channel1> + <TI01 Port="P14" Point="I" /> + <TO01 Port="P14" Point="O" /> + </Channel1> + <Channel2> + <TI02 Port="P41" Point="I" /> + <TO02 Port="P41" Point="O" /> + </Channel2> + <Channel3> + <TI03 Port="P42" Point="I" /> + <TO03 Port="P42" Point="O" /> + </Channel3> + </TAU0> + </TAU> + <PCLBUZ> + <PCLBUZ0> + <PCLBUZ0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="O" /> + </PCLBUZ0> + </PCLBUZ> + <Others> + <VDD AltFunc="VDD" Point="-" /> + <VSS AltFunc="VSS" Point="-" /> + </Others> + </PIN> + <INT> + <INTC> + <INTP> + <INTP0 InUse="0" ISR="r_intc0_interrupt" /> + <INTP1 InUse="0" ISR="r_intc1_interrupt" /> + <INTP2 InUse="0" ISR="r_intc2_interrupt" /> + <INTP3 InUse="0" ISR="r_intc3_interrupt" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <INTKR InUse="0" ISR="r_key_interrupt" /> + </KEY> + </INTC> + <Serial> + <SAU0> + <INTCSI00 InUse="0" ISR="r_csi00_interrupt" /> + <INTCSI01 InUse="0" ISR="r_csi01_interrupt" /> + <INTCSI10 InUse="0" ISR="r_csi10_interrupt" /> + <INTCSI11 InUse="0" ISR="r_csi11_interrupt" /> + <INTST0 InUse="0" ISR="r_uart0_interrupt_send" /> + <INTST1 InUse="0" ISR="r_uart1_interrupt_send" /> + <INTSRE0 InUse="0" ISR="r_uart0_interrupt_error" /> + <INTSRE1 InUse="0" ISR="r_uart1_interrupt_error" /> + <INTSR0 InUse="0" ISR="r_uart0_interrupt_receive" /> + <INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /> + <INTIIC00 InUse="0" ISR="r_iic00_interrupt" /> + <INTIIC01 InUse="0" ISR="r_iic01_interrupt" /> + <INTIIC10 InUse="0" ISR="r_iic10_interrupt" /> + <INTIIC11 InUse="0" ISR="r_iic11_interrupt" /> + </SAU0> + <SAU1> + <INTCSI20 InUse="0" ISR="r_csi20_interrupt" /> + <INTCSI21 InUse="0" ISR="r_csi21_interrupt" /> + <INTCSI30 InUse="0" ISR="r_csi30_interrupt" /> + <INTCSI31 InUse="0" ISR="r_csi31_interrupt" /> + <INTST2 InUse="0" ISR="r_uart2_interrupt_send" /> + <INTST3 InUse="0" ISR="r_uart3_interrupt_send" /> + <INTSRE2 InUse="0" ISR="r_uart2_interrupt_error" /> + <INTSRE3 InUse="0" ISR="r_uart3_interrupt_error" /> + <INTSR2 InUse="0" ISR="r_uart2_interrupt_receive" /> + <INTSR3 InUse="0" ISR="r_uart3_interrupt_receive" /> + <INTIIC20 InUse="0" ISR="r_iic20_interrupt" /> + <INTIIC21 InUse="0" ISR="r_iic21_interrupt" /> + <INTIIC30 InUse="0" ISR="r_iic30_interrupt" /> + <INTIIC31 InUse="0" ISR="r_iic31_interrupt" /> + </SAU1> + <IICA0> + <INTIICA0 InUse="0" ISR="r_iica0_interrupt" /> + </IICA0> + </Serial> + <ADC> + <INTAD InUse="1" ISR="r_adc_interrupt" IsDMATrigger="true" /> + </ADC> + <TAU> + <TAU0> + <Channel0> + <INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM01 InUse="1" ISR="r_tau0_channel1_interrupt" /> + <INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /> + <INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /> + </Channel7> + </TAU0> + </TAU> + <IT> + <INTIT InUse="0" ISR="r_it_interrupt" /> + </IT> + <DMAC> + <DMA0> + <INTDMA0 InUse="0" ISR="r_dmac0_interrupt" /> + </DMA0> + <DMA1> + <INTDMA1 InUse="0" ISR="r_dmac1_interrupt" /> + </DMA1> + </DMAC> + <WDT> + <INTWDTI InUse="0" ISR="r_wdt_interrupt" /> + </WDT> + <LVD> + <INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /> + </LVD> + </INT> + <FUNC> + <Common> + <r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"> + <Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /> + <main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /> + <R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /> + </r_main.c> + <r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /> + <R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /> + <hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /> + <__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /> + </r_systeminit.c> + <r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /> + <R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /> + <HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /> + </r_hardware_setup.c> + <r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"> + <Type R_Dummy="void R_Dummy(void)" /> + <R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /> + </r_cg_vector_table.c> + <r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /> + <r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /> + <r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /> + <r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /> + <r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /> + <r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /> + <iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /> + </Common> + <CGC> + <r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"> + <Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(clock_mode_t mode)" /> + <R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /> + <R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /> + </r_cg_cgc.c> + <r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"> + <Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" /> + <R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /> + <R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /> + </r_cg_cgc_user.c> + <r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /> + <r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"> + <Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /> + <R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /> + <R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /> + <R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /> + <R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /> + <R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /> + <R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /> + <R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /> + <R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /> + </r_cg_pfdl.c> + <r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /> + </CGC> + <PORT> + <r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"> + <Type R_PORT_Create="void R_PORT_Create(void)" /> + <R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /> + </r_cg_port.c> + <r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"> + <Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /> + <R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /> + </r_cg_port_user.c> + <r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /> + </PORT> + <INTC> + <r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse="0"> + <Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /> + <INTP> + <R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="0" Init="2" InitMode="" /> + <INTP0> + <R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP0> + <INTP1> + <R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP1> + <INTP2> + <R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP2> + <INTP3> + <R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP3> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /> + <R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /> + <R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /> + </KEY> + </r_cg_intc.c> + <r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse="0"> + <Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" R_INTC0_Interrupt="__interrupt static void r_intc0_interrupt(void)" R_INTC1_Interrupt="__interrupt static void r_intc1_interrupt(void)" R_INTC2_Interrupt="__interrupt static void r_intc2_interrupt(void)" R_INTC3_Interrupt="__interrupt static void r_intc3_interrupt(void)" R_INTC4_Interrupt="__interrupt static void r_intc4_interrupt(void)" R_INTC5_Interrupt="__interrupt static void r_intc5_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" R_KEY_Interrupt="__interrupt static void r_key_interrupt(void)" /> + <INTP> + <R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="0" /> + <r_intc0_interrupt UserName="r_intc0_interrupt" LibName="R_INTC0_Interrupt" INTHandle="" InUse="0" /> + <r_intc1_interrupt UserName="r_intc1_interrupt" LibName="R_INTC1_Interrupt" INTHandle="" InUse="0" /> + <r_intc2_interrupt UserName="r_intc2_interrupt" LibName="R_INTC2_Interrupt" INTHandle="" InUse="0" /> + <r_intc3_interrupt UserName="r_intc3_interrupt" LibName="R_INTC3_Interrupt" INTHandle="" InUse="0" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /> + <r_key_interrupt UserName="r_key_interrupt" LibName="R_KEY_Interrupt" INTHandle="" InUse="" /> + </KEY> + </r_cg_intc_user.c> + <r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="0" /> + </INTC> + <Serial> + <r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="0"> + <Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t * const rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t * const tx_buf, uint16_t tx_num, uint8_t * const rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" IICn_Init="void IICn_Init(void)" IICn_MasterSendStart="MD_STATUS IICn_MasterSendStart(uint8_t adr, uint8_t * const tx_buf, USHORT tx_num, uint8_t wait)" IICn_MasterReceiveStart="MD_STATUS IICn_MasterReceiveStart(uint8_t adr, uint8_t * const rx_buf, USHORT rx_num, uint8_t wait)" IICn_SlaveSendStart="void IICn_SlaveSendStart(uint8_t * const tx_buf, USHORT tx_num)" IICn_SlaveReceiveStart="void IICn_SlaveReceiveStart(uint8_t * const rx_buf, USHORT rx_num)" IICn_Stop="void IICn_Stop(void)" IICn_StopCondition="void IICn_StopCondition(void)" IICn_PowerOff="void IICn_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="0" Init="1" InitMode="" /> + <R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /> + <R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /> + <R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /> + <UART0 InUse=""> + <R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="0" InitMode="" /> + <R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="0" /> + <R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="0" /> + <R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="0" /> + <R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="0" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC01> + </SAU0> + <IICA0 InUse=""> + <R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /> + <R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /> + <R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /> + <R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /> + <R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /> + <R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /> + <R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /> + <R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /> + <R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /> + <R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /> + </IICA0> + </r_cg_serial.c> + <r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="0"> + <Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" R_UARTn_Interrupt_Receive="__interrupt static void R_UARTn_Interrupt_Receive(void)" R_UARTn_Interrupt_Error="__interrupt static void R_UARTn_Interrupt_Error(void)" R_UARTn_Interrupt_Send="__interrupt static void R_UARTn_Interrupt_Send(void)" R_UARTn_Callback_SendEnd="static void R_UARTn_Callback_SendEnd(void)" R_UARTn_Callback_ReceiveEnd="static void R_UARTn_Callback_ReceiveEnd(void)" R_UARTn_Callback_Error="static void R_UARTn_Callback_Error(uint8_t err_type)" R_UARTn_Callback_SoftwareOverRun="static void R_UARTn_Callback_SoftwareOverRun(uint16_t rx_data)" R_CSIn_Interrupt="__interrupt static void R_CSIn_Interrupt(void)" R_CSIn_Callback_ReceiveEnd="static void R_CSIn_Callback_ReceiveEnd(void)" R_CSIn_Callback_Error="static void R_CSIn_Callback_Error(uint8_t err_type)" R_CSIn_Callback_SendEnd="static void R_CSIn_Callback_SendEnd(void)" R_IICn_Interrupt="__interrupt static void R_IICn_Interrupt(void)" R_IICn_Callback_Master_ReceiveEnd="static void R_IICn_Callback_Master_ReceiveEnd(void)" R_IICn_Callback_Master_SendEnd="static void R_IICn_Callback_Master_SendEnd(void)" R_IICn_Callback_Master_Error="static void R_IICn_Callback_Master_Error(MD_STATUS flag)" IICn_MasterSendEndCallback="static void IICn_MasterSendEndCallback(void)" IICn_MasterReceiveEndCallback="static void IICn_MasterReceiveEndCallback(void)" IICn_MasterErrorCallback="static void IICn_MasterErrorCallback(MD_STATUS flag)" IICn_SlaveErrorCallback="static void IICn_SlaveErrorCallback(MD_STATUS flag)" IICn_GetStopConditionCallback="static void IICn_GetStopConditionCallback(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static void r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /> + <UART0 InUse=""> + <r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="R_UARTn_Interrupt_Receive" InUse="0" /> + <r_uart0_interrupt_error UserName="r_uart0_interrupt_error" INTHandle="" LibName="R_UARTn_Interrupt_Error" InUse="0" /> + <r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="R_UARTn_Interrupt_Send" InUse="0" /> + <r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="R_UARTn_Callback_ReceiveEnd" InUse="0" /> + <r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="R_UARTn_Callback_SendEnd" InUse="0" /> + <r_uart0_callback_error UserName="r_uart0_callback_error" LibName="R_UARTn_Callback_Error" InUse="0" /> + <r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="R_UARTn_Callback_SoftwareOverRun" InUse="0" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /> + <r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /> + <r_csi00_callback_error UserName="r_csi00_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /> + <r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /> + <r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /> + <r_csi01_callback_error UserName="r_csi01_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /> + <r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /> + <r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /> + <r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /> + <r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /> + <r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /> + <r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /> + <r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /> + </IIC01> + </SAU0> + <IICA0 InUse=""> + <R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /> + <r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /> + <r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /> + <r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /> + <r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /> + <r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /> + <r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /> + <r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /> + <r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /> + </IICA0> + </r_cg_serial_user.c> + <r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="0" /> + </Serial> + <ADC> + <r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="1"> + <Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /> + <R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="1" Init="1" InitMode="" /> + <R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="1" /> + <R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="1" /> + <R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="1" /> + <R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="1" /> + <R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="1" /> + <R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /> + <R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /> + <R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /> + <R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /> + <R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /> + <R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /> + </r_cg_adc.c> + <r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="1"> + <Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /> + <R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /> + <r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="1" /> + </r_cg_adc_user.c> + <r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="1" /> + </ADC> + <TAU> + <r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"> + <Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" /> + <TAU0> + <R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /> + <R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel0_Get_PulseWidth UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel2_Get_PulseWidth UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Get_PulseWidth UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + </TAU0> + </r_cg_timer.c> + <r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"> + <Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" /> + <TAU0> + <R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + </Channel0> + <Channel1 InUse=""> + <r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + <r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + </TAU0> + </r_cg_timer_user.c> + <r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /> + </TAU> + <WDT> + <r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"> + <Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /> + <R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /> + <R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /> + </r_cg_wdt.c> + <r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"> + <Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /> + <R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /> + <r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="0" /> + </r_cg_wdt_user.c> + <r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /> + </WDT> + <IT> + <r_cg_it.c UserName="r_cg_it.c" LibName=".c" InUse=""> + <Type R_IT_Create="void R_IT_Create(void)" R_IT_Start="void R_IT_Start(void)" R_IT_Stop="void R_IT_Stop(void)" R_IT_Set_PowerOff="void R_IT_Set_PowerOff(void)" /> + <R_IT_Create UserName="R_IT_Create" LibName="R_IT_Create" InUse="" Init="1" InitMode="" /> + <R_IT_Start UserName="R_IT_Start" LibName="R_IT_Start" InUse="" /> + <R_IT_Stop UserName="R_IT_Stop" LibName="R_IT_Stop" InUse="" /> + <R_IT_Set_PowerOff UserName="R_IT_Set_PowerOff" LibName="R_IT_Set_PowerOff" InUse="" /> + </r_cg_it.c> + <r_cg_it_user.c UserName="r_cg_it_user.c" LibName="_user.c" InUse=""> + <Type R_IT_Create_UserInit="void R_IT_Create_UserInit(void)" r_it_interrupt="__interrupt static void r_it_interrupt(void)" /> + <R_IT_Create_UserInit UserName="R_IT_Create_UserInit" LibName="R_IT_Create_UserInit" InUse="" /> + <r_it_interrupt UserName="r_it_interrupt" INTHandle="" LibName="r_it_interrupt" InUse="" /> + </r_cg_it_user.c> + <r_cg_it.h UserName="r_cg_it.h" LibName=".h" InUse="" /> + </IT> + <PCLBUZ> + <r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse=""> + <Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="" Init="1" InitMode="" /> + <R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="" /> + <R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="" /> + </PCLBUZ0> + </r_cg_pclbuz.c> + <r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse=""> + <Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="" Init="1" /> + </PCLBUZ0> + </r_cg_pclbuz_user.c> + <r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="" /> + </PCLBUZ> + <DMAC> + <r_cg_dmac.c UserName="r_cg_dmac.c" LibName=".c" InUse=""> + <Type R_DMACn_Create="void R_DMACn_Create(void)" R_DMACn_Start="void R_DMACn_Start(void)" R_DMACn_Stop="void R_DMACn_Stop(void)" R_DMACn_Set_SoftwareTriggerOn="void R_DMACn_Set_SoftwareTriggerOn(void)" /> + <DMA0 InUse=""> + <R_DMAC0_Create UserName="R_DMAC0_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /> + <R_DMAC0_Start UserName="R_DMAC0_Start" LibName="R_DMACn_Start" InUse="" /> + <R_DMAC0_Stop UserName="R_DMAC0_Stop" LibName="R_DMACn_Stop" InUse="" /> + <R_DMAC0_Set_SoftwareTriggerOn UserName="R_DMAC0_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /> + </DMA0> + <DMA1 InUse=""> + <R_DMAC1_Create UserName="R_DMAC1_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /> + <R_DMAC1_Start UserName="R_DMAC1_Start" LibName="R_DMACn_Start" InUse="" /> + <R_DMAC1_Stop UserName="R_DMAC1_Stop" LibName="R_DMACn_Stop" InUse="" /> + <R_DMAC1_Set_SoftwareTriggerOn UserName="R_DMAC1_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /> + </DMA1> + </r_cg_dmac.c> + <r_cg_dmac_user.c UserName="r_cg_dmac_user.c" LibName="_user.c" InUse=""> + <Type R_DMACn_Create_UserInit="void R_DMACn_Create_UserInit(void)" r_dmacn_interrupt="__interrupt static void r_dmacn_interrupt(void)" /> + <DMA0> + <R_DMAC0_Create_UserInit UserName="R_DMAC0_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /> + <r_dmac0_interrupt UserName="r_dmac0_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /> + </DMA0> + <DMA1> + <R_DMAC1_Create_UserInit UserName="R_DMAC1_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /> + <r_dmac1_interrupt UserName="r_dmac1_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /> + </DMA1> + </r_cg_dmac_user.c> + <r_cg_dmac.h UserName="r_cg_dmac.h" LibName=".h" InUse="" /> + </DMAC> + <LVD> + <r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"> + <Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /> + <R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /> + <R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /> + </r_cg_lvd.c> + <r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"> + <Type R_LVD_Creat_UserInit="void R_LVD_Creat_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /> + <R_LVD_Creat_UserInit UserName="R_LVD_Creat_UserInit" LibName="R_LVD_Creat_UserInit" InUse="0" /> + <r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /> + </r_cg_lvd_user.c> + <r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /> + </LVD> + </FUNC> + <TAG> + <GlobleUserTag> + <cg_security9 Name="cg_security9" Value="00" /> + <cg_security7 Name="cg_security7" Value="00" /> + <cg_security5 Name="cg_security5" Value="00" /> + <ocdstart Name="ocdstart" Value="01E00" /> + <cg_security3 Name="cg_security3" Value="00" /> + <cg_security0 Name="cg_security0" Value="00" /> + <cg_security1 Name="cg_security1" Value="00" /> + <clock_option Name="clock_option" Value="E0" /> + <pior_value Name="pior_value" Value="02" /> + <cg_option Name="cg_option" Value="04" /> + <cg_security8 Name="cg_security8" Value="00" /> + <cg_security6 Name="cg_security6" Value="00" /> + <cg_security4 Name="cg_security4" Value="00" /> + <cg_security2 Name="cg_security2" Value="00" /> + <cg_iawctl_value Name="cg_iawctl_value" Value="00" /> + <lvi_option Name="lvi_option" Value="47" /> + <wdt_option Name="wdt_option" Value="7A" /> + </GlobleUserTag> + </TAG> + </DIR> + <MACRO> + <CGC HelpID="CGC" Prepared="true" SetFlag="True" NeedRefresh="False"> + <CGC SetFlag="True" MacroName="cgc" /> + </CGC> + <PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"> + <PORT SetFlag="True" MacroName="PORT" /> + </PORT> + <INTC SetFlag="False" HelpID="int" NeedRefresh="False"> + <INTP Accelerate="No" MacroName="INTP" SetFlag="False" TabEnable="True" /> + <KEY Chip="RL78G12_20pin,RL78G12_24pin," MacroName="KEY" TabEnable="True" /> + </INTC> + <Serial SetFlag="False" HelpID="serial" NeedRefresh="False"> + <SAU0 Chip="RL78G12_20pin,RL78G12_24pin" Accelerate="No" MacroName="SAU" Channel="0" SetFlag="False" TabEnable="True"> + <Channel0 UART="0" CSI="00" IIC="00" Channel="0" /> + <Channel1 UART="0" CSI="01" IIC="01" Channel="1" /> + </SAU0> + <IICA0 Accelerate="No" MacroName="IICA" Channel="0" TabEnable="True" /> + </Serial> + <ADC SetFlag="True" HelpID="adc" NeedRefresh="False"> + <ADC SetFlag="True" MacroName="ADC" /> + </ADC> + <TAU SetFlag="True" HelpID="timer" NeedRefresh="False"> + <TAU0 Accelerate="No" Chip="RL78G12_20pin,RL78G12_24pin" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3" SetFlag="True" /> + </TAU> + <WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"> + <WDT SetFlag="True" MacroName="WDT" /> + </WDT> + <IT SetFlag="" HelpID="intervaltimer" NeedRefresh="False"> + <IT MacroName="IntervalTM" /> + </IT> + <PCLBUZ SetFlag="" HelpID="PCLBUZ" NeedRefresh="False"> + <PCLBUZ0 MacroName="PCLBUZ" Channel="0" /> + </PCLBUZ> + <DMAC HelpID="dmac" SetFlag="" NeedRefresh="False"> + <DMA0 MacroName="DMAC" Channel="0" TabEnable="True" /> + <DMA1 MacroName="DMAC" Channel="1" TabEnable="True" /> + </DMAC> + <LVD SetFlag="True" Prepared="true" HelpID="lvi" NeedRefresh="False"> + <LVD MacroName="LVD" SetFlag="True" /> + </LVD> + </MACRO> + <SETTING> + <CGC> + <setting name="PIOR_Setting" value="FIX" /> + <setting name="PIOR6" value="1" /> + <setting name="PIOR5" value="1" /> + <setting name="PIOR4" value="1" /> + <setting name="PIOR3" value="1" /> + <setting name="PIOR2" value="1" /> + <setting name="PIOR1" value="0" /> + <setting name="PIOR0" value="1" /> + <setting name="PIOR10" value="1" /> + <setting name="PIOR11" value="1" /> + <setting name="PIOR12" value="1" /> + <setting name="PIOR13" value="1" /> + <setting name="VDD" value="VDD0" /> + <setting name="EVDD" value="EVDD2" /> + <setting name="Main_system_clock" value="high-speed internal clock" /> + <setting name="High_speed_internal_oscillator" value="operation" /> + <setting name="High_speed_internal_frequency" value="8" /> + <setting name="High_speed_system_clock" value="stop" /> + <setting name="High_speed_system_input" value="external" /> + <setting name="HighSpeedSystemStable" value="7" /> + <setting name="High_speed_system_clock_frequency" value="5" /> + <setting name="Sub_clock_operation" value="XT1" /> + <setting name="SubclockFrequency" value="32.768" /> + <setting name="XT1_oscillator_oscillation_mode" value="0" /> + <setting name="SubClock" value="unused" /> + <setting name="Subclock_in_halt" value="0" /> + <setting name="CPU_clock" value="0" /> + <setting name="Internal_low-speed_clock" value="15" /> + <setting name="RTC_clcok_selection" value="0" /> + <setting name="RESET_PIN_USED" value="false" /> + <setting name="RESET_PIN_UNUSED" value="true" /> + <setting name="On_chip_debug" value="unused" /> + <setting name="RRM" value="used" /> + <setting name="Trace" value="Used" /> + <setting name="Erase_flash_memory" value="yes" /> + <setting name="Security_ID_setting" value="used" /> + <setting name="Security_ID" value="0x00000000000000000000" /> + <setting name="CG_ReadResetSource" value="generated" /> + <setting name="Accessoperation" value="unused" /> + <setting name="RAMoperation" value="unused" /> + <setting name="RAMArea" value="0" /> + <setting name="PORToperation" value="unused" /> + <setting name="INToperation" value="unused" /> + <setting name="CHIPoperation" value="unused" /> + <setting name="DataFlash" value="unused" /> + <setting name="ProgramFlash" value="unused" /> + <setting name="Monitor" value="unused" /> + <setting name="StartStop" value="unused" /> + <setting name="Emulator" value="E1" /> + </CGC> + <PORT> + <PortP1> + <P10> + <setting name="Operation" value="input" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P10> + <P11> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P11> + <P12> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P12> + <P13> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P13> + <P14> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P14> + </PortP1> + <PortP2> + <P20> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P20> + <P21> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P21> + <P22> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P22> + <P23> + <setting name="Operation" value="input" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P23> + </PortP2> + <PortP4> + <P40> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P40> + <P41> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P41> + <P42> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P42> + </PortP4> + <PortP6> + <P60> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P60> + <P61> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P61> + </PortP6> + <PortP12> + <P121> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P121> + <P122> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P122> + <P125> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="used" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P125> + </PortP12> + <PortP13> + <P137> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P137> + </PortP13> + </PORT> + <ADC> + <setting name="AD_convertion" value="used" /> + <setting name="Comparator_operation" value="enable" /> + <setting name="Resolution" value="10bit" /> + <setting name="AD_Positive" value="VDD" /> + <setting name="AD_Negative" value="VSS" /> + <setting name="AD_Trigger" value="hardtrinowait" /> + <setting name="AD_Trigger_Timer" value="0" /> + <setting name="Mode" value="ONESELECT" /> + <setting name="InputPins" value="1" /> + <setting name="InputPinsAttach" value="ANI0 - ANI1" /> + <setting name="AD_Inputpin16" value="unused" /> + <setting name="AD_Inputpin17" value="unused" /> + <setting name="AD_Inputpin18" value="unused" /> + <setting name="AD_Inputpin19" value="unused" /> + <setting name="AD_Inputpin20" value="unused" /> + <setting name="AD_Inputpin21" value="unused" /> + <setting name="AD_Inputpin22" value="unused" /> + <setting name="AD_Inputpin23" value="unused" /> + <setting name="AD_Inputpin24" value="unused" /> + <setting name="AD_Inputpin25" value="unused" /> + <setting name="AD_Inputpin26" value="unused" /> + <setting name="SelectedChannel" value="1" /> + <setting name="SelectedChannelAttach" value="ANI1" /> + <setting name="ConvTimeMode" value="0" /> + <setting name="ConversionTime" value="0" /> + <setting name="AREAFunction" value="AREA1" /> + <setting name="AREAValue_ADUL" value="255" /> + <setting name="AREAValue_ADLL" value="0" /> + <setting name="Interrput_priority" value="3" /> + <setting name="AD_interrupt" value="used" /> + </ADC> + <TAU0> + <Channel0> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval0> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="-1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="-1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="unused" /> + </TAUInterval0> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval1> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="used" /> + </TAUInterval1> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + </TAU0> + <WDT> + <setting name="Operation" value="used" /> + <setting name="Overflow_time" value="5" /> + <setting name="Window_opening_time" value="0" /> + <setting name="Standby_operation" value="stop" /> + <setting name="Interval_interrupt" value="not use" /> + <setting name="Interval_interrupt_priority" value="3" /> + </WDT> + <LVD> + <setting name="Operation" value="used" /> + <setting name="Reset_only_level" value="5" /> + <setting name="InterruptReset_level" value="0" /> + <setting name="Interrupt_level" value="0" /> + <setting name="Interrupt_only_level" value="0" /> + <setting name="operation_mode" value="reset" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="Interrupt_only_priority" value="3" /> + </LVD> + <SAU0> + <IIC00 /> + <CSI00 /> + <UART0 /> + <Channel0> + <setting name="Channel_function_-i" value="0" /> + <setting name="Detail_function_-i" value="-1" /> + <Transmit_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="none" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="none" /> + <setting name="Transmit_stop_length" value="1 bit" /> + <setting name="TranBaudrate" value="115200" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Transmit_UART0> + <Receive_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="none" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="none" /> + <setting name="Transmit_stop_length" value="1 bit" /> + <setting name="TranBaudrate" value="9600" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Receive_UART0> + <Both_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="odd" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="odd" /> + <setting name="Transmit_stop_length" value="2 bits" /> + <setting name="TranBaudrate" value="9600" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Both_UART0> + </Channel0> + <IIC01 /> + <CSI01 /> + <Channel1> + <setting name="Channel_function_-i" value="0" /> + <setting name="Detail_function_-i" value="-1" /> + </Channel1> + </SAU0> + <IICA0> + <setting name="Mode" value="Unused" /> + </IICA0> + <INTP> + <INTP0> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP0> + <INTP1> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP1> + <INTP2> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP2> + <INTP3> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP3> + </INTP> + <KEY> + <setting name="Interrupt_priority" value="3" /> + <setting name="KR0" value="unused" /> + <setting name="KR1" value="unused" /> + <setting name="KR2" value="unused" /> + <setting name="KR3" value="unused" /> + <setting name="KR4" value="unused" /> + <setting name="KR5" value="unused" /> + <setting name="KR6" value="unused" /> + <setting name="KR7" value="unused" /> + <setting name="KR8" value="unused" /> + <setting name="KR9" value="unused" /> + <setting name="EdgeSelection" value="0" /> + <setting name="FlagUse" value="0" /> + </KEY> + </SETTING> +</RL78G12> + 1.0 + 6c6bb60a-ffe1-4884-8dec-f255a2e58155 + b8348788-df17-4b71-a9fa-eab0f1824fb1 + + + + + 9.07.00.00 + + + \ No newline at end of file diff --git a/app/M12.rcpe b/app/M12.rcpe new file mode 100644 index 0000000..8c06c6d --- /dev/null +++ b/app/M12.rcpe @@ -0,0 +1,1410 @@ + + + + + % + % + + + + cstart.asm + stkinit.asm + iodefine.h + + r_main.c + r_systeminit.c + r_cg_cgc.c + r_cg_cgc_user.c + r_cg_port.c + r_cg_port_user.c + r_cg_adc.c + r_cg_adc_user.c + r_cg_timer.c + r_cg_timer_user.c + r_cg_wdt.c + r_cg_wdt_user.c + r_cg_macrodriver.h + r_cg_userdefine.h + r_cg_cgc.h + r_cg_port.h + r_cg_adc.h + r_cg_timer.h + r_cg_wdt.h + + user\appTask.c + user\event.c + user\hwCtrl.c + user\MotorCtrl.c + + + Simulator + + 4000000 + + + + R5F10268 + + + + DefaultBuild\cstart.obj + DefaultBuild\stkinit.obj + DefaultBuild\r_main.obj + DefaultBuild\r_systeminit.obj + DefaultBuild\r_cg_cgc.obj + DefaultBuild\r_cg_cgc_user.obj + DefaultBuild\r_cg_port.obj + DefaultBuild\r_cg_port_user.obj + DefaultBuild\r_cg_adc.obj + DefaultBuild\r_cg_adc_user.obj + DefaultBuild\r_cg_timer.obj + DefaultBuild\r_cg_timer_user.obj + DefaultBuild\r_cg_wdt.obj + DefaultBuild\r_cg_wdt_user.obj + DefaultBuild\appTask.obj + DefaultBuild\event.obj + DefaultBuild\hwCtrl.obj + DefaultBuild\MotorCtrl.obj + + + . + user + + + False + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + None + + + + + <RL78G12> + <VAR> + <fCLK Name="fCLK" Value="24" Comment="4M" Trigger="fCLK"> + <Effect> + <ADC /> + <SAU0 /> + <IICA0 /> + <TAU0 /> + </Effect> + </fCLK> + <fIH Name="fIH" Value="24" Comment="32M" /> + <fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"> + <Effect> + <TAU0 /> + <PCLBUZ0 /> + </Effect> + </fSUB> + <fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"> + <Effect> + <RTC /> + <WDT /> + <TAU0 /> + </Effect> + </fIL> + <fRTC Name="fRTC" Value="0" Comment="0k" Trigger="fIT"> + <Effect> + <RTC /> + <IT /> + </Effect> + </fRTC> + <fMAIN Name="fMAIN" Value="24" Comment="32M" Trigger="fMAIN"> + <Effect> + <PCLBUZ0 /> + </Effect> + </fMAIN> + <fINTTM02 Name="fINTTM02" Value="0" Comment="0M" Trigger="INTTM02"> + <Effect> + <SAU0 /> + </Effect> + </fINTTM02> + <fCLKSource Name="fCLKSource" Text="fIH" /> + <RESET_pin Chip="RL78G12_20pin,RL78G12_24pin" Name="RESET_pin" Text="false" Trigger="RESET_pin"> + <Effect> + <PORT /> + </Effect> + </RESET_pin> + <VDD_MIN Name="VDD_MIN" Value="2.7" Comment="4.0V" Trigger="VDD"> + <Effect> + <PCLBUZ0 /> + <PCLBUZ1 /> + <IICA0 /> + <SAU0 /> + <SAU1 /> + </Effect> + </VDD_MIN> + <VDD_MAX Name="VDD_MAX" Value="3.6" Comment="5.5V" /> + <VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"> + <Effect> + <IICA0 /> + <SAU0 /> + <SAU1 /> + <ADC /> + </Effect> + </VDDValue> + <VDD Name="VDD" Text="false" Comment="used" /> + <AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="ANI0,ANI1," /> + <ADC_ADS_VALUE Name="ADC_ADS_VALUE" Text="ANI1," /> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC00> + <IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC01> + <IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC10> + <IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC11> + <IIC20 Name="IIC20" Text="false" Comment="unused" Trigger="IIC20"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC20> + <IIC21 Name="IIC21" Text="false" Comment="unused" Trigger="IIC21"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC21> + <IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IICA0> + <ProjectName Name="PrjName" Text="M12" /> + <ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\M12\M12-05P\code\app" /> + <ProjectKind Name="PrjKind" Text="Project78K0R" /> + <DeviceName Name="DeviceName" Fixed="" Text="RL78G12" /> + <MCUName Name="MCUName" Text="RL78G12_20pin" /> + <ChipName Name="ChipName" Text="R5F10268" /> + <ChipID Name="ChipID" Text="R5F10268" /> + <MCUType Name="MCUType" Fixed="" Text="RL78" /> + <CPUCoreType Name="CPUCoreType" Fixed="" Text="0" /> + <Compiler Name="Compiler" Text="CCRL" /> + <UseSecurityId Name="GI" Text="0" /> + <SecurityId Name="GIValue" Text="00000000000000000000" /> + <LinkDirectiveFile Name="D0" Text="lk.dr" /> + <OnChipDebugOptionBytes Name="GO" Text="1" /> + <OnChipDebugOptionBytesValue Name="GOValue" Text="04" /> + <StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="1E00" /> + <SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /> + <UserOptionBytes Name="GB" Text="1" /> + <UserOptionBytesValue Name="GBValue" Text="7A47E0" /> + <RAMStartAddress Chip="R5F10268,R5F10278,R5F102A8" Name="RAMStartAddress" Fixed="" Text="000FFC00" /> + <RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /> + <ROMEndAddress Chip="R5F10268,R5F10278,R5F102A8" Name="ROMEndAddress" Fixed="" Text="00001FFF" /> + <MirrorROM Chip="R5F10266, R5F10366,R5F10267, R5F10277, R5F102A7,R5F10367, R5F10377, R5F103A7,R5F10268, R5F10278, R5F102A8,R5F10368, R5F10378, R5F103A8" Name="MirrorROM" Fixed="" Text="0" /> + <ADPC_AD Name="ADPC_AD" Value="1" /> + <CodePath Name="CodePath" Text=".\" /> + <ReportType Name="ReportType" Text="Html" /> + <CreationDateType Name="CreationDateType" Text="OutputDate" /> + <GenerateType Name="GenerateType" Text="Merge" /> + <APIOutputType Name="APIOutputType" Text="Default" /> + <FileRegister Name="FileRegister" Text="Yes" /> + <PinReflect Name="PinReflect" Text="Reflected" /> + <PIOR0Value Name="PIOR0Value" Text="0" /> + <PIOR1Value Name="PIOR1Value" Text="1" /> + <PIOR2Value Name="PIOR2Value" Text="0" /> + <PIOR3Value Name="PIOR3Value" Text="0" /> + <PIOR4Value Name="PIOR4Value" Text="0" /> + <PIOR5Value Name="PIOR5Value" Text="0" /> + <GDataFlash Name="GDataFlash" Text="2" /> + <UseFDL Name="UseFDL" Text="no" /> + <DataFlash Name="DataFlash" Text="0" /> + <OCDROM Name="OCDROM" Text="Unused" /> + <OCDROM_Address Name="OCDROM_Address" Text="00001E00" /> + <OCDROM_Length Name="OCDROM_Length" Text="512" /> + <HasRRMRam Name="HasRRMRam" Text="" /> + <PrjVersion Name="PrjVersion" Text="1.2.0.1" /> + <ProductVersion Name="ProductVersion" Text="4.08.05.01" /> + <PIOR6Value Name="PIOR6Value" Text="0" /> + <TO02_PWM Name="TO02_PWM" Text="false" /> + <TO03_PWM Name="TO03_PWM" Text="false" /> + <LinkFileName Name="LinkFileName" Text="" /> + </VAR> + <DIR> + <PIN> + <CGC> + <X1 Port="P121" Point="-" /> + <X2 Port="P122" Point="-" /> + <EXCLK Port="P122" Point="I" /> + <TOOL0 Port="P40" Point="I/O" /> + <_RESET Chip="RL78G12_20pin,RL78G12_24pin" Port="P125" RealName="_RESET" Point="I" /> + </CGC> + <PORT> + <Port1 Chip="RL78G12_20pin,RL78G12_24pin" DIN="true" Pullup="true"> + <P10 Name="P10/ANI16/PCLBUZ0/_SCK00/SCL00" TTL="true" Nch="true" AltFunc="P10" Point="I/O" /> + <P11 Name="P11/ANI17/SI00/RXD0/SDA00/TOOLRXD" TTL="true" Nch="true" AltFunc="P11" Point="I/O" /> + <P12 Name="P12/ANI18/SO00/TXD0/TOOLTXD" Nch="true" AltFunc="P12" Point="I/O" /> + <P13 Name="P13/ANI19/TI00/TO00/INTP2" AltFunc="P13" Point="I/O" /> + <P14 Name="P14/ANI20/TI01/TO01/INTP3" AltFunc="P14" Point="I/O" /> + </Port1> + <Port2 ADIN="true"> + <P20 Name="P20/ANI0/AVREFP" AltFunc="ANALOG_0" Point="I/O" /> + <P21 Name="P21/ANI1/AVREFM" AltFunc="ANI1" Point="I/O" /> + <P22 Name="P22/ANI2" AltFunc="" Point="I/O" /> + <P23 Name="P23/ANI3" AltFunc="P23" Point="I/O" /> + </Port2> + <Port4 Chip="RL78G12_20pin,RL78G12_24pin" Pullup="true"> + <P40 Name="P40/KR0/TOOL0" AltFunc="" Point="I/O" /> + <P41 Name="P41/ANI22/SO01/SDA01/TI02/TO02/INTP1" DIN="true" Nch="true" AltFunc="" Point="I/O" /> + <P42 Name="P42/ANI21/_SCK01/SCL01/TI03/TO03" DIN="true" AltFunc="" Point="I/O" /> + </Port4> + <Port6 Chip="RL78G12_20pin,RL78G12_24pin"> + <P60 Name="P60/KR4/SCLA0" AltFunc="" Point="I/O" /> + <P61 Name="P61/KR5/SDAA0" AltFunc="" Point="I/O" /> + </Port6> + <Port12 Chip="RL78G12_20pin,RL78G12_24pin"> + <P121 Name="P121/KR3/X1" AltFunc="" Point="I" /> + <P122 Name="P122/KR2/X2/EXCLK" AltFunc="" Point="I" /> + <P125 Name="P125/KR1/SI01/_RESET" Pullup="true" AltFunc="" Point="I" /> + </Port12> + <Port13> + <P137 Name="P137/INTP0" AltFunc="" Point="I" /> + </Port13> + </PORT> + <INTC> + <INTP> + <INTP0 no="1" Point="I" /> + <INTP1 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /> + <INTP2 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P13" Point="I" /> + <INTP3 Chip="RL78G12_20pin,RL78G12_24pin" PIOR0="0" Port="P14" Point="I" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <KR0 Port="P40" Point="I" /> + <KR1 Port="P125" Point="I" /> + <KR2 Port="P122" Point="I" /> + <KR3 Port="P121" Point="I" /> + <KR4 Port="P60" Point="I" /> + <KR5 Port="P61" Point="I" /> + </KEY> + </INTC> + <ADC> + <ANI0 Port="P20" Point="I" /> + <ANI1 Port="P21" Point="I" /> + <ANI2 Port="P22" Point="I" /> + <ANI3 Port="P23" Point="I" /> + <ANI16 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="I" /> + <ANI17 Chip="RL78G12_20pin,RL78G12_24pin" Port="P11" Point="I" /> + <ANI18 Chip="RL78G12_20pin,RL78G12_24pin" Port="P12" Point="I" /> + <ANI19 Chip="RL78G12_20pin,RL78G12_24pin" Port="P13" Point="I" /> + <ANI20 Chip="RL78G12_20pin,RL78G12_24pin" Port="P14" Point="I" /> + <ANI21 Chip="RL78G12_20pin,RL78G12_24pin" Port="P42" Point="I" /> + <ANI22 Chip="RL78G12_20pin,RL78G12_24pin" Port="P41" Point="I" /> + <AVREFP Port="P20" Point="I" /> + <AVREFM Port="P21" Point="I" /> + <ANALOG_0 Port="P20" RealName="ANI0/AVREFP" Point="I" /> + <ANALOG_1 Port="P21" RealName="ANI1/AVREFM" Point="I" /> + <ANALOG_2 Port="P22" RealName="ANI2" Point="I" /> + <ANALOG_3 Port="P23" RealName="ANI3" Point="I" /> + </ADC> + <Serial> + <SAU0> + <UART0> + <RXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P61" RealName="RxD0" Point="I" /> + <TXD0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR1="1" Port="P60" RealName="TxD0" Point="O" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin"> + <SO00 Port="P12" Point="O" /> + <SI00 Port="P11" Point="I" /> + <SCK00 Port="P10" RealName="_SCK00" Point="I/O" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin"> + <SO01 Port="P41" Point="O" /> + <SI01 Port="P125" Point="I" /> + <SCK01 Port="P42" RealName="_SCK01" Point="I/O" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin"> + <SCL00 Port="P10" Point="I/O" CheckNch="true" /> + <SDA00 Port="P11" Point="I/O" CheckNch="true" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin"> + <SCL01 Port="P42" Point="I/O" CheckNch="true" /> + <SDA01 Port="P41" Point="I/O" CheckNch="true" /> + </IIC01> + </SAU0> + <IICA0> + <SCLA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P60" Point="I/O" /> + <SDAA0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P61" Point="I/O" /> + </IICA0> + </Serial> + <TAU> + <TAU0 Chip="RL78G12_20pin,RL78G12_24pin" PIOR2="0"> + <Channel0> + <TI00 Port="P13" Point="I" /> + <TO00 Port="P13" Point="O" /> + </Channel0> + <Channel1> + <TI01 Port="P14" Point="I" /> + <TO01 Port="P14" Point="O" /> + </Channel1> + <Channel2> + <TI02 Port="P41" Point="I" /> + <TO02 Port="P41" Point="O" /> + </Channel2> + <Channel3> + <TI03 Port="P42" Point="I" /> + <TO03 Port="P42" Point="O" /> + </Channel3> + </TAU0> + </TAU> + <PCLBUZ> + <PCLBUZ0> + <PCLBUZ0 Chip="RL78G12_20pin,RL78G12_24pin" Port="P10" Point="O" /> + </PCLBUZ0> + </PCLBUZ> + <Others> + <VDD AltFunc="VDD" Point="-" /> + <VSS AltFunc="VSS" Point="-" /> + </Others> + </PIN> + <INT> + <INTC> + <INTP> + <INTP0 InUse="0" ISR="r_intc0_interrupt" /> + <INTP1 InUse="0" ISR="r_intc1_interrupt" /> + <INTP2 InUse="0" ISR="r_intc2_interrupt" /> + <INTP3 InUse="0" ISR="r_intc3_interrupt" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <INTKR InUse="0" ISR="r_key_interrupt" /> + </KEY> + </INTC> + <Serial> + <SAU0> + <INTCSI00 InUse="0" ISR="r_csi00_interrupt" /> + <INTCSI01 InUse="0" ISR="r_csi01_interrupt" /> + <INTCSI10 InUse="0" ISR="r_csi10_interrupt" /> + <INTCSI11 InUse="0" ISR="r_csi11_interrupt" /> + <INTST0 InUse="0" ISR="r_uart0_interrupt_send" /> + <INTST1 InUse="0" ISR="r_uart1_interrupt_send" /> + <INTSRE0 InUse="0" ISR="r_uart0_interrupt_error" /> + <INTSRE1 InUse="0" ISR="r_uart1_interrupt_error" /> + <INTSR0 InUse="0" ISR="r_uart0_interrupt_receive" /> + <INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /> + <INTIIC00 InUse="0" ISR="r_iic00_interrupt" /> + <INTIIC01 InUse="0" ISR="r_iic01_interrupt" /> + <INTIIC10 InUse="0" ISR="r_iic10_interrupt" /> + <INTIIC11 InUse="0" ISR="r_iic11_interrupt" /> + </SAU0> + <SAU1> + <INTCSI20 InUse="0" ISR="r_csi20_interrupt" /> + <INTCSI21 InUse="0" ISR="r_csi21_interrupt" /> + <INTCSI30 InUse="0" ISR="r_csi30_interrupt" /> + <INTCSI31 InUse="0" ISR="r_csi31_interrupt" /> + <INTST2 InUse="0" ISR="r_uart2_interrupt_send" /> + <INTST3 InUse="0" ISR="r_uart3_interrupt_send" /> + <INTSRE2 InUse="0" ISR="r_uart2_interrupt_error" /> + <INTSRE3 InUse="0" ISR="r_uart3_interrupt_error" /> + <INTSR2 InUse="0" ISR="r_uart2_interrupt_receive" /> + <INTSR3 InUse="0" ISR="r_uart3_interrupt_receive" /> + <INTIIC20 InUse="0" ISR="r_iic20_interrupt" /> + <INTIIC21 InUse="0" ISR="r_iic21_interrupt" /> + <INTIIC30 InUse="0" ISR="r_iic30_interrupt" /> + <INTIIC31 InUse="0" ISR="r_iic31_interrupt" /> + </SAU1> + <IICA0> + <INTIICA0 InUse="0" ISR="r_iica0_interrupt" /> + </IICA0> + </Serial> + <ADC> + <INTAD InUse="1" ISR="r_adc_interrupt" IsDMATrigger="true" /> + </ADC> + <TAU> + <TAU0> + <Channel0> + <INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM01 InUse="1" ISR="r_tau0_channel1_interrupt" /> + <INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /> + <INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /> + </Channel7> + </TAU0> + </TAU> + <IT> + <INTIT InUse="0" ISR="r_it_interrupt" /> + </IT> + <DMAC> + <DMA0> + <INTDMA0 InUse="0" ISR="r_dmac0_interrupt" /> + </DMA0> + <DMA1> + <INTDMA1 InUse="0" ISR="r_dmac1_interrupt" /> + </DMA1> + </DMAC> + <WDT> + <INTWDTI InUse="0" ISR="r_wdt_interrupt" /> + </WDT> + <LVD> + <INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /> + </LVD> + </INT> + <FUNC> + <Common> + <r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"> + <Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /> + <main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /> + <R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /> + </r_main.c> + <r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /> + <R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /> + <hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /> + <__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /> + </r_systeminit.c> + <r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /> + <R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /> + <HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /> + </r_hardware_setup.c> + <r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"> + <Type R_Dummy="void R_Dummy(void)" /> + <R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /> + </r_cg_vector_table.c> + <r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /> + <r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /> + <r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /> + <r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /> + <r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /> + <r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /> + <iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /> + </Common> + <CGC> + <r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"> + <Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(clock_mode_t mode)" /> + <R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /> + <R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /> + </r_cg_cgc.c> + <r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"> + <Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" /> + <R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /> + <R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /> + </r_cg_cgc_user.c> + <r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /> + <r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"> + <Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /> + <R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /> + <R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /> + <R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /> + <R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /> + <R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /> + <R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /> + <R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /> + <R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /> + </r_cg_pfdl.c> + <r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /> + </CGC> + <PORT> + <r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"> + <Type R_PORT_Create="void R_PORT_Create(void)" /> + <R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /> + </r_cg_port.c> + <r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"> + <Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /> + <R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /> + </r_cg_port_user.c> + <r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /> + </PORT> + <INTC> + <r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse="0"> + <Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /> + <INTP> + <R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="0" Init="2" InitMode="" /> + <INTP0> + <R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP0> + <INTP1> + <R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP1> + <INTP2> + <R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP2> + <INTP3> + <R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="0" /> + <R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="0" /> + </INTP3> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /> + <R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /> + <R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /> + </KEY> + </r_cg_intc.c> + <r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse="0"> + <Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" R_INTC0_Interrupt="__interrupt static void r_intc0_interrupt(void)" R_INTC1_Interrupt="__interrupt static void r_intc1_interrupt(void)" R_INTC2_Interrupt="__interrupt static void r_intc2_interrupt(void)" R_INTC3_Interrupt="__interrupt static void r_intc3_interrupt(void)" R_INTC4_Interrupt="__interrupt static void r_intc4_interrupt(void)" R_INTC5_Interrupt="__interrupt static void r_intc5_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" R_KEY_Interrupt="__interrupt static void r_key_interrupt(void)" /> + <INTP> + <R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="0" /> + <r_intc0_interrupt UserName="r_intc0_interrupt" LibName="R_INTC0_Interrupt" INTHandle="" InUse="0" /> + <r_intc1_interrupt UserName="r_intc1_interrupt" LibName="R_INTC1_Interrupt" INTHandle="" InUse="0" /> + <r_intc2_interrupt UserName="r_intc2_interrupt" LibName="R_INTC2_Interrupt" INTHandle="" InUse="0" /> + <r_intc3_interrupt UserName="r_intc3_interrupt" LibName="R_INTC3_Interrupt" INTHandle="" InUse="0" /> + </INTP> + <KEY Chip="RL78G12_20pin,RL78G12_24pin,"> + <R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /> + <r_key_interrupt UserName="r_key_interrupt" LibName="R_KEY_Interrupt" INTHandle="" InUse="" /> + </KEY> + </r_cg_intc_user.c> + <r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="0" /> + </INTC> + <Serial> + <r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="0"> + <Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t * const rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t * const tx_buf, uint16_t tx_num, uint8_t * const rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" IICn_Init="void IICn_Init(void)" IICn_MasterSendStart="MD_STATUS IICn_MasterSendStart(uint8_t adr, uint8_t * const tx_buf, USHORT tx_num, uint8_t wait)" IICn_MasterReceiveStart="MD_STATUS IICn_MasterReceiveStart(uint8_t adr, uint8_t * const rx_buf, USHORT rx_num, uint8_t wait)" IICn_SlaveSendStart="void IICn_SlaveSendStart(uint8_t * const tx_buf, USHORT tx_num)" IICn_SlaveReceiveStart="void IICn_SlaveReceiveStart(uint8_t * const rx_buf, USHORT rx_num)" IICn_Stop="void IICn_Stop(void)" IICn_StopCondition="void IICn_StopCondition(void)" IICn_PowerOff="void IICn_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="0" Init="1" InitMode="" /> + <R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /> + <R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /> + <R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /> + <UART0 InUse=""> + <R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="0" InitMode="" /> + <R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="0" /> + <R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="0" /> + <R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="0" /> + <R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="0" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC01> + </SAU0> + <IICA0 InUse=""> + <R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /> + <R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /> + <R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /> + <R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /> + <R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /> + <R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /> + <R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /> + <R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /> + <R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /> + <R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /> + </IICA0> + </r_cg_serial.c> + <r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="0"> + <Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" R_UARTn_Interrupt_Receive="__interrupt static void R_UARTn_Interrupt_Receive(void)" R_UARTn_Interrupt_Error="__interrupt static void R_UARTn_Interrupt_Error(void)" R_UARTn_Interrupt_Send="__interrupt static void R_UARTn_Interrupt_Send(void)" R_UARTn_Callback_SendEnd="static void R_UARTn_Callback_SendEnd(void)" R_UARTn_Callback_ReceiveEnd="static void R_UARTn_Callback_ReceiveEnd(void)" R_UARTn_Callback_Error="static void R_UARTn_Callback_Error(uint8_t err_type)" R_UARTn_Callback_SoftwareOverRun="static void R_UARTn_Callback_SoftwareOverRun(uint16_t rx_data)" R_CSIn_Interrupt="__interrupt static void R_CSIn_Interrupt(void)" R_CSIn_Callback_ReceiveEnd="static void R_CSIn_Callback_ReceiveEnd(void)" R_CSIn_Callback_Error="static void R_CSIn_Callback_Error(uint8_t err_type)" R_CSIn_Callback_SendEnd="static void R_CSIn_Callback_SendEnd(void)" R_IICn_Interrupt="__interrupt static void R_IICn_Interrupt(void)" R_IICn_Callback_Master_ReceiveEnd="static void R_IICn_Callback_Master_ReceiveEnd(void)" R_IICn_Callback_Master_SendEnd="static void R_IICn_Callback_Master_SendEnd(void)" R_IICn_Callback_Master_Error="static void R_IICn_Callback_Master_Error(MD_STATUS flag)" IICn_MasterSendEndCallback="static void IICn_MasterSendEndCallback(void)" IICn_MasterReceiveEndCallback="static void IICn_MasterReceiveEndCallback(void)" IICn_MasterErrorCallback="static void IICn_MasterErrorCallback(MD_STATUS flag)" IICn_SlaveErrorCallback="static void IICn_SlaveErrorCallback(MD_STATUS flag)" IICn_GetStopConditionCallback="static void IICn_GetStopConditionCallback(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static void r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /> + <UART0 InUse=""> + <r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="R_UARTn_Interrupt_Receive" InUse="0" /> + <r_uart0_interrupt_error UserName="r_uart0_interrupt_error" INTHandle="" LibName="R_UARTn_Interrupt_Error" InUse="0" /> + <r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="R_UARTn_Interrupt_Send" InUse="0" /> + <r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="R_UARTn_Callback_ReceiveEnd" InUse="0" /> + <r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="R_UARTn_Callback_SendEnd" InUse="0" /> + <r_uart0_callback_error UserName="r_uart0_callback_error" LibName="R_UARTn_Callback_Error" InUse="0" /> + <r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="R_UARTn_Callback_SoftwareOverRun" InUse="0" /> + </UART0> + <CSI00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /> + <r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /> + <r_csi00_callback_error UserName="r_csi00_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /> + <r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /> + </CSI00> + <CSI01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="R_CSIn_Interrupt" InUse="0" /> + <r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="R_CSIn_Callback_ReceiveEnd" InUse="0" /> + <r_csi01_callback_error UserName="r_csi01_callback_error" LibName="R_CSIn_Callback_Error" InUse="0" /> + <r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="R_CSIn_Callback_SendEnd" InUse="0" /> + </CSI01> + <IIC00 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /> + <r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /> + <r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /> + <r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /> + </IIC00> + <IIC01 Chip="RL78G12_20pin,RL78G12_24pin" InUse=""> + <r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="R_IICn_Interrupt" InUse="0" /> + <r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="R_IICn_Callback_Master_ReceiveEnd" InUse="0" /> + <r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="R_IICn_Callback_Master_SendEnd" InUse="0" /> + <r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="R_IICn_Callback_Master_Error" InUse="0" /> + </IIC01> + </SAU0> + <IICA0 InUse=""> + <R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /> + <r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /> + <r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /> + <r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /> + <r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /> + <r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /> + <r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /> + <r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /> + <r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /> + </IICA0> + </r_cg_serial_user.c> + <r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="0" /> + </Serial> + <ADC> + <r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="1"> + <Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /> + <R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="1" Init="1" InitMode="" /> + <R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="1" /> + <R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="1" /> + <R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="1" /> + <R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="1" /> + <R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="1" /> + <R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /> + <R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /> + <R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /> + <R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /> + <R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /> + <R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /> + </r_cg_adc.c> + <r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="1"> + <Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /> + <R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /> + <r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="1" /> + </r_cg_adc_user.c> + <r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="1" /> + </ADC> + <TAU> + <r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"> + <Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" /> + <TAU0> + <R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /> + <R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel0_Get_PulseWidth UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel2_Get_PulseWidth UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Get_PulseWidth UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + </TAU0> + </r_cg_timer.c> + <r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"> + <Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" /> + <TAU0> + <R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + </Channel0> + <Channel1 InUse=""> + <r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + <r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + </TAU0> + </r_cg_timer_user.c> + <r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /> + </TAU> + <WDT> + <r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"> + <Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /> + <R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /> + <R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /> + </r_cg_wdt.c> + <r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"> + <Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /> + <R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /> + <r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="0" /> + </r_cg_wdt_user.c> + <r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /> + </WDT> + <IT> + <r_cg_it.c UserName="r_cg_it.c" LibName=".c" InUse=""> + <Type R_IT_Create="void R_IT_Create(void)" R_IT_Start="void R_IT_Start(void)" R_IT_Stop="void R_IT_Stop(void)" R_IT_Set_PowerOff="void R_IT_Set_PowerOff(void)" /> + <R_IT_Create UserName="R_IT_Create" LibName="R_IT_Create" InUse="" Init="1" InitMode="" /> + <R_IT_Start UserName="R_IT_Start" LibName="R_IT_Start" InUse="" /> + <R_IT_Stop UserName="R_IT_Stop" LibName="R_IT_Stop" InUse="" /> + <R_IT_Set_PowerOff UserName="R_IT_Set_PowerOff" LibName="R_IT_Set_PowerOff" InUse="" /> + </r_cg_it.c> + <r_cg_it_user.c UserName="r_cg_it_user.c" LibName="_user.c" InUse=""> + <Type R_IT_Create_UserInit="void R_IT_Create_UserInit(void)" r_it_interrupt="__interrupt static void r_it_interrupt(void)" /> + <R_IT_Create_UserInit UserName="R_IT_Create_UserInit" LibName="R_IT_Create_UserInit" InUse="" /> + <r_it_interrupt UserName="r_it_interrupt" INTHandle="" LibName="r_it_interrupt" InUse="" /> + </r_cg_it_user.c> + <r_cg_it.h UserName="r_cg_it.h" LibName=".h" InUse="" /> + </IT> + <PCLBUZ> + <r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse=""> + <Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="" Init="1" InitMode="" /> + <R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="" /> + <R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="" /> + </PCLBUZ0> + </r_cg_pclbuz.c> + <r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse=""> + <Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="" Init="1" /> + </PCLBUZ0> + </r_cg_pclbuz_user.c> + <r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="" /> + </PCLBUZ> + <DMAC> + <r_cg_dmac.c UserName="r_cg_dmac.c" LibName=".c" InUse=""> + <Type R_DMACn_Create="void R_DMACn_Create(void)" R_DMACn_Start="void R_DMACn_Start(void)" R_DMACn_Stop="void R_DMACn_Stop(void)" R_DMACn_Set_SoftwareTriggerOn="void R_DMACn_Set_SoftwareTriggerOn(void)" /> + <DMA0 InUse=""> + <R_DMAC0_Create UserName="R_DMAC0_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /> + <R_DMAC0_Start UserName="R_DMAC0_Start" LibName="R_DMACn_Start" InUse="" /> + <R_DMAC0_Stop UserName="R_DMAC0_Stop" LibName="R_DMACn_Stop" InUse="" /> + <R_DMAC0_Set_SoftwareTriggerOn UserName="R_DMAC0_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /> + </DMA0> + <DMA1 InUse=""> + <R_DMAC1_Create UserName="R_DMAC1_Create" LibName="R_DMACn_Create" InUse="" Init="1" InitMode="" /> + <R_DMAC1_Start UserName="R_DMAC1_Start" LibName="R_DMACn_Start" InUse="" /> + <R_DMAC1_Stop UserName="R_DMAC1_Stop" LibName="R_DMACn_Stop" InUse="" /> + <R_DMAC1_Set_SoftwareTriggerOn UserName="R_DMAC1_Set_SoftwareTriggerOn" LibName="R_DMACn_Set_SoftwareTriggerOn" InUse="" /> + </DMA1> + </r_cg_dmac.c> + <r_cg_dmac_user.c UserName="r_cg_dmac_user.c" LibName="_user.c" InUse=""> + <Type R_DMACn_Create_UserInit="void R_DMACn_Create_UserInit(void)" r_dmacn_interrupt="__interrupt static void r_dmacn_interrupt(void)" /> + <DMA0> + <R_DMAC0_Create_UserInit UserName="R_DMAC0_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /> + <r_dmac0_interrupt UserName="r_dmac0_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /> + </DMA0> + <DMA1> + <R_DMAC1_Create_UserInit UserName="R_DMAC1_Create_UserInit" LibName="R_DMACn_Create_UserInit" InUse="" /> + <r_dmac1_interrupt UserName="r_dmac1_interrupt" INTHandle="" LibName="r_dmacn_interrupt" InUse="" /> + </DMA1> + </r_cg_dmac_user.c> + <r_cg_dmac.h UserName="r_cg_dmac.h" LibName=".h" InUse="" /> + </DMAC> + <LVD> + <r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"> + <Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /> + <R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /> + <R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /> + </r_cg_lvd.c> + <r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"> + <Type R_LVD_Creat_UserInit="void R_LVD_Creat_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /> + <R_LVD_Creat_UserInit UserName="R_LVD_Creat_UserInit" LibName="R_LVD_Creat_UserInit" InUse="0" /> + <r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /> + </r_cg_lvd_user.c> + <r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /> + </LVD> + </FUNC> + <TAG> + <GlobleUserTag> + <cg_security9 Name="cg_security9" Value="00" /> + <cg_security7 Name="cg_security7" Value="00" /> + <cg_security5 Name="cg_security5" Value="00" /> + <ocdstart Name="ocdstart" Value="01E00" /> + <cg_security3 Name="cg_security3" Value="00" /> + <cg_security0 Name="cg_security0" Value="00" /> + <cg_security1 Name="cg_security1" Value="00" /> + <clock_option Name="clock_option" Value="E0" /> + <pior_value Name="pior_value" Value="02" /> + <cg_option Name="cg_option" Value="04" /> + <cg_security8 Name="cg_security8" Value="00" /> + <cg_security6 Name="cg_security6" Value="00" /> + <cg_security4 Name="cg_security4" Value="00" /> + <cg_security2 Name="cg_security2" Value="00" /> + <cg_iawctl_value Name="cg_iawctl_value" Value="00" /> + <lvi_option Name="lvi_option" Value="47" /> + <wdt_option Name="wdt_option" Value="7A" /> + </GlobleUserTag> + </TAG> + </DIR> + <MACRO> + <CGC HelpID="CGC" Prepared="true" SetFlag="True" NeedRefresh="False"> + <CGC SetFlag="True" MacroName="cgc" /> + </CGC> + <PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"> + <PORT SetFlag="True" MacroName="PORT" /> + </PORT> + <INTC SetFlag="False" HelpID="int" NeedRefresh="False"> + <INTP Accelerate="No" MacroName="INTP" SetFlag="False" TabEnable="True" /> + <KEY Chip="RL78G12_20pin,RL78G12_24pin," MacroName="KEY" TabEnable="True" /> + </INTC> + <Serial SetFlag="False" HelpID="serial" NeedRefresh="False"> + <SAU0 Chip="RL78G12_20pin,RL78G12_24pin" Accelerate="No" MacroName="SAU" Channel="0" SetFlag="False" TabEnable="True"> + <Channel0 UART="0" CSI="00" IIC="00" Channel="0" /> + <Channel1 UART="0" CSI="01" IIC="01" Channel="1" /> + </SAU0> + <IICA0 Accelerate="No" MacroName="IICA" Channel="0" TabEnable="True" /> + </Serial> + <ADC SetFlag="True" HelpID="adc" NeedRefresh="False"> + <ADC SetFlag="True" MacroName="ADC" /> + </ADC> + <TAU SetFlag="True" HelpID="timer" NeedRefresh="False"> + <TAU0 Accelerate="No" Chip="RL78G12_20pin,RL78G12_24pin" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3" SetFlag="True" /> + </TAU> + <WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"> + <WDT SetFlag="True" MacroName="WDT" /> + </WDT> + <IT SetFlag="" HelpID="intervaltimer" NeedRefresh="False"> + <IT MacroName="IntervalTM" /> + </IT> + <PCLBUZ SetFlag="" HelpID="PCLBUZ" NeedRefresh="False"> + <PCLBUZ0 MacroName="PCLBUZ" Channel="0" /> + </PCLBUZ> + <DMAC HelpID="dmac" SetFlag="" NeedRefresh="False"> + <DMA0 MacroName="DMAC" Channel="0" TabEnable="True" /> + <DMA1 MacroName="DMAC" Channel="1" TabEnable="True" /> + </DMAC> + <LVD SetFlag="True" Prepared="true" HelpID="lvi" NeedRefresh="False"> + <LVD MacroName="LVD" SetFlag="True" /> + </LVD> + </MACRO> + <SETTING> + <CGC> + <setting name="PIOR_Setting" value="FIX" /> + <setting name="PIOR6" value="1" /> + <setting name="PIOR5" value="1" /> + <setting name="PIOR4" value="1" /> + <setting name="PIOR3" value="1" /> + <setting name="PIOR2" value="1" /> + <setting name="PIOR1" value="0" /> + <setting name="PIOR0" value="1" /> + <setting name="PIOR10" value="1" /> + <setting name="PIOR11" value="1" /> + <setting name="PIOR12" value="1" /> + <setting name="PIOR13" value="1" /> + <setting name="VDD" value="VDD0" /> + <setting name="EVDD" value="EVDD2" /> + <setting name="Main_system_clock" value="high-speed internal clock" /> + <setting name="High_speed_internal_oscillator" value="operation" /> + <setting name="High_speed_internal_frequency" value="8" /> + <setting name="High_speed_system_clock" value="stop" /> + <setting name="High_speed_system_input" value="external" /> + <setting name="HighSpeedSystemStable" value="7" /> + <setting name="High_speed_system_clock_frequency" value="5" /> + <setting name="Sub_clock_operation" value="XT1" /> + <setting name="SubclockFrequency" value="32.768" /> + <setting name="XT1_oscillator_oscillation_mode" value="0" /> + <setting name="SubClock" value="unused" /> + <setting name="Subclock_in_halt" value="0" /> + <setting name="CPU_clock" value="0" /> + <setting name="Internal_low-speed_clock" value="15" /> + <setting name="RTC_clcok_selection" value="0" /> + <setting name="RESET_PIN_USED" value="false" /> + <setting name="RESET_PIN_UNUSED" value="true" /> + <setting name="On_chip_debug" value="unused" /> + <setting name="RRM" value="used" /> + <setting name="Trace" value="Used" /> + <setting name="Erase_flash_memory" value="yes" /> + <setting name="Security_ID_setting" value="used" /> + <setting name="Security_ID" value="0x00000000000000000000" /> + <setting name="CG_ReadResetSource" value="generated" /> + <setting name="Accessoperation" value="unused" /> + <setting name="RAMoperation" value="unused" /> + <setting name="RAMArea" value="0" /> + <setting name="PORToperation" value="unused" /> + <setting name="INToperation" value="unused" /> + <setting name="CHIPoperation" value="unused" /> + <setting name="DataFlash" value="unused" /> + <setting name="ProgramFlash" value="unused" /> + <setting name="Monitor" value="unused" /> + <setting name="StartStop" value="unused" /> + <setting name="Emulator" value="E1" /> + </CGC> + <PORT> + <PortP1> + <P10> + <setting name="Operation" value="input" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P10> + <P11> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P11> + <P12> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P12> + <P13> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P13> + <P14> + <setting name="Operation" value="output" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P14> + </PortP1> + <PortP2> + <P20> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P20> + <P21> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P21> + <P22> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P22> + <P23> + <setting name="Operation" value="input" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P23> + </PortP2> + <PortP4> + <P40> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P40> + <P41> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P41> + <P42> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="1" /> + </P42> + </PortP4> + <PortP6> + <P60> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P60> + <P61> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P61> + </PortP6> + <PortP12> + <P121> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P121> + <P122> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P122> + <P125> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="used" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P125> + </PortP12> + <PortP13> + <P137> + <setting name="Operation" value="unused" /> + <setting name="Pull_up" value="unused" /> + <setting name="TTL_buffer" value="unused" /> + <setting name="N-ch_open-drain" value="unused" /> + <setting name="Output_value" value="0" /> + </P137> + </PortP13> + </PORT> + <ADC> + <setting name="AD_convertion" value="used" /> + <setting name="Comparator_operation" value="enable" /> + <setting name="Resolution" value="10bit" /> + <setting name="AD_Positive" value="VDD" /> + <setting name="AD_Negative" value="VSS" /> + <setting name="AD_Trigger" value="hardtrinowait" /> + <setting name="AD_Trigger_Timer" value="0" /> + <setting name="Mode" value="ONESELECT" /> + <setting name="InputPins" value="1" /> + <setting name="InputPinsAttach" value="ANI0 - ANI1" /> + <setting name="AD_Inputpin16" value="unused" /> + <setting name="AD_Inputpin17" value="unused" /> + <setting name="AD_Inputpin18" value="unused" /> + <setting name="AD_Inputpin19" value="unused" /> + <setting name="AD_Inputpin20" value="unused" /> + <setting name="AD_Inputpin21" value="unused" /> + <setting name="AD_Inputpin22" value="unused" /> + <setting name="AD_Inputpin23" value="unused" /> + <setting name="AD_Inputpin24" value="unused" /> + <setting name="AD_Inputpin25" value="unused" /> + <setting name="AD_Inputpin26" value="unused" /> + <setting name="SelectedChannel" value="1" /> + <setting name="SelectedChannelAttach" value="ANI1" /> + <setting name="ConvTimeMode" value="0" /> + <setting name="ConversionTime" value="0" /> + <setting name="AREAFunction" value="AREA1" /> + <setting name="AREAValue_ADUL" value="255" /> + <setting name="AREAValue_ADLL" value="0" /> + <setting name="Interrput_priority" value="3" /> + <setting name="AD_interrupt" value="used" /> + </ADC> + <TAU0> + <Channel0> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval0> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="-1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="-1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="unused" /> + </TAUInterval0> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval1> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="used" /> + </TAUInterval1> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + </TAU0> + <WDT> + <setting name="Operation" value="used" /> + <setting name="Overflow_time" value="5" /> + <setting name="Window_opening_time" value="0" /> + <setting name="Standby_operation" value="stop" /> + <setting name="Interval_interrupt" value="not use" /> + <setting name="Interval_interrupt_priority" value="3" /> + </WDT> + <LVD> + <setting name="Operation" value="used" /> + <setting name="Reset_only_level" value="5" /> + <setting name="InterruptReset_level" value="0" /> + <setting name="Interrupt_level" value="0" /> + <setting name="Interrupt_only_level" value="0" /> + <setting name="operation_mode" value="reset" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="Interrupt_only_priority" value="3" /> + </LVD> + <SAU0> + <IIC00 /> + <CSI00 /> + <UART0 /> + <Channel0> + <setting name="Channel_function_-i" value="0" /> + <setting name="Detail_function_-i" value="-1" /> + <Transmit_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="none" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="none" /> + <setting name="Transmit_stop_length" value="1 bit" /> + <setting name="TranBaudrate" value="115200" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Transmit_UART0> + <Receive_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="none" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="none" /> + <setting name="Transmit_stop_length" value="1 bit" /> + <setting name="TranBaudrate" value="9600" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Receive_UART0> + <Both_UART0> + <setting name="Receive_data_direction" value="LSB" /> + <setting name="Receive_data_length" value="8 bits" /> + <setting name="Receive_parity" value="odd" /> + <setting name="RecBaudrate" value="9600" /> + <setting name="Receive_end_callback_function" value="generated" /> + <setting name="Receive_error_callback_function" value="generated" /> + <setting name="Transfer_mode" value="single" /> + <setting name="Transmit_data_direction" value="LSB" /> + <setting name="Transmit_data_level" value="normal" /> + <setting name="Transmit_data_length" value="8 bits" /> + <setting name="Transmit_parity" value="odd" /> + <setting name="Transmit_stop_length" value="2 bits" /> + <setting name="TranBaudrate" value="9600" /> + <setting name="Transmit_end_callback_function" value="generated" /> + <setting name="Transmit_end_interrupt_priority" value="3" /> + <setting name="Receive_error_interrupt_priority" value="3" /> + <setting name="Receive_end_interrupt_priority" value="3" /> + <setting name="Reveive_Data_Level" value="Normal" /> + <setting name="Receive_error_interrupt" value="not used" /> + </Both_UART0> + </Channel0> + <IIC01 /> + <CSI01 /> + <Channel1> + <setting name="Channel_function_-i" value="0" /> + <setting name="Detail_function_-i" value="-1" /> + </Channel1> + </SAU0> + <IICA0> + <setting name="Mode" value="Unused" /> + </IICA0> + <INTP> + <INTP0> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP0> + <INTP1> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP1> + <INTP2> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP2> + <INTP3> + <setting name="Valid_edge" value="falling" /> + <setting name="Operation" value="unused" /> + <setting name="ValidEdge" value="0" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="pinsel" value="-1" /> + </INTP3> + </INTP> + <KEY> + <setting name="Interrupt_priority" value="3" /> + <setting name="KR0" value="unused" /> + <setting name="KR1" value="unused" /> + <setting name="KR2" value="unused" /> + <setting name="KR3" value="unused" /> + <setting name="KR4" value="unused" /> + <setting name="KR5" value="unused" /> + <setting name="KR6" value="unused" /> + <setting name="KR7" value="unused" /> + <setting name="KR8" value="unused" /> + <setting name="KR9" value="unused" /> + <setting name="EdgeSelection" value="0" /> + <setting name="FlagUse" value="0" /> + </KEY> + </SETTING> +</RL78G12> + + + \ No newline at end of file diff --git a/app/OUTPUT/更改履历.txt b/app/OUTPUT/更改履历.txt new file mode 100644 index 0000000..9c3bae6 --- /dev/null +++ b/app/OUTPUT/更改履历.txt @@ -0,0 +1 @@ +SW0101:初版 diff --git a/app/cstart.asm b/app/cstart.asm new file mode 100644 index 0000000..2542550 --- /dev/null +++ b/app/cstart.asm @@ -0,0 +1,229 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/ +; NOTE : THIS IS A TYPICAL EXAMPLE. + +$IFNDEF __RENESAS_VERSION__ +__RENESAS_VERSION__ .EQU 0x01000000 +$ENDIF + + .public _start + .public _exit + +;----------------------------------------------------------------------------- +; RAM section +;----------------------------------------------------------------------------- +.SECTION .dataR, DATA +.SECTION .sdataR, DATA +; .SECTION .datafR, DATAF +; .SECTION .textfR, TEXTF + +$IF (__RENESAS_VERSION__ < 0x01010000) ; for CC-RL V1.00 +;----------------------------------------------------------------------------- +; stack area +;----------------------------------------------------------------------------- +; !!! [CAUTION] !!! +; Set up stack size suitable for a project. +.SECTION .stack_bss, BSS +_stackend: + .DS 0x200 +_stacktop: +$ENDIF + +;----------------------------------------------------------------------------- +; RESET vector +;----------------------------------------------------------------------------- +_start .VECTOR 0 + +;----------------------------------------------------------------------------- +; startup +;----------------------------------------------------------------------------- +.SECTION .text, TEXT +_start: + ;-------------------------------------------------- + ; setting register bank + ;-------------------------------------------------- +; SEL RB0 + + ;-------------------------------------------------- + ; setting mirror area + ;-------------------------------------------------- +; ONEB !PMC ; mirror area = 10000-1FFFFH + + ;-------------------------------------------------- + ; setting the stack pointer + ;-------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) + MOVW SP,#LOWW(__STACK_ADDR_START) +$ELSE ; for CC-RL V1.00 + MOVW SP,#LOWW(_stacktop) +$ENDIF + + ;-------------------------------------------------- + ; initializing stack area + ;-------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) + MOVW AX,#LOWW(__STACK_ADDR_END) +$ELSE ; for CC-RL V1.00 + MOVW AX,#LOWW(_stackend) +$ENDIF + CALL !!_stkinit + + ;-------------------------------------------------- + ; hardware initialization + ;-------------------------------------------------- + CALL !!_hdwinit + + ;-------------------------------------------------- + ; initializing BSS + ;-------------------------------------------------- + ; clear external variables which doesn't have initial value (near) + MOVW HL,#LOWW(STARTOF(.bss)) + MOVW AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss)) + BR $.L2_BSS +.L1_BSS: + MOV [HL+0],#0 + INCW HL +.L2_BSS: + CMPW AX,HL + BNZ $.L1_BSS + + ; clear saddr variables which doesn't have initial value + MOVW HL,#LOWW(STARTOF(.sbss)) + MOVW AX,#LOWW(STARTOF(.sbss) + SIZEOF(.sbss)) + BR $.L2_SBSS +.L1_SBSS: + MOV [HL+0],#0 + INCW HL +.L2_SBSS: + CMPW AX,HL + BNZ $.L1_SBSS + + ; clear external variables which doesn't have initial value (far) +; MOV ES,#HIGHW(STARTOF(.bssf)) +; MOVW HL,#LOWW(STARTOF(.bssf)) +; MOVW AX,#LOWW(STARTOF(.bssf) + SIZEOF(.bssf)) +; BR $.L2_BSSF +;.L1_BSSF: +; MOV ES:[HL+0],#0 +; INCW HL +;.L2_BSSF: +; CMPW AX,HL +; BNZ $.L1_BSSF + + ;-------------------------------------------------- + ; ROM data copy + ;-------------------------------------------------- + ; copy external variables having initial value (near) + MOV ES,#HIGHW(STARTOF(.data)) + MOVW BC,#LOWW(SIZEOF(.data)) + BR $.L2_DATA +.L1_DATA: + DECW BC + MOV A,ES:LOWW(STARTOF(.data))[BC] + MOV LOWW(STARTOF(.dataR))[BC],A +.L2_DATA: + CLRW AX + CMPW AX,BC + BNZ $.L1_DATA + + ; copy saddr variables having initial value + MOV ES,#HIGHW(STARTOF(.sdata)) + MOVW BC,#LOWW(SIZEOF(.sdata)) + BR $.L2_SDATA +.L1_SDATA: + DECW BC + MOV A,ES:LOWW(STARTOF(.sdata))[BC] + MOV LOWW(STARTOF(.sdataR))[BC],A +.L2_SDATA: + CLRW AX + CMPW AX,BC + BNZ $.L1_SDATA + + ; copy external variables having initial value (far) +; MOVW BC,#LOWW(SIZEOF(.dataf)) +; BR $.L2_DATAF +;.L1_DATAF: +; DECW BC +; MOV ES,#HIGHW(STARTOF(.dataf)) +; MOV A,ES:LOWW(STARTOF(.dataf))[BC] +; MOV ES,#HIGHW(STARTOF(.datafR)) +; MOV ES:LOWW(STARTOF(.datafR))[BC],A +;.L2_DATAF: +; CLRW AX +; CMPW AX,BC +; BNZ $.L1_DATAF + + ; copy .text to RAM +; MOV C,#HIGHW(STARTOF(.textf)) +; MOVW HL,#LOWW(STARTOF(.textf)) +; MOVW DE,#LOWW(STARTOF(.textfR)) +; BR $.L2_TEXT +;.L1_TEXT: +; MOV A,C +; MOV ES,A +; MOV A,ES:[HL] +; MOV [DE],A +; INCW DE +; INCW HL +; CLRW AX +; CMPW AX,HL +; SKNZ +; INC C +;.L2_TEXT: +; MOVW AX,HL +; CMPW AX,#LOWW(STARTOF(.text) + SIZEOF(.text)) +; BNZ $.L1_TEXT + + ;-------------------------------------------------- + ; call main function + ;-------------------------------------------------- + CALL !!_main ; main(); + + ;-------------------------------------------------- + ; call exit function + ;-------------------------------------------------- + CLRW AX ; exit(0) +_exit: + BR $_exit + +;----------------------------------------------------------------------------- +; section +;----------------------------------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) +.SECTION .RLIB, TEXTF +.L_section_RLIB: +.SECTION .SLIB, TEXTF +.L_section_SLIB: +$ENDIF +.SECTION .textf, TEXTF +.L_section_textf: +.SECTION .constf, CONSTF +.L_section_constf: +.SECTION .data, DATA +.L_section_data: +;.SECTION .dataf, DATAF +;.L_section_dataf: +.SECTION .sdata, SDATA +.L_section_sdata: +.SECTION .bss, BSS +.L_section_bss: +;.SECTION .bssf, BSSF +;.L_section_bssf: +.SECTION .sbss, SBSS +.L_section_sbss: diff --git a/app/hdwinit.asm b/app/hdwinit.asm new file mode 100644 index 0000000..0b74c68 --- /dev/null +++ b/app/hdwinit.asm @@ -0,0 +1,35 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/;--------------------------------------------------------------------- +; _hdwinit +; +; void _hdwinit(void); +; +; input: +; NONE +; output: +; NONE +;--------------------------------------------------------------------- + +; NOTE : THIS IS A TYPICAL EXAMPLE. + + .PUBLIC _hdwinit + +.textf .CSEG TEXTF +_hdwinit: + RET diff --git a/app/iodefine.h b/app/iodefine.h new file mode 100644 index 0000000..b1f35fb --- /dev/null +++ b/app/iodefine.h @@ -0,0 +1,542 @@ +/******************************************************************************/ +/* DISCLAIMER */ +/* This software is supplied by Renesas Electronics Corporation and is only */ +/* intended for use with Renesas products. No other uses are authorized.This */ +/* software is owned by Renesas Electronics Corporation and is protected */ +/* under all applicable laws, including copyright laws. */ +/* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES */ +/* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING */ +/* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR */ +/* PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY */ +/* DISCLAIMED. */ +/* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS */ +/* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE */ +/* LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL */ +/* DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS */ +/* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. */ +/* Renesas reserves the right, without notice, to make changes to this */ +/* software and to discontinue the availability of this software. */ +/* By using this software, you agree to the additional terms and conditions */ +/* found by accessing the following link: */ +/* http://www.renesas.com/disclaimer */ +/* */ +/* Device : RL78/R5F10268 */ +/* File Name : iodefine.h */ +/* Abstract : Definition of Special Function Register (SFR) */ +/* History : V1.12 [Device File version] */ +/* Options : -df=E:\Program Files (x86)\renesas\CS+\CC\Device\RL78\Devicef */ +/* ile\DR5F10268.DVF -o=C:\Users\dm01\Documents\K67L\iodefine.h */ +/* -f */ +/* Date : 2022/5/20 */ +/* Version : V1.15.00.01 [df2iodef.exe version] */ +/* This is a typical example. */ +/* */ +/******************************************************************************/ +#ifndef __R5F10268IODEFINE_HEADER__ +#define __R5F10268IODEFINE_HEADER__ + +typedef struct +{ + unsigned char no0:1; + unsigned char no1:1; + unsigned char no2:1; + unsigned char no3:1; + unsigned char no4:1; + unsigned char no5:1; + unsigned char no6:1; + unsigned char no7:1; +} __bitf_T; + +typedef struct +{ + unsigned char no0:1; + unsigned char no1:1; + unsigned char no2:1; + unsigned char no3:1; + unsigned char no4:1; + unsigned char no5:1; + unsigned char no6:1; + unsigned char no7:1; + unsigned char no8:1; + unsigned char no9:1; + unsigned char no10:1; + unsigned char no11:1; + unsigned char no12:1; + unsigned char no13:1; + unsigned char no14:1; + unsigned char no15:1; +} __bitf_T2; + + + +#define ADM2 (*(volatile __near unsigned char *)0x10) +#define ADM2_bit (*(volatile __near __bitf_T *)0x10) +#define ADTYP (((volatile __near __bitf_T *)0x10)->no0) +#define AWC (((volatile __near __bitf_T *)0x10)->no2) +#define ADRCK (((volatile __near __bitf_T *)0x10)->no3) +#define ADUL (*(volatile __near unsigned char *)0x11) +#define ADLL (*(volatile __near unsigned char *)0x12) +#define ADTES (*(volatile __near unsigned char *)0x13) +#define PU1 (*(volatile __near unsigned char *)0x31) +#define PU1_bit (*(volatile __near __bitf_T *)0x31) +#define PU4 (*(volatile __near unsigned char *)0x34) +#define PU4_bit (*(volatile __near __bitf_T *)0x34) +#define PU12 (*(volatile __near unsigned char *)0x3C) +#define PU12_bit (*(volatile __near __bitf_T *)0x3C) +#define PIM1 (*(volatile __near unsigned char *)0x41) +#define PIM1_bit (*(volatile __near __bitf_T *)0x41) +#define POM1 (*(volatile __near unsigned char *)0x51) +#define POM1_bit (*(volatile __near __bitf_T *)0x51) +#define POM4 (*(volatile __near unsigned char *)0x54) +#define POM4_bit (*(volatile __near __bitf_T *)0x54) +#define PMC1 (*(volatile __near unsigned char *)0x61) +#define PMC1_bit (*(volatile __near __bitf_T *)0x61) +#define PMC4 (*(volatile __near unsigned char *)0x64) +#define PMC4_bit (*(volatile __near __bitf_T *)0x64) +#define NFEN0 (*(volatile __near unsigned char *)0x70) +#define NFEN0_bit (*(volatile __near __bitf_T *)0x70) +#define NFEN1 (*(volatile __near unsigned char *)0x71) +#define NFEN1_bit (*(volatile __near __bitf_T *)0x71) +#define ISC (*(volatile __near unsigned char *)0x73) +#define ISC_bit (*(volatile __near __bitf_T *)0x73) +#define TIS0 (*(volatile __near unsigned char *)0x74) +#define ADPC (*(volatile __near unsigned char *)0x76) +#define PIOR (*(volatile __near unsigned char *)0x77) +#define IAWCTL (*(volatile __near unsigned char *)0x78) +#define DFLCTL (*(volatile __near unsigned char *)0x90) +#define DFLCTL_bit (*(volatile __near __bitf_T *)0x90) +#define DFLEN (((volatile __near __bitf_T *)0x90)->no0) +#define HIOTRM (*(volatile __near unsigned char *)0xA0) +#define HOCODIV (*(volatile __near unsigned char *)0xA8) +#define TEMPCAL0 (*(volatile __near unsigned char *)0xAC) +#define TEMPCAL1 (*(volatile __near unsigned char *)0xAD) +#define TEMPCAL2 (*(volatile __near unsigned char *)0xAE) +#define TEMPCAL3 (*(volatile __near unsigned char *)0xAF) +#define MDCL (*(volatile __near unsigned short *)0xE0) +#define MDCH (*(volatile __near unsigned short *)0xE2) +#define MDUC (*(volatile __near unsigned char *)0xE8) +#define MDUC_bit (*(volatile __near __bitf_T *)0xE8) +#define DIVST (((volatile __near __bitf_T *)0xE8)->no0) +#define MACSF (((volatile __near __bitf_T *)0xE8)->no1) +#define MACOF (((volatile __near __bitf_T *)0xE8)->no2) +#define MDSM (((volatile __near __bitf_T *)0xE8)->no3) +#define MACMODE (((volatile __near __bitf_T *)0xE8)->no6) +#define DIVMODE (((volatile __near __bitf_T *)0xE8)->no7) +#define PER0 (*(volatile __near unsigned char *)0xF0) +#define PER0_bit (*(volatile __near __bitf_T *)0xF0) +#define TAU0EN (((volatile __near __bitf_T *)0xF0)->no0) +#define SAU0EN (((volatile __near __bitf_T *)0xF0)->no2) +#define IICA0EN (((volatile __near __bitf_T *)0xF0)->no4) +#define ADCEN (((volatile __near __bitf_T *)0xF0)->no5) +#define TMKAEN (((volatile __near __bitf_T *)0xF0)->no7) +#define OSMC (*(volatile __near unsigned char *)0xF3) +#define RMC (*(volatile __near unsigned char *)0xF4) +#define RMC_bit (*(volatile __near __bitf_T *)0xF4) +#define WDVOL (((volatile __near __bitf_T *)0xF4)->no7) +#define RPECTL (*(volatile __near unsigned char *)0xF5) +#define RPECTL_bit (*(volatile __near __bitf_T *)0xF5) +#define RPEF (((volatile __near __bitf_T *)0xF5)->no0) +#define RPERDIS (((volatile __near __bitf_T *)0xF5)->no7) +#define BCDADJ (*(volatile __near unsigned char *)0xFE) +#define SSR00 (*(volatile __near unsigned short *)0x100) +#define SSR00L (*(volatile __near unsigned char *)0x100) +#define SSR01 (*(volatile __near unsigned short *)0x102) +#define SSR01L (*(volatile __near unsigned char *)0x102) +#define SIR00 (*(volatile __near unsigned short *)0x108) +#define SIR00L (*(volatile __near unsigned char *)0x108) +#define SIR01 (*(volatile __near unsigned short *)0x10A) +#define SIR01L (*(volatile __near unsigned char *)0x10A) +#define SMR00 (*(volatile __near unsigned short *)0x110) +#define SMR01 (*(volatile __near unsigned short *)0x112) +#define SCR00 (*(volatile __near unsigned short *)0x118) +#define SCR01 (*(volatile __near unsigned short *)0x11A) +#define SE0 (*(volatile __near unsigned short *)0x120) +#define SE0L (*(volatile __near unsigned char *)0x120) +#define SE0L_bit (*(volatile __near __bitf_T *)0x120) +#define SS0 (*(volatile __near unsigned short *)0x122) +#define SS0L (*(volatile __near unsigned char *)0x122) +#define SS0L_bit (*(volatile __near __bitf_T *)0x122) +#define ST0 (*(volatile __near unsigned short *)0x124) +#define ST0L (*(volatile __near unsigned char *)0x124) +#define ST0L_bit (*(volatile __near __bitf_T *)0x124) +#define SPS0 (*(volatile __near unsigned short *)0x126) +#define SPS0L (*(volatile __near unsigned char *)0x126) +#define SO0 (*(volatile __near unsigned short *)0x128) +#define SOE0 (*(volatile __near unsigned short *)0x12A) +#define SOE0L (*(volatile __near unsigned char *)0x12A) +#define SOE0L_bit (*(volatile __near __bitf_T *)0x12A) +#define SOL0 (*(volatile __near unsigned short *)0x134) +#define SOL0L (*(volatile __near unsigned char *)0x134) +#define SSC0 (*(volatile __near unsigned short *)0x138) +#define SSC0L (*(volatile __near unsigned char *)0x138) +#define TCR00 (*(volatile __near unsigned short *)0x180) +#define TCR01 (*(volatile __near unsigned short *)0x182) +#define TCR02 (*(volatile __near unsigned short *)0x184) +#define TCR03 (*(volatile __near unsigned short *)0x186) +#define TMR00 (*(volatile __near unsigned short *)0x190) +#define TMR01 (*(volatile __near unsigned short *)0x192) +#define TMR02 (*(volatile __near unsigned short *)0x194) +#define TMR03 (*(volatile __near unsigned short *)0x196) +#define TSR00 (*(volatile __near unsigned short *)0x1A0) +#define TSR00L (*(volatile __near unsigned char *)0x1A0) +#define TSR01 (*(volatile __near unsigned short *)0x1A2) +#define TSR01L (*(volatile __near unsigned char *)0x1A2) +#define TSR02 (*(volatile __near unsigned short *)0x1A4) +#define TSR02L (*(volatile __near unsigned char *)0x1A4) +#define TSR03 (*(volatile __near unsigned short *)0x1A6) +#define TSR03L (*(volatile __near unsigned char *)0x1A6) +#define TE0 (*(volatile __near unsigned short *)0x1B0) +#define TE0L (*(volatile __near unsigned char *)0x1B0) +#define TE0L_bit (*(volatile __near __bitf_T *)0x1B0) +#define TS0 (*(volatile __near unsigned short *)0x1B2) +#define TS0L (*(volatile __near unsigned char *)0x1B2) +#define TS0L_bit (*(volatile __near __bitf_T *)0x1B2) +#define TT0 (*(volatile __near unsigned short *)0x1B4) +#define TT0L (*(volatile __near unsigned char *)0x1B4) +#define TT0L_bit (*(volatile __near __bitf_T *)0x1B4) +#define TPS0 (*(volatile __near unsigned short *)0x1B6) +#define TO0 (*(volatile __near unsigned short *)0x1B8) +#define TO0L (*(volatile __near unsigned char *)0x1B8) +#define TOE0 (*(volatile __near unsigned short *)0x1BA) +#define TOE0L (*(volatile __near unsigned char *)0x1BA) +#define TOE0L_bit (*(volatile __near __bitf_T *)0x1BA) +#define TOL0 (*(volatile __near unsigned short *)0x1BC) +#define TOL0L (*(volatile __near unsigned char *)0x1BC) +#define TOM0 (*(volatile __near unsigned short *)0x1BE) +#define TOM0L (*(volatile __near unsigned char *)0x1BE) +#define IICCTL00 (*(volatile __near unsigned char *)0x230) +#define IICCTL00_bit (*(volatile __near __bitf_T *)0x230) +#define SPT0 (((volatile __near __bitf_T *)0x230)->no0) +#define STT0 (((volatile __near __bitf_T *)0x230)->no1) +#define ACKE0 (((volatile __near __bitf_T *)0x230)->no2) +#define WTIM0 (((volatile __near __bitf_T *)0x230)->no3) +#define SPIE0 (((volatile __near __bitf_T *)0x230)->no4) +#define WREL0 (((volatile __near __bitf_T *)0x230)->no5) +#define LREL0 (((volatile __near __bitf_T *)0x230)->no6) +#define IICE0 (((volatile __near __bitf_T *)0x230)->no7) +#define IICCTL01 (*(volatile __near unsigned char *)0x231) +#define IICCTL01_bit (*(volatile __near __bitf_T *)0x231) +#define PRS0 (((volatile __near __bitf_T *)0x231)->no0) +#define DFC0 (((volatile __near __bitf_T *)0x231)->no2) +#define SMC0 (((volatile __near __bitf_T *)0x231)->no3) +#define DAD0 (((volatile __near __bitf_T *)0x231)->no4) +#define CLD0 (((volatile __near __bitf_T *)0x231)->no5) +#define WUP0 (((volatile __near __bitf_T *)0x231)->no7) +#define IICWL0 (*(volatile __near unsigned char *)0x232) +#define IICWH0 (*(volatile __near unsigned char *)0x233) +#define SVA0 (*(volatile __near unsigned char *)0x234) +#define CRCD (*(volatile __near unsigned short *)0x2FA) +#define P1 (*(volatile __near unsigned char *)0xFF01) +#define P1_bit (*(volatile __near __bitf_T *)0xFF01) +#define P2 (*(volatile __near unsigned char *)0xFF02) +#define P2_bit (*(volatile __near __bitf_T *)0xFF02) +#define P4 (*(volatile __near unsigned char *)0xFF04) +#define P4_bit (*(volatile __near __bitf_T *)0xFF04) +#define P6 (*(volatile __near unsigned char *)0xFF06) +#define P6_bit (*(volatile __near __bitf_T *)0xFF06) +#define P12 (*(volatile __near unsigned char *)0xFF0C) +#define P12_bit (*(volatile __near __bitf_T *)0xFF0C) +#define P13 (*(volatile __near unsigned char *)0xFF0D) +#define P13_bit (*(volatile __near __bitf_T *)0xFF0D) +#define SDR00 (*(volatile __near unsigned short *)0xFF10) +#define SIO00 (*(volatile __near unsigned char *)0xFF10) +#define TXD0 (*(volatile __near unsigned char *)0xFF10) +#define SDR01 (*(volatile __near unsigned short *)0xFF12) +#define RXD0 (*(volatile __near unsigned char *)0xFF12) +#define SIO01 (*(volatile __near unsigned char *)0xFF12) +#define TDR00 (*(volatile __near unsigned short *)0xFF18) +#define TDR01 (*(volatile __near unsigned short *)0xFF1A) +#define TDR01L (*(volatile __near unsigned char *)0xFF1A) +#define TDR01H (*(volatile __near unsigned char *)0xFF1B) +#define ADCR (*(volatile __near unsigned short *)0xFF1E) +#define ADCRH (*(volatile __near unsigned char *)0xFF1F) +#define PM1 (*(volatile __near unsigned char *)0xFF21) +#define PM1_bit (*(volatile __near __bitf_T *)0xFF21) +#define PM2 (*(volatile __near unsigned char *)0xFF22) +#define PM2_bit (*(volatile __near __bitf_T *)0xFF22) +#define PM4 (*(volatile __near unsigned char *)0xFF24) +#define PM4_bit (*(volatile __near __bitf_T *)0xFF24) +#define PM6 (*(volatile __near unsigned char *)0xFF26) +#define PM6_bit (*(volatile __near __bitf_T *)0xFF26) +#define ADM0 (*(volatile __near unsigned char *)0xFF30) +#define ADM0_bit (*(volatile __near __bitf_T *)0xFF30) +#define ADCE (((volatile __near __bitf_T *)0xFF30)->no0) +#define ADCS (((volatile __near __bitf_T *)0xFF30)->no7) +#define ADS (*(volatile __near unsigned char *)0xFF31) +#define ADS_bit (*(volatile __near __bitf_T *)0xFF31) +#define ADM1 (*(volatile __near unsigned char *)0xFF32) +#define ADM1_bit (*(volatile __near __bitf_T *)0xFF32) +#define KRCTL (*(volatile __near unsigned char *)0xFF34) +#define KRCTL_bit (*(volatile __near __bitf_T *)0xFF34) +#define KRF (*(volatile __near unsigned char *)0xFF35) +#define KRM0 (*(volatile __near unsigned char *)0xFF37) +#define KRM0_bit (*(volatile __near __bitf_T *)0xFF37) +#define EGP0 (*(volatile __near unsigned char *)0xFF38) +#define EGP0_bit (*(volatile __near __bitf_T *)0xFF38) +#define EGN0 (*(volatile __near unsigned char *)0xFF39) +#define EGN0_bit (*(volatile __near __bitf_T *)0xFF39) +#define IICA0 (*(volatile __near unsigned char *)0xFF50) +#define IICS0 (*(volatile __near unsigned char *)0xFF51) +#define IICS0_bit (*(volatile __near __bitf_T *)0xFF51) +#define SPD0 (((volatile __near __bitf_T *)0xFF51)->no0) +#define STD0 (((volatile __near __bitf_T *)0xFF51)->no1) +#define ACKD0 (((volatile __near __bitf_T *)0xFF51)->no2) +#define TRC0 (((volatile __near __bitf_T *)0xFF51)->no3) +#define COI0 (((volatile __near __bitf_T *)0xFF51)->no4) +#define EXC0 (((volatile __near __bitf_T *)0xFF51)->no5) +#define ALD0 (((volatile __near __bitf_T *)0xFF51)->no6) +#define MSTS0 (((volatile __near __bitf_T *)0xFF51)->no7) +#define IICF0 (*(volatile __near unsigned char *)0xFF52) +#define IICF0_bit (*(volatile __near __bitf_T *)0xFF52) +#define IICRSV0 (((volatile __near __bitf_T *)0xFF52)->no0) +#define STCEN0 (((volatile __near __bitf_T *)0xFF52)->no1) +#define IICBSY0 (((volatile __near __bitf_T *)0xFF52)->no6) +#define STCF0 (((volatile __near __bitf_T *)0xFF52)->no7) +#define TDR02 (*(volatile __near unsigned short *)0xFF64) +#define TDR03 (*(volatile __near unsigned short *)0xFF66) +#define TDR03L (*(volatile __near unsigned char *)0xFF66) +#define TDR03H (*(volatile __near unsigned char *)0xFF67) +#define ITMC (*(volatile __near unsigned short *)0xFF90) +#define CMC (*(volatile __near unsigned char *)0xFFA0) +#define CSC (*(volatile __near unsigned char *)0xFFA1) +#define CSC_bit (*(volatile __near __bitf_T *)0xFFA1) +#define HIOSTOP (((volatile __near __bitf_T *)0xFFA1)->no0) +#define MSTOP (((volatile __near __bitf_T *)0xFFA1)->no7) +#define OSTC (*(volatile __near unsigned char *)0xFFA2) +#define OSTC_bit (*(volatile __near __bitf_T *)0xFFA2) +#define OSTS (*(volatile __near unsigned char *)0xFFA3) +#define CKC (*(volatile __near unsigned char *)0xFFA4) +#define CKC_bit (*(volatile __near __bitf_T *)0xFFA4) +#define MCM0 (((volatile __near __bitf_T *)0xFFA4)->no4) +#define MCS (((volatile __near __bitf_T *)0xFFA4)->no5) +#define CKS0 (*(volatile __near unsigned char *)0xFFA5) +#define CKS0_bit (*(volatile __near __bitf_T *)0xFFA5) +#define PCLOE0 (((volatile __near __bitf_T *)0xFFA5)->no7) +#define RESF (*(volatile __near unsigned char *)0xFFA8) +#define LVIM (*(volatile __near unsigned char *)0xFFA9) +#define LVIM_bit (*(volatile __near __bitf_T *)0xFFA9) +#define LVIF (((volatile __near __bitf_T *)0xFFA9)->no0) +#define LVIOMSK (((volatile __near __bitf_T *)0xFFA9)->no1) +#define LVISEN (((volatile __near __bitf_T *)0xFFA9)->no7) +#define LVIS (*(volatile __near unsigned char *)0xFFAA) +#define LVIS_bit (*(volatile __near __bitf_T *)0xFFAA) +#define LVILV (((volatile __near __bitf_T *)0xFFAA)->no0) +#define LVIMD (((volatile __near __bitf_T *)0xFFAA)->no7) +#define WDTE (*(volatile __near unsigned char *)0xFFAB) +#define CRCIN (*(volatile __near unsigned char *)0xFFAC) +#define DSA0 (*(volatile __near unsigned char *)0xFFB0) +#define DSA1 (*(volatile __near unsigned char *)0xFFB1) +#define DRA0 (*(volatile __near unsigned short *)0xFFB2) +#define DRA0L (*(volatile __near unsigned char *)0xFFB2) +#define DRA0H (*(volatile __near unsigned char *)0xFFB3) +#define DRA1 (*(volatile __near unsigned short *)0xFFB4) +#define DRA1L (*(volatile __near unsigned char *)0xFFB4) +#define DRA1H (*(volatile __near unsigned char *)0xFFB5) +#define DBC0 (*(volatile __near unsigned short *)0xFFB6) +#define DBC0L (*(volatile __near unsigned char *)0xFFB6) +#define DBC0H (*(volatile __near unsigned char *)0xFFB7) +#define DBC1 (*(volatile __near unsigned short *)0xFFB8) +#define DBC1L (*(volatile __near unsigned char *)0xFFB8) +#define DBC1H (*(volatile __near unsigned char *)0xFFB9) +#define DMC0 (*(volatile __near unsigned char *)0xFFBA) +#define DMC0_bit (*(volatile __near __bitf_T *)0xFFBA) +#define DWAIT0 (((volatile __near __bitf_T *)0xFFBA)->no4) +#define DS0 (((volatile __near __bitf_T *)0xFFBA)->no5) +#define DRS0 (((volatile __near __bitf_T *)0xFFBA)->no6) +#define STG0 (((volatile __near __bitf_T *)0xFFBA)->no7) +#define DMC1 (*(volatile __near unsigned char *)0xFFBB) +#define DMC1_bit (*(volatile __near __bitf_T *)0xFFBB) +#define DWAIT1 (((volatile __near __bitf_T *)0xFFBB)->no4) +#define DS1 (((volatile __near __bitf_T *)0xFFBB)->no5) +#define DRS1 (((volatile __near __bitf_T *)0xFFBB)->no6) +#define STG1 (((volatile __near __bitf_T *)0xFFBB)->no7) +#define DRC0 (*(volatile __near unsigned char *)0xFFBC) +#define DRC0_bit (*(volatile __near __bitf_T *)0xFFBC) +#define DST0 (((volatile __near __bitf_T *)0xFFBC)->no0) +#define DEN0 (((volatile __near __bitf_T *)0xFFBC)->no7) +#define DRC1 (*(volatile __near unsigned char *)0xFFBD) +#define DRC1_bit (*(volatile __near __bitf_T *)0xFFBD) +#define DST1 (((volatile __near __bitf_T *)0xFFBD)->no0) +#define DEN1 (((volatile __near __bitf_T *)0xFFBD)->no7) +#define IF0 (*(volatile __near unsigned short *)0xFFE0) +#define IF0L (*(volatile __near unsigned char *)0xFFE0) +#define IF0L_bit (*(volatile __near __bitf_T *)0xFFE0) +#define IF0H (*(volatile __near unsigned char *)0xFFE1) +#define IF0H_bit (*(volatile __near __bitf_T *)0xFFE1) +#define WDTIIF (((volatile __near __bitf_T *)0xFFE0)->no0) +#define LVIIF (((volatile __near __bitf_T *)0xFFE0)->no1) +#define PIF0 (((volatile __near __bitf_T *)0xFFE0)->no2) +#define PIF1 (((volatile __near __bitf_T *)0xFFE0)->no3) +#define PIF2 (((volatile __near __bitf_T *)0xFFE0)->no4) +#define PIF3 (((volatile __near __bitf_T *)0xFFE0)->no5) +#define DMAIF0 (((volatile __near __bitf_T *)0xFFE0)->no6) +#define DMAIF1 (((volatile __near __bitf_T *)0xFFE0)->no7) +#define CSIIF00 (((volatile __near __bitf_T *)0xFFE1)->no0) +#define IICIF00 (((volatile __near __bitf_T *)0xFFE1)->no0) +#define STIF0 (((volatile __near __bitf_T *)0xFFE1)->no0) +#define CSIIF01 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define IICIF01 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define SRIF0 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define SREIF0 (((volatile __near __bitf_T *)0xFFE1)->no2) +#define TMIF01H (((volatile __near __bitf_T *)0xFFE1)->no3) +#define TMIF03H (((volatile __near __bitf_T *)0xFFE1)->no4) +#define IICAIF0 (((volatile __near __bitf_T *)0xFFE1)->no5) +#define TMIF00 (((volatile __near __bitf_T *)0xFFE1)->no6) +#define TMIF01 (((volatile __near __bitf_T *)0xFFE1)->no7) +#define IF1 (*(volatile __near unsigned short *)0xFFE2) +#define IF1L (*(volatile __near unsigned char *)0xFFE2) +#define IF1L_bit (*(volatile __near __bitf_T *)0xFFE2) +#define TMIF02 (((volatile __near __bitf_T *)0xFFE2)->no0) +#define TMIF03 (((volatile __near __bitf_T *)0xFFE2)->no1) +#define ADIF (((volatile __near __bitf_T *)0xFFE2)->no2) +#define TMKAIF (((volatile __near __bitf_T *)0xFFE2)->no3) +#define KRIF (((volatile __near __bitf_T *)0xFFE2)->no4) +#define MDIF (((volatile __near __bitf_T *)0xFFE2)->no5) +#define FLIF (((volatile __near __bitf_T *)0xFFE2)->no6) +#define MK0 (*(volatile __near unsigned short *)0xFFE4) +#define MK0L (*(volatile __near unsigned char *)0xFFE4) +#define MK0L_bit (*(volatile __near __bitf_T *)0xFFE4) +#define MK0H (*(volatile __near unsigned char *)0xFFE5) +#define MK0H_bit (*(volatile __near __bitf_T *)0xFFE5) +#define WDTIMK (((volatile __near __bitf_T *)0xFFE4)->no0) +#define LVIMK (((volatile __near __bitf_T *)0xFFE4)->no1) +#define PMK0 (((volatile __near __bitf_T *)0xFFE4)->no2) +#define PMK1 (((volatile __near __bitf_T *)0xFFE4)->no3) +#define PMK2 (((volatile __near __bitf_T *)0xFFE4)->no4) +#define PMK3 (((volatile __near __bitf_T *)0xFFE4)->no5) +#define DMAMK0 (((volatile __near __bitf_T *)0xFFE4)->no6) +#define DMAMK1 (((volatile __near __bitf_T *)0xFFE4)->no7) +#define CSIMK00 (((volatile __near __bitf_T *)0xFFE5)->no0) +#define IICMK00 (((volatile __near __bitf_T *)0xFFE5)->no0) +#define STMK0 (((volatile __near __bitf_T *)0xFFE5)->no0) +#define CSIMK01 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define IICMK01 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define SRMK0 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define SREMK0 (((volatile __near __bitf_T *)0xFFE5)->no2) +#define TMMK01H (((volatile __near __bitf_T *)0xFFE5)->no3) +#define TMMK03H (((volatile __near __bitf_T *)0xFFE5)->no4) +#define IICAMK0 (((volatile __near __bitf_T *)0xFFE5)->no5) +#define TMMK00 (((volatile __near __bitf_T *)0xFFE5)->no6) +#define TMMK01 (((volatile __near __bitf_T *)0xFFE5)->no7) +#define MK1 (*(volatile __near unsigned short *)0xFFE6) +#define MK1L (*(volatile __near unsigned char *)0xFFE6) +#define MK1L_bit (*(volatile __near __bitf_T *)0xFFE6) +#define TMMK02 (((volatile __near __bitf_T *)0xFFE6)->no0) +#define TMMK03 (((volatile __near __bitf_T *)0xFFE6)->no1) +#define ADMK (((volatile __near __bitf_T *)0xFFE6)->no2) +#define TMKAMK (((volatile __near __bitf_T *)0xFFE6)->no3) +#define KRMK (((volatile __near __bitf_T *)0xFFE6)->no4) +#define MDMK (((volatile __near __bitf_T *)0xFFE6)->no5) +#define FLMK (((volatile __near __bitf_T *)0xFFE6)->no6) +#define PR00 (*(volatile __near unsigned short *)0xFFE8) +#define PR00L (*(volatile __near unsigned char *)0xFFE8) +#define PR00L_bit (*(volatile __near __bitf_T *)0xFFE8) +#define PR00H (*(volatile __near unsigned char *)0xFFE9) +#define PR00H_bit (*(volatile __near __bitf_T *)0xFFE9) +#define WDTIPR0 (((volatile __near __bitf_T *)0xFFE8)->no0) +#define LVIPR0 (((volatile __near __bitf_T *)0xFFE8)->no1) +#define PPR00 (((volatile __near __bitf_T *)0xFFE8)->no2) +#define PPR01 (((volatile __near __bitf_T *)0xFFE8)->no3) +#define PPR02 (((volatile __near __bitf_T *)0xFFE8)->no4) +#define PPR03 (((volatile __near __bitf_T *)0xFFE8)->no5) +#define DMAPR00 (((volatile __near __bitf_T *)0xFFE8)->no6) +#define DMAPR01 (((volatile __near __bitf_T *)0xFFE8)->no7) +#define CSIPR000 (((volatile __near __bitf_T *)0xFFE9)->no0) +#define IICPR000 (((volatile __near __bitf_T *)0xFFE9)->no0) +#define STPR00 (((volatile __near __bitf_T *)0xFFE9)->no0) +#define CSIPR001 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define IICPR001 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define SRPR00 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define SREPR00 (((volatile __near __bitf_T *)0xFFE9)->no2) +#define TMPR001H (((volatile __near __bitf_T *)0xFFE9)->no3) +#define TMPR003H (((volatile __near __bitf_T *)0xFFE9)->no4) +#define IICAPR00 (((volatile __near __bitf_T *)0xFFE9)->no5) +#define TMPR000 (((volatile __near __bitf_T *)0xFFE9)->no6) +#define TMPR001 (((volatile __near __bitf_T *)0xFFE9)->no7) +#define PR01 (*(volatile __near unsigned short *)0xFFEA) +#define PR01L (*(volatile __near unsigned char *)0xFFEA) +#define PR01L_bit (*(volatile __near __bitf_T *)0xFFEA) +#define TMPR002 (((volatile __near __bitf_T *)0xFFEA)->no0) +#define TMPR003 (((volatile __near __bitf_T *)0xFFEA)->no1) +#define ADPR0 (((volatile __near __bitf_T *)0xFFEA)->no2) +#define TMKAPR0 (((volatile __near __bitf_T *)0xFFEA)->no3) +#define KRPR0 (((volatile __near __bitf_T *)0xFFEA)->no4) +#define MDPR0 (((volatile __near __bitf_T *)0xFFEA)->no5) +#define FLPR0 (((volatile __near __bitf_T *)0xFFEA)->no6) +#define PR10 (*(volatile __near unsigned short *)0xFFEC) +#define PR10L (*(volatile __near unsigned char *)0xFFEC) +#define PR10L_bit (*(volatile __near __bitf_T *)0xFFEC) +#define PR10H (*(volatile __near unsigned char *)0xFFED) +#define PR10H_bit (*(volatile __near __bitf_T *)0xFFED) +#define WDTIPR1 (((volatile __near __bitf_T *)0xFFEC)->no0) +#define LVIPR1 (((volatile __near __bitf_T *)0xFFEC)->no1) +#define PPR10 (((volatile __near __bitf_T *)0xFFEC)->no2) +#define PPR11 (((volatile __near __bitf_T *)0xFFEC)->no3) +#define PPR12 (((volatile __near __bitf_T *)0xFFEC)->no4) +#define PPR13 (((volatile __near __bitf_T *)0xFFEC)->no5) +#define DMAPR10 (((volatile __near __bitf_T *)0xFFEC)->no6) +#define DMAPR11 (((volatile __near __bitf_T *)0xFFEC)->no7) +#define CSIPR100 (((volatile __near __bitf_T *)0xFFED)->no0) +#define IICPR100 (((volatile __near __bitf_T *)0xFFED)->no0) +#define STPR10 (((volatile __near __bitf_T *)0xFFED)->no0) +#define CSIPR101 (((volatile __near __bitf_T *)0xFFED)->no1) +#define IICPR101 (((volatile __near __bitf_T *)0xFFED)->no1) +#define SRPR10 (((volatile __near __bitf_T *)0xFFED)->no1) +#define SREPR10 (((volatile __near __bitf_T *)0xFFED)->no2) +#define TMPR101H (((volatile __near __bitf_T *)0xFFED)->no3) +#define TMPR103H (((volatile __near __bitf_T *)0xFFED)->no4) +#define IICAPR10 (((volatile __near __bitf_T *)0xFFED)->no5) +#define TMPR100 (((volatile __near __bitf_T *)0xFFED)->no6) +#define TMPR101 (((volatile __near __bitf_T *)0xFFED)->no7) +#define PR11 (*(volatile __near unsigned short *)0xFFEE) +#define PR11L (*(volatile __near unsigned char *)0xFFEE) +#define PR11L_bit (*(volatile __near __bitf_T *)0xFFEE) +#define TMPR102 (((volatile __near __bitf_T *)0xFFEE)->no0) +#define TMPR103 (((volatile __near __bitf_T *)0xFFEE)->no1) +#define ADPR1 (((volatile __near __bitf_T *)0xFFEE)->no2) +#define TMKAPR1 (((volatile __near __bitf_T *)0xFFEE)->no3) +#define KRPR1 (((volatile __near __bitf_T *)0xFFEE)->no4) +#define MDPR1 (((volatile __near __bitf_T *)0xFFEE)->no5) +#define FLPR1 (((volatile __near __bitf_T *)0xFFEE)->no6) +#define MDAL (*(volatile __near unsigned short *)0xFFF0) +#define MULA (*(volatile __near unsigned short *)0xFFF0) +#define MDAH (*(volatile __near unsigned short *)0xFFF2) +#define MULB (*(volatile __near unsigned short *)0xFFF2) +#define MDBH (*(volatile __near unsigned short *)0xFFF4) +#define MULOH (*(volatile __near unsigned short *)0xFFF4) +#define MDBL (*(volatile __near unsigned short *)0xFFF6) +#define MULOL (*(volatile __near unsigned short *)0xFFF6) +#define PMC (*(volatile __near unsigned char *)0xFFFE) +#define PMC_bit (*(volatile __near __bitf_T *)0xFFFE) +#define MAA (((volatile __near __bitf_T *)0xFFFE)->no0) + + +#define INTWDTI 0x0004 +#define INTLVI 0x0006 +#define INTP0 0x0008 +#define INTP1 0x000A +#define INTP2 0x000C +#define INTP3 0x000E +#define INTDMA0 0x0010 +#define INTDMA1 0x0012 +#define INTCSI00 0x0014 +#define INTIIC00 0x0014 +#define INTST0 0x0014 +#define INTCSI01 0x0016 +#define INTIIC01 0x0016 +#define INTSR0 0x0016 +#define INTSRE0 0x0018 +#define INTTM01H 0x001A +#define INTTM03H 0x001C +#define INTIICA0 0x001E +#define INTTM00 0x0020 +#define INTTM01 0x0022 +#define INTTM02 0x0024 +#define INTTM03 0x0026 +#define INTAD 0x0028 +#define INTIT 0x002A +#define INTKR 0x002C +#define INTMD 0x002E +#define INTFL 0x0030 + +#endif diff --git a/app/r_cg_adc.c b/app/r_cg_adc.c new file mode 100644 index 0000000..90502a9 --- /dev/null +++ b/app/r_cg_adc.c @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_adc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_ADC_Create +* Description : This function initializes the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Create(void) +{ + ADCEN = 1U; /* supply AD clock */ + ADM0 = _00_AD_ADM0_INITIALVALUE; /* disable AD conversion and clear ADM0 register */ + ADMK = 1U; /* disable INTAD interrupt */ + ADIF = 0U; /* clear INTAD interrupt flag */ + /* Set INTAD low priority */ + ADPR1 = 1U; + ADPR0 = 1U; + /* The reset status of ADPC is analog input, so it's unnecessary to set. */ + /* Set ANI0 - ANI1 pin as analog input */ + PM2 |= 0x03U; + ADM0 = _08_AD_CONVERSION_CLOCK_32 | _00_AD_TIME_MODE_NORMAL_1 | _00_AD_OPERMODE_SELECT; + ADM1 = _80_AD_TRIGGER_HARDWARE_NOWAIT | _20_AD_CONVMODE_ONESELECT | _00_AD_TRIGGER_INTTM01; + ADM2 = _00_AD_POSITIVE_VDD | _00_AD_NEGATIVE_VSS | _00_AD_AREA_MODE_1 | _00_AD_RESOLUTION_10BIT; + ADUL = _FF_AD_ADUL_VALUE; + ADLL = _00_AD_ADLL_VALUE; + ADS = _01_AD_INPUT_CHANNEL_1; + ADCE = 1U; /* enable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Start +* Description : This function starts the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Start(void) +{ + ADIF = 0U; /* clear INTAD interrupt flag */ + ADMK = 0U; /* enable INTAD interrupt */ + ADCS = 1U; /* enable AD conversion */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Stop +* Description : This function stops the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Stop(void) +{ + ADCS = 0U; /* disable AD conversion */ + ADMK = 1U; /* disable INTAD interrupt */ + ADIF = 0U; /* clear INTAD interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Set_OperationOn +* Description : This function enables comparator operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Set_OperationOn(void) +{ + ADCE = 1U; /* enable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Set_OperationOff +* Description : This function stops comparator operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Set_OperationOff(void) +{ + ADCE = 0U; /* disable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Get_Result +* Description : This function returns the conversion result in the buffer. +* Arguments : buffer - +* the address where to write the conversion result +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Get_Result(uint16_t * const buffer) +{ + *buffer = (uint16_t)(ADCR >> 6U); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_adc.h b/app/r_cg_adc.h new file mode 100644 index 0000000..3c094d4 --- /dev/null +++ b/app/r_cg_adc.h @@ -0,0 +1,179 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef ADC_H +#define ADC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Peripheral enable register 0 (PER0) +*/ +/* Control of AD converter input clock (ADCEN) */ +#define _00_AD_CLOCK_STOP (0x00U) /* stop supply of input clock */ +#define _20_AD_CLOCK_SUPPLY (0x20U) /* supply input clock */ + +/* + AD converter mode register 0 (ADM0) +*/ +#define _00_AD_ADM0_INITIALVALUE (0x00U) +/* AD conversion operation control (ADCS) */ +#define _80_AD_CONVERSION_ENABLE (0x80U) /* enable AD conversion operation control */ +#define _00_AD_CONVERSION_DISABLE (0x00U) /* disable AD conversion operation control */ +/* Specification of AD conversion operation mode (ADMD) */ +#define _00_AD_OPERMODE_SELECT (0x00U) /* select operation mode */ +#define _40_AD_OPERMODE_SCAN (0x40U) /* scan operation mode */ +/* AD conversion clock selection (FR2 - FR0) */ +#define _00_AD_CONVERSION_CLOCK_64 (0x00U) /* fCLK/64 */ +#define _08_AD_CONVERSION_CLOCK_32 (0x08U) /* fCLK/32 */ +#define _10_AD_CONVERSION_CLOCK_16 (0x10U) /* fCLK/16 */ +#define _18_AD_CONVERSION_CLOCK_8 (0x18U) /* fCLK/8 */ +#define _20_AD_CONVERSION_CLOCK_6 (0x20U) /* fCLK/6 */ +#define _28_AD_CONVERSION_CLOCK_5 (0x28U) /* fCLK/5 */ +#define _30_AD_CONVERSION_CLOCK_4 (0x30U) /* fCLK/4 */ +#define _38_AD_CONVERSION_CLOCK_2 (0x38U) /* fCLK/2 */ +/* Specification AD conversion time mode (LV1, LV0) */ +#define _00_AD_TIME_MODE_NORMAL_1 (0x00U) /* normal 1 mode */ +#define _02_AD_TIME_MODE_NORMAL_2 (0x02U) /* normal 2 mode */ +#define _04_AD_TIME_MODE_LOWVOLTAGE_1 (0x04U) /* low-voltage 1 mode */ +#define _06_AD_TIME_MODE_LOWVOLTAGE_2 (0x06U) /* low-voltage 2 mode */ +/* AD comparator operation control (ADCE) */ +#define _01_AD_COMPARATOR_ENABLE (0x01U) /* enable comparator operation control */ +#define _00_AD_COMPARATOR_DISABLE (0x00U) /* disable comparator operation control */ + +/* + Analog input channel specification register (ADS) +*/ +/* Specification of analog input channel (ADISS, ADS4 - ADS0) */ +/* Select mode */ +#define _00_AD_INPUT_CHANNEL_0 (0x00U) /* ANI0 */ +#define _01_AD_INPUT_CHANNEL_1 (0x01U) /* ANI1 */ +#define _02_AD_INPUT_CHANNEL_2 (0x02U) /* ANI2 */ +#define _03_AD_INPUT_CHANNEL_3 (0x03U) /* ANI3 */ +#define _10_AD_INPUT_CHANNEL_16 (0x10U) /* ANI16 */ +#define _11_AD_INPUT_CHANNEL_17 (0x11U) /* ANI17 */ +#define _12_AD_INPUT_CHANNEL_18 (0x12U) /* ANI18 */ +#define _13_AD_INPUT_CHANNEL_19 (0x13U) /* ANI19 */ +#define _14_AD_INPUT_CHANNEL_20 (0x14U) /* ANI20 */ +#define _15_AD_INPUT_CHANNEL_21 (0x15U) /* ANI21 */ +#define _16_AD_INPUT_CHANNEL_22 (0x16U) /* ANI22 */ +#define _80_AD_INPUT_TEMPERSENSOR_0 (0x80U) /* temperature sensor 0 output is used to be the input channel */ +#define _81_AD_INPUT_INTERREFVOLT (0x81U) /* internal reference voltage output is used to be the input channel */ +/* Scan mode */ +#define _00_AD_INPUT_CHANNEL_0_3 (0x00U) /* ANI0 - ANI3 */ + +/* + AD converter mode register 1 (ADM1) +*/ +/* AD trigger mode selection (ADTMD1, ADTMD0) */ +#define _00_AD_TRIGGER_SOFTWARE (0x00U) /* software trigger mode */ +#define _80_AD_TRIGGER_HARDWARE_NOWAIT (0x80U) /* hardware trigger mode (no wait) */ +#define _C0_AD_TRIGGER_HARDWARE_WAIT (0xC0U) /* hardware trigger mode (wait) */ +/* AD convertion mode selection (ADSCM) */ +#define _00_AD_CONVMODE_CONSELECT (0x00U) /* continuous convertion mode */ +#define _20_AD_CONVMODE_ONESELECT (0x20U) /* oneshot convertion mode */ +/* Trigger signal selection (ADTRS1, ADTRS0) */ +#define _00_AD_TRIGGER_INTTM01 (0x00U) /* INTTM01 */ +#define _03_AD_TRIGGER_INTIT (0x03U) /* INTIT */ + +/* + AD converter mode register 2 (ADM2) +*/ +/* AD VREF(+) selection (ADREFP1, ADREFP0) */ +#define _00_AD_POSITIVE_VDD (0x00U) /* use VDD as VREF(+) */ +#define _40_AD_POSITIVE_AVREFP (0x40U) /* use AVREFP as VREF(+) */ +#define _80_AD_POSITIVE_INTERVOLT (0x80U) /* use internal voltage as VREF(+) */ +/* AD VREF(-) selection (ADREFM) */ +#define _00_AD_NEGATIVE_VSS (0x00U) /* use VSS as VREF(-) */ +#define _20_AD_NEGATIVE_AVREFM (0x20U) /* use AVREFM as VREF(-) */ +/* AD conversion result upper/lower bound value selection (ADRCK) */ +#define _00_AD_AREA_MODE_1 (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */ +#define _08_AD_AREA_MODE_2_3 (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */ +/* AD wakeup function selection (AWC) */ +#define _00_AD_WAKEUP_OFF (0x00U) /* stop wakeup function */ +#define _04_AD_WAKEUP_ON (0x04U) /* use wakeup function */ +/* AD resolution selection (ADTYP) */ +#define _00_AD_RESOLUTION_10BIT (0x00U) /* 10 bits */ +#define _01_AD_RESOLUTION_8BIT (0x01U) /* 8 bits */ + +/* + AD test function register (ADTES) +*/ +/* AD test mode signal (ADTES1, ADTES0) */ +#define _00_AD_NORMAL_INPUT (0x00U) /* normal mode */ +#define _02_AD_TEST_AVREFM (0x02U) /* use AVREFM as test signal */ +#define _03_AD_TEST_AVREFP (0x03U) /* use AVREFP as test signal */ + +/* + AD port configuration register (ADPC) +*/ +/* Analog input/digital input switching (ADPC3 - ADPC0) */ +#define _00_AD_ADPC_4ANALOG (0x00U) /* ANI0 - ANI3 */ +#define _04_AD_ADPC_3ANALOG (0x04U) /* ANI0 - ANI2 */ +#define _03_AD_ADPC_2ANALOG (0x03U) /* ANI0 - ANI1 */ +#define _02_AD_ADPC_1ANALOG (0x02U) /* ANI0 */ +#define _01_AD_ADPC_0ANALOG (0x01U) /* ANI0 - ANI4 (all digital) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Upper bound (ADUL) value */ +#define _FF_AD_ADUL_VALUE (0xFFU) +/* Upper bound (ADLL) value */ +#define _00_AD_ADLL_VALUE (0x00U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef enum +{ + ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL16 = 16U, + ADCHANNEL17, ADCHANNEL18, ADCHANNEL19, ADCHANNEL20, ADCHANNEL21, + ADCHANNEL22, ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT +} ad_channel_t; +typedef enum +{ + ADNORMALINPUT, + ADAVREFM = 2U, + ADAVREFP +} test_channel_t; + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_ADC_Create(void); +void R_ADC_Start(void); +void R_ADC_Stop(void); +void R_ADC_Set_OperationOn(void); +void R_ADC_Set_OperationOff(void); +void R_ADC_Get_Result(uint16_t * const buffer); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_adc_user.c b/app/r_cg_adc_user.c new file mode 100644 index 0000000..ef5c484 --- /dev/null +++ b/app/r_cg_adc_user.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_adc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_adc_interrupt(vect=INTAD) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +uint16_t g_AdVal[3]; +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_adc_interrupt +* Description : This function is INTAD interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_adc_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + //R_ADC_Get_Result(g_AdVal); + + switch (ADS) + { + /* + case _02_AD_INPUT_CHANNEL_2: + R_ADC_Get_Result(g_AdVal+1); + ADS = _01_AD_INPUT_CHANNEL_1; + break; + */ + case _01_AD_INPUT_CHANNEL_1: + R_ADC_Get_Result(g_AdVal); + //ADS = _02_AD_INPUT_CHANNEL_2; + break; + default: + ADS = _01_AD_INPUT_CHANNEL_1; + break; + + } + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_cgc.c b/app/r_cg_cgc.c new file mode 100644 index 0000000..2c6be9f --- /dev/null +++ b/app/r_cg_cgc.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + /* Set fMX */ + CMC = _00_CGC_HISYS_PORT | _00_CGC_SYSOSC_DEFAULT; + MSTOP = 1U; + /* Set fMAIN */ + MCM0 = 0U; + OSMC = _00_CGC_IT_CLK_NO; + /* Set fIH */ + HIOSTOP = 0U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_cgc.h b/app/r_cg_cgc.h new file mode 100644 index 0000000..c90966f --- /dev/null +++ b/app/r_cg_cgc.h @@ -0,0 +1,146 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Clock operation mode control register (CMC) +*/ +/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */ +#define _C0_CGC_HISYS_PIN (0xC0U) +#define _00_CGC_HISYS_PORT (0x00U) /* X1, X2 as I/O port */ +#define _40_CGC_HISYS_OSC (0x40U) /* X1, X2 as crystal/ceramic resonator connection */ +#define _80_CGC_HISYS_PORT1 (0x80U) /* X1, X2 as I/O port */ +#define _C0_CGC_HISYS_EXT (0xC0U) /* X1 as I/O port, X2 as external clock input */ +/* Control of X1 high-speed system clock oscillation frequency (AMPH) */ +#define _00_CGC_SYSOSC_DEFAULT (0x00U) +#define _00_CGC_SYSOSC_UNDER10M (0x00U) /* fX <= 10MHz */ +#define _01_CGC_SYSOSC_OVER10M (0x01U) /* fX > 10MHz */ + +/* + Clock operation status control register (CSC) +*/ +/* Control of high-speed system clock operation (MSTOP) */ +#define _00_CGC_HISYS_OPER (0x00U) /* X1 oscillator/external clock operating */ +#define _80_CGC_HISYS_STOP (0x80U) /* X1 oscillator/external clock stopped */ +/* High-speed OCO operation (HIOSTOP) */ +#define _00_CGC_HIO_OPER (0x00U) /* high-speed OCO operating */ +#define _01_CGC_HIO_STOP (0x01U) /* high-speed OCO stopped */ + +/* + Oscillation stabilization time counter status register (OSTC) +*/ +/* Oscillation stabilization time status (MOST18 - MOST8) */ +#define _00_CGC_OSCSTAB_STA0 (0x00U) /* < 2^8/fX */ +#define _80_CGC_OSCSTAB_STA8 (0x80U) /* 2^8/fX */ +#define _C0_CGC_OSCSTAB_STA9 (0xC0U) /* 2^9/fX */ +#define _E0_CGC_OSCSTAB_STA10 (0xE0U) /* 2^10/fX */ +#define _F0_CGC_OSCSTAB_STA11 (0xF0U) /* 2^11/fX */ +#define _F8_CGC_OSCSTAB_STA13 (0xF8U) /* 2^13/fX */ +#define _FC_CGC_OSCSTAB_STA15 (0xFCU) /* 2^15/fX */ +#define _FE_CGC_OSCSTAB_STA17 (0xFEU) /* 2^17/fX */ +#define _FF_CGC_OSCSTAB_STA18 (0xFFU) /* 2^18/fX */ + +/* + Oscillation stabilization time select register (OSTS) +*/ +/* Oscillation stabilization time selection (OSTS2 - OSTS0) */ +#define _00_CGC_OSCSTAB_SEL8 (0x00U) /* 2^8/fX */ +#define _01_CGC_OSCSTAB_SEL9 (0x01U) /* 2^9/fX */ +#define _02_CGC_OSCSTAB_SEL10 (0x02U) /* 2^10/fX */ +#define _03_CGC_OSCSTAB_SEL11 (0x03U) /* 2^11/fX */ +#define _04_CGC_OSCSTAB_SEL13 (0x04U) /* 2^13/fX */ +#define _05_CGC_OSCSTAB_SEL15 (0x05U) /* 2^15/fX */ +#define _06_CGC_OSCSTAB_SEL17 (0x06U) /* 2^17/fX */ +#define _07_CGC_OSCSTAB_SEL18 (0x07U) /* 2^18/fX */ + +/* + System clock control register (CKC) +*/ +/* Status of Main system clock fMAIN (MCS) */ +#define _00_CGC_MAINCLK_HIO (0x00U) /* high-speed OCO clock (fIH) */ +#define _20_CGC_MAINCLK_HISYS (0x20U) /* high-speed system clock (fMX) */ +/* Selection of Main system clock fMAIN (MCM0) */ +#define _00_CGC_MAINCLK_SELHIO (0x00U) /* high-speed OCO clock (fIH) */ +#define _10_CGC_MAINCLK_SELHISYS (0x10U) /* high-speed system clock (fMX) */ + +/* + Operation speed mode control register (OSMC) +*/ +/* Interval timer unit input clock supply (WUTMMCK0) */ +#define _00_CGC_IT_CLK_NO (0x00U) /* stop */ +#define _10_CGC_IT_CLK_FIL (0x10U) /* use fIL clcok */ + +/* + Illegal memory access detection control register (IAWCTL) +*/ +/* Illegal memory access detection control (IAWEN) */ +#define _00_CGC_ILLEGAL_ACCESS_OFF (0x00U) /* disables illegal memory access detection */ +#define _80_CGC_ILLEGAL_ACCESS_ON (0x80U) /* enables illegal memory access detection */ +/* RAM guard area (GRAM1, GRAM0) */ +#define _00_CGC_RAM_GUARD_OFF (0x00U) /* invalid, it is possible to write RAM */ +#define _10_CGC_RAM_GUARD_ARAE0 (0x10U) /* 128 bytes from RAM bottom address */ +#define _20_CGC_RAM_GUARD_ARAE1 (0x20U) /* 256 bytes from RAM bottom address */ +#define _30_CGC_RAM_GUARD_ARAE2 (0x30U) /* 512 bytes from RAM bottom address */ +/* PORT register guard (GPORT) */ +#define _00_CGC_PORT_GUARD_OFF (0x00U) /* invalid, it is possible to write PORT register */ +#define _04_CGC_PORT_GUARD_ON (0x04U) /* valid, it is impossible to write PORT register, but possible for read */ +/* Interrupt register guard (GINT) */ +#define _00_CGC_INT_GUARD_OFF (0x00U) /* invalid, it is possible to write interrupt register */ +#define _02_CGC_INT_GUARD_ON (0x02U) /* valid, impossible to write interrupt register, but possible for read */ +/* CSC register guard (GCSC) */ +#define _00_CGC_CSC_GUARD_OFF (0x00U) /* invalid, it is possible to write CSC register */ +#define _01_CGC_CSC_GUARD_ON (0x01U) /* valid, it is impossible to write CSC register, but possible for read */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef enum +{ + HIOCLK, + SYSX1CLK, + SYSEXTCLK +} clock_mode_t; + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); +void R_CGC_Get_ResetSource(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_cgc_user.c b/app/r_cg_cgc_user.c new file mode 100644 index 0000000..0cee857 --- /dev/null +++ b/app/r_cg_cgc_user.c @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Get_ResetSource +* Description : This function process of Reset. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Get_ResetSource(void) +{ + uint8_t reset_flag = RESF; + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_macrodriver.h b/app/r_cg_macrodriver.h new file mode 100644 index 0000000..ece6276 --- /dev/null +++ b/app/r_cg_macrodriver.h @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements general head file. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef STATUS_H +#define STATUS_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "iodefine.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ +#define DI __DI +#define EI __EI +#define HALT __halt +#define NOP __nop +#define STOP __stop +#define BRK __brk + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ +#define MD_OVERRUN (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error agrument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef unsigned short MD_STATUS; +#define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif diff --git a/app/r_cg_port.c b/app/r_cg_port.c new file mode 100644 index 0000000..4c6fd20 --- /dev/null +++ b/app/r_cg_port.c @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + P1 = _02_Pn1_OUTPUT_1 | _04_Pn2_OUTPUT_1 | _08_Pn3_OUTPUT_1 | _00_Pn4_OUTPUT_0; + PU4 = _00_PUn0_PULLUP_OFF; + PMC1 = _00_PMCn0_DI_ON | _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _00_PMCn3_DI_ON | _00_PMCn4_DI_ON | _E0_PMC1_DEFAULT; + ADPC = _04_ADPC_DI_ON; + PM1 = _01_PMn0_MODE_INPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | + _00_PMn4_MODE_OUTPUT | _E0_PM1_DEFAULT; + PM2 = _01_PMn0_NOT_USE | _02_PMn1_NOT_USE | _04_PMn2_NOT_USE | _08_PMn3_MODE_INPUT | _F0_PM2_DEFAULT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_port.h b/app/r_cg_port.h new file mode 100644 index 0000000..3c2636c --- /dev/null +++ b/app/r_cg_port.h @@ -0,0 +1,200 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Mode Register (PMm) +*/ +/* Pmn pin I/O mode selection (PMm7 - PMm0) */ +#define _01_PMn0_NOT_USE (0x01U) /* not use Pn0 as digital I/O */ +#define _01_PMn0_MODE_INPUT (0x01U) /* use Pn0 as input mode */ +#define _00_PMn0_MODE_OUTPUT (0x00U) /* use Pn0 as output mode */ +#define _02_PMn1_NOT_USE (0x02U) /* not use Pn1 as digital I/O */ +#define _02_PMn1_MODE_INPUT (0x02U) /* use Pn1 as input mode */ +#define _00_PMn1_MODE_OUTPUT (0x00U) /* use Pn1 as output mode */ +#define _04_PMn2_NOT_USE (0x04U) /* not use Pn2 as digital I/O */ +#define _04_PMn2_MODE_INPUT (0x04U) /* use Pn2 as input mode */ +#define _00_PMn2_MODE_OUTPUT (0x00U) /* use Pn2 as output mode */ +#define _08_PMn3_NOT_USE (0x08U) /* not use Pn3 as digital I/O */ +#define _08_PMn3_MODE_INPUT (0x08U) /* use Pn3 as input mode */ +#define _00_PMn3_MODE_OUTPUT (0x00U) /* use Pn3 as output mode */ +#define _10_PMn4_NOT_USE (0x10U) /* not use Pn4 as digital I/O */ +#define _10_PMn4_MODE_INPUT (0x10U) /* use Pn4 as input mode */ +#define _00_PMn4_MODE_OUTPUT (0x00U) /* use Pn4 as output mode */ +#define _20_PMn5_NOT_USE (0x20U) /* not use Pn5 as digital I/O */ +#define _20_PMn5_MODE_INPUT (0x20U) /* use Pn5 as input mode */ +#define _00_PMn5_MODE_OUTPUT (0x00U) /* use Pn5 as output mode */ +#define _40_PMn6_NOT_USE (0x40U) /* not use Pn6 as digital I/O */ +#define _40_PMn6_MODE_INPUT (0x40U) /* use Pn6 as input mode */ +#define _00_PMn6_MODE_OUTPUT (0x00U) /* use Pn6 as output mode */ +#define _80_PMn7_NOT_USE (0x80U) /* not use Pn7 as digital I/O */ +#define _80_PMn7_MODE_INPUT (0x80U) /* use Pn7 as input mode */ +#define _00_PMn7_MODE_OUTPUT (0x00U) /* use Pn7 as output mode */ + +/* + Port Register (Pm) +*/ +/* Pmn pin data (Pm0 to Pm7) */ +#define _00_Pn0_OUTPUT_0 (0x00U) /* Pn0 output 0 */ +#define _01_Pn0_OUTPUT_1 (0x01U) /* Pn0 output 1 */ +#define _00_Pn1_OUTPUT_0 (0x00U) /* Pn1 output 0 */ +#define _02_Pn1_OUTPUT_1 (0x02U) /* Pn1 output 1 */ +#define _00_Pn2_OUTPUT_0 (0x00U) /* Pn2 output 0 */ +#define _04_Pn2_OUTPUT_1 (0x04U) /* Pn2 output 1 */ +#define _00_Pn3_OUTPUT_0 (0x00U) /* Pn3 output 0 */ +#define _08_Pn3_OUTPUT_1 (0x08U) /* Pn3 output 1 */ +#define _00_Pn4_OUTPUT_0 (0x00U) /* Pn4 output 0 */ +#define _10_Pn4_OUTPUT_1 (0x10U) /* Pn4 output 1 */ +#define _00_Pn5_OUTPUT_0 (0x00U) /* Pn5 output 0 */ +#define _20_Pn5_OUTPUT_1 (0x20U) /* Pn5 output 1 */ +#define _00_Pn6_OUTPUT_0 (0x00U) /* Pn6 output 0 */ +#define _40_Pn6_OUTPUT_1 (0x40U) /* Pn6 output 1 */ +#define _00_Pn7_OUTPUT_0 (0x00U) /* Pn7 output 0 */ +#define _80_Pn7_OUTPUT_1 (0x80U) /* Pn7 output 1 */ + +/* + Pull-up Resistor Option Register (PUm) +*/ +/* Pmn pin on-chip pull-up resistor selection (PUmn) */ +#define _00_PUn0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */ +#define _01_PUn0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */ +#define _00_PUn1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */ +#define _02_PUn1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */ +#define _00_PUn2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */ +#define _04_PUn2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */ +#define _00_PUn3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */ +#define _08_PUn3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */ +#define _00_PUn4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */ +#define _10_PUn4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */ +#define _00_PUn5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */ +#define _20_PUn5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */ +#define _00_PUn6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */ +#define _40_PUn6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */ +#define _00_PUn7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */ +#define _80_PUn7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */ + +/* + Port Input Mode Register (PIMm) +*/ +/* Pmn pin input buffer selection (PIMmn) */ +#define _00_PIMn0_TTL_OFF (0x00U) /* set Pn0 normal input buffer */ +#define _01_PIMn0_TTL_ON (0x01U) /* set Pn0 TTL input buffer */ +#define _00_PIMn1_TTL_OFF (0x00U) /* set Pn1 normal input buffer */ +#define _02_PIMn1_TTL_ON (0x02U) /* set Pn1 TTL input buffer */ +#define _00_PIMn2_TTL_OFF (0x00U) /* set Pn2 normal input buffer */ +#define _04_PIMn2_TTL_ON (0x04U) /* set Pn2 TTL input buffer */ +#define _00_PIMn3_TTL_OFF (0x00U) /* set Pn3 normal input buffer */ +#define _08_PIMn3_TTL_ON (0x08U) /* set Pn3 TTL input buffer */ +#define _00_PIMn4_TTL_OFF (0x00U) /* set Pn4 normal input buffer */ +#define _10_PIMn4_TTL_ON (0x10U) /* set Pn4 TTL input buffer */ +#define _00_PIMn5_TTL_OFF (0x00U) /* set Pn5 normal input buffer */ +#define _20_PIMn5_TTL_ON (0x20U) /* set Pn5 TTL input buffer */ +#define _00_PIMn6_TTL_OFF (0x00U) /* set Pn6 normal input buffer */ +#define _40_PIMn6_TTL_ON (0x40U) /* set Pn6 TTL input buffer */ +#define _00_PIMn7_TTL_OFF (0x00U) /* set Pn7 normal input buffer */ +#define _80_PIMn7_TTL_ON (0x80U) /* set Pn7 TTL input buffer */ + +/* + Port Output Mode Register (POMm) +*/ +/* Pmn pin output mode selection (POMmn) */ +#define _00_POMn0_NCH_OFF (0x00U) /* set Pn0 output normal mode */ +#define _01_POMn0_NCH_ON (0x01U) /* set Pn0 output N-ch open-drain mode */ +#define _00_POMn1_NCH_OFF (0x00U) /* set Pn1 output normal mode */ +#define _02_POMn1_NCH_ON (0x02U) /* set Pn1 output N-ch open-drain mode */ +#define _00_POMn2_NCH_OFF (0x00U) /* set Pn2 output normal mode */ +#define _04_POMn2_NCH_ON (0x04U) /* set Pn2 output N-ch open-drain mode */ +#define _00_POMn3_NCH_OFF (0x00U) /* set Pn3 output normal mode */ +#define _08_POMn3_NCH_ON (0x08U) /* set Pn3 output N-ch open-drain mode */ +#define _00_POMn4_NCH_OFF (0x00U) /* set Pn4 output normal mode */ +#define _10_POMn4_NCH_ON (0x10U) /* set Pn4 output N-ch open-drain mode */ +#define _00_POMn5_NCH_OFF (0x00U) /* set Pn5 output normal mode */ +#define _20_POMn5_NCH_ON (0x20U) /* set Pn5 output N-ch open-drain mode */ +#define _00_POMn6_NCH_OFF (0x00U) /* set Pn6 output normal mode */ +#define _40_POMn6_NCH_ON (0x40U) /* set Pn6 output N-ch open-drain mode */ +#define _00_POMn7_NCH_OFF (0x00U) /* set Pn7 output normal mode */ +#define _80_POMn7_NCH_ON (0x80U) /* set Pn7 output N-ch open-drain mode */ + +/* + Port Operation Mode Register (PMCm) +*/ +/* Pmn pin digital input buffer selection (PMCmn) */ +#define _01_PMCn0_NOT_USE (0x01U) /* not use Pn0 digital input */ +#define _00_PMCn0_DI_ON (0x00U) /* enable Pn0 digital input */ +#define _02_PMCn1_NOT_USE (0x02U) /* not use Pn1 digital input */ +#define _00_PMCn1_DI_ON (0x00U) /* enable Pn1 digital input */ +#define _04_PMCn2_NOT_USE (0x04U) /* not use Pn2 digital input */ +#define _00_PMCn2_DI_ON (0x00U) /* enable Pn2 digital input */ +#define _08_PMCn3_NOT_USE (0x08U) /* not use Pn3 digital input */ +#define _00_PMCn3_DI_ON (0x00U) /* enable Pn3 digital input */ +#define _10_PMCn4_NOT_USE (0x10U) /* not use Pn4 digital input */ +#define _00_PMCn4_DI_ON (0x00U) /* enable Pn4 digital input */ +#define _20_PMCn5_NOT_USE (0x20U) /* not use Pn5 digital input */ +#define _00_PMCn5_DI_ON (0x00U) /* enable Pn5 digital input */ +#define _40_PMCn6_NOT_USE (0x40U) /* not use Pn6 digital input */ +#define _00_PMCn6_DI_ON (0x00U) /* enable Pn6 digital input */ +#define _80_PMCn7_NOT_USE (0x80U) /* not use Pn7 digital input */ +#define _00_PMCn7_DI_ON (0x00U) /* enable Pn7 digital input */ + +/* + AD port configuration register (ADPC) +*/ +/* Analog input/digital input switching (ADPC3 - ADPC0) */ +#define _00_ADPC_DI_OFF (0x00U) /* use P20 - P23 as analog input */ +#define _04_ADPC_DI_ON (0x04U) /* use P23 as digital input */ +#define _03_ADPC_DI_ON (0x03U) /* use P22 - P23 as digital input */ +#define _02_ADPC_DI_ON (0x02U) /* use P21 - P23 as digital input */ +#define _01_ADPC_DI_ON (0x01U) /* use P20 - P23 as digital input */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _E0_PM1_DEFAULT (0xE0U) /* PM1 default value */ +#define _F0_PM2_DEFAULT (0xF0U) /* PM2 default value */ +#define _F8_PM4_DEFAULT (0xF8U) /* PM4 default value */ +#define _FC_PM6_DEFAULT (0xFCU) /* PM6 default value */ +#define _E0_PMC1_DEFAULT (0xE0U) /* PMC1 default value */ +#define _F9_PMC4_DEFAULT (0xF9U) /* PMC4 default value */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_port_user.c b/app/r_cg_port_user.c new file mode 100644 index 0000000..a9b4dad --- /dev/null +++ b/app/r_cg_port_user.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_serial.c b/app/r_cg_serial.c new file mode 100644 index 0000000..0814154 --- /dev/null +++ b/app/r_cg_serial.c @@ -0,0 +1,166 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_serial.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for Serial module. +* Creation Date: 2023-12-13 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_serial.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +volatile uint8_t * gp_uart0_tx_address; /* uart0 transmit buffer address */ +volatile uint16_t g_uart0_tx_count; /* uart0 transmit data number */ +volatile uint8_t * gp_uart0_rx_address; /* uart0 receive buffer address */ +volatile uint16_t g_uart0_rx_count; /* uart0 receive data number */ +volatile uint16_t g_uart0_rx_length; /* uart0 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_SAU0_Create +* Description : This function initializes the SAU0 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SAU0_Create(void) +{ + SAU0EN = 1U; /* supply SAU0 clock */ + NOP(); + NOP(); + NOP(); + NOP(); + SPS0 = _0000_SAU_CK00_FCLK_0 | _0000_SAU_CK01_FCLK_0; + R_UART0_Create(); +} + +/*********************************************************************************************************************** +* Function Name: R_UART0_Create +* Description : This function initializes the UART0 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_UART0_Create(void) +{ + /* UART0 initial setting */ + ST0 |= _0001_SAU_CH0_STOP_TRG_ON; /* UART0 transmit disable */ + STMK0 = 1U; /* disable INTST0 interrupt */ + STIF0 = 0U; /* clear INTST0 interrupt flag */ + SRMK0 = 1U; /* disable INTSR0 interrupt */ + SRIF0 = 0U; /* clear INTSR0 interrupt flag */ + SREMK0 = 1U; /* disable INTSRE0 interrupt */ + SREIF0 = 0U; /* clear INTSRE0 interrupt flag */ + /* Set INTST0 low priority */ + STPR10 = 1U; + STPR00 = 1U; + SMR00 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0000_SAU_TRIGGER_SOFTWARE | + _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END; + SCR00 = _8000_SAU_TRANSMISSION | _0000_SAU_INTSRE_MASK | _0000_SAU_PARITY_NONE | _0080_SAU_LSB | _0010_SAU_STOP_1 | + _0007_SAU_LENGTH_8; + SDR00 = _CE00_UART0_TRANSMIT_DIVISOR; + SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1; + SOL0 |= _0000_SAU_CHANNEL0_NORMAL; /* output level normal */ + SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE; /* enable UART0 output */ + /* Set TxD0 pin */ + P6 |= 0x01U; + PM6 &= 0xFEU; +} + +/*********************************************************************************************************************** +* Function Name: R_UART0_Start +* Description : This function starts the UART0 module operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_UART0_Start(void) +{ + SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1; /* output level normal */ + SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE; /* enable UART0 output */ + SS0 |= _0001_SAU_CH0_START_TRG_ON; /* enable UART0 transmit */ + STIF0 = 0U; /* clear INTST0 interrupt flag */ + STMK0 = 0U; /* enable INTST0 interrupt */ +} + +/*********************************************************************************************************************** +* Function Name: R_UART0_Stop +* Description : This function stops the UART0 module operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_UART0_Stop(void) +{ + STMK0 = 1U; /* disable INTST0 interrupt */ + ST0 |= _0001_SAU_CH0_STOP_TRG_ON; /* disable UART0 transmit */ + SOE0 &= ~_0001_SAU_CH0_OUTPUT_ENABLE; /* disable UART0 output */ + STIF0 = 0U; /* clear INTST0 interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_UART0_Send +* Description : This function sends UART0 data. +* Arguments : tx_buf - +* transfer buffer pointer +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (tx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + gp_uart0_tx_address = tx_buf; + g_uart0_tx_count = tx_num; + STMK0 = 1U; /* disable INTST0 interrupt */ + TXD0 = *gp_uart0_tx_address; + gp_uart0_tx_address++; + g_uart0_tx_count--; + STMK0 = 0U; /* enable INTST0 interrupt */ + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_serial.h b/app/r_cg_serial.h new file mode 100644 index 0000000..bfec9ab --- /dev/null +++ b/app/r_cg_serial.h @@ -0,0 +1,394 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_serial.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for Serial module. +* Creation Date: 2023-12-13 +***********************************************************************************************************************/ + +#ifndef SERIAL_H +#define SERIAL_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Serial Clock Select Register m (SPSm) +*/ +/* Section of operation clock (CKm0) (PRSm03 - PRSm00) */ +#define _0000_SAU_CK00_FCLK_0 (0x0000U) /* ck00 - fCLK */ +#define _0001_SAU_CK00_FCLK_1 (0x0001U) /* ck00 - fCLK/2^1 */ +#define _0002_SAU_CK00_FCLK_2 (0x0002U) /* ck00 - fCLK/2^2 */ +#define _0003_SAU_CK00_FCLK_3 (0x0003U) /* ck00 - fCLK/2^3 */ +#define _0004_SAU_CK00_FCLK_4 (0x0004U) /* ck00 - fCLK/2^4 */ +#define _0005_SAU_CK00_FCLK_5 (0x0005U) /* ck00 - fCLK/2^5 */ +#define _0006_SAU_CK00_FCLK_6 (0x0006U) /* ck00 - fCLK/2^6 */ +#define _0007_SAU_CK00_FCLK_7 (0x0007U) /* ck00 - fCLK/2^7 */ +#define _0008_SAU_CK00_FCLK_8 (0x0008U) /* ck00 - fCLK/2^8 */ +#define _0009_SAU_CK00_FCLK_9 (0x0009U) /* ck00 - fCLK/2^9 */ +#define _000A_SAU_CK00_FCLK_10 (0x000AU) /* ck00 - fCLK/2^10 */ +#define _000B_SAU_CK00_FCLK_11 (0x000BU) /* ck00 - fCLK/2^11 */ +#define _000C_SAU_CK00_FCLK_12 (0x000CU) /* ck00 - fCLK/2^12 */ +#define _000D_SAU_CK00_FCLK_13 (0x000DU) /* ck00 - fCLK/2^13 */ +#define _000E_SAU_CK00_FCLK_14 (0x000EU) /* ck00 - fCLK/2^14 */ +#define _000F_SAU_CK00_FCLK_15 (0x000FU) /* ck00 - fCLK/2^15 */ +/* Section of operation clock (CKm1) (PRSm13 - PRSm10) */ +#define _0000_SAU_CK01_FCLK_0 (0x0000U) /* ck01 - fCLK */ +#define _0010_SAU_CK01_FCLK_1 (0x0010U) /* ck01 - fCLK/2^1 */ +#define _0020_SAU_CK01_FCLK_2 (0x0020U) /* ck01 - fCLK/2^2 */ +#define _0030_SAU_CK01_FCLK_3 (0x0030U) /* ck01 - fCLK/2^3 */ +#define _0040_SAU_CK01_FCLK_4 (0x0040U) /* ck01 - fCLK/2^4 */ +#define _0050_SAU_CK01_FCLK_5 (0x0050U) /* ck01 - fCLK/2^5 */ +#define _0060_SAU_CK01_FCLK_6 (0x0060U) /* ck01 - fCLK/2^6 */ +#define _0070_SAU_CK01_FCLK_7 (0x0070U) /* ck01 - fCLK/2^7 */ +#define _0080_SAU_CK01_FCLK_8 (0x0080U) /* ck01 - fCLK/2^8 */ +#define _0090_SAU_CK01_FCLK_9 (0x0090U) /* ck01 - fCLK/2^9 */ +#define _00A0_SAU_CK01_FCLK_10 (0x00A0U) /* ck01 - fCLK/2^10 */ +#define _00B0_SAU_CK01_FCLK_11 (0x00B0U) /* ck01 - fCLK/2^11 */ +#define _00C0_SAU_CK01_FCLK_12 (0x00C0U) /* ck01 - fCLK/2^12 */ +#define _00D0_SAU_CK01_FCLK_13 (0x00D0U) /* ck01 - fCLK/2^13 */ +#define _00E0_SAU_CK01_FCLK_14 (0x00E0U) /* ck01 - fCLK/2^14 */ +#define _00F0_SAU_CK01_FCLK_15 (0x00F0U) /* ck01 - fCLK/2^15 */ + +/* + Serial Mode Register mn (SMRmn) +*/ +#define _0020_SAU_SMRMN_INITIALVALUE (0x0020U) +/* Selection of macro clock (MCK) of channel n (CKSmn) */ +#define _0000_SAU_CLOCK_SELECT_CK00 (0x0000U) /* operation clock CK0 set by PRS register */ +#define _8000_SAU_CLOCK_SELECT_CK01 (0x8000U) /* operation clock CK1 set by PRS register */ +/* Selection of transfer clock (TCLK) of channel n (CCSmn) */ +#define _0000_SAU_CLOCK_MODE_CKS (0x0000U) /* divided operation clock MCK specified by CKSmn bit */ +#define _4000_SAU_CLOCK_MODE_TI0N (0x4000U) /* clock input from SCK pin (slave transfer in CSI mode) */ +/* Selection of start trigger source (STSmn) */ +#define _0000_SAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger is valid */ +#define _0100_SAU_TRIGGER_RXD (0x0100U) /* valid edge of RXD pin */ +/* Controls inversion of level of receive data of channel n in UART mode (SISmn0) */ +#define _0000_SAU_EDGE_FALL (0x0000U) /* falling edge is detected as the start bit */ +#define _0040_SAU_EDGE_RISING (0x0040U) /* rising edge is detected as the start bit */ +/* Setting of operation mode of channel n (MDmn2, MDmn1) */ +#define _0000_SAU_MODE_CSI (0x0000U) /* CSI mode */ +#define _0002_SAU_MODE_UART (0x0002U) /* UART mode */ +#define _0004_SAU_MODE_IIC (0x0004U) /* simplified IIC mode */ +/* Selection of interrupt source of channel n (MDmn0) */ +#define _0000_SAU_TRANSFER_END (0x0000U) /* transfer end interrupt */ +#define _0001_SAU_BUFFER_EMPTY (0x0001U) /* buffer empty interrupt */ + +/* + Serial Communication Operation Setting Register mn (SCRmn) +*/ +/* Setting of operation mode of channel n (TXEmn, RXEmn) */ +#define _0000_SAU_NOT_COMMUNICATION (0x0000U) /* does not start communication */ +#define _4000_SAU_RECEPTION (0x4000U) /* reception only */ +#define _8000_SAU_TRANSMISSION (0x8000U) /* transmission only */ +#define _C000_SAU_RECEPTION_TRANSMISSION (0xC000U) /* reception and transmission */ +/* Selection of data and clock phase in CSI mode (DAPmn, CKPmn) */ +#define _0000_SAU_TIMING_1 (0x0000U) /* type 1 */ +#define _1000_SAU_TIMING_2 (0x1000U) /* type 2 */ +#define _2000_SAU_TIMING_3 (0x2000U) /* type 3 */ +#define _3000_SAU_TIMING_4 (0x3000U) /* type 4 */ +/* Selection of masking of error interrupt signal (EOCmn) */ +#define _0000_SAU_INTSRE_MASK (0x0000U) /* masks error interrupt INTSREx */ +#define _0400_SAU_INTSRE_ENABLE (0x0400U) /* enables generation of error interrupt INTSREx */ +/* Setting of parity bit in UART mode (PTCmn1 - PTCmn0) */ +#define _0000_SAU_PARITY_NONE (0x0000U) /* none parity */ +#define _0100_SAU_PARITY_ZERO (0x0100U) /* zero parity */ +#define _0200_SAU_PARITY_EVEN (0x0200U) /* even parity */ +#define _0300_SAU_PARITY_ODD (0x0300U) /* odd parity */ +/* Selection of data transfer sequence in CSI and UART modes (DIRmn) */ +#define _0000_SAU_MSB (0x0000U) /* MSB */ +#define _0080_SAU_LSB (0x0080U) /* LSB */ +/* Setting of stop bit in UART mode (SLCmn1, SLCmn0) */ +#define _0000_SAU_STOP_NONE (0x0000U) /* none stop bit */ +#define _0010_SAU_STOP_1 (0x0010U) /* 1 stop bit */ +#define _0020_SAU_STOP_2 (0x0020U) /* 2 stop bits */ +/* Setting of data length in CSI and UART modes (DLSmn2 - DLSmn0) */ +#define _0005_SAU_LENGTH_9 (0x0005U) /* 9-bit data length */ +#define _0006_SAU_LENGTH_7 (0x0006U) /* 7-bit data length */ +#define _0007_SAU_LENGTH_8 (0x0007U) /* 8-bit data length */ + +/* + Serial Output Level Register m (SOLm) +*/ +/* Selects inversion of the level of the transmit data of channel n in UART mode */ +#define _0000_SAU_CHANNEL0_NORMAL (0x0000U) /* normal bit level */ +#define _0001_SAU_CHANNEL0_INVERTED (0x0001U) /* inverted bit level */ +#define _0000_SAU_CHANNEL1_NORMAL (0x0000U) /* normal bit level */ +#define _0002_SAU_CHANNEL1_INVERTED (0x0002U) /* inverted bit level */ +#define _0000_SAU_CHANNEL2_NORMAL (0x0000U) /* normal bit level */ +#define _0004_SAU_CHANNEL2_INVERTED (0x0004U) /* inverted bit level */ +#define _0000_SAU_CHANNEL3_NORMAL (0x0000U) /* normal bit level */ +#define _0008_SAU_CHANNEL3_INVERTED (0x0008U) /* inverted bit level */ + +/* + Noise Filter Enable Register 0 (NFEN0) +*/ +/* Use of noise filter */ +#define _00_SAU_RXD3_FILTER_OFF (0x00U) /* noise filter off */ +#define _40_SAU_RXD3_FILTER_ON (0x40U) /* noise filter on */ +#define _00_SAU_RXD2_FILTER_OFF (0x00U) /* noise filter off */ +#define _10_SAU_RXD2_FILTER_ON (0x10U) /* noise filter on */ +#define _00_SAU_RXD1_FILTER_OFF (0x00U) /* noise filter off */ +#define _04_SAU_RXD1_FILTER_ON (0x04U) /* noise filter on */ +#define _00_SAU_RXD0_FILTER_OFF (0x00U) /* noise filter off */ +#define _01_SAU_RXD0_FILTER_ON (0x01U) /* noise filter on */ + +/* + Format of Serial Status Register mn (SSRmn) +*/ +/* Communication status indication flag of channel n (TSFmn) */ +#define _0040_SAU_UNDER_EXECUTE (0x0040U) /* communication is under execution */ +/* Buffer register status indication flag of channel n (BFFmn) */ +#define _0020_SAU_VALID_STORED (0x0020U) /* valid data is stored in the SDRmn register */ +/* Framing error detection flag of channel n (FEFmn) */ +#define _0004_SAU_FRAM_ERROR (0x0004U) /* a framing error occurs during UART reception */ +/* Parity error detection flag of channel n (PEFmn) */ +#define _0002_SAU_PARITY_ERROR (0x0002U) /* a parity error occurs or ACK is not detected */ +/* Overrun error detection flag of channel n (OVFmn) */ +#define _0001_SAU_OVERRUN_ERROR (0x0001U) /* an overrun error occurs */ + +/* + Serial Channel Start Register m (SSm) +*/ +/* Operation start trigger of channel 0 (SSm0) */ +#define _0000_SAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_SAU_CH0_START_TRG_ON (0x0001U) /* sets SEm0 to 1 and enters the communication wait status */ +/* Operation start trigger of channel 1 (SSm1) */ +#define _0000_SAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_SAU_CH1_START_TRG_ON (0x0002U) /* sets SEm1 to 1 and enters the communication wait status */ +/* Operation start trigger of channel 2 (SSm2) */ +#define _0000_SAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_SAU_CH2_START_TRG_ON (0x0004U) /* sets SEm2 to 1 and enters the communication wait status */ +/* Operation start trigger of channel 3 (SSm3) */ +#define _0000_SAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_SAU_CH3_START_TRG_ON (0x0008U) /* sets SEm3 to 1 and enters the communication wait status */ + +/* + Serial Channel Stop Register m (STm) +*/ +/* Operation stop trigger of channel 0 (STm0) */ +#define _0000_SAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_SAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 1 (STm1) */ +#define _0000_SAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_SAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 2 (STm2) */ +#define _0000_SAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_SAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 3 (STm3) */ +#define _0000_SAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_SAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */ + +/* + Format of Serial Flag Clear Trigger Register mn (SIRmn) +*/ +/* Clear trigger of overrun error flag of channel n (OVCTmn) */ +#define _0001_SAU_SIRMN_OVCTMN (0x0001U) +/* Clear trigger of parity error flag of channel n (PECTmn) */ +#define _0002_SAU_SIRMN_PECTMN (0x0002U) +/* Clear trigger of framing error of channel n (FECTMN) */ +#define _0004_SAU_SIRMN_FECTMN (0x0004U) + +/* + Serial Output Enable Register m (SOEm) +*/ +/* Serial output enable/disable of channel 0 (SOEm0) */ +#define _0001_SAU_CH0_OUTPUT_ENABLE (0x0001U) /* enables output by serial communication operation */ +#define _0000_SAU_CH0_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */ +/* Serial output enable/disable of channel 1 (SOEm1) */ +#define _0002_SAU_CH1_OUTPUT_ENABLE (0x0002U) /* enables output by serial communication operation */ +#define _0000_SAU_CH1_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */ +/* Serial output enable/disable of channel 2 (SOEm2) */ +#define _0004_SAU_CH2_OUTPUT_ENABLE (0x0004U) /* enables output by serial communication operation */ +#define _0000_SAU_CH2_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */ +/* Serial output enable/disable of channel 3 (SOEm3) */ +#define _0008_SAU_CH3_OUTPUT_ENABLE (0x0008U) /* enables output by serial communication operation */ +#define _0000_SAU_CH3_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */ + +/* + Serial Output Register m (SOm) +*/ +/* Serial data output of channel 0 (SOm0) */ +#define _0000_SAU_CH0_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */ +#define _0001_SAU_CH0_DATA_OUTPUT_1 (0x0001U) /* Serial data output value is "1" */ +/* Serial data output of channel 1 (SOm1) */ +#define _0000_SAU_CH1_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */ +#define _0002_SAU_CH1_DATA_OUTPUT_1 (0x0002U) /* Serial data output value is "1" */ +/* Serial data output of channel 2 (SOm2) */ +#define _0000_SAU_CH2_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */ +#define _0004_SAU_CH2_DATA_OUTPUT_1 (0x0004U) /* Serial data output value is "1" */ +/* Serial data output of channel 3 (SOm3) */ +#define _0000_SAU_CH3_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */ +#define _0008_SAU_CH3_DATA_OUTPUT_1 (0x0008U) /* Serial data output value is "1" */ +/* Serial clock output of channel 0 (CKOm0) */ +#define _0000_SAU_CH0_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */ +#define _0100_SAU_CH0_CLOCK_OUTPUT_1 (0x0100U) /* Serial clock output value is "1" */ +/* Serial clock output of channel 1 (CKOm1) */ +#define _0000_SAU_CH1_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */ +#define _0200_SAU_CH1_CLOCK_OUTPUT_1 (0x0200U) /* Serial clock output value is "1" */ +/* Serial clock output of channel 2 (CKOm2) */ +#define _0000_SAU_CH2_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */ +#define _0400_SAU_CH2_CLOCK_OUTPUT_1 (0x0400U) /* Serial clock output value is "1" */ +/* Serial clock output of channel 3 (CKOm3) */ +#define _0000_SAU_CH3_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */ +#define _0800_SAU_CH3_CLOCK_OUTPUT_1 (0x0800U) /* Serial clock output value is "1" */ + +/* + SAU Standby Control Register m (SSCm) +*/ +/* SAU Standby Wakeup Control Bit (SWC) */ +#define _0000_SAU_CH0_SNOOZE_OFF (0x0000U) /* disable start function from STOP state of chip */ +#define _0001_SAU_CH0_SNOOZE_ON (0x0001U) /* enable start function from STOP state of chip */ + +/* SAU used flag */ +#define _00_SAU_IIC_MASTER_FLAG_CLEAR (0x00U) +#define _01_SAU_IIC_SEND_FLAG (0x01U) +#define _02_SAU_IIC_RECEIVE_FLAG (0x02U) +#define _04_SAU_IIC_SENDED_ADDRESS_FLAG (0x04U) + +/* + Input switch control register (ISC) +*/ +/* Channel 0 SSI00 input setting in CSI communication and slave mode (SSIE00) */ +#define _00_SAU_SSI00_UNUSED (0x00U) /* disables SSI00 pin input */ +#define _80_SAU_SSI00_USED (0x80U) /* enables SSI00 pin input */ + +/* + IICA Control Register (IICCTLn0) +*/ +/* IIC operation enable (IICEn) */ +#define _00_IICA_OPERATION_DISABLE (0x00U) /* stop operation */ +#define _80_IICA_OPERATION_ENABLE (0x80U) /* enable operation */ +/* Exit from communications (LRELn) */ +#define _00_IICA_COMMUNICATION_NORMAL (0x00U) /* normal operation */ +#define _40_IICA_COMMUNICATION_EXIT (0x40U) /* exit from current communication */ +/* Wait cancellation (WRELn) */ +#define _00_IICA_WAIT_NOTCANCEL (0x00U) /* do not cancel wait */ +#define _20_IICA_WAIT_CANCEL (0x20U) /* cancel wait */ +/* Generation of interrupt when stop condition (SPIEn) */ +#define _00_IICA_STOPINT_DISABLE (0x00U) /* disable */ +#define _10_IICA_STOPINT_ENABLE (0x10U) /* enable */ +/* Wait and interrupt generation (WTIMn) */ +#define _00_IICA_WAITINT_CLK8FALLING (0x00U) /* generated at the eighth clock's falling edge */ +#define _08_IICA_WAITINT_CLK9FALLING (0x08U) /* generated at the ninth clock's falling edge */ +/* Acknowledgement control (ACKEn) */ +#define _00_IICA_ACK_DISABLE (0x00U) /* disable acknowledgement */ +#define _04_IICA_ACK_ENABLE (0x04U) /* enable acknowledgement */ +/* Start condition trigger (STTn) */ +#define _00_IICA_START_NOTGENERATE (0x00U) /* do not generate start condition */ +#define _02_IICA_START_GENERATE (0x02U) /* generate start condition */ +/* Stop condition trigger (SPTn) */ +#define _00_IICA_STOP_NOTGENERATE (0x00U) /* do not generate stop condition */ +#define _01_IICA_STOP_GENERATE (0x01U) /* generate stop condition */ + +/* + IICA Status Register (IICSn) +*/ +/* Master device status (MSTSn) */ +#define _00_IICA_STATUS_NOTMASTER (0x00U) /* slave device status or communication standby status */ +#define _80_IICA_STATUS_MASTER (0x80U) /* master device communication status */ +/* Detection of arbitration loss (ALDn) */ +#define _00_IICA_ARBITRATION_NO (0x00U) /* arbitration win or no arbitration */ +#define _40_IICA_ARBITRATION_LOSS (0x40U) /* arbitration loss */ +/* Detection of extension code reception (EXCn) */ +#define _00_IICA_EXTCODE_NOT (0x00U) /* extension code not received */ +#define _20_IICA_EXTCODE_RECEIVED (0x20U) /* extension code received */ +/* Detection of matching addresses (COIn) */ +#define _00_IICA_ADDRESS_NOTMATCH (0x00U) /* addresses do not match */ +#define _10_IICA_ADDRESS_MATCH (0x10U) /* addresses match */ +/* Detection of transmit/receive status (TRCn) */ +#define _00_IICA_STATUS_RECEIVE (0x00U) /* receive status */ +#define _08_IICA_STATUS_TRANSMIT (0x08U) /* transmit status */ +/* Detection of acknowledge signal (ACKDn) */ +#define _00_IICA_ACK_NOTDETECTED (0x00U) /* ACK signal was not detected */ +#define _04_IICA_ACK_DETECTED (0x04U) /* ACK signal was detected */ +/* Detection of start condition (STDn) */ +#define _00_IICA_START_NOTDETECTED (0x00U) /* start condition not detected */ +#define _02_IICA_START_DETECTED (0x02U) /* start condition detected */ +/* Detection of stop condition (SPDn) */ +#define _00_IICA_STOP_NOTDETECTED (0x00U) /* stop condition not detected */ +#define _01_IICA_STOP_DETECTED (0x01U) /* stop condition detected */ + +/* + IICA Flag Register (IICFn) +*/ +/* STT clear flag (STCFn) */ +#define _00_IICA_STARTFLAG_GENERATE (0x00U) /* generate start condition */ +#define _80_IICA_STARTFLAG_UNSUCCESSFUL (0x80U) /* start condition generation unsuccessful */ +/* IIC bus status flag (IICBSYn) */ +#define _00_IICA_BUS_RELEASE (0x00U) /* bus release status */ +#define _40_IICA_BUS_COMMUNICATION (0x40U) /* bus communication status */ +/* Initial start enable trigger (STCENn) */ +#define _00_IICA_START_WITHSTOP (0x00U) /* generate start condition upon detecting a stop condition */ +#define _02_IICA_START_WITHOUTSTOP (0x02U) /* generate start condition without detection of a stop condition */ +/* Communication reservation function disable bit (IICRSVn) */ +#define _00_IICA_RESERVATION_ENABLE (0x00U) /* enable communication reservation */ +#define _01_IICA_RESERVATION_DISABLE (0x01U) /* disable communication reservation */ + +/* + IICA Control Register 1 (IICCTLn1) +*/ +/* Control of address match wakeup (WUPn) */ +#define _00_IICA_WAKEUP_STOP (0x00U) /* stop address match wakeup function in STOP mode */ +#define _80_IICA_WAKEUP_ENABLE (0x80U) /* enable address match wakeup function in STOP mode */ +/* Detection of SCL0 pin level (CLDn) */ +#define _00_IICA_SCL_LOW (0x00U) /* detect clock line at low level */ +#define _20_IICA_SCL_HIGH (0x20U) /* detect clock line at high level */ +/* Detection of SDA0 pin level (DADn) */ +#define _00_IICA_SDA_LOW (0x00U) /* detect data line at low level */ +#define _10_IICA_SDA_HIGH (0x10U) /* detect data line at high level */ +/* Operation mode switching (SMCn) */ +#define _00_IICA_MODE_STANDARD (0x00U) /* operates in standard mode */ +#define _08_IICA_MODE_HIGHSPEED (0x08U) /* operates in high-speed mode */ +/* Digital filter operation control (DFCn) */ +#define _00_IICA_FILTER_OFF (0x00U) /* digital filter off */ +#define _04_IICA_FILTER_ON (0x04U) /* digital filter on */ +/* Operation of clock dividing frequency permission (PRSn) */ +#define _00_IICA_fCLK (0x00U) /* clock of dividing frequency operation (fCLK) */ +#define _01_IICA_fCLK_HALF (0x01U) /* 2 clock of dividing frequency operation (fCLK/2) */ +/* IICA used flag */ +#define _80_IICA_ADDRESS_COMPLETE (0x80U) +#define _00_IICA_MASTER_FLAG_CLEAR (0x00U) + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _CE00_UART0_TRANSMIT_DIVISOR (0xCE00U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_SAU0_Create(void); +void R_UART0_Create(void); +void R_UART0_Start(void); +void R_UART0_Stop(void); +MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num); +static void r_uart0_callback_sendend(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_serial_user.c b/app/r_cg_serial_user.c new file mode 100644 index 0000000..fd6a76f --- /dev/null +++ b/app/r_cg_serial_user.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_serial_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for Serial module. +* Creation Date: 2023-12-13 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_serial.h" +/* Start user code for include. Do not edit comment generated here */ +#include "appTask.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_uart0_interrupt_send(vect=INTST0) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern volatile uint8_t * gp_uart0_tx_address; /* uart0 send buffer address */ +extern volatile uint16_t g_uart0_tx_count; /* uart0 send data number */ +extern volatile uint8_t * gp_uart0_rx_address; /* uart0 receive buffer address */ +extern volatile uint16_t g_uart0_rx_count; /* uart0 receive data number */ +extern volatile uint16_t g_uart0_rx_length; /* uart0 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +extern uint8_t g_rx_buf[3]; +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_uart0_interrupt_send +* Description : This function is INTST0 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_uart0_interrupt_send(void) +{ + if (g_uart0_tx_count > 0U) + { + TXD0 = *gp_uart0_tx_address; + gp_uart0_tx_address++; + g_uart0_tx_count--; + } + else + { + r_uart0_callback_sendend(); + } +} + +/*********************************************************************************************************************** +* Function Name: r_uart0_callback_sendend +* Description : This function is a callback function when UART0 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_uart0_callback_sendend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_timer.c b/app/r_cg_timer.c new file mode 100644 index 0000000..0205a79 --- /dev/null +++ b/app/r_cg_timer.c @@ -0,0 +1,158 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Create +* Description : This function initializes the TAU0 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Create(void) +{ + TAU0EN = 1U; /* supplies input clock */ + TPS0 = _0000_TAU_CKM0_FCLK_0 | _0000_TAU_CKM1_FCLK_0 | _0000_TAU_CKM2_FCLK_1 | _0000_TAU_CKM3_FCLK_8; + /* Stop all channels */ + TT0 = _0001_TAU_CH0_STOP_TRG_ON | _0002_TAU_CH1_STOP_TRG_ON | _0004_TAU_CH2_STOP_TRG_ON | + _0008_TAU_CH3_STOP_TRG_ON | _0200_TAU_CH1_H8_STOP_TRG_ON | _0800_TAU_CH3_H8_STOP_TRG_ON; + /* Mask channel 0 interrupt */ + TMMK00 = 1U; /* disable INTTM00 interrupt */ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ + /* Mask channel 1 interrupt */ + TMMK01 = 1U; /* disable INTTM01 interrupt */ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ + /* Mask channel 1 higher 8 bits interrupt */ + TMMK01H = 1U; /* disable INTTM01H interrupt */ + TMIF01H = 0U; /* clear INTTM01H interrupt flag */ + /* Mask channel 2 interrupt */ + TMMK02 = 1U; /* disable INTTM02 interrupt */ + TMIF02 = 0U; /* clear INTTM02 interrupt flag */ + /* Mask channel 3 interrupt */ + TMMK03 = 1U; /* disable INTTM03 interrupt */ + TMIF03 = 0U; /* clear INTTM03 interrupt flag */ + /* Mask channel 3 higher 8 bits interrupt */ + TMMK03H = 1U; /* disable INTTM03H interrupt */ + TMIF03H = 0U; /* clear INTTM03H interrupt flag */ + /* Set INTTM00 low priority */ + TMPR100 = 1U; + TMPR000 = 1U; + /* Set INTTM01 low priority */ + TMPR101 = 1U; + TMPR001 = 1U; + /* Channel 0 used as interval timer */ + TMR00 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_COMBINATION_SLAVE | + _0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED; + TDR00 = _5DBF_TAU_TDR00_VALUE; + TO0 &= ~_0001_TAU_CH0_OUTPUT_VALUE_1; + TOE0 &= ~_0001_TAU_CH0_OUTPUT_ENABLE; + /* Channel 1 used as interval timer */ + TMR01 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_16BITS_MODE | + _0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED; + TDR01 = _5DBF_TAU_TDR01_VALUE; + TOM0 &= ~_0002_TAU_CH1_OUTPUT_COMBIN; + TOL0 &= ~_0002_TAU_CH1_OUTPUT_LEVEL_L; + TO0 &= ~_0002_TAU_CH1_OUTPUT_VALUE_1; + TOE0 &= ~_0002_TAU_CH1_OUTPUT_ENABLE; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel0_Start +* Description : This function starts TAU0 channel 0 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel0_Start(void) +{ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ + TMMK00 = 0U; /* enable INTTM00 interrupt */ + TS0 |= _0001_TAU_CH0_START_TRG_ON; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel0_Stop +* Description : This function stops TAU0 channel 0 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel0_Stop(void) +{ + TT0 |= _0001_TAU_CH0_STOP_TRG_ON; + /* Mask channel 0 interrupt */ + TMMK00 = 1U; /* disable INTTM00 interrupt */ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel1_Start +* Description : This function starts TAU0 channel 1 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel1_Start(void) +{ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ + TMMK01 = 0U; /* enable INTTM01 interrupt */ + TS0 |= _0002_TAU_CH1_START_TRG_ON; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel1_Stop +* Description : This function stops TAU0 channel 1 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel1_Stop(void) +{ + TT0 |= _0002_TAU_CH1_STOP_TRG_ON; + /* Mask channel 1 interrupt */ + TMMK01 = 1U; /* disable INTTM01 interrupt */ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_timer.h b/app/r_cg_timer.h new file mode 100644 index 0000000..9033933 --- /dev/null +++ b/app/r_cg_timer.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef TAU_H +#define TAU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Peripheral Enable Register 0 (PER0) +*/ +/* Control of timer array unit 0 input clock (TAU0EN) */ +#define _00_TAU0_CLOCK_STOP (0x00U) /* stops supply of input clock */ +#define _01_TAU0_CLOCK_SUPPLY (0x01U) /* supplies input clock */ + +/* + Timer Clock Select Register m (TPSm) +*/ +/* Operating mode and clear mode selection (PRSm03 - PRSm00) */ +#define _0000_TAU_CKM0_FCLK_0 (0x0000U) /* ckm0 - fCLK */ +#define _0001_TAU_CKM0_FCLK_1 (0x0001U) /* ckm0 - fCLK/2^1 */ +#define _0002_TAU_CKM0_FCLK_2 (0x0002U) /* ckm0 - fCLK/2^2 */ +#define _0003_TAU_CKM0_FCLK_3 (0x0003U) /* ckm0 - fCLK/2^3 */ +#define _0004_TAU_CKM0_FCLK_4 (0x0004U) /* ckm0 - fCLK/2^4 */ +#define _0005_TAU_CKM0_FCLK_5 (0x0005U) /* ckm0 - fCLK/2^5 */ +#define _0006_TAU_CKM0_FCLK_6 (0x0006U) /* ckm0 - fCLK/2^6 */ +#define _0007_TAU_CKM0_FCLK_7 (0x0007U) /* ckm0 - fCLK/2^7 */ +#define _0008_TAU_CKM0_FCLK_8 (0x0008U) /* ckm0 - fCLK/2^8 */ +#define _0009_TAU_CKM0_FCLK_9 (0x0009U) /* ckm0 - fCLK/2^9 */ +#define _000A_TAU_CKM0_FCLK_10 (0x000AU) /* ckm0 - fCLK/2^10 */ +#define _000B_TAU_CKM0_FCLK_11 (0x000BU) /* ckm0 - fCLK/2^11 */ +#define _000C_TAU_CKM0_FCLK_12 (0x000CU) /* ckm0 - fCLK/2^12 */ +#define _000D_TAU_CKM0_FCLK_13 (0x000DU) /* ckm0 - fCLK/2^13 */ +#define _000E_TAU_CKM0_FCLK_14 (0x000EU) /* ckm0 - fCLK/2^14 */ +#define _000F_TAU_CKM0_FCLK_15 (0x000FU) /* ckm0 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm13 - PRSm10) */ +#define _0000_TAU_CKM1_FCLK_0 (0x0000U) /* ckm1 - fCLK */ +#define _0010_TAU_CKM1_FCLK_1 (0x0010U) /* ckm1 - fCLK/2^1 */ +#define _0020_TAU_CKM1_FCLK_2 (0x0020U) /* ckm1 - fCLK/2^2 */ +#define _0030_TAU_CKM1_FCLK_3 (0x0030U) /* ckm1 - fCLK/2^3 */ +#define _0040_TAU_CKM1_FCLK_4 (0x0040U) /* ckm1 - fCLK/2^4 */ +#define _0050_TAU_CKM1_FCLK_5 (0x0050U) /* ckm1 - fCLK/2^5 */ +#define _0060_TAU_CKM1_FCLK_6 (0x0060U) /* ckm1 - fCLK/2^6 */ +#define _0070_TAU_CKM1_FCLK_7 (0x0070U) /* ckm1 - fCLK/2^7 */ +#define _0080_TAU_CKM1_FCLK_8 (0x0080U) /* ckm1 - fCLK/2^8 */ +#define _0090_TAU_CKM1_FCLK_9 (0x0090U) /* ckm1 - fCLK/2^9 */ +#define _00A0_TAU_CKM1_FCLK_10 (0x00A0U) /* ckm1 - fCLK/2^10 */ +#define _00B0_TAU_CKM1_FCLK_11 (0x00B0U) /* ckm1 - fCLK/2^11 */ +#define _00C0_TAU_CKM1_FCLK_12 (0x00C0U) /* ckm1 - fCLK/2^12 */ +#define _00D0_TAU_CKM1_FCLK_13 (0x00D0U) /* ckm1 - fCLK/2^13 */ +#define _00E0_TAU_CKM1_FCLK_14 (0x00E0U) /* ckm1 - fCLK/2^14 */ +#define _00F0_TAU_CKM1_FCLK_15 (0x00F0U) /* ckm1 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm21 - PRSm20) */ +#define _0000_TAU_CKM2_FCLK_1 (0x0000U) /* ckm2 - fCLK/2^1 */ +#define _0100_TAU_CKM2_FCLK_2 (0x0100U) /* ckm2 - fCLK/2^2 */ +#define _0200_TAU_CKM2_FCLK_4 (0x0200U) /* ckm2 - fCLK/2^4 */ +#define _0300_TAU_CKM2_FCLK_6 (0x0300U) /* ckm2 - fCLK/2^6 */ +/* Operating mode and clear mode selection (PRSm31 - PRSm30) */ +#define _0000_TAU_CKM3_FCLK_8 (0x0000U) /* ckm2 - fCLK/2^8 */ +#define _1000_TAU_CKM3_FCLK_10 (0x1000U) /* ckm2 - fCLK/2^10 */ +#define _2000_TAU_CKM3_FCLK_12 (0x2000U) /* ckm2 - fCLK/2^12 */ +#define _3000_TAU_CKM3_FCLK_14 (0x3000U) /* ckm2 - fCLK/2^14 */ + +/* + Timer Mode Register mn (TMRmn) +*/ +/* Selection of macro clock (MCK) of channel n (CKSmn1 - CKSmn0) */ +#define _0000_TAU_CLOCK_SELECT_CKM0 (0x0000U) /* operation clock CK0 set by PRS register */ +#define _8000_TAU_CLOCK_SELECT_CKM1 (0x8000U) /* operation clock CK1 set by PRS register */ +#define _4000_TAU_CLOCK_SELECT_CKM2 (0x4000U) /* operation clock CK2 set by PRS register */ +#define _C000_TAU_CLOCK_SELECT_CKM3 (0xC000U) /* operation clock CK3 set by PRS register */ +/* Selection of count clock (CCK) of channel n (CCSmn) */ +#define _0000_TAU_CLOCK_MODE_CKS (0x0000U) /* macro clock MCK specified by CKSmn bit */ +#define _1000_TAU_CLOCK_MODE_TIMN (0x1000U) /* valid edge of input signal input from TImn pin */ +/* Selection of slave/master of channel n (MASTERmn) */ +#define _0000_TAU_COMBINATION_SLAVE (0x0000U) /* operates as slave channel */ +#define _0000_TAU_COMBINATION_MASTER (0x0000U) /* channel0 operates as master channel */ +#define _0800_TAU_COMBINATION_MASTER (0x0800U) /* channel2, 4, 6 operates as master channel */ +/* Operation explanation of channel 1 or 3 (SPLIT) */ +#define _0000_TAU_16BITS_MODE (0x0000U) /* operates as 16 bits timer */ +#define _0800_TAU_8BITS_MODE (0x0800U) /* operates as 8 bits timer */ +/* Setting of start trigger or capture trigger of channel n (STSmn2 - STSmn0) */ +#define _0000_TAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger start is valid */ +#define _0100_TAU_TRIGGER_TIMN_VALID (0x0100U) /* TImn input edge is used as a start/capture trigger */ +#define _0200_TAU_TRIGGER_TIMN_BOTH (0x0200U) /* TImn input edges are used as a start/capture trigger */ +#define _0400_TAU_TRIGGER_MASTER_INT (0x0400U) /* interrupt signal of the master channel is used */ +/* Selection of TImn pin input valid edge (CISmn1 - CISmn0) */ +#define _0000_TAU_TIMN_EDGE_FALLING (0x0000U) /* falling edge */ +#define _0040_TAU_TIMN_EDGE_RISING (0x0040U) /* rising edge */ +#define _0080_TAU_TIMN_EDGE_BOTH_LOW (0x0080U) /* both edges (when low-level width is measured) */ +#define _00C0_TAU_TIMN_EDGE_BOTH_HIGH (0x00C0U) /* both edges (when high-level width is measured) */ +/* Operation mode of channel n (MDmn3 - MDmn0) */ +#define _0000_TAU_MODE_INTERVAL_TIMER (0x0000U) /* interval timer mode */ +#define _0004_TAU_MODE_CAPTURE (0x0004U) /* capture mode */ +#define _0006_TAU_MODE_EVENT_COUNT (0x0006U) /* event counter mode */ +#define _0008_TAU_MODE_ONE_COUNT (0x0008U) /* one count mode */ +#define _000C_TAU_MODE_HIGHLOW_MEASURE (0x000CU) /* high-/low-level width measurement mode */ +#define _0001_TAU_MODE_PWM_MASTER (0x0001U) /* PWM Function (Master Channel) mode */ +#define _0009_TAU_MODE_PWM_SLAVE (0x0009U) /* PWM Function (Slave Channel) mode */ +#define _0008_TAU_MODE_ONESHOT (0x0008U) /* one-shot pulse output mode */ +/* Setting of starting counting and interrupt (MDmn0) */ +#define _0000_TAU_START_INT_UNUSED (0x0000U) /* interrupt is not generated when counting is started */ +#define _0001_TAU_START_INT_USED (0x0001U) /* interrupt is generated when counting is started */ + +/* + Timer Status Register mn (TSRmn) +*/ +/* Counter overflow status of channel n (OVF) */ +#define _0000_TAU_OVERFLOW_NOT_OCCURS (0x0000U) /* overflow does not occur */ +#define _0001_TAU_OVERFLOW_OCCURS (0x0001U) /* overflow occurs */ + +/* + Timer Channel Enable Status Register m (TEm) +*/ +/* Indication of operation enable/stop status of channel 0 (TEm0) */ +#define _0000_TAU_CH0_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0001_TAU_CH0_OPERATION_ENABLE (0x0001U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 1 (TEm1) */ +#define _0000_TAU_CH1_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0002_TAU_CH1_OPERATION_ENABLE (0x0002U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 2 (TEm2) */ +#define _0000_TAU_CH2_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0004_TAU_CH2_OPERATION_ENABLE (0x0004U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 3 (TEm3) */ +#define _0000_TAU_CH3_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0008_TAU_CH3_OPERATION_ENABLE (0x0008U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEHm1) */ +#define _0000_TAU_CH1_H8_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0200_TAU_CH1_H8_OPERATION_ENABLE (0x0200U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEHm3) */ +#define _0000_TAU_CH3_H8_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0800_TAU_CH3_H8_OPERATION_ENABLE (0x0800U) /* operation is enabled */ + +/* + Timer Channel Start Register m (TSm) +*/ +/* Operation enable (start) trigger of channel 0 (TSm0) */ +#define _0000_TAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_TAU_CH0_START_TRG_ON (0x0001U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 1 (TSm1) */ +#define _0000_TAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_TAU_CH1_START_TRG_ON (0x0002U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 2 (TSm2) */ +#define _0000_TAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_TAU_CH2_START_TRG_ON (0x0004U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 3 (TSm3) */ +#define _0000_TAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_TAU_CH3_START_TRG_ON (0x0008U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 1 higher 8 bits (TSHm1) */ +#define _0000_TAU_CH1_H8_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0200_TAU_CH1_H8_START_TRG_ON (0x0200U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 3 higher 8 bits (TSHm3) */ +#define _0000_TAU_CH3_H8_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0800_TAU_CH3_H8_START_TRG_ON (0x0800U) /* operation is enabled (start trigger is generated) */ + +/* + Timer Channel Stop Register m (TTm) +*/ +/* Operation stop trigger of channel 0 (TTm0) */ +#define _0000_TAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_TAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 1 (TTm1) */ +#define _0000_TAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_TAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 2 (TTm2) */ +#define _0000_TAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_TAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 3 (TTm3) */ +#define _0000_TAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_TAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 1 higher 8 bits (TTHm1) */ +#define _0000_TAU_CH1_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0200_TAU_CH1_H8_STOP_TRG_ON (0x0200U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 3 higher 8 bits (TTHm3) */ +#define _0000_TAU_CH3_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0800_TAU_CH3_H8_STOP_TRG_ON (0x0800U) /* operation is stopped (stop trigger is generated) */ + +/* + Timer Input Select Register m (TIS0) +*/ +/* Selection of timer input used with channel 1 (TIS01 - TIS00) */ +#define _00_TAU_CH1_INPUT_TI01 (0x00U) /* input signal of timer input pin (TI01) */ +#define _01_TAU_CH1_INPUT_FIL (0x01U) /* internal low speed oscillation colock (fIL) */ +#define _10_TAU_CH1_INPUT_TI01 (0x10U) /* input signal of timer input pin (TI01) */ + +/* + Timer Output Enable Register m (TOEm) +*/ +/* Timer output enable/disable of channel 0 (TOEm0) */ +#define _0001_TAU_CH0_OUTPUT_ENABLE (0x0001U) /* the TOm0 operation enabled by count operation */ +#define _0000_TAU_CH0_OUTPUT_DISABLE (0x0000U) /* the TOm0 operation stopped by count operation */ +/* Timer output enable/disable of channel 1 (TOEm1) */ +#define _0002_TAU_CH1_OUTPUT_ENABLE (0x0002U) /* the TOm1 operation enabled by count operation */ +#define _0000_TAU_CH1_OUTPUT_DISABLE (0x0000U) /* the TOm1 operation stopped by count operation */ +/* Timer output enable/disable of channel 2 (TOEm2) */ +#define _0004_TAU_CH2_OUTPUT_ENABLE (0x0004U) /* the TOm2 operation enabled by count operation */ +#define _0000_TAU_CH2_OUTPUT_DISABLE (0x0000U) /* the TOm2 operation stopped by count operation */ +/* Timer output enable/disable of channel 3 (TOEm3) */ +#define _0008_TAU_CH3_OUTPUT_ENABLE (0x0008U) /* the TOm3 operation enabled by count operation */ +#define _0000_TAU_CH3_OUTPUT_DISABLE (0x0000U) /* the TOm3 operation stopped by count operation */ + +/* + Timer Output Register m (TOm) +*/ +/* Timer output of channel 0 (TOm0) */ +#define _0000_TAU_CH0_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0001_TAU_CH0_OUTPUT_VALUE_1 (0x0001U) /* timer output value is "1" */ +/* Timer output of channel 1 (TOm1) */ +#define _0000_TAU_CH1_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0002_TAU_CH1_OUTPUT_VALUE_1 (0x0002U) /* timer output value is "1" */ +/* Timer output of channel 2 (TOm2) */ +#define _0000_TAU_CH2_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0004_TAU_CH2_OUTPUT_VALUE_1 (0x0004U) /* timer output value is "1" */ +/* Timer output of channel 3 (TOm3) */ +#define _0000_TAU_CH3_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0008_TAU_CH3_OUTPUT_VALUE_1 (0x0008U) /* timer output value is "1" */ + +/* + Timer Output Level Register 0 (TOLm) +*/ +/* Control of timer output level of channel 1 (TOLm1) */ +#define _0000_TAU_CH1_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0002_TAU_CH1_OUTPUT_LEVEL_L (0x0002U) /* inverted output (active-low) */ +/* Control of timer output level of channel 2 (TOLm2) */ +#define _0000_TAU_CH2_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0004_TAU_CH2_OUTPUT_LEVEL_L (0x0004U) /* inverted output (active-low) */ +/* Control of timer output level of channel 3 (TOLm3) */ +#define _0000_TAU_CH3_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0008_TAU_CH3_OUTPUT_LEVEL_L (0x0008U) /* inverted output (active-low) */ + +/* + Timer Output Mode Register m (TOMm) +*/ +/* Control of timer output mode of channel 1 (TOMm1) */ +#define _0000_TAU_CH1_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0002_TAU_CH1_OUTPUT_COMBIN (0x0002U) /* combination operation mode */ +/* Control of timer output mode of channel 2 (TOMm2) */ +#define _0000_TAU_CH2_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0004_TAU_CH2_OUTPUT_COMBIN (0x0004U) /* combination operation mode */ +/* Control of timer output mode of channel 3 (TOMm3) */ +#define _0000_TAU_CH3_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0008_TAU_CH3_OUTPUT_COMBIN (0x0008U) /* combination operation mode */ + +/* + Input Switch Control Register (ISC) +*/ +/* Switching channel 7 input of timer array unit (ISC1) */ +#define _00_TAU_CH7_NO_INPUT (0x00U) /* timer input is not used */ +#define _02_TAU_CH7_RXD3_INPUT (0x02U) /* input signal of RxD3 pin is used as timer input */ + +/* + Noise Filter Enable Register 1 (NFEN1) +*/ +/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */ +#define _00_TAU_CH3_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _08_TAU_CH3_NOISE_ON (0x08U) /* noise filter ON */ +/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */ +#define _00_TAU_CH2_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _04_TAU_CH2_NOISE_ON (0x04U) /* noise filter ON */ +/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */ +#define _00_TAU_CH1_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _02_TAU_CH1_NOISE_ON (0x02U) /* noise filter ON */ +/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */ +#define _00_TAU_CH0_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _01_TAU_CH0_NOISE_ON (0x01U) /* noise filter ON */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* 16-bit timer data register 00 (TDR00) */ +#define _5DBF_TAU_TDR00_VALUE (0x5DBFU) +/* Clock divisor for TAU0 channel 0 */ +#define _0001_TAU0_CHANNEL0_DIVISOR (0x0001U) +/* 16-bit timer data register 01 (TDR01) */ +#define _5DBF_TAU_TDR01_VALUE (0x5DBFU) +/* Clock divisor for TAU0 channel 1 */ +#define _0001_TAU0_CHANNEL1_DIVISOR (0x0001U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_TAU0_Create(void); +void R_TAU0_Channel0_Start(void); +void R_TAU0_Channel0_Stop(void); +void R_TAU0_Channel1_Start(void); +void R_TAU0_Channel1_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_timer_user.c b/app/r_cg_timer_user.c new file mode 100644 index 0000000..5f829f8 --- /dev/null +++ b/app/r_cg_timer_user.c @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_timer.h" +/* Start user code for include. Do not edit comment generated here */ +#include "event.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_tau0_channel0_interrupt(vect=INTTM00) +#pragma interrupt r_tau0_channel1_interrupt(vect=INTTM01) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_tau0_channel0_interrupt +* Description : This function is INTTM00 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_tau0_channel0_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + TimeBaseCount(); + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: r_tau0_channel1_interrupt +* Description : This function is INTTM01 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_tau0_channel1_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_userdefine.h b/app/r_cg_userdefine.h new file mode 100644 index 0000000..6c3b618 --- /dev/null +++ b/app/r_cg_userdefine.h @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file includes user definition. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_wdt.c b/app/r_cg_wdt.c new file mode 100644 index 0000000..a89400e --- /dev/null +++ b/app/r_cg_wdt.c @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_WDT_Create +* Description : This function initializes the watchdogtimer. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_WDT_Create(void) +{ + WDTIMK = 1U; /* disable INTWDTI interrupt */ + WDTIIF = 0U; /* clear INTWDTI interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_WDT_Restart +* Description : This function restarts the watchdog timer. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_WDT_Restart(void) +{ + WDTE = 0xACU; /* restart watchdog timer */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_wdt.h b/app/r_cg_wdt.h new file mode 100644 index 0000000..e488ac2 --- /dev/null +++ b/app/r_cg_wdt.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt.h +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +#ifndef WDT_H +#define WDT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_WDT_Create(void); +void R_WDT_Restart(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_wdt_user.c b/app/r_cg_wdt_user.c new file mode 100644 index 0000000..4564d7e --- /dev/null +++ b/app/r_cg_wdt_user.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt_user.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_main.c b/app/r_main.c new file mode 100644 index 0000000..2ddd8cd --- /dev/null +++ b/app/r_main.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_main.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements main function. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_adc.h" +#include "r_cg_timer.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +#include "appTask.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +void R_MAIN_UserInit(void); + +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + HardWare_Init(); + Variable_Init(); + + while (1U) + { + AppTask(); + } + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + EI(); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_systeminit.c b/app/r_systeminit.c new file mode 100644 index 0000000..8dc2f9b --- /dev/null +++ b/app/r_systeminit.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_systeminit.c +* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021] +* Device(s) : R5F10268 +* Tool-Chain : CCRL +* Description : This file implements system initializing function. +* Creation Date: 2024-01-05 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_adc.h" +#include "r_cg_timer.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + PIOR = 0x02U; + R_CGC_Get_ResetSource(); + R_CGC_Create(); + R_PORT_Create(); + R_ADC_Create(); + R_TAU0_Create(); + R_WDT_Create(); + IAWCTL = 0x00U; +} + + +/*********************************************************************************************************************** +* Function Name: hdwinit +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void hdwinit(void) +{ + DI(); + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/stkinit.asm b/app/stkinit.asm new file mode 100644 index 0000000..ed79566 --- /dev/null +++ b/app/stkinit.asm @@ -0,0 +1,77 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/;--------------------------------------------------------------------- +; _stkinit +; +; void _stkinit(void __near * stackbss); +; +; input: +; stackbss = AX (#LOWW(_stackend)) +; output: +; NONE +;--------------------------------------------------------------------- + +; NOTE : THIS IS A TYPICAL EXAMPLE. + + .PUBLIC _stkinit + +.textf .CSEG TEXTF +_stkinit: + MOVW HL,AX ; stack_end_addr + MOV [SP+3],#0x00 ; [SP+0]-[SP+2] for return address + MOVW AX,SP + SUBW AX,HL ; SUBW AX,#LOWW _@STEND + BNH $LSTINIT3 ; goto end + SHRW AX,5 ; loop count for 32 byte transfer + MOVW BC,AX + CLRW AX +LSTINIT1: + CMPW AX,BC + BZ $LSTINIT2 + MOVW [HL],AX + MOVW [HL+2],AX + MOVW [HL+4],AX + MOVW [HL+6],AX + MOVW [HL+8],AX + MOVW [HL+10],AX + MOVW [HL+12],AX + MOVW [HL+14],AX + MOVW [HL+16],AX + MOVW [HL+18],AX + MOVW [HL+20],AX + MOVW [HL+22],AX + MOVW [HL+24],AX + MOVW [HL+26],AX + MOVW [HL+28],AX + MOVW [HL+30],AX + XCHW AX,HL + ADDW AX,#0x20 + XCHW AX,HL + DECW BC + BR $LSTINIT1 +LSTINIT2: + MOVW AX,SP + CMPW AX,HL + BZ $LSTINIT3 ; goto end + CLRW AX + MOVW [HL],AX + INCW HL + INCW HL + BR $LSTINIT2 +LSTINIT3: + RET diff --git a/app/user/MotorCtrl.c b/app/user/MotorCtrl.c new file mode 100644 index 0000000..e651586 --- /dev/null +++ b/app/user/MotorCtrl.c @@ -0,0 +1,90 @@ + +#include "MotorCtrl.h" + +#include "hwCtrl.h" +#include "PINdef.h" +#include "appTask.h" +//#include "pfdl.h" + + +uint8_t MotorState[6],MotorStateReal[6]; + + + +void MotorValueInit(void) +{ + uint8_t i = 0; + for (i = 0; i < 6; i++) + { + MotorState[i] = ACT_NOACT; + MotorStateReal[i] = ACT_NOACT; + } +} + + +void setMotorState(uint8_t motorid,uint8_t act) +{ + //motorid-=1; + if (act <= ACT_XH && motorid < 6) + { + MotorState[motorid] = act; + } +} + + + + + +#define MOTOR_DELAY_TIME_8S (800) +#define MOTOR_DELAY_TIME_6S (600) +void MotorCtrl(void)//10ms +{ + static uint16_t MotorRunCount; + switch (MotorState[0]) + { + case ACT_NOACT: + MotorRunCount = 0; + MotorStateReal[MOTOR1] = ACT_NOACT; + MotorStateReal[MOTOR2] = ACT_NOACT; + break; + case ACT_XQ: + MotorRunCount++; + MotorStateReal[MOTOR1] = ACT_XQ; + if (MotorRunCount > MOTOR_DELAY_TIME_6S) + { + MotorRunCount = MOTOR_DELAY_TIME_6S; + MotorStateReal[MOTOR2] = ACT_XQ; + } + else + { + MotorStateReal[MOTOR2] = ACT_NOACT; + + } + break; + + case ACT_XH: + MotorRunCount++; + MotorStateReal[MOTOR2] = ACT_XH; + if (MotorRunCount > MOTOR_DELAY_TIME_8S) + { + MotorRunCount = MOTOR_DELAY_TIME_8S; + MotorStateReal[MOTOR1] = ACT_XH; + } + else + { + MotorStateReal[MOTOR1] = ACT_NOACT; + } + break; + + + default: + break; + } + + MOTOR1Ctrl(MotorStateReal[MOTOR1]); + MOTOR2Ctrl(MotorStateReal[MOTOR2]); +} + + + + diff --git a/app/user/MotorCtrl.h b/app/user/MotorCtrl.h new file mode 100644 index 0000000..ef74208 --- /dev/null +++ b/app/user/MotorCtrl.h @@ -0,0 +1,20 @@ +#ifndef __MOTORCTRL_H__ +#define __MOTORCTRL_H__ + +#include "r_cg_macrodriver.h" + +#define MOTOR1 0 +#define MOTOR2 1 +#define MOTOR3 2 +#define MOTOR4 3 +#define MOTOR5 4 +#define MOTOR6 5 + + +void MotorCtrl(void); +void MotorValueInit(void); +void setMotorState(uint8_t motorid,uint8_t act); + + + +#endif diff --git a/app/user/PINdef.h b/app/user/PINdef.h new file mode 100644 index 0000000..c65f706 --- /dev/null +++ b/app/user/PINdef.h @@ -0,0 +1,25 @@ +#ifndef __PINDEF_H__ +#define __PINDEF_H__ + +#include "iodefine.h" + + + +#define SIGID_KEY1 0 +#define SIGID_KEY2 1 + + +#define IN_KEY1 P1_bit.no0 +#define IN_KEY2 P2_bit.no3 + +#define OUT_RLY1P P1_bit.no1 +#define OUT_RLY1N P1_bit.no2 +#define OUT_RLY2P P1_bit.no3 +#define OUT_RLY2N P1_bit.no4 + +#define ADCH_BAT 0 + + + +#endif + diff --git a/app/user/appTask.c b/app/user/appTask.c new file mode 100644 index 0000000..e3a6c43 --- /dev/null +++ b/app/user/appTask.c @@ -0,0 +1,157 @@ +#include "r_cg_macrodriver.h" +#include "appTask.h" +#include "event.h" +#include "r_cg_port.h" +#include "r_cg_timer.h" +#include "r_cg_wdt.h" +#include "hwCtrl.h" +#include "r_cg_adc.h" +#include "r_cg_serial.h" +#include "PINdef.h" +#include "MotorCtrl.h" + + + +extern uint16_t g_AdVal[3]; + +void HardWare_Init(void) +{ + //时基初始化 + R_TAU0_Channel0_Start(); + + //AD 初始化 + R_ADC_Start(); + R_ADC_Set_OperationOn(); + R_TAU0_Channel1_Start(); + + MOTOR1Ctrl(ACT_NOACT); + MOTOR2Ctrl(ACT_NOACT); +} + +void Variable_Init(void) +{ + MotorValueInit(); +} +#define KEY1 0 +#define KEY2 1 +void keyLogic(uint8_t keyno) +{ + switch (keyno) + { + case KEY1: + setMotorState(0,ACT_XQ); + break; + case KEY2: + setMotorState(0,ACT_XH); + break; + default: + break; + } + +} +void keyLogicRelease(uint8_t keyno) +{ + switch (keyno) + { + case KEY1: + setMotorState(0,ACT_NOACT); + break; + case KEY2: + setMotorState(0,ACT_NOACT); + break; + default: + break; + } + +} +#define KEY_DELAY_TIME 40 + +void keyScan(void)//5ms +{ + static uint16_t keydelay[9]={0,0,0,0,0,0,0,0,0}; + static uint8_t keyflag[9]={0,0,0,0,0,0,0,0,0}; + static uint8_t keep_count[9]={0,0,0,0,0,0,0,0,0}; + uint8_t keyval,i; + + keyval = GetIOState(SIGID_KEY1); + if (keyval == 1 && keyflag[KEY1] == 0) + { + keydelay[KEY1]++; + if (keydelay[KEY1] > KEY_DELAY_TIME)//30ms + { + keyflag[KEY1] = 1; + keydelay[KEY1] = KEY_DELAY_TIME; + keyLogic(KEY1); + } + } + else if (keyval == 0) + { + if (keyflag[KEY1] == 1) + { + keyLogicRelease(KEY1); + } + keyflag[KEY1] = 0; + keydelay[KEY1] = 0; + } + + keyval = GetIOState(SIGID_KEY2); + if (keyval == 1 && keyflag[KEY2] == 0) + { + keydelay[KEY2]++; + if (keydelay[KEY2] > KEY_DELAY_TIME)//30ms + { + keyflag[KEY2] = 1; + keydelay[KEY2] = KEY_DELAY_TIME; + keyLogic(KEY2); + } + + } + else if (keyval == 0) + { + if (keyflag[KEY2] == 1) + { + keyLogicRelease(KEY2); + } + keyflag[KEY2] = 0; + keydelay[KEY2] = 0; + } + +} + +void AppTask(void) +{ + static uint8_t ledno = 1,last = 0; + if (TimeBase1msFlag == 1) + { + TimeBase1msFlag = 0; + } + if (TimeBase5msFlag == 1) + { + TimeBase5msFlag = 0; + keyScan(); + + } + + + if (TimeBase10msFlag == 1) + { + TimeBase10msFlag = 0; + MotorCtrl(); + } + + if (TimeBase100msFlag == 1) + { + TimeBase100msFlag = 0; + R_WDT_Restart(); + + } + + if (TimeBase1000msFlag == 1) + { + TimeBase1000msFlag = 0; + } + +} + + + diff --git a/app/user/appTask.h b/app/user/appTask.h new file mode 100644 index 0000000..498f89b --- /dev/null +++ b/app/user/appTask.h @@ -0,0 +1,10 @@ +#ifndef __APPTASK_H__ +#define __APPTASK_H__ + + +void HardWare_Init(void); +void Variable_Init(void); +void AppTask(void); +void keyLogicRelease(uint8_t keyno); + +#endif diff --git a/app/user/event.c b/app/user/event.c new file mode 100644 index 0000000..53ec8ed --- /dev/null +++ b/app/user/event.c @@ -0,0 +1,46 @@ + +#include "event.h" + +static volatile uint16_t TimeBaseCounter; +volatile uint8_t TimeBase1msFlag; +volatile uint8_t TimeBase5msFlag; +volatile uint8_t TimeBase10msFlag; +volatile uint8_t TimeBase20msFlag; +volatile uint8_t TimeBase50msFlag; +volatile uint8_t TimeBase100msFlag; +volatile uint8_t TimeBase1000msFlag; + + +void TimeBaseCount(void) +{ + TimeBaseCounter++; + TimeBase1msFlag = 1; + if(TimeBaseCounter % 5 == 0) + { + TimeBase5msFlag = 1; + } + if(TimeBaseCounter % 10 == 0) + { + TimeBase10msFlag = 1; + } + if(TimeBaseCounter % 20 == 0) + { + TimeBase20msFlag = 1; + } + if(TimeBaseCounter % 50 == 0) + { + TimeBase50msFlag = 1; + } + if(TimeBaseCounter % 100 == 0) + { + TimeBase100msFlag = 1; + } + if(TimeBaseCounter % 1000 == 0) + { + TimeBase1000msFlag = 1; + } + if(TimeBaseCounter >= 60000) + { + TimeBaseCounter = 0; + } +} \ No newline at end of file diff --git a/app/user/event.h b/app/user/event.h new file mode 100644 index 0000000..8aab0ed --- /dev/null +++ b/app/user/event.h @@ -0,0 +1,18 @@ + + +#ifndef __EVENT_H__ +#define __EVENT_H__ +#include "r_cg_macrodriver.h" + +extern volatile uint8_t TimeBase1msFlag; +extern volatile uint8_t TimeBase5msFlag; +extern volatile uint8_t TimeBase10msFlag; +extern volatile uint8_t TimeBase20msFlag; +extern volatile uint8_t TimeBase50msFlag; +extern volatile uint8_t TimeBase100msFlag; +extern volatile uint8_t TimeBase1000msFlag; + + +extern void TimeBaseCount(void); + +#endif diff --git a/app/user/hwCtrl.c b/app/user/hwCtrl.c new file mode 100644 index 0000000..92844d2 --- /dev/null +++ b/app/user/hwCtrl.c @@ -0,0 +1,86 @@ + +#include "hwCtrl.h" +#include "r_cg_port.h" +#include "iodefine.h" +#include "appTask.h" +#include "PINdef.h" + + + + + + +uint8_t GetIOState(uint8_t sigid) +{ + switch (sigid) + { + case SIGID_KEY1: + return IN_KEY1==0?1:0; + break; + case SIGID_KEY2: + return IN_KEY2==0?1:0; + default: + return 0; + break; + } +} + + +#define OUT_OFF 0 +#define OUT_ON 1 + +void MOTOR1Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY1P = OUT_OFF; + OUT_RLY1N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY1P = OUT_ON; + OUT_RLY1N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY1P = OUT_OFF; + OUT_RLY1N = OUT_ON; + break; + default: + break; + } +} + +void MOTOR2Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY2P = OUT_OFF; + OUT_RLY2N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY2P = OUT_ON; + OUT_RLY2N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY2P = OUT_OFF; + OUT_RLY2N = OUT_ON; + break; + default: + break; + } +} + + +extern uint16_t g_AdVal[3]; +uint16_t getAdval(uint8_t ch) +{ + if (ch < 4) + { + return g_AdVal[ch]; + } + + return 0; +} + + diff --git a/app/user/hwCtrl.h b/app/user/hwCtrl.h new file mode 100644 index 0000000..7b0a0d1 --- /dev/null +++ b/app/user/hwCtrl.h @@ -0,0 +1,19 @@ + +#ifndef __HWCTRL_H__ +#define __HWCTRL_H__ +#include "r_cg_macrodriver.h" + +#define LED_ON 0 +#define LED_OFF 1 + +#define ACT_NOACT 0 +#define ACT_XQ 1 +#define ACT_XH 2 + + +uint8_t GetIOState(uint8_t sigid); +void MOTOR1Ctrl(uint8_t act); +void MOTOR2Ctrl(uint8_t act); +uint16_t getAdval(uint8_t ch); + +#endif