commit 00ac229a6a82570e8ad7b76b217c2ea85be6aa64 Author: sunbeam Date: Mon Jan 8 17:02:46 2024 +0800 初版 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d42bcf9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +QualityReport(BCZT,DefaultBuild).txt +DefaultBuild diff --git a/app/.vscode/c_cpp_properties.json b/app/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..1526a99 --- /dev/null +++ b/app/.vscode/c_cpp_properties.json @@ -0,0 +1,14 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${workspaceFolder}/**" + ], + "defines": [ + "__near=" + ] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/app/.vscode/settings.json b/app/.vscode/settings.json new file mode 100644 index 0000000..6cf0c59 --- /dev/null +++ b/app/.vscode/settings.json @@ -0,0 +1,6 @@ +{ + "files.associations": { + "motorctrl.h": "c", + "r_cg_wdt.h": "c" + } +} \ No newline at end of file diff --git a/app/BCZT.dm01.mtud b/app/BCZT.dm01.mtud new file mode 100644 index 0000000..c0e98f2 --- /dev/null +++ b/app/BCZT.dm01.mtud @@ -0,0 +1,1045 @@ + + + + UgB1AG4ALQBCAHIAZQBhAGsAIABUAGkAbQBlAHIA + + Enable + Invalid + True + 0 + 0 + 0 + 0 + 0 + VQBuAGMAbwBuAGQAaQB0AGkAbwBuAGEAbAAgAFQAcgBhAGMAZQA= + + Enable + Invalid + True + AllTrace + 0 + 0 + 0 + QgByAGUAYQBrADAAMAAwADEA + + Enable + Invalid + False + None + 1 + 1 + RQB2AGUAbgB0ACAAQwBvAG4AZABpAHQAaQBvAG4AIAAxAA== + 1 + 0 + RQB2AGUAbgB0ACAAQwBvAG4AZABpAHQAaQBvAG4AIAAxAA== + + False + False + Hardware + 1 + Execution + 0 + 0 + 0 + 1 + 0 + 4294967295 + SymbolOffset + F:\FCB_project\temp\bczt_new\CODE\BCZT\DefaultBuild\BCZT.abs + appTask.c + F:\FCB_project\temp\bczt_new\CODE\BCZT\user\ + _LIN_Rx_Handle + 4 + + Address + 2095 + ExecuteAddress + 1 + 1 + 2095 + XwBMAEkATgBfAFIAeABfAEgAYQBuAGQAbABlACsANAA= + 2095 + 0 + 113 + BreakAfter + True + 1 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + R5F10AGF + SymbolOffset + Yes + + + 0 + R5F10AGF + SymbolOffset + Yes + + + 0 + R5F10AGF + SymbolOffset + Yes + + + + + UgB1AG4ALQBCAHIAZQBhAGsAIABUAGkAbQBlAHIA + + Enable + Invalid + True + 0 + 0 + 0 + 0 + 0 + VQBuAGMAbwBuAGQAaQB0AGkAbwBuAGEAbAAgAFQAcgBhAGMAZQA= + + Enable + Invalid + True + AllTrace + 0 + 0 + 0 + QgByAGUAYQBrADAAMAAwADEA + + Enable + Invalid + False + None + 1 + 1 + RQB2AGUAbgB0ACAAQwBvAG4AZABpAHQAaQBvAG4AIAAxAA== + 1 + 0 + RQB2AGUAbgB0ACAAQwBvAG4AZABpAHQAaQBvAG4AIAAxAA== + + False + False + Hardware + 1 + Execution + 0 + 0 + 0 + 1 + 0 + 4294967295 + SymbolOffset + F:\FCB_project\temp\bczt_new\CODE\BCZT\DefaultBuild\BCZT.abs + appTask.c + F:\FCB_project\temp\bczt_new\CODE\BCZT\user\ + _LIN_Rx_Handle + 4 + + Address + 2095 + ExecuteAddress + 1 + 1 + 2095 + XwBMAEkATgBfAFIAeABfAEgAYQBuAGQAbABlACsANAA= + 2095 + 0 + 113 + BreakAfter + True + 1 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + R5F10AGF + SymbolOffset + Yes + + + 0 + R5F10AGF + SymbolOffset + Yes + + + 3 + R5F10AGF + SymbolOffset + Yes + + + + + Header=True,LineEditor=True,SelectionEditor=True,Out of Date Module Indicator=True,Coverage=True,Address=True,Event=True,MainDebug=True,Main=True,OpCode=True,Label=True, + + + 0 + + + + + True + NonStopOverwriteMemory + ST10US + All + False + OverThreshold + False + False + + + + + 12.2.20122.2006 + + + + + 12.2.20122.2006 + 9.07.00.06 + F o r m a t V e r s i o n : 1 . 0  
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   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l E v e n t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 4 6 b 8 6 6 a - 3 f 4 d - 4 b 9 4 - a 5 0 2 - d 3 0 0 e 2 d d a b 5 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 6 7 6 1 0 5 2 - 9 7 c 4 - 4 2 f 3 - b c a 7 - 1 a 6 2 5 b 9 9 3 b 4 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : c 2 2 2 5 7 3 2 - 0 5 2 5 - 4 f 5 e - a 2 8 c - 1 6 d 5 a c c 5 5 8 c 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 1 3 f f 2 5 7 - c 5 1 a - 4 c f a - 9 2 1 3 - a 7 d 0 2 f c 5 4 e 3 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d d c d 5 d 9 a - d 2 d b - 4 2 1 6 - 8 8 2 b - 8 0 2 3 0 0 d d b a 6 c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d e e 4 e 6 3 5 - b d c d - 4 b 8 b - 8 5 5 e - e 3 6 2 f 1 9 5 7 b 1 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 f e e c 6 5 b - 5 0 d e - 4 8 8 3 - 9 6 9 2 - 7 e e 0 8 1 3 5 2 9 5 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 6 3 4 7 5 7 9 - 4 4 8 9 - 4 b 9 8 - 8 e 6 5 - a c 7 8 c 9 3 2 f 4 0 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 4 d 3 8 4 5 a - 9 f 8 6 - 4 1 9 2 - 8 5 2 e - e c e 3 4 f 3 f 8 6 e 1  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e b u g C o n s o l e P a n e l  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 c 9 5 a 8 8 b - f f e 7 - 4 9 8 2 - b 4 f d - 3 c 5 7 7 b 4 c c c 6 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l F u n c t i o n L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 7 9 d c e 4 e - 9 5 4 e - 4 a c c - 9 d f e - d 6 e c b 2 e 1 d a 0 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V a r i a b l e L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 8 7 d f c 6 c - b 6 6 6 - 4 4 2 2 - b e 6 a - 7 c 5 0 e 1 0 8 d 8 e 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l A n a l y s i s C h a r t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b 5 1 9 e 0 6 e - 8 e c 8 - 4 0 a 6 - 8 8 e 2 - d 4 0 2 4 7 4 4 a 2 2 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C a l l G r a p h  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 b f b a 2 6 1 - 4 6 6 a - 4 8 e 8 - 9 d 1 5 - 4 1 e 3 a 7 0 0 a 6 0 8  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C a n R e c P r o c T i m e  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d L e f t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 6 9 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1 2  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : c d 3 f 8 0 1 2 - 4 b 0 2 - 4 6 6 c - 9 c 1 c - e 7 b b 5 7 b 0 7 4 6 0  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l I n C a r T o o l s C a t e l o g  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 f 8 b f 4 f 6 - 6 b 5 5 - 4 2 5 2 - 8 9 b 5 - c 0 6 b c 4 4 a f 8 7 3  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S t a r t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 5 f 1 a 3 c 7 - 0 b 9 1 - 4 7 9 4 - 9 d 4 a - c 2 8 a 9 b 1 f e 7 e 5  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 9 5 ,   6 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o j e c t T r e e  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 3 8 7 2 8 3 3 - 3 f 3 1 - 4 a c c - 8 8 9 2 - 7 7 d 4 7 7 0 a e a 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t M a n u a l  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 2 8 f 4 2 9 3 - e b f 0 - 4 2 4 3 - 9 d 0 0 - 9 a 1 2 6 5 c 2 9 b 9 b  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o p e r t y G r i d  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 a 5 8 5 c 8 c - 0 2 4 d - 4 4 1 1 - 8 3 b d - 6 5 5 d e 7 3 9 f 1 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y M a p p i n g P r o f i l e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 7 9 d 4 9 2 4 - a 5 a 8 - 4 3 d 1 - b c 4 9 - 6 7 6 c c 7 b 8 c 6 0 4  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 4 ,   4 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 b 0 c 7 8 6 a - 8 3 f c - 4 b b 9 - b e 8 e - f 9 b 9 8 e 1 4 0 7 b 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 8 5 6 6 b b 9 - 6 7 b 1 - 4 9 1 d - b a 9 e - 7 5 4 a 9 c d f 4 e 4 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 f e 5 5 d d b - 4 e f 1 - 4 c f 1 - 9 e 7 8 - 8 e c f a 5 0 e e a 7 e  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 b 2 9 2 d d 0 - 0 7 7 b - 4 7 2 9 - 8 e 8 c - b b 0 6 a 2 6 d c 2 9 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C l a s s M e m b e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 b 9 9 1 c 4 6 - c 1 d 2 - 4 2 e 5 - b e 4 3 - f 3 4 b c f 9 f 7 3 9 8  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O r t h o g o n a l A n a l y s i s  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 3 7 ,   5 7 8  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 8 4 5 ,   6 4 3  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : H o r i z o n t a l S p l i t  
 D o c k A r e a P a n e . P a n e s . C o u n t : 0  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d B o t t o m  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 1 2 4 1 ,   2 6 5  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 8 4 5 ,   6 4 3  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 4  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 3 2 f 6 e 3 d - 2 0 f b - 4 0 b 8 - 8 b 3 d - a 6 4 4 d 4 7 6 b 3 4 0  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O u t p u t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 c 5 f 6 5 9 c - 5 b 3 4 - 4 8 f 6 - a 8 3 7 - 0 8 a a 3 2 2 f 9 e 4 6  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t B r o w s e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 6 b d 1 a 9 9 - 1 6 8 8 - 4 2 d 8 - 8 a c 6 - 1 7 3 a 1 5 0 9 e 2 d c  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 8 1 6 ,   1 7 1  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : b 9 c 5 7 7 d c - 7 e a b - 4 3 6 d - 8 7 9 d - d a 4 6 e 7 9 b 2 b b 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l E r r o r L i s t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f b 6 d 3 f 1 9 - f 7 9 a - 4 b 4 2 - b a 0 a - 6 9 c c a f f d 5 f 6 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 9 2 8 2 3 3 4 - 6 9 5 2 - 4 7 8 a - b 0 8 e - 1 4 5 9 2 0 3 f 8 9 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P y t h o n C o n s o l e  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c a 1 c b 8 1 f - 7 9 1 0 - 4 b 3 7 - b c 8 5 - 9 6 a 4 1 d b d e 4 7 2  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 5 6 ,   2 5 6  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 9 2 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 3 8 1 4 d 2 e - 5 2 5 8 - 4 3 2 e - 8 1 4 7 - e 2 e a 2 9 a e a 3 7 5  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : c a 1 c b 8 1 f - 7 9 1 0 - 4 b 3 7 - b c 8 5 - 9 6 a 4 1 d b d e 4 7 2  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D e b u g M a n a g e r  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 6 5 5 a e 3 1 a - 9 4 6 6 - 4 d c 0 - 8 f 2 3 - a d 1 8 b e 2 8 a 2 4 2  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : e 8 a 8 1 4 e d - 6 d e 6 - 4 2 0 b - b a b c - 0 1 b c 1 6 d 1 e 4 b d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 5 5 a e 3 1 a - 9 4 6 6 - 4 d c 0 - 8 f 2 3 - a d 1 8 b e 2 8 a 2 4 2  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 5 8 c f 3 8 7 - 3 1 7 f - 4 2 c 2 - 8 f 7 7 - 6 b c d a 7 d 1 d 0 6 c  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 d 0 8 e b 0 5 - 6 3 8 3 - 4 e f 8 - 8 b c 5 - f 2 e 2 c 5 7 6 4 5 8 f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 9 5 8 c f 3 8 7 - 3 1 7 f - 4 2 c 2 - 8 f 7 7 - 6 b c d a 7 d 1 d 0 6 c  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e L i s t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 4 8 9 6 5 1 2 2 - a 4 0 a - 4 5 f f - b 9 d 6 - 6 2 2 7 d e 1 4 5 a 8 c  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 2 9 5 8 a 7 9 c - e 6 6 b - 4 4 d f - 9 c a 8 - 9 b 7 3 f 3 5 7 a b 6 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 4 8 9 6 5 1 2 2 - a 4 0 a - 4 5 f f - b 9 d 6 - 6 2 2 7 d e 1 4 5 a 8 c  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : M a c r o P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 f 9 2 4 0 f 1 - 8 e c d - 4 1 2 0 - 9 4 e e - 8 3 5 a b c b 7 6 c d 9  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 9 f 5 7 c d 6 - 8 1 d e - 4 6 d e - 8 8 9 0 - 5 0 f 3 3 a d 5 e c 9 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 f 9 2 4 0 f 1 - 8 e c d - 4 1 2 0 - 9 4 e e - 8 3 5 a b c b 7 6 c d 9  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : T e x t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : d 6 d 5 6 c 1 2 - e 9 4 c - 4 1 a c - a 6 8 5 - c 7 b a e 5 4 6 6 4 1 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   6 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 4 a 9 1 a 4 3 - e 8 a 5 - 4 2 9 7 - 9 0 8 0 - e 9 2 a f e 8 0 f 1 d c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : d 6 d 5 6 c 1 2 - e 9 4 c - 4 1 a c - a 6 8 5 - c 7 b a e 5 4 6 6 4 1 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V i r t u a l B o a r d  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c 2 1 9 3 d 6 8 - 7 b 5 4 - 4 d 5 2 - b a 9 3 - b 2 a 0 b 7 4 9 1 d 0 9  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 6 5 d 7 2 7 8 - 3 4 5 3 - 4 6 d 4 - 9 2 e c - e 0 3 2 1 6 c 9 5 d 2 b  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : c 2 1 9 3 d 6 8 - 7 b 5 4 - 4 d 5 2 - b a 9 3 - b 2 a 0 b 7 4 9 1 d 0 9  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e P i n L i s t F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 8 0 0 e 8 e 9 7 - 1 9 7 5 - 4 b 1 a - 8 5 9 4 - c 0 5 3 c e 9 9 0 2 0 d  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : e 9 3 9 3 4 6 9 - d 9 b 8 - 4 5 a 3 - a 8 9 a - e 2 1 0 c 4 f 7 2 c 1 8  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 8 0 0 e 8 e 9 7 - 1 9 7 5 - 4 b 1 a - 8 5 9 4 - c 0 5 3 c e 9 9 0 2 0 d  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p V i e w F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 c b 6 c 0 d 2 - 7 1 7 1 - 4 7 c 5 - 9 d b 7 - 4 a 1 f f 4 e b 4 9 7 0  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 2 3 2 6 6 6 3 - 8 1 1 0 - 4 8 e 5 - 9 f 6 e - f 1 d b 6 d 6 2 2 5 3 0  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 9 c b 6 c 0 d 2 - 7 1 7 1 - 4 7 c 5 - 9 d b 7 - 4 a 1 f f 4 e b 4 9 7 0  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : b 2 a 2 9 8 2 f - 8 f 8 c - 4 4 e 6 - 8 5 1 2 - 3 d 9 6 b 7 3 e a a 2 b  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   5 0 3  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 8 0 e 4 4 5 3 - 9 6 d f - 4 1 9 f - 9 2 b c - f 4 b e b 4 c d d 9 5 7  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : b 2 a 2 9 8 2 f - 8 f 8 c - 4 4 e 6 - 8 5 1 2 - 3 d 9 6 b 7 3 e a a 2 b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t P r e v i e w  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 e 1 d 8 3 c 2 - a 1 2 1 - 4 5 a f - a 3 1 4 - 1 d 8 5 4 6 8 c 1 1 1 2  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 6 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 6 2 e b 3 a f - 2 e 9 8 - 4 4 7 f - b 3 6 8 - 3 d 6 1 9 e 2 3 c 5 d a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 5 e 1 d 8 3 c 2 - a 1 2 1 - 4 5 a f - a 3 1 4 - 1 d 8 5 4 6 8 c 1 1 1 2  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P s e u d o E r r o r D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 9 1 d 8 f 1 2 - c b 3 c - 4 3 6 e - 8 1 7 e - 1 3 0 a a 1 5 9 d 4 6 c  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 5 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 1 0 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f c e 8 c e 2 2 - 2 b c a - 4 6 9 c - 8 b b 8 - a 4 6 b 4 3 1 d 3 0 8 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 9 9 1 d 8 f 1 2 - c b 3 c - 4 3 6 e - 8 1 7 e - 1 3 0 a a 1 5 9 d 4 6 c  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C A N R e c e i v e D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : f a b c c f b 8 - 4 f 6 5 - 4 d 3 b - a a a a - c f 2 7 a 7 9 6 1 a 3 7  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : c 8 2 8 5 8 f a - 2 d 6 5 - 4 f 0 e - 8 3 0 1 - 1 e 5 0 5 c 5 4 7 0 a 0  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : f a b c c f b 8 - 4 f 6 5 - 4 d 3 b - a a a a - c f 2 7 a 7 9 6 1 a 3 7  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C u r C o n s u m p t i o n  
  + < S O A P - E N V : E n v e l o p e   x m l n s : x s i = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a - i n s t a n c e "   x m l n s : x s d = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a "   x m l n s : S O A P - E N C = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / "   x m l n s : S O A P - E N V = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n v e l o p e / "   x m l n s : c l r = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / s o a p / e n c o d i n g / c l r / 1 . 0 "   S O A P - E N V : e n c o d i n g S t y l e = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / " >  
 < S O A P - E N V : B o d y >  
 < a 1 : O b j e c t S t r e a m e r   i d = " r e f - 1 "   x m l n s : a 1 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i " >  
 < O b j e c t S t r e a m e r A s s e m b l y N a m e   i d = " r e f - 5 " > I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i < / O b j e c t S t r e a m e r A s s e m b l y N a m e >  
 < T a b S e t t i n g s   h r e f = " # r e f - 6 " / >  
 < H i d d e n T a b s   h r e f = " # r e f - 7 " / >  
 < T a b G r o u p s   h r e f = " # r e f - 8 " / >  
 < M a x T a b G r o u p s > 4 < / M a x T a b G r o u p s >  
 < A c t i v e T a b G r o u p I n d e x > 0 < / A c t i v e T a b G r o u p I n d e x >  
 < S p l i t t e r A p p e a r a n c e   h r e f = " # r e f - 9 " / >  
 < S p l i t t e r B o r d e r S t y l e > 6 < / S p l i t t e r B o r d e r S t y l e >  
 < V i e w S t y l e > 4 < / V i e w S t y l e >  
 < T a b G r o u p S e t t i n g s   h r e f = " # r e f - 1 0 " / >  
 < / a 1 : O b j e c t S t r e a m e r >  
 < a 2 : M d i T a b S e t t i n g s   i d = " r e f - 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < A c t i v e T a b A p p e a r a n c e   h r e f = " # r e f - 1 1 " / >  
 < D i s p l a y F o r m I c o n > 1 < / D i s p l a y F o r m I c o n >  
 < H o t T r a c k > 1 < / H o t T r a c k >  
 < S e l e c t e d T a b A p p e a r a n c e   h r e f = " # r e f - 1 2 " / >  
 < T a b A p p e a r a n c e   h r e f = " # r e f - 1 3 " / >  
 < / a 2 : M d i T a b S e t t i n g s >  
 < a 2 : H i d d e n M d i T a b s C o l l e c t i o n   i d = " r e f - 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 5 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 1 4 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 1 5 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 1 6 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 1 7 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 1 8 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 1 9 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 2 0 " / >  
 < _ x 0 0 3 7 _   h r e f = " # r e f - 2 1 " / >  
 < _ x 0 0 3 8 _   h r e f = " # r e f - 2 2 " / >  
 < _ x 0 0 3 9 _   h r e f = " # r e f - 2 3 " / >  
 < _ x 0 0 3 1 _ 0   h r e f = " # r e f - 2 4 " / >  
 < _ x 0 0 3 1 _ 1   h r e f = " # r e f - 2 5 " / >  
 < _ x 0 0 3 1 _ 2   h r e f = " # r e f - 2 6 " / >  
 < _ x 0 0 3 1 _ 3   h r e f = " # r e f - 2 7 " / >  
 < _ x 0 0 3 1 _ 4   h r e f = " # r e f - 2 8 " / >  
 < / a 2 : H i d d e n M d i T a b s C o l l e c t i o n >  
 < a 2 : M d i T a b G r o u p s C o l l e c t i o n   i d = " r e f - 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 2 9 " / >  
 < / a 2 : M d i T a b G r o u p s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 9 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 0 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b G r o u p S e t t i n g s   i d = " r e f - 1 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C l o s e B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 1 " / >  
 < T a b L i s t B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 2 " / >  
 < S c r o l l B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 3 " / >  
 < T a b A r e a A p p e a r a n c e   h r e f = " # r e f - 3 4 " / >  
 < S h o w T a b L i s t B u t t o n > 1 < / S h o w T a b L i s t B u t t o n >  
 < T a b B u t t o n S t y l e > 1 6 < / T a b B u t t o n S t y l e >  
 < S c r o l l A r r o w S t y l e > 2 < / S c r o l l A r r o w S t y l e >  
 < S c r o l l B u t t o n s > 3 < / S c r o l l B u t t o n s >  
 < T a b S t y l e > 2 < / T a b S t y l e >  
 < T a b A r e a M a r g i n s   h r e f = " # r e f - 3 5 " / >  
 < C l o s e B u t t o n L o c a t i o n > 2 < / C l o s e B u t t o n L o c a t i o n >  
 < / a 2 : M d i T a b G r o u p S e t t i n g s >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 1 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 6 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 7 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 8 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b   i d = " r e f - 1 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 9 7 3 9 2 0 6 2 8 < / _ a >  
 < _ b > 5 8 9 < / _ b >  
 < _ c > 1 7 4 2 5 < / _ c >  
 < _ d > 1 3 1 < / _ d >  
 < _ e > 1 8 9 < / _ e >  
 < _ f > 1 0 1 < / _ f >  
 < _ g > 9 3 < / _ g >  
 < _ h > 2 3 1 < / _ h >  
 < _ i > 5 7 < / _ i >  
 < _ j > 2 4 1 < / _ j >  
 < _ k > 7 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 7 5 1 2 9 9 8 0 4 < / _ a >  
 < _ b > - 2 3 1 2 8 < / _ b >  
 < _ c > 1 7 3 6 1 < / _ c >  
 < _ d > 1 8 8 < / _ d >  
 < _ e > 7 3 < / _ e >  
 < _ f > 1 0 3 < / _ f >  
 < _ g > 1 0 8 < / _ g >  
 < _ h > 1 9 9 < / _ h >  
 < _ i > 1 8 4 < / _ i >  
 < _ j > 1 9 8 < / _ j >  
 < _ k > 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 9 9 0 6 7 3 0 0 2 < / _ a >  
 < _ b > - 3 1 7 4 8 < / _ b >  
 < _ c > 1 9 3 8 5 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 4 2 < / _ e >  
 < _ f > 2 4 9 < / _ f >  
 < _ g > 1 8 5 < / _ g >  
 < _ h > 1 4 2 < / _ h >  
 < _ i > 2 0 < / _ i >  
 < _ j > 7 < / _ j >  
 < _ k > 1 8 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 2 8 5 5 4 0 5 5 < / _ a >  
 < _ b > 2 6 5 4 5 < / _ b >  
 < _ c > 1 8 7 1 7 < / _ c >  
 < _ d > 1 8 6 < / _ d >  
 < _ e > 1 5 8 < / _ e >  
 < _ f > 1 1 7 < / _ f >  
 < _ g > 7 4 < / _ g >  
 < _ h > 1 5 6 < / _ h >  
 < _ i > 2 2 3 < / _ i >  
 < _ j > 7 8 < / _ j >  
 < _ k > 7 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 2 1 4 5 7 3 8 2 0 3 < / _ a >  
 < _ b > 2 0 2 0 9 < / _ b >  
 < _ c > 1 9 6 9 7 < / _ c >  
 < _ d > 1 5 8 < / _ d >  
 < _ e > 1 2 0 < / _ e >  
 < _ f > 1 4 2 < / _ f >  
 < _ g > 2 0 7 < / _ g >  
 < _ h > 1 6 5 < / _ h >  
 < _ i > 1 4 < / _ i >  
 < _ j > 2 3 4 < / _ j >  
 < _ k > 1 2 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 2 6 8 3 2 5 4 4 6 < / _ a >  
 < _ b > - 1 5 9 1 8 < / _ b >  
 < _ c > 1 7 1 2 5 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 6 7 < / _ e >  
 < _ f > 2 4 3 < / _ f >  
 < _ g > 7 5 < / _ g >  
 < _ h > 2 0 7 < / _ h >  
 < _ i > 1 5 9 < / _ i >  
 < _ j > 1 1 5 < / _ j >  
 < _ k > 1 5 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 3 9 1 6 3 7 7 7 9 < / _ a >  
 < _ b > 2 8 1 3 4 < / _ b >  
 < _ c > 1 6 9 0 7 < / _ c >  
 < _ d > 1 8 6 < / _ d >  
 < _ e > 1 8 8 < / _ e >  
 < _ f > 1 < / _ f >  
 < _ g > 1 8 8 < / _ g >  
 < _ h > 2 2 < / _ h >  
 < _ i > 2 0 9 < / _ i >  
 < _ j > 2 2 8 < / _ j >  
 < _ k > 1 8 9 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 0 2 3 9 9 4 6 2 9 < / _ a >  
 < _ b > 2 5 4 7 5 < / _ b >  
 < _ c > 2 0 2 1 6 < / _ c >  
 < _ d > 1 3 9 < / _ d >  
 < _ e > 1 9 7 < / _ e >  
 < _ f > 2 4 2 < / _ f >  
 < _ g > 2 2 6 < / _ g >  
 < _ h > 1 9 7 < / _ h >  
 < _ i > 1 1 8 < / _ i >  
 < _ j > 6 9 < / _ j >  
 < _ k > 1 4 3 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 6 9 3 6 7 5 9 3 2 < / _ a >  
 < _ b > - 6 5 4 9 < / _ b >  
 < _ c > 1 7 6 3 1 < / _ c >  
 < _ d > 1 5 6 < / _ d >  
 < _ e > 1 6 8 < / _ e >  
 < _ f > 1 5 5 < / _ f >  
 < _ g > 1 1 5 < / _ g >  
 < _ h > 2 4 3 < / _ h >  
 < _ i > 8 7 < / _ i >  
 < _ j > 1 7 1 < / _ j >  
 < _ k > 1 0 9 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 7 1 1 9 6 4 9 7 0 < / _ a >  
 < _ b > - 3 2 2 9 0 < / _ b >  
 < _ c > 1 8 1 4 2 < / _ c >  
 < _ d > 1 3 6 < / _ d >  
 < _ e > 1 4 4 < / _ e >  
 < _ f > 8 0 < / _ f >  
 < _ g > 2 4 3 < / _ g >  
 < _ h > 5 8 < / _ h >  
 < _ i > 2 1 3 < / _ i >  
 < _ j > 2 3 6 < / _ j >  
 < _ k > 1 5 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 2 0 1 4 2 0 0 9 1 5 < / _ a >  
 < _ b > - 2 6 9 1 3 < / _ b >  
 < _ c > 1 6 7 9 9 < / _ c >  
 < _ d > 1 4 6 < / _ d >  
 < _ e > 1 8 8 < / _ e >  
 < _ f > 2 4 4 < / _ f >  
 < _ g > 1 9 0 < / _ g >  
 < _ h > 1 8 0 < / _ h >  
 < _ i > 2 0 5 < / _ i >  
 < _ j > 2 1 7 < / _ j >  
 < _ k > 8 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 4 2 4 7 4 3 4 8 < / _ a >  
 < _ b > - 1 8 8 4 2 < / _ b >  
 < _ c > 1 7 4 4 2 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 0 6 < / _ e >  
 < _ f > 1 2 4 < / _ f >  
 < _ g > 8 0 < / _ g >  
 < _ h > 2 2 5 < / _ h >  
 < _ i > 8 < / _ i >  
 < _ j > 2 1 6 < / _ j >  
 < _ k > 2 3 1 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 2 5 6 5 9 5 3 4 6 < / _ a >  
 < _ b > - 2 8 9 8 4 < / _ b >  
 < _ c > 1 6 5 5 0 < / _ c >  
 < _ d > 1 3 6 < / _ d >  
 < _ e > 2 2 6 < / _ e >  
 < _ f > 2 1 2 < / _ f >  
 < _ g > 2 < / _ g >  
 < _ h > 7 1 < / _ h >  
 < _ i > 6 8 < / _ i >  
 < _ j > 1 6 2 < / _ j >  
 < _ k > 4 3 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 8 5 1 4 7 6 4 6 2 < / _ a >  
 < _ b > 1 9 2 0 2 < / _ b >  
 < _ c > 1 8 0 2 8 < / _ c >  
 < _ d > 1 5 6 < / _ d >  
 < _ e > 2 8 < / _ e >  
 < _ f > 2 3 1 < / _ f >  
 < _ g > 1 8 7 < / _ g >  
 < _ h > 8 7 < / _ h >  
 < _ i > 1 7 6 < / _ i >  
 < _ j > 1 1 6 < / _ j >  
 < _ k > 9 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 8 7 1 4 4 3 1 9 0 < / _ a >  
 < _ b > 2 7 4 7 7 < / _ b >  
 < _ c > 1 6 9 7 8 < / _ c >  
 < _ d > 1 3 7 < / _ d >  
 < _ e > 1 8 1 < / _ e >  
 < _ f > 1 9 2 < / _ f >  
 < _ g > 1 0 7 < / _ g >  
 < _ h > 1 9 6 < / _ h >  
 < _ i > 7 4 < / _ i >  
 < _ j > 2 4 8 < / _ j >  
 < _ k > 1 1 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b G r o u p   i d = " r e f - 2 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < T a b s   h r e f = " # r e f - 4 0 " / >  
 < E x t e n t > 4 0 7 < / E x t e n t >  
 < F i r s t D i s p l a y T a b I n d e x > 0 < / F i r s t D i s p l a y T a b I n d e x >  
 < S e l e c t e d T a b I n d e x > 5 < / S e l e c t e d T a b I n d e x >  
 < / a 2 : M d i T a b G r o u p >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 0 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 5 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 6 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 1 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 2 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 3 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 4 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 5 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : M a r g i n s   i d = " r e f - 3 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < L e f t D e f a u l t > 0 < / L e f t D e f a u l t >  
 < T o p D e f a u l t > 0 < / T o p D e f a u l t >  
 < R i g h t D e f a u l t > 0 < / R i g h t D e f a u l t >  
 < B o t t o m D e f a u l t > 0 < / B o t t o m D e f a u l t >  
 < B o t t o m > 4 < / B o t t o m >  
 < / a 3 : M a r g i n s >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 6 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 7 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 8 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b s C o l l e c t i o n   i d = " r e f - 4 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 0 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 4 6 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 4 7 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 4 8 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 4 9 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 5 0 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 5 1 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 5 2 " / >  
 < _ x 0 0 3 7 _   h r e f = " # r e f - 5 3 " / >  
 < _ x 0 0 3 8 _   h r e f = " # r e f - 5 4 " / >  
 < _ x 0 0 3 9 _   h r e f = " # r e f - 5 5 " / >  
 < / a 2 : M d i T a b s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b   i d = " r e f - 4 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 6 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 0 b c b 0 3 9 6 - f 8 7 2 - 4 c 8 c - b 1 b 9 - 0 3 0 f 5 d 0 2 5 8 a 4 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 7 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ u s e r \ a p p T a s k . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 1 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 4 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 8 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 2 a f 7 a a 0 - c 7 3 f - 4 3 f 8 - 8 3 9 7 - 4 3 8 6 4 6 b d b 1 a b < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 9 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ R L I N _ d r i v e r \ R L I N _ d r i v e r . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 4 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 0 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 3 d 0 0 a d 2 3 - 9 d d 3 - 4 b 2 f - 9 2 8 8 - 7 c 9 d 8 f 9 d e c e d < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 1 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ r _ m a i n . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 4 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 2 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > b 6 c 4 7 9 8 b - d 6 8 0 - 4 8 7 a - 8 a a 0 - a 0 2 2 0 9 6 f 0 0 f 7 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 3 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ u s e r \ h w C t r l . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 4 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 8 7 9 4 7 c 1 - b 3 7 4 - 4 f 7 5 - 8 f 5 8 - 6 e b d 9 5 8 7 a f 3 e < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 5 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ r _ c g _ c g c . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 3 0 5 2 9 2 8 9 9 < / _ a >  
 < _ b > - 3 2 4 9 6 < / _ b >  
 < _ c > 1 8 6 6 1 < / _ c >  
 < _ d > 1 5 9 < / _ d >  
 < _ e > 1 1 0 < / _ e >  
 < _ f > 2 4 1 < / _ f >  
 < _ g > 2 1 9 < / _ g >  
 < _ h > 1 0 9 < / _ h >  
 < _ i > 9 8 < / _ i >  
 < _ j > 3 7 < / _ j >  
 < _ k > 4 8 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 1 0 4 5 4 0 5 2 5 < / _ a >  
 < _ b > - 5 1 3 6 < / _ b >  
 < _ c > 1 6 9 6 3 < / _ c >  
 < _ d > 1 5 7 < / _ d >  
 < _ e > 0 < / _ e >  
 < _ f > 1 5 4 < / _ f >  
 < _ g > 1 8 < / _ g >  
 < _ h > 1 0 1 < / _ h >  
 < _ i > 1 9 4 < / _ i >  
 < _ j > 1 5 5 < / _ j >  
 < _ k > 1 5 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 7 1 7 4 0 0 1 8 4 < / _ a >  
 < _ b > 1 3 3 9 5 < / _ b >  
 < _ c > 1 8 1 3 2 < / _ c >  
 < _ d > 1 4 6 < / _ d >  
 < _ e > 2 3 6 < / _ e >  
 < _ f > 2 2 4 < / _ f >  
 < _ g > 5 0 < / _ g >  
 < _ h > 2 2 < / _ h >  
 < _ i > 2 0 1 < / _ i >  
 < _ j > 9 3 < / _ j >  
 < _ k > 4 3 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 3 8 2 1 2 6 9 9 9 < / _ a >  
 < _ b > - 9 8 0 0 < / _ b >  
 < _ c > 1 7 8 2 7 < / _ c >  
 < _ d > 1 6 8 < / _ d >  
 < _ e > 1 5 4 < / _ e >  
 < _ f > 2 2 6 < / _ f >  
 < _ g > 1 6 < / _ g >  
 < _ h > 1 9 6 < / _ h >  
 < _ i > 2 4 7 < / _ i >  
 < _ j > 4 4 < / _ j >  
 < _ k > 2 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 6 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 e 6 7 d 7 2 d - c 9 4 6 - 4 5 7 b - a c 8 8 - b 6 f a e 3 b b 5 e 2 1 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 7 " > F : \ F C B _ p r o j e c t \ t e m p \ M 2 6 \ B C Z T \ D a t a F l a s h \ r _ p f d l . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < / S O A P - E N V : B o d y >  
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                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        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+ + + + + 12.2.20122.2006 + 9.07.00.06 + F o r m a t V e r s i o n : 1 . 0  
 D o c k A r e a s . C o u n t : 1 6  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 3 9 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 0 2 ,   1 3 8  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : H o r i z o n t a l S p l i t  
 D o c k A r e a P a n e . P a n e s . C o u n t : 2  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 3 5 2 ,   4 6 9  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e G r o u p P a n e  
   D o c k a b l e G r o u p P a n e . S e l e c t e d T a b I n d e x : 0  
   D o c k a b l e G r o u p P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
   D o c k a b l e G r o u p P a n e . P a n e s . C o u n t : 2 0  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 b 8 0 4 6 0 8 - a 4 8 9 - 4 1 f b - b 4 5 4 - c b 7 7 c 5 7 e 6 5 b 5  
     D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
     D o c k a b l e P a n e B a s e . S i z e : 3 5 2 ,   4 4 9  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l L o c a l V a r i a b l e  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 3 d 0 9 d f 1 - 3 e 6 3 - 4 6 3 5 - b 9 8 6 - 5 e f a 1 f 6 a 4 a 5 9  
     D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C p u R e g i s t e r  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 f 7 3 7 1 1 2 - b 2 5 7 - 4 3 d 1 - b 9 f 3 - b d 6 5 d e 8 e 1 f 6 3  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l I O R e g i s t e r  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : b c f d 5 2 9 a - 6 a 3 a - 4 f 3 8 - a d 1 6 - 6 8 a 0 9 c 1 3 2 0 d c  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C a l l S t a c k  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 4 4 8 9 2 e a - 3 a c b - 4 e c 5 - 9 c b 0 - 6 a 1 f c 4 f c 5 8 5 d  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l T r a c e  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 f 6 0 3 6 4 b - e 7 4 a - 4 6 3 d - b 7 1 5 - d 2 7 9 9 3 8 c 6 4 6 3  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l E v e n t  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 4 6 b 8 6 6 a - 3 f 4 d - 4 b 9 4 - a 5 0 2 - d 3 0 0 e 2 d d a b 5 b  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 1  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 6 7 6 1 0 5 2 - 9 7 c 4 - 4 2 f 3 - b c a 7 - 1 a 6 2 5 b 9 9 3 b 4 7  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 2  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : c 2 2 2 5 7 3 2 - 0 5 2 5 - 4 f 5 e - a 2 8 c - 1 6 d 5 a c c 5 5 8 c 7  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 3  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 1 3 f f 2 5 7 - c 5 1 a - 4 c f a - 9 2 1 3 - a 7 d 0 2 f c 5 4 e 3 7  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l W a t c h 4  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : d d c d 5 d 9 a - d 2 d b - 4 2 1 6 - 8 8 2 b - 8 0 2 3 0 0 d d b a 6 c  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 1  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : d e e 4 e 6 3 5 - b d c d - 4 b 8 b - 8 5 5 e - e 3 6 2 f 1 9 5 7 b 1 b  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 2  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 f e e c 6 5 b - 5 0 d e - 4 8 8 3 - 9 6 9 2 - 7 e e 0 8 1 3 5 2 9 5 6  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 3  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 6 3 4 7 5 7 9 - 4 4 8 9 - 4 b 9 8 - 8 e 6 5 - a c 7 8 c 9 3 2 f 4 0 a  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 2 9 3 ,   3 8 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y 4  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 c a 3 8 7 0 6 - a b 4 f - 4 a 8 1 - 9 1 d 7 - b 1 0 a 3 1 6 9 b b 7 5  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e b u g C o n s o l e P a n e l  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 4 c 5 6 5 9 1 8 - 6 6 4 f - 4 9 8 8 - a 6 2 2 - 6 9 4 8 6 7 9 f a a 2 4  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l F u n c t i o n L i s t  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 3 e e 1 2 0 0 - 5 5 0 9 - 4 e b c - a c 8 c - 2 6 6 9 a e 7 7 6 e b 3  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V a r i a b l e L i s t  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 0 6 8 a e 3 e - 4 d 9 8 - 4 6 d d - 8 0 b 2 - 1 4 6 c 6 2 e e 1 d 9 a  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l A n a l y s i s C h a r t  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : a 8 5 d f f 0 5 - 0 7 c 0 - 4 d a f - b 5 9 a - d 6 a a 9 e 4 3 0 0 d f  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C a l l G r a p h  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 0 2 1 c 9 4 6 - a 5 6 2 - 4 d 4 5 - 8 6 7 1 - 4 8 b d f 3 7 0 6 c c 2  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 c 1 a 3 f 7 8 - 3 4 a 9 - 4 e 5 4 - 9 7 d d - 8 f 8 0 e 4 4 e 6 4 1 3  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C a n R e c P r o c T i m e  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 1 1 c 0 2 2 a - 3 a 1 1 - 4 6 8 8 - a c 2 f - f 8 8 9 3 c 7 a 8 5 f e  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 3 5 2 ,   1 7 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 6 0 7 8 9 7 8 7 - f f a 7 - 4 f f 2 - b c 7 4 - c 3 3 f f f a 0 3 a b b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e G r o u p P a n e  
   D o c k a b l e G r o u p P a n e . S e l e c t e d T a b I n d e x : 0  
   D o c k a b l e G r o u p P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
   D o c k a b l e G r o u p P a n e . P a n e s . C o u n t : 3  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 3 2 f 6 e 3 d - 2 0 f b - 4 0 b 8 - 8 b 3 d - a 6 4 4 d 4 7 6 b 3 4 0  
     D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
     D o c k a b l e P a n e B a s e . S i z e : 3 5 2 ,   1 7 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : d 1 1 c 0 2 2 a - 3 a 1 1 - 4 6 8 8 - a c 2 f - f 8 8 9 3 c 7 a 8 5 f e  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O u t p u t  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 c 5 f 6 5 9 c - 5 b 3 4 - 4 8 f 6 - a 8 3 7 - 0 8 a a 3 2 2 f 9 e 4 6  
     D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
     D o c k a b l e P a n e B a s e . S i z e : 3 5 2 ,   1 7 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : d 1 1 c 0 2 2 a - 3 a 1 1 - 4 6 8 8 - a c 2 f - f 8 8 9 3 c 7 a 8 5 f e  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t B r o w s e r  
 - - D o c k a b l e P a n e B a s e - -  
     D o c k a b l e P a n e B a s e . I n t e r n a l I d : e 1 a b 6 c 0 0 - 7 4 1 0 - 4 8 4 1 - 9 7 1 0 - 3 0 8 e 1 5 7 a 8 3 f e  
     D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
     D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
     D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : d 1 1 c 0 2 2 a - 3 a 1 1 - 4 6 8 8 - a c 2 f - f 8 8 9 3 c 7 a 8 5 f e  
     D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
     D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
     D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
     D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
     D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
     D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P y t h o n C o n s o l e  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d L e f t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 6 9 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1 2  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d d 2 7 c 5 0 2 - 3 e 8 9 - 4 d b 8 - b 2 4 5 - 6 e b 7 3 7 d a c c e 3  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l I n C a r T o o l s C a t e l o g  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 6 f 8 b f 4 f 6 - 6 b 5 5 - 4 2 5 2 - 8 9 b 5 - c 0 6 b c 4 4 a f 8 7 3  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 5 7 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S t a r t  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 5 f 1 a 3 c 7 - 0 b 9 1 - 4 7 9 4 - 9 d 4 a - c 2 8 a 9 b 1 f e 7 e 5  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 1 9 5 ,   6 4 4  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o j e c t T r e e  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 1 3 8 7 2 8 3 3 - 3 f 3 1 - 4 a c c - 8 8 9 2 - 7 7 d 4 7 7 0 a e a 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : 3 5 0 ,   5 0 0  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l S m a r t M a n u a l  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 2 8 f 4 2 9 3 - e b f 0 - 4 2 4 3 - 9 d 0 0 - 9 a 1 2 6 5 c 2 9 b 9 b  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 4 5 7 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P r o p e r t y G r i d  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 8 a 5 8 5 c 8 c - 0 2 4 d - 4 4 1 1 - 8 3 b d - 6 5 5 d e 7 3 9 f 1 4 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e m o r y M a p p i n g P r o f i l e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 7 9 d 4 9 2 4 - a 5 a 8 - 4 3 d 1 - b c 4 9 - 6 7 6 c c 7 b 8 c 6 0 4  
   D o c k a b l e P a n e B a s e . C l o s e d : F a l s e  
   D o c k a b l e P a n e B a s e . S i z e : 4 5 7 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 1  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 b 0 c 7 8 6 a - 8 3 f c - 4 b b 9 - b e 8 e - f 9 b 9 8 e 1 4 0 7 b 6  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 2  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : f 8 5 6 6 b b 9 - 6 7 b 1 - 4 9 1 d - b a 9 e - 7 5 4 a 9 c d f 4 e 4 d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 3  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 f e 5 5 d d b - 4 e f 1 - 4 c f 1 - 9 e 7 8 - 8 e c f a 5 0 e e a 7 e  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 4 7 4 ,   6 2 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D i s a s s e m b l e 4  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 f 1 0 f e 1 5 - 2 4 3 e - 4 1 3 5 - 9 9 8 4 - 7 a f 8 9 b 2 c f f d 2  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C l a s s M e m b e r  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 2 e 4 2 6 b 4 b - 8 e 4 b - 4 0 0 c - 8 0 7 f - 5 8 2 d a 8 c 7 f 2 5 c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 1 9 6 e e 9 3 6 - 3 d e f - 4 6 3 d - 8 3 0 6 - 7 4 6 6 7 c 2 6 2 4 8 5  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l O r t h o g o n a l A n a l y s i s  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 4 e 9 7 1 1 a d - 1 5 0 d - 4 7 8 9 - b 7 d 1 - 2 e 6 4 9 9 0 5 8 4 1 9  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d B o t t o m  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 0 2 ,   1 3 8  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 0 2 ,   1 3 8  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : H o r i z o n t a l S p l i t  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : d 6 b d 1 a 9 9 - 1 6 8 8 - 4 2 d 8 - 8 a c 6 - 1 7 3 a 1 5 0 9 e 2 d c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 9 0 2 ,   1 3 8  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 4 e 9 7 1 1 a d - 1 5 0 d - 4 7 8 9 - b 7 d 1 - 2 e 6 4 9 9 0 5 8 4 1 9  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l E r r o r L i s t  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 9 9 1 c 5 5 7 3 - 1 5 a 9 - 4 6 9 e - b 0 8 a - d f 0 3 6 7 f f 4 b 6 c  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 5 a 8 9 2 9 a 0 - 3 2 3 f - 4 7 c 7 - b 7 0 d - 1 3 1 b 6 a e c 0 1 4 c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 9 9 1 c 5 5 7 3 - 1 5 a 9 - 4 6 9 e - b 0 8 a - d f 0 3 6 7 f f 4 b 6 c  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 0 7 c b b a 3 - c e 4 d - 4 4 8 3 - 9 8 0 f - 6 6 c 5 e 5 7 1 4 d 4 d  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : e e f 1 8 7 2 2 - 3 3 f b - 4 4 a e - b e c 6 - 2 5 7 e f 6 7 3 4 e b f  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 5 0 7 c b b a 3 - c e 4 d - 4 4 8 3 - 9 8 0 f - 6 6 c 5 e 5 7 1 4 d 4 d  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e L i s t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 2 4 9 9 2 9 5 0 - 2 1 0 c - 4 6 f 3 - 8 2 c 9 - 2 4 e b 5 a 4 e 4 c b 9  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 2 c 7 1 4 e d - 9 7 d 5 - 4 e 8 e - b 8 e 7 - 0 4 6 d 3 7 e a d 1 4 c  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 2 4 9 9 2 9 5 0 - 2 1 0 c - 4 6 f 3 - 8 2 c 9 - 2 4 e b 5 a 4 e 4 c b 9  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : M a c r o P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : b 2 b 0 7 1 e 8 - a f 3 e - 4 f 5 6 - 8 3 0 7 - 5 e c d 1 a 3 6 6 8 5 4  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 3 6 f 5 a c 5 - 7 a c a - 4 e 9 3 - a b 2 1 - f 0 7 2 c 1 1 b 5 b 0 8  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : b 2 b 0 7 1 e 8 - a f 3 e - 4 f 5 6 - 8 3 0 7 - 5 e c d 1 a 3 6 6 8 5 4  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : T e x t P a n e l  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 5 9 c e d 4 4 - 3 0 2 5 - 4 0 f e - b a b 1 - 3 4 6 7 7 4 6 7 a 5 7 8  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 2 5 6 ,   2 5 6  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 1 2 4 8 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 2 5 b 6 b 8 6 d - 7 6 2 c - 4 9 0 4 - a 4 3 7 - 8 4 a f 6 f 4 4 5 5 a 5  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 5 5 9 c e d 4 4 - 3 0 2 5 - 4 0 f e - b a b 1 - 3 4 6 7 7 4 6 7 a 5 7 8  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l D e b u g M a n a g e r  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 5 4 f 3 f 4 5 f - 5 f a 8 - 4 d 5 2 - b 4 d c - a e b b 3 9 0 0 f 0 0 0  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   6 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : a 5 0 e 8 2 a 5 - e 6 1 4 - 4 f f 8 - 8 4 1 0 - 2 e 9 6 8 1 b c b c f d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 5 4 f 3 f 4 5 f - 5 f a 8 - 4 d 5 2 - b 4 d c - a e b b 3 9 0 0 f 0 0 0  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l V i r t u a l B o a r d  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 7 e 2 0 a 7 b c - b c 2 8 - 4 4 f f - 9 f 0 0 - 0 8 3 e 1 4 f 0 e c 8 b  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b 0 f 4 a a a 8 - 6 1 d 4 - 4 4 7 9 - a 8 d d - 1 3 c 5 8 1 2 2 6 e 9 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 7 e 2 0 a 7 b c - b c 2 8 - 4 4 f f - 9 f 0 0 - 0 8 3 e 1 4 f 0 e c 8 b  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e P i n L i s t F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 7 c e 8 1 d b d - 9 5 a 8 - 4 9 c d - 9 8 d f - c a b a 9 1 9 b b 4 a 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : b 8 9 c 7 7 a d - 9 0 8 2 - 4 c e 0 - 9 2 f 4 - c f 4 5 2 6 b b 5 d 6 a  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 7 c e 8 1 d b d - 9 5 a 8 - 4 9 c d - 9 8 d f - c a b a 9 1 9 b b 4 a 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : D e v i c e T o p V i e w F o r m  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 3 5 7 4 2 d 7 0 - 0 8 c a - 4 4 1 a - 9 2 5 6 - 2 2 9 9 6 0 4 0 b 3 1 9  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 3 9 f c 1 0 9 f - a 9 4 4 - 4 7 e c - 9 6 2 c - 2 8 e d 7 f a 5 0 6 1 b  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : 3 5 7 4 2 d 7 0 - 0 8 c a - 4 4 1 a - 9 2 5 6 - 2 2 9 9 6 0 4 0 b 3 1 9  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : f 5 e f 0 c 5 4 - 3 a a 6 - 4 e 0 8 - a 9 3 6 - 5 b 6 b 8 0 d a 8 d 9 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : D o c k e d R i g h t  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 9 5 ,   6 7 9  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : - 1 ,   - 1  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : e e d 8 9 0 2 4 - 0 f 8 3 - 4 2 f 3 - b e a b - 6 b 4 b c c 1 4 b 7 5 9  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d : f 5 e f 0 c 5 4 - 3 a a 6 - 4 e 0 8 - a 9 3 6 - 5 b 6 b 8 0 d a 8 d 9 3  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : T r u e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C o d e P a r t P r e v i e w  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : c 6 6 f 4 2 d 9 - 9 0 4 3 - 4 a 5 6 - 9 b d 4 - 4 4 c e 1 e 0 d 2 e a 7  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 6 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 9 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 7 b b f 4 8 f 6 - b 9 9 5 - 4 4 e 6 - 9 f b 2 - 0 2 6 c a 3 b 2 b e b d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : c 6 6 f 4 2 d 9 - 9 0 4 3 - 4 a 5 6 - 9 b d 4 - 4 4 c e 1 e 0 d 2 e a 7  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l P s e u d o E r r o r D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 3 5 b 4 a d 7 b - b 4 f b - 4 a b d - 9 3 7 1 - 9 1 9 7 a c b e 1 d 3 7  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 5 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 1 0 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 0 2 a 3 4 5 b 3 - c 5 1 5 - 4 e 6 8 - 8 b 7 2 - d 5 8 2 7 8 a 9 4 a 0 9  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 3 5 b 4 a d 7 b - b 4 f b - 4 a b d - 9 3 7 1 - 9 1 9 7 a c b e 1 d 3 7  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l C A N R e c e i v e D e b u g  
 - - D o c k A r e a P a n e - -  
 D o c k A r e a P a n e . I n t e r n a l I d : 0 e e a a 1 4 5 - c 0 3 0 - 4 5 7 6 - 9 1 3 4 - 6 5 8 7 2 a b 6 2 d 5 3  
 D o c k A r e a P a n e . D o c k e d L o c a t i o n : F l o a t i n g  
 D o c k A r e a P a n e . C l o s e d : F a l s e  
 D o c k A r e a P a n e . S i z e : 8 0 0 ,   5 0 0  
 D o c k A r e a P a n e . F l o a t i n g L o c a t i o n : 7 0 4 ,   3 2  
 D o c k A r e a P a n e . C h i l d P a n e S t y l e : T a b G r o u p  
 D o c k A r e a P a n e . P a n e s . C o u n t : 1  
 D o c k A r e a P a n e . S e l e c t e d T a b I n d e x : 0  
 - - D o c k a b l e P a n e B a s e - -  
   D o c k a b l e P a n e B a s e . I n t e r n a l I d : 9 7 7 0 9 2 9 6 - 9 4 e c - 4 0 2 1 - 8 1 9 e - e 1 a 4 9 5 1 8 2 0 d d  
   D o c k a b l e P a n e B a s e . C l o s e d : T r u e  
   D o c k a b l e P a n e B a s e . S i z e : 1 0 0 ,   1 0 0  
   D o c k a b l e P a n e B a s e . P a r e n t D o c k e d . I n t e r n a l I d :  
   D o c k a b l e P a n e B a s e . P a r e n t F l o a t i n g . I n t e r n a l I d : 0 e e a a 1 4 5 - c 0 3 0 - 4 5 7 6 - 9 1 3 4 - 6 5 8 7 2 a b 6 2 d 5 3  
   D o c k a b l e P a n e B a s e . T y p e : D o c k a b l e C o n t r o l P a n e  
   D o c k a b l e C o n t r o l P a n e . I s M d i C h i l d : F a l s e  
   D o c k a b l e C o n t r o l P a n e . F l y o u t S i z e : - 1 ,   - 1  
   D o c k a b l e C o n t r o l P a n e . P i n n e d : T r u e  
   D o c k a b l e C o n t r o l P a n e . C o n t r o l . N a m e : P a n e l M e s C u r C o n s u m p t i o n  
  + < S O A P - E N V : E n v e l o p e   x m l n s : x s i = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a - i n s t a n c e "   x m l n s : x s d = " h t t p : / / w w w . w 3 . o r g / 2 0 0 1 / X M L S c h e m a "   x m l n s : S O A P - E N C = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / "   x m l n s : S O A P - E N V = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n v e l o p e / "   x m l n s : c l r = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / s o a p / e n c o d i n g / c l r / 1 . 0 "   S O A P - E N V : e n c o d i n g S t y l e = " h t t p : / / s c h e m a s . x m l s o a p . o r g / s o a p / e n c o d i n g / " >  
 < S O A P - E N V : B o d y >  
 < a 1 : O b j e c t S t r e a m e r   i d = " r e f - 1 "   x m l n s : a 1 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i " >  
 < O b j e c t S t r e a m e r A s s e m b l y N a m e   i d = " r e f - 5 " > I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i < / O b j e c t S t r e a m e r A s s e m b l y N a m e >  
 < T a b S e t t i n g s   h r e f = " # r e f - 6 " / >  
 < H i d d e n T a b s   h r e f = " # r e f - 7 " / >  
 < T a b G r o u p s   h r e f = " # r e f - 8 " / >  
 < M a x T a b G r o u p s > 4 < / M a x T a b G r o u p s >  
 < A c t i v e T a b G r o u p I n d e x > 0 < / A c t i v e T a b G r o u p I n d e x >  
 < S p l i t t e r A p p e a r a n c e   h r e f = " # r e f - 9 " / >  
 < S p l i t t e r B o r d e r S t y l e > 6 < / S p l i t t e r B o r d e r S t y l e >  
 < V i e w S t y l e > 4 < / V i e w S t y l e >  
 < T a b G r o u p S e t t i n g s   h r e f = " # r e f - 1 0 " / >  
 < / a 1 : O b j e c t S t r e a m e r >  
 < a 2 : M d i T a b S e t t i n g s   i d = " r e f - 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < A c t i v e T a b A p p e a r a n c e   h r e f = " # r e f - 1 1 " / >  
 < D i s p l a y F o r m I c o n > 1 < / D i s p l a y F o r m I c o n >  
 < H o t T r a c k > 1 < / H o t T r a c k >  
 < S e l e c t e d T a b A p p e a r a n c e   h r e f = " # r e f - 1 2 " / >  
 < T a b A p p e a r a n c e   h r e f = " # r e f - 1 3 " / >  
 < / a 2 : M d i T a b S e t t i n g s >  
 < a 2 : H i d d e n M d i T a b s C o l l e c t i o n   i d = " r e f - 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 7 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 1 4 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 1 5 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 1 6 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 1 7 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 1 8 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 1 9 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 2 0 " / >  
 < _ x 0 0 3 7 _   h r e f = " # r e f - 2 1 " / >  
 < _ x 0 0 3 8 _   h r e f = " # r e f - 2 2 " / >  
 < _ x 0 0 3 9 _   h r e f = " # r e f - 2 3 " / >  
 < _ x 0 0 3 1 _ 0   h r e f = " # r e f - 2 4 " / >  
 < _ x 0 0 3 1 _ 1   h r e f = " # r e f - 2 5 " / >  
 < _ x 0 0 3 1 _ 2   h r e f = " # r e f - 2 6 " / >  
 < _ x 0 0 3 1 _ 3   h r e f = " # r e f - 2 7 " / >  
 < _ x 0 0 3 1 _ 4   h r e f = " # r e f - 2 8 " / >  
 < _ x 0 0 3 1 _ 5   h r e f = " # r e f - 2 9 " / >  
 < _ x 0 0 3 1 _ 6   h r e f = " # r e f - 3 0 " / >  
 < / a 2 : H i d d e n M d i T a b s C o l l e c t i o n >  
 < a 2 : M d i T a b G r o u p s C o l l e c t i o n   i d = " r e f - 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 1 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 3 1 " / >  
 < / a 2 : M d i T a b G r o u p s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 9 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 2 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b G r o u p S e t t i n g s   i d = " r e f - 1 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C l o s e B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 3 " / >  
 < T a b L i s t B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 4 " / >  
 < S c r o l l B u t t o n A p p e a r a n c e   h r e f = " # r e f - 3 5 " / >  
 < T a b A r e a A p p e a r a n c e   h r e f = " # r e f - 3 6 " / >  
 < S h o w T a b L i s t B u t t o n > 1 < / S h o w T a b L i s t B u t t o n >  
 < T a b B u t t o n S t y l e > 1 6 < / T a b B u t t o n S t y l e >  
 < S c r o l l A r r o w S t y l e > 2 < / S c r o l l A r r o w S t y l e >  
 < S c r o l l B u t t o n s > 3 < / S c r o l l B u t t o n s >  
 < T a b S t y l e > 2 < / T a b S t y l e >  
 < T a b A r e a M a r g i n s   h r e f = " # r e f - 3 7 " / >  
 < C l o s e B u t t o n L o c a t i o n > 2 < / C l o s e B u t t o n L o c a t i o n >  
 < / a 2 : M d i T a b G r o u p S e t t i n g s >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 1 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 8 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 3 9 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 1 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 0 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 2 : M d i T a b   i d = " r e f - 1 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 9 9 0 6 7 3 0 0 2 < / _ a >  
 < _ b > - 3 1 7 4 8 < / _ b >  
 < _ c > 1 9 3 8 5 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 4 2 < / _ e >  
 < _ f > 2 4 9 < / _ f >  
 < _ g > 1 8 5 < / _ g >  
 < _ h > 1 4 2 < / _ h >  
 < _ i > 2 0 < / _ i >  
 < _ j > 7 < / _ j >  
 < _ k > 1 8 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 2 8 5 5 4 0 5 5 < / _ a >  
 < _ b > 2 6 5 4 5 < / _ b >  
 < _ c > 1 8 7 1 7 < / _ c >  
 < _ d > 1 8 6 < / _ d >  
 < _ e > 1 5 8 < / _ e >  
 < _ f > 1 1 7 < / _ f >  
 < _ g > 7 4 < / _ g >  
 < _ h > 1 5 6 < / _ h >  
 < _ i > 2 2 3 < / _ i >  
 < _ j > 7 8 < / _ j >  
 < _ k > 7 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 2 1 4 5 7 3 8 2 0 3 < / _ a >  
 < _ b > 2 0 2 0 9 < / _ b >  
 < _ c > 1 9 6 9 7 < / _ c >  
 < _ d > 1 5 8 < / _ d >  
 < _ e > 1 2 0 < / _ e >  
 < _ f > 1 4 2 < / _ f >  
 < _ g > 2 0 7 < / _ g >  
 < _ h > 1 6 5 < / _ h >  
 < _ i > 1 4 < / _ i >  
 < _ j > 2 3 4 < / _ j >  
 < _ k > 1 2 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 8 7 1 4 4 3 1 9 0 < / _ a >  
 < _ b > 2 7 4 7 7 < / _ b >  
 < _ c > 1 6 9 7 8 < / _ c >  
 < _ d > 1 3 7 < / _ d >  
 < _ e > 1 8 1 < / _ e >  
 < _ f > 1 9 2 < / _ f >  
 < _ g > 1 0 7 < / _ g >  
 < _ h > 1 9 6 < / _ h >  
 < _ i > 7 4 < / _ i >  
 < _ j > 2 4 8 < / _ j >  
 < _ k > 1 1 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 9 7 3 9 2 0 6 2 8 < / _ a >  
 < _ b > 5 8 9 < / _ b >  
 < _ c > 1 7 4 2 5 < / _ c >  
 < _ d > 1 3 1 < / _ d >  
 < _ e > 1 8 9 < / _ e >  
 < _ f > 1 0 1 < / _ f >  
 < _ g > 9 3 < / _ g >  
 < _ h > 2 3 1 < / _ h >  
 < _ i > 5 7 < / _ i >  
 < _ j > 2 4 1 < / _ j >  
 < _ k > 7 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 1 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 5 1 8 9 3 8 5 2 8 < / _ a >  
 < _ b > 1 2 8 6 3 < / _ b >  
 < _ c > 1 8 3 7 5 < / _ c >  
 < _ d > 1 8 3 < / _ d >  
 < _ e > 1 3 < / _ e >  
 < _ f > 1 9 < / _ f >  
 < _ g > 2 7 < / _ g >  
 < _ h > 1 0 6 < / _ h >  
 < _ i > 2 3 6 < / _ i >  
 < _ j > 1 < / _ j >  
 < _ k > 7 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 1 9 2 5 6 4 9 6 4 5 < / _ a >  
 < _ b > - 2 6 6 6 7 < / _ b >  
 < _ c > 2 0 1 1 0 < / _ c >  
 < _ d > 1 8 4 < / _ d >  
 < _ e > 2 3 1 < / _ e >  
 < _ f > 4 < / _ f >  
 < _ g > 1 0 9 < / _ g >  
 < _ h > 5 5 < / _ h >  
 < _ i > 2 3 4 < / _ i >  
 < _ j > 2 0 9 < / _ j >  
 < _ k > 7 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 8 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 5 7 6 2 9 3 8 1 < / _ a >  
 < _ b > 3 1 4 3 4 < / _ b >  
 < _ c > 2 0 1 1 5 < / _ c >  
 < _ d > 1 7 1 < / _ d >  
 < _ e > 3 3 < / _ e >  
 < _ f > 2 4 0 < / _ f >  
 < _ g > 1 1 4 < / _ g >  
 < _ h > 1 9 3 < / _ h >  
 < _ i > 2 7 < / _ i >  
 < _ j > 9 1 < / _ j >  
 < _ k > 8 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 3 2 6 1 4 2 8 0 8 < / _ a >  
 < _ b > 2 5 0 4 4 < / _ b >  
 < _ c > 1 7 5 2 9 < / _ c >  
 < _ d > 1 6 8 < / _ d >  
 < _ e > 2 2 1 < / _ e >  
 < _ f > 1 9 < / _ f >  
 < _ g > 1 9 7 < / _ g >  
 < _ h > 1 2 9 < / _ h >  
 < _ i > 3 4 < / _ i >  
 < _ j > 1 1 0 < / _ j >  
 < _ k > 1 5 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 4 7 0 2 3 4 8 7 5 < / _ a >  
 < _ b > 1 9 8 4 < / _ b >  
 < _ c > 1 9 8 8 7 < / _ c >  
 < _ d > 1 8 1 < / _ d >  
 < _ e > 1 5 4 < / _ e >  
 < _ f > 2 1 4 < / _ f >  
 < _ g > 1 7 0 < / _ g >  
 < _ h > 1 5 8 < / _ h >  
 < _ i > 6 7 < / _ i >  
 < _ j > 0 < / _ j >  
 < _ k > 2 2 3 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 6 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 8 7 7 9 7 2 1 2 < / _ a >  
 < _ b > 3 9 7 1 < / _ b >  
 < _ c > 1 7 1 3 9 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 7 1 < / _ e >  
 < _ f > 1 0 7 < / _ f >  
 < _ g > 7 5 < / _ g >  
 < _ h > 2 0 4 < / _ h >  
 < _ i > 2 0 < / _ i >  
 < _ j > 1 8 3 < / _ j >  
 < _ k > 8 9 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 5 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 5 8 4 5 9 6 2 2 2 < / _ a >  
 < _ b > 1 6 0 0 9 < / _ b >  
 < _ c > 1 9 8 9 6 < / _ c >  
 < _ d > 1 7 8 < / _ d >  
 < _ e > 6 9 < / _ e >  
 < _ f > 1 1 0 < / _ f >  
 < _ g > 1 8 3 < / _ g >  
 < _ h > 5 5 < / _ h >  
 < _ i > 2 1 8 < / _ i >  
 < _ j > 2 0 4 < / _ j >  
 < _ k > 2 2 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 6 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 7 7 6 1 0 4 7 7 9 < / _ a >  
 < _ b > - 2 9 1 0 9 < / _ b >  
 < _ c > 1 6 3 9 6 < / _ c >  
 < _ d > 1 2 8 < / _ d >  
 < _ e > 1 2 7 < / _ e >  
 < _ f > 8 8 < / _ f >  
 < _ g > 4 5 < / _ g >  
 < _ h > 1 6 8 < / _ h >  
 < _ i > 1 9 9 < / _ i >  
 < _ j > 2 4 2 < / _ j >  
 < _ k > 9 2 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 7 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 6 8 6 0 3 5 0 < / _ a >  
 < _ b > 1 9 8 6 4 < / _ b >  
 < _ c > 1 8 1 4 1 < / _ c >  
 < _ d > 1 2 8 < / _ d >  
 < _ e > 1 7 8 < / _ e >  
 < _ f > 2 0 < / _ f >  
 < _ g > 1 0 8 < / _ g >  
 < _ h > 9 8 < / _ h >  
 < _ i > 2 3 8 < / _ i >  
 < _ j > 2 9 < / _ j >  
 < _ k > 1 5 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 5 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 8 6 1 6 1 1 1 8 < / _ a >  
 < _ b > 1 3 3 0 7 < / _ b >  
 < _ c > 1 7 5 8 2 < / _ c >  
 < _ d > 1 9 0 < / _ d >  
 < _ e > 1 9 8 < / _ e >  
 < _ f > 3 7 < / _ f >  
 < _ g > 1 2 6 < / _ g >  
 < _ h > 2 4 6 < / _ h >  
 < _ i > 1 1 5 < / _ i >  
 < _ j > 7 8 < / _ j >  
 < _ k > 1 9 1 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 7 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 2 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 1 9 7 7 0 5 2 9 9 < / _ a >  
 < _ b > - 2 8 5 4 2 < / _ b >  
 < _ c > 1 9 6 8 0 < / _ c >  
 < _ d > 1 4 6 < / _ d >  
 < _ e > 2 4 4 < / _ e >  
 < _ f > 2 0 7 < / _ f >  
 < _ g > 6 9 < / _ g >  
 < _ h > 3 8 < / _ h >  
 < _ i > 1 8 7 < / _ i >  
 < _ j > 9 3 < / _ j >  
 < _ k > 1 0 6 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 3 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > 9 7 2 8 2 0 6 3 9 < / _ a >  
 < _ b > - 2 2 2 0 4 < / _ b >  
 < _ c > 1 8 4 1 2 < / _ c >  
 < _ d > 1 5 0 < / _ d >  
 < _ e > 4 4 < / _ e >  
 < _ f > 4 0 < / _ f >  
 < _ g > 2 3 7 < / _ g >  
 < _ h > 1 2 7 < / _ h >  
 < _ i > 1 6 5 < / _ i >  
 < _ j > 6 < / _ j >  
 < _ k > 2 7 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 2 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b G r o u p   i d = " r e f - 3 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < T a b s   h r e f = " # r e f - 4 2 " / >  
 < E x t e n t > 6 7 7 < / E x t e n t >  
 < F i r s t D i s p l a y T a b I n d e x > 0 < / F i r s t D i s p l a y T a b I n d e x >  
 < S e l e c t e d T a b I n d e x > 2 < / S e l e c t e d T a b I n d e x >  
 < / a 2 : M d i T a b G r o u p >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 2 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 5 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 0 < / v a l u e >  
 < k n o w n C o l o r > 6 < / k n o w n C o l o r >  
 < s t a t e > 1 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 3 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 4 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 5 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 6 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : A p p e a r a n c e H o l d e r   i d = " r e f - 3 6 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < A p p e a r a n c e   h r e f = " # r e f - 4 7 " / >  
 < / a 3 : A p p e a r a n c e H o l d e r >  
 < a 3 : M a r g i n s   i d = " r e f - 3 7 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < L e f t D e f a u l t > 0 < / L e f t D e f a u l t >  
 < T o p D e f a u l t > 0 < / T o p D e f a u l t >  
 < R i g h t D e f a u l t > 0 < / R i g h t D e f a u l t >  
 < B o t t o m D e f a u l t > 0 < / B o t t o m D e f a u l t >  
 < B o t t o m > 4 < / B o t t o m >  
 < / a 3 : M a r g i n s >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 8 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 8 2 0 8 9 7 0 9 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k C o l o r 2   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 8 1 4 2 8 6 7 7 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r 2 >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 3 9 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 0 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < B a c k G r a d i e n t S t y l e > 1 < / B a c k G r a d i e n t S t y l e >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b s C o l l e c t i o n   i d = " r e f - 4 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < C o u n t > 7 < / C o u n t >  
 < _ x 0 0 3 0 _   h r e f = " # r e f - 4 8 " / >  
 < _ x 0 0 3 1 _   h r e f = " # r e f - 4 9 " / >  
 < _ x 0 0 3 2 _   h r e f = " # r e f - 5 0 " / >  
 < _ x 0 0 3 3 _   h r e f = " # r e f - 5 1 " / >  
 < _ x 0 0 3 4 _   h r e f = " # r e f - 5 2 " / >  
 < _ x 0 0 3 5 _   h r e f = " # r e f - 5 3 " / >  
 < _ x 0 0 3 6 _   h r e f = " # r e f - 5 4 " / >  
 < / a 2 : M d i T a b s C o l l e c t i o n >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 4 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 5 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 6 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < T h e m e d E l e m e n t A l p h a > 3 < / T h e m e d E l e m e n t A l p h a >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 3 : A p p e a r a n c e   i d = " r e f - 4 7 "   x m l n s : a 3 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n / I n f r a g i s t i c s 4 . W i n . v 1 2 . 2 " >  
 < B a c k C o l o r   x s i : t y p e = " a 6 : C o l o r "   x m l n s : a 6 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / S y s t e m . D r a w i n g / S y s t e m . D r a w i n g " >  
 < n a m e   x s i : n u l l = " 1 " / >  
 < v a l u e > 4 2 9 1 6 1 0 5 5 4 < / v a l u e >  
 < k n o w n C o l o r > 0 < / k n o w n C o l o r >  
 < s t a t e > 2 < / s t a t e >  
 < / B a c k C o l o r >  
 < I d > 0 < / I d >  
 < / a 3 : A p p e a r a n c e >  
 < a 2 : M d i T a b   i d = " r e f - 4 8 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 2 1 0 4 5 4 0 5 2 5 < / _ a >  
 < _ b > - 5 1 3 6 < / _ b >  
 < _ c > 1 6 9 6 3 < / _ c >  
 < _ d > 1 5 7 < / _ d >  
 < _ e > 0 < / _ e >  
 < _ f > 1 5 4 < / _ f >  
 < _ g > 1 8 < / _ g >  
 < _ h > 1 0 1 < / _ h >  
 < _ i > 1 9 4 < / _ i >  
 < _ j > 1 5 5 < / _ j >  
 < _ k > 1 5 5 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 9 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 4 9 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   x s i : t y p e = " a 5 : G u i d "   x m l n s : a 5 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s / S y s t e m " >  
 < _ a > - 1 7 5 1 2 9 9 8 0 4 < / _ a >  
 < _ b > - 2 3 1 2 8 < / _ b >  
 < _ c > 1 7 3 6 1 < / _ c >  
 < _ d > 1 8 8 < / _ d >  
 < _ e > 7 3 < / _ e >  
 < _ f > 1 0 3 < / _ f >  
 < _ g > 1 0 8 < / _ g >  
 < _ h > 1 9 9 < / _ h >  
 < _ i > 1 8 4 < / _ i >  
 < _ j > 1 9 8 < / _ j >  
 < _ k > 4 < / _ k >  
 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < M d i C h i l d I n d e x > 1 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 0 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 5 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 d a c d f 7 2 - 2 6 6 a - 4 c 4 c - 8 7 2 1 - c a 2 3 d 4 3 e 5 6 8 6 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 6 " > F : \ F C B _ p r o j e c t \ t e m p \ b c z t _ n e w \ C O D E \ B C Z T \ u s e r \ a p p T a s k . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 0 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 1 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 7 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 6 3 6 5 d b a - 6 a 2 1 - 4 e a e - a 0 1 2 - 2 e 5 d 1 c 6 7 c 7 6 3 < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 5 8 " > F : \ F C B _ p r o j e c t \ t e m p \ b c z t _ n e w \ C O D E \ B C Z T \ R L I N _ d r i v e r \ R L I N _ d r i v e r . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 1 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 2 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 5 9 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 3 2 5 d 9 8 2 d - 8 2 a 5 - 4 4 d a - 8 6 b 2 - 2 b 4 e 2 1 0 e c d 1 c < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 0 " > F : \ F C B _ p r o j e c t \ t e m p \ b c z t _ n e w \ C O D E \ B C Z T \ r _ m a i n . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 2 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 3 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 1 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 5 c 8 5 9 7 2 4 - a f e c - 4 b 8 9 - b 3 f e - e 7 d b 1 5 0 f 0 a 6 c < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 2 " > F : \ F C B _ p r o j e c t \ t e m p \ b c z t _ n e w \ C O D E \ B C Z T \ u s e r \ h w C t r l . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 3 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < a 2 : M d i T a b   i d = " r e f - 5 4 "   x m l n s : a 2 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . W i n . U l t r a W i n T a b b e d M d i / I n f r a g i s t i c s 4 . W i n . U l t r a W i n T a b b e d M d i . v 1 2 . 2 " >  
 < P e r s i s t e d I n f o   x s i : t y p e = " a 4 : O b j e c t W r a p p e r "   x m l n s : a 4 = " h t t p : / / s c h e m a s . m i c r o s o f t . c o m / c l r / n s a s s e m / I n f r a g i s t i c s . S h a r e d . S e r i a l i z a t i o n / I n f r a g i s t i c s 4 . S h a r e d . v 1 2 . 2 " >  
 < o b j e c t V a l u e   i d = " r e f - 6 3 "   x s i : t y p e = " S O A P - E N C : s t r i n g " > 2 5 f e 6 3 a a - 7 6 9 e - 4 4 0 a - b 2 0 a - 2 f 7 0 d 4 8 a c 3 e f < / o b j e c t V a l u e >  
 < / P e r s i s t e d I n f o >  
 < T o o l T i p   i d = " r e f - 6 4 " > F : \ F C B _ p r o j e c t \ t e m p \ b c z t _ n e w \ C O D E \ B C Z T \ r _ c g _ c g c . c < / T o o l T i p >  
 < M d i C h i l d I n d e x > 4 < / M d i C h i l d I n d e x >  
 < / a 2 : M d i T a b >  
 < / S O A P - E N V : B o d y >  
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+ + + + + COM1 + 0 + enable + enable + + + + + False + False + True + + + + + False + False + True + + + + + False + False + True + + + + + False + False + True + + + + + PanelWatch1 + 150 + 100 + 150 + 100 + 150 + None + + + PanelWatch2 + 150 + 100 + 150 + 100 + 150 + None + + + PanelWatch3 + 150 + 100 + 150 + 100 + 150 + None + + + PanelWatch4 + 150 + 100 + 150 + 100 + 150 + None + + + + + PanelIORegister + 150 + 100 + 150 + 100 + 150 + + + + + PanelCpuRegister + 0 + 0 + 0 + 0 + 0 + + + + + PanelLocalVariable + 150 + 100 + 150 + 100 + 150 + False + Decimal + Decimal + 20127 + + + + + PanelCallStack + Auto + Decimal + 20127 + True + True + 50 + 500 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Run-Break Timer + Nanosecond + + + + + PanelTrace + False + False + Decimal + Mixed + + + + + PanelMemory1 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + PanelMemory2 + Hexadecimal + Ascii + View8bitWidth + None + False + True + + 16 + 0 + + + PanelMemory3 + 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<SAU1 /> + <IICA0 /> + <TAU0 /> + <TAU1 /> + <TMRJ0 /> + </Effect> + </fCLK> + <ISPullupForPort Name="ISPullupForPort" Text="P00-P10-P11-P12-P13-P14-P15-P16-P17-P30-P31-P32-P40-P41-P60-P61-P62-P63-P70-P71-P72-P73-P120-P125-P140-" Comment="unused" /> + <fHOCO Name="fHOCO" Value="64" Comment="64M" Trigger="fHOCO" /> + <fIH Name="fIH" Value="64" Comment="32M" /> + <fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"> + <Effect> + <TAU0 /> + <TAU1 /> + <TMRJ0 /> + </Effect> + </fSUB> + <fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"> + <Effect> + <TMRJ0 /> + <WDT /> + <TAU0 /> + <TAU1 /> + </Effect> + </fIL> + <fSL Name="fSL" Value="15" Comment="15K" Trigger="fSL"> + <Effect> + <PCLBUZ0 /> + <TMRJ0 /> + <TAU0 /> + <TAU1 /> + </Effect> + </fSL> + <fPLL Name="fPLL" Value="24" Comment="24M" Trigger="fPLL" /> + <fRTC Name="fRTC" Value="524.590163934426" Comment="15k" Trigger="fRTC"> + <Effect> + <RTC /> + </Effect> + </fRTC> + <fTRD Name="fTRD" Value="64" Comment="64M" Trigger="fTRD"> + <Effect> + <TMRD0 /> + <TMRD1 /> + </Effect> + </fTRD> + <fMAIN Name="fMAIN" Value="64" Comment="32M" Trigger="fMAIN"> + <Effect> + <PCLBUZ0 /> + </Effect> + </fMAIN> + <fTRDSource Name="fTRDSource" Trigger="fTRD" Text="fIH" /> + <VDD_MIN Name="VDD_MIN" Value="4" Comment="4.0V" Trigger="VDD"> + <Effect> + <PCLBUZ0 /> + <IICA0 /> + <SAU0 /> + <SAU1 /> + </Effect> + </VDD_MIN> + <VDD_MAX Name="VDD_MAX" Value="5.5" Comment="5.5V" /> + <VDD Name="VDD" Text="false" Comment="used" /> + <VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"> + <Effect> + <ADC /> + </Effect> + </VDDValue> + <AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="ANI0,ANI1,ANI2,ANI3," /> + <AD_ADS_USEDPIN Name="AD_ADS_USEDPIN" Text="ANI0," /> + <ADPCForPort3 Name="ADPCForPort3" Value="255" Comment="ADPCForPort3" /> + <ADPCForPort8 Name="ADPCForPort8" Value="5" Comment="ADPCForPort8" /> + <ADPCForPort9 Name="ADPCForPort9" Value="12" Comment="ADPCForPort9" /> + <ADPCForKey Name="ADPCForKey" Value="255" Comment="ADPCForKey" /> + <OnChipDebugTraceDTC Name="GTraceRam" Text="0" Trigger="ocdtraceram"> + <Effect> + <DTC /> + </Effect> + </OnChipDebugTraceDTC> + <OnChipDebugTrace Name="GTrace" Text="1" /> + <OnChipDebugHotPlugDTC Name="GHotPlugRam" Text="0" Trigger="ocdhotplugram"> + <Effect> + <DTC /> + </Effect> + </OnChipDebugHotPlugDTC> + <KR0 Name="KR0" Text="false" Comment="unused" Trigger="KR0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR0> + <KR1 Name="KR1" Text="false" Comment="unused" Trigger="KR1"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR1> + <KR2 Name="KR2" Text="false" Comment="unused" Trigger="KR2"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR2> + <KR3 Name="KR3" Text="false" Comment="unused" Trigger="KR3"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR3> + <KR4 Name="KR4" Text="false" Comment="unused" Trigger="KR4"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR4> + <KR5 Name="KR5" Text="false" Comment="unused" Trigger="KR5"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR5> + <KR6 Name="KR6" Text="false" Comment="unused" Trigger="KR6"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR6> + <KR7 Name="KR7" Text="false" Comment="unused" Trigger="KR7"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR7> + <OnChipDebugHotPlug Name="GHotPlug" Text="1" /> + <IIC00 Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC00> + <IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC01> + <IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC10> + <IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC11> + <IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IICA0> + <PIOR00Value Name="PIOR00Value" Text="0" /> + <PIOR01Value Name="PIOR01Value" Text="0" /> + <PIOR02Value Name="PIOR02Value" Text="0" /> + <PIOR03Value Name="PIOR03Value" Text="0" /> + <PIOR04Value Name="PIOR04Value" Text="0" /> + <PIOR05Value Name="PIOR05Value" Text="0" /> + <PIOR06Value Name="PIOR06Value" Text="0" /> + <PIOR07Value Name="PIOR07Value" Text="0" /> + <PIOR10Value Name="PIOR10Value" Text="0" /> + <PIOR11Value Name="PIOR11Value" Text="0" /> + <PIOR12Value Name="PIOR12Value" Text="0" /> + <PIOR13Value Name="PIOR13Value" Text="0" /> + <PIOR14Value Name="PIOR14Value" Text="0" /> + <PIOR15Value Name="PIOR15Value" Text="1" /> + <PIOR16Value Name="PIOR16Value" Text="0" /> + <PIOR17Value Name="PIOR17Value" Text="0" /> + <PIOR20Value Name="PIOR20Value" Text="0" /> + <PIOR21Value Name="PIOR21Value" Text="0" /> + <PIOR22Value Name="PIOR22Value" Text="0" /> + <PIOR23Value Name="PIOR23Value" Text="0" /> + <PIOR24Value Name="PIOR24Value" Text="0" /> + <PIOR25Value Name="PIOR25Value" Text="0" /> + <PIOR26Value Name="PIOR26Value" Text="0" /> + <PIOR27Value Name="PIOR27Value" Text="0" /> + <PIOR30Value Name="PIOR30Value" Text="0" /> + <PIOR31Value Name="PIOR31Value" Text="0" /> + <PIOR32Value Name="PIOR32Value" Text="0" /> + <PIOR33Value Name="PIOR33Value" Text="0" /> + <PIOR34Value Name="PIOR34Value" Text="0" /> + <PIOR35Value Name="PIOR35Value" Text="0" /> + <PIOR36Value Name="PIOR36Value" Text="0" /> + <PIOR37Value Name="PIOR37Value" Text="0" /> + <PIOR40Value Name="PIOR40Value" Text="0" /> + <PIOR41Value Name="PIOR41Value" Text="0" /> + <PIOR42Value Name="PIOR42Value" Text="0" /> + <PIOR43Value Name="PIOR43Value" Text="0" /> + <PIOR44Value Name="PIOR44Value" Text="0" /> + <PIOR45Value Name="PIOR45Value" Text="0" /> + <PIOR46Value Name="PIOR46Value" Text="0" /> + <PIOR50Value Name="PIOR50Value" Text="0" /> + <PIOR52Value Name="PIOR52Value" Text="0" /> + <PIOR53Value Name="PIOR53Value" Text="0" /> + <PIOR60Value Name="PIOR60Value" Text="0" /> + <PIOR61Value Name="PIOR61Value" Text="0" /> + <PIOR62Value Name="PIOR62Value" Text="0" /> + <PIOR63Value Name="PIOR63Value" Text="0" /> + <PIOR64Value Name="PIOR64Value" Text="0" /> + <PIOR65Value Name="PIOR65Value" Text="0" /> + <PIOR66Value Name="PIOR66Value" Text="0" /> + <PIOR67Value Name="PIOR67Value" Text="0" /> + <PIOR70Value Name="PIOR70Value" Text="0" /> + <PIOR71Value Name="PIOR71Value" Text="0" /> + <PIOR73Value Name="PIOR73Value" Text="0" /> + <RTC1HZ Name="RTC1HZ" Text="disable" Trigger="RTC1HZ"> + <Effect> + <TAU0 /> + <TAU1 /> + </Effect> + </RTC1HZ> + <RXD0 Name="RXD0" Text="disable" /> + <ProjectName Name="PrjName" Text="BCZT" /> + <ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\M26\BCZT" /> + <ProjectKind Name="PrjKind" Text="Project78K0R" /> + <DeviceName Name="DeviceName" Fixed="" Text="RL78F13" /> + <MCUName Name="MCUName" Text="RL78F13_48pin" /> + <ChipName Name="ChipName" Text="R5F10AGF" /> + <ChipID Name="ChipID" Text="R5F10AGF" /> + <CPUCoreType Name="CPUCoreType" Fixed="" Text="1" /> + <MCUType Name="MCUType" Fixed="" Text="RL78" /> + <Compiler Name="Compiler" Text="CCRL" /> + <UseSecurityId Name="GI" Text="0" /> + <SecurityId Name="GIValue" Text="00000000000000000000" /> + <LinkDirectiveFile Name="D0" Text="lk.dr" /> + <OnChipDebugOptionBytes Name="GO" Text="1" /> + <OnChipDebugOptionBytesValue Name="GOValue" Text="04" /> + <StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="17E00" /> + <SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /> + <UserOptionBytes Name="GB" Text="1" /> + <UserOptionBytesValue Name="GBValue" Text="F933F8" /> + <RAMStartAddress Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="RAMStartAddress" Fixed="" Text="000FE700" /> + <RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /> + <ROMEndAddress Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="ROMEndAddress" Fixed="" Text="00017FFF" /> + <MirrorROM Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="MirrorROM" Fixed="" Text="47.75" /> + <TAUUsedRTC1Hz Name="TAUUsedRTC1Hz" Text="false" Comment="unused" Trigger="RTC1HZ"> + <Effect> + <RTC /> + </Effect> + </TAUUsedRTC1Hz> + <TRDCLKUSE1 Name="TRDCLKUSE1" Value="0" Comment="unused" Trigger="TRDCLK input"> + <Effect> + <TMRD0 /> + </Effect> + </TRDCLKUSE1> + <fMP Name="fMP" Value="64" /> + <GroupName Name="GroupName" Text="groupb" /> + <CodePath Name="CodePath" Text=".\" /> + <ReportType Name="ReportType" Text="Html" /> + <CreationDateType Name="CreationDateType" Text="OutputDate" /> + <GenerateType Name="GenerateType" Text="Merge" /> + <APIOutputType Name="APIOutputType" Text="Default" /> + <FileRegister Name="FileRegister" Text="Yes" /> + <PinReflect Name="PinReflect" Text="Reflected" /> + <fCLKSource Name="fCLKSource" Text="fIH" /> + <UseFDL Name="UseFDL" Text="no" /> + <DataFlash Name="DataFlash" Text="0" /> + <OCDROM Name="OCDROM" Text="Unused" /> + <OCDROM_Address Name="OCDROM_Address" Text="00017E00" /> + <OCDROM_Length Name="OCDROM_Length" Text="512" /> + <PrjVersion Name="PrjVersion" Text="1.2.0.1" /> + <ProductVersion Name="ProductVersion" Text="4.08.05.01" /> + <ADPCForPort0 Name="ADPCForPort0" Value="255" /> + <ADPCForPort1 Name="ADPCForPort1" Value="255" /> + <ADPCForPort4 Name="ADPCForPort4" Value="255" /> + <ADPCForPort6 Name="ADPCForPort6" Value="255" /> + <ADPCForPort7 Name="ADPCForPort7" Value="255" /> + <ADPCForPort12 Name="ADPCForPort12" Value="255" /> + <ADPCForPort13 Name="ADPCForPort13" Value="255" /> + <ADPCForPort14 Name="ADPCForPort14" Value="255" /> + <TRDCLKTag Name="TRDCLKTag" Value="-1" /> + <TRDCLKUSE0 Name="TRDCLKUSE0" Value="0" /> + <RTC1HZ_Used Name="RTC1HZ_Used" Value="0" /> + <TO02_PWM Name="TO02_PWM" Text="false" /> + <TO03_PWM Name="TO03_PWM" Text="false" /> + <Ch3UseTI03 Name="Ch3UseTI03" Text="false" /> + <Ch4UseTI03 Name="Ch4UseTI03" Text="false" /> + <Ch5UseTI03 Name="Ch5UseTI03" Text="false" /> + <INPT0USE0 Name="INPT0USE0" Text="false" /> + <TRDINTP0LINK0 Name="TRDINTP0LINK0" Text="false" /> + <TRDIOC1_PWM Name="TRDIOC1_PWM" Text="false" /> + <TRDIOD1_PWM Name="TRDIOD1_PWM" Text="false" /> + <INPT0USE1 Name="INPT0USE1" Text="false" /> + <TRDINTP0LINK1 Name="TRDINTP0LINK1" Text="false" /> + <LinkFileName Name="LinkFileName" Text="" /> + </VAR> + <DIR> + <PIN> + <CGC> + <X1 Port="P121" Point="-" /> + <X2 Port="P122" Point="-" /> + <EXCLK Port="P122" Point="I" /> + <XT1 Chip="RL78F13_48pin,RL78F13_64pin" Port="P123" Point="-" /> + <XT2 Chip="RL78F13_48pin,RL78F13_64pin" Port="P124" Point="-" /> + <EXCLKS Chip="RL78F13_48pin,RL78F13_64pin" Port="P124" Point="I" /> + <TOOL0 Port="P40" Point="I/O" /> + <RESOUT Port="P130" Point="O" /> + </CGC> + <PORT> + <Port0 Chip="RL78F13_48pin,RL78F13_64pin" Pullup="true"> + <P00 Name="P00/TI05/TO05/INTP9" AltFunc="TO05" Point="I/O" /> + </Port0> + <Port1 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Pullup="true"> + <P10 Name="P10/TI13/TO13/TRJO0/_SCK10/SCL10/LTXD1/CTXD0" Chip="groupb,groupc1,groupc2" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P11 Name="P11/TI12/TO12/TRDIOB0/SI10/SDA10/RXD1/LRXD1/CRXD0" Chip="groupb,groupc1,groupc2" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P12 Name="P12/TI11/TO11/TRDIOD0/INTP5/SO10/TXD1/SNZOUT3" Chip="groupb,groupc1,groupc2" Nch="true" AltFunc="" Point="I/O" /> + <P13 Name="P13/TI04/TO04/TRDIOA0/TRDCLK0/SI01/SDA01/LTXD0" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P14 Name="P14/TI06/TO06/TRDIOC0/_SCK01/SCL01/LRXD0" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P15 Name="P15/TI05/TO05/TRDIOA1/TRDIOA0/TRDCLK0/SO00/TXD0/TOOLTXD/RTC1HZ" Nch="true" AltFunc="" Point="I/O" /> + <P16 Name="P16/TI02/TO02/TRDIOC1/SI00/SDA00/RXD0/TOOLRXD" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P17 Name="P17/TI00/TO00/TRDIOB1/_SCK00/SCL00/INTP3" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + </Port1> + <Port3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P30 Name="P30/TI01/TO01/TRDIOD1/_SSI00/INTP2/SNZOUT0" TTL="true" PITHL="true" Pullup="true" AltFunc="P30" Point="I/O" /> + <P31 Name="P31/TI14/TO14/STOPST/INTP2" Pullup="true" AltFunc="" Point="I/O" /> + <P32 Name="P32/TI16/TO16/INTP7" Pullup="true" AltFunc="P32" Point="I/O" /> + <P33 Name="P33/AVREFP/ANI00" AltFunc="ANI0" Point="I/O" /> + <P34 Name="P34/AVREFM/ANI01" AltFunc="ANALOG_1" Point="I/O" /> + </Port3> + <Port4 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin" Pullup="true"> + <P40 Name="P40/TOOL0" AltFunc="" Point="I/O" /> + <P41 Name="P41/TI10/TO10/TRJIO0/VCOUT0/SNZOUT2" AltFunc="" Point="I/O" /> + </Port4> + <Port6 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin" Pullup="true"> + <P60 Name="P60/_SCK00/SCL00" PITHL="true" Nch="true" AltFunc="P60" Point="I/O" /> + <P61 Name="P61/SI00/SDA00/RXD0" PITHL="true" Nch="true" AltFunc="P61" Point="I/O" /> + <P62 Name="P62/SO00/TXD0/SCLA0" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" PITHL="true" Nch="true" TTL="true" AltFunc="P62" Point="I/O" /> + <P63 Name="P63/_SSI00/SDAA0" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" TTL="true" PITHL="true" Nch="true" AltFunc="P63" Point="I/O" /> + </Port6> + <Port7 Chip="RL78F13_48pin" Pullup="true"> + <P70 Name="P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" Nch="true" AltFunc="P70" Point="I/O" /> + <P71 Name="P71/ANI27/KR1/TI17/TO17/INTP6/_SCK11/SCL11/SNZOUT5" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" Nch="true" AltFunc="P71" Point="I/O" /> + <P72 Name="P72/ANI28/KR2/CTXD0/SO11/SNZOUT6" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" Nch="true" AltFunc="P72" Point="I/O" /> + <P73 Name="P73/ANI29/KR3/CRXD0/_SSI11/SNZOUT7" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" AltFunc="P73" Point="I/O" /> + </Port7> + <Port8 Chip="RL78F13_30pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P80 Name="P80/ANI02/ANO0" AltFunc="ANALOG_2" Point="I/O" /> + <P81 Name="P81/ANI03/IVCMP00" AltFunc="ANALOG_3" Point="I/O" /> + <P82 Name="P82/ANI04/IVCMP01" AltFunc="P82" Point="I/O" /> + <P83 Name="P83/ANI05/IVCMP02" AltFunc="P83" Point="I/O" /> + <P84 Name="P84/ANI06/IVCMP03" AltFunc="P84" Point="I/O" /> + <P85 Name="P85/ANI07/IVREF0" AltFunc="P85" Point="I/O" /> + <P86 Name="P86/ANI08" AltFunc="P86" Point="I/O" /> + <P87 Name="P87/ANI09" AltFunc="P87" Point="I/O" /> + </Port8> + <Port9 Chip="RL78F13_48pin"> + <P90 Name="P90/ANI10" AltFunc="" Point="I/O" /> + <P91 Name="P91/ANI11" AltFunc="P91" Point="I/O" /> + <P92 Name="P92/ANI12" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" AltFunc="P92" Point="I/O" /> + </Port9> + <Port12 Chip="RL78F13_48pin,RL78F13_64pin"> + <P120 Name="P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" DIN="true" Nch="true" Pullup="true" AltFunc="P120" Point="I/O" /> + <P121 Name="P121/X1" AltFunc="" Point="I" /> + <P122 Name="P122/X2/EXCLK" AltFunc="" Point="I" /> + <P123 Name="P123/XT1" AltFunc="" Point="I" /> + <P124 Name="P124/XT2/EXCLKS" AltFunc="" Point="I" /> + <P125 Name="P125/ANI24/TI03/TO03/TRDIOB0/_SSI01/INTP1/SNZOUT1" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" DIN="true" TTL="true" PITHL="true" Pullup="true" AltFunc="P125" Point="I/O" /> + </Port12> + <Port13 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P130 Name="P130/RESOUT" AltFunc="P130" Point="O" /> + <P137 Name="P137/INTP0" AltFunc="" Point="I" /> + </Port13> + <Port14 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Pullup="true"> + <P140 Name="P140/PCLBUZ0" AltFunc="P140" Point="I/O" /> + </Port14> + </PORT> + <INTC> + <INTP> + <INTP0 Port="P137" Point="I" /> + <INTP1 Port="P125" Point="I" /> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR52="0" Port="P30" Point="I" /> + <INTP3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" Port="P17" Point="I" /> + <INTP4 Port="P120" Point="I" /> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P12" Point="I" /> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P71" Point="I" /> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P32" Point="I" /> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" Port="P70" Point="I" /> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" Port="P00" Point="I" /> + </INTP> + <KEY> + <KR0 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P70" Point="I" /> + <KR1 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P71" Point="I" /> + <KR2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P72" Point="I" /> + <KR3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P73" Point="I" /> + </KEY> + </INTC> + <ADC> + <ANI0 Port="P33" Point="I" /> + <ANI1 Port="P34" Point="I" /> + <ANI2 Port="P80" Point="I" /> + <ANI3 Port="P81" Point="I" /> + <ANI4 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P82" Point="I" /> + <ANI5 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P83" Point="I" /> + <ANI6 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P84" Point="I" /> + <ANI7 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P85" Point="I" /> + <ANI8 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P86" Point="I" /> + <ANI9 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P87" Point="I" /> + <ANI10 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P90" Point="I" /> + <ANI11 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P91" Point="I" /> + <ANI12 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin" Port="P92" Point="I" /> + <ANI24 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin, R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG, R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG" Port="P125" Point="I" /> + <ANI25 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin, R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG, R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG" Port="P120" Point="I" /> + <AVREFP Port="P33" Point="I" /> + <AVREFM Port="P34" Point="I" /> + <ANALOG_0 Port="P33" Point="I" RealName="ANI0" /> + <ANALOG_1 Port="P34" Point="I" RealName="ANI1" /> + <ANALOG_2 Port="P80" Point="I" RealName="ANI2" /> + <ANALOG_3 Port="P81" Point="I" RealName="ANI3" /> + <ANALOG_4 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P82" Point="I" RealName="ANI4" /> + <ANALOG_5 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P83" Point="I" RealName="ANI5" /> + <ANALOG_6 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P84" Point="I" RealName="ANI6" /> + <ANALOG_7 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P85" Point="I" RealName="ANI7" /> + <ANALOG_8 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P86" Point="I" RealName="ANI8" /> + <ANALOG_9 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P87" Point="I" RealName="ANI9" /> + <ANALOG_10 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P90" Point="I" RealName="ANI10" /> + <ANALOG_11 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P91" Point="I" RealName="ANI11" /> + <ANALOG_12 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin" Port="P92" Point="I" RealName="ANI12" /> + </ADC> + <Serial> + <SAU0> + <UART0> + <RXD0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="I" /> + <TXD0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P15" Point="O" /> + </UART0> + <CSI00> + <SO00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P15" Point="O" /> + <SI00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="I" /> + <SCK00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" RealName="_SCK00" Port="P17" Point="I/O" /> + <SSI00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" RealName="_SSI00" Port="P30" Point="I" /> + </CSI00> + <CSI01> + <SO01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P120" Point="O" /> + <SI01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P13" Point="I" /> + <SCK01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P14" RealName="_SCK01" Point="I/O" /> + <SSI01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" RealName="_SSI01" Port="P125" Point="I" /> + </CSI01> + <IIC00> + <SCL00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P17" Point="O" CheckNch="true" /> + <SDA00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="O" CheckNch="true" /> + </IIC00> + <IIC01> + <SCL01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P14" Point="O" CheckNch="true" /> + <SDA01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P13" Point="O" CheckNch="true" /> + </IIC01> + </SAU0> + <SAU1> + <UART1> + <RXD1 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="I" /> + <TXD1 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P12" Point="O" /> + </UART1> + <CSI10> + <SO10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P12" Point="O" /> + <SI10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="I" /> + <SCK10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P10" RealName="_SCK10" Point="I/O" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG"> + <SO11 PIOR43="0" Port="P72" Point="O" /> + <SI11 PIOR43="0" Port="P70" Point="I" /> + <SCK11 PIOR43="0" Port="P71" RealName="_SCK11" Point="I/O" /> + <SSI11 PIOR43="0" RealName="_SSI11" Port="P73" Point="I" /> + </CSI11> + <IIC10> + <SCL10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P10" Point="O" CheckNch="true" /> + <SDA10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="O" CheckNch="true" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG"> + <SCL11 PIOR43="0" Port="P71" Point="O" CheckNch="true" /> + <SDA11 PIOR43="0" Port="P70" Point="O" CheckNch="true" /> + </IIC11> + </SAU1> + <IICA0> + <SCLA0 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" Port="P62" Point="I/O" /> + <SDAA0 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" Port="P63" Point="I/O" /> + </IICA0> + </Serial> + <TAU> + <TAU0> + <Channel0> + <TI00 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR00="0" Port="P17" Point="I" /> + <TO00 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR10="0" Port="P17" Point="O" /> + </Channel0> + <Channel1> + <TI01 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR01="0" Port="P30" Point="I" /> + <TO01 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR11="0" Port="P30" Point="O" /> + </Channel1> + <Channel2> + <TI02 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR02="0" Port="P16" Point="I" /> + <TO02 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR12="0" Port="P16" Point="O" /> + </Channel2> + <Channel3> + <TI03 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR03="0" Port="P125" Point="I" /> + <TO03 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR13="0" Port="P125" Point="O" /> + </Channel3> + <Channel4> + <TI04 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR04="0" Port="P13" Point="I" /> + <TO04 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR14="0" Port="P13" Point="O" /> + </Channel4> + <Channel5> + <TI05 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR05="0" Port="P15" Point="I" /> + <TO05 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR15="1" Port="P00" Point="O" /> + </Channel5> + <Channel6> + <TI06 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR06="0" Port="P14" Point="I" /> + <TO06 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR16="0" Port="P14" Point="O" /> + </Channel6> + <Channel7> + <TI07 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR07="0" Port="P120" Point="I" /> + <TO07 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR17="0" Port="P120" Point="O" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <Channel0> + <TI10 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P41" Point="I" /> + <TO10 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P41" Point="O" /> + </Channel0> + <Channel1> + <TI11 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P12" Point="I" /> + <TO11 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P12" Point="O" /> + </Channel1> + <Channel2> + <TI12 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P11" Point="I" /> + <TO12 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P11" Point="O" /> + </Channel2> + <Channel3> + <TI13 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P10" Point="I" /> + <TO13 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P10" Point="O" /> + </Channel3> + </TAU1> + <TMRJ0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin,RL78F13_30pin"> + <TRJIO0 Port="P41" Point="I/O" /> + <TRJO0 Port="P10" Point="O" /> + </TMRJ0> + <TMRD0> + <TRDCLK_P13_0 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_1" RealName="TRDCLK0" /> + <TRDIOA0_P13 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_0" RealName="TRDIOA0" /> + <TRDIOB0_P125 PIOR71="0" Port="P125" Point="I/O" RealName="TRDIOB0" /> + <TRDIOC0_P14 Port="P14" Point="I/O" RealName="TRDIOC0" /> + <TRDIOD0_P120 PIOR73="0" Port="P120" Point="I/O" RealName="TRDIOD0" /> + <TRDIOA1_P15_0 Port="P15" Point="I/O" UnConflict="TRDIOA1_P15" RealName="TRDIOA1" /> + <TRDIOB1_P17_0 Port="P17" Point="I/O" UnConflict="TRDIOB1_P17" RealName="TRDIOB1" /> + <TRDIOC1_P16_0 Port="P16" Point="I/O" UnConflict="TRDIOC1_P16" RealName="TRDIOC1" /> + <TRDIOD1_P30_0 Port="P30" Point="I/O" UnConflict="TRDIOD1_P30" RealName="TRDIOD1" /> + </TMRD0> + <TMRD1> + <TRDCLK_P13_1 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_0,TRDIOA0_P13" RealName="TRDCLK0" /> + <TRDIOA1_P15 Port="P15" Point="I/O" UnConflict="TRDIOA1_P15_0" RealName="TRDIOA1" /> + <TRDIOB1_P17 Port="P17" Point="I/O" UnConflict="TRDIOB1_P17_0" RealName="TRDIOB1" /> + <TRDIOC1_P16 Port="P16" Point="I/O" UnConflict="TRDIOC1_P16_0" RealName="TRDIOC1" /> + <TRDIOD1_P30 Port="P30" Point="I/O" UnConflict="TRDIOD1_P30_0" RealName="TRDIOD1" /> + </TMRD1> + </TAU> + <RTC> + <RTC1HZ Port="P15" Point="O" /> + </RTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <PCLBUZ0> + <PCLBUZ0 Port="P140" Point="O" /> + </PCLBUZ0> + </PCLBUZ> + <LIN> + <LTxD0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin" PIOR44="0" Port="P13" Point="O" /> + <LRxD0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin" PIOR44="0" Port="P14" Point="I" /> + </LIN> + <CAN> + </CAN> + <Others> + <VDD AltFunc="VDD" Point="-" /> + <VSS AltFunc="VSS" Point="-" /> + <REGC AltFunc="REGC" Point="-" /> + <_RESET AltFunc="_RESET" RealName="_RESET" Point="I" /> + </Others> + </PIN> + <INT> + <CGC> + <INTCLM InUse="0" ISR="r_cgc_clockmonitor_interrupt" /> + <INTRAM InUse="0" ISR="r_cgc_ram_ecc_interrupt" /> + <INTSPM InUse="0" ISR="r_cgc_stackpointer_interrupt" /> + </CGC> + <INTC> + <INTP> + <INTP0 InUse="0" ISR="r_intc0_interrupt" /> + <INTP1 InUse="0" ISR="r_intc1_interrupt" /> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR52="0" InUse="0" ISR="r_intc2_interrupt" /> + <INTP3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" InUse="0" ISR="r_intc3_interrupt" /> + <INTP4 InUse="0" ISR="r_intc4_interrupt" /> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc5_interrupt" /> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc6_interrupt" /> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc7_interrupt" /> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" InUse="0" ISR="r_intc8_interrupt" /> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" InUse="0" ISR="r_intc9_interrupt" /> + </INTP> + <KEY> + <INTKR Chip="RL78F13_48pin,RL78F13_64pin" InUse="0" ISR="r_key_interrupt" /> + </KEY> + </INTC> + <Serial> + <SAU0> + <INTCSI00 InUse="0" ISR="r_csi00_interrupt" /> + <INTCSI01 InUse="0" ISR="r_csi01_interrupt" /> + <INTST0 InUse="0" ISR="r_uart0_interrupt_send" /> + <INTSR0 InUse="0" ISR="r_uart0_interrupt_receive" /> + <INTIIC00 InUse="0" ISR="r_iic00_interrupt" /> + <INTIIC01 InUse="0" ISR="r_iic01_interrupt" /> + </SAU0> + <SAU1> + <INTCSI10 InUse="0" ISR="r_csi10_interrupt" /> + <INTCSI11 InUse="0" ISR="r_csi11_interrupt" /> + <INTST1 InUse="0" ISR="r_uart1_interrupt_send" /> + <INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /> + <INTIIC10 InUse="0" ISR="r_iic10_interrupt" /> + <INTIIC11 InUse="0" ISR="r_iic11_interrupt" /> + </SAU1> + <IICA0> + <INTIICA0 InUse="0" ISR="r_iica0_interrupt" /> + </IICA0> + </Serial> + <ADC> + <INTAD InUse="1" ISR="r_adc_interrupt" IsDMATrigger="true" /> + </ADC> + <TAU> + <TAU0> + <Channel0> + <INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM01 InUse="1" ISR="r_tau0_channel1_interrupt" /> + <INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /> + <INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /> + </Channel7> + </TAU0> + <TAU1> + <Channel0> + <INTTM10 InUse="0" ISR="r_tau1_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM11 InUse="0" ISR="r_tau1_channel1_interrupt" /> + <INTTM11H InUse="0" ISR="r_tau1_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM12 InUse="0" ISR="r_tau1_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM13 InUse="0" ISR="r_tau1_channel3_interrupt" /> + <INTTM13H InUse="0" ISR="r_tau1_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM14 InUse="0" ISR="r_tau1_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM15 InUse="0" ISR="r_tau1_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM16 InUse="0" ISR="r_tau1_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM17 InUse="0" ISR="r_tau1_channel7_interrupt" /> + </Channel7> + </TAU1> + <TMRJ0> + <INTTRJ0 InUse="0" ISR="r_tmr_rj0_interrupt" /> + </TMRJ0> + <TMRD0> + <INTTRD0 InUse="0" ISR="r_tmr_rd0_interrupt" /> + </TMRD0> + <TMRD1> + <INTTRD1 InUse="0" ISR="r_tmr_rd1_interrupt" /> + </TMRD1> + </TAU> + <RTC> + <INTRTC InUse="0" ISR="r_rtc_interrupt" /> + </RTC> + <WDT> + <INTWDTI InUse="1" ISR="r_wdt_interrupt" /> + </WDT> + <LVD> + <INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /> + </LVD> + </INT> + <FUNC> + <Common> + <r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"> + <Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /> + <main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /> + <R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /> + </r_main.c> + <r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /> + <R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /> + <hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /> + <__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /> + </r_systeminit.c> + <r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /> + <R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /> + <HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /> + </r_hardware_setup.c> + <r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"> + <Type R_Dummy="void R_Dummy(void)" /> + <R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /> + </r_cg_vector_table.c> + <r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /> + <r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /> + <r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /> + <r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /> + <r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /> + <r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /> + <iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /> + </Common> + <CGC> + <r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"> + <Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(enum ClockMode mode)" R_CGC_ClockMonitor_Start="void R_CGC_ClockMonitor_Start(void)" R_CGC_ClockMonitor_Stop="void R_CGC_ClockMonitor_Stop(void)" R_CGC_StackPointer_Start="void R_CGC_StackPointer_Start(void)" R_CGC_StackPointer_Stop="void R_CGC_StackPointer_Stop(void)" R_CGC_RAMECC_Start="void R_CGC_RAMECC_Start(void)" R_CGC_RAMECC_Stop="void R_CGC_RAMECC_Stop(void)" /> + <R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /> + <R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /> + <R_CGC_ClockMonitor_Start UserName="R_CGC_ClockMonitor_Start" LibName="R_CGC_ClockMonitor_Start" InUse="0" /> + <R_CGC_ClockMonitor_Stop UserName="R_CGC_ClockMonitor_Stop" LibName="R_CGC_ClockMonitor_Stop" InUse="0" /> + <R_CGC_StackPointer_Start UserName="R_CGC_StackPointer_Start" LibName="R_CGC_StackPointer_Start" InUse="0" /> + <R_CGC_StackPointer_Stop UserName="R_CGC_StackPointer_Stop" LibName="R_CGC_StackPointer_Stop" InUse="0" /> + <R_CGC_RAMECC_Start UserName="R_CGC_RAMECC_Start" LibName="R_CGC_RAMECC_Start" InUse="0" /> + <R_CGC_RAMECC_Stop UserName="R_CGC_RAMECC_Stop" LibName="R_CGC_RAMECC_Stop" InUse="0" /> + </r_cg_cgc.c> + <r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"> + <Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" r_cgc_clockmonitor_interrupt="__interrupt static void r_cgc_clockmonitor_interrupt(void)" r_cgc_stackpointer_interrupt="__interrupt static void r_cgc_stackpointer_interrupt(void)" r_cgc_ram_ecc_interrupt="__interrupt static void r_cgc_ram_ecc_interrupt(void)" /> + <R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /> + <R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /> + <r_cgc_clockmonitor_interrupt UserName="r_cgc_clockmonitor_interrupt" INTHandle="" LibName="r_cgc_clockmonitor_interrupt" InUse="0" /> + <r_cgc_stackpointer_interrupt UserName="r_cgc_stackpointer_interrupt" INTHandle="" LibName="r_cgc_stackpointer_interrupt" InUse="0" /> + <r_cgc_ram_ecc_interrupt UserName="r_cgc_ram_ecc_interrupt" INTHandle="" LibName="r_cgc_ram_ecc_interrupt" InUse="0" /> + </r_cg_cgc_user.c> + <r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /> + <r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"> + <Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /> + <R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /> + <R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /> + <R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /> + <R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /> + <R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /> + <R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /> + <R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /> + <R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /> + </r_cg_pfdl.c> + <r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /> + </CGC> + <PORT> + <r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"> + <Type R_PORT_Create="void R_PORT_Create(void)" /> + <R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /> + </r_cg_port.c> + <r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"> + <Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /> + <R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /> + </r_cg_port_user.c> + <r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /> + </PORT> + <INTC> + <r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse=""> + <Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /> + <INTP> + <R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="" Init="2" InitMode="" /> + <INTP0> + <R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP0> + <INTP1> + <R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP1> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP2> + <INTP3 Chip="RL78F13_48pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0"> + <R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP3> + <INTP4> + <R_INTC4_Start UserName="R_INTC4_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC4_Stop UserName="R_INTC4_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP4> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC5_Start UserName="R_INTC5_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC5_Stop UserName="R_INTC5_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP5> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC6_Start UserName="R_INTC6_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC6_Stop UserName="R_INTC6_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP6> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC7_Start UserName="R_INTC7_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC7_Stop UserName="R_INTC7_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP7> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin"> + <R_INTC8_Start UserName="R_INTC8_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC8_Stop UserName="R_INTC8_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP8> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin"> + <R_INTC9_Start UserName="R_INTC9_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC9_Stop UserName="R_INTC9_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP9> + </INTP> + <KEY Chip="RL78F13_48pin,RL78F13_64pin"> + <R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /> + <R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /> + <R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /> + </KEY> + </r_cg_intc.c> + <r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse=""> + <Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" r_intc0_interrupt="__interrupt static void r_intc0_interrupt(void)" r_intc1_interrupt="__interrupt static void r_intc1_interrupt(void)" r_intc2_interrupt="__interrupt static void r_intc2_interrupt(void)" r_intc3_interrupt="__interrupt static void r_intc3_interrupt(void)" r_intc4_interrupt="__interrupt static void r_intc4_interrupt(void)" r_intc5_interrupt="__interrupt static void r_intc5_interrupt(void)" r_intc6_interrupt="__interrupt static void r_intc6_interrupt(void)" r_intc7_interrupt="__interrupt static void r_intc7_interrupt(void)" r_intc8_interrupt="__interrupt static void r_intc8_interrupt(void)" r_intc9_interrupt="__interrupt static void r_intc9_interrupt(void)" r_intc10_interrupt="__interrupt static void r_intc10_interrupt(void)" r_intc11_interrupt="__interrupt static void r_intc11_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" r_key_interrupt="__interrupt static void r_key_interrupt(void)" /> + <INTP> + <R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="" /> + <r_intc0_interrupt UserName="r_intc0_interrupt" LibName="r_intc0_interrupt" INTHandle="" InUse="" /> + <r_intc1_interrupt UserName="r_intc1_interrupt" LibName="r_intc1_interrupt" INTHandle="" InUse="" /> + <r_intc2_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc2_interrupt" LibName="r_intc2_interrupt" INTHandle="" InUse="" /> + <r_intc3_interrupt Chip="RL78F13_48pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" UserName="r_intc3_interrupt" LibName="r_intc3_interrupt" INTHandle="" InUse="" /> + <r_intc4_interrupt UserName="r_intc4_interrupt" LibName="r_intc4_interrupt" INTHandle="" InUse="" /> + <r_intc5_interrupt Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc5_interrupt" LibName="r_intc5_interrupt" INTHandle="" InUse="" /> + <r_intc6_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc6_interrupt" LibName="r_intc6_interrupt" INTHandle="" InUse="" /> + <r_intc7_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc7_interrupt" LibName="r_intc7_interrupt" INTHandle="" InUse="" /> + <r_intc8_interrupt Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" UserName="r_intc8_interrupt" LibName="r_intc8_interrupt" INTHandle="" InUse="" /> + <r_intc9_interrupt Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" UserName="r_intc9_interrupt" LibName="r_intc9_interrupt" INTHandle="" InUse="" /> + </INTP> + <KEY Chip="RL78F13_48pin,RL78F13_64pin"> + <R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /> + <r_key_interrupt UserName="r_key_interrupt" LibName="r_key_interrupt" INTHandle="" InUse="" /> + </KEY> + </r_cg_intc_user.c> + <r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="" /> + </INTC> + <Serial> + <r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="0"> + <Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t const * tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t const * rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t const * tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t const * rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t const * tx_buf, uint16_t tx_num, uint8_t const * rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t const * tx_buf, uint16_t txnum)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t const * rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" R_UARTFn_Create="void R_UARTFn_Create(void)" R_UARTFn_Send="MD_STATUS R_UARTFn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTFn_Receive="MD_STATUS R_UARTFn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTFn_Set_ComparisonData="void R_UARTFn_Set_ComparisonData(uint16_t com_data)" R_UARTFn_Set_DataComparisonOn="void R_UARTFn_Set_DataComparisonOn(void)" R_UARTFn_Set_DataComparisonOff="void R_UARTFn_Set_DataComparisonOff(void)" R_UARTFn_Set_PowerOff="void R_UARTFn_Set_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="0" Init="1" InitMode="" /> + <R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /> + <R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /> + <R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /> + <UART0 InUse=""> + <R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="0" InitMode="" /> + <R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="0" /> + <R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="0" /> + <R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="0" /> + <R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="0" /> + </UART0> + <CSI00 InUse=""> + <R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI00> + <CSI01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI01> + <IIC00 InUse=""> + <R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC00> + <IIC01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC01> + </SAU0> + <SAU1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_SAU1_Create UserName="R_SAU1_Create" LibName="R_SAUn_Create" InUse="" Init="1" InitMode="" /> + <R_SAU1_Set_PowerOff UserName="R_SAU1_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="" /> + <UART1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_UART1_Create UserName="R_UART1_Create" LibName="R_UARTn_Create" InUse="" InitMode="" /> + <R_UART1_Start UserName="R_UART1_Start" LibName="R_UARTn_Start" InUse="" /> + <R_UART1_Stop UserName="R_UART1_Stop" LibName="R_UARTn_Stop" InUse="" /> + <R_UART1_Send UserName="R_UART1_Send" LibName="R_UARTn_Send" InUse="" /> + <R_UART1_Receive UserName="R_UART1_Receive" LibName="R_UARTn_Receive" InUse="" /> + </UART1> + <CSI10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <R_CSI10_Create UserName="R_CSI10_Create" LibName="R_CSIn_Create" InUse="" InitMode="" /> + <R_CSI10_Start UserName="R_CSI10_Start" LibName="R_CSIn_Start" InUse="" /> + <R_CSI10_Stop UserName="R_CSI10_Stop" LibName="R_CSIn_Stop" InUse="" /> + <R_CSI10_Send UserName="R_CSI10_Send" LibName="R_CSIn_Send" InUse="" /> + <R_CSI10_Receive UserName="R_CSI10_Receive" LibName="R_CSIn_Receive" InUse="" /> + <R_CSI10_Send_Receive UserName="R_CSI10_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <R_CSI11_Create UserName="R_CSI11_Create" LibName="R_CSIn_Create" InUse="" InitMode="" /> + <R_CSI11_Start UserName="R_CSI11_Start" LibName="R_CSIn_Start" InUse="" /> + <R_CSI11_Stop UserName="R_CSI11_Stop" LibName="R_CSIn_Stop" InUse="" /> + <R_CSI11_Send UserName="R_CSI11_Send" LibName="R_CSIn_Send" InUse="" /> + <R_CSI11_Receive UserName="R_CSI11_Receive" LibName="R_CSIn_Receive" InUse="" /> + <R_CSI11_Send_Receive UserName="R_CSI11_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="" /> + </CSI11> + <IIC10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <R_IIC10_Create UserName="R_IIC10_Create" LibName="R_IICn_Create" InUse="" InitMode="" /> + <R_IIC10_Master_Send UserName="R_IIC10_Master_Send" LibName="R_IICn_Master_Send" InUse="" /> + <R_IIC10_Master_Receive UserName="R_IIC10_Master_Receive" LibName="R_IICn_Master_Receive" InUse="" /> + <R_IIC10_Stop UserName="R_IIC10_Stop" LibName="R_IICn_Stop" InUse="" /> + <R_IIC10_StartCondition UserName="R_IIC10_StartCondition" LibName="R_IICn_StartCondition" InUse="" /> + <R_IIC10_StopCondition UserName="R_IIC10_StopCondition" LibName="R_IICn_StopCondition" InUse="" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <R_IIC11_Create UserName="R_IIC11_Create" LibName="R_IICn_Create" InUse="" InitMode="" /> + <R_IIC11_Master_Send UserName="R_IIC11_Master_Send" LibName="R_IICn_Master_Send" InUse="" /> + <R_IIC11_Master_Receive UserName="R_IIC11_Master_Receive" LibName="R_IICn_Master_Receive" InUse="" /> + <R_IIC11_Stop UserName="R_IIC11_Stop" LibName="R_IICn_Stop" InUse="" /> + <R_IIC11_StartCondition UserName="R_IIC11_StartCondition" LibName="R_IICn_StartCondition" InUse="" /> + <R_IIC11_StopCondition UserName="R_IIC11_StopCondition" LibName="R_IICn_StopCondition" InUse="" /> + </IIC11> + </SAU1> + <IICA0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse=""> + <R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /> + <R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /> + <R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /> + <R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /> + <R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /> + <R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /> + <R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /> + <R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /> + <R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /> + <R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /> + </IICA0> + </r_cg_serial.c> + <r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="0"> + <Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" r_uartn_interrupt_receive="__interrupt void r_uartn_interrupt_receive(void)" r_uartn_interrupt_error="__interrupt void r_uartn_interrupt_error(void)" r_uartn_interrupt_send="__interrupt void r_uartn_interrupt_send(void)" r_uartn_callback_sendend="void r_uartn_callback_sendend(void)" r_uartn_callback_receiveend="void r_uartn_callback_receiveend(void)" r_uartn_callback_error="void r_uartn_callback_error(uint16_t err_type)" r_uartn_callback_softwareoverrun="void r_uartn_callback_softwareoverrun(uint16_t err_type)" r_csin_interrupt="__interrupt void r_csin_interrupt(void)" r_csin_callback_receiveend="void r_csin_callback_receiveend(void)" r_csin_callback_error="void r_csin_callback_error(uint16_t err_type)" r_csin_callback_sendend="void r_csin_callback_sendend(void)" r_iicn_interrupt="__interrupt void r_iicn_interrupt(void)" r_iicn_callback_master_receiveend="void r_iicn_callback_master_receiveend(void)" r_iicn_callback_master_sendend="void r_iicn_callback_master_sendend(void)" r_iicn_callback_master_error="void r_iicn_callback_master_error(MD_STATUS flag)" R_UARTFn_Create_UserInit="void R_UARTFn_Create_UserInit(void)" r_uartfn_interrupt_receive="__interrupt static void r_uartfn_interrupt_receive(void)" r_uartfn_interrupt_error="__interrupt static void r_uartfn_interrupt_error(void)" r_uartfn_interrupt_send="__interrupt static void r_uartfn_interrupt_send(void)" r_uartfn_callback_receiveend="static void r_uartfn_callback_receiveend(void)" r_uartfn_callback_sendend="static void r_uartfn_callback_sendend(void)" r_uartfn_callback_error="static void r_uartfn_callback_error(void)" r_uartfn_callback_softwareoverrun="static void r_uartfn_callback_softwareoverrun(uint16_t rx_data)" r_uartfn_callback_expbitdetect="static void r_uartfn_callback_expbitdetect(void)" r_uartfn_callback_idmatch="static void r_uartfn_callback_idmatch(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /> + <UART0 InUse=""> + <r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="r_uartn_interrupt_receive" InUse="0" /> + <r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="r_uartn_interrupt_send" InUse="0" /> + <r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="r_uartn_callback_receiveend" InUse="0" /> + <r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="r_uartn_callback_sendend" InUse="0" /> + <r_uart0_callback_error UserName="r_uart0_callback_error" LibName="r_uartn_callback_error" InUse="0" /> + <r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="r_uartn_callback_softwareoverrun" InUse="0" /> + </UART0> + <CSI00 InUse=""> + <r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="0" /> + <r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="0" /> + <r_csi00_callback_error UserName="r_csi00_callback_error" LibName="r_csin_callback_error" InUse="0" /> + <r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="r_csin_callback_sendend" InUse="0" /> + </CSI00> + <CSI01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="0" /> + <r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="0" /> + <r_csi01_callback_error UserName="r_csi01_callback_error" LibName="r_csin_callback_error" InUse="0" /> + <r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="r_csin_callback_sendend" InUse="0" /> + </CSI01> + <IIC00 InUse=""> + <r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="0" /> + <r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="0" /> + <r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="0" /> + <r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="r_iicn_callback_master_error" InUse="0" /> + </IIC00> + <IIC01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="0" /> + <r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="0" /> + <r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="0" /> + <r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="r_iicn_callback_master_error" InUse="0" /> + </IIC01> + </SAU0> + <SAU1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_SAU1_Create_UserInit UserName="R_SAU1_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="" /> + <UART1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_uart1_interrupt_receive UserName="r_uart1_interrupt_receive" INTHandle="" LibName="r_uartn_interrupt_receive" InUse="" /> + <r_uart1_interrupt_send UserName="r_uart1_interrupt_send" INTHandle="" LibName="r_uartn_interrupt_send" InUse="" /> + <r_uart1_callback_receiveend UserName="r_uart1_callback_receiveend" LibName="r_uartn_callback_receiveend" InUse="" /> + <r_uart1_callback_sendend UserName="r_uart1_callback_sendend" LibName="r_uartn_callback_sendend" InUse="" /> + <r_uart1_callback_error UserName="r_uart1_callback_error" LibName="r_uartn_callback_error" InUse="" /> + <r_uart1_callback_softwareoverrun UserName="r_uart1_callback_softwareoverrun" LibName="r_uartn_callback_softwareoverrun" InUse="" /> + </UART1> + <CSI10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_csi10_interrupt UserName="r_csi10_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="" /> + <r_csi10_callback_receiveend UserName="r_csi10_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="" /> + <r_csi10_callback_error UserName="r_csi10_callback_error" LibName="r_csin_callback_error" InUse="" /> + <r_csi10_callback_sendend UserName="r_csi10_callback_sendend" LibName="r_csin_callback_sendend" InUse="" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <r_csi11_interrupt UserName="r_csi11_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="" /> + <r_csi11_callback_receiveend UserName="r_csi11_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="" /> + <r_csi11_callback_error UserName="r_csi11_callback_error" LibName="r_csin_callback_error" InUse="" /> + <r_csi11_callback_sendend UserName="r_csi11_callback_sendend" LibName="r_csin_callback_sendend" InUse="" /> + </CSI11> + <IIC10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_iic10_interrupt UserName="r_iic10_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="" /> + <r_iic10_callback_master_receiveend UserName="r_iic10_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="" /> + <r_iic10_callback_master_sendend UserName="r_iic10_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="" /> + <r_iic10_callback_master_error UserName="r_iic10_callback_master_error" LibName="r_iicn_callback_master_error" InUse="" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <r_iic11_interrupt UserName="r_iic11_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="" /> + <r_iic11_callback_master_receiveend UserName="r_iic11_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="" /> + <r_iic11_callback_master_sendend UserName="r_iic11_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="" /> + <r_iic11_callback_master_error UserName="r_iic11_callback_master_error" LibName="r_iicn_callback_master_error" InUse="" /> + </IIC11> + </SAU1> + <IICA0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse=""> + <R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /> + <r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /> + <r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /> + <r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /> + <r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /> + <r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /> + <r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /> + <r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /> + <r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /> + </IICA0> + </r_cg_serial_user.c> + <r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="0" /> + </Serial> + <ADC> + <r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="1"> + <Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /> + <R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="1" Init="1" InitMode="" /> + <R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="1" /> + <R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="1" /> + <R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="1" /> + <R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="1" /> + <R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="1" /> + <R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /> + <R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /> + <R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /> + <R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /> + <R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /> + <R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /> + </r_cg_adc.c> + <r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="1"> + <Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /> + <R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /> + <r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="1" /> + </r_cg_adc_user.c> + <r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="1" /> + </ADC> + <TAU> + <r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"> + <Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" R_WUTM_Create="void R_WUTM_Create(void)" R_WUTM_Start="void R_WUTM_Start(void)" R_WUTM_Stop="void R_WUTM_Stop(void)" R_WUTM_Set_PowerOff="void R_WUTM_Set_PowerOff(void)" /> + <TAU0> + <R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /> + <R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel0_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" PIOR00="0" UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel2_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" PIOR02="0" UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR03="0" UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + <Channel4 InUse=""> + <R_TAU0_Channel4_Start UserName="R_TAU0_Channel4_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel4_Stop UserName="R_TAU0_Channel4_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel4_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" UserName="R_TAU0_Channel4_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel4_Set_SoftwareTriggerOn UserName="R_TAU0_Channel4_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel4> + <Channel5 InUse=""> + <R_TAU0_Channel5_Start UserName="R_TAU0_Channel5_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel5_Stop UserName="R_TAU0_Channel5_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel5_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="R_TAU0_Channel5_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel5> + <Channel6 InUse=""> + <R_TAU0_Channel6_Start UserName="R_TAU0_Channel6_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel6_Stop UserName="R_TAU0_Channel6_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel6_Get_PulseWidth UserName="R_TAU0_Channel6_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel6_Set_SoftwareTriggerOn Chip="RL78F13_48pin,RL78F13_64pin" PIOR17="0" UserName="R_TAU0_Channel6_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel6> + <Channel7 InUse=""> + <R_TAU0_Channel7_Start UserName="R_TAU0_Channel7_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel7_Stop UserName="R_TAU0_Channel7_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel7_Get_PulseWidth UserName="R_TAU0_Channel7_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <R_TAU1_Create UserName="R_TAU1_Create" LibName="R_TAU_Create" InUse="0" Init="1" InitMode="" /> + <R_TAU1_Set_PowerOff UserName="R_TAU1_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU1_Channel0_Start UserName="R_TAU1_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel0_Stop UserName="R_TAU1_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel0_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU1_Channel0_Set_SoftwareTriggerOn UserName="R_TAU1_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU1_Channel1_Start UserName="R_TAU1_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel1_Higher8bits_Start UserName="R_TAU1_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU1_Channel1_Lower8bits_Start UserName="R_TAU1_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU1_Channel1_Stop UserName="R_TAU1_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel1_Higher8bits_Stop UserName="R_TAU1_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU1_Channel1_Lower8bits_Stop UserName="R_TAU1_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU1_Channel1_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU1_Channel2_Start UserName="R_TAU1_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel2_Stop UserName="R_TAU1_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel2_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU1_Channel2_Set_SoftwareTriggerOn UserName="R_TAU1_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU1_Channel3_Start UserName="R_TAU1_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel3_Higher8bits_Start UserName="R_TAU1_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU1_Channel3_Lower8bits_Start UserName="R_TAU1_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU1_Channel3_Stop UserName="R_TAU1_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel3_Higher8bits_Stop UserName="R_TAU1_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU1_Channel3_Lower8bits_Stop UserName="R_TAU1_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU1_Channel3_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + </TAU1> + <TMRJ0 InUse=""> + <R_TMR_RJ0_Create UserName="R_TMR_RJ0_Create" LibName="R_TMR_RJn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RJ0_Start UserName="R_TMR_RJ0_Start" LibName="R_TMR_RJn_Start" InUse="" /> + <R_TMR_RJ0_Stop UserName="R_TMR_RJ0_Stop" LibName="R_TMR_RJn_Stop" InUse="" /> + <R_TMR_RJ0_Get_PulseWidth Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin,RL78F13_30pin" UserName="R_TMR_RJ0_Get_PulseWidth" LibName="R_TMR_RJn_Get_PulseWidth" InUse="" /> + <R_TMR_RJ0_Set_PowerOff UserName="R_TMR_RJ0_Set_PowerOff" LibName="R_TMR_RJn_Set_PowerOff" InUse="" /> + </TMRJ0> + <TMRD0 InUse=""> + <R_TMR_RD0_Create UserName="R_TMR_RD0_Create" LibName="R_TMR_RDn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RD0_Start UserName="R_TMR_RD0_Start" LibName="R_TMR_RDn_Start" InUse="" /> + <R_TMR_RD0_Stop UserName="R_TMR_RD0_Stop" LibName="R_TMR_RDn_Stop" InUse="" /> + <R_TMR_RD0_Get_PulseWidth UserName="R_TMR_RD0_Get_PulseWidth" LibName="R_TMR_RDn_Get_PulseWidth" InUse="" /> + <R_TMR_RD0_Set_PowerOff UserName="R_TMR_RD0_Set_PowerOff" LibName="R_TMR_RDn_Set_PowerOff" InUse="" /> + <R_TMR_RD0_ForcedOutput_Start UserName="R_TMR_RD0_ForcedOutput_Start" LibName="R_TMR_RDn_ForcedOutput_Start" InUse="" /> + <R_TMR_RD0_ForcedOutput_Stop UserName="R_TMR_RD0_ForcedOutput_Stop" LibName="R_TMR_RDn_ForcedOutput_Stop" InUse="" /> + </TMRD0> + <TMRD1 InUse=""> + <R_TMR_RD1_Create UserName="R_TMR_RD1_Create" LibName="R_TMR_RDn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RD1_Start UserName="R_TMR_RD1_Start" LibName="R_TMR_RDn_Start" InUse="" /> + <R_TMR_RD1_Stop UserName="R_TMR_RD1_Stop" LibName="R_TMR_RDn_Stop" InUse="" /> + <R_TMR_RD1_Get_PulseWidth UserName="R_TMR_RD1_Get_PulseWidth" LibName="R_TMR_RDn_Get_PulseWidth" InUse="" /> + <R_TMR_RD1_Set_PowerOff UserName="R_TMR_RD1_Set_PowerOff" LibName="R_TMR_RDn_Set_PowerOff" InUse="" /> + <R_TMR_RD1_ForcedOutput_Start UserName="R_TMR_RD1_ForcedOutput_Start" LibName="R_TMR_RDn_ForcedOutput_Start" InUse="" /> + <R_TMR_RD1_ForcedOutput_Stop UserName="R_TMR_RD1_ForcedOutput_Stop" LibName="R_TMR_RDn_ForcedOutput_Stop" InUse="" /> + </TMRD1> + </r_cg_timer.c> + <r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"> + <Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" R_WUTM_Create_UserInit="void R_WUTM_Create_UserInit(void)" r_wutm_interrupt="__interrupt static void r_wutm_interrupt(void)" /> + <TAU0> + <R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + </Channel0> + <Channel1 InUse=""> + <r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + <r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + <Channel4 InUse=""> + <r_tau0_channel4_interrupt UserName="r_tau0_channel4_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel4> + <Channel5 InUse=""> + <r_tau0_channel5_interrupt UserName="r_tau0_channel5_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel5> + <Channel6 InUse=""> + <r_tau0_channel6_interrupt UserName="r_tau0_channel6_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel6> + <Channel7 InUse=""> + <r_tau0_channel7_interrupt UserName="r_tau0_channel7_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <R_TAU1_Create_UserInit UserName="R_TAU1_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau1_channel0_interrupt UserName="r_tau1_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <r_tau1_channel1_interrupt UserName="r_tau1_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau1_channel1_higher8bits_interrupt UserName="r_tau1_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau1_channel2_interrupt UserName="r_tau1_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau1_channel3_interrupt UserName="r_tau1_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau1_channel3_higher8bits_interrupt UserName="r_tau1_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + </TAU1> + <TMRJ0 InUse=""> + <R_TMR_RJ0_Create_UserInit UserName="R_TMR_RJ0_Create_UserInit" LibName="R_TMR_RJn_Create_UserInit" InUse="" /> + <r_tmr_rj0_interrupt UserName="r_tmr_rj0_interrupt" LibName="r_tmr_rjn_interrupt" INTHandle="" InUse="" /> + </TMRJ0> + <TMRD0 InUse=""> + <R_TMR_RD0_Create_UserInit UserName="R_TMR_RD0_Create_UserInit" LibName="R_TMR_RDn_Create_UserInit" InUse="" /> + <r_tmr_rd0_interrupt UserName="r_tmr_rd0_interrupt" LibName="r_tmr_rdn_interrupt" INTHandle="" InUse="" /> + </TMRD0> + <TMRD1 InUse=""> + <R_TMR_RD1_Create_UserInit UserName="R_TMR_RD1_Create_UserInit" LibName="R_TMR_RDn_Create_UserInit" InUse="" /> + <r_tmr_rd1_interrupt UserName="r_tmr_rd1_interrupt" LibName="r_tmr_rdn_interrupt" INTHandle="" InUse="" /> + </TMRD1> + </r_cg_timer_user.c> + <r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /> + </TAU> + <WDT> + <r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"> + <Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /> + <R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /> + <R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /> + </r_cg_wdt.c> + <r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"> + <Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /> + <R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /> + <r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="1" /> + </r_cg_wdt_user.c> + <r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /> + </WDT> + <RTC> + <r_cg_rtc.c UserName="r_cg_rtc.c" LibName=".c" InUse="0"> + <Type R_RTC_Create="void R_RTC_Create(void)" R_RTC_Start="void R_RTC_Start(void)" R_RTC_Stop="void R_RTC_Stop(void)" R_RTC_Set_HourSystem="MD_STATUS R_RTC_SetHourSystem(rtc_hour_system_t hour_system)" R_RTC_Get_CounterValue="MD_STATUS R_RTC_Get_CounterValue(rtc_counter_value_t * const counter_read_val)" R_RTC_Set_CounterValue="MD_STATUS R_RTC_Set_CounterValue(rtc_counter_value_t counter_write_val)" R_RTC_Set_AlarmOn="void R_RTC_Set_AlarmOn(void)" R_RTC_Set_AlarmOff="void R_RTC_Set_AlarmOff(void)" R_RTC_Set_AlarmValue="void R_RTC_Set_AlarmValue(rtc_alarm_value_t alarm_val)" R_RTC_Get_AlarmValue="void R_RTC_Get_AlarmValue(rtc_alarm_value_t * const alarm_val)" R_RTC_Set_ConstPeriodInterruptOn="MD_STATUS R_RTC_Set_ConstPeriodInterruptOn(rtc_int_period_t period)" R_RTC_Set_ConstPeriodInterruptOff="void R_RTC_Set_ConstPeriodInterruptOff(void)" R_RTC_Set_RTC1HZOn="void R_RTC_Set_RTC1HZOn(void)" R_RTC_Set_RTC1HZOff="void R_RTC_Set_RTC1HZOff(void)" R_RTC_Set_PowerOff="void R_RTC_Set_PowerOff(void)" /> + <R_RTC_Create UserName="R_RTC_Create" LibName="R_RTC_Create" InUse="0" Init="1" InitMode="" /> + <R_RTC_Start UserName="R_RTC_Start" LibName="R_RTC_Start" InUse="0" /> + <R_RTC_Stop UserName="R_RTC_Stop" LibName="R_RTC_Stop" InUse="0" /> + <R_RTC_Set_HourSystem UserName="R_RTC_Set_HourSystem" LibName="R_RTC_Set_HourSystem" InUse="0" /> + <R_RTC_Get_CounterValue UserName="R_RTC_Get_CounterValue" LibName="R_RTC_Get_CounterValue" InUse="0" /> + <R_RTC_Set_CounterValue UserName="R_RTC_Set_CounterValue" LibName="R_RTC_Set_CounterValue" InUse="0" /> + <R_RTC_Set_AlarmOn UserName="R_RTC_Set_AlarmOn" LibName="R_RTC_Set_AlarmOn" InUse="0" /> + <R_RTC_Set_AlarmOff UserName="R_RTC_Set_AlarmOff" LibName="R_RTC_Set_AlarmOff" InUse="0" /> + <R_RTC_Set_AlarmValue UserName="R_RTC_Set_AlarmValue" LibName="R_RTC_Set_AlarmValue" InUse="0" /> + <R_RTC_Get_AlarmValue UserName="R_RTC_Get_AlarmValue" LibName="R_RTC_Get_AlarmValue" InUse="0" /> + <R_RTC_Set_ConstPeriodInterruptOn UserName="R_RTC_Set_ConstPeriodInterruptOn" LibName="R_RTC_Set_ConstPeriodInterruptOn" InUse="0" /> + <R_RTC_Set_ConstPeriodInterruptOff UserName="R_RTC_Set_ConstPeriodInterruptOff" LibName="R_RTC_Set_ConstPeriodInterruptOff" InUse="0" /> + <R_RTC_Set_RTC1HZOn UserName="R_RTC_Set_RTC1HZOn" LibName="R_RTC_Set_RTC1HZOn" InUse="0" /> + <R_RTC_Set_RTC1HZOff UserName="R_RTC_Set_RTC1HZOff" LibName="R_RTC_Set_RTC1HZOff" InUse="0" /> + <R_RTC_Set_PowerOff UserName="R_RTC_Set_PowerOff" LibName="R_RTC_Set_PowerOff" InUse="0" /> + </r_cg_rtc.c> + <r_cg_rtc_user.c UserName="r_cg_rtc_user.c" LibName="_user.c" InUse="0"> + <Type R_RTC_Create_UserInit="void R_RTC_Create_UserInit(void)" r_rtc_interrupt="__interrupt static void r_rtc_interrupt(void)" r_rtc_callback_constperiod="static void r_rtc_callback_constperiod(void)" r_rtc_callback_alarm="static void r_rtc_callback_alarm(void)" /> + <R_RTC_Create_UserInit UserName="R_RTC_Create_UserInit" LibName="R_RTC_Create_UserInit" InUse="0" /> + <r_rtc_interrupt UserName="r_rtc_interrupt" INTHandle="" LibName="r_rtc_interrupt" InUse="0" /> + <r_rtc_callback_constperiod UserName="r_rtc_callback_constperiod" LibName="r_rtc_callback_constperiod" InUse="0" /> + <r_rtc_callback_alarm UserName="r_rtc_callback_alarm" LibName="r_rtc_callback_alarm" InUse="0" /> + </r_cg_rtc_user.c> + <r_cg_rtc.h UserName="r_cg_rtc.h" LibName=".h" InUse="0" /> + </RTC> + <DTC InUse=""> + <r_cg_dtc.c UserName="r_cg_dtc.c" LibName=".c" InUse=""> + <Type R_DTC_Create="void R_DTC_Create(void)" R_DTCDn_Start="void R_DTCDn_Start(void)" R_DTCDn_Stop="void R_DTCDn_Stop(void)" R_DTC_Set_PowerOff="void R_DTC_Set_PowerOff(void)" /> + <R_DTC_Create UserName="R_DTC_Create" LibName="R_DTC_Create" InUse="" Init="2" InitMode="" /> + <DTCD0> + <R_DTCD0_Start LibName="R_DTCDn_Start" InUse="" Visible="False" /> + <R_DTCD0_Stop LibName="R_DTCDn_Stop" InUse="" Visible="False" /> + </DTCD0> + <DTCD1> + <R_DTCD1_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD1_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD1> + <DTCD2> + <R_DTCD2_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD2_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD2> + <DTCD3> + <R_DTCD3_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD3_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD3> + <DTCD4> + <R_DTCD4_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD4_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD4> + <DTCD5> + <R_DTCD5_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD5_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD5> + <DTCD6> + <R_DTCD6_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD6_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD6> + <DTCD7> + <R_DTCD7_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD7_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD7> + <DTCD8> + <R_DTCD8_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD8_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD8> + <DTCD9> + <R_DTCD9_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD9_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD9> + <DTCD10> + <R_DTCD10_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD10_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD10> + <DTCD11> + <R_DTCD11_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD11_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD11> + <DTCD12> + <R_DTCD12_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD12_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD12> + <DTCD13> + <R_DTCD13_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD13_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD13> + <DTCD14> + <R_DTCD14_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD14_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD14> + <DTCD15> + <R_DTCD15_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD15_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD15> + <DTCD16> + <R_DTCD16_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD16_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD16> + <DTCD17> + <R_DTCD17_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD17_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD17> + <DTCD18> + <R_DTCD18_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD18_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD18> + <DTCD19> + <R_DTCD19_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD19_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD19> + <DTCD20> + <R_DTCD20_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD20_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD20> + <DTCD21> + <R_DTCD21_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD21_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD21> + <DTCD22> + <R_DTCD22_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD22_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD22> + <DTCD23> + <R_DTCD23_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD23_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD23> + <DTCH0> + <R_DTCH0_Start LibName="R_DTCHn_Start" InUse="" Visible="false" /> + <R_DTCH0_Stop LibName="R_DTCHn_Stop" InUse="" Visible="false" /> + </DTCH0> + <DTCH1> + <R_DTCH1_Start LibName="R_DTCHn_Start" InUse="" Visible="false" /> + <R_DTCH1_Stop LibName="R_DTCHn_Stop" InUse="" Visible="false" /> + </DTCH1> + <R_DTC_Set_PowerOff UserName="R_DTC_Set_PowerOff" LibName="R_DTC_Set_PowerOff" InUse="" /> + </r_cg_dtc.c> + <r_cg_dtc_user.c UserName="r_cg_dtc_user.c" LibName="_user.c" InUse=""> + <Type R_DTC_Create_UserInit="void R_DTC_Create_UserInit(void)" /> + <R_DTC_Create_UserInit UserName="R_DTC_Create_UserInit" LibName="R_DTC_Create_UserInit" InUse="" /> + </r_cg_dtc_user.c> + <r_cg_dtc.h UserName="r_cg_dtc.h" LibName=".h" InUse="" /> + </DTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse="0"> + <Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="0" Init="1" InitMode="" /> + <R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="0" /> + <R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="0" /> + </PCLBUZ0> + </r_cg_pclbuz.c> + <r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse="0"> + <Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="0" Init="1" /> + </PCLBUZ0> + </r_cg_pclbuz_user.c> + <r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="0" /> + </PCLBUZ> + <LVD> + <r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"> + <Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /> + <R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /> + <R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /> + </r_cg_lvd.c> + <r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"> + <Type R_LVD_Create_UserInit="void R_LVD_Create_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /> + <R_LVD_Create_UserInit UserName="R_LVD_Create_UserInit" LibName="R_LVD_Create_UserInit" InUse="0" /> + <r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /> + </r_cg_lvd_user.c> + <r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /> + </LVD> + </FUNC> + <TAG> + <GlobleUserTag> + <cg_security9 Name="cg_security9" Value="00" /> + <cg_security7 Name="cg_security7" Value="00" /> + <pior_value4 Name="pior_value4" Value="00" /> + <cg_security5 Name="cg_security5" Value="00" /> + <cg_crc_area Name="cg_crc_area" Value="00" /> + <ocdstart Name="ocdstart" Value="17E00" /> + <cg_security3 Name="cg_security3" Value="00" /> + <cg_security0 Name="cg_security0" Value="00" /> + <pior_value5 Name="pior_value5" Value="00" /> + <cg_security1 Name="cg_security1" Value="00" /> + <pior_value1 Name="pior_value1" Value="20" /> + <wdt_option Name="wdt_option" Value="F9" /> + <clock_option Name="clock_option" Value="F8" /> + <cg_option Name="cg_option" Value="04" /> + <cg_security8 Name="cg_security8" Value="00" /> + <cg_security6 Name="cg_security6" Value="00" /> + <pior_value0 Name="pior_value0" Value="00" /> + <cg_security4 Name="cg_security4" Value="00" /> + <cg_security2 Name="cg_security2" Value="00" /> + <cg_iawctl_value Name="cg_iawctl_value" Value="00" /> + <lvi_option Name="lvi_option" Value="33" /> + <pior_value7 Name="pior_value7" Value="00" /> + </GlobleUserTag> + </TAG> + </DIR> + <MACRO> + <CGC Prepared="true" SetFlag="True" NeedRefresh="False"> + <CGC SetFlag="True" MacroName="cgc" /> + </CGC> + <PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"> + <PORT SetFlag="True" MacroName="PORT" /> + </PORT> + <INTC SetFlag="" HelpID="int" NeedRefresh="False"> + <INTP Accelerate="No" MacroName="INTP" TabEnable="True" /> + <KEY Chip="RL78F13_48pin,RL78F13_64pin" MacroName="KEY" TabEnable="True" /> + </INTC> + <Serial SetFlag="False" HelpID="serial" NeedRefresh="False"> + <SAU0 Accelerate="No" MacroName="SAU" Channel="0" SetFlag="False" TabEnable="True"> + <Channel0 UART="0" CSI="00" IIC="00" Channel="0" /> + <Channel1 Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0" UART="0" CSI="01" IIC="01" Channel="1" /> + </SAU0> + <SAU1 Accelerate="No" MacroName="SAU" Channel="1" PIOR42="0" Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" TabEnable="True"> + <Channel0 UART="1" CSI="10" IIC="10" Channel="0" /> + <Channel1 Chip="groupb,groupc2" PIOR43="0" UART="1" CSI="11" IIC="11" Channel="1" /> + </SAU1> + <IICA0 Accelerate="No" Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" MacroName="IICA" Channel="0" TabEnable="True" /> + </Serial> + <ADC SetFlag="True" HelpID="adc" NeedRefresh="False"> + <ADC SetFlag="True" MacroName="ADC" /> + </ADC> + <TAU SetFlag="True" HelpID="timer" NeedRefresh="False"> + <TAU0 Accelerate="No" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3,4,5,6,7" SetFlag="True" TabEnable="True" /> + <TAU1 Accelerate="No" Chip="groupb,groupc1,groupc2" MacroName="TAU" Channel="1" ChannelNum="0,1,2,3" SetFlag="False" TabEnable="True" /> + <TMRJ0 SetFlag="" MacroName="TMRJ" Channel="0" TabEnable="True" /> + <TMRD0 SetFlag="" MacroName="TMRD" Channel="0" TabEnable="True" /> + <TMRD1 SetFlag="" MacroName="TMRD" Channel="1" TabEnable="True" /> + </TAU> + <WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"> + <WDT SetFlag="True" MacroName="WDT" /> + </WDT> + <RTC SetFlag="False" HelpID="rtc" NeedRefresh="False"> + <RTC MacroName="RTC" SetFlag="False" /> + </RTC> + <DTC HelpID="dtc" SetFlag="" NeedRefresh="False"> + <DTC SetFlag="" /> + </DTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" SetFlag="False" HelpID="PCLBUZ" NeedRefresh="False"> + <PCLBUZ0 MacroName="PCLBUZ" Channel="0" SetFlag="False" /> + </PCLBUZ> + <LVD SetFlag="True" Prepared="true" NeedRefresh="False"> + <LVD MacroName="LVD" SetFlag="True" /> + </LVD> + </MACRO> + <SETTING> + <CGC> + <setting name="PIN_ASSIGNMENT_FIX_SETTING" value="false" /> + <setting name="OPERATION_MODE_HS_27_55" value="false" /> + <setting name="OPERATION_MODE_HS_40_55" value="true" /> + <setting name="MAIN_CLOCK_SELECT_HIGH_SYSTEM_CLOCK" value="false" /> + <setting name="MAIN_CLOCK_SELECT_HIGH_INTERNAL_CLOCK" value="true" /> + <setting name="INTERNAL_HIGH_CLOCK_OPERATION" value="true" /> + <setting name="INTERNAL_HIGH_CLOCK_FREQUENCY" value="8" /> + <setting name="HIGH_SYSTEM_CLOCK_OPERATION" value="false" /> + <setting name="HIGH_SYSTEM_CLOCK_SELECT_EXTERNAL_CLOCK" value="false" /> + <setting name="HIGH_SYSTEM_CLOCK_SELECT_X1_CLOCK" value="true" /> + <setting name="X1_CLOCK_STABLE_TIME" value="7" /> + <setting name="HIGH_SYSTEM_CLOCK_FREQUENCY" value="5" /> + <setting name="SUBCLOCK_SELECT_XT1_CLOCK" value="true" /> + <setting name="SUBCLOCK_XT1_OSCILLATION_MODE" value="0" /> + <setting name="SUBCLOCK_OPERATION" value="false" /> + <setting name="SUBCLOCK_SELECT_EXTERNAL_CLOCK" value="false" /> + <setting name="SUBCLOCK_HALT_STOP_STATUS" value="0" /> + <setting name="CPU_PERIPHERAL_CLOCK_FREQUENCY" value="0" /> + <setting name="FPLL_FREQUENCY_VALUE" value="0" /> + <setting name="FPLL_FREQUENCY_OPERATION" value="false" /> + <setting name="FPLL_LOCKUP_WAIT_COUNTER" value="0" /> + <setting name="FMP_FREQUENCY_VALUE" value="0" /> + <setting name="TRD_FREQUENCY_VALUE" value="0" /> + <setting name="FSL_FREQUENCY_VALUE" value="0" /> + <setting name="RTC_IT_CLOCK" value="0" /> + <setting name="OCD_UNUSED" value="true" /> + <setting name="OCD_USED" value="false" /> + <setting name="RRM_UNUSED" value="false" /> + <setting name="RRM_USED" value="true" /> + <setting name="TRACE_UNUSED" value="false" /> + <setting name="TRACE_USED" value="true" /> + <setting name="HOTPLUG_UNUSED" value="true" /> + <setting name="HOTPLUG_USED" value="false" /> + <setting name="SECURITY_ID_AUTHENTICATION_ERASE" value="true" /> + <setting name="SECURITY_ID_AUTHENTICATION_NOT_ERASE" value="false" /> + <setting name="SECURITY_ID_SELECT" value="true" /> + <setting name="SECURITY_ID_VALUE" value="0x00000000000000000000" /> + <setting name="RESET_SOURCE_FUNCTION_OUTPUT" value="true" /> + <setting name="RESOUT_UNUSED" value="true" /> + <setting name="RESOUT_USED" value="false" /> + <setting name="ILLEGAL_MEMORY_ACCESS_UNUSED" value="true" /> + <setting name="ILLEGAL_MEMORY_ACCESS_USED" value="false" /> + <setting name="RAM_GUARD_UNUSED" value="true" /> + <setting name="RAM_GUARD_USED" value="false" /> + <setting name="RAM_GUARD_AREA" value="0" /> + <setting name="PORT_GUARD_UNUSED" value="true" /> + <setting name="PORT_GUARD_USED" value="false" /> + <setting name="INTERRUPT_GUARD_UNUSED" value="true" /> + <setting name="INTERRUPT_GUARD_USED" value="false" /> + <setting name="CHIP_CONTROL_GUARD_UNUSED" value="true" /> + <setting name="CHIP_CONTROL_GUARD_USED" value="false" /> + <setting name="STACKPOINTER_INTERRUPT_PRIORITY" value="3" /> + <setting name="STACKPOINTER_INTERRUPT_USED" value="true" /> + <setting name="CLOCK_MONITOR_INTERRUPT_PRIORITY" value="3" /> + <setting name="CLOCK_MONITOR_INTERRUPT_USED" value="true" /> + <setting name="CLOCK_MONITOR_UNUSED" value="true" /> + <setting name="CLOCK_MONITOR_USED" value="false" /> + <setting name="STACK_POINTER_UNUSED" value="true" /> + <setting name="STACK_POINTER_USED" value="false" /> + <setting name="STACK_POINTER_UNDERFLOW_DATA" value="0x0000" /> + <setting name="STACK_POINTER_OVERFLOW_DATA" value="0xFFFE" /> + <setting name="RAM_ECC_INTERRUPT_USED" value="false" /> + <setting name="RAM_ECC_INTERRUPT_PRIORITY" value="3" /> + <setting name="DataFlash" value="unused" /> + <setting name="ProgramFlash" value="unused" /> + <setting name="Monitor" value="unused" /> + <setting name="StartStop" value="unused" /> + <setting name="Emulator" value="E1" /> + </CGC> + <PORT> + <PortP0> + <P00> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P00> + </PortP0> + <PortP1> + <P10> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P10> + <P11> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P11> + <P12> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P12> + <P13> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P13> + <P14> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P14> + <P15> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P15> + <P16> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P16> + <P17> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P17> + </PortP1> + <PortP3> + <P30> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P30> + <P31> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P31> + <P32> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P32> + <P33> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P33> + <P34> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P34> + </PortP3> + <PortP4> + <P40> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="true" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P40> + <P41> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P41> + </PortP4> + <PortP6> + <P60> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P60> + <P61> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P61> + <P62> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P62> + <P63> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P63> + </PortP6> + <PortP7> + <P70> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P70> + <P71> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P71> + <P72> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P72> + <P73> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P73> + </PortP7> + <PortP8> + <P80> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P80> + <P81> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P81> + <P82> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P82> + <P83> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P83> + <P84> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P84> + <P85> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P85> + <P86> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P86> + <P87> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P87> + </PortP8> + <PortP9> + <P90> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P90> + <P91> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P91> + <P92> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P92> + </PortP9> + <PortP12> + <P120> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P120> + <P121> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P121> + <P122> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P122> + <P123> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P123> + <P124> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P124> + <P125> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P125> + </PortP12> + <PortP13> + <P130> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P130> + <P137> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P137> + </PortP13> + <PortP14> + <P140> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P140> + </PortP14> + </PORT> + <TAU0> + <Channel0> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval0> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="-1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="-1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="unused" /> + </TAUInterval0> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval1> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="used" /> + </TAUInterval1> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + <Channel4> + <setting name="ChannelFunction" value="7" /> + <setting name="Pinselection" value="-1" /> + <TAUPWMMaster4> + <PWMMaster4> + <setting name="Value_scale" value="1" /> + <setting name="PWM_cycle" value="1000" /> + <setting name="Master_interrupt_priority" value="3" /> + <setting name="Master_interrupt" value="unused" /> + </PWMMaster4> + <PWMSlave5> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="unused" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave5> + <PWMSlave6> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="used" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave6> + <PWMSlave7> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="used" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave7> + </TAUPWMMaster4> + </Channel4> + <Channel5> + <setting name="ChannelFunction" value="9" /> + <setting name="Pinselection" value="-1" /> + </Channel5> + <Channel6> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel6> + <Channel7> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel7> + </TAU0> + <TAU1> + <Channel0> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + </TAU1> + <TMRJ0> + <setting name="Function" value="Unused" /> + </TMRJ0> + <TMRD0> + <setting name="Function" value="Unused" /> + </TMRD0> + <TMRD1> + <setting name="Function" value="Unused" /> + </TMRD1> + <SAU0> + <IIC00 /> + <CSI00 /> + <UART0 /> + <Channel0> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel0> + <IIC01 /> + <CSI01 /> + <Channel1> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel1> + </SAU0> + <SAU1> + <Channel0> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel0> + <UART1 /> + <Channel1> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel1> + <IIC10 /> + <CSI10 /> + <IIC11 /> + <CSI11 /> + </SAU1> + <IICA0> + <setting name="SLAVE_MODE_USED" value="false" /> + <setting name="MODULE_UNUSE" value="true" /> + <setting name="SINGLE_MASTER_USED" value="false" /> + </IICA0> + <ADC> + <setting name="ADC_USED" value="true" /> + <setting name="ADC_UNUSED" value="false" /> + <setting name="ADC_COMPARATOR_ENABLE" value="true" /> + <setting name="ADC_COMPARATOR_DISABLE" value="false" /> + <setting name="ADC_RESOLUTION_10BIT" value="true" /> + <setting name="ADC_RESOLUTION_8BIT" value="false" /> + <setting name="ADC_POSITIVE_VDD" value="true" /> + <setting name="ADC_POSITIVE_AVREFP" value="false" /> + <setting name="ADC_POSITIVE_BGR" value="false" /> + <setting name="ADC_NEGATIVE_VSS" value="true" /> + <setting name="ADC_NEGATIVE_AVREFM" value="false" /> + <setting name="ADC_TRIGGER_SOFTWARE" value="false" /> + <setting name="ADC_TRIGGER_HARDWARE_NOWAIT" value="true" /> + <setting name="ADC_TRIGGER_HARDWARE_WAIT" value="false" /> + <setting name="ADC_TRIGGER_SOURCE_UPDATE" value="0" /> + <setting name="ADC_CONTINUOUS_SELECT_MODE" value="true" /> + <setting name="ADC_ONESHOT_SELECT_MODE" value="false" /> + <setting name="ADC_CONTINUOUS_SCAN_MODE" value="false" /> + <setting name="ADC_ONESHOT_SCAN_MODE" value="false" /> + <setting name="ADC_ANALOG_INPUT_SELECTION" value="9" /> + <setting name="ANALOG_INPUT_24" value="false" /> + <setting name="ANALOG_INPUT_25" value="false" /> + <setting name="ANALOG_INPUT_26" value="true" /> + <setting name="ADC_CONVERSION_MODE" value="0" /> + <setting name="ADC_CONVERSION_TIME" value="0" /> + <setting name="ADC_INTERRUPT_GENERATE_CONDITION_1" value="true" /> + <setting name="ADC_INTERRUPT_GENERATE_CONDITION_2" value="false" /> + <setting name="ADC_UPPER_BOUND_VALUE" value="255" /> + <setting name="ADC_LOWER_BOUND_VALUE" value="0" /> + <setting name="ADC_INTERRUPT_PRIORITY" value="3" /> + <setting name="ADC_INTERRUPT_USED" value="true" /> + <setting name="ANALOG_INPUT_30" value="true" /> + <setting name="ANALOG_INPUT_29" value="true" /> + <setting name="ANALOG_INPUT_28" value="true" /> + <setting name="ANALOG_INPUT_27" value="true" /> + <setting name="ADC_CHANNEL_SELECTION" value="0" /> + </ADC> + <WDT> + <setting name="WDT_MODULE_USED" value="true" /> + <setting name="WDT_MODULE_UNUSE" value="false" /> + <setting name="WDT_OVERFLOW_TIME" value="4" /> + <setting name="WDT_WINDOW_OPEN_TIME" value="2" /> + <setting name="WDT_HALT_STOP_OPERATION_ENABLE" value="true" /> + <setting name="WDT_HALT_STOP_OPERATION_STOP" value="false" /> + <setting name="WDT_INTERRUPT_USED" value="true" /> + <setting name="WDT_INTERRUPT_PRIORITY" value="3" /> + </WDT> + <RTC> + <setting name="INITIAL_VALUE" value="01/01/2000 00:00:00" /> + <setting name="ALARM_WEEK_DAY" value="Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_" /> + <setting name="ALARM_TIME" value="01/01/2000 00:00:00" /> + <setting name="MODULE_USED" value="false" /> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="ALARM_OPERATION_USED" value="false" /> + <setting name="HOUR_SYSTEM" value="0" /> + <setting name="INITIAL_VALUE_USED" value="false" /> + <setting name="ALARM_VALUE_USED" value="false" /> + <setting name="INTERRUPT_PRIORITY" value="3" /> + <setting name="CONSTANT_INTERRUPT_USED" value="false" /> + <setting name="CONSTANT_INTERRUPT_VALUE" value="0" /> + <setting name="ALARM_INTERRUPT_USED" value="true" /> + <setting name="RTC1HZ_OUTPUT_USED" value="false" /> + <setting name="RTC1HZ_OUTPUTPIN_SEL" value="-1" /> + </RTC> + <PCLBUZ0> + <setting name="PCLBUZ_clock" value="16000 (fMAIN/2^2)(kHZ)" /> + <setting name="PCLBUZ_USED" value="false" /> + <setting name="PCLBUZ_UNUSED" value="true" /> + <setting name="PCLBUZ_OUTPUT_CLOCK" value="0" /> + <setting name="PCLBUZ_PSRSEL_USE" value="false" /> + </PCLBUZ0> + <LVD> + <setting name="Operation" value="used" /> + <setting name="Reset_only_level" value="3" /> + <setting name="InterruptReset_level" value="0" /> + <setting name="Interrupt_level" value="0" /> + <setting name="Interrupt_only_level" value="0" /> + <setting name="operation_mode" value="reset" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="Interrupt_only_priority" value="3" /> + </LVD> + </SETTING> +</RL78F13> + 1.0 + 9f0a5b27-2465-47e7-adea-895ce294b875 + 459ade49-d7bc-4bb4-84e4-942e057b7504 + + + + + 9.07.00.00 + + + \ No newline at end of file diff --git a/app/BCZT.rcpe b/app/BCZT.rcpe new file mode 100644 index 0000000..c808a09 --- /dev/null +++ b/app/BCZT.rcpe @@ -0,0 +1,2447 @@ + + + + + % + % + + + + cstart.asm + stkinit.asm + iodefine.h + + r_main.c + r_systeminit.c + r_cg_cgc.c + r_cg_cgc_user.c + r_cg_timer.c + r_cg_timer_user.c + r_cg_macrodriver.h + r_cg_userdefine.h + r_cg_cgc.h + r_cg_timer.h + r_cg_port.c + r_cg_port_user.c + r_cg_adc.c + r_cg_adc_user.c + r_cg_port.h + r_cg_adc.h + r_cg_wdt.c + r_cg_wdt_user.c + r_cg_wdt.h + + + RLIN_driver\RLIN_driver.c + RLIN_driver\RLIN_driver_user.c + RLIN_driver\RLIN_user.c + + + user\appTask.c + user\hwCtrl.c + user\MotorCtrl.c + + + DataFlash\r_pfdl.c + + + + + 0 + + + + R5F10AGF + + + + DefaultBuild\cstart.obj + DefaultBuild\stkinit.obj + DefaultBuild\r_main.obj + DefaultBuild\r_systeminit.obj + DefaultBuild\r_cg_cgc.obj + DefaultBuild\r_cg_cgc_user.obj + DefaultBuild\r_cg_timer.obj + DefaultBuild\r_cg_timer_user.obj + DefaultBuild\r_cg_port.obj + DefaultBuild\r_cg_port_user.obj + DefaultBuild\r_cg_adc.obj + DefaultBuild\r_cg_adc_user.obj + DefaultBuild\RLIN_driver.obj + DefaultBuild\RLIN_driver_user.obj + DefaultBuild\RLIN_user.obj + DefaultBuild\appTask.obj + DefaultBuild\hwCtrl.obj + DefaultBuild\MotorCtrl.obj + DefaultBuild\r_pfdl.obj + DefaultBuild\r_cg_wdt.obj + DefaultBuild\r_cg_wdt_user.obj + + + . + RLIN_driver + user + DataFlash + + + False + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + None + + + + + <RL78F13> + <VAR> + <fCLK Name="fCLK" Value="32" Comment="4M" Trigger="fCLK"> + <Effect> + <ADC /> + <SAU0 /> + <SAU1 /> + <IICA0 /> + <TAU0 /> + <TAU1 /> + <TMRJ0 /> + </Effect> + </fCLK> + <ISPullupForPort Name="ISPullupForPort" Text="P00-P10-P11-P12-P13-P14-P15-P16-P17-P30-P31-P32-P40-P41-P60-P61-P62-P63-P70-P71-P72-P73-P120-P125-P140-" Comment="unused" /> + <fHOCO Name="fHOCO" Value="64" Comment="64M" Trigger="fHOCO" /> + <fIH Name="fIH" Value="64" Comment="32M" /> + <fSUB Name="fSUB" Value="0" Comment="0K" Trigger="fSUB"> + <Effect> + <TAU0 /> + <TAU1 /> + <TMRJ0 /> + </Effect> + </fSUB> + <fIL Name="fIL" Value="15" Comment="15K" Trigger="fIL"> + <Effect> + <TMRJ0 /> + <WDT /> + <TAU0 /> + <TAU1 /> + </Effect> + </fIL> + <fSL Name="fSL" Value="15" Comment="15K" Trigger="fSL"> + <Effect> + <PCLBUZ0 /> + <TMRJ0 /> + <TAU0 /> + <TAU1 /> + </Effect> + </fSL> + <fPLL Name="fPLL" Value="24" Comment="24M" Trigger="fPLL" /> + <fRTC Name="fRTC" Value="524.590163934426" Comment="15k" Trigger="fRTC"> + <Effect> + <RTC /> + </Effect> + </fRTC> + <fTRD Name="fTRD" Value="64" Comment="64M" Trigger="fTRD"> + <Effect> + <TMRD0 /> + <TMRD1 /> + </Effect> + </fTRD> + <fMAIN Name="fMAIN" Value="64" Comment="32M" Trigger="fMAIN"> + <Effect> + <PCLBUZ0 /> + </Effect> + </fMAIN> + <fTRDSource Name="fTRDSource" Trigger="fTRD" Text="fIH" /> + <VDD_MIN Name="VDD_MIN" Value="4" Comment="4.0V" Trigger="VDD"> + <Effect> + <PCLBUZ0 /> + <IICA0 /> + <SAU0 /> + <SAU1 /> + </Effect> + </VDD_MIN> + <VDD_MAX Name="VDD_MAX" Value="5.5" Comment="5.5V" /> + <VDD Name="VDD" Text="false" Comment="used" /> + <VDDValue Name="VDDValue" Value="2.7" Comment="2.7V" Trigger="VDD"> + <Effect> + <ADC /> + </Effect> + </VDDValue> + <AD_ADPC_USEDPIN Name="AD_ADPC_USEDPIN" Text="ANI0,ANI1,ANI2,ANI3," /> + <AD_ADS_USEDPIN Name="AD_ADS_USEDPIN" Text="ANI0," /> + <ADPCForPort3 Name="ADPCForPort3" Value="255" Comment="ADPCForPort3" /> + <ADPCForPort8 Name="ADPCForPort8" Value="5" Comment="ADPCForPort8" /> + <ADPCForPort9 Name="ADPCForPort9" Value="12" Comment="ADPCForPort9" /> + <ADPCForKey Name="ADPCForKey" Value="255" Comment="ADPCForKey" /> + <OnChipDebugTraceDTC Name="GTraceRam" Text="0" Trigger="ocdtraceram"> + <Effect> + <DTC /> + </Effect> + </OnChipDebugTraceDTC> + <OnChipDebugTrace Name="GTrace" Text="1" /> + <OnChipDebugHotPlugDTC Name="GHotPlugRam" Text="0" Trigger="ocdhotplugram"> + <Effect> + <DTC /> + </Effect> + </OnChipDebugHotPlugDTC> + <KR0 Name="KR0" Text="false" Comment="unused" Trigger="KR0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR0> + <KR1 Name="KR1" Text="false" Comment="unused" Trigger="KR1"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR1> + <KR2 Name="KR2" Text="false" Comment="unused" Trigger="KR2"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR2> + <KR3 Name="KR3" Text="false" Comment="unused" Trigger="KR3"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR3> + <KR4 Name="KR4" Text="false" Comment="unused" Trigger="KR4"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR4> + <KR5 Name="KR5" Text="false" Comment="unused" Trigger="KR5"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR5> + <KR6 Name="KR6" Text="false" Comment="unused" Trigger="KR6"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR6> + <KR7 Name="KR7" Text="false" Comment="unused" Trigger="KR7"> + <Effect> + <PORT Forcible="" /> + </Effect> + </KR7> + <OnChipDebugHotPlug Name="GHotPlug" Text="1" /> + <IIC00 Name="IIC00" Text="false" Comment="unused" Trigger="IIC00"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC00> + <IIC01 Name="IIC01" Text="false" Comment="unused" Trigger="IIC01"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC01> + <IIC10 Name="IIC10" Text="false" Comment="unused" Trigger="IIC10"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC10> + <IIC11 Name="IIC11" Text="false" Comment="unused" Trigger="IIC11"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IIC11> + <IICA0 Name="IICA0" Text="false" Comment="unused" Trigger="IICA0"> + <Effect> + <PORT Forcible="" /> + </Effect> + </IICA0> + <PIOR00Value Name="PIOR00Value" Text="0" /> + <PIOR01Value Name="PIOR01Value" Text="0" /> + <PIOR02Value Name="PIOR02Value" Text="0" /> + <PIOR03Value Name="PIOR03Value" Text="0" /> + <PIOR04Value Name="PIOR04Value" Text="0" /> + <PIOR05Value Name="PIOR05Value" Text="0" /> + <PIOR06Value Name="PIOR06Value" Text="0" /> + <PIOR07Value Name="PIOR07Value" Text="0" /> + <PIOR10Value Name="PIOR10Value" Text="0" /> + <PIOR11Value Name="PIOR11Value" Text="0" /> + <PIOR12Value Name="PIOR12Value" Text="0" /> + <PIOR13Value Name="PIOR13Value" Text="0" /> + <PIOR14Value Name="PIOR14Value" Text="0" /> + <PIOR15Value Name="PIOR15Value" Text="1" /> + <PIOR16Value Name="PIOR16Value" Text="0" /> + <PIOR17Value Name="PIOR17Value" Text="0" /> + <PIOR20Value Name="PIOR20Value" Text="0" /> + <PIOR21Value Name="PIOR21Value" Text="0" /> + <PIOR22Value Name="PIOR22Value" Text="0" /> + <PIOR23Value Name="PIOR23Value" Text="0" /> + <PIOR24Value Name="PIOR24Value" Text="0" /> + <PIOR25Value Name="PIOR25Value" Text="0" /> + <PIOR26Value Name="PIOR26Value" Text="0" /> + <PIOR27Value Name="PIOR27Value" Text="0" /> + <PIOR30Value Name="PIOR30Value" Text="0" /> + <PIOR31Value Name="PIOR31Value" Text="0" /> + <PIOR32Value Name="PIOR32Value" Text="0" /> + <PIOR33Value Name="PIOR33Value" Text="0" /> + <PIOR34Value Name="PIOR34Value" Text="0" /> + <PIOR35Value Name="PIOR35Value" Text="0" /> + <PIOR36Value Name="PIOR36Value" Text="0" /> + <PIOR37Value Name="PIOR37Value" Text="0" /> + <PIOR40Value Name="PIOR40Value" Text="0" /> + <PIOR41Value Name="PIOR41Value" Text="0" /> + <PIOR42Value Name="PIOR42Value" Text="0" /> + <PIOR43Value Name="PIOR43Value" Text="0" /> + <PIOR44Value Name="PIOR44Value" Text="0" /> + <PIOR45Value Name="PIOR45Value" Text="0" /> + <PIOR46Value Name="PIOR46Value" Text="0" /> + <PIOR50Value Name="PIOR50Value" Text="0" /> + <PIOR52Value Name="PIOR52Value" Text="0" /> + <PIOR53Value Name="PIOR53Value" Text="0" /> + <PIOR60Value Name="PIOR60Value" Text="0" /> + <PIOR61Value Name="PIOR61Value" Text="0" /> + <PIOR62Value Name="PIOR62Value" Text="0" /> + <PIOR63Value Name="PIOR63Value" Text="0" /> + <PIOR64Value Name="PIOR64Value" Text="0" /> + <PIOR65Value Name="PIOR65Value" Text="0" /> + <PIOR66Value Name="PIOR66Value" Text="0" /> + <PIOR67Value Name="PIOR67Value" Text="0" /> + <PIOR70Value Name="PIOR70Value" Text="0" /> + <PIOR71Value Name="PIOR71Value" Text="0" /> + <PIOR73Value Name="PIOR73Value" Text="0" /> + <RTC1HZ Name="RTC1HZ" Text="disable" Trigger="RTC1HZ"> + <Effect> + <TAU0 /> + <TAU1 /> + </Effect> + </RTC1HZ> + <RXD0 Name="RXD0" Text="disable" /> + <ProjectName Name="PrjName" Text="BCZT" /> + <ProjectPath Name="PrjPath" Text="F:\FCB_project\temp\M26\BCZT" /> + <ProjectKind Name="PrjKind" Text="Project78K0R" /> + <DeviceName Name="DeviceName" Fixed="" Text="RL78F13" /> + <MCUName Name="MCUName" Text="RL78F13_48pin" /> + <ChipName Name="ChipName" Text="R5F10AGF" /> + <ChipID Name="ChipID" Text="R5F10AGF" /> + <CPUCoreType Name="CPUCoreType" Fixed="" Text="1" /> + <MCUType Name="MCUType" Fixed="" Text="RL78" /> + <Compiler Name="Compiler" Text="CCRL" /> + <UseSecurityId Name="GI" Text="0" /> + <SecurityId Name="GIValue" Text="00000000000000000000" /> + <LinkDirectiveFile Name="D0" Text="lk.dr" /> + <OnChipDebugOptionBytes Name="GO" Text="1" /> + <OnChipDebugOptionBytesValue Name="GOValue" Text="04" /> + <StartAddressOfOnChipDebugOptionBytes Name="GOStart" Text="17E00" /> + <SizeOfOnChipDebugOptionBytesArea Name="GOSizeValue" Text="512" /> + <UserOptionBytes Name="GB" Text="1" /> + <UserOptionBytesValue Name="GBValue" Text="F933F8" /> + <RAMStartAddress Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="RAMStartAddress" Fixed="" Text="000FE700" /> + <RAMEndAddress Name="RAMEndAddress" Fixed="" Text="000FFEFF" /> + <ROMEndAddress Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="ROMEndAddress" Fixed="" Text="00017FFF" /> + <MirrorROM Chip="R5F10AGF,R5F10ALF,R5F10AMF,R5F10BAF,R5F10BBF,R5F10BGF,R5F10BLF,R5F10BMF" Name="MirrorROM" Fixed="" Text="47.75" /> + <TAUUsedRTC1Hz Name="TAUUsedRTC1Hz" Text="false" Comment="unused" Trigger="RTC1HZ"> + <Effect> + <RTC /> + </Effect> + </TAUUsedRTC1Hz> + <TRDCLKUSE1 Name="TRDCLKUSE1" Value="0" Comment="unused" Trigger="TRDCLK input"> + <Effect> + <TMRD0 /> + </Effect> + </TRDCLKUSE1> + <fMP Name="fMP" Value="64" /> + <GroupName Name="GroupName" Text="groupb" /> + <CodePath Name="CodePath" Text=".\" /> + <ReportType Name="ReportType" Text="Html" /> + <CreationDateType Name="CreationDateType" Text="OutputDate" /> + <GenerateType Name="GenerateType" Text="Merge" /> + <APIOutputType Name="APIOutputType" Text="Default" /> + <FileRegister Name="FileRegister" Text="Yes" /> + <PinReflect Name="PinReflect" Text="Reflected" /> + <fCLKSource Name="fCLKSource" Text="fIH" /> + <UseFDL Name="UseFDL" Text="no" /> + <DataFlash Name="DataFlash" Text="0" /> + <OCDROM Name="OCDROM" Text="Unused" /> + <OCDROM_Address Name="OCDROM_Address" Text="00017E00" /> + <OCDROM_Length Name="OCDROM_Length" Text="512" /> + <PrjVersion Name="PrjVersion" Text="1.2.0.1" /> + <ProductVersion Name="ProductVersion" Text="4.08.05.01" /> + <ADPCForPort0 Name="ADPCForPort0" Value="255" /> + <ADPCForPort1 Name="ADPCForPort1" Value="255" /> + <ADPCForPort4 Name="ADPCForPort4" Value="255" /> + <ADPCForPort6 Name="ADPCForPort6" Value="255" /> + <ADPCForPort7 Name="ADPCForPort7" Value="255" /> + <ADPCForPort12 Name="ADPCForPort12" Value="255" /> + <ADPCForPort13 Name="ADPCForPort13" Value="255" /> + <ADPCForPort14 Name="ADPCForPort14" Value="255" /> + <TRDCLKTag Name="TRDCLKTag" Value="-1" /> + <TRDCLKUSE0 Name="TRDCLKUSE0" Value="0" /> + <RTC1HZ_Used Name="RTC1HZ_Used" Value="0" /> + <TO02_PWM Name="TO02_PWM" Text="false" /> + <TO03_PWM Name="TO03_PWM" Text="false" /> + <Ch3UseTI03 Name="Ch3UseTI03" Text="false" /> + <Ch4UseTI03 Name="Ch4UseTI03" Text="false" /> + <Ch5UseTI03 Name="Ch5UseTI03" Text="false" /> + <INPT0USE0 Name="INPT0USE0" Text="false" /> + <TRDINTP0LINK0 Name="TRDINTP0LINK0" Text="false" /> + <TRDIOC1_PWM Name="TRDIOC1_PWM" Text="false" /> + <TRDIOD1_PWM Name="TRDIOD1_PWM" Text="false" /> + <INPT0USE1 Name="INPT0USE1" Text="false" /> + <TRDINTP0LINK1 Name="TRDINTP0LINK1" Text="false" /> + <LinkFileName Name="LinkFileName" Text="" /> + </VAR> + <DIR> + <PIN> + <CGC> + <X1 Port="P121" Point="-" /> + <X2 Port="P122" Point="-" /> + <EXCLK Port="P122" Point="I" /> + <XT1 Chip="RL78F13_48pin,RL78F13_64pin" Port="P123" Point="-" /> + <XT2 Chip="RL78F13_48pin,RL78F13_64pin" Port="P124" Point="-" /> + <EXCLKS Chip="RL78F13_48pin,RL78F13_64pin" Port="P124" Point="I" /> + <TOOL0 Port="P40" Point="I/O" /> + <RESOUT Port="P130" Point="O" /> + </CGC> + <PORT> + <Port0 Chip="RL78F13_48pin,RL78F13_64pin" Pullup="true"> + <P00 Name="P00/TI05/TO05/INTP9" AltFunc="TO05" Point="I/O" /> + </Port0> + <Port1 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Pullup="true"> + <P10 Name="P10/TI13/TO13/TRJO0/_SCK10/SCL10/LTXD1/CTXD0" Chip="groupb,groupc1,groupc2" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P11 Name="P11/TI12/TO12/TRDIOB0/SI10/SDA10/RXD1/LRXD1/CRXD0" Chip="groupb,groupc1,groupc2" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P12 Name="P12/TI11/TO11/TRDIOD0/INTP5/SO10/TXD1/SNZOUT3" Chip="groupb,groupc1,groupc2" Nch="true" AltFunc="" Point="I/O" /> + <P13 Name="P13/TI04/TO04/TRDIOA0/TRDCLK0/SI01/SDA01/LTXD0" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P14 Name="P14/TI06/TO06/TRDIOC0/_SCK01/SCL01/LRXD0" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P15 Name="P15/TI05/TO05/TRDIOA1/TRDIOA0/TRDCLK0/SO00/TXD0/TOOLTXD/RTC1HZ" Nch="true" AltFunc="" Point="I/O" /> + <P16 Name="P16/TI02/TO02/TRDIOC1/SI00/SDA00/RXD0/TOOLRXD" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + <P17 Name="P17/TI00/TO00/TRDIOB1/_SCK00/SCL00/INTP3" TTL="true" PITHL="true" Nch="true" AltFunc="" Point="I/O" /> + </Port1> + <Port3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P30 Name="P30/TI01/TO01/TRDIOD1/_SSI00/INTP2/SNZOUT0" TTL="true" PITHL="true" Pullup="true" AltFunc="P30" Point="I/O" /> + <P31 Name="P31/TI14/TO14/STOPST/INTP2" Pullup="true" AltFunc="" Point="I/O" /> + <P32 Name="P32/TI16/TO16/INTP7" Pullup="true" AltFunc="P32" Point="I/O" /> + <P33 Name="P33/AVREFP/ANI00" AltFunc="ANI0" Point="I/O" /> + <P34 Name="P34/AVREFM/ANI01" AltFunc="ANALOG_1" Point="I/O" /> + </Port3> + <Port4 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin" Pullup="true"> + <P40 Name="P40/TOOL0" AltFunc="" Point="I/O" /> + <P41 Name="P41/TI10/TO10/TRJIO0/VCOUT0/SNZOUT2" AltFunc="" Point="I/O" /> + </Port4> + <Port6 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin" Pullup="true"> + <P60 Name="P60/_SCK00/SCL00" PITHL="true" Nch="true" AltFunc="P60" Point="I/O" /> + <P61 Name="P61/SI00/SDA00/RXD0" PITHL="true" Nch="true" AltFunc="P61" Point="I/O" /> + <P62 Name="P62/SO00/TXD0/SCLA0" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" PITHL="true" Nch="true" TTL="true" AltFunc="P62" Point="I/O" /> + <P63 Name="P63/_SSI00/SDAA0" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" TTL="true" PITHL="true" Nch="true" AltFunc="P63" Point="I/O" /> + </Port6> + <Port7 Chip="RL78F13_48pin" Pullup="true"> + <P70 Name="P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" Nch="true" AltFunc="P70" Point="I/O" /> + <P71 Name="P71/ANI27/KR1/TI17/TO17/INTP6/_SCK11/SCL11/SNZOUT5" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" Nch="true" AltFunc="P71" Point="I/O" /> + <P72 Name="P72/ANI28/KR2/CTXD0/SO11/SNZOUT6" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" Nch="true" AltFunc="P72" Point="I/O" /> + <P73 Name="P73/ANI29/KR3/CRXD0/_SSI11/SNZOUT7" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" TTL="true" PITHL="true" AltFunc="P73" Point="I/O" /> + </Port7> + <Port8 Chip="RL78F13_30pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P80 Name="P80/ANI02/ANO0" AltFunc="ANALOG_2" Point="I/O" /> + <P81 Name="P81/ANI03/IVCMP00" AltFunc="ANALOG_3" Point="I/O" /> + <P82 Name="P82/ANI04/IVCMP01" AltFunc="P82" Point="I/O" /> + <P83 Name="P83/ANI05/IVCMP02" AltFunc="P83" Point="I/O" /> + <P84 Name="P84/ANI06/IVCMP03" AltFunc="P84" Point="I/O" /> + <P85 Name="P85/ANI07/IVREF0" AltFunc="P85" Point="I/O" /> + <P86 Name="P86/ANI08" AltFunc="P86" Point="I/O" /> + <P87 Name="P87/ANI09" AltFunc="P87" Point="I/O" /> + </Port8> + <Port9 Chip="RL78F13_48pin"> + <P90 Name="P90/ANI10" AltFunc="" Point="I/O" /> + <P91 Name="P91/ANI11" AltFunc="P91" Point="I/O" /> + <P92 Name="P92/ANI12" Chip="R5F10AGF,R5F10AGG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" AltFunc="P92" Point="I/O" /> + </Port9> + <Port12 Chip="RL78F13_48pin,RL78F13_64pin"> + <P120 Name="P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" DIN="true" Nch="true" Pullup="true" AltFunc="P120" Point="I/O" /> + <P121 Name="P121/X1" AltFunc="" Point="I" /> + <P122 Name="P122/X2/EXCLK" AltFunc="" Point="I" /> + <P123 Name="P123/XT1" AltFunc="" Point="I" /> + <P124 Name="P124/XT2/EXCLKS" AltFunc="" Point="I" /> + <P125 Name="P125/ANI24/TI03/TO03/TRDIOB0/_SSI01/INTP1/SNZOUT1" Chip="R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG" DIN="true" TTL="true" PITHL="true" Pullup="true" AltFunc="P125" Point="I/O" /> + </Port12> + <Port13 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <P130 Name="P130/RESOUT" AltFunc="P130" Point="O" /> + <P137 Name="P137/INTP0" AltFunc="" Point="I" /> + </Port13> + <Port14 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Pullup="true"> + <P140 Name="P140/PCLBUZ0" AltFunc="P140" Point="I/O" /> + </Port14> + </PORT> + <INTC> + <INTP> + <INTP0 Port="P137" Point="I" /> + <INTP1 Port="P125" Point="I" /> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR52="0" Port="P30" Point="I" /> + <INTP3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" Port="P17" Point="I" /> + <INTP4 Port="P120" Point="I" /> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P12" Point="I" /> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P71" Point="I" /> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" Port="P32" Point="I" /> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" Port="P70" Point="I" /> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" Port="P00" Point="I" /> + </INTP> + <KEY> + <KR0 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P70" Point="I" /> + <KR1 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P71" Point="I" /> + <KR2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P72" Point="I" /> + <KR3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR50="0" Port="P73" Point="I" /> + </KEY> + </INTC> + <ADC> + <ANI0 Port="P33" Point="I" /> + <ANI1 Port="P34" Point="I" /> + <ANI2 Port="P80" Point="I" /> + <ANI3 Port="P81" Point="I" /> + <ANI4 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P82" Point="I" /> + <ANI5 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P83" Point="I" /> + <ANI6 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P84" Point="I" /> + <ANI7 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P85" Point="I" /> + <ANI8 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P86" Point="I" /> + <ANI9 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P87" Point="I" /> + <ANI10 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P90" Point="I" /> + <ANI11 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P91" Point="I" /> + <ANI12 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin" Port="P92" Point="I" /> + <ANI24 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin, R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG, R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG" Port="P125" Point="I" /> + <ANI25 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin, R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG, R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG" Port="P120" Point="I" /> + <AVREFP Port="P33" Point="I" /> + <AVREFM Port="P34" Point="I" /> + <ANALOG_0 Port="P33" Point="I" RealName="ANI0" /> + <ANALOG_1 Port="P34" Point="I" RealName="ANI1" /> + <ANALOG_2 Port="P80" Point="I" RealName="ANI2" /> + <ANALOG_3 Port="P81" Point="I" RealName="ANI3" /> + <ANALOG_4 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P82" Point="I" RealName="ANI4" /> + <ANALOG_5 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P83" Point="I" RealName="ANI5" /> + <ANALOG_6 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P84" Point="I" RealName="ANI6" /> + <ANALOG_7 Chip="RL78F13_30pin, RL78F13_32pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P85" Point="I" RealName="ANI7" /> + <ANALOG_8 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P86" Point="I" RealName="ANI8" /> + <ANALOG_9 Chip="RL78F13_30pin, RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P87" Point="I" RealName="ANI9" /> + <ANALOG_10 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P90" Point="I" RealName="ANI10" /> + <ANALOG_11 Chip="RL78F13_48pin, RL78F13_64pin, RL78F13_80pin" Port="P91" Point="I" RealName="ANI11" /> + <ANALOG_12 Chip="R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG, R5F10AGF, R5F10AGG, R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG, R5F10ALF, R5F10ALG, RL78F13_80pin" Port="P92" Point="I" RealName="ANI12" /> + </ADC> + <Serial> + <SAU0> + <UART0> + <RXD0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="I" /> + <TXD0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P15" Point="O" /> + </UART0> + <CSI00> + <SO00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P15" Point="O" /> + <SI00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="I" /> + <SCK00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" RealName="_SCK00" Port="P17" Point="I/O" /> + <SSI00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" RealName="_SSI00" Port="P30" Point="I" /> + </CSI00> + <CSI01> + <SO01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P120" Point="O" /> + <SI01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P13" Point="I" /> + <SCK01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P14" RealName="_SCK01" Point="I/O" /> + <SSI01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" RealName="_SSI01" Port="P125" Point="I" /> + </CSI01> + <IIC00> + <SCL00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P17" Point="O" CheckNch="true" /> + <SDA00 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR40="0" Port="P16" Point="O" CheckNch="true" /> + </IIC00> + <IIC01> + <SCL01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P14" Point="O" CheckNch="true" /> + <SDA01 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR41="0" Port="P13" Point="O" CheckNch="true" /> + </IIC01> + </SAU0> + <SAU1> + <UART1> + <RXD1 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="I" /> + <TXD1 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P12" Point="O" /> + </UART1> + <CSI10> + <SO10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P12" Point="O" /> + <SI10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="I" /> + <SCK10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P10" RealName="_SCK10" Point="I/O" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG"> + <SO11 PIOR43="0" Port="P72" Point="O" /> + <SI11 PIOR43="0" Port="P70" Point="I" /> + <SCK11 PIOR43="0" Port="P71" RealName="_SCK11" Point="I/O" /> + <SSI11 PIOR43="0" RealName="_SSI11" Port="P73" Point="I" /> + </CSI11> + <IIC10> + <SCL10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P10" Point="O" CheckNch="true" /> + <SDA10 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG" PIOR42="0" Port="P11" Point="O" CheckNch="true" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG"> + <SCL11 PIOR43="0" Port="P71" Point="O" CheckNch="true" /> + <SDA11 PIOR43="0" Port="P70" Point="O" CheckNch="true" /> + </IIC11> + </SAU1> + <IICA0> + <SCLA0 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" Port="P62" Point="I/O" /> + <SDAA0 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" Port="P63" Point="I/O" /> + </IICA0> + </Serial> + <TAU> + <TAU0> + <Channel0> + <TI00 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR00="0" Port="P17" Point="I" /> + <TO00 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR10="0" Port="P17" Point="O" /> + </Channel0> + <Channel1> + <TI01 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR01="0" Port="P30" Point="I" /> + <TO01 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR11="0" Port="P30" Point="O" /> + </Channel1> + <Channel2> + <TI02 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR02="0" Port="P16" Point="I" /> + <TO02 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR12="0" Port="P16" Point="O" /> + </Channel2> + <Channel3> + <TI03 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR03="0" Port="P125" Point="I" /> + <TO03 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR13="0" Port="P125" Point="O" /> + </Channel3> + <Channel4> + <TI04 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR04="0" Port="P13" Point="I" /> + <TO04 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR14="0" Port="P13" Point="O" /> + </Channel4> + <Channel5> + <TI05 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR05="0" Port="P15" Point="I" /> + <TO05 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR15="1" Port="P00" Point="O" /> + </Channel5> + <Channel6> + <TI06 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR06="0" Port="P14" Point="I" /> + <TO06 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR16="0" Port="P14" Point="O" /> + </Channel6> + <Channel7> + <TI07 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR07="0" Port="P120" Point="I" /> + <TO07 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR17="0" Port="P120" Point="O" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <Channel0> + <TI10 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P41" Point="I" /> + <TO10 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P41" Point="O" /> + </Channel0> + <Channel1> + <TI11 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P12" Point="I" /> + <TO11 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P12" Point="O" /> + </Channel1> + <Channel2> + <TI12 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P11" Point="I" /> + <TO12 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P11" Point="O" /> + </Channel2> + <Channel3> + <TI13 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P10" Point="I" /> + <TO13 Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" Port="P10" Point="O" /> + </Channel3> + </TAU1> + <TMRJ0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin,RL78F13_30pin"> + <TRJIO0 Port="P41" Point="I/O" /> + <TRJO0 Port="P10" Point="O" /> + </TMRJ0> + <TMRD0> + <TRDCLK_P13_0 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_1" RealName="TRDCLK0" /> + <TRDIOA0_P13 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_0" RealName="TRDIOA0" /> + <TRDIOB0_P125 PIOR71="0" Port="P125" Point="I/O" RealName="TRDIOB0" /> + <TRDIOC0_P14 Port="P14" Point="I/O" RealName="TRDIOC0" /> + <TRDIOD0_P120 PIOR73="0" Port="P120" Point="I/O" RealName="TRDIOD0" /> + <TRDIOA1_P15_0 Port="P15" Point="I/O" UnConflict="TRDIOA1_P15" RealName="TRDIOA1" /> + <TRDIOB1_P17_0 Port="P17" Point="I/O" UnConflict="TRDIOB1_P17" RealName="TRDIOB1" /> + <TRDIOC1_P16_0 Port="P16" Point="I/O" UnConflict="TRDIOC1_P16" RealName="TRDIOC1" /> + <TRDIOD1_P30_0 Port="P30" Point="I/O" UnConflict="TRDIOD1_P30" RealName="TRDIOD1" /> + </TMRD0> + <TMRD1> + <TRDCLK_P13_1 PIOR70="0" Port="P13" Point="I/O" UnConflict="TRDCLK_P13_0,TRDIOA0_P13" RealName="TRDCLK0" /> + <TRDIOA1_P15 Port="P15" Point="I/O" UnConflict="TRDIOA1_P15_0" RealName="TRDIOA1" /> + <TRDIOB1_P17 Port="P17" Point="I/O" UnConflict="TRDIOB1_P17_0" RealName="TRDIOB1" /> + <TRDIOC1_P16 Port="P16" Point="I/O" UnConflict="TRDIOC1_P16_0" RealName="TRDIOC1" /> + <TRDIOD1_P30 Port="P30" Point="I/O" UnConflict="TRDIOD1_P30_0" RealName="TRDIOD1" /> + </TMRD1> + </TAU> + <RTC> + <RTC1HZ Port="P15" Point="O" /> + </RTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <PCLBUZ0> + <PCLBUZ0 Port="P140" Point="O" /> + </PCLBUZ0> + </PCLBUZ> + <LIN> + <LTxD0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin" PIOR44="0" Port="P13" Point="O" /> + <LRxD0 Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin" PIOR44="0" Port="P14" Point="I" /> + </LIN> + <CAN> + </CAN> + <Others> + <VDD AltFunc="VDD" Point="-" /> + <VSS AltFunc="VSS" Point="-" /> + <REGC AltFunc="REGC" Point="-" /> + <_RESET AltFunc="_RESET" RealName="_RESET" Point="I" /> + </Others> + </PIN> + <INT> + <CGC> + <INTCLM InUse="0" ISR="r_cgc_clockmonitor_interrupt" /> + <INTRAM InUse="0" ISR="r_cgc_ram_ecc_interrupt" /> + <INTSPM InUse="0" ISR="r_cgc_stackpointer_interrupt" /> + </CGC> + <INTC> + <INTP> + <INTP0 InUse="0" ISR="r_intc0_interrupt" /> + <INTP1 InUse="0" ISR="r_intc1_interrupt" /> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR52="0" InUse="0" ISR="r_intc2_interrupt" /> + <INTP3 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" InUse="0" ISR="r_intc3_interrupt" /> + <INTP4 InUse="0" ISR="r_intc4_interrupt" /> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc5_interrupt" /> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc6_interrupt" /> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse="0" ISR="r_intc7_interrupt" /> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" InUse="0" ISR="r_intc8_interrupt" /> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" InUse="0" ISR="r_intc9_interrupt" /> + </INTP> + <KEY> + <INTKR Chip="RL78F13_48pin,RL78F13_64pin" InUse="0" ISR="r_key_interrupt" /> + </KEY> + </INTC> + <Serial> + <SAU0> + <INTCSI00 InUse="0" ISR="r_csi00_interrupt" /> + <INTCSI01 InUse="0" ISR="r_csi01_interrupt" /> + <INTST0 InUse="0" ISR="r_uart0_interrupt_send" /> + <INTSR0 InUse="0" ISR="r_uart0_interrupt_receive" /> + <INTIIC00 InUse="0" ISR="r_iic00_interrupt" /> + <INTIIC01 InUse="0" ISR="r_iic01_interrupt" /> + </SAU0> + <SAU1> + <INTCSI10 InUse="0" ISR="r_csi10_interrupt" /> + <INTCSI11 InUse="0" ISR="r_csi11_interrupt" /> + <INTST1 InUse="0" ISR="r_uart1_interrupt_send" /> + <INTSR1 InUse="0" ISR="r_uart1_interrupt_receive" /> + <INTIIC10 InUse="0" ISR="r_iic10_interrupt" /> + <INTIIC11 InUse="0" ISR="r_iic11_interrupt" /> + </SAU1> + <IICA0> + <INTIICA0 InUse="0" ISR="r_iica0_interrupt" /> + </IICA0> + </Serial> + <ADC> + <INTAD InUse="1" ISR="r_adc_interrupt" IsDMATrigger="true" /> + </ADC> + <TAU> + <TAU0> + <Channel0> + <INTTM00 InUse="1" ISR="r_tau0_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM01 InUse="1" ISR="r_tau0_channel1_interrupt" /> + <INTTM01H InUse="0" ISR="r_tau0_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM02 InUse="0" ISR="r_tau0_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM03 InUse="0" ISR="r_tau0_channel3_interrupt" /> + <INTTM03H InUse="0" ISR="r_tau0_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM04 InUse="0" ISR="r_tau0_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM05 InUse="0" ISR="r_tau0_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM06 InUse="0" ISR="r_tau0_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM07 InUse="0" ISR="r_tau0_channel7_interrupt" /> + </Channel7> + </TAU0> + <TAU1> + <Channel0> + <INTTM10 InUse="0" ISR="r_tau1_channel0_interrupt" /> + </Channel0> + <Channel1> + <INTTM11 InUse="0" ISR="r_tau1_channel1_interrupt" /> + <INTTM11H InUse="0" ISR="r_tau1_channel1_higher8bits_interrupt" /> + </Channel1> + <Channel2> + <INTTM12 InUse="0" ISR="r_tau1_channel2_interrupt" /> + </Channel2> + <Channel3> + <INTTM13 InUse="0" ISR="r_tau1_channel3_interrupt" /> + <INTTM13H InUse="0" ISR="r_tau1_channel3_higher8bits_interrupt" /> + </Channel3> + <Channel4> + <INTTM14 InUse="0" ISR="r_tau1_channel4_interrupt" /> + </Channel4> + <Channel5> + <INTTM15 InUse="0" ISR="r_tau1_channel5_interrupt" /> + </Channel5> + <Channel6> + <INTTM16 InUse="0" ISR="r_tau1_channel6_interrupt" /> + </Channel6> + <Channel7> + <INTTM17 InUse="0" ISR="r_tau1_channel7_interrupt" /> + </Channel7> + </TAU1> + <TMRJ0> + <INTTRJ0 InUse="0" ISR="r_tmr_rj0_interrupt" /> + </TMRJ0> + <TMRD0> + <INTTRD0 InUse="0" ISR="r_tmr_rd0_interrupt" /> + </TMRD0> + <TMRD1> + <INTTRD1 InUse="0" ISR="r_tmr_rd1_interrupt" /> + </TMRD1> + </TAU> + <RTC> + <INTRTC InUse="0" ISR="r_rtc_interrupt" /> + </RTC> + <WDT> + <INTWDTI InUse="1" ISR="r_wdt_interrupt" /> + </WDT> + <LVD> + <INTLVI InUse="0" ISR="r_lvd_interrupt" IsDMATrigger="true" /> + </LVD> + </INT> + <FUNC> + <Common> + <r_main.c UserName="r_main.c" LibName="main.c" IsLibrary="false" InUse="2"> + <Type main="void main(void)" R_MAIN_UserInit="void R_MAIN_UserInit(void)" /> + <main UserName="main" LibName="main" FixedName="" InUse="2" ForRTOS="false" Init="" /> + <R_MAIN_UserInit UserName="R_MAIN_UserInit" LibName="R_MAIN_UserInit" InUse="2" /> + </r_main.c> + <r_systeminit.c UserName="r_systeminit.c" LibName="systeminit.c" Compiler="CARL78,ICCRL78,CCRL" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hdwinit="void hdwinit(void)" low_level_init="int __low_level_init(void)" inti_handler="void inti_handler(void)" idle_handler="void idle_handler(void)" /> + <R_Systeminit UserName="R_Systeminit" LibName="systeminit" InUse="1" Init="" /> + <hdwinit UserName="hdwinit" LibName="hdwinit" FixedName="" Compiler="CARL78,CCRL" InUse="1" Init="" /> + <__low_level_init UserName="" LibName="low_level_init" FixedName="" Compiler="ICCRL78" InUse="1" Init="" /> + </r_systeminit.c> + <r_hardware_setup.c UserName="" LibName="hardwaresetup.c" Compiler="GCCRL78" InUse="1"> + <Type systeminit="void R_Systeminit(void)" hardwaresetup="void HardwareSetup(void)" /> + <R_Systeminit UserName="" LibName="systeminit" InUse="1" Init="" /> + <HardwareSetup UserName="" LibName="hardwaresetup" FixedName="" InUse="1" Init="" /> + </r_hardware_setup.c> + <r_cg_vector_table.c UserName="" LibName="vectortable.c" Compiler="GCCRL78" InUse="1"> + <Type R_Dummy="void R_Dummy(void)" /> + <R_Dummy UserName="R_Dummy" LibName="R_Dummy" InUse="1" /> + </r_cg_vector_table.c> + <r_reset_program.asm UserName="" LibName="resetprogram.s" Compiler="GCCRL78" InUse="1" /> + <r_cg_interrupt_handlers.h UserName="" LibName="interrupthandlers.h" Compiler="GCCRL78" InUse="1" /> + <r_cg_macrodriver.h UserName="r_cg_macrodriver.h" LibName="macrodriver1.h" InUse="1" /> + <r_cg_userdefine.h UserName="r_cg_userdefine.h" LibName="userdefine.h" InUse="1" /> + <r_lk.dr UserName="" LibName="lk.dr" IsLibrary="false" Compiler="CARL78" InUse="1" /> + <r_mdlnk.xcl UserName="" LibName="md_lnk.xcl" Visible="false" IsLibrary="false" Compiler="ICCRL78" InUse="1" /> + <iodefine.head UserName="" LibName="iodefine.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <iodefineext.head UserName="" LibName="iodefineext.head" Visible="false" IsLibrary="false" Compiler="GCCRL78" InUse="1" /> + <mdt.customdebuglinker UserName="" LibName="mdt.customdebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.debuglinker UserName="" LibName="mdt.debuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.hardwaredebuglinker UserName="" LibName="mdt.hardwaredebuglinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.releaselinker UserName="" LibName="mdt.releaselinker" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.project UserName="" LibName="mdt.project" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.cproject UserName="" LibName="mdt.cproject" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <mdt.info UserName="" LibName="mdt.info" Visible="false" IsLibrary="false" Compiler="GCCRL78" ForAP="true" InUse="1" /> + <r_mdt.ipcf UserName="" LibName="mdt.ipcf" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.eww UserName="" LibName="mdt.eww" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.ewp UserName="" LibName="rl78mdt.ewp" Visible="false" IsLibrary="false" Compiler="ICCRL78" ForAP="true" InUse="1" /> + <r_mdt.txt UserName="r_mdt.txt" LibName="mdt.txt" Visible="false" IsLibrary="false" Compiler="CARL78,CCRL" ForAP="true" InUse="1" /> + </Common> + <CGC> + <r_cg_cgc.c UserName="r_cg_cgc.c" LibName=".c" InUse="1"> + <Type R_CGC_Create="void R_CGC_Create(void)" R_CGC_Set_ClockMode="MD_STATUS R_CGC_Set_ClockMode(enum ClockMode mode)" R_CGC_ClockMonitor_Start="void R_CGC_ClockMonitor_Start(void)" R_CGC_ClockMonitor_Stop="void R_CGC_ClockMonitor_Stop(void)" R_CGC_StackPointer_Start="void R_CGC_StackPointer_Start(void)" R_CGC_StackPointer_Stop="void R_CGC_StackPointer_Stop(void)" R_CGC_RAMECC_Start="void R_CGC_RAMECC_Start(void)" R_CGC_RAMECC_Stop="void R_CGC_RAMECC_Stop(void)" /> + <R_CGC_Create UserName="R_CGC_Create" LibName="R_CGC_Create" InUse="1" Init="1" InitMode="" /> + <R_CGC_Set_ClockMode UserName="R_CGC_Set_ClockMode" LibName="R_CGC_Set_ClockMode" InUse="0" /> + <R_CGC_ClockMonitor_Start UserName="R_CGC_ClockMonitor_Start" LibName="R_CGC_ClockMonitor_Start" InUse="0" /> + <R_CGC_ClockMonitor_Stop UserName="R_CGC_ClockMonitor_Stop" LibName="R_CGC_ClockMonitor_Stop" InUse="0" /> + <R_CGC_StackPointer_Start UserName="R_CGC_StackPointer_Start" LibName="R_CGC_StackPointer_Start" InUse="0" /> + <R_CGC_StackPointer_Stop UserName="R_CGC_StackPointer_Stop" LibName="R_CGC_StackPointer_Stop" InUse="0" /> + <R_CGC_RAMECC_Start UserName="R_CGC_RAMECC_Start" LibName="R_CGC_RAMECC_Start" InUse="0" /> + <R_CGC_RAMECC_Stop UserName="R_CGC_RAMECC_Stop" LibName="R_CGC_RAMECC_Stop" InUse="0" /> + </r_cg_cgc.c> + <r_cg_cgc_user.c UserName="r_cg_cgc_user.c" LibName="_user.c" InUse="1"> + <Type R_CGC_Get_ResetSource="void R_CGC_Get_ResetSource(void)" R_CGC_Create_UserInit="void R_CGC_Create_UserInit(void)" r_cgc_clockmonitor_interrupt="__interrupt static void r_cgc_clockmonitor_interrupt(void)" r_cgc_stackpointer_interrupt="__interrupt static void r_cgc_stackpointer_interrupt(void)" r_cgc_ram_ecc_interrupt="__interrupt static void r_cgc_ram_ecc_interrupt(void)" /> + <R_CGC_Create_UserInit UserName="R_CGC_Create_UserInit" LibName="R_CGC_Create_UserInit" InUse="0" /> + <R_CGC_Get_ResetSource UserName="R_CGC_Get_ResetSource" LibName="R_CGC_Get_ResetSource" Init="0" InUse="1" /> + <r_cgc_clockmonitor_interrupt UserName="r_cgc_clockmonitor_interrupt" INTHandle="" LibName="r_cgc_clockmonitor_interrupt" InUse="0" /> + <r_cgc_stackpointer_interrupt UserName="r_cgc_stackpointer_interrupt" INTHandle="" LibName="r_cgc_stackpointer_interrupt" InUse="0" /> + <r_cgc_ram_ecc_interrupt UserName="r_cgc_ram_ecc_interrupt" INTHandle="" LibName="r_cgc_ram_ecc_interrupt" InUse="0" /> + </r_cg_cgc_user.c> + <r_cg_cgc.h UserName="r_cg_cgc.h" LibName=".h" InUse="1" /> + <r_cg_pfdl.c UserName="r_cg_pfdl.c" LibName="_pfdl.c" InUse="1"> + <Type R_FDL_Create="void R_FDL_Create(void)" R_FDL_Write="pfdl_status_t R_FDL_Write(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Read="pfdl_status_t R_FDL_Read(pfdl_u16 index, __near pfdl_u08* buffer, pfdl_u16 bytecount)" R_FDL_Erase="pfdl_status_t R_FDL_Erase(pfdl_u16 blockno)" R_FDL_Open="void R_FDL_Open(void)" R_FDL_Close="void PFDL_Close(void)" R_FDL_BlankCheck="pfdl_status_t R_FDL_BlankCheck(pfdl_u16 index, pfdl_u16 bytecount)" R_FDL_IVerify="pfdl_status_t R_FDL_IVerify(pfdl_u16 index, pfdl_u16 bytecount)" /> + <R_FDL_Create UserName="R_FDL_Create" LibName="R_FDL_Create" InUse="0" InitMode="" /> + <R_FDL_Write UserName="R_FDL_Write" LibName="R_FDL_Write" InUse="0" /> + <R_FDL_Read UserName="R_FDL_Read" LibName="R_FDL_Read" InUse="0" /> + <R_FDL_Erase UserName="R_FDL_Erase" LibName="R_FDL_Erase" InUse="0" /> + <R_FDL_Open UserName="R_FDL_Open" LibName="R_FDL_Open" InUse="0" /> + <R_FDL_Close UserName="R_FDL_Close" LibName="R_FDL_Close" InUse="0" /> + <R_FDL_BlankCheck UserName="R_FDL_BlankCheck" LibName="R_FDL_BlankCheck" InUse="0" /> + <R_FDL_IVerify UserName="R_FDL_IVerify" LibName="R_FDL_IVerify" InUse="0" /> + </r_cg_pfdl.c> + <r_cg_pfdl.h UserName="r_cg_pfdl.h" LibName="_pfdl.h" InUse="0" /> + </CGC> + <PORT> + <r_cg_port.c UserName="r_cg_port.c" LibName=".c" InUse="1"> + <Type R_PORT_Create="void R_PORT_Create(void)" /> + <R_PORT_Create UserName="R_PORT_Create" LibName="R_PORT_Create" Init="1" InitMode="" InUse="1" /> + </r_cg_port.c> + <r_cg_port_user.c UserName="r_cg_port_user.c" LibName="_user.c" InUse="1"> + <Type R_PORT_Create_UserInit="void R_PORT_Create_UserInit(void)" /> + <R_PORT_Create_UserInit UserName="R_PORT_Create_UserInit" LibName="R_PORT_Create_UserInit" InUse="0" /> + </r_cg_port_user.c> + <r_cg_port.h UserName="r_cg_port.h" LibName=".h" InUse="1" /> + </PORT> + <INTC> + <r_cg_intc.c UserName="r_cg_intc.c" LibName=".c" InUse=""> + <Type R_INTC_Create="void R_INTC_Create(void)" R_INTCn_Start="void R_INTCn_Start(void)" R_INTCn_Stop="void R_INTCn_Stop(void)" R_KEY_Create="void R_KEY_Create(void)" R_KEY_Start="void R_KEY_Start(void)" R_KEY_Stop="void R_KEY_Stop(void)" /> + <INTP> + <R_INTC_Create UserName="R_INTC_Create" LibName="R_INTC_Create" InUse="" Init="2" InitMode="" /> + <INTP0> + <R_INTC0_Start UserName="R_INTC0_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC0_Stop UserName="R_INTC0_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP0> + <INTP1> + <R_INTC1_Start UserName="R_INTC1_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC1_Stop UserName="R_INTC1_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP1> + <INTP2 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC2_Start UserName="R_INTC2_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC2_Stop UserName="R_INTC2_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP2> + <INTP3 Chip="RL78F13_48pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0"> + <R_INTC3_Start UserName="R_INTC3_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC3_Stop UserName="R_INTC3_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP3> + <INTP4> + <R_INTC4_Start UserName="R_INTC4_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC4_Stop UserName="R_INTC4_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP4> + <INTP5 Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC5_Start UserName="R_INTC5_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC5_Stop UserName="R_INTC5_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP5> + <INTP6 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC6_Start UserName="R_INTC6_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC6_Stop UserName="R_INTC6_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP6> + <INTP7 Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <R_INTC7_Start UserName="R_INTC7_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC7_Stop UserName="R_INTC7_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP7> + <INTP8 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin"> + <R_INTC8_Start UserName="R_INTC8_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC8_Stop UserName="R_INTC8_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP8> + <INTP9 Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin"> + <R_INTC9_Start UserName="R_INTC9_Start" LibName="R_INTCn_Start" InUse="" /> + <R_INTC9_Stop UserName="R_INTC9_Stop" LibName="R_INTCn_Stop" InUse="" /> + </INTP9> + </INTP> + <KEY Chip="RL78F13_48pin,RL78F13_64pin"> + <R_KEY_Create UserName="R_KEY_Create" LibName="R_KEY_Create" InUse="" Init="2" InitMode="" /> + <R_KEY_Start UserName="R_KEY_Start" LibName="R_KEY_Start" InUse="" /> + <R_KEY_Stop UserName="R_KEY_Stop" LibName="R_KEY_Stop" InUse="" /> + </KEY> + </r_cg_intc.c> + <r_cg_intc_user.c UserName="r_cg_intc_user.c" LibName="_user.c" InUse=""> + <Type R_INTC_Create_UserInit="void R_INTC_Create_UserInit(void)" r_intc0_interrupt="__interrupt static void r_intc0_interrupt(void)" r_intc1_interrupt="__interrupt static void r_intc1_interrupt(void)" r_intc2_interrupt="__interrupt static void r_intc2_interrupt(void)" r_intc3_interrupt="__interrupt static void r_intc3_interrupt(void)" r_intc4_interrupt="__interrupt static void r_intc4_interrupt(void)" r_intc5_interrupt="__interrupt static void r_intc5_interrupt(void)" r_intc6_interrupt="__interrupt static void r_intc6_interrupt(void)" r_intc7_interrupt="__interrupt static void r_intc7_interrupt(void)" r_intc8_interrupt="__interrupt static void r_intc8_interrupt(void)" r_intc9_interrupt="__interrupt static void r_intc9_interrupt(void)" r_intc10_interrupt="__interrupt static void r_intc10_interrupt(void)" r_intc11_interrupt="__interrupt static void r_intc11_interrupt(void)" R_KEY_Create_UserInit="void R_KEY_Create_UserInit(void)" r_key_interrupt="__interrupt static void r_key_interrupt(void)" /> + <INTP> + <R_INTC_Create_UserInit UserName="R_INTC_Create_UserInit" LibName="R_INTC_Create_UserInit" InUse="" /> + <r_intc0_interrupt UserName="r_intc0_interrupt" LibName="r_intc0_interrupt" INTHandle="" InUse="" /> + <r_intc1_interrupt UserName="r_intc1_interrupt" LibName="r_intc1_interrupt" INTHandle="" InUse="" /> + <r_intc2_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc2_interrupt" LibName="r_intc2_interrupt" INTHandle="" InUse="" /> + <r_intc3_interrupt Chip="RL78F13_48pin,RL78F13_30pin,RL78F13_32pin,RL78F13_20pin" PIOR53="0" UserName="r_intc3_interrupt" LibName="r_intc3_interrupt" INTHandle="" InUse="" /> + <r_intc4_interrupt UserName="r_intc4_interrupt" LibName="r_intc4_interrupt" INTHandle="" InUse="" /> + <r_intc5_interrupt Chip="RL78F13_30pin,RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc5_interrupt" LibName="r_intc5_interrupt" INTHandle="" InUse="" /> + <r_intc6_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc6_interrupt" LibName="r_intc6_interrupt" INTHandle="" InUse="" /> + <r_intc7_interrupt Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="r_intc7_interrupt" LibName="r_intc7_interrupt" INTHandle="" InUse="" /> + <r_intc8_interrupt Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" UserName="r_intc8_interrupt" LibName="r_intc8_interrupt" INTHandle="" InUse="" /> + <r_intc9_interrupt Chip="R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10AGF,R5F10AGG,R5F10ALF,R5F10ALG,RL78F13_80pin" UserName="r_intc9_interrupt" LibName="r_intc9_interrupt" INTHandle="" InUse="" /> + </INTP> + <KEY Chip="RL78F13_48pin,RL78F13_64pin"> + <R_KEY_Create_UserInit UserName="R_KEY_Create_UserInit" LibName="R_KEY_Create_UserInit" InUse="" /> + <r_key_interrupt UserName="r_key_interrupt" LibName="r_key_interrupt" INTHandle="" InUse="" /> + </KEY> + </r_cg_intc_user.c> + <r_cg_intc.h UserName="r_cg_intc.h" LibName=".h" InUse="" /> + </INTC> + <Serial> + <r_cg_serial.c UserName="r_cg_serial.c" LibName=".c" InUse="0"> + <Type R_SAUn_Create="void R_SAUn_Create(void)" R_SAUn_Set_PowerOff="void R_SAUn_Set_PowerOff(void)" R_SAUn_Set_SnoozeOn="void R_SAUn_Set_SnoozeOn(void)" R_SAUn_Set_SnoozeOff="void R_SAUn_Set_SnoozeOff(void)" R_UARTn_Create="void R_UARTn_Create(void)" R_UARTn_Send="MD_STATUS R_UARTn_Send(uint8_t const * tx_buf, uint16_t tx_num)" R_UARTn_Receive="MD_STATUS R_UARTn_Receive(uint8_t const * rx_buf, uint16_t rx_num)" R_UARTn_Start="void R_UARTn_Start(void)" R_UARTn_Stop="void R_UARTn_Stop(void)" R_CSIn_Create="void R_CSIn_Create(void)" R_CSIn_Send="MD_STATUS R_CSIn_Send(uint8_t const * tx_buf, uint16_t tx_num)" R_CSIn_Receive="MD_STATUS R_CSIn_Receive(uint8_t const * rx_buf, uint16_t rx_num) " R_CSIn_Send_Receive="MD_STATUS R_CSIn_Send_Receive(uint8_t const * tx_buf, uint16_t tx_num, uint8_t const * rx_buf) " R_CSIn_Start="void R_CSIn_Start(void)" R_CSIn_Stop="void R_CSIn_Stop(void)" R_IICn_Create="void R_IICn_Create(void)" R_IICn_Master_Send="void R_IICn_Master_Send(uint8_t adr, uint8_t const * tx_buf, uint16_t txnum)" R_IICn_Master_Receive="void R_IICn_Master_Receive(uint8_t adr, uint8_t const * rx_buf, uint16_t rx_num) " R_IICn_Stop="void R_IICn_Stop(void)" R_IICn_StartCondition="void R_IICn_StartCondition(void)" R_IICn_StopCondition="void R_IICn_StopCondition(void)" R_UARTFn_Create="void R_UARTFn_Create(void)" R_UARTFn_Send="MD_STATUS R_UARTFn_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_UARTFn_Receive="MD_STATUS R_UARTFn_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_UARTFn_Set_ComparisonData="void R_UARTFn_Set_ComparisonData(uint16_t com_data)" R_UARTFn_Set_DataComparisonOn="void R_UARTFn_Set_DataComparisonOn(void)" R_UARTFn_Set_DataComparisonOff="void R_UARTFn_Set_DataComparisonOff(void)" R_UARTFn_Set_PowerOff="void R_UARTFn_Set_PowerOff(void)" R_IICAn_Create="void R_IICAn_Create(void)" R_IICAn_Master_Send="MD_STATUS R_IICAn_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)" R_IICAn_Master_Receive="MD_STATUS R_IICAn_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)" R_IICAn_Slave_Send="void R_IICAn_Slave_Send(uint8_t * const tx_buf, uint16_t tx_num)" R_IICAn_Slave_Receive="void R_IICAn_Slave_Receive(uint8_t * const rx_buf, uint16_t rx_num)" R_IICAn_Stop="void R_IICAn_Stop(void)" R_IICAn_StopCondition="void R_IICAn_StopCondition(void)" R_IICAn_Set_SnoozeOn="void R_IICAn_Set_SnoozeOn(void)" R_IICAn_Set_SnoozeOff="void R_IICAn_Set_SnoozeOff(void)" R_IICAn_Set_PowerOff="void R_IICAn_Set_PowerOff(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create UserName="R_SAU0_Create" LibName="R_SAUn_Create" InUse="0" Init="1" InitMode="" /> + <R_SAU0_Set_PowerOff UserName="R_SAU0_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="0" /> + <R_SAU0_Set_SnoozeOn UserName="R_SAU0_Set_SnoozeOn" LibName="R_SAUn_Set_SnoozeOn" InUse="0" /> + <R_SAU0_Set_SnoozeOff UserName="R_SAU0_Set_SnoozeOff" LibName="R_SAUn_Set_SnoozeOff" InUse="0" /> + <UART0 InUse=""> + <R_UART0_Create UserName="R_UART0_Create" LibName="R_UARTn_Create" InUse="0" InitMode="" /> + <R_UART0_Start UserName="R_UART0_Start" LibName="R_UARTn_Start" InUse="0" /> + <R_UART0_Stop UserName="R_UART0_Stop" LibName="R_UARTn_Stop" InUse="0" /> + <R_UART0_Send UserName="R_UART0_Send" LibName="R_UARTn_Send" InUse="0" /> + <R_UART0_Receive UserName="R_UART0_Receive" LibName="R_UARTn_Receive" InUse="0" /> + </UART0> + <CSI00 InUse=""> + <R_CSI00_Create UserName="R_CSI00_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI00_Start UserName="R_CSI00_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI00_Stop UserName="R_CSI00_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI00_Send UserName="R_CSI00_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI00_Receive UserName="R_CSI00_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI00_Send_Receive UserName="R_CSI00_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI00> + <CSI01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <R_CSI01_Create UserName="R_CSI01_Create" LibName="R_CSIn_Create" InUse="0" InitMode="" /> + <R_CSI01_Start UserName="R_CSI01_Start" LibName="R_CSIn_Start" InUse="0" /> + <R_CSI01_Stop UserName="R_CSI01_Stop" LibName="R_CSIn_Stop" InUse="0" /> + <R_CSI01_Send UserName="R_CSI01_Send" LibName="R_CSIn_Send" InUse="0" /> + <R_CSI01_Receive UserName="R_CSI01_Receive" LibName="R_CSIn_Receive" InUse="0" /> + <R_CSI01_Send_Receive UserName="R_CSI01_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="0" /> + </CSI01> + <IIC00 InUse=""> + <R_IIC00_Create UserName="R_IIC00_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC00_Master_Send UserName="R_IIC00_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC00_Master_Receive UserName="R_IIC00_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC00_Stop UserName="R_IIC00_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC00_StartCondition UserName="R_IIC00_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC00_StopCondition UserName="R_IIC00_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC00> + <IIC01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <R_IIC01_Create UserName="R_IIC01_Create" LibName="R_IICn_Create" InUse="0" InitMode="" /> + <R_IIC01_Master_Send UserName="R_IIC01_Master_Send" LibName="R_IICn_Master_Send" InUse="0" /> + <R_IIC01_Master_Receive UserName="R_IIC01_Master_Receive" LibName="R_IICn_Master_Receive" InUse="0" /> + <R_IIC01_Stop UserName="R_IIC01_Stop" LibName="R_IICn_Stop" InUse="0" /> + <R_IIC01_StartCondition UserName="R_IIC01_StartCondition" LibName="R_IICn_StartCondition" InUse="0" /> + <R_IIC01_StopCondition UserName="R_IIC01_StopCondition" LibName="R_IICn_StopCondition" InUse="0" /> + </IIC01> + </SAU0> + <SAU1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_SAU1_Create UserName="R_SAU1_Create" LibName="R_SAUn_Create" InUse="" Init="1" InitMode="" /> + <R_SAU1_Set_PowerOff UserName="R_SAU1_Set_PowerOff" LibName="R_SAUn_Set_PowerOff" InUse="" /> + <UART1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_UART1_Create UserName="R_UART1_Create" LibName="R_UARTn_Create" InUse="" InitMode="" /> + <R_UART1_Start UserName="R_UART1_Start" LibName="R_UARTn_Start" InUse="" /> + <R_UART1_Stop UserName="R_UART1_Stop" LibName="R_UARTn_Stop" InUse="" /> + <R_UART1_Send UserName="R_UART1_Send" LibName="R_UARTn_Send" InUse="" /> + <R_UART1_Receive UserName="R_UART1_Receive" LibName="R_UARTn_Receive" InUse="" /> + </UART1> + <CSI10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <R_CSI10_Create UserName="R_CSI10_Create" LibName="R_CSIn_Create" InUse="" InitMode="" /> + <R_CSI10_Start UserName="R_CSI10_Start" LibName="R_CSIn_Start" InUse="" /> + <R_CSI10_Stop UserName="R_CSI10_Stop" LibName="R_CSIn_Stop" InUse="" /> + <R_CSI10_Send UserName="R_CSI10_Send" LibName="R_CSIn_Send" InUse="" /> + <R_CSI10_Receive UserName="R_CSI10_Receive" LibName="R_CSIn_Receive" InUse="" /> + <R_CSI10_Send_Receive UserName="R_CSI10_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <R_CSI11_Create UserName="R_CSI11_Create" LibName="R_CSIn_Create" InUse="" InitMode="" /> + <R_CSI11_Start UserName="R_CSI11_Start" LibName="R_CSIn_Start" InUse="" /> + <R_CSI11_Stop UserName="R_CSI11_Stop" LibName="R_CSIn_Stop" InUse="" /> + <R_CSI11_Send UserName="R_CSI11_Send" LibName="R_CSIn_Send" InUse="" /> + <R_CSI11_Receive UserName="R_CSI11_Receive" LibName="R_CSIn_Receive" InUse="" /> + <R_CSI11_Send_Receive UserName="R_CSI11_Send_Receive" LibName="R_CSIn_Send_Receive" InUse="" /> + </CSI11> + <IIC10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <R_IIC10_Create UserName="R_IIC10_Create" LibName="R_IICn_Create" InUse="" InitMode="" /> + <R_IIC10_Master_Send UserName="R_IIC10_Master_Send" LibName="R_IICn_Master_Send" InUse="" /> + <R_IIC10_Master_Receive UserName="R_IIC10_Master_Receive" LibName="R_IICn_Master_Receive" InUse="" /> + <R_IIC10_Stop UserName="R_IIC10_Stop" LibName="R_IICn_Stop" InUse="" /> + <R_IIC10_StartCondition UserName="R_IIC10_StartCondition" LibName="R_IICn_StartCondition" InUse="" /> + <R_IIC10_StopCondition UserName="R_IIC10_StopCondition" LibName="R_IICn_StopCondition" InUse="" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <R_IIC11_Create UserName="R_IIC11_Create" LibName="R_IICn_Create" InUse="" InitMode="" /> + <R_IIC11_Master_Send UserName="R_IIC11_Master_Send" LibName="R_IICn_Master_Send" InUse="" /> + <R_IIC11_Master_Receive UserName="R_IIC11_Master_Receive" LibName="R_IICn_Master_Receive" InUse="" /> + <R_IIC11_Stop UserName="R_IIC11_Stop" LibName="R_IICn_Stop" InUse="" /> + <R_IIC11_StartCondition UserName="R_IIC11_StartCondition" LibName="R_IICn_StartCondition" InUse="" /> + <R_IIC11_StopCondition UserName="R_IIC11_StopCondition" LibName="R_IICn_StopCondition" InUse="" /> + </IIC11> + </SAU1> + <IICA0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse=""> + <R_IICA0_Create UserName="R_IICA0_Create" LibName="R_IICAn_Create" InUse="" Init="1" InitMode="" /> + <R_IICA0_Master_Send UserName="R_IICA0_Master_Send" LibName="R_IICAn_Master_Send" InUse="" /> + <R_IICA0_Master_Receive UserName="R_IICA0_Master_Receive" LibName="R_IICAn_Master_Receive" InUse="" /> + <R_IICA0_Slave_Send UserName="R_IICA0_Slave_Send" LibName="R_IICAn_Slave_Send" InUse="" /> + <R_IICA0_Slave_Receive UserName="R_IICA0_Slave_Receive" LibName="R_IICAn_Slave_Receive" InUse="" /> + <R_IICA0_Stop UserName="R_IICA0_Stop" LibName="R_IICAn_Stop" InUse="" /> + <R_IICA0_StopCondition UserName="R_IICA0_StopCondition" LibName="R_IICAn_StopCondition" InUse="" /> + <R_IICA0_Set_SnoozeOn UserName="R_IICA0_Set_SnoozeOn" LibName="R_IICAn_Set_SnoozeOn" InUse="" /> + <R_IICA0_Set_SnoozeOff UserName="R_IICA0_Set_SnoozeOff" LibName="R_IICAn_Set_SnoozeOff" InUse="" /> + <R_IICA0_Set_PowerOff UserName="R_IICA0_Set_PowerOff" LibName="R_IICAn_Set_PowerOff" InUse="" /> + </IICA0> + </r_cg_serial.c> + <r_cg_serial_user.c UserName="r_cg_serial_user.c" LibName="_user.c" InUse="0"> + <Type R_SAUn_Create_UserInit="void R_SAUn_Create_UserInit(void)" r_uartn_interrupt_receive="__interrupt void r_uartn_interrupt_receive(void)" r_uartn_interrupt_error="__interrupt void r_uartn_interrupt_error(void)" r_uartn_interrupt_send="__interrupt void r_uartn_interrupt_send(void)" r_uartn_callback_sendend="void r_uartn_callback_sendend(void)" r_uartn_callback_receiveend="void r_uartn_callback_receiveend(void)" r_uartn_callback_error="void r_uartn_callback_error(uint16_t err_type)" r_uartn_callback_softwareoverrun="void r_uartn_callback_softwareoverrun(uint16_t err_type)" r_csin_interrupt="__interrupt void r_csin_interrupt(void)" r_csin_callback_receiveend="void r_csin_callback_receiveend(void)" r_csin_callback_error="void r_csin_callback_error(uint16_t err_type)" r_csin_callback_sendend="void r_csin_callback_sendend(void)" r_iicn_interrupt="__interrupt void r_iicn_interrupt(void)" r_iicn_callback_master_receiveend="void r_iicn_callback_master_receiveend(void)" r_iicn_callback_master_sendend="void r_iicn_callback_master_sendend(void)" r_iicn_callback_master_error="void r_iicn_callback_master_error(MD_STATUS flag)" R_UARTFn_Create_UserInit="void R_UARTFn_Create_UserInit(void)" r_uartfn_interrupt_receive="__interrupt static void r_uartfn_interrupt_receive(void)" r_uartfn_interrupt_error="__interrupt static void r_uartfn_interrupt_error(void)" r_uartfn_interrupt_send="__interrupt static void r_uartfn_interrupt_send(void)" r_uartfn_callback_receiveend="static void r_uartfn_callback_receiveend(void)" r_uartfn_callback_sendend="static void r_uartfn_callback_sendend(void)" r_uartfn_callback_error="static void r_uartfn_callback_error(void)" r_uartfn_callback_softwareoverrun="static void r_uartfn_callback_softwareoverrun(uint16_t rx_data)" r_uartfn_callback_expbitdetect="static void r_uartfn_callback_expbitdetect(void)" r_uartfn_callback_idmatch="static void r_uartfn_callback_idmatch(void)" R_IICAn_Create_UserInit="void R_IICAn_Create_UserInit(void)" r_iican_interrupt="__interrupt static r_iican_interrupt(void)" r_iican_callback_master_sendend="static void r_iican_callback_master_sendend(void)" r_iican_callback_master_receiveend="static void r_iican_callback_master_receiveend(void)" r_iican_callback_slave_sendend="static void r_iican_callback_slave_sendend(void)" r_iican_callback_slave_receiveend="static void r_iican_callback_slave_receiveend(void)" r_iican_callback_master_error="static void r_iican_callback_master_error(MD_STATUS flag)" r_iican_callback_slave_error="static void r_iican_callback_slave_error(MD_STATUS flag)" r_iican_callback_getstopcondition="static void r_iican_callback_getstopcondition(void)" /> + <SAU0 InUse=""> + <R_SAU0_Create_UserInit UserName="R_SAU0_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="0" /> + <UART0 InUse=""> + <r_uart0_interrupt_receive UserName="r_uart0_interrupt_receive" INTHandle="" LibName="r_uartn_interrupt_receive" InUse="0" /> + <r_uart0_interrupt_send UserName="r_uart0_interrupt_send" INTHandle="" LibName="r_uartn_interrupt_send" InUse="0" /> + <r_uart0_callback_receiveend UserName="r_uart0_callback_receiveend" LibName="r_uartn_callback_receiveend" InUse="0" /> + <r_uart0_callback_sendend UserName="r_uart0_callback_sendend" LibName="r_uartn_callback_sendend" InUse="0" /> + <r_uart0_callback_error UserName="r_uart0_callback_error" LibName="r_uartn_callback_error" InUse="0" /> + <r_uart0_callback_softwareoverrun UserName="r_uart0_callback_softwareoverrun" LibName="r_uartn_callback_softwareoverrun" InUse="0" /> + </UART0> + <CSI00 InUse=""> + <r_csi00_interrupt UserName="r_csi00_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="0" /> + <r_csi00_callback_receiveend UserName="r_csi00_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="0" /> + <r_csi00_callback_error UserName="r_csi00_callback_error" LibName="r_csin_callback_error" InUse="0" /> + <r_csi00_callback_sendend UserName="r_csi00_callback_sendend" LibName="r_csin_callback_sendend" InUse="0" /> + </CSI00> + <CSI01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <r_csi01_interrupt UserName="r_csi01_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="0" /> + <r_csi01_callback_receiveend UserName="r_csi01_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="0" /> + <r_csi01_callback_error UserName="r_csi01_callback_error" LibName="r_csin_callback_error" InUse="0" /> + <r_csi01_callback_sendend UserName="r_csi01_callback_sendend" LibName="r_csin_callback_sendend" InUse="0" /> + </CSI01> + <IIC00 InUse=""> + <r_iic00_interrupt UserName="r_iic00_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="0" /> + <r_iic00_callback_master_receiveend UserName="r_iic00_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="0" /> + <r_iic00_callback_master_sendend UserName="r_iic00_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="0" /> + <r_iic00_callback_master_error UserName="r_iic00_callback_master_error" LibName="r_iicn_callback_master_error" InUse="0" /> + </IIC00> + <IIC01 InUse="" Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0"> + <r_iic01_interrupt UserName="r_iic01_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="0" /> + <r_iic01_callback_master_receiveend UserName="r_iic01_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="0" /> + <r_iic01_callback_master_sendend UserName="r_iic01_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="0" /> + <r_iic01_callback_master_error UserName="r_iic01_callback_master_error" LibName="r_iicn_callback_master_error" InUse="0" /> + </IIC01> + </SAU0> + <SAU1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" PIOR42="0" InUse=""> + <R_SAU1_Create_UserInit UserName="R_SAU1_Create_UserInit" LibName="R_SAUn_Create_UserInit" InUse="" /> + <UART1 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_uart1_interrupt_receive UserName="r_uart1_interrupt_receive" INTHandle="" LibName="r_uartn_interrupt_receive" InUse="" /> + <r_uart1_interrupt_send UserName="r_uart1_interrupt_send" INTHandle="" LibName="r_uartn_interrupt_send" InUse="" /> + <r_uart1_callback_receiveend UserName="r_uart1_callback_receiveend" LibName="r_uartn_callback_receiveend" InUse="" /> + <r_uart1_callback_sendend UserName="r_uart1_callback_sendend" LibName="r_uartn_callback_sendend" InUse="" /> + <r_uart1_callback_error UserName="r_uart1_callback_error" LibName="r_uartn_callback_error" InUse="" /> + <r_uart1_callback_softwareoverrun UserName="r_uart1_callback_softwareoverrun" LibName="r_uartn_callback_softwareoverrun" InUse="" /> + </UART1> + <CSI10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_csi10_interrupt UserName="r_csi10_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="" /> + <r_csi10_callback_receiveend UserName="r_csi10_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="" /> + <r_csi10_callback_error UserName="r_csi10_callback_error" LibName="r_csin_callback_error" InUse="" /> + <r_csi10_callback_sendend UserName="r_csi10_callback_sendend" LibName="r_csin_callback_sendend" InUse="" /> + </CSI10> + <CSI11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <r_csi11_interrupt UserName="r_csi11_interrupt" INTHandle="" LibName="r_csin_interrupt" InUse="" /> + <r_csi11_callback_receiveend UserName="r_csi11_callback_receiveend" LibName="r_csin_callback_receiveend" InUse="" /> + <r_csi11_callback_error UserName="r_csi11_callback_error" LibName="r_csin_callback_error" InUse="" /> + <r_csi11_callback_sendend UserName="r_csi11_callback_sendend" LibName="r_csin_callback_sendend" InUse="" /> + </CSI11> + <IIC10 Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" InUse=""> + <r_iic10_interrupt UserName="r_iic10_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="" /> + <r_iic10_callback_master_receiveend UserName="r_iic10_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="" /> + <r_iic10_callback_master_sendend UserName="r_iic10_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="" /> + <r_iic10_callback_master_error UserName="r_iic10_callback_master_error" LibName="r_iicn_callback_master_error" InUse="" /> + </IIC10> + <IIC11 Chip="RL78F13_80pin,R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG" PIOR43="0" InUse=""> + <r_iic11_interrupt UserName="r_iic11_interrupt" INTHandle="" LibName="r_iicn_interrupt" InUse="" /> + <r_iic11_callback_master_receiveend UserName="r_iic11_callback_master_receiveend" LibName="r_iicn_callback_master_receiveend" InUse="" /> + <r_iic11_callback_master_sendend UserName="r_iic11_callback_master_sendend" LibName="r_iicn_callback_master_sendend" InUse="" /> + <r_iic11_callback_master_error UserName="r_iic11_callback_master_error" LibName="r_iicn_callback_master_error" InUse="" /> + </IIC11> + </SAU1> + <IICA0 Chip="RL78F13_32pin,RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" InUse=""> + <R_IICA0_Create_UserInit UserName="R_IICA0_Create_UserInit" LibName="R_IICAn_Create_UserInit" InUse="" /> + <r_iica0_interrupt UserName="r_iica0_interrupt" INTHandle="" LibName="r_iican_interrupt" InUse="" /> + <r_iica0_callback_master_sendend UserName="r_iica0_callback_master_sendend" LibName="r_iican_callback_master_sendend" InUse="" /> + <r_iica0_callback_master_receiveend UserName="r_iica0_callback_master_receiveend" LibName="r_iican_callback_master_receiveend" InUse="" /> + <r_iica0_callback_slave_sendend UserName="r_iica0_callback_slave_sendend" LibName="r_iican_callback_slave_sendend" InUse="" /> + <r_iica0_callback_slave_receiveend UserName="r_iica0_callback_slave_receiveend" LibName="r_iican_callback_slave_receiveend" InUse="" /> + <r_iica0_callback_master_error UserName="r_iica0_callback_master_error" LibName="r_iican_callback_master_error" InUse="" /> + <r_iica0_callback_slave_error UserName="r_iica0_callback_slave_error" LibName="r_iican_callback_slave_error" InUse="" /> + <r_iica0_callback_getstopcondition UserName="r_iica0_callback_getstopcondition" LibName="r_iican_callback_getstopcondition" InUse="" /> + </IICA0> + </r_cg_serial_user.c> + <r_cg_serial.h UserName="r_cg_serial.h" LibName=".h" InUse="0" /> + </Serial> + <ADC> + <r_cg_adc.c UserName="r_cg_adc.c" LibName=".c" InUse="1"> + <Type R_ADC_Create="void R_ADC_Create(void)" R_ADC_Start="void R_ADC_Start(void)" R_ADC_Stop="void R_ADC_Stop(void)" R_ADC_Set_OperationOn="void R_ADC_Set_OperationOn(void)" R_ADC_Set_OperationOff="void R_ADC_Set_OperationOff(void)" R_ADC_Get_Result="void R_ADC_Get_Result(uint16_t * const buffer)" R_ADC_Get_Result_8bit="void R_ADC_Get_Result_8bit(uint8_t * const buffer)" R_ADC_Set_ADChannel="MD_STATUS R_ADC_Set_ADChannel(ad_channel_t channel)" R_ADC_Set_SnoozeOn="void R_ADC_Set_SnoozeOn(void)" R_ADC_Set_SnoozeOff="void R_ADC_Set_SnoozeOff(void)" R_ADC_Set_TestChannel="MD_STATUS R_ADC_Set_TestChannel(test_channel_t channel)" R_ADC_Set_PowerOff="void R_ADC_Set_PowerOff(void)" /> + <R_ADC_Create UserName="R_ADC_Create" LibName="R_ADC_Create" InUse="1" Init="1" InitMode="" /> + <R_ADC_Start UserName="R_ADC_Start" LibName="R_ADC_Start" InUse="1" /> + <R_ADC_Stop UserName="R_ADC_Stop" LibName="R_ADC_Stop" InUse="1" /> + <R_ADC_Set_OperationOn UserName="R_ADC_Set_OperationOn" LibName="R_ADC_Set_OperationOn" InUse="1" /> + <R_ADC_Set_OperationOff UserName="R_ADC_Set_OperationOff" LibName="R_ADC_Set_OperationOff" InUse="1" /> + <R_ADC_Get_Result UserName="R_ADC_Get_Result" LibName="R_ADC_Get_Result" InUse="1" /> + <R_ADC_Get_Result_8bit UserName="R_ADC_Get_Result_8bit" LibName="R_ADC_Get_Result_8bit" InUse="0" /> + <R_ADC_Set_ADChannel UserName="R_ADC_Set_ADChannel" LibName="R_ADC_Set_ADChannel" InUse="0" /> + <R_ADC_Set_SnoozeOn UserName="R_ADC_Set_SnoozeOn" LibName="R_ADC_Set_SnoozeOn" InUse="0" /> + <R_ADC_Set_SnoozeOff UserName="R_ADC_Set_SnoozeOff" LibName="R_ADC_Set_SnoozeOff" InUse="0" /> + <R_ADC_Set_TestChannel UserName="R_ADC_Set_TestChannel" LibName="R_ADC_Set_TestChannel" InUse="0" /> + <R_ADC_Set_PowerOff UserName="R_ADC_Set_PowerOff" LibName="R_ADC_Set_PowerOff" InUse="0" /> + </r_cg_adc.c> + <r_cg_adc_user.c UserName="r_cg_adc_user.c" LibName="_user.c" InUse="1"> + <Type R_ADC_Create_UserInit="void R_ADC_Create_UserInit(void)" r_adc_interrupt="__interrupt static void r_adc_interrupt(void)" /> + <R_ADC_Create_UserInit UserName="R_ADC_Create_UserInit" LibName="R_ADC_Create_UserInit" InUse="0" /> + <r_adc_interrupt UserName="r_adc_interrupt" INTHandle="" LibName="r_adc_interrupt" InUse="1" /> + </r_cg_adc_user.c> + <r_cg_adc.h UserName="r_cg_adc.h" LibName=".h" InUse="1" /> + </ADC> + <TAU> + <r_cg_timer.c UserName="r_cg_timer.c" LibName=".c" InUse="1"> + <Type R_TAU_Create="void R_TAU_Create(void)" R_TAU_Set_PowerOff="void R_TAU_Set_PowerOff(void)" R_TAU_Channeln_Start="void R_TAU_Channeln_Start(void)" R_TAU_Channeln_Higher8bits_Start="void R_TAU_Channeln_Higher8bits_Start(void)" R_TAU_Channeln_Lower8bits_Start="void R_TAU_Channeln_Lower8bits_Start(void)" R_TAU_Channeln_Stop="void R_TAU_Channeln_Stop(void)" R_TAU_Channeln_Higher8bits_Stop="void R_TAU_Channeln_Higher8bits_Stop(void)" R_TAU_Channeln_Lower8bits_Stop="void R_TAU_Channeln_Lower8bits_Stop(void)" R_TAU_Channeln_Get_PulseWidth="void R_TAU_Channeln_Get_PulseWidth(uint32_t * const width)" R_TAU_Channeln_Set_SoftwareTriggerOn="void R_TAU_Channeln_Set_SoftwareTriggerOn(void)" R_WUTM_Create="void R_WUTM_Create(void)" R_WUTM_Start="void R_WUTM_Start(void)" R_WUTM_Stop="void R_WUTM_Stop(void)" R_WUTM_Set_PowerOff="void R_WUTM_Set_PowerOff(void)" /> + <TAU0> + <R_TAU0_Create UserName="R_TAU0_Create" LibName="R_TAU_Create" InUse="1" Init="1" InitMode="" /> + <R_TAU0_Set_PowerOff UserName="R_TAU0_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU0_Channel0_Start UserName="R_TAU0_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel0_Stop UserName="R_TAU0_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel0_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" PIOR00="0" UserName="R_TAU0_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel0_Set_SoftwareTriggerOn UserName="R_TAU0_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU0_Channel1_Start UserName="R_TAU0_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Start UserName="R_TAU0_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Start UserName="R_TAU0_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel1_Stop UserName="R_TAU0_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel1_Higher8bits_Stop UserName="R_TAU0_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Lower8bits_Stop UserName="R_TAU0_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel1_Get_PulseWidth UserName="R_TAU0_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU0_Channel2_Start UserName="R_TAU0_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel2_Stop UserName="R_TAU0_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel2_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" PIOR02="0" UserName="R_TAU0_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel2_Set_SoftwareTriggerOn UserName="R_TAU0_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU0_Channel3_Start UserName="R_TAU0_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Start UserName="R_TAU0_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Start UserName="R_TAU0_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU0_Channel3_Stop UserName="R_TAU0_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel3_Higher8bits_Stop UserName="R_TAU0_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Lower8bits_Stop UserName="R_TAU0_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU0_Channel3_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" PIOR03="0" UserName="R_TAU0_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + <Channel4 InUse=""> + <R_TAU0_Channel4_Start UserName="R_TAU0_Channel4_Start" LibName="R_TAU_Channeln_Start" InUse="1" /> + <R_TAU0_Channel4_Stop UserName="R_TAU0_Channel4_Stop" LibName="R_TAU_Channeln_Stop" InUse="1" /> + <R_TAU0_Channel4_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin" UserName="R_TAU0_Channel4_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel4_Set_SoftwareTriggerOn UserName="R_TAU0_Channel4_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel4> + <Channel5 InUse=""> + <R_TAU0_Channel5_Start UserName="R_TAU0_Channel5_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel5_Stop UserName="R_TAU0_Channel5_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel5_Get_PulseWidth Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" UserName="R_TAU0_Channel5_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel5> + <Channel6 InUse=""> + <R_TAU0_Channel6_Start UserName="R_TAU0_Channel6_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel6_Stop UserName="R_TAU0_Channel6_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel6_Get_PulseWidth UserName="R_TAU0_Channel6_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU0_Channel6_Set_SoftwareTriggerOn Chip="RL78F13_48pin,RL78F13_64pin" PIOR17="0" UserName="R_TAU0_Channel6_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel6> + <Channel7 InUse=""> + <R_TAU0_Channel7_Start UserName="R_TAU0_Channel7_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU0_Channel7_Stop UserName="R_TAU0_Channel7_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU0_Channel7_Get_PulseWidth UserName="R_TAU0_Channel7_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <R_TAU1_Create UserName="R_TAU1_Create" LibName="R_TAU_Create" InUse="0" Init="1" InitMode="" /> + <R_TAU1_Set_PowerOff UserName="R_TAU1_Set_PowerOff" LibName="R_TAU_Set_PowerOff" InUse="0" /> + <Channel0 InUse=""> + <R_TAU1_Channel0_Start UserName="R_TAU1_Channel0_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel0_Stop UserName="R_TAU1_Channel0_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel0_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel0_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU1_Channel0_Set_SoftwareTriggerOn UserName="R_TAU1_Channel0_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <R_TAU1_Channel1_Start UserName="R_TAU1_Channel1_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel1_Higher8bits_Start UserName="R_TAU1_Channel1_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU1_Channel1_Lower8bits_Start UserName="R_TAU1_Channel1_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU1_Channel1_Stop UserName="R_TAU1_Channel1_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel1_Higher8bits_Stop UserName="R_TAU1_Channel1_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU1_Channel1_Lower8bits_Stop UserName="R_TAU1_Channel1_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU1_Channel1_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel1_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <R_TAU1_Channel2_Start UserName="R_TAU1_Channel2_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel2_Stop UserName="R_TAU1_Channel2_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel2_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel2_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + <R_TAU1_Channel2_Set_SoftwareTriggerOn UserName="R_TAU1_Channel2_Set_SoftwareTriggerOn" LibName="R_TAU_Channeln_Set_SoftwareTriggerOn" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <R_TAU1_Channel3_Start UserName="R_TAU1_Channel3_Start" LibName="R_TAU_Channeln_Start" InUse="0" /> + <R_TAU1_Channel3_Higher8bits_Start UserName="R_TAU1_Channel3_Higher8bits_Start" LibName="R_TAU_Channeln_Higher8bits_Start" InUse="0" /> + <R_TAU1_Channel3_Lower8bits_Start UserName="R_TAU1_Channel3_Lower8bits_Start" LibName="R_TAU_Channeln_Lower8bits_Start" InUse="0" /> + <R_TAU1_Channel3_Stop UserName="R_TAU1_Channel3_Stop" LibName="R_TAU_Channeln_Stop" InUse="0" /> + <R_TAU1_Channel3_Higher8bits_Stop UserName="R_TAU1_Channel3_Higher8bits_Stop" LibName="R_TAU_Channeln_Higher8bits_Stop" InUse="0" /> + <R_TAU1_Channel3_Lower8bits_Stop UserName="R_TAU1_Channel3_Lower8bits_Stop" LibName="R_TAU_Channeln_Lower8bits_Stop" InUse="0" /> + <R_TAU1_Channel3_Get_PulseWidth Chip="R5F10ALF,R5F10ALG,R5F10AGF,R5F10AGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BAC,R5F10BAD,R5F10BAE,R5F10BAF,R5F10BAG" UserName="R_TAU1_Channel3_Get_PulseWidth" LibName="R_TAU_Channeln_Get_PulseWidth" InUse="0" /> + </Channel3> + </TAU1> + <TMRJ0 InUse=""> + <R_TMR_RJ0_Create UserName="R_TMR_RJ0_Create" LibName="R_TMR_RJn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RJ0_Start UserName="R_TMR_RJ0_Start" LibName="R_TMR_RJn_Start" InUse="" /> + <R_TMR_RJ0_Stop UserName="R_TMR_RJ0_Stop" LibName="R_TMR_RJn_Stop" InUse="" /> + <R_TMR_RJ0_Get_PulseWidth Chip="RL78F13_80pin,RL78F13_64pin,RL78F13_48pin,RL78F13_32pin,RL78F13_30pin" UserName="R_TMR_RJ0_Get_PulseWidth" LibName="R_TMR_RJn_Get_PulseWidth" InUse="" /> + <R_TMR_RJ0_Set_PowerOff UserName="R_TMR_RJ0_Set_PowerOff" LibName="R_TMR_RJn_Set_PowerOff" InUse="" /> + </TMRJ0> + <TMRD0 InUse=""> + <R_TMR_RD0_Create UserName="R_TMR_RD0_Create" LibName="R_TMR_RDn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RD0_Start UserName="R_TMR_RD0_Start" LibName="R_TMR_RDn_Start" InUse="" /> + <R_TMR_RD0_Stop UserName="R_TMR_RD0_Stop" LibName="R_TMR_RDn_Stop" InUse="" /> + <R_TMR_RD0_Get_PulseWidth UserName="R_TMR_RD0_Get_PulseWidth" LibName="R_TMR_RDn_Get_PulseWidth" InUse="" /> + <R_TMR_RD0_Set_PowerOff UserName="R_TMR_RD0_Set_PowerOff" LibName="R_TMR_RDn_Set_PowerOff" InUse="" /> + <R_TMR_RD0_ForcedOutput_Start UserName="R_TMR_RD0_ForcedOutput_Start" LibName="R_TMR_RDn_ForcedOutput_Start" InUse="" /> + <R_TMR_RD0_ForcedOutput_Stop UserName="R_TMR_RD0_ForcedOutput_Stop" LibName="R_TMR_RDn_ForcedOutput_Stop" InUse="" /> + </TMRD0> + <TMRD1 InUse=""> + <R_TMR_RD1_Create UserName="R_TMR_RD1_Create" LibName="R_TMR_RDn_Create" InUse="" Init="2" InitMode="" /> + <R_TMR_RD1_Start UserName="R_TMR_RD1_Start" LibName="R_TMR_RDn_Start" InUse="" /> + <R_TMR_RD1_Stop UserName="R_TMR_RD1_Stop" LibName="R_TMR_RDn_Stop" InUse="" /> + <R_TMR_RD1_Get_PulseWidth UserName="R_TMR_RD1_Get_PulseWidth" LibName="R_TMR_RDn_Get_PulseWidth" InUse="" /> + <R_TMR_RD1_Set_PowerOff UserName="R_TMR_RD1_Set_PowerOff" LibName="R_TMR_RDn_Set_PowerOff" InUse="" /> + <R_TMR_RD1_ForcedOutput_Start UserName="R_TMR_RD1_ForcedOutput_Start" LibName="R_TMR_RDn_ForcedOutput_Start" InUse="" /> + <R_TMR_RD1_ForcedOutput_Stop UserName="R_TMR_RD1_ForcedOutput_Stop" LibName="R_TMR_RDn_ForcedOutput_Stop" InUse="" /> + </TMRD1> + </r_cg_timer.c> + <r_cg_timer_user.c UserName="r_cg_timer_user.c" LibName="_user.c" InUse="1"> + <Type R_TAU_Create_UserInit="void R_TAUn_Create_UserInit(void)" r_tau_channeln_interrupt="__interrupt static void r_tau_channeln_interrupt(void)" r_tau_channeln_higher8bits_interrupt="__interrupt static void r_tau_channeln_higher8bits_interrupt(void)" R_WUTM_Create_UserInit="void R_WUTM_Create_UserInit(void)" r_wutm_interrupt="__interrupt static void r_wutm_interrupt(void)" /> + <TAU0> + <R_TAU0_Create_UserInit UserName="R_TAU0_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau0_channel0_interrupt UserName="r_tau0_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + </Channel0> + <Channel1 InUse=""> + <r_tau0_channel1_interrupt UserName="r_tau0_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="1" /> + <r_tau0_channel1_higher8bits_interrupt UserName="r_tau0_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau0_channel2_interrupt UserName="r_tau0_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau0_channel3_interrupt UserName="r_tau0_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau0_channel3_higher8bits_interrupt UserName="r_tau0_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + <Channel4 InUse=""> + <r_tau0_channel4_interrupt UserName="r_tau0_channel4_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel4> + <Channel5 InUse=""> + <r_tau0_channel5_interrupt UserName="r_tau0_channel5_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel5> + <Channel6 InUse=""> + <r_tau0_channel6_interrupt UserName="r_tau0_channel6_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel6> + <Channel7 InUse=""> + <r_tau0_channel7_interrupt UserName="r_tau0_channel7_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel7> + </TAU0> + <TAU1 Chip="groupb,groupc1,groupc2"> + <R_TAU1_Create_UserInit UserName="R_TAU1_Create_UserInit" LibName="R_TAU_Create_UserInit" InUse="0" /> + <Channel0 InUse=""> + <r_tau1_channel0_interrupt UserName="r_tau1_channel0_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel0> + <Channel1 InUse=""> + <r_tau1_channel1_interrupt UserName="r_tau1_channel1_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau1_channel1_higher8bits_interrupt UserName="r_tau1_channel1_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel1> + <Channel2 InUse=""> + <r_tau1_channel2_interrupt UserName="r_tau1_channel2_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + </Channel2> + <Channel3 InUse=""> + <r_tau1_channel3_interrupt UserName="r_tau1_channel3_interrupt" INTHandle="" LibName="r_tau_channeln_interrupt" InUse="0" /> + <r_tau1_channel3_higher8bits_interrupt UserName="r_tau1_channel3_higher8bits_interrupt" INTHandle="" LibName="r_tau_channeln_higher8bits_interrupt" InUse="0" /> + </Channel3> + </TAU1> + <TMRJ0 InUse=""> + <R_TMR_RJ0_Create_UserInit UserName="R_TMR_RJ0_Create_UserInit" LibName="R_TMR_RJn_Create_UserInit" InUse="" /> + <r_tmr_rj0_interrupt UserName="r_tmr_rj0_interrupt" LibName="r_tmr_rjn_interrupt" INTHandle="" InUse="" /> + </TMRJ0> + <TMRD0 InUse=""> + <R_TMR_RD0_Create_UserInit UserName="R_TMR_RD0_Create_UserInit" LibName="R_TMR_RDn_Create_UserInit" InUse="" /> + <r_tmr_rd0_interrupt UserName="r_tmr_rd0_interrupt" LibName="r_tmr_rdn_interrupt" INTHandle="" InUse="" /> + </TMRD0> + <TMRD1 InUse=""> + <R_TMR_RD1_Create_UserInit UserName="R_TMR_RD1_Create_UserInit" LibName="R_TMR_RDn_Create_UserInit" InUse="" /> + <r_tmr_rd1_interrupt UserName="r_tmr_rd1_interrupt" LibName="r_tmr_rdn_interrupt" INTHandle="" InUse="" /> + </TMRD1> + </r_cg_timer_user.c> + <r_cg_timer.h UserName="r_cg_timer.h" LibName=".h" InUse="1" /> + </TAU> + <WDT> + <r_cg_wdt.c UserName="r_cg_wdt.c" LibName=".c" InUse="1"> + <Type R_WDT_Create="void R_WDT_Create(void)" R_WDT_Restart="void R_WDT_Restart(void)" /> + <R_WDT_Create UserName="R_WDT_Create" LibName="R_WDT_Create" InUse="1" Init="1" InitMode="" /> + <R_WDT_Restart UserName="R_WDT_Restart" LibName="R_WDT_Restart" InUse="1" /> + </r_cg_wdt.c> + <r_cg_wdt_user.c UserName="r_cg_wdt_user.c" LibName="_user.c" InUse="1"> + <Type R_WDT_Create_UserInit="void R_WDT_Create_UserInit(void)" r_wdt_interrupt="__interrupt static void r_wdt_interrupt(void)" /> + <R_WDT_Create_UserInit UserName="R_WDT_Create_UserInit" LibName="R_WDT_Create_UserInit" InUse="0" /> + <r_wdt_interrupt UserName="r_wdt_interrupt" INTHandle="" LibName="r_wdt_interrupt" InUse="1" /> + </r_cg_wdt_user.c> + <r_cg_wdt.h UserName="r_cg_wdt.h" LibName=".h" InUse="1" /> + </WDT> + <RTC> + <r_cg_rtc.c UserName="r_cg_rtc.c" LibName=".c" InUse="0"> + <Type R_RTC_Create="void R_RTC_Create(void)" R_RTC_Start="void R_RTC_Start(void)" R_RTC_Stop="void R_RTC_Stop(void)" R_RTC_Set_HourSystem="MD_STATUS R_RTC_SetHourSystem(rtc_hour_system_t hour_system)" R_RTC_Get_CounterValue="MD_STATUS R_RTC_Get_CounterValue(rtc_counter_value_t * const counter_read_val)" R_RTC_Set_CounterValue="MD_STATUS R_RTC_Set_CounterValue(rtc_counter_value_t counter_write_val)" R_RTC_Set_AlarmOn="void R_RTC_Set_AlarmOn(void)" R_RTC_Set_AlarmOff="void R_RTC_Set_AlarmOff(void)" R_RTC_Set_AlarmValue="void R_RTC_Set_AlarmValue(rtc_alarm_value_t alarm_val)" R_RTC_Get_AlarmValue="void R_RTC_Get_AlarmValue(rtc_alarm_value_t * const alarm_val)" R_RTC_Set_ConstPeriodInterruptOn="MD_STATUS R_RTC_Set_ConstPeriodInterruptOn(rtc_int_period_t period)" R_RTC_Set_ConstPeriodInterruptOff="void R_RTC_Set_ConstPeriodInterruptOff(void)" R_RTC_Set_RTC1HZOn="void R_RTC_Set_RTC1HZOn(void)" R_RTC_Set_RTC1HZOff="void R_RTC_Set_RTC1HZOff(void)" R_RTC_Set_PowerOff="void R_RTC_Set_PowerOff(void)" /> + <R_RTC_Create UserName="R_RTC_Create" LibName="R_RTC_Create" InUse="0" Init="1" InitMode="" /> + <R_RTC_Start UserName="R_RTC_Start" LibName="R_RTC_Start" InUse="0" /> + <R_RTC_Stop UserName="R_RTC_Stop" LibName="R_RTC_Stop" InUse="0" /> + <R_RTC_Set_HourSystem UserName="R_RTC_Set_HourSystem" LibName="R_RTC_Set_HourSystem" InUse="0" /> + <R_RTC_Get_CounterValue UserName="R_RTC_Get_CounterValue" LibName="R_RTC_Get_CounterValue" InUse="0" /> + <R_RTC_Set_CounterValue UserName="R_RTC_Set_CounterValue" LibName="R_RTC_Set_CounterValue" InUse="0" /> + <R_RTC_Set_AlarmOn UserName="R_RTC_Set_AlarmOn" LibName="R_RTC_Set_AlarmOn" InUse="0" /> + <R_RTC_Set_AlarmOff UserName="R_RTC_Set_AlarmOff" LibName="R_RTC_Set_AlarmOff" InUse="0" /> + <R_RTC_Set_AlarmValue UserName="R_RTC_Set_AlarmValue" LibName="R_RTC_Set_AlarmValue" InUse="0" /> + <R_RTC_Get_AlarmValue UserName="R_RTC_Get_AlarmValue" LibName="R_RTC_Get_AlarmValue" InUse="0" /> + <R_RTC_Set_ConstPeriodInterruptOn UserName="R_RTC_Set_ConstPeriodInterruptOn" LibName="R_RTC_Set_ConstPeriodInterruptOn" InUse="0" /> + <R_RTC_Set_ConstPeriodInterruptOff UserName="R_RTC_Set_ConstPeriodInterruptOff" LibName="R_RTC_Set_ConstPeriodInterruptOff" InUse="0" /> + <R_RTC_Set_RTC1HZOn UserName="R_RTC_Set_RTC1HZOn" LibName="R_RTC_Set_RTC1HZOn" InUse="0" /> + <R_RTC_Set_RTC1HZOff UserName="R_RTC_Set_RTC1HZOff" LibName="R_RTC_Set_RTC1HZOff" InUse="0" /> + <R_RTC_Set_PowerOff UserName="R_RTC_Set_PowerOff" LibName="R_RTC_Set_PowerOff" InUse="0" /> + </r_cg_rtc.c> + <r_cg_rtc_user.c UserName="r_cg_rtc_user.c" LibName="_user.c" InUse="0"> + <Type R_RTC_Create_UserInit="void R_RTC_Create_UserInit(void)" r_rtc_interrupt="__interrupt static void r_rtc_interrupt(void)" r_rtc_callback_constperiod="static void r_rtc_callback_constperiod(void)" r_rtc_callback_alarm="static void r_rtc_callback_alarm(void)" /> + <R_RTC_Create_UserInit UserName="R_RTC_Create_UserInit" LibName="R_RTC_Create_UserInit" InUse="0" /> + <r_rtc_interrupt UserName="r_rtc_interrupt" INTHandle="" LibName="r_rtc_interrupt" InUse="0" /> + <r_rtc_callback_constperiod UserName="r_rtc_callback_constperiod" LibName="r_rtc_callback_constperiod" InUse="0" /> + <r_rtc_callback_alarm UserName="r_rtc_callback_alarm" LibName="r_rtc_callback_alarm" InUse="0" /> + </r_cg_rtc_user.c> + <r_cg_rtc.h UserName="r_cg_rtc.h" LibName=".h" InUse="0" /> + </RTC> + <DTC InUse=""> + <r_cg_dtc.c UserName="r_cg_dtc.c" LibName=".c" InUse=""> + <Type R_DTC_Create="void R_DTC_Create(void)" R_DTCDn_Start="void R_DTCDn_Start(void)" R_DTCDn_Stop="void R_DTCDn_Stop(void)" R_DTC_Set_PowerOff="void R_DTC_Set_PowerOff(void)" /> + <R_DTC_Create UserName="R_DTC_Create" LibName="R_DTC_Create" InUse="" Init="2" InitMode="" /> + <DTCD0> + <R_DTCD0_Start LibName="R_DTCDn_Start" InUse="" Visible="False" /> + <R_DTCD0_Stop LibName="R_DTCDn_Stop" InUse="" Visible="False" /> + </DTCD0> + <DTCD1> + <R_DTCD1_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD1_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD1> + <DTCD2> + <R_DTCD2_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD2_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD2> + <DTCD3> + <R_DTCD3_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD3_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD3> + <DTCD4> + <R_DTCD4_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD4_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD4> + <DTCD5> + <R_DTCD5_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD5_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD5> + <DTCD6> + <R_DTCD6_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD6_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD6> + <DTCD7> + <R_DTCD7_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD7_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD7> + <DTCD8> + <R_DTCD8_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD8_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD8> + <DTCD9> + <R_DTCD9_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD9_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD9> + <DTCD10> + <R_DTCD10_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD10_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD10> + <DTCD11> + <R_DTCD11_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD11_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD11> + <DTCD12> + <R_DTCD12_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD12_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD12> + <DTCD13> + <R_DTCD13_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD13_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD13> + <DTCD14> + <R_DTCD14_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD14_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD14> + <DTCD15> + <R_DTCD15_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD15_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD15> + <DTCD16> + <R_DTCD16_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD16_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD16> + <DTCD17> + <R_DTCD17_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD17_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD17> + <DTCD18> + <R_DTCD18_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD18_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD18> + <DTCD19> + <R_DTCD19_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD19_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD19> + <DTCD20> + <R_DTCD20_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD20_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD20> + <DTCD21> + <R_DTCD21_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD21_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD21> + <DTCD22> + <R_DTCD22_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD22_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD22> + <DTCD23> + <R_DTCD23_Start LibName="R_DTCDn_Start" InUse="" Visible="false" /> + <R_DTCD23_Stop LibName="R_DTCDn_Stop" InUse="" Visible="false" /> + </DTCD23> + <DTCH0> + <R_DTCH0_Start LibName="R_DTCHn_Start" InUse="" Visible="false" /> + <R_DTCH0_Stop LibName="R_DTCHn_Stop" InUse="" Visible="false" /> + </DTCH0> + <DTCH1> + <R_DTCH1_Start LibName="R_DTCHn_Start" InUse="" Visible="false" /> + <R_DTCH1_Stop LibName="R_DTCHn_Stop" InUse="" Visible="false" /> + </DTCH1> + <R_DTC_Set_PowerOff UserName="R_DTC_Set_PowerOff" LibName="R_DTC_Set_PowerOff" InUse="" /> + </r_cg_dtc.c> + <r_cg_dtc_user.c UserName="r_cg_dtc_user.c" LibName="_user.c" InUse=""> + <Type R_DTC_Create_UserInit="void R_DTC_Create_UserInit(void)" /> + <R_DTC_Create_UserInit UserName="R_DTC_Create_UserInit" LibName="R_DTC_Create_UserInit" InUse="" /> + </r_cg_dtc_user.c> + <r_cg_dtc.h UserName="r_cg_dtc.h" LibName=".h" InUse="" /> + </DTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin"> + <r_cg_pclbuz.c UserName="r_cg_pclbuz.c" LibName=".c" InUse="0"> + <Type R_PCLBUZn_Create="void R_PCLBUZn_Create(void) " R_PCLBUZn_Start="void R_PCLBUZn_Start(void)" R_PCLBUZn_Stop="void R_PCLBUZn_Stop(void)" /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create UserName="R_PCLBUZ0_Create" LibName="R_PCLBUZn_Create" InUse="0" Init="1" InitMode="" /> + <R_PCLBUZ0_Start UserName="R_PCLBUZ0_Start" LibName="R_PCLBUZn_Start" InUse="0" /> + <R_PCLBUZ0_Stop UserName="R_PCLBUZ0_Stop" LibName="R_PCLBUZn_Stop" InUse="0" /> + </PCLBUZ0> + </r_cg_pclbuz.c> + <r_cg_pclbuz_user.c UserName="r_cg_pclbuz_user.c" LibName="_user.c" InUse="0"> + <Type R_PCLBUZn_Create_UserInit="void R_PCLBUZn_Create_UserInit(void) " /> + <PCLBUZ0 InUse=""> + <R_PCLBUZ0_Create_UserInit UserName="R_PCLBUZ0_Create_UserInit" LibName="R_PCLBUZn_Create_UserInit" InUse="0" Init="1" /> + </PCLBUZ0> + </r_cg_pclbuz_user.c> + <r_cg_pclbuz.h UserName="r_cg_pclbuz.h" LibName=".h" InUse="0" /> + </PCLBUZ> + <LVD> + <r_cg_lvd.c UserName="r_cg_lvd.c" LibName=".c" InUse="0"> + <Type R_LVD_Create="void R_LVD_Create(void)" R_LVD_InterruptMode_Start="void R_LVD_InterruptMode_Start(void)" /> + <R_LVD_Create UserName="R_LVD_Create" LibName="R_LVD_Create" InUse="0" Init="1" InitMode="" /> + <R_LVD_InterruptMode_Start UserName="R_LVD_InterruptMode_Start" LibName="R_LVD_InterruptMode_Start" InUse="0" /> + </r_cg_lvd.c> + <r_cg_lvd_user.c UserName="r_cg_lvd_user.c" LibName="_user.c" InUse="0"> + <Type R_LVD_Create_UserInit="void R_LVD_Create_UserInit(void)" r_lvd_interrupt="__interrupt static void r_lvd_interrupt(void)" /> + <R_LVD_Create_UserInit UserName="R_LVD_Create_UserInit" LibName="R_LVD_Create_UserInit" InUse="0" /> + <r_lvd_interrupt UserName="r_lvd_interrupt" INTHandle="" LibName="r_lvd_interrupt" InUse="0" /> + </r_cg_lvd_user.c> + <r_cg_lvd.h UserName="r_cg_lvd.h" LibName=".h" InUse="0" /> + </LVD> + </FUNC> + <TAG> + <GlobleUserTag> + <cg_security9 Name="cg_security9" Value="00" /> + <cg_security7 Name="cg_security7" Value="00" /> + <pior_value4 Name="pior_value4" Value="00" /> + <cg_security5 Name="cg_security5" Value="00" /> + <cg_crc_area Name="cg_crc_area" Value="00" /> + <ocdstart Name="ocdstart" Value="17E00" /> + <cg_security3 Name="cg_security3" Value="00" /> + <cg_security0 Name="cg_security0" Value="00" /> + <pior_value5 Name="pior_value5" Value="00" /> + <cg_security1 Name="cg_security1" Value="00" /> + <pior_value1 Name="pior_value1" Value="20" /> + <wdt_option Name="wdt_option" Value="F9" /> + <clock_option Name="clock_option" Value="F8" /> + <cg_option Name="cg_option" Value="04" /> + <cg_security8 Name="cg_security8" Value="00" /> + <cg_security6 Name="cg_security6" Value="00" /> + <pior_value0 Name="pior_value0" Value="00" /> + <cg_security4 Name="cg_security4" Value="00" /> + <cg_security2 Name="cg_security2" Value="00" /> + <cg_iawctl_value Name="cg_iawctl_value" Value="00" /> + <lvi_option Name="lvi_option" Value="33" /> + <pior_value7 Name="pior_value7" Value="00" /> + </GlobleUserTag> + </TAG> + </DIR> + <MACRO> + <CGC Prepared="true" SetFlag="True" NeedRefresh="False"> + <CGC SetFlag="True" MacroName="cgc" /> + </CGC> + <PORT HelpID="port" Prepared="true" SetFlag="True" NeedRefresh="False"> + <PORT SetFlag="True" MacroName="PORT" /> + </PORT> + <INTC SetFlag="" HelpID="int" NeedRefresh="False"> + <INTP Accelerate="No" MacroName="INTP" TabEnable="True" /> + <KEY Chip="RL78F13_48pin,RL78F13_64pin" MacroName="KEY" TabEnable="True" /> + </INTC> + <Serial SetFlag="False" HelpID="serial" NeedRefresh="False"> + <SAU0 Accelerate="No" MacroName="SAU" Channel="0" SetFlag="False" TabEnable="True"> + <Channel0 UART="0" CSI="00" IIC="00" Channel="0" /> + <Channel1 Chip="RL78F13_64pin,RL78F13_80pin,RL78F13_48pin,RL78F13_32pin" PIOR41="0" UART="0" CSI="01" IIC="01" Channel="1" /> + </SAU0> + <SAU1 Accelerate="No" MacroName="SAU" Channel="1" PIOR42="0" Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,groupc2" TabEnable="True"> + <Channel0 UART="1" CSI="10" IIC="10" Channel="0" /> + <Channel1 Chip="groupb,groupc2" PIOR43="0" UART="1" CSI="11" IIC="11" Channel="1" /> + </SAU1> + <IICA0 Accelerate="No" Chip="groupb,R5F10BBC,R5F10BBD,R5F10BBE,R5F10BBF,R5F10BBG,R5F10BGC,R5F10BGD,R5F10BGE,R5F10BGF,R5F10BGG,R5F10BLC,R5F10BLD,R5F10BLE,R5F10BLF,R5F10BLG,R5F10BME,R5F10BMF,R5F10BMG" MacroName="IICA" Channel="0" TabEnable="True" /> + </Serial> + <ADC SetFlag="True" HelpID="adc" NeedRefresh="False"> + <ADC SetFlag="True" MacroName="ADC" /> + </ADC> + <TAU SetFlag="True" HelpID="timer" NeedRefresh="False"> + <TAU0 Accelerate="No" MacroName="TAU" Channel="0" ChannelNum="0,1,2,3,4,5,6,7" SetFlag="True" TabEnable="True" /> + <TAU1 Accelerate="No" Chip="groupb,groupc1,groupc2" MacroName="TAU" Channel="1" ChannelNum="0,1,2,3" SetFlag="False" TabEnable="True" /> + <TMRJ0 SetFlag="" MacroName="TMRJ" Channel="0" TabEnable="True" /> + <TMRD0 SetFlag="" MacroName="TMRD" Channel="0" TabEnable="True" /> + <TMRD1 SetFlag="" MacroName="TMRD" Channel="1" TabEnable="True" /> + </TAU> + <WDT Prepared="true" SetFlag="True" HelpID="watchdogtimer" NeedRefresh="False"> + <WDT SetFlag="True" MacroName="WDT" /> + </WDT> + <RTC SetFlag="False" HelpID="rtc" NeedRefresh="False"> + <RTC MacroName="RTC" SetFlag="False" /> + </RTC> + <DTC HelpID="dtc" SetFlag="" NeedRefresh="False"> + <DTC SetFlag="" /> + </DTC> + <PCLBUZ Chip="RL78F13_48pin,RL78F13_64pin,RL78F13_80pin" SetFlag="False" HelpID="PCLBUZ" NeedRefresh="False"> + <PCLBUZ0 MacroName="PCLBUZ" Channel="0" SetFlag="False" /> + </PCLBUZ> + <LVD SetFlag="True" Prepared="true" NeedRefresh="False"> + <LVD MacroName="LVD" SetFlag="True" /> + </LVD> + </MACRO> + <SETTING> + <CGC> + <setting name="PIN_ASSIGNMENT_FIX_SETTING" value="false" /> + <setting name="OPERATION_MODE_HS_27_55" value="false" /> + <setting name="OPERATION_MODE_HS_40_55" value="true" /> + <setting name="MAIN_CLOCK_SELECT_HIGH_SYSTEM_CLOCK" value="false" /> + <setting name="MAIN_CLOCK_SELECT_HIGH_INTERNAL_CLOCK" value="true" /> + <setting name="INTERNAL_HIGH_CLOCK_OPERATION" value="true" /> + <setting name="INTERNAL_HIGH_CLOCK_FREQUENCY" value="8" /> + <setting name="HIGH_SYSTEM_CLOCK_OPERATION" value="false" /> + <setting name="HIGH_SYSTEM_CLOCK_SELECT_EXTERNAL_CLOCK" value="false" /> + <setting name="HIGH_SYSTEM_CLOCK_SELECT_X1_CLOCK" value="true" /> + <setting name="X1_CLOCK_STABLE_TIME" value="7" /> + <setting name="HIGH_SYSTEM_CLOCK_FREQUENCY" value="5" /> + <setting name="SUBCLOCK_SELECT_XT1_CLOCK" value="true" /> + <setting name="SUBCLOCK_XT1_OSCILLATION_MODE" value="0" /> + <setting name="SUBCLOCK_OPERATION" value="false" /> + <setting name="SUBCLOCK_SELECT_EXTERNAL_CLOCK" value="false" /> + <setting name="SUBCLOCK_HALT_STOP_STATUS" value="0" /> + <setting name="CPU_PERIPHERAL_CLOCK_FREQUENCY" value="0" /> + <setting name="FPLL_FREQUENCY_VALUE" value="0" /> + <setting name="FPLL_FREQUENCY_OPERATION" value="false" /> + <setting name="FPLL_LOCKUP_WAIT_COUNTER" value="0" /> + <setting name="FMP_FREQUENCY_VALUE" value="0" /> + <setting name="TRD_FREQUENCY_VALUE" value="0" /> + <setting name="FSL_FREQUENCY_VALUE" value="0" /> + <setting name="RTC_IT_CLOCK" value="0" /> + <setting name="OCD_UNUSED" value="true" /> + <setting name="OCD_USED" value="false" /> + <setting name="RRM_UNUSED" value="false" /> + <setting name="RRM_USED" value="true" /> + <setting name="TRACE_UNUSED" value="false" /> + <setting name="TRACE_USED" value="true" /> + <setting name="HOTPLUG_UNUSED" value="true" /> + <setting name="HOTPLUG_USED" value="false" /> + <setting name="SECURITY_ID_AUTHENTICATION_ERASE" value="true" /> + <setting name="SECURITY_ID_AUTHENTICATION_NOT_ERASE" value="false" /> + <setting name="SECURITY_ID_SELECT" value="true" /> + <setting name="SECURITY_ID_VALUE" value="0x00000000000000000000" /> + <setting name="RESET_SOURCE_FUNCTION_OUTPUT" value="true" /> + <setting name="RESOUT_UNUSED" value="true" /> + <setting name="RESOUT_USED" value="false" /> + <setting name="ILLEGAL_MEMORY_ACCESS_UNUSED" value="true" /> + <setting name="ILLEGAL_MEMORY_ACCESS_USED" value="false" /> + <setting name="RAM_GUARD_UNUSED" value="true" /> + <setting name="RAM_GUARD_USED" value="false" /> + <setting name="RAM_GUARD_AREA" value="0" /> + <setting name="PORT_GUARD_UNUSED" value="true" /> + <setting name="PORT_GUARD_USED" value="false" /> + <setting name="INTERRUPT_GUARD_UNUSED" value="true" /> + <setting name="INTERRUPT_GUARD_USED" value="false" /> + <setting name="CHIP_CONTROL_GUARD_UNUSED" value="true" /> + <setting name="CHIP_CONTROL_GUARD_USED" value="false" /> + <setting name="STACKPOINTER_INTERRUPT_PRIORITY" value="3" /> + <setting name="STACKPOINTER_INTERRUPT_USED" value="true" /> + <setting name="CLOCK_MONITOR_INTERRUPT_PRIORITY" value="3" /> + <setting name="CLOCK_MONITOR_INTERRUPT_USED" value="true" /> + <setting name="CLOCK_MONITOR_UNUSED" value="true" /> + <setting name="CLOCK_MONITOR_USED" value="false" /> + <setting name="STACK_POINTER_UNUSED" value="true" /> + <setting name="STACK_POINTER_USED" value="false" /> + <setting name="STACK_POINTER_UNDERFLOW_DATA" value="0x0000" /> + <setting name="STACK_POINTER_OVERFLOW_DATA" value="0xFFFE" /> + <setting name="RAM_ECC_INTERRUPT_USED" value="false" /> + <setting name="RAM_ECC_INTERRUPT_PRIORITY" value="3" /> + <setting name="DataFlash" value="unused" /> + <setting name="ProgramFlash" value="unused" /> + <setting name="Monitor" value="unused" /> + <setting name="StartStop" value="unused" /> + <setting name="Emulator" value="E1" /> + </CGC> + <PORT> + <PortP0> + <P00> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P00> + </PortP0> + <PortP1> + <P10> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P10> + <P11> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P11> + <P12> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P12> + <P13> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P13> + <P14> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P14> + <P15> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P15> + <P16> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P16> + <P17> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P17> + </PortP1> + <PortP3> + <P30> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P30> + <P31> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P31> + <P32> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P32> + <P33> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P33> + <P34> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P34> + </PortP3> + <PortP4> + <P40> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="true" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P40> + <P41> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P41> + </PortP4> + <PortP6> + <P60> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P60> + <P61> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P61> + <P62> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P62> + <P63> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P63> + </PortP6> + <PortP7> + <P70> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P70> + <P71> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P71> + <P72> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P72> + <P73> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P73> + </PortP7> + <PortP8> + <P80> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P80> + <P81> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P81> + <P82> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P82> + <P83> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P83> + <P84> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P84> + <P85> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P85> + <P86> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P86> + <P87> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P87> + </PortP8> + <PortP9> + <P90> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P90> + <P91> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P91> + <P92> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P92> + </PortP9> + <PortP12> + <P120> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P120> + <P121> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P121> + <P122> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P122> + <P123> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P123> + <P124> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P124> + <P125> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="true" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="0" /> + <setting name="PSRSEL" value="false" /> + </P125> + </PortP12> + <PortP13> + <P130> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P130> + <P137> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="false" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P137> + </PortP13> + <PortP14> + <P140> + <setting name="MODULE_UNUSED" value="false" /> + <setting name="INPUT_MODE" value="false" /> + <setting name="OUTPUT_MODE" value="true" /> + <setting name="PULLUP_ON" value="false" /> + <setting name="NCH_ON" value="false" /> + <setting name="OUTPUT_1" value="false" /> + <setting name="INPUT_BUFFER" value="-1" /> + <setting name="PSRSEL" value="false" /> + </P140> + </PortP14> + </PORT> + <TAU0> + <Channel0> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval0> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="-1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="-1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="unused" /> + </TAUInterval0> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="1" /> + <setting name="Pinselection" value="-1" /> + <TAUInterval1> + <setting name="OperationMode" value="16bits" /> + <setting name="Count_clock" value="MCK clock" /> + <setting name="Sub_clock_mode" value="-1" /> + <setting name="Interval_value" value="1000" /> + <setting name="Value_scale" value="1" /> + <setting name="Intervalvalue_High8bits" value="100" /> + <setting name="Intervalvalue_High8bits_scale" value="1" /> + <setting name="Intervalvalue_Low8bits" value="100" /> + <setting name="Intervalvalue_Low8bits_Scale" value="1" /> + <setting name="Generate_interrupt_when_couting_started" value="no" /> + <setting name="Interrupt" value="used" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="InterruptH_priority" value="3" /> + <setting name="InterruptH8" value="used" /> + </TAUInterval1> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + <Channel4> + <setting name="ChannelFunction" value="7" /> + <setting name="Pinselection" value="-1" /> + <TAUPWMMaster4> + <PWMMaster4> + <setting name="Value_scale" value="1" /> + <setting name="PWM_cycle" value="1000" /> + <setting name="Master_interrupt_priority" value="3" /> + <setting name="Master_interrupt" value="unused" /> + </PWMMaster4> + <PWMSlave5> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="unused" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave5> + <PWMSlave6> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="used" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave6> + <PWMSlave7> + <setting name="PWM_duty" value="50" /> + <setting name="OuputLevel" value="0" /> + <setting name="OuputValue" value="0" /> + <setting name="Slave_interrupt_priority" value="3" /> + <setting name="Slave_interrupt" value="used" /> + <setting name="OuputTime" value="0" /> + <setting name="TauPWMSlave cbPSRSEL" value="false" /> + </PWMSlave7> + </TAUPWMMaster4> + </Channel4> + <Channel5> + <setting name="ChannelFunction" value="9" /> + <setting name="Pinselection" value="-1" /> + </Channel5> + <Channel6> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel6> + <Channel7> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel7> + </TAU0> + <TAU1> + <Channel0> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel0> + <Channel1> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel1> + <Channel2> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel2> + <Channel3> + <setting name="ChannelFunction" value="0" /> + <setting name="Pinselection" value="-1" /> + </Channel3> + </TAU1> + <TMRJ0> + <setting name="Function" value="Unused" /> + </TMRJ0> + <TMRD0> + <setting name="Function" value="Unused" /> + </TMRD0> + <TMRD1> + <setting name="Function" value="Unused" /> + </TMRD1> + <SAU0> + <IIC00 /> + <CSI00 /> + <UART0 /> + <Channel0> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel0> + <IIC01 /> + <CSI01 /> + <Channel1> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel1> + </SAU0> + <SAU1> + <Channel0> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel0> + <UART1 /> + <Channel1> + <setting name="CHANNEL_FUNCTION" value="0" /> + <setting name="DETAIL_FUNCTION" value="-1" /> + </Channel1> + <IIC10 /> + <CSI10 /> + <IIC11 /> + <CSI11 /> + </SAU1> + <IICA0> + <setting name="SLAVE_MODE_USED" value="false" /> + <setting name="MODULE_UNUSE" value="true" /> + <setting name="SINGLE_MASTER_USED" value="false" /> + </IICA0> + <ADC> + <setting name="ADC_USED" value="true" /> + <setting name="ADC_UNUSED" value="false" /> + <setting name="ADC_COMPARATOR_ENABLE" value="true" /> + <setting name="ADC_COMPARATOR_DISABLE" value="false" /> + <setting name="ADC_RESOLUTION_10BIT" value="true" /> + <setting name="ADC_RESOLUTION_8BIT" value="false" /> + <setting name="ADC_POSITIVE_VDD" value="true" /> + <setting name="ADC_POSITIVE_AVREFP" value="false" /> + <setting name="ADC_POSITIVE_BGR" value="false" /> + <setting name="ADC_NEGATIVE_VSS" value="true" /> + <setting name="ADC_NEGATIVE_AVREFM" value="false" /> + <setting name="ADC_TRIGGER_SOFTWARE" value="false" /> + <setting name="ADC_TRIGGER_HARDWARE_NOWAIT" value="true" /> + <setting name="ADC_TRIGGER_HARDWARE_WAIT" value="false" /> + <setting name="ADC_TRIGGER_SOURCE_UPDATE" value="0" /> + <setting name="ADC_CONTINUOUS_SELECT_MODE" value="true" /> + <setting name="ADC_ONESHOT_SELECT_MODE" value="false" /> + <setting name="ADC_CONTINUOUS_SCAN_MODE" value="false" /> + <setting name="ADC_ONESHOT_SCAN_MODE" value="false" /> + <setting name="ADC_ANALOG_INPUT_SELECTION" value="9" /> + <setting name="ANALOG_INPUT_24" value="false" /> + <setting name="ANALOG_INPUT_25" value="false" /> + <setting name="ANALOG_INPUT_26" value="true" /> + <setting name="ADC_CONVERSION_MODE" value="0" /> + <setting name="ADC_CONVERSION_TIME" value="0" /> + <setting name="ADC_INTERRUPT_GENERATE_CONDITION_1" value="true" /> + <setting name="ADC_INTERRUPT_GENERATE_CONDITION_2" value="false" /> + <setting name="ADC_UPPER_BOUND_VALUE" value="255" /> + <setting name="ADC_LOWER_BOUND_VALUE" value="0" /> + <setting name="ADC_INTERRUPT_PRIORITY" value="3" /> + <setting name="ADC_INTERRUPT_USED" value="true" /> + <setting name="ANALOG_INPUT_30" value="true" /> + <setting name="ANALOG_INPUT_29" value="true" /> + <setting name="ANALOG_INPUT_28" value="true" /> + <setting name="ANALOG_INPUT_27" value="true" /> + <setting name="ADC_CHANNEL_SELECTION" value="0" /> + </ADC> + <WDT> + <setting name="WDT_MODULE_USED" value="true" /> + <setting name="WDT_MODULE_UNUSE" value="false" /> + <setting name="WDT_OVERFLOW_TIME" value="4" /> + <setting name="WDT_WINDOW_OPEN_TIME" value="2" /> + <setting name="WDT_HALT_STOP_OPERATION_ENABLE" value="true" /> + <setting name="WDT_HALT_STOP_OPERATION_STOP" value="false" /> + <setting name="WDT_INTERRUPT_USED" value="true" /> + <setting name="WDT_INTERRUPT_PRIORITY" value="3" /> + </WDT> + <RTC> + <setting name="INITIAL_VALUE" value="01/01/2000 00:00:00" /> + <setting name="ALARM_WEEK_DAY" value="Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_Unchecked_" /> + <setting name="ALARM_TIME" value="01/01/2000 00:00:00" /> + <setting name="MODULE_USED" value="false" /> + <setting name="MODULE_UNUSED" value="true" /> + <setting name="ALARM_OPERATION_USED" value="false" /> + <setting name="HOUR_SYSTEM" value="0" /> + <setting name="INITIAL_VALUE_USED" value="false" /> + <setting name="ALARM_VALUE_USED" value="false" /> + <setting name="INTERRUPT_PRIORITY" value="3" /> + <setting name="CONSTANT_INTERRUPT_USED" value="false" /> + <setting name="CONSTANT_INTERRUPT_VALUE" value="0" /> + <setting name="ALARM_INTERRUPT_USED" value="true" /> + <setting name="RTC1HZ_OUTPUT_USED" value="false" /> + <setting name="RTC1HZ_OUTPUTPIN_SEL" value="-1" /> + </RTC> + <PCLBUZ0> + <setting name="PCLBUZ_clock" value="16000 (fMAIN/2^2)(kHZ)" /> + <setting name="PCLBUZ_USED" value="false" /> + <setting name="PCLBUZ_UNUSED" value="true" /> + <setting name="PCLBUZ_OUTPUT_CLOCK" value="0" /> + <setting name="PCLBUZ_PSRSEL_USE" value="false" /> + </PCLBUZ0> + <LVD> + <setting name="Operation" value="used" /> + <setting name="Reset_only_level" value="3" /> + <setting name="InterruptReset_level" value="0" /> + <setting name="Interrupt_level" value="0" /> + <setting name="Interrupt_only_level" value="0" /> + <setting name="operation_mode" value="reset" /> + <setting name="Interrupt_priority" value="3" /> + <setting name="Interrupt_only_priority" value="3" /> + </LVD> + </SETTING> +</RL78F13> + + + \ No newline at end of file diff --git a/app/DataFlash/pfdl.h b/app/DataFlash/pfdl.h new file mode 100644 index 0000000..a670b56 --- /dev/null +++ b/app/DataFlash/pfdl.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* Library : Flash Data Library T04 (PicoFDL) +* +* File Name : $Source: pfdl.h $ +* Lib. Version : $RL78_FDL_LIB_VERSION_T04_REN: V1.05 $ +* Mod. Revision : $Revision: 1.8 $ +* Mod. Date : $Date: 2013/06/10 22:04:41JST $ +* Device(s) : RL78 +* Description : C language API definition of the Flash Data Library +******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011-2013 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + + +#ifndef __PFDL_H_INCLUDED +#define __PFDL_H_INCLUDED + +/*================================================================================================*/ +/* include files list */ +/*================================================================================================*/ +#include "pfdl_types.h" + +#define FLASH_START_ADDRESS (0xF1000) /* Start address of data flash */ +#define TARGET_BLOCK (0) /* Block number of target(0 ~ 3) */ +#define BLOCK_SIZE (0x400) /* Block size */ +//#define WRITE_SIZE (1) /* Size of data to be written at once */ +#define MAX_VALUE (0xFF) /* Maximum value of writing */ +#define MAX_ADDRESS ((TARGET_BLOCK + 1) * BLOCK_SIZE - 1) /* Maximum address of writing */ +#define PFDL_NG (1) /* Failure to Data Flash */ +#define FDL_FRQ (32) /* Setting frequency (MHz) */ +#define FDL_VOL (0x00) /* Voltage mode */ + +uint8_t WriteDataflash(uint8_t* buffer,uint32_t Addr,uint16_t lenth); +uint8_t WriteDataflash1(uint8_t* buffer,uint32_t Addr,uint16_t lenth); + +void ReadFlashData(uint8_t* buffer,uint32_t Addr,uint16_t lenth); +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Block type: standard function */ +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Purpose: Unconditional activation of the Data Flash Library. */ +/* Based on the descriptor data: */ +/* - the flash firmware will be initialized for data-flash access only */ +/* - the internal timing and low-voltage capability will be configured according to the descriptor */ +/* After successful initialization the data flash clock is ON and the PFDL is ready to use. */ +/* */ +/* CAUTION: */ +/* Due to the code size minimization no plausibility checks are done by the PicoFDL. */ +/* Neither configuration, frequency range nor data flash size will be checked by the library. */ +/* */ +/* Input: address of the PFDL descriptor variable (RAM only) */ +/* Output: - */ +/* Return: PFDL status */ +/* ---------------------------------------------------------------------------------------------------------------*/ +extern pfdl_status_t __far PFDL_Open(__near pfdl_descriptor_t* descriptor_pstr); + + + + +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Block type: standard function */ +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Purpose: Disable data flash access unconditionally. */ +/* If any command is just executed, PFDL_Close will stop it immediately. */ +/* After return the data flash clock is switched OFF. */ +/* Input: - */ +/* Output: - */ +/* Return: - */ +/* ---------------------------------------------------------------------------------------------------------------*/ +extern void __far PFDL_Close(void); + + + +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Block type: standard function */ +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Purpose: Initiating execution of the PFDL request related to the data flash. */ +/* The corresponding request variable has to be parametrized before. */ +/* */ +/* request_pstr->index_u16 : byte-index or block-number within PFDL-pool */ +/* request_pstr->data_pu08 : start address of the RAM data that should be read/written */ +/* request_pstr->bytecount_u16 : number of bytes has to be read/written */ +/* request_pstr->command_enu : command code */ +/* */ +/* CAUTION: */ +/* Due to the code size minimization no plausibility checks are done by the PFDL. */ +/* */ +/* Input: &request_pstr - pointer to PFDL request variable */ +/* Output: - */ +/* Return: status of the request */ +/* ---------------------------------------------------------------------------------------------------------------*/ +extern pfdl_status_t __far PFDL_Execute(__near pfdl_request_t* request_pstr); + + + +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Block type: standard function */ +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Purpose: Continuation of command execution and status update of requests being under execution. */ +/* Input: - */ +/* Output: - */ +/* Return: PFDL status = */ +/* PFDL_IDLE - no request is processed by PFDL, PFDL is ready to receive new requests */ +/* PFDL_OK - processed request/command finished without problems */ +/* PFDL_BUSY - request/command is still being processed */ +/* other - flash or firmware related errors */ +/* ---------------------------------------------------------------------------------------------------------------*/ +extern pfdl_status_t __far PFDL_Handler(void); + + + +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Block type: standard function */ +/* ---------------------------------------------------------------------------------------------------------------*/ +/* Purpose: Returns the start address of the library version string */ +/* */ +/* Input: - */ +/* Output: - */ +/* Return: starting address of the zero-terminated version string */ +/* ---------------------------------------------------------------------------------------------------------------*/ +extern __far pfdl_u08* __far PFDL_GetVersionString(void); + + + +#endif diff --git a/app/DataFlash/pfdl.lib b/app/DataFlash/pfdl.lib new file mode 100644 index 0000000..81b7bb6 Binary files /dev/null and b/app/DataFlash/pfdl.lib differ diff --git a/app/DataFlash/pfdl_types.h b/app/DataFlash/pfdl_types.h new file mode 100644 index 0000000..4f3837d --- /dev/null +++ b/app/DataFlash/pfdl_types.h @@ -0,0 +1,146 @@ +/******************************************************************************* +* Library : Flash Data Library T04 (PicoFDL) +* +* File Name : $Source: pfdl_types.h $ +* Lib. Version : $RL78_FDL_LIB_VERSION_T04_REN: V1.05 $ +* Mod. Revision : $Revision: 1.8 $ +* Mod. Date : $Date: 2013/06/10 22:28:01JST $ +* Device(s) : RL78 +* Description : Type definitions used by the library +******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011-2013 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + + +#ifndef __PFDL_TYPES_H_INCLUDED +#define __PFDL_TYPES_H_INCLUDED + + + + +#ifndef __TYPEDEF__ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef unsigned short MD_STATUS; +#define __TYPEDEF__ +#endif +/*==============================================================================================*/ +/* unsigned type definitions */ +/*==============================================================================================*/ +typedef unsigned char pfdl_u08; +typedef unsigned int pfdl_u16; +typedef unsigned long int pfdl_u32; + + +/*==============================================================================================*/ +/* global constant definitions */ +/*==============================================================================================*/ + + + +/*==============================================================================================*/ +/* global type definitions */ +/*==============================================================================================*/ + + +/* PFDL command code set */ +typedef enum +{ /* ---------------------------------------------- */ + PFDL_CMD_READ_BYTES = (0x00), /* 0x00, reads data from flash memory */ + PFDL_CMD_IVERIFY_BYTES = (0x06), /* 0x06, verifies data if flash content is stable */ + PFDL_CMD_BLANKCHECK_BYTES = (0x08), /* 0x08, checks if flash content is blank */ + PFDL_CMD_WRITE_BYTES = (0x04), /* 0x04, writes data into flash memory */ + PFDL_CMD_ERASE_BLOCK = (0x03) /* 0x03, erases one flash block */ +} pfdl_command_t; /* ---------------------------------------------- */ + + +/* PFDL error code set */ +typedef enum +{ + /* operation related status */ /* ---------------------------------------------- */ + PFDL_IDLE = (0x30), /* 0x30, PFDL ready to receive requests */ + PFDL_OK = (0x00), /* 0x00, command finished without problems */ + PFDL_BUSY = (0xFF), /* 0xFF, command is being processed */ + /* flash related status */ /* ---------------------------------------------- */ + PFDL_ERR_PROTECTION = (0x10), /* 0x10, protection error (access right conflict) */ + PFDL_ERR_ERASE = (0x1A), /* 0x1A, erase error */ + PFDL_ERR_MARGIN = (0x1B), /* 0x1B, blankcheck or verify margin violated */ + PFDL_ERR_WRITE = (0x1C), /* 0x1C, write error */ + PFDL_ERR_PARAMETER = (0x05) /* 0x05, parameter error */ +} pfdl_status_t; /* ---------------------------------------------- */ + + +/* PFDL request type (base type for any PFDL access) */ +typedef struct +{ /* ---------------------------------------------- */ + pfdl_u16 index_u16; /* 2, W, virt. byte/block index inside PFDL-pool */ + __near pfdl_u08* data_pu08; /* 2, W, pointer to the 1'st byte of data buffer */ + pfdl_u16 bytecount_u16; /* 2, W, number of bytes to be transfered */ + pfdl_command_t command_enu; /* 1, W, command code */ +} pfdl_request_t; /*------------------------------------------------*/ + /* 7 bytes in total */ + /*------------------------------------------------*/ + +/* PFDL descriptor type */ +typedef struct +{ /* ---------------------------------------------- */ + pfdl_u08 fx_MHz_u08; /* 1, system frequency expressed in MHz */ + pfdl_u08 wide_voltage_mode_u08; /* 1, programming voltage mode ( full/wide ) */ +} pfdl_descriptor_t; /*------------------------------------------------*/ + /* 2 bytes in total */ + + +/*==============================================================================================*/ +/* type definition plausibility check */ +/*==============================================================================================*/ + +/* The following checks are implemented in order to check the correct size of the FDL type */ +/* definitions at compile time. In case of a compilation error in the following lines, please */ +/* check your compiler options for enumeration types and structures and contact your local */ +/* support, if necessary. */ + +#define R_PFDLT04_ASSERT_CONCAT_(a, b) a##b +#define R_PFDLT04_ASSERT_CONCAT(a, b) R_PFDLT04_ASSERT_CONCAT_(a, b) +#define R_PFDLT04_STATIC_ASSERT(e) enum { R_PFDLT04_ASSERT_CONCAT(R_PFDLT04_ASSERT_LINE_, __LINE__) = 1/(!!(e)) } + + +/* assertion if unsigned data type size is not correct, please evaluate compiler settings for integer types */ +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_u08)==1); +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_u16)==2); +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_u32)==4); + +/* assertion if unsigned data type size is not correct, please evaluate compiler settings for enumeration types */ +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_command_t)==1); +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_status_t)==1); + +/* assertion if structure type size is not correct, please evaluate compiler settings for structure types */ +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_request_t)>=7); /* sizeof(pfdl_request_t) == 7 for packed structures */ +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_request_t)<=8); /* sizeof(pfdl_request_t) == 8 for unpacked structures */ +R_PFDLT04_STATIC_ASSERT(sizeof(pfdl_descriptor_t)==2); + + +#endif diff --git a/app/DataFlash/r_pfdl.c b/app/DataFlash/r_pfdl.c new file mode 100644 index 0000000..bb1ab0c --- /dev/null +++ b/app/DataFlash/r_pfdl.c @@ -0,0 +1,303 @@ + + +#include "r_cg_macrodriver.h" + +#include "pfdl.h" +#include "pfdl_types.h" + +/*********************************************************************************************************************** +* Function Name: WriteDataflash +* Description : +* Arguments : buffer: to be writed data; Addr:Target absolute address,must be check for different mcu;lenth:to be writed number,<=1024 +* Return Value : PFDL_OK - + Success + PFDL_IDLE - + Idling statement + PFDL_ERR_MARGIN - + Blank check error + + other//if(Addr>=FLASH_START_ADDRESS&&Addr=0x000F1000 && Addr<0x000F2000) + { + if(Wr_Status == 0) + { + /* ---- Setting for PFDL_Open ---- */ + descriptor.fx_MHz_u08 = FDL_FRQ; + descriptor.wide_voltage_mode_u08 = FDL_VOL; + PFDL_Open(&descriptor); + + /* ---- Setting for blank check ---- */ + requester.command_enu = PFDL_CMD_BLANKCHECK_BYTES; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000);//g_write_address;0x0F1000 according to MCU + requester.bytecount_u16 = lenth; + ret = PFDL_Execute(&requester); /* Blank check */ + Wr_Status = 1; + } + + if(Wr_Status == 1) + { + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } + if(ret != PFDL_BUSY) + { + /* **** When blank check error **** */ + if(ret == PFDL_ERR_MARGIN) + { + + /* ---- Setting for erase ---- */ + requester.command_enu = PFDL_CMD_ERASE_BLOCK; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000)/0x400;//TARGET_BLOCK; + ret = PFDL_Execute(&requester); /* Erase block data */ + Wr_Status = 2; + /* Erase data of target block */ + } + /* **** When other than blank check error **** */ + else + { + /* Do nothing */ + } + + /******When blank no check error***/ + if(ret == PFDL_OK) + { + /* ---- Setting for write ---- */ + requester.command_enu = PFDL_CMD_WRITE_BYTES; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000);//g_write_address;; + requester.bytecount_u16 = lenth; + requester.data_pu08 = buffer;//&g_write_value; + ret = PFDL_Execute(&requester); /* Execute write */ + Wr_Status = 3; + } + } + } + + if(Wr_Status == 2) + { + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } + if(ret != PFDL_BUSY) + { + if(ret == PFDL_OK) + { + /* ---- Setting for write ---- */ + requester.command_enu = PFDL_CMD_WRITE_BYTES; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000);//g_write_address;; + requester.bytecount_u16 = lenth; + requester.data_pu08 = buffer;//&g_write_value; + ret = PFDL_Execute(&requester); /* Execute write */ + Wr_Status = 3; + } + /* **** When blank check or data erase is failure **** */ + else + { + ret = PFDL_NG; + //PFDL_Close(); /* Close FDL */ + //Wr_Status = 0; + return ret; + } + } + } + + if(Wr_Status == 3) + { + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } + if(ret != PFDL_BUSY) + { + /* ==== When write data is success ==== */ + if(ret == PFDL_OK) + { + /* ---- Setting for verify ---- */ + requester.command_enu = PFDL_CMD_IVERIFY_BYTES; + requester.index_u16 = (unsigned int)(Addr- 0x0F1000);//g_write_address;; + requester.bytecount_u16 = lenth; + ret = PFDL_Execute(&requester); /* Execute internal verify */ + Wr_Status = 4; + } + /* ==== When writing data is failure ==== */ + else + { + ret = PFDL_NG; + //PFDL_Close(); /* Close FDL */ + //Wr_Status = 0; + return ret; + } + } + } + + if(Wr_Status == 4) + { + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } + if(ret != PFDL_BUSY) + { + PFDL_Close(); /* Close FDL */ + Wr_Status = 0; + return 0x11;//write data flash finished + } + } + } + else + { + ret = PFDL_NG; + Wr_Status = 0; + return ret; + } +} + + +uint8_t WriteDataflash1(uint8_t* buffer,uint32_t Addr,uint16_t lenth) +{ + pfdl_status_t ret; + pfdl_descriptor_t descriptor; + pfdl_request_t requester; + + if(Addr>=0x000F1000&&Addr<0x000F2000){ + /* ---- Setting for PFDL_Open ---- */ + descriptor.fx_MHz_u08 = FDL_FRQ; + descriptor.wide_voltage_mode_u08 = FDL_VOL; + PFDL_Open(&descriptor); + + /* ---- Setting for blank check ---- */ + requester.command_enu = PFDL_CMD_BLANKCHECK_BYTES; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000);//g_write_address;0x0F1000 according to MCU + requester.bytecount_u16 = lenth; + ret = PFDL_Execute(&requester); /* Blank check */ + + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } + + /* **** When blank check error **** */ + if(ret == PFDL_ERR_MARGIN) + { + + /* ---- Setting for erase ---- */ + requester.command_enu = PFDL_CMD_ERASE_BLOCK; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000)/0x400;//TARGET_BLOCK; + ret = PFDL_Execute(&requester); /* Erase block data */ + + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } /* Erase data of target block */ + } + /* **** When other than blank check error **** */ + else + { + /* Do nothing */ + } + + if(ret == PFDL_OK) + { + /* ---- Setting for write ---- */ + requester.command_enu = PFDL_CMD_WRITE_BYTES; + requester.index_u16 = (unsigned int)(Addr - 0x0F1000);//g_write_address;; + requester.bytecount_u16 = lenth; + requester.data_pu08 = buffer;//&g_write_value; + ret = PFDL_Execute(&requester); /* Execute write */ + + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler(); /* Status check process */ + } /* Write data process */ + /* ==== When write data is success ==== */ + + if(ret == PFDL_OK) + { + /* ---- Setting for verify ---- */ + requester.command_enu = PFDL_CMD_IVERIFY_BYTES; + requester.index_u16 = (unsigned int)(Addr- 0x0F1000);//g_write_address;; + requester.bytecount_u16 = lenth; + ret = PFDL_Execute(&requester); /* Execute internal verify */ + + /* ---- Waiting for command finish ---- */ + while(ret == PFDL_BUSY) + { + ret = PFDL_Handler();/* Status check process */ + } + + } + /* ==== When writing data is failure ==== */ + else + { + ret = PFDL_NG; + } + } + /* **** When blank check or data erase is failure **** */ + else + { + ret = PFDL_NG; + } + + PFDL_Close(); /* Close FDL */ + + return ret; + } + else{ + ret = PFDL_NG; + return ret; + } +} + + +/*********************************************************************************************************************** +* Function Name: ReadFlashData +* Description : +* Arguments : buffer: to be read data; + Addr:Target absolute address,must be check for different mcu; Both codeflash & dataflash can be used + lenth:to be read number +* Return Value : None +***********************************************************************************************************************/ + +void ReadFlashData(uint8_t* buffer,uint32_t Addr,uint16_t lenth) +{ + uint8_t temp; + volatile uint32_t w_count; + volatile uint8_t * snnumber; + /**** Only dataflash needed start*****/ + if(0 == DFLEN) + { + DFLEN = 1U; //ȡ + for (w_count = 0U; w_count < 15U; w_count++)//3U + { + NOP(); //ʱӲӦʱ + } + } + /**** Only dataflash needed end******/ + snnumber = Addr; + + for(temp = 0; temp < lenth; temp ++) + { + *buffer = *snnumber; + buffer ++; + snnumber ++; + } + //memcpy(buffer,snnumber,lenth); +} + +/* End user code. Do not edit comment generated here */ \ No newline at end of file diff --git a/app/DataFlash/测试数据.txt b/app/DataFlash/测试数据.txt new file mode 100644 index 0000000..6e0a546 --- /dev/null +++ b/app/DataFlash/测试数据.txt @@ -0,0 +1,10 @@ +32MHz + + 64Bytes1024Bytes00HʱһΪ5.7mS +д 1024Bytes00H Ҫ46.8mSдʱݳȳԹϵ + +T04ʹע +1ջΣDMAӦRAMַҪŵRAMܷ +2дֽڵʱϳ鲻Ҫṩеȵİ취ѭвPFDL_Handler() +3ֱCPUָҪ +4ĵַΧķֵпܷܲ \ No newline at end of file diff --git a/app/cstart.asm b/app/cstart.asm new file mode 100644 index 0000000..d6267ab --- /dev/null +++ b/app/cstart.asm @@ -0,0 +1,231 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/ +; NOTE : THIS IS A TYPICAL EXAMPLE. + +$IFNDEF __RENESAS_VERSION__ +__RENESAS_VERSION__ .EQU 0x01000000 +$ENDIF + + .public _start + .public _exit + +;----------------------------------------------------------------------------- +; RAM section +;----------------------------------------------------------------------------- +.SECTION .dataR, DATA +.SECTION .sdataR, DATA +; .SECTION .datafR, DATAF +; .SECTION .textfR, TEXTF + +$IF (__RENESAS_VERSION__ < 0x01010000) ; for CC-RL V1.00 +;----------------------------------------------------------------------------- +; stack area +;----------------------------------------------------------------------------- +; !!! [CAUTION] !!! +; Set up stack size suitable for a project. +.SECTION .stack_bss, BSS +_stackend: + .DS 0x200 +_stacktop: +$ENDIF + +;----------------------------------------------------------------------------- +; RESET vector +;----------------------------------------------------------------------------- +_start .VECTOR 0 + +;----------------------------------------------------------------------------- +; startup +;----------------------------------------------------------------------------- +.SECTION .text, TEXT +_start: + ;-------------------------------------------------- + ; setting register bank + ;-------------------------------------------------- +; SEL RB0 + + ;-------------------------------------------------- + ; setting mirror area + ;-------------------------------------------------- +; ONEB !PMC ; mirror area = 10000-1FFFFH + + ;-------------------------------------------------- + ; setting the stack pointer + ;-------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) + MOVW SP,#LOWW(__STACK_ADDR_START) +$ELSE ; for CC-RL V1.00 + MOVW SP,#LOWW(_stacktop) +$ENDIF + + ;-------------------------------------------------- + ; initializing stack area + ;-------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) + MOVW AX,#LOWW(__STACK_ADDR_END) +$ELSE ; for CC-RL V1.00 + MOVW AX,#LOWW(_stackend) +$ENDIF + CALL !!_stkinit + + ;-------------------------------------------------- + ; hardware initialization + ;-------------------------------------------------- + CALL !!_hdwinit + + ;-------------------------------------------------- + ; initializing BSS + ;-------------------------------------------------- + ; clear external variables which doesn't have initial value (near) + MOVW HL,#LOWW(STARTOF(.bss)) + MOVW AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss)) + BR $.L2_BSS +.L1_BSS: + MOV [HL+0],#0 + INCW HL +.L2_BSS: + CMPW AX,HL + BNZ $.L1_BSS + + ; clear saddr variables which doesn't have initial value + MOVW HL,#LOWW(STARTOF(.sbss)) + MOVW AX,#LOWW(STARTOF(.sbss) + SIZEOF(.sbss)) + BR $.L2_SBSS +.L1_SBSS: + MOV [HL+0],#0 + INCW HL +.L2_SBSS: + CMPW AX,HL + BNZ $.L1_SBSS + + ; clear external variables which doesn't have initial value (far) +; MOV ES,#HIGHW(STARTOF(.bssf)) +; MOVW HL,#LOWW(STARTOF(.bssf)) +; MOVW AX,#LOWW(STARTOF(.bssf) + SIZEOF(.bssf)) +; BR $.L2_BSSF +;.L1_BSSF: +; MOV ES:[HL+0],#0 +; INCW HL +;.L2_BSSF: +; CMPW AX,HL +; BNZ $.L1_BSSF + + ;-------------------------------------------------- + ; ROM data copy + ;-------------------------------------------------- + ; copy external variables having initial value (near) + MOV ES,#HIGHW(STARTOF(.data)) + MOVW BC,#LOWW(SIZEOF(.data)) + BR $.L2_DATA +.L1_DATA: + DECW BC + MOV A,ES:LOWW(STARTOF(.data))[BC] + MOV LOWW(STARTOF(.dataR))[BC],A +.L2_DATA: + CLRW AX + CMPW AX,BC + BNZ $.L1_DATA + + ; copy saddr variables having initial value + MOV ES,#HIGHW(STARTOF(.sdata)) + MOVW BC,#LOWW(SIZEOF(.sdata)) + BR $.L2_SDATA +.L1_SDATA: + DECW BC + MOV A,ES:LOWW(STARTOF(.sdata))[BC] + MOV LOWW(STARTOF(.sdataR))[BC],A +.L2_SDATA: + CLRW AX + CMPW AX,BC + BNZ $.L1_SDATA + + ; copy external variables having initial value (far) +; MOVW BC,#LOWW(SIZEOF(.dataf)) +; BR $.L2_DATAF +;.L1_DATAF: +; DECW BC +; MOV ES,#HIGHW(STARTOF(.dataf)) +; MOV A,ES:LOWW(STARTOF(.dataf))[BC] +; MOV ES,#HIGHW(STARTOF(.datafR)) +; MOV ES:LOWW(STARTOF(.datafR))[BC],A +;.L2_DATAF: +; CLRW AX +; CMPW AX,BC +; BNZ $.L1_DATAF + + ; copy .text to RAM +; MOV C,#HIGHW(STARTOF(.textf)) +; MOVW HL,#LOWW(STARTOF(.textf)) +; MOVW DE,#LOWW(STARTOF(.textfR)) +; BR $.L2_TEXT +;.L1_TEXT: +; MOV A,C +; MOV ES,A +; MOV A,ES:[HL] +; MOV [DE],A +; INCW DE +; INCW HL +; CLRW AX +; CMPW AX,HL +; SKNZ +; INC C +;.L2_TEXT: +; MOVW AX,HL +; CMPW AX,#LOWW(STARTOF(.text) + SIZEOF(.text)) +; BNZ $.L1_TEXT + + ;-------------------------------------------------- + ; call main function + ;-------------------------------------------------- + CALL !!_main ; main(); + + ;-------------------------------------------------- + ; call exit function + ;-------------------------------------------------- + CLRW AX ; exit(0) +_exit: + BR $_exit + +;----------------------------------------------------------------------------- +; section +;----------------------------------------------------------------------------- +$IF (__RENESAS_VERSION__ >= 0x01010000) +.SECTION .RLIB, TEXTF +.L_section_RLIB: +.SECTION .SLIB, TEXTF +.L_section_SLIB: +$ENDIF +.SECTION .textf, TEXTF +.L_section_textf: +.SECTION .const, CONST +.L_section_const: +.SECTION .constf, CONSTF +.L_section_constf: +.SECTION .data, DATA +.L_section_data: +;.SECTION .dataf, DATAF +;.L_section_dataf: +.SECTION .sdata, SDATA +.L_section_sdata: +.SECTION .bss, BSS +.L_section_bss: +;.SECTION .bssf, BSSF +;.L_section_bssf: +.SECTION .sbss, SBSS +.L_section_sbss: diff --git a/app/hdwinit.asm b/app/hdwinit.asm new file mode 100644 index 0000000..0b74c68 --- /dev/null +++ b/app/hdwinit.asm @@ -0,0 +1,35 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/;--------------------------------------------------------------------- +; _hdwinit +; +; void _hdwinit(void); +; +; input: +; NONE +; output: +; NONE +;--------------------------------------------------------------------- + +; NOTE : THIS IS A TYPICAL EXAMPLE. + + .PUBLIC _hdwinit + +.textf .CSEG TEXTF +_hdwinit: + RET diff --git a/app/iodefine.h b/app/iodefine.h new file mode 100644 index 0000000..6fc967c --- /dev/null +++ b/app/iodefine.h @@ -0,0 +1,1108 @@ +/******************************************************************************/ +/* DISCLAIMER */ +/* This software is supplied by Renesas Electronics Corporation and is only */ +/* intended for use with Renesas products. No other uses are authorized.This */ +/* software is owned by Renesas Electronics Corporation and is protected */ +/* under all applicable laws, including copyright laws. */ +/* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES */ +/* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING */ +/* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR */ +/* PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY */ +/* DISCLAIMED. */ +/* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS */ +/* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE */ +/* LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL */ +/* DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS */ +/* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. */ +/* Renesas reserves the right, without notice, to make changes to this */ +/* software and to discontinue the availability of this software. */ +/* By using this software, you agree to the additional terms and conditions */ +/* found by accessing the following link: */ +/* http://www.renesas.com/disclaimer */ +/* */ +/* Device : RL78/R5F10AGF */ +/* File Name : iodefine.h */ +/* Abstract : Definition of Special Function Register (SFR) */ +/* History : V1.11 [Device File version] */ +/* Options : -df=E:\Program Files (x86)\renesas\CS+\CC\Device\RL78\Devicef */ +/* ile\DR5F10AGF.DVF -o=F:\FCB_project\temp\bczt_new\CODE\R5f10A */ +/* GF\iodefine.h -f */ +/* Date : 2023-11-24 */ +/* Version : V1.15.00.01 [df2iodef.exe version] */ +/* This is a typical example. */ +/* */ +/******************************************************************************/ +#ifndef __R5F10AGFIODEFINE_HEADER__ +#define __R5F10AGFIODEFINE_HEADER__ + +typedef struct +{ + unsigned char no0:1; + unsigned char no1:1; + unsigned char no2:1; + unsigned char no3:1; + unsigned char no4:1; + unsigned char no5:1; + unsigned char no6:1; + unsigned char no7:1; +} __bitf_T; + +typedef struct +{ + unsigned char no0:1; + unsigned char no1:1; + unsigned char no2:1; + unsigned char no3:1; + unsigned char no4:1; + unsigned char no5:1; + unsigned char no6:1; + unsigned char no7:1; + unsigned char no8:1; + unsigned char no9:1; + unsigned char no10:1; + unsigned char no11:1; + unsigned char no12:1; + unsigned char no13:1; + unsigned char no14:1; + unsigned char no15:1; +} __bitf_T2; + + + +#define ADM2 (*(volatile __near unsigned char *)0x10) +#define ADM2_bit (*(volatile __near __bitf_T *)0x10) +#define ADTYP (((volatile __near __bitf_T *)0x10)->no0) +#define AWC (((volatile __near __bitf_T *)0x10)->no2) +#define ADRCK (((volatile __near __bitf_T *)0x10)->no3) +#define ADUL (*(volatile __near unsigned char *)0x11) +#define ADLL (*(volatile __near unsigned char *)0x12) +#define ADTES (*(volatile __near unsigned char *)0x13) +#define PIOR0 (*(volatile __near unsigned char *)0x16) +#define PIOR1 (*(volatile __near unsigned char *)0x17) +#define PIOR4 (*(volatile __near unsigned char *)0x1A) +#define PIOR5 (*(volatile __near unsigned char *)0x1B) +#define PIOR7 (*(volatile __near unsigned char *)0x1D) +#define PITHL1 (*(volatile __near unsigned char *)0x21) +#define PITHL1_bit (*(volatile __near __bitf_T *)0x21) +#define PITHL3 (*(volatile __near unsigned char *)0x23) +#define PITHL3_bit (*(volatile __near __bitf_T *)0x23) +#define PITHL6 (*(volatile __near unsigned char *)0x26) +#define PITHL6_bit (*(volatile __near __bitf_T *)0x26) +#define PITHL7 (*(volatile __near unsigned char *)0x27) +#define PITHL7_bit (*(volatile __near __bitf_T *)0x27) +#define PITHL12 (*(volatile __near unsigned char *)0x2C) +#define PITHL12_bit (*(volatile __near __bitf_T *)0x2C) +#define PU0 (*(volatile __near unsigned char *)0x30) +#define PU0_bit (*(volatile __near __bitf_T *)0x30) +#define PU1 (*(volatile __near unsigned char *)0x31) +#define PU1_bit (*(volatile __near __bitf_T *)0x31) +#define PU3 (*(volatile __near unsigned char *)0x33) +#define PU3_bit (*(volatile __near __bitf_T *)0x33) +#define PU4 (*(volatile __near unsigned char *)0x34) +#define PU4_bit (*(volatile __near __bitf_T *)0x34) +#define PU6 (*(volatile __near unsigned char *)0x36) +#define PU6_bit (*(volatile __near __bitf_T *)0x36) +#define PU7 (*(volatile __near unsigned char *)0x37) +#define PU7_bit (*(volatile __near __bitf_T *)0x37) +#define PU12 (*(volatile __near unsigned char *)0x3C) +#define PU12_bit (*(volatile __near __bitf_T *)0x3C) +#define PU14 (*(volatile __near unsigned char *)0x3E) +#define PU14_bit (*(volatile __near __bitf_T *)0x3E) +#define PIM1 (*(volatile __near unsigned char *)0x41) +#define PIM1_bit (*(volatile __near __bitf_T *)0x41) +#define PIM3 (*(volatile __near unsigned char *)0x43) +#define PIM3_bit (*(volatile __near __bitf_T *)0x43) +#define PIM6 (*(volatile __near unsigned char *)0x46) +#define PIM6_bit (*(volatile __near __bitf_T *)0x46) +#define PIM7 (*(volatile __near unsigned char *)0x47) +#define PIM7_bit (*(volatile __near __bitf_T *)0x47) +#define PIM12 (*(volatile __near unsigned char *)0x4C) +#define PIM12_bit (*(volatile __near __bitf_T *)0x4C) +#define POM1 (*(volatile __near unsigned char *)0x51) +#define POM1_bit (*(volatile __near __bitf_T *)0x51) +#define POM6 (*(volatile __near unsigned char *)0x56) +#define POM6_bit (*(volatile __near __bitf_T *)0x56) +#define POM7 (*(volatile __near unsigned char *)0x57) +#define POM7_bit (*(volatile __near __bitf_T *)0x57) +#define POM12 (*(volatile __near unsigned char *)0x5C) +#define POM12_bit (*(volatile __near __bitf_T *)0x5C) +#define PMC12 (*(volatile __near unsigned char *)0x6C) +#define PMC12_bit (*(volatile __near __bitf_T *)0x6C) +#define NFEN0 (*(volatile __near unsigned char *)0x70) +#define NFEN0_bit (*(volatile __near __bitf_T *)0x70) +#define NFEN1 (*(volatile __near unsigned char *)0x71) +#define NFEN1_bit (*(volatile __near __bitf_T *)0x71) +#define NFEN2 (*(volatile __near unsigned char *)0x72) +#define NFEN2_bit (*(volatile __near __bitf_T *)0x72) +#define ISC (*(volatile __near unsigned char *)0x73) +#define ISC_bit (*(volatile __near __bitf_T *)0x73) +#define TIS0 (*(volatile __near unsigned char *)0x74) +#define TIS1 (*(volatile __near unsigned char *)0x75) +#define ADPC (*(volatile __near unsigned char *)0x76) +#define PMS (*(volatile __near unsigned char *)0x77) +#define PMS_bit (*(volatile __near __bitf_T *)0x77) +#define IAWCTL (*(volatile __near unsigned char *)0x78) +#define INTFLG0 (*(volatile __near unsigned char *)0x79) +#define LCHSEL (*(volatile __near unsigned char *)0x7B) +#define INTMSK (*(volatile __near unsigned char *)0x7C) +#define DFLCTL (*(volatile __near unsigned char *)0x90) +#define DFLCTL_bit (*(volatile __near __bitf_T *)0x90) +#define DFLEN (((volatile __near __bitf_T *)0x90)->no0) +#define HIOTRM (*(volatile __near unsigned char *)0xA0) +#define HOCODIV (*(volatile __near unsigned char *)0xA8) +#define SPMCTRL (*(volatile __near unsigned char *)0xD8) +#define SPOFR (*(volatile __near unsigned short *)0xDA) +#define SPUFR (*(volatile __near unsigned short *)0xDC) +#define PER0 (*(volatile __near unsigned char *)0xF0) +#define PER0_bit (*(volatile __near __bitf_T *)0xF0) +#define TAU0EN (((volatile __near __bitf_T *)0xF0)->no0) +#define TAU1EN (((volatile __near __bitf_T *)0xF0)->no1) +#define SAU0EN (((volatile __near __bitf_T *)0xF0)->no2) +#define SAU1EN (((volatile __near __bitf_T *)0xF0)->no3) +#define IICA0EN (((volatile __near __bitf_T *)0xF0)->no4) +#define ADCEN (((volatile __near __bitf_T *)0xF0)->no5) +#define RTCEN (((volatile __near __bitf_T *)0xF0)->no7) +#define OSMC (*(volatile __near unsigned char *)0xF3) +#define BCDADJ (*(volatile __near unsigned char *)0xFE) +#define SSR00 (*(volatile __near unsigned short *)0x100) +#define SSR00L (*(volatile __near unsigned char *)0x100) +#define SSR01 (*(volatile __near unsigned short *)0x102) +#define SSR01L (*(volatile __near unsigned char *)0x102) +#define SIR00 (*(volatile __near unsigned short *)0x104) +#define SIR00L (*(volatile __near unsigned char *)0x104) +#define SIR01 (*(volatile __near unsigned short *)0x106) +#define SIR01L (*(volatile __near unsigned char *)0x106) +#define SMR00 (*(volatile __near unsigned short *)0x108) +#define SMR01 (*(volatile __near unsigned short *)0x10A) +#define SCR00 (*(volatile __near unsigned short *)0x10C) +#define SCR01 (*(volatile __near unsigned short *)0x10E) +#define SE0 (*(volatile __near unsigned short *)0x110) +#define SE0L (*(volatile __near unsigned char *)0x110) +#define SE0L_bit (*(volatile __near __bitf_T *)0x110) +#define SS0 (*(volatile __near unsigned short *)0x112) +#define SS0L (*(volatile __near unsigned char *)0x112) +#define SS0L_bit (*(volatile __near __bitf_T *)0x112) +#define ST0 (*(volatile __near unsigned short *)0x114) +#define ST0L (*(volatile __near unsigned char *)0x114) +#define ST0L_bit (*(volatile __near __bitf_T *)0x114) +#define SPS0 (*(volatile __near unsigned short *)0x116) +#define SPS0L (*(volatile __near unsigned char *)0x116) +#define SO0 (*(volatile __near unsigned short *)0x118) +#define SOE0 (*(volatile __near unsigned short *)0x11A) +#define SOE0L (*(volatile __near unsigned char *)0x11A) +#define SOE0L_bit (*(volatile __near __bitf_T *)0x11A) +#define SOL0 (*(volatile __near unsigned short *)0x120) +#define SOL0L (*(volatile __near unsigned char *)0x120) +#define SSE0 (*(volatile __near unsigned short *)0x122) +#define SSE0L (*(volatile __near unsigned char *)0x122) +#define SSR10 (*(volatile __near unsigned short *)0x140) +#define SSR10L (*(volatile __near unsigned char *)0x140) +#define SSR11 (*(volatile __near unsigned short *)0x142) +#define SSR11L (*(volatile __near unsigned char *)0x142) +#define SIR10 (*(volatile __near unsigned short *)0x144) +#define SIR10L (*(volatile __near unsigned char *)0x144) +#define SIR11 (*(volatile __near unsigned short *)0x146) +#define SIR11L (*(volatile __near unsigned char *)0x146) +#define SMR10 (*(volatile __near unsigned short *)0x148) +#define SMR11 (*(volatile __near unsigned short *)0x14A) +#define SCR10 (*(volatile __near unsigned short *)0x14C) +#define SCR11 (*(volatile __near unsigned short *)0x14E) +#define SE1 (*(volatile __near unsigned short *)0x150) +#define SE1L (*(volatile __near unsigned char *)0x150) +#define SE1L_bit (*(volatile __near __bitf_T *)0x150) +#define SS1 (*(volatile __near unsigned short *)0x152) +#define SS1L (*(volatile __near unsigned char *)0x152) +#define SS1L_bit (*(volatile __near __bitf_T *)0x152) +#define ST1 (*(volatile __near unsigned short *)0x154) +#define ST1L (*(volatile __near unsigned char *)0x154) +#define ST1L_bit (*(volatile __near __bitf_T *)0x154) +#define SPS1 (*(volatile __near unsigned short *)0x156) +#define SPS1L (*(volatile __near unsigned char *)0x156) +#define SO1 (*(volatile __near unsigned short *)0x158) +#define SOE1 (*(volatile __near unsigned short *)0x15A) +#define SOE1L (*(volatile __near unsigned char *)0x15A) +#define SOE1L_bit (*(volatile __near __bitf_T *)0x15A) +#define SOL1 (*(volatile __near unsigned short *)0x160) +#define SOL1L (*(volatile __near unsigned char *)0x160) +#define SSE1 (*(volatile __near unsigned short *)0x162) +#define SSE1L (*(volatile __near unsigned char *)0x162) +#define TCR00 (*(volatile __near unsigned short *)0x180) +#define TCR01 (*(volatile __near unsigned short *)0x182) +#define TCR02 (*(volatile __near unsigned short *)0x184) +#define TCR03 (*(volatile __near unsigned short *)0x186) +#define TCR04 (*(volatile __near unsigned short *)0x188) +#define TCR05 (*(volatile __near unsigned short *)0x18A) +#define TCR06 (*(volatile __near unsigned short *)0x18C) +#define TCR07 (*(volatile __near unsigned short *)0x18E) +#define TMR00 (*(volatile __near unsigned short *)0x190) +#define TMR01 (*(volatile __near unsigned short *)0x192) +#define TMR02 (*(volatile __near unsigned short *)0x194) +#define TMR03 (*(volatile __near unsigned short *)0x196) +#define TMR04 (*(volatile __near unsigned short *)0x198) +#define TMR05 (*(volatile __near unsigned short *)0x19A) +#define TMR06 (*(volatile __near unsigned short *)0x19C) +#define TMR07 (*(volatile __near unsigned short *)0x19E) +#define TSR00 (*(volatile __near unsigned short *)0x1A0) +#define TSR00L (*(volatile __near unsigned char *)0x1A0) +#define TSR01 (*(volatile __near unsigned short *)0x1A2) +#define TSR01L (*(volatile __near unsigned char *)0x1A2) +#define TSR02 (*(volatile __near unsigned short *)0x1A4) +#define TSR02L (*(volatile __near unsigned char *)0x1A4) +#define TSR03 (*(volatile __near unsigned short *)0x1A6) +#define TSR03L (*(volatile __near unsigned char *)0x1A6) +#define TSR04 (*(volatile __near unsigned short *)0x1A8) +#define TSR04L (*(volatile __near unsigned char *)0x1A8) +#define TSR05 (*(volatile __near unsigned short *)0x1AA) +#define TSR05L (*(volatile __near unsigned char *)0x1AA) +#define TSR06 (*(volatile __near unsigned short *)0x1AC) +#define TSR06L (*(volatile __near unsigned char *)0x1AC) +#define TSR07 (*(volatile __near unsigned short *)0x1AE) +#define TSR07L (*(volatile __near unsigned char *)0x1AE) +#define TE0 (*(volatile __near unsigned short *)0x1B0) +#define TE0L (*(volatile __near unsigned char *)0x1B0) +#define TE0L_bit (*(volatile __near __bitf_T *)0x1B0) +#define TS0 (*(volatile __near unsigned short *)0x1B2) +#define TS0L (*(volatile __near unsigned char *)0x1B2) +#define TS0L_bit (*(volatile __near __bitf_T *)0x1B2) +#define TT0 (*(volatile __near unsigned short *)0x1B4) +#define TT0L (*(volatile __near unsigned char *)0x1B4) +#define TT0L_bit (*(volatile __near __bitf_T *)0x1B4) +#define TPS0 (*(volatile __near unsigned short *)0x1B6) +#define TO0 (*(volatile __near unsigned short *)0x1B8) +#define TO0L (*(volatile __near unsigned char *)0x1B8) +#define TOE0 (*(volatile __near unsigned short *)0x1BA) +#define TOE0L (*(volatile __near unsigned char *)0x1BA) +#define TOE0L_bit (*(volatile __near __bitf_T *)0x1BA) +#define TOL0 (*(volatile __near unsigned short *)0x1BC) +#define TOL0L (*(volatile __near unsigned char *)0x1BC) +#define TOM0 (*(volatile __near unsigned short *)0x1BE) +#define TOM0L (*(volatile __near unsigned char *)0x1BE) +#define TCR10 (*(volatile __near unsigned short *)0x1C0) +#define TCR11 (*(volatile __near unsigned short *)0x1C2) +#define TCR12 (*(volatile __near unsigned short *)0x1C4) +#define TCR13 (*(volatile __near unsigned short *)0x1C6) +#define TMR10 (*(volatile __near unsigned short *)0x1D0) +#define TMR11 (*(volatile __near unsigned short *)0x1D2) +#define TMR12 (*(volatile __near unsigned short *)0x1D4) +#define TMR13 (*(volatile __near unsigned short *)0x1D6) +#define TSR10 (*(volatile __near unsigned short *)0x1E0) +#define TSR10L (*(volatile __near unsigned char *)0x1E0) +#define TSR11 (*(volatile __near unsigned short *)0x1E2) +#define TSR11L (*(volatile __near unsigned char *)0x1E2) +#define TSR12 (*(volatile __near unsigned short *)0x1E4) +#define TSR12L (*(volatile __near unsigned char *)0x1E4) +#define TSR13 (*(volatile __near unsigned short *)0x1E6) +#define TSR13L (*(volatile __near unsigned char *)0x1E6) +#define TE1 (*(volatile __near unsigned short *)0x1F0) +#define TE1L (*(volatile __near unsigned char *)0x1F0) +#define TE1L_bit (*(volatile __near __bitf_T *)0x1F0) +#define TS1 (*(volatile __near unsigned short *)0x1F2) +#define TS1L (*(volatile __near unsigned char *)0x1F2) +#define TS1L_bit (*(volatile __near __bitf_T *)0x1F2) +#define TT1 (*(volatile __near unsigned short *)0x1F4) +#define TT1L (*(volatile __near unsigned char *)0x1F4) +#define TT1L_bit (*(volatile __near __bitf_T *)0x1F4) +#define TPS1 (*(volatile __near unsigned short *)0x1F6) +#define TO1 (*(volatile __near unsigned short *)0x1F8) +#define TO1L (*(volatile __near unsigned char *)0x1F8) +#define TOE1 (*(volatile __near unsigned short *)0x1FA) +#define TOE1L (*(volatile __near unsigned char *)0x1FA) +#define TOE1L_bit (*(volatile __near __bitf_T *)0x1FA) +#define TOL1 (*(volatile __near unsigned short *)0x1FC) +#define TOL1L (*(volatile __near unsigned char *)0x1FC) +#define TOM1 (*(volatile __near unsigned short *)0x1FE) +#define TOM1L (*(volatile __near unsigned char *)0x1FE) +#define ERADR (*(volatile __near unsigned short *)0x200) +#define ECCIER (*(volatile __near unsigned char *)0x202) +#define ECCER (*(volatile __near unsigned char *)0x203) +#define ECCTPR (*(volatile __near unsigned char *)0x204) +#define ECCTMDR (*(volatile __near unsigned char *)0x205) +#define ECCDWRVR (*(volatile __near unsigned short *)0x206) +#define PSRSEL (*(volatile __near unsigned char *)0x220) +#define PSRSEL_bit (*(volatile __near __bitf_T *)0x220) +#define PSNZCNT0 (*(volatile __near unsigned char *)0x222) +#define PSNZCNT0_bit (*(volatile __near __bitf_T *)0x222) +#define PSNZCNT1 (*(volatile __near unsigned char *)0x223) +#define PSNZCNT1_bit (*(volatile __near __bitf_T *)0x223) +#define PSNZCNT2 (*(volatile __near unsigned char *)0x224) +#define PSNZCNT2_bit (*(volatile __near __bitf_T *)0x224) +#define PSNZCNT3 (*(volatile __near unsigned char *)0x225) +#define PSNZCNT3_bit (*(volatile __near __bitf_T *)0x225) +#define PWMDLY0 (*(volatile __near unsigned short *)0x228) +#define PWMDLY1 (*(volatile __near unsigned short *)0x22A) +#define PWMDLY2 (*(volatile __near unsigned short *)0x22C) +#define IICCTL00 (*(volatile __near unsigned char *)0x230) +#define IICCTL00_bit (*(volatile __near __bitf_T *)0x230) +#define SPT0 (((volatile __near __bitf_T *)0x230)->no0) +#define STT0 (((volatile __near __bitf_T *)0x230)->no1) +#define ACKE0 (((volatile __near __bitf_T *)0x230)->no2) +#define WTIM0 (((volatile __near __bitf_T *)0x230)->no3) +#define SPIE0 (((volatile __near __bitf_T *)0x230)->no4) +#define WREL0 (((volatile __near __bitf_T *)0x230)->no5) +#define LREL0 (((volatile __near __bitf_T *)0x230)->no6) +#define IICE0 (((volatile __near __bitf_T *)0x230)->no7) +#define IICCTL01 (*(volatile __near unsigned char *)0x231) +#define IICCTL01_bit (*(volatile __near __bitf_T *)0x231) +#define PRS0 (((volatile __near __bitf_T *)0x231)->no0) +#define DFC0 (((volatile __near __bitf_T *)0x231)->no2) +#define SMC0 (((volatile __near __bitf_T *)0x231)->no3) +#define DAD0 (((volatile __near __bitf_T *)0x231)->no4) +#define CLD0 (((volatile __near __bitf_T *)0x231)->no5) +#define WUP0 (((volatile __near __bitf_T *)0x231)->no7) +#define IICWL0 (*(volatile __near unsigned char *)0x232) +#define IICWH0 (*(volatile __near unsigned char *)0x233) +#define SVA0 (*(volatile __near unsigned char *)0x234) +#define TRJCR0 (*(volatile __near unsigned char *)0x240) +#define TRJIOC0 (*(volatile __near unsigned char *)0x241) +#define TRJIOC0_bit (*(volatile __near __bitf_T *)0x241) +#define TRJMR0 (*(volatile __near unsigned char *)0x242) +#define TRJMR0_bit (*(volatile __near __bitf_T *)0x242) +#define TRJISR0 (*(volatile __near unsigned char *)0x243) +#define TRJISR0_bit (*(volatile __near __bitf_T *)0x243) +#define TRDSTR (*(volatile __near unsigned char *)0x263) +#define TRDMR (*(volatile __near unsigned char *)0x264) +#define TRDMR_bit (*(volatile __near __bitf_T *)0x264) +#define TRDSYNC (((volatile __near __bitf_T *)0x264)->no0) +#define TRDBFC0 (((volatile __near __bitf_T *)0x264)->no4) +#define TRDBFD0 (((volatile __near __bitf_T *)0x264)->no5) +#define TRDBFC1 (((volatile __near __bitf_T *)0x264)->no6) +#define TRDBFD1 (((volatile __near __bitf_T *)0x264)->no7) +#define TRDPMR (*(volatile __near unsigned char *)0x265) +#define TRDPMR_bit (*(volatile __near __bitf_T *)0x265) +#define TRDPWMB0 (((volatile __near __bitf_T *)0x265)->no0) +#define TRDPWMC0 (((volatile __near __bitf_T *)0x265)->no1) +#define TRDPWMD0 (((volatile __near __bitf_T *)0x265)->no2) +#define TRDPWMB1 (((volatile __near __bitf_T *)0x265)->no4) +#define TRDPWMC1 (((volatile __near __bitf_T *)0x265)->no5) +#define TRDPWMD1 (((volatile __near __bitf_T *)0x265)->no6) +#define TRDFCR (*(volatile __near unsigned char *)0x266) +#define TRDFCR_bit (*(volatile __near __bitf_T *)0x266) +#define TRDOER1 (*(volatile __near unsigned char *)0x267) +#define TRDOER1_bit (*(volatile __near __bitf_T *)0x267) +#define TRDOER2 (*(volatile __near unsigned char *)0x268) +#define TRDOER2_bit (*(volatile __near __bitf_T *)0x268) +#define TRDSHUTS (((volatile __near __bitf_T *)0x268)->no0) +#define TRDPTO (((volatile __near __bitf_T *)0x268)->no7) +#define TRDOCR (*(volatile __near unsigned char *)0x269) +#define TRDOCR_bit (*(volatile __near __bitf_T *)0x269) +#define TRDDF0 (*(volatile __near unsigned char *)0x26A) +#define TRDDF0_bit (*(volatile __near __bitf_T *)0x26A) +#define TRDDF1 (*(volatile __near unsigned char *)0x26B) +#define TRDDF1_bit (*(volatile __near __bitf_T *)0x26B) +#define TRDCR0 (*(volatile __near unsigned char *)0x270) +#define TRDCR0_bit (*(volatile __near __bitf_T *)0x270) +#define TRDIORA0 (*(volatile __near unsigned char *)0x271) +#define TRDIORA0_bit (*(volatile __near __bitf_T *)0x271) +#define TRDIORC0 (*(volatile __near unsigned char *)0x272) +#define TRDIORC0_bit (*(volatile __near __bitf_T *)0x272) +#define TRDSR0 (*(volatile __near unsigned char *)0x273) +#define TRDSR0_bit (*(volatile __near __bitf_T *)0x273) +#define TRDIER0 (*(volatile __near unsigned char *)0x274) +#define TRDIER0_bit (*(volatile __near __bitf_T *)0x274) +#define TRDPOCR0 (*(volatile __near unsigned char *)0x275) +#define TRDPOCR0_bit (*(volatile __near __bitf_T *)0x275) +#define TRD0 (*(volatile __near unsigned short *)0x276) +#define TRDGRA0 (*(volatile __near unsigned short *)0x278) +#define TRDGRB0 (*(volatile __near unsigned short *)0x27A) +#define TRDCR1 (*(volatile __near unsigned char *)0x280) +#define TRDCR1_bit (*(volatile __near __bitf_T *)0x280) +#define TRDIORA1 (*(volatile __near unsigned char *)0x281) +#define TRDIORA1_bit (*(volatile __near __bitf_T *)0x281) +#define TRDIORC1 (*(volatile __near unsigned char *)0x282) +#define TRDIORC1_bit (*(volatile __near __bitf_T *)0x282) +#define TRDSR1 (*(volatile __near unsigned char *)0x283) +#define TRDSR1_bit (*(volatile __near __bitf_T *)0x283) +#define TRDIER1 (*(volatile __near unsigned char *)0x284) +#define TRDIER1_bit (*(volatile __near __bitf_T *)0x284) +#define TRDPOCR1 (*(volatile __near unsigned char *)0x285) +#define TRDPOCR1_bit (*(volatile __near __bitf_T *)0x285) +#define TRD1 (*(volatile __near unsigned short *)0x286) +#define TRDGRA1 (*(volatile __near unsigned short *)0x288) +#define TRDGRB1 (*(volatile __near unsigned short *)0x28A) +#define PER1 (*(volatile __near unsigned char *)0x2C0) +#define PER1_bit (*(volatile __near __bitf_T *)0x2C0) +#define TRJ0EN (((volatile __near __bitf_T *)0x2C0)->no0) +#define DTCEN (((volatile __near __bitf_T *)0x2C0)->no3) +#define TRD0EN (((volatile __near __bitf_T *)0x2C0)->no4) +#define PER2 (*(volatile __near unsigned char *)0x2C1) +#define PER2_bit (*(volatile __near __bitf_T *)0x2C1) +#define LIN0EN (((volatile __near __bitf_T *)0x2C1)->no2) +#define LINCKSEL (*(volatile __near unsigned char *)0x2C3) +#define LINCKSEL_bit (*(volatile __near __bitf_T *)0x2C3) +#define LIN0MCK (((volatile __near __bitf_T *)0x2C3)->no0) +#define LIN0MCKE (((volatile __near __bitf_T *)0x2C3)->no4) +#define CKSEL (*(volatile __near unsigned char *)0x2C4) +#define CKSEL_bit (*(volatile __near __bitf_T *)0x2C4) +#define SELLOSC (((volatile __near __bitf_T *)0x2C4)->no0) +#define TRD_CKSEL (((volatile __near __bitf_T *)0x2C4)->no2) +#define PLLCTL (*(volatile __near unsigned char *)0x2C5) +#define PLLCTL_bit (*(volatile __near __bitf_T *)0x2C5) +#define PLLON (((volatile __near __bitf_T *)0x2C5)->no0) +#define PLLMUL (((volatile __near __bitf_T *)0x2C5)->no1) +#define SELPLL (((volatile __near __bitf_T *)0x2C5)->no2) +#define PLLDIV0 (((volatile __near __bitf_T *)0x2C5)->no4) +#define PLLDIV1 (((volatile __near __bitf_T *)0x2C5)->no5) +#define LCKSEL0 (((volatile __near __bitf_T *)0x2C5)->no6) +#define LCKSEL1 (((volatile __near __bitf_T *)0x2C5)->no7) +#define PLLSTS (*(volatile __near unsigned char *)0x2C6) +#define PLLSTS_bit (*(volatile __near __bitf_T *)0x2C6) +#define SELPLLS (((volatile __near __bitf_T *)0x2C6)->no3) +#define LOCK (((volatile __near __bitf_T *)0x2C6)->no7) +#define MDIV (*(volatile __near unsigned char *)0x2C7) +#define RTCCL (*(volatile __near unsigned char *)0x2C8) +#define RTCCL_bit (*(volatile __near __bitf_T *)0x2C8) +#define POCRES (*(volatile __near unsigned char *)0x2C9) +#define POCRES_bit (*(volatile __near __bitf_T *)0x2C9) +#define POCRES0 (((volatile __near __bitf_T *)0x2C9)->no0) +#define CLKRF (((volatile __near __bitf_T *)0x2C9)->no4) +#define STPSTC (*(volatile __near unsigned char *)0x2CA) +#define STPSTC_bit (*(volatile __near __bitf_T *)0x2CA) +#define STPLV (((volatile __near __bitf_T *)0x2CA)->no4) +#define STPOEN (((volatile __near __bitf_T *)0x2CA)->no7) +#define HDTCCR0 (*(volatile __near unsigned char *)0x2D0) +#define HDTCCR0_bit (*(volatile __near __bitf_T *)0x2D0) +#define HMODE0 (((volatile __near __bitf_T *)0x2D0)->no0) +#define HRPTSEL0 (((volatile __near __bitf_T *)0x2D0)->no1) +#define HSAMOD0 (((volatile __near __bitf_T *)0x2D0)->no2) +#define HDAMOD0 (((volatile __near __bitf_T *)0x2D0)->no3) +#define HCHNE0 (((volatile __near __bitf_T *)0x2D0)->no4) +#define HRPTINT0 (((volatile __near __bitf_T *)0x2D0)->no5) +#define HSZ0 (((volatile __near __bitf_T *)0x2D0)->no6) +#define HDTCCT0 (*(volatile __near unsigned char *)0x2D2) +#define HDTCCT0_bit (*(volatile __near __bitf_T *)0x2D2) +#define HDTRLD0 (*(volatile __near unsigned char *)0x2D3) +#define HDTRLD0_bit (*(volatile __near __bitf_T *)0x2D3) +#define HDTSAR0 (*(volatile __near unsigned short *)0x2D4) +#define HDTDAR0 (*(volatile __near unsigned short *)0x2D6) +#define HDTCCR1 (*(volatile __near unsigned char *)0x2D8) +#define HDTCCR1_bit (*(volatile __near __bitf_T *)0x2D8) +#define HMODE1 (((volatile __near __bitf_T *)0x2D8)->no0) +#define HRPTSEL1 (((volatile __near __bitf_T *)0x2D8)->no1) +#define HSAMOD1 (((volatile __near __bitf_T *)0x2D8)->no2) +#define HDAMOD1 (((volatile __near __bitf_T *)0x2D8)->no3) +#define HCHNE1 (((volatile __near __bitf_T *)0x2D8)->no4) +#define HRPTINT1 (((volatile __near __bitf_T *)0x2D8)->no5) +#define HSZ1 (((volatile __near __bitf_T *)0x2D8)->no6) +#define HDTCCT1 (*(volatile __near unsigned char *)0x2DA) +#define HDTCCT1_bit (*(volatile __near __bitf_T *)0x2DA) +#define HDTRLD1 (*(volatile __near unsigned char *)0x2DB) +#define HDTRLD1_bit (*(volatile __near __bitf_T *)0x2DB) +#define HDTSAR1 (*(volatile __near unsigned short *)0x2DC) +#define HDTDAR1 (*(volatile __near unsigned short *)0x2DE) +#define DTCBAR (*(volatile __near unsigned char *)0x2E0) +#define SELHS0 (*(volatile __near unsigned char *)0x2E1) +#define SELHS0_bit (*(volatile __near __bitf_T *)0x2E1) +#define SELHS1 (*(volatile __near unsigned char *)0x2E2) +#define SELHS1_bit (*(volatile __near __bitf_T *)0x2E2) +#define DTCEN0 (*(volatile __near unsigned char *)0x2E8) +#define DTCEN0_bit (*(volatile __near __bitf_T *)0x2E8) +#define DTCEN00 (((volatile __near __bitf_T *)0x2E8)->no0) +#define DTCEN01 (((volatile __near __bitf_T *)0x2E8)->no1) +#define DTCEN02 (((volatile __near __bitf_T *)0x2E8)->no2) +#define DTCEN03 (((volatile __near __bitf_T *)0x2E8)->no3) +#define DTCEN04 (((volatile __near __bitf_T *)0x2E8)->no4) +#define DTCEN05 (((volatile __near __bitf_T *)0x2E8)->no5) +#define DTCEN06 (((volatile __near __bitf_T *)0x2E8)->no6) +#define DTCEN1 (*(volatile __near unsigned char *)0x2E9) +#define DTCEN1_bit (*(volatile __near __bitf_T *)0x2E9) +#define DTCEN10 (((volatile __near __bitf_T *)0x2E9)->no0) +#define DTCEN11 (((volatile __near __bitf_T *)0x2E9)->no1) +#define DTCEN12 (((volatile __near __bitf_T *)0x2E9)->no2) +#define DTCEN13 (((volatile __near __bitf_T *)0x2E9)->no3) +#define DTCEN14 (((volatile __near __bitf_T *)0x2E9)->no4) +#define DTCEN15 (((volatile __near __bitf_T *)0x2E9)->no5) +#define DTCEN16 (((volatile __near __bitf_T *)0x2E9)->no6) +#define DTCEN17 (((volatile __near __bitf_T *)0x2E9)->no7) +#define DTCEN2 (*(volatile __near unsigned char *)0x2EA) +#define DTCEN2_bit (*(volatile __near __bitf_T *)0x2EA) +#define DTCEN20 (((volatile __near __bitf_T *)0x2EA)->no0) +#define DTCEN21 (((volatile __near __bitf_T *)0x2EA)->no1) +#define DTCEN22 (((volatile __near __bitf_T *)0x2EA)->no2) +#define DTCEN23 (((volatile __near __bitf_T *)0x2EA)->no3) +#define DTCEN24 (((volatile __near __bitf_T *)0x2EA)->no4) +#define DTCEN25 (((volatile __near __bitf_T *)0x2EA)->no5) +#define DTCEN3 (*(volatile __near unsigned char *)0x2EB) +#define DTCEN3_bit (*(volatile __near __bitf_T *)0x2EB) +#define DTCEN30 (((volatile __near __bitf_T *)0x2EB)->no0) +#define DTCEN31 (((volatile __near __bitf_T *)0x2EB)->no1) +#define DTCEN32 (((volatile __near __bitf_T *)0x2EB)->no2) +#define DTCEN33 (((volatile __near __bitf_T *)0x2EB)->no3) +#define DTCEN34 (((volatile __near __bitf_T *)0x2EB)->no4) +#define DTCEN35 (((volatile __near __bitf_T *)0x2EB)->no5) +#define DTCEN36 (((volatile __near __bitf_T *)0x2EB)->no6) +#define DTCEN37 (((volatile __near __bitf_T *)0x2EB)->no7) +#define DTCEN4 (*(volatile __near unsigned char *)0x2EC) +#define DTCEN4_bit (*(volatile __near __bitf_T *)0x2EC) +#define DTCEN40 (((volatile __near __bitf_T *)0x2EC)->no0) +#define DTCEN41 (((volatile __near __bitf_T *)0x2EC)->no1) +#define DTCEN42 (((volatile __near __bitf_T *)0x2EC)->no2) +#define DTCEN43 (((volatile __near __bitf_T *)0x2EC)->no3) +#define DTCEN45 (((volatile __near __bitf_T *)0x2EC)->no5) +#define DTCEN46 (((volatile __near __bitf_T *)0x2EC)->no6) +#define DTCEN47 (((volatile __near __bitf_T *)0x2EC)->no7) +#define CRC0CTL (*(volatile __near unsigned char *)0x2F0) +#define CRC0CTL_bit (*(volatile __near __bitf_T *)0x2F0) +#define CRC0EN (((volatile __near __bitf_T *)0x2F0)->no7) +#define PGCRCL (*(volatile __near unsigned short *)0x2F2) +#define CRCMD (*(volatile __near unsigned char *)0x2F9) +#define CRCD (*(volatile __near unsigned short *)0x2FA) +#define LWBR0 (*(volatile __near unsigned char *)0x6C1) +#define LBRP0 (*(volatile __near unsigned short *)0x6C2) +#define LBRP00 (*(volatile __near unsigned char *)0x6C2) +#define LBRP01 (*(volatile __near unsigned char *)0x6C3) +#define LSTC0 (*(volatile __near unsigned char *)0x6C4) +#define LUSC0 (*(volatile __near unsigned char *)0x6C5) +#define LMD0 (*(volatile __near unsigned char *)0x6C8) +#define LBFC0 (*(volatile __near unsigned char *)0x6C9) +#define LSC0 (*(volatile __near unsigned char *)0x6CA) +#define LWUP0 (*(volatile __near unsigned char *)0x6CB) +#define LIE0 (*(volatile __near unsigned char *)0x6CC) +#define LEDE0 (*(volatile __near unsigned char *)0x6CD) +#define LCUC0 (*(volatile __near unsigned char *)0x6CE) +#define LTRC0 (*(volatile __near unsigned char *)0x6D0) +#define LMST0 (*(volatile __near unsigned char *)0x6D1) +#define LST0 (*(volatile __near unsigned char *)0x6D2) +#define LEST0 (*(volatile __near unsigned char *)0x6D3) +#define LDFC0 (*(volatile __near unsigned char *)0x6D4) +#define LIDB0 (*(volatile __near unsigned char *)0x6D5) +#define LCBR0 (*(volatile __near unsigned char *)0x6D6) +#define LUDB00 (*(volatile __near unsigned char *)0x6D7) +#define LDB01 (*(volatile __near unsigned char *)0x6D8) +#define LDB02 (*(volatile __near unsigned char *)0x6D9) +#define LDB03 (*(volatile __near unsigned char *)0x6DA) +#define LDB04 (*(volatile __near unsigned char *)0x6DB) +#define LDB05 (*(volatile __near unsigned char *)0x6DC) +#define LDB06 (*(volatile __near unsigned char *)0x6DD) +#define LDB07 (*(volatile __near unsigned char *)0x6DE) +#define LDB08 (*(volatile __near unsigned char *)0x6DF) +#define LUOER0 (*(volatile __near unsigned char *)0x6E0) +#define LUOR01 (*(volatile __near unsigned char *)0x6E1) +#define LUTDR0 (*(volatile __near unsigned short *)0x6E4) +#define LUTDR0L (*(volatile __near unsigned char *)0x6E4) +#define LUTDR0H (*(volatile __near unsigned char *)0x6E5) +#define LURDR0 (*(volatile __near unsigned short *)0x6E6) +#define LURDR0L (*(volatile __near unsigned char *)0x6E6) +#define LURDR0H (*(volatile __near unsigned char *)0x6E7) +#define LUWTDR0 (*(volatile __near unsigned short *)0x6E8) +#define LUWTDR0L (*(volatile __near unsigned char *)0x6E8) +#define LUWTDR0H (*(volatile __near unsigned char *)0x6E9) +#define TRJ0 (*(volatile __near unsigned short *)0x6F0) +#define ADTRGS0 (*(volatile __near unsigned char *)0x789) +#define ADTRGS0_bit (*(volatile __near __bitf_T *)0x789) +#define ADTRGS1 (*(volatile __near unsigned char *)0x78D) +#define ADTRGS1_bit (*(volatile __near __bitf_T *)0x78D) +#define P0 (*(volatile __near unsigned char *)0xFF00) +#define P0_bit (*(volatile __near __bitf_T *)0xFF00) +#define P1 (*(volatile __near unsigned char *)0xFF01) +#define P1_bit (*(volatile __near __bitf_T *)0xFF01) +#define P3 (*(volatile __near unsigned char *)0xFF03) +#define P3_bit (*(volatile __near __bitf_T *)0xFF03) +#define P4 (*(volatile __near unsigned char *)0xFF04) +#define P4_bit (*(volatile __near __bitf_T *)0xFF04) +#define P6 (*(volatile __near unsigned char *)0xFF06) +#define P6_bit (*(volatile __near __bitf_T *)0xFF06) +#define P7 (*(volatile __near unsigned char *)0xFF07) +#define P7_bit (*(volatile __near __bitf_T *)0xFF07) +#define P8 (*(volatile __near unsigned char *)0xFF08) +#define P8_bit (*(volatile __near __bitf_T *)0xFF08) +#define P9 (*(volatile __near unsigned char *)0xFF09) +#define P9_bit (*(volatile __near __bitf_T *)0xFF09) +#define P12 (*(volatile __near unsigned char *)0xFF0C) +#define P12_bit (*(volatile __near __bitf_T *)0xFF0C) +#define P13 (*(volatile __near unsigned char *)0xFF0D) +#define P13_bit (*(volatile __near __bitf_T *)0xFF0D) +#define P14 (*(volatile __near unsigned char *)0xFF0E) +#define P14_bit (*(volatile __near __bitf_T *)0xFF0E) +#define SDR00 (*(volatile __near unsigned short *)0xFF10) +#define SDR00L (*(volatile __near unsigned char *)0xFF10) +#define SDR01 (*(volatile __near unsigned short *)0xFF12) +#define SDR01L (*(volatile __near unsigned char *)0xFF12) +#define TDR00 (*(volatile __near unsigned short *)0xFF18) +#define TDR01 (*(volatile __near unsigned short *)0xFF1A) +#define TDR01L (*(volatile __near unsigned char *)0xFF1A) +#define TDR01H (*(volatile __near unsigned char *)0xFF1B) +#define ADCR (*(volatile __near unsigned short *)0xFF1E) +#define ADCRH (*(volatile __near unsigned char *)0xFF1F) +#define PM0 (*(volatile __near unsigned char *)0xFF20) +#define PM0_bit (*(volatile __near __bitf_T *)0xFF20) +#define PM1 (*(volatile __near unsigned char *)0xFF21) +#define PM1_bit (*(volatile __near __bitf_T *)0xFF21) +#define PM3 (*(volatile __near unsigned char *)0xFF23) +#define PM3_bit (*(volatile __near __bitf_T *)0xFF23) +#define PM4 (*(volatile __near unsigned char *)0xFF24) +#define PM4_bit (*(volatile __near __bitf_T *)0xFF24) +#define PM6 (*(volatile __near unsigned char *)0xFF26) +#define PM6_bit (*(volatile __near __bitf_T *)0xFF26) +#define PM7 (*(volatile __near unsigned char *)0xFF27) +#define PM7_bit (*(volatile __near __bitf_T *)0xFF27) +#define PM8 (*(volatile __near unsigned char *)0xFF28) +#define PM8_bit (*(volatile __near __bitf_T *)0xFF28) +#define PM9 (*(volatile __near unsigned char *)0xFF29) +#define PM9_bit (*(volatile __near __bitf_T *)0xFF29) +#define PM12 (*(volatile __near unsigned char *)0xFF2C) +#define PM12_bit (*(volatile __near __bitf_T *)0xFF2C) +#define PM14 (*(volatile __near unsigned char *)0xFF2E) +#define PM14_bit (*(volatile __near __bitf_T *)0xFF2E) +#define ADM0 (*(volatile __near unsigned char *)0xFF30) +#define ADM0_bit (*(volatile __near __bitf_T *)0xFF30) +#define ADCE (((volatile __near __bitf_T *)0xFF30)->no0) +#define ADCS (((volatile __near __bitf_T *)0xFF30)->no7) +#define ADS (*(volatile __near unsigned char *)0xFF31) +#define ADS_bit (*(volatile __near __bitf_T *)0xFF31) +#define ADM1 (*(volatile __near unsigned char *)0xFF32) +#define ADM1_bit (*(volatile __near __bitf_T *)0xFF32) +#define KRM (*(volatile __near unsigned char *)0xFF37) +#define KRM_bit (*(volatile __near __bitf_T *)0xFF37) +#define EGP0 (*(volatile __near unsigned char *)0xFF38) +#define EGP0_bit (*(volatile __near __bitf_T *)0xFF38) +#define EGN0 (*(volatile __near unsigned char *)0xFF39) +#define EGN0_bit (*(volatile __near __bitf_T *)0xFF39) +#define EGP1 (*(volatile __near unsigned char *)0xFF3A) +#define EGP1_bit (*(volatile __near __bitf_T *)0xFF3A) +#define EGN1 (*(volatile __near unsigned char *)0xFF3B) +#define EGN1_bit (*(volatile __near __bitf_T *)0xFF3B) +#define SDR10 (*(volatile __near unsigned short *)0xFF48) +#define SDR10L (*(volatile __near unsigned char *)0xFF48) +#define SDR11 (*(volatile __near unsigned short *)0xFF4A) +#define SDR11L (*(volatile __near unsigned char *)0xFF4A) +#define IICA0 (*(volatile __near unsigned char *)0xFF50) +#define IICS0 (*(volatile __near unsigned char *)0xFF51) +#define IICS0_bit (*(volatile __near __bitf_T *)0xFF51) +#define SPD0 (((volatile __near __bitf_T *)0xFF51)->no0) +#define STD0 (((volatile __near __bitf_T *)0xFF51)->no1) +#define ACKD0 (((volatile __near __bitf_T *)0xFF51)->no2) +#define TRC0 (((volatile __near __bitf_T *)0xFF51)->no3) +#define COI0 (((volatile __near __bitf_T *)0xFF51)->no4) +#define EXC0 (((volatile __near __bitf_T *)0xFF51)->no5) +#define ALD0 (((volatile __near __bitf_T *)0xFF51)->no6) +#define MSTS0 (((volatile __near __bitf_T *)0xFF51)->no7) +#define IICF0 (*(volatile __near unsigned char *)0xFF52) +#define IICF0_bit (*(volatile __near __bitf_T *)0xFF52) +#define IICRSV0 (((volatile __near __bitf_T *)0xFF52)->no0) +#define STCEN0 (((volatile __near __bitf_T *)0xFF52)->no1) +#define IICBSY0 (((volatile __near __bitf_T *)0xFF52)->no6) +#define STCF0 (((volatile __near __bitf_T *)0xFF52)->no7) +#define SUBCUDW (*(volatile __near unsigned short *)0xFF54) +#define TRDGRC0 (*(volatile __near unsigned short *)0xFF58) +#define TRDGRD0 (*(volatile __near unsigned short *)0xFF5A) +#define TRDGRC1 (*(volatile __near unsigned short *)0xFF5C) +#define TRDGRD1 (*(volatile __near unsigned short *)0xFF5E) +#define TDR02 (*(volatile __near unsigned short *)0xFF64) +#define TDR03 (*(volatile __near unsigned short *)0xFF66) +#define TDR03L (*(volatile __near unsigned char *)0xFF66) +#define TDR03H (*(volatile __near unsigned char *)0xFF67) +#define TDR04 (*(volatile __near unsigned short *)0xFF68) +#define TDR05 (*(volatile __near unsigned short *)0xFF6A) +#define TDR06 (*(volatile __near unsigned short *)0xFF6C) +#define TDR07 (*(volatile __near unsigned short *)0xFF6E) +#define TDR10 (*(volatile __near unsigned short *)0xFF70) +#define TDR11 (*(volatile __near unsigned short *)0xFF72) +#define TDR11L (*(volatile __near unsigned char *)0xFF72) +#define TDR11H (*(volatile __near unsigned char *)0xFF73) +#define TDR12 (*(volatile __near unsigned short *)0xFF74) +#define TDR13 (*(volatile __near unsigned short *)0xFF76) +#define TDR13L (*(volatile __near unsigned char *)0xFF76) +#define TDR13H (*(volatile __near unsigned char *)0xFF77) +#define SEC (*(volatile __near unsigned char *)0xFF92) +#define MIN (*(volatile __near unsigned char *)0xFF93) +#define HOUR (*(volatile __near unsigned char *)0xFF94) +#define WEEK (*(volatile __near unsigned char *)0xFF95) +#define DAY (*(volatile __near unsigned char *)0xFF96) +#define MONTH (*(volatile __near unsigned char *)0xFF97) +#define YEAR (*(volatile __near unsigned char *)0xFF98) +#define SUBCUD (*(volatile __near unsigned char *)0xFF99) +#define ALARMWM (*(volatile __near unsigned char *)0xFF9A) +#define ALARMWH (*(volatile __near unsigned char *)0xFF9B) +#define ALARMWW (*(volatile __near unsigned char *)0xFF9C) +#define RTCC0 (*(volatile __near unsigned char *)0xFF9D) +#define RTCC0_bit (*(volatile __near __bitf_T *)0xFF9D) +#define RCLOE1 (((volatile __near __bitf_T *)0xFF9D)->no5) +#define RTCE (((volatile __near __bitf_T *)0xFF9D)->no7) +#define RTCC1 (*(volatile __near unsigned char *)0xFF9E) +#define RTCC1_bit (*(volatile __near __bitf_T *)0xFF9E) +#define RWAIT (((volatile __near __bitf_T *)0xFF9E)->no0) +#define RWST (((volatile __near __bitf_T *)0xFF9E)->no1) +#define RIFG (((volatile __near __bitf_T *)0xFF9E)->no3) +#define WAFG (((volatile __near __bitf_T *)0xFF9E)->no4) +#define WALIE (((volatile __near __bitf_T *)0xFF9E)->no6) +#define WALE (((volatile __near __bitf_T *)0xFF9E)->no7) +#define CMC (*(volatile __near unsigned char *)0xFFA0) +#define CSC (*(volatile __near unsigned char *)0xFFA1) +#define CSC_bit (*(volatile __near __bitf_T *)0xFFA1) +#define HIOSTOP (((volatile __near __bitf_T *)0xFFA1)->no0) +#define XTSTOP (((volatile __near __bitf_T *)0xFFA1)->no6) +#define MSTOP (((volatile __near __bitf_T *)0xFFA1)->no7) +#define OSTC (*(volatile __near unsigned char *)0xFFA2) +#define OSTC_bit (*(volatile __near __bitf_T *)0xFFA2) +#define OSTS (*(volatile __near unsigned char *)0xFFA3) +#define CKC (*(volatile __near unsigned char *)0xFFA4) +#define CKC_bit (*(volatile __near __bitf_T *)0xFFA4) +#define MCM0 (((volatile __near __bitf_T *)0xFFA4)->no4) +#define MCS (((volatile __near __bitf_T *)0xFFA4)->no5) +#define CSS (((volatile __near __bitf_T *)0xFFA4)->no6) +#define CLS (((volatile __near __bitf_T *)0xFFA4)->no7) +#define CKS0 (*(volatile __near unsigned char *)0xFFA5) +#define CKS0_bit (*(volatile __near __bitf_T *)0xFFA5) +#define PCLOE0 (((volatile __near __bitf_T *)0xFFA5)->no7) +#define RESF (*(volatile __near unsigned char *)0xFFA8) +#define LVIM (*(volatile __near unsigned char *)0xFFA9) +#define LVIM_bit (*(volatile __near __bitf_T *)0xFFA9) +#define LVIF (((volatile __near __bitf_T *)0xFFA9)->no0) +#define LVIOMSK (((volatile __near __bitf_T *)0xFFA9)->no1) +#define LVISEN (((volatile __near __bitf_T *)0xFFA9)->no7) +#define LVIS (*(volatile __near unsigned char *)0xFFAA) +#define LVIS_bit (*(volatile __near __bitf_T *)0xFFAA) +#define LVILV (((volatile __near __bitf_T *)0xFFAA)->no0) +#define LVIMD (((volatile __near __bitf_T *)0xFFAA)->no7) +#define WDTE (*(volatile __near unsigned char *)0xFFAB) +#define CRCIN (*(volatile __near unsigned char *)0xFFAC) +#define IF2 (*(volatile __near unsigned short *)0xFFD0) +#define IF2L (*(volatile __near unsigned char *)0xFFD0) +#define IF2L_bit (*(volatile __near __bitf_T *)0xFFD0) +#define IF2H (*(volatile __near unsigned char *)0xFFD1) +#define IF2H_bit (*(volatile __near __bitf_T *)0xFFD1) +#define TMIF05 (((volatile __near __bitf_T *)0xFFD0)->no0) +#define TMIF06 (((volatile __near __bitf_T *)0xFFD0)->no1) +#define TMIF07 (((volatile __near __bitf_T *)0xFFD0)->no2) +#define LIN0WUPIF (((volatile __near __bitf_T *)0xFFD0)->no3) +#define KRIF (((volatile __near __bitf_T *)0xFFD0)->no4) +#define TMIF10 (((volatile __near __bitf_T *)0xFFD1)->no3) +#define TMIF11 (((volatile __near __bitf_T *)0xFFD1)->no4) +#define TMIF12 (((volatile __near __bitf_T *)0xFFD1)->no5) +#define TMIF13 (((volatile __near __bitf_T *)0xFFD1)->no6) +#define FLIF (((volatile __near __bitf_T *)0xFFD1)->no7) +#define MK2 (*(volatile __near unsigned short *)0xFFD4) +#define MK2L (*(volatile __near unsigned char *)0xFFD4) +#define MK2L_bit (*(volatile __near __bitf_T *)0xFFD4) +#define MK2H (*(volatile __near unsigned char *)0xFFD5) +#define MK2H_bit (*(volatile __near __bitf_T *)0xFFD5) +#define TMMK05 (((volatile __near __bitf_T *)0xFFD4)->no0) +#define TMMK06 (((volatile __near __bitf_T *)0xFFD4)->no1) +#define TMMK07 (((volatile __near __bitf_T *)0xFFD4)->no2) +#define LIN0WUPMK (((volatile __near __bitf_T *)0xFFD4)->no3) +#define KRMK (((volatile __near __bitf_T *)0xFFD4)->no4) +#define TMMK10 (((volatile __near __bitf_T *)0xFFD5)->no3) +#define TMMK11 (((volatile __near __bitf_T *)0xFFD5)->no4) +#define TMMK12 (((volatile __near __bitf_T *)0xFFD5)->no5) +#define TMMK13 (((volatile __near __bitf_T *)0xFFD5)->no6) +#define FLMK (((volatile __near __bitf_T *)0xFFD5)->no7) +#define PR02 (*(volatile __near unsigned short *)0xFFD8) +#define PR02L (*(volatile __near unsigned char *)0xFFD8) +#define PR02L_bit (*(volatile __near __bitf_T *)0xFFD8) +#define PR02H (*(volatile __near unsigned char *)0xFFD9) +#define PR02H_bit (*(volatile __near __bitf_T *)0xFFD9) +#define TMPR005 (((volatile __near __bitf_T *)0xFFD8)->no0) +#define TMPR006 (((volatile __near __bitf_T *)0xFFD8)->no1) +#define TMPR007 (((volatile __near __bitf_T *)0xFFD8)->no2) +#define LIN0WUPPR0 (((volatile __near __bitf_T *)0xFFD8)->no3) +#define KRPR0 (((volatile __near __bitf_T *)0xFFD8)->no4) +#define TMPR010 (((volatile __near __bitf_T *)0xFFD9)->no3) +#define TMPR011 (((volatile __near __bitf_T *)0xFFD9)->no4) +#define TMPR012 (((volatile __near __bitf_T *)0xFFD9)->no5) +#define TMPR013 (((volatile __near __bitf_T *)0xFFD9)->no6) +#define FLPR0 (((volatile __near __bitf_T *)0xFFD9)->no7) +#define PR12 (*(volatile __near unsigned short *)0xFFDC) +#define PR12L (*(volatile __near unsigned char *)0xFFDC) +#define PR12L_bit (*(volatile __near __bitf_T *)0xFFDC) +#define PR12H (*(volatile __near unsigned char *)0xFFDD) +#define PR12H_bit (*(volatile __near __bitf_T *)0xFFDD) +#define TMPR105 (((volatile __near __bitf_T *)0xFFDC)->no0) +#define TMPR106 (((volatile __near __bitf_T *)0xFFDC)->no1) +#define TMPR107 (((volatile __near __bitf_T *)0xFFDC)->no2) +#define LIN0WUPPR1 (((volatile __near __bitf_T *)0xFFDC)->no3) +#define KRPR1 (((volatile __near __bitf_T *)0xFFDC)->no4) +#define TMPR110 (((volatile __near __bitf_T *)0xFFDD)->no3) +#define TMPR111 (((volatile __near __bitf_T *)0xFFDD)->no4) +#define TMPR112 (((volatile __near __bitf_T *)0xFFDD)->no5) +#define TMPR113 (((volatile __near __bitf_T *)0xFFDD)->no6) +#define FLPR1 (((volatile __near __bitf_T *)0xFFDD)->no7) +#define IF0 (*(volatile __near unsigned short *)0xFFE0) +#define IF0L (*(volatile __near unsigned char *)0xFFE0) +#define IF0L_bit (*(volatile __near __bitf_T *)0xFFE0) +#define IF0H (*(volatile __near unsigned char *)0xFFE1) +#define IF0H_bit (*(volatile __near __bitf_T *)0xFFE1) +#define WDTIIF (((volatile __near __bitf_T *)0xFFE0)->no0) +#define LVIIF (((volatile __near __bitf_T *)0xFFE0)->no1) +#define PIF0 (((volatile __near __bitf_T *)0xFFE0)->no2) +#define PIF1 (((volatile __near __bitf_T *)0xFFE0)->no3) +#define PIF2 (((volatile __near __bitf_T *)0xFFE0)->no4) +#define PIF3 (((volatile __near __bitf_T *)0xFFE0)->no5) +#define PIF4 (((volatile __near __bitf_T *)0xFFE0)->no6) +#define SPMIF (((volatile __near __bitf_T *)0xFFE0)->no6) +#define PIF5 (((volatile __near __bitf_T *)0xFFE0)->no7) +#define CLMIF (((volatile __near __bitf_T *)0xFFE1)->no0) +#define CSIIF00 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define IICIF00 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define STIF0 (((volatile __near __bitf_T *)0xFFE1)->no1) +#define CSIIF01 (((volatile __near __bitf_T *)0xFFE1)->no2) +#define IICIF01 (((volatile __near __bitf_T *)0xFFE1)->no2) +#define SRIF0 (((volatile __near __bitf_T *)0xFFE1)->no2) +#define TRDIF0 (((volatile __near __bitf_T *)0xFFE1)->no3) +#define TRDIF1 (((volatile __near __bitf_T *)0xFFE1)->no4) +#define TRJIF0 (((volatile __near __bitf_T *)0xFFE1)->no5) +#define RAMIF (((volatile __near __bitf_T *)0xFFE1)->no6) +#define LIN0TRMIF (((volatile __near __bitf_T *)0xFFE1)->no7) +#define IF1 (*(volatile __near unsigned short *)0xFFE2) +#define IF1L (*(volatile __near unsigned char *)0xFFE2) +#define IF1L_bit (*(volatile __near __bitf_T *)0xFFE2) +#define IF1H (*(volatile __near unsigned char *)0xFFE3) +#define IF1H_bit (*(volatile __near __bitf_T *)0xFFE3) +#define LIN0RVCIF (((volatile __near __bitf_T *)0xFFE2)->no0) +#define LIN0IF (((volatile __near __bitf_T *)0xFFE2)->no1) +#define LIN0STAIF (((volatile __near __bitf_T *)0xFFE2)->no1) +#define IICAIF0 (((volatile __near __bitf_T *)0xFFE2)->no2) +#define PIF8 (((volatile __near __bitf_T *)0xFFE2)->no3) +#define RTCIF (((volatile __near __bitf_T *)0xFFE2)->no3) +#define TMIF00 (((volatile __near __bitf_T *)0xFFE2)->no4) +#define TMIF01 (((volatile __near __bitf_T *)0xFFE2)->no5) +#define TMIF02 (((volatile __near __bitf_T *)0xFFE2)->no6) +#define TMIF03 (((volatile __near __bitf_T *)0xFFE2)->no7) +#define ADIF (((volatile __near __bitf_T *)0xFFE3)->no0) +#define PIF6 (((volatile __near __bitf_T *)0xFFE3)->no1) +#define TMIF11H (((volatile __near __bitf_T *)0xFFE3)->no1) +#define PIF7 (((volatile __near __bitf_T *)0xFFE3)->no2) +#define TMIF13H (((volatile __near __bitf_T *)0xFFE3)->no2) +#define PIF9 (((volatile __near __bitf_T *)0xFFE3)->no3) +#define TMIF01H (((volatile __near __bitf_T *)0xFFE3)->no3) +#define TMIF03H (((volatile __near __bitf_T *)0xFFE3)->no4) +#define CSIIF10 (((volatile __near __bitf_T *)0xFFE3)->no5) +#define IICIF10 (((volatile __near __bitf_T *)0xFFE3)->no5) +#define STIF1 (((volatile __near __bitf_T *)0xFFE3)->no5) +#define CSIIF11 (((volatile __near __bitf_T *)0xFFE3)->no6) +#define IICIF11 (((volatile __near __bitf_T *)0xFFE3)->no6) +#define SRIF1 (((volatile __near __bitf_T *)0xFFE3)->no6) +#define TMIF04 (((volatile __near __bitf_T *)0xFFE3)->no7) +#define MK0 (*(volatile __near unsigned short *)0xFFE4) +#define MK0L (*(volatile __near unsigned char *)0xFFE4) +#define MK0L_bit (*(volatile __near __bitf_T *)0xFFE4) +#define MK0H (*(volatile __near unsigned char *)0xFFE5) +#define MK0H_bit (*(volatile __near __bitf_T *)0xFFE5) +#define WDTIMK (((volatile __near __bitf_T *)0xFFE4)->no0) +#define LVIMK (((volatile __near __bitf_T *)0xFFE4)->no1) +#define PMK0 (((volatile __near __bitf_T *)0xFFE4)->no2) +#define PMK1 (((volatile __near __bitf_T *)0xFFE4)->no3) +#define PMK2 (((volatile __near __bitf_T *)0xFFE4)->no4) +#define PMK3 (((volatile __near __bitf_T *)0xFFE4)->no5) +#define PMK4 (((volatile __near __bitf_T *)0xFFE4)->no6) +#define SPMMK (((volatile __near __bitf_T *)0xFFE4)->no6) +#define PMK5 (((volatile __near __bitf_T *)0xFFE4)->no7) +#define CLMMK (((volatile __near __bitf_T *)0xFFE5)->no0) +#define CSIMK00 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define IICMK00 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define STMK0 (((volatile __near __bitf_T *)0xFFE5)->no1) +#define CSIMK01 (((volatile __near __bitf_T *)0xFFE5)->no2) +#define IICMK01 (((volatile __near __bitf_T *)0xFFE5)->no2) +#define SRMK0 (((volatile __near __bitf_T *)0xFFE5)->no2) +#define TRDMK0 (((volatile __near __bitf_T *)0xFFE5)->no3) +#define TRDMK1 (((volatile __near __bitf_T *)0xFFE5)->no4) +#define TRJMK0 (((volatile __near __bitf_T *)0xFFE5)->no5) +#define RAMMK (((volatile __near __bitf_T *)0xFFE5)->no6) +#define LIN0TRMMK (((volatile __near __bitf_T *)0xFFE5)->no7) +#define MK1 (*(volatile __near unsigned short *)0xFFE6) +#define MK1L (*(volatile __near unsigned char *)0xFFE6) +#define MK1L_bit (*(volatile __near __bitf_T *)0xFFE6) +#define MK1H (*(volatile __near unsigned char *)0xFFE7) +#define MK1H_bit (*(volatile __near __bitf_T *)0xFFE7) +#define LIN0RVCMK (((volatile __near __bitf_T *)0xFFE6)->no0) +#define LIN0MK (((volatile __near __bitf_T *)0xFFE6)->no1) +#define LIN0STAMK (((volatile __near __bitf_T *)0xFFE6)->no1) +#define IICAMK0 (((volatile __near __bitf_T *)0xFFE6)->no2) +#define PMK8 (((volatile __near __bitf_T *)0xFFE6)->no3) +#define RTCMK (((volatile __near __bitf_T *)0xFFE6)->no3) +#define TMMK00 (((volatile __near __bitf_T *)0xFFE6)->no4) +#define TMMK01 (((volatile __near __bitf_T *)0xFFE6)->no5) +#define TMMK02 (((volatile __near __bitf_T *)0xFFE6)->no6) +#define TMMK03 (((volatile __near __bitf_T *)0xFFE6)->no7) +#define ADMK (((volatile __near __bitf_T *)0xFFE7)->no0) +#define PMK6 (((volatile __near __bitf_T *)0xFFE7)->no1) +#define TMMK11H (((volatile __near __bitf_T *)0xFFE7)->no1) +#define PMK7 (((volatile __near __bitf_T *)0xFFE7)->no2) +#define TMMK13H (((volatile __near __bitf_T *)0xFFE7)->no2) +#define PMK9 (((volatile __near __bitf_T *)0xFFE7)->no3) +#define TMMK01H (((volatile __near __bitf_T *)0xFFE7)->no3) +#define TMMK03H (((volatile __near __bitf_T *)0xFFE7)->no4) +#define CSIMK10 (((volatile __near __bitf_T *)0xFFE7)->no5) +#define IICMK10 (((volatile __near __bitf_T *)0xFFE7)->no5) +#define STMK1 (((volatile __near __bitf_T *)0xFFE7)->no5) +#define CSIMK11 (((volatile __near __bitf_T *)0xFFE7)->no6) +#define IICMK11 (((volatile __near __bitf_T *)0xFFE7)->no6) +#define SRMK1 (((volatile __near __bitf_T *)0xFFE7)->no6) +#define TMMK04 (((volatile __near __bitf_T *)0xFFE7)->no7) +#define PR00 (*(volatile __near unsigned short *)0xFFE8) +#define PR00L (*(volatile __near unsigned char *)0xFFE8) +#define PR00L_bit (*(volatile __near __bitf_T *)0xFFE8) +#define PR00H (*(volatile __near unsigned char *)0xFFE9) +#define PR00H_bit (*(volatile __near __bitf_T *)0xFFE9) +#define WDTIPR0 (((volatile __near __bitf_T *)0xFFE8)->no0) +#define LVIPR0 (((volatile __near __bitf_T *)0xFFE8)->no1) +#define PPR00 (((volatile __near __bitf_T *)0xFFE8)->no2) +#define PPR01 (((volatile __near __bitf_T *)0xFFE8)->no3) +#define PPR02 (((volatile __near __bitf_T *)0xFFE8)->no4) +#define PPR03 (((volatile __near __bitf_T *)0xFFE8)->no5) +#define PPR04 (((volatile __near __bitf_T *)0xFFE8)->no6) +#define SPMPR0 (((volatile __near __bitf_T *)0xFFE8)->no6) +#define PPR05 (((volatile __near __bitf_T *)0xFFE8)->no7) +#define CLMPR0 (((volatile __near __bitf_T *)0xFFE9)->no0) +#define CSIPR000 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define IICPR000 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define STPR00 (((volatile __near __bitf_T *)0xFFE9)->no1) +#define CSIPR001 (((volatile __near __bitf_T *)0xFFE9)->no2) +#define IICPR001 (((volatile __near __bitf_T *)0xFFE9)->no2) +#define SRPR00 (((volatile __near __bitf_T *)0xFFE9)->no2) +#define TRDPR00 (((volatile __near __bitf_T *)0xFFE9)->no3) +#define TRDPR01 (((volatile __near __bitf_T *)0xFFE9)->no4) +#define TRJPR00 (((volatile __near __bitf_T *)0xFFE9)->no5) +#define RAMPR0 (((volatile __near __bitf_T *)0xFFE9)->no6) +#define LIN0TRMPR0 (((volatile __near __bitf_T *)0xFFE9)->no7) +#define PR01 (*(volatile __near unsigned short *)0xFFEA) +#define PR01L (*(volatile __near unsigned char *)0xFFEA) +#define PR01L_bit (*(volatile __near __bitf_T *)0xFFEA) +#define PR01H (*(volatile __near unsigned char *)0xFFEB) +#define PR01H_bit (*(volatile __near __bitf_T *)0xFFEB) +#define LIN0RVCPR0 (((volatile __near __bitf_T *)0xFFEA)->no0) +#define LIN0PR0 (((volatile __near __bitf_T *)0xFFEA)->no1) +#define LIN0STAPR0 (((volatile __near __bitf_T *)0xFFEA)->no1) +#define IICAPR00 (((volatile __near __bitf_T *)0xFFEA)->no2) +#define PPR08 (((volatile __near __bitf_T *)0xFFEA)->no3) +#define RTCPR0 (((volatile __near __bitf_T *)0xFFEA)->no3) +#define TMPR000 (((volatile __near __bitf_T *)0xFFEA)->no4) +#define TMPR001 (((volatile __near __bitf_T *)0xFFEA)->no5) +#define TMPR002 (((volatile __near __bitf_T *)0xFFEA)->no6) +#define TMPR003 (((volatile __near __bitf_T *)0xFFEA)->no7) +#define ADPR0 (((volatile __near __bitf_T *)0xFFEB)->no0) +#define PPR06 (((volatile __near __bitf_T *)0xFFEB)->no1) +#define TMPR011H (((volatile __near __bitf_T *)0xFFEB)->no1) +#define PPR07 (((volatile __near __bitf_T *)0xFFEB)->no2) +#define TMPR013H (((volatile __near __bitf_T *)0xFFEB)->no2) +#define PPR09 (((volatile __near __bitf_T *)0xFFEB)->no3) +#define TMPR001H (((volatile __near __bitf_T *)0xFFEB)->no3) +#define TMPR003H (((volatile __near __bitf_T *)0xFFEB)->no4) +#define CSIPR010 (((volatile __near __bitf_T *)0xFFEB)->no5) +#define IICPR010 (((volatile __near __bitf_T *)0xFFEB)->no5) +#define STPR01 (((volatile __near __bitf_T *)0xFFEB)->no5) +#define CSIPR011 (((volatile __near __bitf_T *)0xFFEB)->no6) +#define IICPR011 (((volatile __near __bitf_T *)0xFFEB)->no6) +#define SRPR01 (((volatile __near __bitf_T *)0xFFEB)->no6) +#define TMPR004 (((volatile __near __bitf_T *)0xFFEB)->no7) +#define PR10 (*(volatile __near unsigned short *)0xFFEC) +#define PR10L (*(volatile __near unsigned char *)0xFFEC) +#define PR10L_bit (*(volatile __near __bitf_T *)0xFFEC) +#define PR10H (*(volatile __near unsigned char *)0xFFED) +#define PR10H_bit (*(volatile __near __bitf_T *)0xFFED) +#define WDTIPR1 (((volatile __near __bitf_T *)0xFFEC)->no0) +#define LVIPR1 (((volatile __near __bitf_T *)0xFFEC)->no1) +#define PPR10 (((volatile __near __bitf_T *)0xFFEC)->no2) +#define PPR11 (((volatile __near __bitf_T *)0xFFEC)->no3) +#define PPR12 (((volatile __near __bitf_T *)0xFFEC)->no4) +#define PPR13 (((volatile __near __bitf_T *)0xFFEC)->no5) +#define PPR14 (((volatile __near __bitf_T *)0xFFEC)->no6) +#define SPMPR1 (((volatile __near __bitf_T *)0xFFEC)->no6) +#define PPR15 (((volatile __near __bitf_T *)0xFFEC)->no7) +#define CLMPR1 (((volatile __near __bitf_T *)0xFFED)->no0) +#define CSIPR100 (((volatile __near __bitf_T *)0xFFED)->no1) +#define IICPR100 (((volatile __near __bitf_T *)0xFFED)->no1) +#define STPR10 (((volatile __near __bitf_T *)0xFFED)->no1) +#define CSIPR101 (((volatile __near __bitf_T *)0xFFED)->no2) +#define IICPR101 (((volatile __near __bitf_T *)0xFFED)->no2) +#define SRPR10 (((volatile __near __bitf_T *)0xFFED)->no2) +#define TRDPR10 (((volatile __near __bitf_T *)0xFFED)->no3) +#define TRDPR11 (((volatile __near __bitf_T *)0xFFED)->no4) +#define TRJPR10 (((volatile __near __bitf_T *)0xFFED)->no5) +#define RAMPR1 (((volatile __near __bitf_T *)0xFFED)->no6) +#define LIN0TRMPR1 (((volatile __near __bitf_T *)0xFFED)->no7) +#define PR11 (*(volatile __near unsigned short *)0xFFEE) +#define PR11L (*(volatile __near unsigned char *)0xFFEE) +#define PR11L_bit (*(volatile __near __bitf_T *)0xFFEE) +#define PR11H (*(volatile __near unsigned char *)0xFFEF) +#define PR11H_bit (*(volatile __near __bitf_T *)0xFFEF) +#define LIN0RVCPR1 (((volatile __near __bitf_T *)0xFFEE)->no0) +#define LIN0PR1 (((volatile __near __bitf_T *)0xFFEE)->no1) +#define LIN0STAPR1 (((volatile __near __bitf_T *)0xFFEE)->no1) +#define IICAPR10 (((volatile __near __bitf_T *)0xFFEE)->no2) +#define PPR18 (((volatile __near __bitf_T *)0xFFEE)->no3) +#define RTCPR1 (((volatile __near __bitf_T *)0xFFEE)->no3) +#define TMPR100 (((volatile __near __bitf_T *)0xFFEE)->no4) +#define TMPR101 (((volatile __near __bitf_T *)0xFFEE)->no5) +#define TMPR102 (((volatile __near __bitf_T *)0xFFEE)->no6) +#define TMPR103 (((volatile __near __bitf_T *)0xFFEE)->no7) +#define ADPR1 (((volatile __near __bitf_T *)0xFFEF)->no0) +#define PPR16 (((volatile __near __bitf_T *)0xFFEF)->no1) +#define TMPR111H (((volatile __near __bitf_T *)0xFFEF)->no1) +#define PPR17 (((volatile __near __bitf_T *)0xFFEF)->no2) +#define TMPR113H (((volatile __near __bitf_T *)0xFFEF)->no2) +#define PPR19 (((volatile __near __bitf_T *)0xFFEF)->no3) +#define TMPR101H (((volatile __near __bitf_T *)0xFFEF)->no3) +#define TMPR103H (((volatile __near __bitf_T *)0xFFEF)->no4) +#define CSIPR110 (((volatile __near __bitf_T *)0xFFEF)->no5) +#define IICPR110 (((volatile __near __bitf_T *)0xFFEF)->no5) +#define STPR11 (((volatile __near __bitf_T *)0xFFEF)->no5) +#define CSIPR111 (((volatile __near __bitf_T *)0xFFEF)->no6) +#define IICPR111 (((volatile __near __bitf_T *)0xFFEF)->no6) +#define SRPR11 (((volatile __near __bitf_T *)0xFFEF)->no6) +#define TMPR104 (((volatile __near __bitf_T *)0xFFEF)->no7) +#define MACRL (*(volatile __near unsigned short *)0xFFF0) +#define MACRH (*(volatile __near unsigned short *)0xFFF2) +#define PMC (*(volatile __near unsigned char *)0xFFFE) +#define PMC_bit (*(volatile __near __bitf_T *)0xFFFE) +#define MAA (((volatile __near __bitf_T *)0xFFFE)->no0) + + +#define INTSRO 0x0004 +#define INTWDTI 0x0004 +#define INTLVI 0x0006 +#define INTP0 0x0008 +#define INTP1 0x000A +#define INTP2 0x000C +#define INTP3 0x000E +#define INTP4 0x0010 +#define INTSPM 0x0010 +#define INTP5 0x0012 +#define INTCLM 0x0014 +#define INTCSI00 0x0016 +#define INTIIC00 0x0016 +#define INTST0 0x0016 +#define INTCSI01 0x0018 +#define INTIIC01 0x0018 +#define INTSR0 0x0018 +#define INTTRD0 0x001A +#define INTTRD1 0x001C +#define INTTRJ0 0x001E +#define INTRAM 0x0020 +#define INTLIN0TRM 0x0022 +#define INTLIN0RVC 0x0024 +#define INTLIN0 0x0026 +#define INTLIN0STA 0x0026 +#define INTIICA0 0x0028 +#define INTP8 0x002A +#define INTRTC 0x002A +#define INTTM00 0x002C +#define INTTM01 0x002E +#define INTTM02 0x0030 +#define INTTM03 0x0032 +#define INTAD 0x0034 +#define INTP6 0x0036 +#define INTTM11H 0x0036 +#define INTP7 0x0038 +#define INTTM13H 0x0038 +#define INTP9 0x003A +#define INTTM01H 0x003A +#define INTTM03H 0x003C +#define INTCSI10 0x003E +#define INTIIC10 0x003E +#define INTST1 0x003E +#define INTCSI11 0x0040 +#define INTIIC11 0x0040 +#define INTSR1 0x0040 +#define INTTM04 0x0042 +#define INTTM05 0x0044 +#define INTTM06 0x0046 +#define INTTM07 0x0048 +#define INTLIN0WUP 0x004A +#define INTKR 0x004C +#define INTTM10 0x005A +#define INTTM11 0x005C +#define INTTM12 0x005E +#define INTTM13 0x0060 +#define INTFL 0x0062 + +#endif diff --git a/app/main.c b/app/main.c new file mode 100644 index 0000000..20c5b4b --- /dev/null +++ b/app/main.c @@ -0,0 +1,35 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/***********************************************************************/ +/* */ +/* FILE :Main.c */ +/* DATE : */ +/* DESCRIPTION :Main Program */ +/* CPU TYPE : */ +/* */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + +void main(void); + +void main(void) +{ + +} diff --git a/app/r_cg_adc.c b/app/r_cg_adc.c new file mode 100644 index 0000000..3e13c3d --- /dev/null +++ b/app/r_cg_adc.c @@ -0,0 +1,139 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_adc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_ADC_Create +* Description : This function initializes the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Create(void) +{ + ADCEN = 1U; /* supply AD clock */ + ADM0 = _00_AD_ADM0_INITIALVALUE; /* disable AD conversion and clear ADM0 register */ + ADMK = 1U; /* disable INTAD interrupt */ + ADIF = 0U; /* clear INTAD interrupt flag */ + /* Set INTAD low priority */ + ADPR1 = 1U; + ADPR0 = 1U; + /* The reset status of ADPC is analog input, so it's unnecessary to set. */ + /* Set ANI0 - ANI3 pin as analog input */ + PM8 |= 0x03U; + PM3 |= 0x18U; + ADM0 = _00_AD_CONVERSION_CLOCK_64 | _00_AD_TIME_MODE_NORMAL_1 | _00_AD_OPERMODE_SELECT; + ADM1 = _80_AD_TRIGGER_HARDWARE_NOWAIT | _00_AD_CONVMODE_CONSELECT | _00_AD_TRIGGER_INTTM01; + ADM2 = _00_AD_POSITIVE_VDD | _00_AD_NEGATIVE_VSS | _00_AD_AREA_MODE_1 | _00_AD_RESOLUTION_10BIT; + ADUL = _FF_AD_ADUL_VALUE; + ADLL = _00_AD_ADLL_VALUE; + ADS = _00_AD_INPUT_CHANNEL_0; + ADCE = 1U; /* enable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Start +* Description : This function starts the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Start(void) +{ + ADIF = 0U; /* clear INTAD interrupt flag */ + ADMK = 0U; /* enable INTAD interrupt */ + ADCS = 1U; /* enable AD conversion */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Stop +* Description : This function stops the AD converter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Stop(void) +{ + ADCS = 0U; /* disable AD conversion */ + ADMK = 1U; /* disable INTAD interrupt */ + ADIF = 0U; /* clear INTAD interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Set_OperationOn +* Description : This function enables comparator operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Set_OperationOn(void) +{ + ADCE = 1U; /* enable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Set_OperationOff +* Description : This function stops comparator operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Set_OperationOff(void) +{ + ADCE = 0U; /* disable AD comparator */ +} + +/*********************************************************************************************************************** +* Function Name: R_ADC_Get_Result +* Description : This function returns the conversion result in the buffer. +* Arguments : buffer - +* the address where to write the conversion result +* Return Value : None +***********************************************************************************************************************/ +void R_ADC_Get_Result(uint16_t * const buffer) +{ + *buffer = (uint16_t)(ADCR >> 6U); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_adc.h b/app/r_cg_adc.h new file mode 100644 index 0000000..eca80d7 --- /dev/null +++ b/app/r_cg_adc.h @@ -0,0 +1,193 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef ADC_H +#define ADC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Peripheral enable register 0 (PER0) +*/ +/* Control of AD converter input clock (ADCEN) */ +#define _00_AD_CLOCK_STOP (0x00U) /* stop supply of input clock */ +#define _20_AD_CLOCK_SUPPLY (0x20U) /* supply input clock */ + +/* + AD converter mode register 0 (ADM0) +*/ +#define _00_AD_ADM0_INITIALVALUE (0x00U) +/* AD conversion operation control (ADCS) */ +#define _80_AD_CONVERSION_ENABLE (0x80U) /* enable AD conversion operation control */ +#define _00_AD_CONVERSION_DISABLE (0x00U) /* disable AD conversion operation control */ +/* Specification of AD conversion operation mode (ADMD) */ +#define _00_AD_OPERMODE_SELECT (0x00U) /* select operation mode */ +#define _40_AD_OPERMODE_SCAN (0x40U) /* scan operation mode */ +/* AD conversion clock selection (FR2 - FR0) */ +#define _00_AD_CONVERSION_CLOCK_64 (0x00U) /* fCLK/64 */ +#define _08_AD_CONVERSION_CLOCK_32 (0x08U) /* fCLK/32 */ +#define _10_AD_CONVERSION_CLOCK_16 (0x10U) /* fCLK/16 */ +#define _18_AD_CONVERSION_CLOCK_8 (0x18U) /* fCLK/8 */ +#define _20_AD_CONVERSION_CLOCK_6 (0x20U) /* fCLK/6 */ +#define _28_AD_CONVERSION_CLOCK_5 (0x28U) /* fCLK/5 */ +#define _30_AD_CONVERSION_CLOCK_4 (0x30U) /* fCLK/4 */ +#define _38_AD_CONVERSION_CLOCK_2 (0x38U) /* fCLK/2 */ +/* Specification AD conversion time mode (LV1, LV0) */ +#define _00_AD_TIME_MODE_NORMAL_1 (0x00U) /* normal 1 mode */ +#define _02_AD_TIME_MODE_NORMAL_2 (0x02U) /* normal 2 mode */ +/* AD comparator operation control (ADCE) */ +#define _01_AD_COMPARATOR_ENABLE (0x01U) /* enable comparator operation control */ +#define _00_AD_COMPARATOR_DISABLE (0x00U) /* disable comparator operation control */ + +/* + Analog input channel specification register (ADS) +*/ +/* Specification of analog input channel (ADISS, ADS4 - ADS0) */ +/* Select mode */ +#define _00_AD_INPUT_CHANNEL_0 (0x00U) /* ANI0 */ +#define _01_AD_INPUT_CHANNEL_1 (0x01U) /* ANI1 */ +#define _02_AD_INPUT_CHANNEL_2 (0x02U) /* ANI2 */ +#define _03_AD_INPUT_CHANNEL_3 (0x03U) /* ANI3 */ +#define _04_AD_INPUT_CHANNEL_4 (0x04U) /* ANI4 */ +#define _05_AD_INPUT_CHANNEL_5 (0x05U) /* ANI5 */ +#define _06_AD_INPUT_CHANNEL_6 (0x06U) /* ANI6 */ +#define _07_AD_INPUT_CHANNEL_7 (0x07U) /* ANI7 */ +#define _08_AD_INPUT_CHANNEL_8 (0x08U) /* ANI8 */ +#define _09_AD_INPUT_CHANNEL_9 (0x09U) /* ANI9 */ +#define _0A_AD_INPUT_CHANNEL_10 (0x0AU) /* ANI10 */ +#define _0B_AD_INPUT_CHANNEL_11 (0x0BU) /* ANI11 */ +#define _0C_AD_INPUT_CHANNEL_12 (0x0CU) /* ANI12 */ +#define _18_AD_INPUT_CHANNEL_24 (0x18U) /* ANI24 */ +#define _19_AD_INPUT_CHANNEL_25 (0x19U) /* ANI25 */ +#define _80_AD_INPUT_TEMPERSENSOR_0 (0x80U) /* temperature sensor 0 output is used to be the input channel */ +#define _81_AD_INPUT_INTERREFVOLT (0x81U) /* internal reference voltage output is used to be the input channel */ +/* Scan mode */ +#define _00_AD_INPUT_CHANNEL_0_3 (0x00U) /* ANI0 - ANI3 */ +#define _01_AD_INPUT_CHANNEL_1_4 (0x01U) /* ANI1 - ANI4 */ +#define _02_AD_INPUT_CHANNEL_2_5 (0x02U) /* ANI2 - ANI5 */ +#define _03_AD_INPUT_CHANNEL_3_6 (0x03U) /* ANI3 - ANI6 */ +#define _04_AD_INPUT_CHANNEL_4_7 (0x04U) /* ANI4 - ANI7 */ +#define _05_AD_INPUT_CHANNEL_5_8 (0x05U) /* ANI5 - ANI8 */ +#define _06_AD_INPUT_CHANNEL_6_9 (0x06U) /* ANI6 - ANI9 */ +#define _07_AD_INPUT_CHANNEL_7_10 (0x07U) /* ANI7 - ANI10 */ +#define _08_AD_INPUT_CHANNEL_8_11 (0x08U) /* ANI8 - ANI11 */ +#define _09_AD_INPUT_CHANNEL_9_12 (0x09U) /* ANI9 - ANI12 */ + +/* + AD converter mode register 1 (ADM1) +*/ +/* AD trigger mode selection (ADTMD1, ADTMD0) */ +#define _00_AD_TRIGGER_SOFTWARE (0x00U) /* software trigger mode */ +#define _80_AD_TRIGGER_HARDWARE_NOWAIT (0x80U) /* hardware trigger mode (no wait) */ +#define _C0_AD_TRIGGER_HARDWARE_WAIT (0xC0U) /* hardware trigger mode (wait) */ +/* AD convertion mode selection (ADSCM) */ +#define _00_AD_CONVMODE_CONSELECT (0x00U) /* continuous convertion mode */ +#define _20_AD_CONVMODE_ONESELECT (0x20U) /* oneshot convertion mode */ +/* Trigger signal selection (ADTRS1, ADTRS0) */ +#define _00_AD_TRIGGER_INTTM01 (0x00U) /* INTTM01 */ +#define _01_AD_TRIGGER_ELC (0x01U) /* ELC */ +#define _01_AD_TRIGGER_TIMER (0x01U) /* INTTRD0,INTTRJ0 */ +#define _02_AD_TRIGGER_INTRTC (0x02U) /* INTRTC */ +/* + AD converter mode register 2 (ADM2) +*/ +/* AD VREF(+) selection (ADREFP1, ADREFP0) */ +#define _00_AD_POSITIVE_VDD (0x00U) /* use VDD as VREF(+) */ +#define _40_AD_POSITIVE_AVREFP (0x40U) /* use AVREFP as VREF(+) */ +#define _80_AD_POSITIVE_INTERVOLT (0x80U) /* use internal voltage as VREF(+) */ +/* AD VREF(-) selection (ADREFM) */ +#define _00_AD_NEGATIVE_VSS (0x00U) /* use VSS as VREF(-) */ +#define _20_AD_NEGATIVE_AVREFM (0x20U) /* use AVREFM as VREF(-) */ +/* AD conversion result upper/lower bound value selection (ADRCK) */ +#define _00_AD_AREA_MODE_1 (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */ +#define _08_AD_AREA_MODE_2_3 (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */ +/* AD wakeup function selection (AWC) */ +#define _00_AD_WAKEUP_OFF (0x00U) /* stop wakeup function */ +#define _04_AD_WAKEUP_ON (0x04U) /* use wakeup function */ +/* AD resolution selection (ADTYP) */ +#define _00_AD_RESOLUTION_10BIT (0x00U) /* 10 bits */ +#define _01_AD_RESOLUTION_8BIT (0x01U) /* 8 bits */ + +/* + AD test function register (ADTES) +*/ +/* AD test mode signal (ADTES2 - ADTES0) */ +#define _00_AD_NORMAL_INPUT (0x00U) /* normal mode */ +#define _02_AD_TEST_AVREFM (0x02U) /* use AVREFM as test signal */ +#define _03_AD_TEST_AVREFP (0x03U) /* use AVREFP as test signal */ +/* + Format of A/D Converter Trigger Select Register 0 (ADTRGS0)(F13 only) +*/ +/* Selection of the operation trigger of the A/D converter when the timer RD0 input capture B/compare match B +interrupt request is generated (ADTRGS00) */ +#define _01_AD_TRIGGER_INTTRD0 (0x01U) /* A/D conversion is started when the interrupt request is generated */ + +/* + Format of A/D Converter Trigger Select Register 1 (ADTRGS1)(F13 only) +*/ +/* Selection of the operation trigger of the A/D converter when the timer RJ0 interrupt request is generated (ADTRGS10) */ +#define _01_AD_TRIGGER_INTTRJ0 (0x01U) /* A/D conversion is started when the interrupt request is generated */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Upper bound (ADUL) value */ +#define _FF_AD_ADUL_VALUE (0xFFU) +/* Upper bound (ADLL) value */ +#define _00_AD_ADLL_VALUE (0x00U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef enum +{ + ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL4, ADCHANNEL5, ADCHANNEL6, + ADCHANNEL7, ADCHANNEL8, ADCHANNEL9, ADCHANNEL10, ADCHANNEL11, ADCHANNEL12, + ADCHANNEL24 = 24U, ADCHANNEL25, ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT +} ad_channel_t; +typedef enum +{ + ADNORMALINPUT, + ADAVREFM = 2U, + ADAVREFP +} test_channel_t; + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_ADC_Create(void); +void R_ADC_Start(void); +void R_ADC_Stop(void); +void R_ADC_Set_OperationOn(void); +void R_ADC_Set_OperationOff(void); +void R_ADC_Get_Result(uint16_t * const buffer); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_adc_user.c b/app/r_cg_adc_user.c new file mode 100644 index 0000000..7be48f7 --- /dev/null +++ b/app/r_cg_adc_user.c @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_adc_user.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for ADC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_adc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_adc_interrupt(vect=INTAD) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +uint16_t g_adval[4]; +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_adc_interrupt +* Description : This function is INTAD interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_adc_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + switch (ADS) + { + case _00_AD_INPUT_CHANNEL_0: + R_ADC_Get_Result(g_adval); + ADS = _01_AD_INPUT_CHANNEL_1; + break; + case _01_AD_INPUT_CHANNEL_1: + R_ADC_Get_Result(g_adval+1); + ADS = _02_AD_INPUT_CHANNEL_2; + break; + case _02_AD_INPUT_CHANNEL_2: + R_ADC_Get_Result(g_adval+2); + ADS = _03_AD_INPUT_CHANNEL_3; + break; + case _03_AD_INPUT_CHANNEL_3: + R_ADC_Get_Result(g_adval+3); + ADS = _00_AD_INPUT_CHANNEL_0; + break; + default: + ADS = _00_AD_INPUT_CHANNEL_0; + break; + } + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_cgc.c b/app/r_cg_cgc.c new file mode 100644 index 0000000..49b99ea --- /dev/null +++ b/app/r_cg_cgc.c @@ -0,0 +1,82 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + /* Set fSL */ + SELLOSC = 1U; + /* Set fMX */ + CMC = _00_CGC_HISYS_PORT | _00_CGC_SUB_PORT | _00_CGC_SYSOSC_DEFAULT | _00_CGC_SUBMODE_DEFAULT; + MSTOP = 1U; + /* Set fMAIN */ + MCM0 = 0U; + MDIV = _01_CGC_FMP_DIV_1; + /* Set fMP to clock through mode */ + SELPLL = 0U; + /* Set fSUB */ + XTSTOP = 1U; + /* Set fCLK */ + CSS = 0U; + /* Set fIH */ + HIOSTOP = 0U; + /* Set RTC clock source */ + RTCCL = _80_CGC_RTC_FIH; + RTCCL |= _42_CGC_RTC_DIV122; + /* Set Timer RD clock source to fCLK, fMP */ + TRD_CKSEL = 0U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_cgc.h b/app/r_cg_cgc.h new file mode 100644 index 0000000..ca99a45 --- /dev/null +++ b/app/r_cg_cgc.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Clock operation mode control register (CMC) +*/ +/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */ +#define _C0_CGC_HISYS_PIN (0xC0U) +#define _00_CGC_HISYS_PORT (0x00U) /* X1, X2 as I/O port */ +#define _40_CGC_HISYS_OSC (0x40U) /* X1, X2 as crystal/ceramic resonator connection */ +#define _80_CGC_HISYS_PORT1 (0x80U) /* X1, X2 as I/O port */ +#define _C0_CGC_HISYS_EXT (0xC0U) /* X1 as I/O port, X2 as external clock input */ +/* Subsystem clock pin operation mode (EXCLKS, OSCSELS) */ +#define _30_CGC_SUB_PIN (0x30U) +#define _00_CGC_SUB_PORT (0x00U) /* XT1, XT2 as I/O port */ +#define _10_CGC_SUB_OSC (0x10U) /* XT1, XT2 as crystal connection */ +#define _20_CGC_SUB_PORT1 (0x20U) /* XT1, XT2 as I/O port */ +#define _30_CGC_SUB_EXT (0x30U) /* XT1 as I/O port, XT2 as external clock input */ +/* XT1 oscillator oscillation mode selection (AMPHS1, AMPHS0) */ +#define _00_CGC_SUBMODE_DEFAULT (0x00U) +#define _00_CGC_SUBMODE_LOW (0x00U) /* low power consumption oscillation */ +#define _02_CGC_SUBMODE_NORMAL (0x02U) /* normal oscillation */ +#define _04_CGC_SUBMODE_ULOW (0x04U) /* ultra-low power consumption oscillation */ +/* Control of X1 high-speed system clock oscillation frequency (AMPH) */ +#define _00_CGC_SYSOSC_DEFAULT (0x00U) +#define _00_CGC_SYSOSC_UNDER10M (0x00U) /* fX <= 10MHz */ +#define _01_CGC_SYSOSC_OVER10M (0x01U) /* fX > 10MHz */ + +/* + Clock operation status control register (CSC) +*/ +/* Control of high-speed system clock operation (MSTOP) */ +#define _00_CGC_HISYS_OPER (0x00U) /* X1 oscillator/external clock operating */ +#define _80_CGC_HISYS_STOP (0x80U) /* X1 oscillator/external clock stopped */ +/* Subsystem clock operation (XTSTOP) */ +#define _00_CGC_SUB_OPER (0x00U) /* XT1 oscillator operating */ +#define _40_CGC_SUB_STOP (0x40U) /* XT1 oscillator stopped */ +/* High-speed OCO operation (HIOSTOP) */ +#define _00_CGC_HIO_OPER (0x00U) /* high-speed OCO operating */ +#define _01_CGC_HIO_STOP (0x01U) /* high-speed OCO stopped */ + +/* + Oscillation stabilization time counter status register (OSTC) +*/ +/* Oscillation stabilization time status (MOST18 - MOST8) */ +#define _00_CGC_OSCSTAB_STA0 (0x00U) /* < 2^8/fX */ +#define _80_CGC_OSCSTAB_STA8 (0x80U) /* 2^8/fX */ +#define _C0_CGC_OSCSTAB_STA9 (0xC0U) /* 2^9/fX */ +#define _E0_CGC_OSCSTAB_STA10 (0xE0U) /* 2^10/fX */ +#define _F0_CGC_OSCSTAB_STA11 (0xF0U) /* 2^11/fX */ +#define _F8_CGC_OSCSTAB_STA13 (0xF8U) /* 2^13/fX */ +#define _FC_CGC_OSCSTAB_STA15 (0xFCU) /* 2^15/fX */ +#define _FE_CGC_OSCSTAB_STA17 (0xFEU) /* 2^17/fX */ +#define _FF_CGC_OSCSTAB_STA18 (0xFFU) /* 2^18/fX */ + +/* + Oscillation stabilization time select register (OSTS) +*/ +/* Oscillation stabilization time selection (OSTS2 - OSTS0) */ +#define _00_CGC_OSCSTAB_SEL8 (0x00U) /* 2^8/fX */ +#define _01_CGC_OSCSTAB_SEL9 (0x01U) /* 2^9/fX */ +#define _02_CGC_OSCSTAB_SEL10 (0x02U) /* 2^10/fX */ +#define _03_CGC_OSCSTAB_SEL11 (0x03U) /* 2^11/fX */ +#define _04_CGC_OSCSTAB_SEL13 (0x04U) /* 2^13/fX */ +#define _05_CGC_OSCSTAB_SEL15 (0x05U) /* 2^15/fX */ +#define _06_CGC_OSCSTAB_SEL17 (0x06U) /* 2^17/fX */ +#define _07_CGC_OSCSTAB_SEL18 (0x07U) /* 2^18/fX */ + +/* + PLL control register (PLLCTL) +*/ +/* Lockup wait counter setting value */ +#define _00_CGC_LOCKUP_WAIT_7 (0x00U) /* 2^7/fMAIN */ +#define _40_CGC_LOCKUP_WAIT_8 (0x40U) /* 2^8/fMAIN */ +#define _80_CGC_LOCKUP_WAIT_9 (0x80U) /* 2^9/fMAIN */ +/* PLL output clock selection (PLLDIV1) */ +#define _00_CGC_PLL_BELOW_32MHZ (0x00U) /* when fMAIN <= 32 MHz */ +#define _20_CGC_PLL_ABOVE_32MHZ (0x20U) /* when fMAIN > 32 MHz */ +/* PLL output clock division selection (PLLDIV0) */ +#define _00_CGC_PLL_DIVISION_2 (0x00U) /* divides the clock frequency by 2 */ +#define _10_CGC_PLL_DIVISION_4 (0x10U) /* divides the clock frequency by 4 */ +/* Clock mode selection (SELPLL) */ +#define _00_CGC_NOSEL_PLL (0x00U) /* clock through mode */ +#define _04_CGC_SEL_PLL (0x04U) /* PLL clock select mode */ +/* PLL output clock (fPLLO) multiplier selection (PLLMUL) */ +#define _00_CGC_PLL_MULTIPLY_X12 (0x00U) /* clock through mode */ +#define _02_CGC_PLL_MULTIPLY_X16 (0x02U) /* PLL clock select mode */ +/* Operating or stopping PLL function (PLLON) */ +#define _00_CGC_PLL_STOP (0x00U) /* PLL operating stopped */ +#define _01_CGC_PLL_ENABLE (0x01U) /* PLL operating */ + +/* + PLL status register (PLLSTS) +*/ +/* PLL lock state */ +#define _00_CGC_PLL_UNLOCKED (0x00U) /* Unlocked state */ +#define _80_CGC_PLL_LOCKED (0x80U) /* Locked state */ + +/* + FMP clock selection division register (MDIV) +*/ +/* Division of PLL clock (fMP) */ +#define _00_CGC_FMP_DIV_DEFAULT (0x00U) /* fMP (default) */ +#define _01_CGC_FMP_DIV_1 (0x01U) /* fMP/2^1 */ +#define _02_CGC_FMP_DIV_2 (0x02U) /* fMP/2^2 */ +#define _03_CGC_FMP_DIV_3 (0x03U) /* fMP/2^3 */ +#define _04_CGC_FMP_DIV_4 (0x04U) /* fMP/2^4 */ +#define _05_CGC_FMP_DIV_5 (0x05U) /* fMP/2^5 */ +#define _06_CGC_FMP_DIV_6 (0x06U) /* fMP/2^6 */ + +/* + System clock control register (CKC) +*/ +/* Status of CPU/peripheral hardware clock fCLK (CLS) */ +#define _00_CGC_CPUCLK_MAIN (0x00U) /* main system clock (fMAIN) */ +#define _80_CGC_CPUCLK_SUB (0x80U) /* subsystem clock (fSUB) */ +/* Selection of CPU/peripheral hardware clock fCLK (CSS) */ +#define _00_CGC_CPUCLK_SELMAIN (0x00U) /* main system clock (fMAIN) */ +#define _40_CGC_CPUCLK_SELSUB (0x40U) /* subsystem clock (fSUB) */ +/* Status of Main system clock fMAIN (MCS) */ +#define _00_CGC_MAINCLK_HIO (0x00U) /* high-speed OCO clock (fIH) */ +#define _20_CGC_MAINCLK_HISYS (0x20U) /* high-speed system clock (fMX) */ +/* Selection of Main system clock fMAIN (MCM0) */ +#define _00_CGC_MAINCLK_SELHIO (0x00U) /* high-speed OCO clock (fIH) */ +#define _10_CGC_MAINCLK_SELHISYS (0x10U) /* high-speed system clock (fMX) */ + +/* + Operation speed mode control register (OSMC) +*/ +/* Setting in subsystem clock HALT mode (RTCLPC) */ +#define _00_CGC_SUBINHALT_ON (0x00U) /* enables supply of subsystem clock to peripheral functions */ +#define _80_CGC_SUBINHALT_OFF (0x80U) /* stops supply to peripheral functions other than RTC and interval timer */ +/* RTC macro operation clock (WUTMMCK0) */ +#define _00_CGC_RTC_CLK_OTHER (0x00U) /* Other than fIL */ +#define _10_CGC_RTC_CLK_FIL (0x10U) /* use fIL clock */ + +/* + Illegal memory access detection control register (IAWCTL) +*/ +/* Illegal memory access detection control (IAWEN) */ +#define _00_CGC_ILLEGAL_ACCESS_OFF (0x00U) /* disables illegal memory access detection */ +#define _80_CGC_ILLEGAL_ACCESS_ON (0x80U) /* enables illegal memory access detection */ +/* RAM guard area (GRAM1, GRAM0) */ +#define _00_CGC_RAM_GUARD_OFF (0x00U) /* invalid, it is possible to write RAM */ +#define _10_CGC_RAM_GUARD_AREA0 (0x10U) /* 128 bytes from RAM bottom address */ +#define _20_CGC_RAM_GUARD_AREA1 (0x20U) /* 256 bytes from RAM bottom address */ +#define _30_CGC_RAM_GUARD_AREA2 (0x30U) /* 512 bytes from RAM bottom address */ +/* PORT register guard (GPORT) */ +#define _00_CGC_PORT_GUARD_OFF (0x00U) /* invalid, it is possible to write PORT register */ +#define _04_CGC_PORT_GUARD_ON (0x04U) /* valid, it is impossible to write PORT register, but possible for read */ +/* Interrupt register guard (GINT) */ +#define _00_CGC_INT_GUARD_OFF (0x00U) /* invalid, it is possible to write interrupt register */ +#define _02_CGC_INT_GUARD_ON (0x02U) /* valid, it is impossible to write , but possible for read */ +/* CSC register guard (GCSC) */ +#define _00_CGC_CSC_GUARD_OFF (0x00U) /* invalid, it is possible to write CSC register */ +#define _01_CGC_CSC_GUARD_ON (0x01U) /* valid, it is impossible to write CSC register, but possible for read */ + +/* + RTC clock selection register (RTCCL) +*/ +/* Operation clock source selection for RTC (RTCCL7) */ +#define _00_CGC_RTC_FMX (0x00U) /* RTC uses External Main clock (fMX) */ +#define _80_CGC_RTC_FIH (0x80U) /* RTC uses Internal high speed clock (fIH) */ +/* Operation selection of RTC macro (RTCCL6,RTCCKS1 - RTCCKS0) */ +#define _00_CGC_RTC_FSUB (0x00U) /* RTC uses sub clock */ +#define _02_CGC_RTC_DIV128 (0x02U) /* RTC uses high-speed clock / 128 */ +#define _03_CGC_RTC_DIV256 (0x03U) /* RTC uses high-speed clock / 256 */ +#define _42_CGC_RTC_DIV122 (0x42U) /* RTC uses high-speed clock / 122 */ +#define _43_CGC_RTC_DIV244 (0x43U) /* RTC uses high-speed clock / 244 */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef enum +{ + HIOCLK, + SYSX1CLK, + SYSEXTCLK, + SUBXT1CLK, + SUBEXTCLK +} clock_mode_t; + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); +void R_CGC_Get_ResetSource(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_cgc_user.c b/app/r_cg_cgc_user.c new file mode 100644 index 0000000..35492e9 --- /dev/null +++ b/app/r_cg_cgc_user.c @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for CGC module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Get_ResetSource +* Description : This function process of Reset. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Get_ResetSource(void) +{ + uint8_t reset_flag = RESF; + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_macrodriver.h b/app/r_cg_macrodriver.h new file mode 100644 index 0000000..36cdeda --- /dev/null +++ b/app/r_cg_macrodriver.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements general head file. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef STATUS_H +#define STATUS_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "iodefine.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ +#define DI __DI +#define EI __EI +#define HALT __halt +#define NOP __nop +#define STOP __stop +#define BRK __brk + +/* Status list definition */ +#define MD_STATUSBASE 0x00U +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ +#define MD_OVERRUN (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */ + +/* Error list definition */ +#define MD_ERRORBASE 0x80U +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error agrument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_DATAEXISTS (MD_ERRORBASE + 0x06U) /* data to be transferred next exists in TXBn register */ +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef unsigned short MD_STATUS; +#define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif diff --git a/app/r_cg_port.c b/app/r_cg_port.c new file mode 100644 index 0000000..19042ec --- /dev/null +++ b/app/r_cg_port.c @@ -0,0 +1,77 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + P3 = _00_Pn0_OUTPUT_0 | _00_Pn2_OUTPUT_0; + P7 = _00_Pn0_OUTPUT_0 | _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0; + P13 = _00_Pn0_OUTPUT_0; + P14 = _00_Pn0_OUTPUT_0; + PMC12 = _00_PMCn0_DI_ON | _00_PMCn5_DI_ON | _DE_PMC12_DEFAULT; + PSRSEL = _00_PSR140_NORMAL | _00_PSR120_NORMAL | _00_PSR30_NORMAL; + ADPC = _05_ADPC_DI_ON; + PM3 = _00_PMn0_MODE_OUTPUT | _02_PMn1_NOT_USE | _00_PMn2_MODE_OUTPUT | _08_PMn3_NOT_USE | _10_PMn4_NOT_USE | + _E0_PM3_DEFAULT; + PM6 = _01_PMn0_MODE_INPUT | _02_PMn1_MODE_INPUT | _04_PMn2_MODE_INPUT | _08_PMn3_MODE_INPUT | _F0_PM6_DEFAULT; + PM7 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _F0_PM7_DEFAULT; + PM8 = _01_PMn0_NOT_USE | _02_PMn1_NOT_USE | _04_PMn2_MODE_INPUT | _08_PMn3_MODE_INPUT | _10_PMn4_MODE_INPUT | + _20_PMn5_MODE_INPUT | _40_PMn6_MODE_INPUT | _80_PMn7_MODE_INPUT; + PM9 = _01_PMn0_NOT_USE | _02_PMn1_MODE_INPUT | _04_PMn2_MODE_INPUT | _F8_PM9_DEFAULT; + PM12 = _01_PMn0_MODE_INPUT | _20_PMn5_MODE_INPUT | _DE_PM12_DEFAULT; + PM14 = _00_PMn0_MODE_OUTPUT | _FE_PM14_DEFAULT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_port.h b/app/r_cg_port.h new file mode 100644 index 0000000..e4b89df --- /dev/null +++ b/app/r_cg_port.h @@ -0,0 +1,257 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Mode Register (PMm) +*/ +/* Pmn pin I/O mode selection (PMm7 - PMm0) */ +#define _01_PMn0_NOT_USE (0x01U) /* not use Pn0 as digital I/O */ +#define _01_PMn0_MODE_INPUT (0x01U) /* use Pn0 as input mode */ +#define _00_PMn0_MODE_OUTPUT (0x00U) /* use Pn0 as output mode */ +#define _02_PMn1_NOT_USE (0x02U) /* not use Pn1 as digital I/O */ +#define _02_PMn1_MODE_INPUT (0x02U) /* use Pn1 as input mode */ +#define _00_PMn1_MODE_OUTPUT (0x00U) /* use Pn1 as output mode */ +#define _04_PMn2_NOT_USE (0x04U) /* not use Pn2 as digital I/O */ +#define _04_PMn2_MODE_INPUT (0x04U) /* use Pn2 as input mode */ +#define _00_PMn2_MODE_OUTPUT (0x00U) /* use Pn2 as output mode */ +#define _08_PMn3_NOT_USE (0x08U) /* not use Pn3 as digital I/O */ +#define _08_PMn3_MODE_INPUT (0x08U) /* use Pn3 as input mode */ +#define _00_PMn3_MODE_OUTPUT (0x00U) /* use Pn3 as output mode */ +#define _10_PMn4_NOT_USE (0x10U) /* not use Pn4 as digital I/O */ +#define _10_PMn4_MODE_INPUT (0x10U) /* use Pn4 as input mode */ +#define _00_PMn4_MODE_OUTPUT (0x00U) /* use Pn4 as output mode */ +#define _20_PMn5_NOT_USE (0x20U) /* not use Pn5 as digital I/O */ +#define _20_PMn5_MODE_INPUT (0x20U) /* use Pn5 as input mode */ +#define _00_PMn5_MODE_OUTPUT (0x00U) /* use Pn5 as output mode */ +#define _40_PMn6_NOT_USE (0x40U) /* not use Pn6 as digital I/O */ +#define _40_PMn6_MODE_INPUT (0x40U) /* use Pn6 as input mode */ +#define _00_PMn6_MODE_OUTPUT (0x00U) /* use Pn6 as output mode */ +#define _80_PMn7_NOT_USE (0x80U) /* not use Pn7 as digital I/O */ +#define _80_PMn7_MODE_INPUT (0x80U) /* use Pn7 as input mode */ +#define _00_PMn7_MODE_OUTPUT (0x00U) /* use Pn7 as output mode */ + +/* + Port Register (Pm) +*/ +/* Pmn pin data (Pm0 to Pm7) */ +#define _00_Pn0_OUTPUT_0 (0x00U) /* Pn0 output 0 */ +#define _01_Pn0_OUTPUT_1 (0x01U) /* Pn0 output 1 */ +#define _00_Pn1_OUTPUT_0 (0x00U) /* Pn1 output 0 */ +#define _02_Pn1_OUTPUT_1 (0x02U) /* Pn1 output 1 */ +#define _00_Pn2_OUTPUT_0 (0x00U) /* Pn2 output 0 */ +#define _04_Pn2_OUTPUT_1 (0x04U) /* Pn2 output 1 */ +#define _00_Pn3_OUTPUT_0 (0x00U) /* Pn3 output 0 */ +#define _08_Pn3_OUTPUT_1 (0x08U) /* Pn3 output 1 */ +#define _00_Pn4_OUTPUT_0 (0x00U) /* Pn4 output 0 */ +#define _10_Pn4_OUTPUT_1 (0x10U) /* Pn4 output 1 */ +#define _00_Pn5_OUTPUT_0 (0x00U) /* Pn5 output 0 */ +#define _20_Pn5_OUTPUT_1 (0x20U) /* Pn5 output 1 */ +#define _00_Pn6_OUTPUT_0 (0x00U) /* Pn6 output 0 */ +#define _40_Pn6_OUTPUT_1 (0x40U) /* Pn6 output 1 */ +#define _00_Pn7_OUTPUT_0 (0x00U) /* Pn7 output 0 */ +#define _80_Pn7_OUTPUT_1 (0x80U) /* Pn7 output 1 */ + +/* + Pull-up Resistor Option Register (PUm) +*/ +/* Pmn pin on-chip pull-up resistor selection (PUmn) */ +#define _00_PUn0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */ +#define _01_PUn0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */ +#define _00_PUn1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */ +#define _02_PUn1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */ +#define _00_PUn2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */ +#define _04_PUn2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */ +#define _00_PUn3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */ +#define _08_PUn3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */ +#define _00_PUn4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */ +#define _10_PUn4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */ +#define _00_PUn5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */ +#define _20_PUn5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */ +#define _00_PUn6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */ +#define _40_PUn6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */ +#define _00_PUn7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */ +#define _80_PUn7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */ + +/* + Port Input Mode Register (PIMm) +*/ +/* Pmn pin input buffer selection (PIMmn) */ +#define _00_PIMn0_TTL_OFF (0x00U) /* set Pn0 normal input buffer */ +#define _01_PIMn0_TTL_ON (0x01U) /* set Pn0 TTL input buffer */ +#define _00_PIMn1_TTL_OFF (0x00U) /* set Pn1 normal input buffer */ +#define _02_PIMn1_TTL_ON (0x02U) /* set Pn1 TTL input buffer */ +#define _00_PIMn2_TTL_OFF (0x00U) /* set Pn2 normal input buffer */ +#define _04_PIMn2_TTL_ON (0x04U) /* set Pn2 TTL input buffer */ +#define _00_PIMn3_TTL_OFF (0x00U) /* set Pn3 normal input buffer */ +#define _08_PIMn3_TTL_ON (0x08U) /* set Pn3 TTL input buffer */ +#define _00_PIMn4_TTL_OFF (0x00U) /* set Pn4 normal input buffer */ +#define _10_PIMn4_TTL_ON (0x10U) /* set Pn4 TTL input buffer */ +#define _00_PIMn5_TTL_OFF (0x00U) /* set Pn5 normal input buffer */ +#define _20_PIMn5_TTL_ON (0x20U) /* set Pn5 TTL input buffer */ +#define _00_PIMn6_TTL_OFF (0x00U) /* set Pn6 normal input buffer */ +#define _40_PIMn6_TTL_ON (0x40U) /* set Pn6 TTL input buffer */ +#define _00_PIMn7_TTL_OFF (0x00U) /* set Pn7 normal input buffer */ +#define _80_PIMn7_TTL_ON (0x80U) /* set Pn7 TTL input buffer */ + +/* + Port Input Threshold Control Register (PITHLm) +*/ +/* Pmn pin input threshold selection (PITHLmn) */ +#define _00_PITHLn0_SCHMITT3_OFF (0x00U) /* set Pn0 schmitt 1 input (default) */ +#define _01_PITHLn0_SCHMITT3_ON (0x01U) /* set Pn0 schmitt 3 input */ +#define _00_PITHLn1_SCHMITT3_OFF (0x00U) /* set Pn1 schmitt 1 input (default) */ +#define _02_PITHLn1_SCHMITT3_ON (0x02U) /* set Pn1 schmitt 3 input */ +#define _00_PITHLn2_SCHMITT3_OFF (0x00U) /* set Pn2 schmitt 1 input (default) */ +#define _04_PITHLn2_SCHMITT3_ON (0x04U) /* set Pn2 schmitt 3 input */ +#define _00_PITHLn3_SCHMITT3_OFF (0x00U) /* set Pn3 schmitt 1 input (default) */ +#define _08_PITHLn3_SCHMITT3_ON (0x08U) /* set Pn3 schmitt 3 input */ +#define _00_PITHLn4_SCHMITT3_OFF (0x00U) /* set Pn4 schmitt 1 input (default) */ +#define _10_PITHLn4_SCHMITT3_ON (0x10U) /* set Pn4 schmitt 3 input */ +#define _00_PITHLn5_SCHMITT3_OFF (0x00U) /* set Pn5 schmitt 1 input (default) */ +#define _20_PITHLn5_SCHMITT3_ON (0x20U) /* set Pn5 schmitt 3 input */ +#define _00_PITHLn6_SCHMITT3_OFF (0x00U) /* set Pn6 schmitt 1 input (default) */ +#define _40_PITHLn6_SCHMITT3_ON (0x40U) /* set Pn6 schmitt 3 input */ +#define _00_PITHLn7_SCHMITT3_OFF (0x00U) /* set Pn7 schmitt 1 input (default) */ +#define _80_PITHLn7_SCHMITT3_ON (0x80U) /* set Pn7 schmitt 3 input */ + +/* + Port Output Mode Register (POMm) +*/ +/* Pmn pin output mode selection (POMmn) */ +#define _00_POMn0_NCH_OFF (0x00U) /* set Pn0 output normal mode */ +#define _01_POMn0_NCH_ON (0x01U) /* set Pn0 output N-ch open-drain mode */ +#define _00_POMn1_NCH_OFF (0x00U) /* set Pn1 output normal mode */ +#define _02_POMn1_NCH_ON (0x02U) /* set Pn1 output N-ch open-drain mode */ +#define _00_POMn2_NCH_OFF (0x00U) /* set Pn2 output normal mode */ +#define _04_POMn2_NCH_ON (0x04U) /* set Pn2 output N-ch open-drain mode */ +#define _00_POMn3_NCH_OFF (0x00U) /* set Pn3 output normal mode */ +#define _08_POMn3_NCH_ON (0x08U) /* set Pn3 output N-ch open-drain mode */ +#define _00_POMn4_NCH_OFF (0x00U) /* set Pn4 output normal mode */ +#define _10_POMn4_NCH_ON (0x10U) /* set Pn4 output N-ch open-drain mode */ +#define _00_POMn5_NCH_OFF (0x00U) /* set Pn5 output normal mode */ +#define _20_POMn5_NCH_ON (0x20U) /* set Pn5 output N-ch open-drain mode */ +#define _00_POMn6_NCH_OFF (0x00U) /* set Pn6 output normal mode */ +#define _40_POMn6_NCH_ON (0x40U) /* set Pn6 output N-ch open-drain mode */ +#define _00_POMn7_NCH_OFF (0x00U) /* set Pn7 output normal mode */ +#define _80_POMn7_NCH_ON (0x80U) /* set Pn7 output N-ch open-drain mode */ + +/* + Port Operation Mode Register (PMCm) +*/ +/* Pmn pin digital input buffer selection (PMCmn) */ +#define _01_PMCn0_NOT_USE (0x01U) /* not use Pn0 digital input */ +#define _00_PMCn0_DI_ON (0x00U) /* enable Pn0 digital input */ +#define _02_PMCn1_NOT_USE (0x02U) /* not use Pn1 digital input */ +#define _00_PMCn1_DI_ON (0x00U) /* enable Pn1 digital input */ +#define _04_PMCn2_NOT_USE (0x04U) /* not use Pn2 digital input */ +#define _00_PMCn2_DI_ON (0x00U) /* enable Pn2 digital input */ +#define _08_PMCn3_NOT_USE (0x08U) /* not use Pn3 digital input */ +#define _00_PMCn3_DI_ON (0x00U) /* enable Pn3 digital input */ +#define _10_PMCn4_NOT_USE (0x10U) /* not use Pn4 digital input */ +#define _00_PMCn4_DI_ON (0x00U) /* enable Pn4 digital input */ +#define _20_PMCn5_NOT_USE (0x20U) /* not use Pn5 digital input */ +#define _00_PMCn5_DI_ON (0x00U) /* enable Pn5 digital input */ +#define _40_PMCn6_NOT_USE (0x40U) /* not use Pn6 digital input */ +#define _00_PMCn6_DI_ON (0x00U) /* enable Pn6 digital input */ +#define _80_PMCn7_NOT_USE (0x80U) /* not use Pn7 digital input */ +#define _00_PMCn7_DI_ON (0x00U) /* enable Pn7 digital input */ + +/* + Port output slew rate select register (PSRSEL) +*/ +/* P140/PCLBUZ0 pin output mode selection (PSR140) */ +#define _00_PSR140_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _20_PSR140_SLOW (0x20U) /* slow mode (25 V/5 ns (target) (TYP.)) */ +/* P14/SCK01/SCL01/TO06/TRDIOC0 pin output mode selection (PSR14) */ +#define _00_PSR14_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _10_PSR14_SLOW (0x10U) /* slow mode (25 V/5 ns (target) (TYP.)) */ +/* P120/SO01/TO07/TRDIOD0 pin output mode selection (PSR120) */ +#define _00_PSR120_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _08_PSR120_SLOW (0x08U) /* slow mode (25 V/5 ns (target) (TYP.)) */ +/* P30/TO01/TRDIOD1/SNZOUT0 pin output mode selection (PSR30) */ +#define _00_PSR30_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _04_PSR30_SLOW (0x04U) /* slow mode (25 V/5 ns (target) (TYP.)) */ +/* P12/SO10/TO11/(TRDIOD0)/TXD1/SNZOUT3 pin output mode selection (PSR12) */ +#define _00_PSR12_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _02_PSR12_SLOW (0x02U) /* slow mode (25 V/5 ns (target) (TYP.)) */ +/* P10/SCK10/TO13/TRJO0/SCL10/LTXD1/CTXD0 pin output mode selection (PSR10) */ +#define _00_PSR10_NORMAL (0x00U) /* normal mode (5 V/5 ns) */ +#define _01_PSR10_SLOW (0x01U) /* slow mode (25 V/5 ns (target) (TYP.)) */ + + +/* + AD port configuration register (ADPC) +*/ +/* Analog input/digital input switching (ADPC4 - ADPC0) */ +#define _00_ADPC_DI_OFF (0x00U) /* use P33, P34, P80 - P87, P90 - P92 as analog input */ +#define _0D_ADPC_DI_ON (0x0DU) /* use P92 as digital input */ +#define _0C_ADPC_DI_ON (0x0CU) /* use P91 - P92 as digital input */ +#define _0B_ADPC_DI_ON (0x0BU) /* use P90 - P92 as digital input */ +#define _0A_ADPC_DI_ON (0x0AU) /* use P87, P90 - P92 as digital input */ +#define _09_ADPC_DI_ON (0x09U) /* use P86 - P87, P90 - P92 as digital input */ +#define _08_ADPC_DI_ON (0x08U) /* use P85 - P87, P90 - P92 as digital input */ +#define _07_ADPC_DI_ON (0x07U) /* use P84 - P87, P90 - P92 as digital input */ +#define _06_ADPC_DI_ON (0x06U) /* use P83 - P87, P90 - P92 as digital input */ +#define _05_ADPC_DI_ON (0x05U) /* use P82 - P87, P90 - P92 as digital input */ +#define _04_ADPC_DI_ON (0x04U) /* use P81 - P87, P90 - P92 as digital input */ +#define _03_ADPC_DI_ON (0x03U) /* use P80 - P87, P90 - P92 as digital input */ +#define _02_ADPC_DI_ON (0x02U) /* use P34, P80 - P87, P90 - P92 as digital input */ +#define _01_ADPC_DI_ON (0x01U) /* use P33, P34, P80 - P87, P90 - P92 as digital input */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _FE_PM0_DEFAULT (0xFEU) /* PM0 default value */ +#define _E0_PM3_DEFAULT (0xE0U) /* PM3 default value */ +#define _FC_PM4_DEFAULT (0xFCU) /* PM4 default value */ +#define _F0_PM6_DEFAULT (0xF0U) /* PM6 default value */ +#define _F0_PM7_DEFAULT (0xF0U) /* PM7 default value */ +#define _F8_PM9_DEFAULT (0xF8U) /* PM9 default value */ +#define _DE_PM12_DEFAULT (0xDEU) /* PM12 default value */ +#define _FE_PM14_DEFAULT (0xFEU) /* PM14 default value */ +#define _DE_PMC12_DEFAULT (0xDEU) /* PMC12 default value */ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_port_user.c b/app/r_cg_port_user.c new file mode 100644 index 0000000..9bf7daf --- /dev/null +++ b/app/r_cg_port_user.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for PORT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_timer.c b/app/r_cg_timer.c new file mode 100644 index 0000000..4afd6f5 --- /dev/null +++ b/app/r_cg_timer.c @@ -0,0 +1,217 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Create +* Description : This function initializes the TAU0 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Create(void) +{ + TAU0EN = 1U; /* supplies input clock */ + TPS0 = _0000_TAU_CKM0_FCLK_0 | _0000_TAU_CKM1_FCLK_0 | _0000_TAU_CKM2_FCLK_0 | _0000_TAU_CKM3_FCLK_0; + /* Stop all channels */ + TT0 = _0001_TAU_CH0_STOP_TRG_ON | _0002_TAU_CH1_STOP_TRG_ON | _0004_TAU_CH2_STOP_TRG_ON | + _0008_TAU_CH3_STOP_TRG_ON | _0010_TAU_CH4_STOP_TRG_ON | _0020_TAU_CH5_STOP_TRG_ON | + _0040_TAU_CH6_STOP_TRG_ON | _0080_TAU_CH7_STOP_TRG_ON | _0200_TAU_CH1_H8_STOP_TRG_ON | + _0800_TAU_CH3_H8_STOP_TRG_ON; + PWMDLY1 = _0000_TAU_PWM_DELAY_CLEAR; /* clear PWM output delay */ + /* Mask channel 0 interrupt */ + TMMK00 = 1U; /* disable INTTM00 interrupt */ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ + /* Mask channel 1 interrupt */ + TMMK01 = 1U; /* disable INTTM01 interrupt */ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ + /* Mask channel 1 higher 8 bits interrupt */ + TMMK01H = 1U; /* disable INTTM01H interrupt */ + TMIF01H = 0U; /* clear INTTM01H interrupt flag */ + /* Mask channel 2 interrupt */ + TMMK02 = 1U; /* disable INTTM02 interrupt */ + TMIF02 = 0U; /* clear INTTM02 interrupt flag */ + /* Mask channel 3 interrupt */ + TMMK03 = 1U; /* disable INTTM03 interrupt */ + TMIF03 = 0U; /* clear INTTM03 interrupt flag */ + /* Mask channel 3 higher 8 bits interrupt */ + TMMK03H = 1U; /* disable INTTM03H interrupt */ + TMIF03H = 0U; /* clear INTTM03H interrupt flag */ + /* Mask channel 4 interrupt */ + TMMK04 = 1U; /* disable INTTM04 interrupt */ + TMIF04 = 0U; /* clear INTTM04 interrupt flag */ + /* Mask channel 5 interrupt */ + TMMK05 = 1U; /* disable INTTM05 interrupt */ + TMIF05 = 0U; /* clear INTTM05 interrupt flag */ + /* Mask channel 6 interrupt */ + TMMK06 = 1U; /* disable INTTM06 interrupt */ + TMIF06 = 0U; /* clear INTTM06 interrupt flag */ + /* Mask channel 7 interrupt */ + TMMK07 = 1U; /* disable INTTM07 interrupt */ + TMIF07 = 0U; /* clear INTTM07 interrupt flag */ + /* Set INTTM00 low priority */ + TMPR100 = 1U; + TMPR000 = 1U; + /* Set INTTM01 low priority */ + TMPR101 = 1U; + TMPR001 = 1U; + /* Channel 0 used as interval timer */ + TMR00 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_COMBINATION_SLAVE | + _0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED; + TDR00 = _7CFF_TAU_TDR00_VALUE; + TO0 &= ~_0001_TAU_CH0_OUTPUT_VALUE_1; + TOE0 &= ~_0001_TAU_CH0_OUTPUT_ENABLE; + /* Channel 1 used as interval timer */ + TMR01 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_16BITS_MODE | + _0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED; + TDR01 = _7CFF_TAU_TDR01_VALUE; + TOM0 &= ~_0002_TAU_CH1_OUTPUT_COMBIN; + TOL0 &= ~_0002_TAU_CH1_OUTPUT_LEVEL_L; + TO0 &= ~_0002_TAU_CH1_OUTPUT_VALUE_1; + TOE0 &= ~_0002_TAU_CH1_OUTPUT_ENABLE; + /* Channel 4 is used as master channel for PWM output function */ + TMR04 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0800_TAU_COMBINATION_MASTER | + _0000_TAU_TRIGGER_SOFTWARE | _0001_TAU_MODE_PWM_MASTER; + TDR04 = _7CFF_TAU_TDR04_VALUE; + TOM0 &= ~_0010_TAU_CH4_OUTPUT_COMBIN; + TOL0 &= ~_0010_TAU_CH4_OUTPUT_LEVEL_L; + TO0 &= ~_0010_TAU_CH4_OUTPUT_VALUE_1; + TOE0 &= ~_0010_TAU_CH4_OUTPUT_ENABLE; + /* Channel 5 is used as slave channel for PWM output function */ + TMR05 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_COMBINATION_SLAVE | + _0400_TAU_TRIGGER_MASTER_INT | _0009_TAU_MODE_PWM_SLAVE; + TDR05 = _3E80_TAU_TDR05_VALUE; + TOM0 |= _0020_TAU_CH5_OUTPUT_COMBIN; + TOL0 &= ~_0020_TAU_CH5_OUTPUT_LEVEL_L; + TO0 &= ~_0020_TAU_CH5_OUTPUT_VALUE_1; + PWMDLY1 |= _0000_TO05_OUTPUT_DELAY_0; + TOE0 |= _0020_TAU_CH5_OUTPUT_ENABLE; + /* Set TO05 pin */ + P0 &= 0xFEU; + PM0 &= 0xFEU; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel0_Start +* Description : This function starts TAU0 channel 0 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel0_Start(void) +{ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ + TMMK00 = 0U; /* enable INTTM00 interrupt */ + TS0 |= _0001_TAU_CH0_START_TRG_ON; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel0_Stop +* Description : This function stops TAU0 channel 0 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel0_Stop(void) +{ + TT0 |= _0001_TAU_CH0_STOP_TRG_ON; + /* Mask channel 0 interrupt */ + TMMK00 = 1U; /* disable INTTM00 interrupt */ + TMIF00 = 0U; /* clear INTTM00 interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel1_Start +* Description : This function starts TAU0 channel 1 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel1_Start(void) +{ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ + TMMK01 = 0U; /* enable INTTM01 interrupt */ + TS0 |= _0002_TAU_CH1_START_TRG_ON; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel1_Stop +* Description : This function stops TAU0 channel 1 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel1_Stop(void) +{ + TT0 |= _0002_TAU_CH1_STOP_TRG_ON; + /* Mask channel 1 interrupt */ + TMMK01 = 1U; /* disable INTTM01 interrupt */ + TMIF01 = 0U; /* clear INTTM01 interrupt flag */ +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel4_Start +* Description : This function starts TAU0 channel 4 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel4_Start(void) +{ + TOE0 |= _0020_TAU_CH5_OUTPUT_ENABLE; + TS0 |= _0010_TAU_CH4_START_TRG_ON | _0020_TAU_CH5_START_TRG_ON; +} + +/*********************************************************************************************************************** +* Function Name: R_TAU0_Channel4_Stop +* Description : This function stops TAU0 channel 4 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TAU0_Channel4_Stop(void) +{ + TT0 |= _0010_TAU_CH4_STOP_TRG_ON | _0020_TAU_CH5_STOP_TRG_ON; + TOE0 &= ~_0020_TAU_CH5_OUTPUT_ENABLE; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_timer.h b/app/r_cg_timer.h new file mode 100644 index 0000000..84fdfba --- /dev/null +++ b/app/r_cg_timer.h @@ -0,0 +1,1051 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef TAU_H +#define TAU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Peripheral Enable Register 0 (PER0) +*/ +/* Control of timer array unit 0 input clock (TAU0EN) */ +#define _00_TAU0_CLOCK_STOP (0x00U) /* stops supply of input clock */ +#define _01_TAU0_CLOCK_SUPPLY (0x01U) /* supplies input clock */ +/* Control of timer array unit 1 input clock (TAU1EN) */ +#define _00_TAU1_CLOCK_STOP (0x00U) /* stops supply of input clock */ +#define _02_TAU1_CLOCK_SUPPLY (0x02U) /* supplies input clock */ + +/* + Timer Clock Select Register m (TPSm) +*/ +/* Operating mode and clear mode selection (PRSm03 - PRSm00) */ +#define _0000_TAU_CKM0_FCLK_0 (0x0000U) /* ckm0 - fCLK */ +#define _0001_TAU_CKM0_FCLK_1 (0x0001U) /* ckm0 - fCLK/2^1 */ +#define _0002_TAU_CKM0_FCLK_2 (0x0002U) /* ckm0 - fCLK/2^2 */ +#define _0003_TAU_CKM0_FCLK_3 (0x0003U) /* ckm0 - fCLK/2^3 */ +#define _0004_TAU_CKM0_FCLK_4 (0x0004U) /* ckm0 - fCLK/2^4 */ +#define _0005_TAU_CKM0_FCLK_5 (0x0005U) /* ckm0 - fCLK/2^5 */ +#define _0006_TAU_CKM0_FCLK_6 (0x0006U) /* ckm0 - fCLK/2^6 */ +#define _0007_TAU_CKM0_FCLK_7 (0x0007U) /* ckm0 - fCLK/2^7 */ +#define _0008_TAU_CKM0_FCLK_8 (0x0008U) /* ckm0 - fCLK/2^8 */ +#define _0009_TAU_CKM0_FCLK_9 (0x0009U) /* ckm0 - fCLK/2^9 */ +#define _000A_TAU_CKM0_FCLK_10 (0x000AU) /* ckm0 - fCLK/2^10 */ +#define _000B_TAU_CKM0_FCLK_11 (0x000BU) /* ckm0 - fCLK/2^11 */ +#define _000C_TAU_CKM0_FCLK_12 (0x000CU) /* ckm0 - fCLK/2^12 */ +#define _000D_TAU_CKM0_FCLK_13 (0x000DU) /* ckm0 - fCLK/2^13 */ +#define _000E_TAU_CKM0_FCLK_14 (0x000EU) /* ckm0 - fCLK/2^14 */ +#define _000F_TAU_CKM0_FCLK_15 (0x000FU) /* ckm0 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm13 - PRSm10) */ +#define _0000_TAU_CKM1_FCLK_0 (0x0000U) /* ckm1 - fCLK */ +#define _0010_TAU_CKM1_FCLK_1 (0x0010U) /* ckm1 - fCLK/2^1 */ +#define _0020_TAU_CKM1_FCLK_2 (0x0020U) /* ckm1 - fCLK/2^2 */ +#define _0030_TAU_CKM1_FCLK_3 (0x0030U) /* ckm1 - fCLK/2^3 */ +#define _0040_TAU_CKM1_FCLK_4 (0x0040U) /* ckm1 - fCLK/2^4 */ +#define _0050_TAU_CKM1_FCLK_5 (0x0050U) /* ckm1 - fCLK/2^5 */ +#define _0060_TAU_CKM1_FCLK_6 (0x0060U) /* ckm1 - fCLK/2^6 */ +#define _0070_TAU_CKM1_FCLK_7 (0x0070U) /* ckm1 - fCLK/2^7 */ +#define _0080_TAU_CKM1_FCLK_8 (0x0080U) /* ckm1 - fCLK/2^8 */ +#define _0090_TAU_CKM1_FCLK_9 (0x0090U) /* ckm1 - fCLK/2^9 */ +#define _00A0_TAU_CKM1_FCLK_10 (0x00A0U) /* ckm1 - fCLK/2^10 */ +#define _00B0_TAU_CKM1_FCLK_11 (0x00B0U) /* ckm1 - fCLK/2^11 */ +#define _00C0_TAU_CKM1_FCLK_12 (0x00C0U) /* ckm1 - fCLK/2^12 */ +#define _00D0_TAU_CKM1_FCLK_13 (0x00D0U) /* ckm1 - fCLK/2^13 */ +#define _00E0_TAU_CKM1_FCLK_14 (0x00E0U) /* ckm1 - fCLK/2^14 */ +#define _00F0_TAU_CKM1_FCLK_15 (0x00F0U) /* ckm1 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm21 - PRSm20) */ +#define _0000_TAU_CKM2_FCLK_0 (0x0000U) /* CKM2 - fCLK */ +#define _0100_TAU_CKM2_FCLK_1 (0x0100U) /* CKM2 - fCLK/2^1 */ +#define _0200_TAU_CKM2_FCLK_2 (0x0200U) /* CKM2 - fCLK/2^2 */ +#define _0300_TAU_CKM2_FCLK_3 (0x0300U) /* CKM2 - fCLK/2^3 */ +#define _0400_TAU_CKM2_FCLK_4 (0x0400U) /* CKM2 - fCLK/2^4 */ +#define _0500_TAU_CKM2_FCLK_5 (0x0500U) /* CKM2 - fCLK/2^5 */ +#define _0600_TAU_CKM2_FCLK_6 (0x0600U) /* CKM2 - fCLK/2^6 */ +#define _0700_TAU_CKM2_FCLK_7 (0x0700U) /* CKM2 - fCLK/2^7 */ +#define _0800_TAU_CKM2_FCLK_8 (0x0800U) /* CKM2 - fCLK/2^8 */ +#define _0900_TAU_CKM2_FCLK_9 (0x0900U) /* CKM2 - fCLK/2^9 */ +#define _0A00_TAU_CKM2_FCLK_10 (0x0A00U) /* CKM2 - fCLK/2^10 */ +#define _0B00_TAU_CKM2_FCLK_11 (0x0B00U) /* CKM2 - fCLK/2^11 */ +#define _0C00_TAU_CKM2_FCLK_12 (0x0C00U) /* CKM2 - fCLK/2^12 */ +#define _0D00_TAU_CKM2_FCLK_13 (0x0D00U) /* CKM2 - fCLK/2^13 */ +#define _0E00_TAU_CKM2_FCLK_14 (0x0E00U) /* CKM2 - fCLK/2^14 */ +#define _0F00_TAU_CKM2_FCLK_15 (0x0F00U) /* CKM2 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm31 - PRSm30) */ +#define _0000_TAU_CKM3_FCLK_0 (0x0000U) /* CKM3 - fCLK */ +#define _1000_TAU_CKM3_FCLK_1 (0x1000U) /* CKM3 - fCLK/2^1 */ +#define _2000_TAU_CKM3_FCLK_2 (0x2000U) /* CKM3 - fCLK/2^2 */ +#define _3000_TAU_CKM3_FCLK_3 (0x3000U) /* CKM3 - fCLK/2^3 */ +#define _4000_TAU_CKM3_FCLK_4 (0x4000U) /* CKM3 - fCLK/2^4 */ +#define _5000_TAU_CKM3_FCLK_5 (0x5000U) /* CKM3 - fCLK/2^5 */ +#define _6000_TAU_CKM3_FCLK_6 (0x6000U) /* CKM3 - fCLK/2^6 */ +#define _7000_TAU_CKM3_FCLK_7 (0x7000U) /* CKM3 - fCLK/2^7 */ +#define _8000_TAU_CKM3_FCLK_8 (0x8000U) /* CKM3 - fCLK/2^8 */ +#define _9000_TAU_CKM3_FCLK_9 (0x9000U) /* CKM3 - fCLK/2^9 */ +#define _A000_TAU_CKM3_FCLK_10 (0xA000U) /* CKM3 - fCLK/2^10 */ +#define _B000_TAU_CKM3_FCLK_11 (0xB000U) /* CKM3 - fCLK/2^11 */ +#define _C000_TAU_CKM3_FCLK_12 (0xC000U) /* CKM3 - fCLK/2^12 */ +#define _D000_TAU_CKM3_FCLK_13 (0xD000U) /* CKM3 - fCLK/2^13 */ +#define _E000_TAU_CKM3_FCLK_14 (0xE000U) /* CKM3 - fCLK/2^14 */ +#define _F000_TAU_CKM3_FCLK_15 (0xF000U) /* CKM3 - fCLK/2^15 */ +/* Operating mode and clear mode selection (PRSm21 - PRSm20) */ +#define _0000_TAU_CKM2_FCLK_1 (0x0000U) /* ckm2 - fCLK/2^1 */ +#define _0100_TAU_CKM2_FCLK_2 (0x0100U) /* ckm2 - fCLK/2^2 */ +#define _0200_TAU_CKM2_FCLK_4 (0x0200U) /* ckm2 - fCLK/2^4 */ +#define _0300_TAU_CKM2_FCLK_6 (0x0300U) /* ckm2 - fCLK/2^6 */ +/* Operating mode and clear mode selection (PRSm31 - PRSm30) */ +#define _0000_TAU_CKM3_FCLK_8 (0x0000U) /* ckm2 - fCLK/2^8 */ +#define _1000_TAU_CKM3_FCLK_10 (0x1000U) /* ckm2 - fCLK/2^10 */ +#define _2000_TAU_CKM3_FCLK_12 (0x2000U) /* ckm2 - fCLK/2^12 */ +#define _3000_TAU_CKM3_FCLK_14 (0x3000U) /* ckm2 - fCLK/2^14 */ + +/* + Timer Mode Register mn (TMRmn) +*/ +/* Selection of macro clock (MCK) of channel n (CKSmn1 - CKSmn0) */ +#define _0000_TAU_CLOCK_SELECT_CKM0 (0x0000U) /* operation clock CK0 set by PRS register */ +#define _8000_TAU_CLOCK_SELECT_CKM1 (0x8000U) /* operation clock CK1 set by PRS register */ +#define _4000_TAU_CLOCK_SELECT_CKM2 (0x4000U) /* operation clock CK2 set by PRS register */ +#define _C000_TAU_CLOCK_SELECT_CKM3 (0xC000U) /* operation clock CK3 set by PRS register */ +/* Selection of count clock (CCK) of channel n (CCSmn) */ +#define _0000_TAU_CLOCK_MODE_CKS (0x0000U) /* macro clock MCK specified by CKSmn bit */ +#define _1000_TAU_CLOCK_MODE_TIMN (0x1000U) /* valid edge of input signal input from TImn pin */ +/* Selection of slave/master of channel n (MASTERmn) */ +#define _0000_TAU_COMBINATION_SLAVE (0x0000U) /* operates as slave channel */ +#define _0800_TAU_COMBINATION_MASTER (0x0800U) /* operates as master channel */ +/* Operation explanation of channel 1 or 3 (SPLIT) */ +#define _0000_TAU_16BITS_MODE (0x0000U) /* operates as 16 bits timer */ +#define _0800_TAU_8BITS_MODE (0x0800U) /* operates as 8 bits timer */ +/* Setting of start trigger or capture trigger of channel n (STSmn2 - STSmn0) */ +#define _0000_TAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger start is valid */ +#define _0100_TAU_TRIGGER_TIMN_VALID (0x0100U) /* TImn input edge is used as a start/capture trigger */ +#define _0200_TAU_TRIGGER_TIMN_BOTH (0x0200U) /* TImn input edges are used as a start/capture trigger */ +#define _0400_TAU_TRIGGER_MASTER_INT (0x0400U) /* interrupt signal of the master channel is used */ +/* Selection of TImn pin input valid edge (CISmn1 - CISmn0) */ +#define _0000_TAU_TIMN_EDGE_FALLING (0x0000U) /* falling edge */ +#define _0040_TAU_TIMN_EDGE_RISING (0x0040U) /* rising edge */ +#define _0080_TAU_TIMN_EDGE_BOTH_LOW (0x0080U) /* both edges (when low-level width is measured) */ +#define _00C0_TAU_TIMN_EDGE_BOTH_HIGH (0x00C0U) /* both edges (when high-level width is measured) */ +/* Operation mode of channel n (MDmn3 - MDmn0) */ +#define _0000_TAU_MODE_INTERVAL_TIMER (0x0000U) /* interval timer mode */ +#define _0004_TAU_MODE_CAPTURE (0x0004U) /* capture mode */ +#define _0006_TAU_MODE_EVENT_COUNT (0x0006U) /* event counter mode */ +#define _0008_TAU_MODE_ONE_COUNT (0x0008U) /* one count mode */ +#define _000C_TAU_MODE_HIGHLOW_MEASURE (0x000CU) /* high-/low-level width measurement mode */ +#define _0001_TAU_MODE_PWM_MASTER (0x0001U) /* PWM Function (Master Channel) mode */ +#define _0009_TAU_MODE_PWM_SLAVE (0x0009U) /* PWM Function (Slave Channel) mode */ +#define _0008_TAU_MODE_ONESHOT (0x0008U) /* one-shot pulse output mode */ +/* Setting of starting counting and interrupt (MDmn0) */ +#define _0000_TAU_START_INT_UNUSED (0x0000U) /* interrupt is not generated when counting is started */ +#define _0001_TAU_START_INT_USED (0x0001U) /* interrupt is generated when counting is started */ + +/* + Timer Status Register mn (TSRmn) +*/ +/* Counter overflow status of channel n (OVF) */ +#define _0000_TAU_OVERFLOW_NOT_OCCURS (0x0000U) /* overflow does not occur */ +#define _0001_TAU_OVERFLOW_OCCURS (0x0001U) /* overflow occurs */ + +/* + Timer Channel Enable Status Register m (TEm) +*/ +/* Indication of operation enable/stop status of channel 0 (TEm0) */ +#define _0000_TAU_CH0_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0001_TAU_CH0_OPERATION_ENABLE (0x0001U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 1 (TEm1) */ +#define _0000_TAU_CH1_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0002_TAU_CH1_OPERATION_ENABLE (0x0002U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 2 (TEm2) */ +#define _0000_TAU_CH2_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0004_TAU_CH2_OPERATION_ENABLE (0x0004U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 3 (TEm3) */ +#define _0000_TAU_CH3_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0008_TAU_CH3_OPERATION_ENABLE (0x0008U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 4 (TEm4) */ +#define _0000_TAU_CH4_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0010_TAU_CH4_OPERATION_ENABLE (0x0010U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 5 (TEm5) */ +#define _0000_TAU_CH5_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0020_TAU_CH5_OPERATION_ENABLE (0x0020U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 6 (TEm6) */ +#define _0000_TAU_CH6_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0040_TAU_CH6_OPERATION_ENABLE (0x0040U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 7 (TEm7) */ +#define _0000_TAU_CH7_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0080_TAU_CH7_OPERATION_ENABLE (0x0080U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEHm1) */ +#define _0000_TAU_CH1_H8_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0200_TAU_CH1_H8_OPERATION_ENABLE (0x0200U) /* operation is enabled */ +/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEHm3) */ +#define _0000_TAU_CH3_H8_OPERATION_STOP (0x0000U) /* operation is stopped */ +#define _0800_TAU_CH3_H8_OPERATION_ENABLE (0x0800U) /* operation is enabled */ + +/* + Timer Channel Start Register m (TSm) +*/ +/* Operation enable (start) trigger of channel 0 (TSm0) */ +#define _0000_TAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_TAU_CH0_START_TRG_ON (0x0001U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 1 (TSm1) */ +#define _0000_TAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_TAU_CH1_START_TRG_ON (0x0002U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 2 (TSm2) */ +#define _0000_TAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_TAU_CH2_START_TRG_ON (0x0004U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 3 (TSm3) */ +#define _0000_TAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_TAU_CH3_START_TRG_ON (0x0008U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 4 (TSm4) */ +#define _0000_TAU_CH4_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0010_TAU_CH4_START_TRG_ON (0x0010U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 5 (TSm5) */ +#define _0000_TAU_CH5_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0020_TAU_CH5_START_TRG_ON (0x0020U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 6 (TSm6) */ +#define _0000_TAU_CH6_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0040_TAU_CH6_START_TRG_ON (0x0040U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 7 (TSm7) */ +#define _0000_TAU_CH7_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0080_TAU_CH7_START_TRG_ON (0x0080U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 1 higher 8 bits (TSHm1) */ +#define _0000_TAU_CH1_H8_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0200_TAU_CH1_H8_START_TRG_ON (0x0200U) /* operation is enabled (start trigger is generated) */ +/* Operation enable (start) trigger of channel 3 higher 8 bits (TSHm3) */ +#define _0000_TAU_CH3_H8_START_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0800_TAU_CH3_H8_START_TRG_ON (0x0800U) /* operation is enabled (start trigger is generated) */ + +/* + Timer Channel Stop Register m (TTm) +*/ +/* Operation stop trigger of channel 0 (TTm0) */ +#define _0000_TAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0001_TAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 1 (TTm1) */ +#define _0000_TAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0002_TAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 2 (TTm2) */ +#define _0000_TAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0004_TAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 3 (TTm3) */ +#define _0000_TAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0008_TAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 4 (TTm4) */ +#define _0000_TAU_CH4_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0010_TAU_CH4_STOP_TRG_ON (0x0010U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 5 (TTm5) */ +#define _0000_TAU_CH5_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0020_TAU_CH5_STOP_TRG_ON (0x0020U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 6 (TTm6) */ +#define _0000_TAU_CH6_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0040_TAU_CH6_STOP_TRG_ON (0x0040U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 7 (TTm7) */ +#define _0000_TAU_CH7_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0080_TAU_CH7_STOP_TRG_ON (0x0080U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 1 higher 8 bits (TTHm1) */ +#define _0000_TAU_CH1_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0200_TAU_CH1_H8_STOP_TRG_ON (0x0200U) /* operation is stopped (stop trigger is generated) */ +/* Operation stop trigger of channel 3 higher 8 bits (TTHm3) */ +#define _0000_TAU_CH3_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */ +#define _0800_TAU_CH3_H8_STOP_TRG_ON (0x0800U) /* operation is stopped (stop trigger is generated) */ + +/* + Timer Input Select Register m (TIS0) +*/ +/* Selection of timer input used with TAU0 channel 1 (TIS02 - TIS00) */ +#define _00_TAU_CH1_INPUT_TI01 (0x00U) /* input signal of timer input pin (TI01) */ +#define _01_TAU_CH1_INPUT_ELC (0x01U) /* input signal of timer input pin (ELC) */ +#define _02_TAU_CH1_INPUT_TI01 (0x02U) /* input signal of timer input pin (TI01) */ +#define _03_TAU_CH1_INPUT_TI01 (0x03U) /* input signal of timer input pin (TI01) */ +#define _04_TAU_CH1_INPUT_FIL (0x04U) /* internal low speed oscillation clock (fIL) */ +#define _05_TAU_CH1_INPUT_FSL (0x05U) /* low speed on-chip oscillator clock (fSL) */ +/* Selection of timer input used with TAU0 channel 0 (TIS04) */ +#define _00_TAU_CH0_INPUT_TI00 (0x00U) /* input signal of timer input pin (TI00) */ +#define _10_TAU_CH0_INPUT_ELC (0x10U) /* event input signal from ELC */ +/* Selection of timer input used with TAU0 channel 2 (TIS06) */ +#define _00_TAU_CH2_INPUT_TI02 (0x00U) /* input signal of timer input pin (TI02) */ +#define _40_TAU_CH2_INPUT_ELC (0x40U) /* event input signal from ELC */ +/* Selection of timer input used with TAU0 channel 3 (TIS07) */ +#define _00_TAU_CH3_INPUT_TI03 (0x00U) /* input signal of timer input pin (TI03) */ +#define _80_TAU_CH3_INPUT_ELC (0x80U) /* event input signal from ELC */ + +/* + Timer Input Select Register m (TIS1) +*/ +/* Selection of timer input used with TAU0 channel 4 (TIS10) */ +#define _00_TAU_CH4_INPUT_TI04 (0x00U) /* input signal of timer input pin (TI04) */ +#define _01_TAU_CH4_INPUT_TI03 (0x01U) /* input signal of timer input pin (TI03) */ +/* Selection of timer input used with TAU0 channel 5 (TIS12) */ +#define _00_TAU_CH5_INPUT_TI05 (0x00U) /* input signal of timer input pin (TI05) */ +#define _04_TAU_CH5_INPUT_TI03 (0x04U) /* input signal of timer input pin (TI03) */ +/* Selection of timer input used with TAU0 channel 6 (TIS14) */ +#define _00_TAU_CH6_INPUT_TI06 (0x00U) /* input signal of timer input pin (TI06) */ +#define _10_TAU_CH6_INPUT_RTC1HZ (0x10U) /* RTC1HZ output signal */ +/* Selection of timer input used with TAU0 channel 7 (TIS17 - TIS16) */ +#define _00_TAU_CH7_INPUT_TI07 (0x00U) /* input signal of timer input pin (TI07) */ +#define _40_TAU_CH7_INPUT_RTC1HZ (0x40U) /* RTC1HZ output signal */ +#define _80_TAU_CH7_INPUT_RXD0 (0x80U) /* input signal of RXD0 pin */ + +/* + Timer Input Select Register m (TIS2) +*/ +/* Selection of timer input used with TAU1 channel 6 (TIS22) */ +#define _00_TAU_CH6_INPUT_TI16 (0x00U) /* input signal of timer input pin (TI16) */ +#define _04_TAU_CH6_INPUT_RTC1HZ (0x04U) /* RTC1HZ output signal */ +/* Selection of timer input used with TAU1 channel 7 (TIS23) */ +#define _00_TAU_CH7_INPUT_TI17 (0x00U) /* input signal of timer input pin (TI17) */ +#define _08_TAU_CH7_INPUT_RTC1HZ (0x08U) /* RTC1HZ output signal */ + +/* + Timer Output Enable Register m (TOEm) +*/ +/* Timer output enable/disable of channel 0 (TOEm0) */ +#define _0001_TAU_CH0_OUTPUT_ENABLE (0x0001U) /* the TOm0 operation enabled by count operation */ +#define _0000_TAU_CH0_OUTPUT_DISABLE (0x0000U) /* the TOm0 operation stopped by count operation */ +/* Timer output enable/disable of channel 1 (TOEm1) */ +#define _0002_TAU_CH1_OUTPUT_ENABLE (0x0002U) /* the TOm1 operation enabled by count operation */ +#define _0000_TAU_CH1_OUTPUT_DISABLE (0x0000U) /* the TOm1 operation stopped by count operation */ +/* Timer output enable/disable of channel 2 (TOEm2) */ +#define _0004_TAU_CH2_OUTPUT_ENABLE (0x0004U) /* the TOm2 operation enabled by count operation */ +#define _0000_TAU_CH2_OUTPUT_DISABLE (0x0000U) /* the TOm2 operation stopped by count operation */ +/* Timer output enable/disable of channel 3 (TOEm3) */ +#define _0008_TAU_CH3_OUTPUT_ENABLE (0x0008U) /* the TOm3 operation enabled by count operation */ +#define _0000_TAU_CH3_OUTPUT_DISABLE (0x0000U) /* the TOm3 operation stopped by count operation */ +/* Timer output enable/disable of channel 4 (TOEm4) */ +#define _0010_TAU_CH4_OUTPUT_ENABLE (0x0010U) /* the TOm4 operation enabled by count operation */ +#define _0000_TAU_CH4_OUTPUT_DISABLE (0x0000U) /* the TOm4 operation stopped by count operation */ +/* Timer output enable/disable of channel 5 (TOEm5) */ +#define _0020_TAU_CH5_OUTPUT_ENABLE (0x0020U) /* the TOm5 operation enabled by count operation */ +#define _0000_TAU_CH5_OUTPUT_DISABLE (0x0000U) /* the TOm5 operation stopped by count operation */ +/* Timer output enable/disable of channel 6 (TOEm6) */ +#define _0040_TAU_CH6_OUTPUT_ENABLE (0x0040U) /* the TOm6 operation enabled by count operation */ +#define _0000_TAU_CH6_OUTPUT_DISABLE (0x0000U) /* the TOm6 operation stopped by count operation */ +/* Timer output enable/disable of channel 7 (TOEm7) */ +#define _0080_TAU_CH7_OUTPUT_ENABLE (0x0080U) /* the TOm7 operation enabled by count operation */ +#define _0000_TAU_CH7_OUTPUT_DISABLE (0x0000U) /* the TOm7 operation stopped by count operation */ + +/* + Timer Output Register m (TOm) +*/ +/* Timer output of channel 0 (TOm0) */ +#define _0000_TAU_CH0_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0001_TAU_CH0_OUTPUT_VALUE_1 (0x0001U) /* timer output value is "1" */ +/* Timer output of channel 1 (TOm1) */ +#define _0000_TAU_CH1_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0002_TAU_CH1_OUTPUT_VALUE_1 (0x0002U) /* timer output value is "1" */ +/* Timer output of channel 2 (TOm2) */ +#define _0000_TAU_CH2_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0004_TAU_CH2_OUTPUT_VALUE_1 (0x0004U) /* timer output value is "1" */ +/* Timer output of channel 3 (TOm3) */ +#define _0000_TAU_CH3_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0008_TAU_CH3_OUTPUT_VALUE_1 (0x0008U) /* timer output value is "1" */ +/* Timer output of channel 4 (TOm4) */ +#define _0000_TAU_CH4_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0010_TAU_CH4_OUTPUT_VALUE_1 (0x0010U) /* timer output value is "1" */ +/* Timer output of channel 5 (TOm5) */ +#define _0000_TAU_CH5_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0020_TAU_CH5_OUTPUT_VALUE_1 (0x0020U) /* timer output value is "1" */ +/* Timer output of channel 6 (TOm6) */ +#define _0000_TAU_CH6_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0040_TAU_CH6_OUTPUT_VALUE_1 (0x0040U) /* timer output value is "1" */ +/* Timer output of channel 7 (TOm7) */ +#define _0000_TAU_CH7_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */ +#define _0080_TAU_CH7_OUTPUT_VALUE_1 (0x0080U) /* timer output value is "1" */ + +/* + Timer Output Level Register 0 (TOLm) +*/ +/* Control of timer output level of channel 1 (TOLm1) */ +#define _0000_TAU_CH1_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0002_TAU_CH1_OUTPUT_LEVEL_L (0x0002U) /* inverted output (active-low) */ +/* Control of timer output level of channel 2 (TOLm2) */ +#define _0000_TAU_CH2_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0004_TAU_CH2_OUTPUT_LEVEL_L (0x0004U) /* inverted output (active-low) */ +/* Control of timer output level of channel 3 (TOLm3) */ +#define _0000_TAU_CH3_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0008_TAU_CH3_OUTPUT_LEVEL_L (0x0008U) /* inverted output (active-low) */ +/* Control of timer output level of channel 4 (TOLm4) */ +#define _0000_TAU_CH4_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0010_TAU_CH4_OUTPUT_LEVEL_L (0x0010U) /* inverted output (active-low) */ +/* Control of timer output level of channel 5 (TOLm5) */ +#define _0000_TAU_CH5_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0020_TAU_CH5_OUTPUT_LEVEL_L (0x0020U) /* inverted output (active-low) */ +/* Control of timer output level of channel 6 (TOLm6) */ +#define _0000_TAU_CH6_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0040_TAU_CH6_OUTPUT_LEVEL_L (0x0040U) /* inverted output (active-low) */ +/* Control of timer output level of channel 7 (TOLm7) */ +#define _0000_TAU_CH7_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */ +#define _0080_TAU_CH7_OUTPUT_LEVEL_L (0x0080U) /* inverted output (active-low) */ + +/* + Timer Output Mode Register m (TOMm) +*/ +/* Control of timer output mode of channel 1 (TOMm1) */ +#define _0000_TAU_CH1_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0002_TAU_CH1_OUTPUT_COMBIN (0x0002U) /* combination operation mode */ +/* Control of timer output mode of channel 2 (TOMm2) */ +#define _0000_TAU_CH2_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0004_TAU_CH2_OUTPUT_COMBIN (0x0004U) /* combination operation mode */ +/* Control of timer output mode of channel 3 (TOMm3) */ +#define _0000_TAU_CH3_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0008_TAU_CH3_OUTPUT_COMBIN (0x0008U) /* combination operation mode */ +/* Control of timer output mode of channel 4 (TOMm4) */ +#define _0000_TAU_CH4_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0010_TAU_CH4_OUTPUT_COMBIN (0x0010U) /* combination operation mode */ +/* Control of timer output mode of channel 5 (TOMm5) */ +#define _0000_TAU_CH5_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0020_TAU_CH5_OUTPUT_COMBIN (0x0020U) /* combination operation mode */ +/* Control of timer output mode of channel 6 (TOMm6) */ +#define _0000_TAU_CH6_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0040_TAU_CH6_OUTPUT_COMBIN (0x0040U) /* combination operation mode */ +/* Control of timer output mode of channel 7 (TOMm7) */ +#define _0000_TAU_CH7_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */ +#define _0080_TAU_CH7_OUTPUT_COMBIN (0x0080U) /* combination operation mode */ + +#define _0000_TAU_PWM_DELAY_CLEAR (0x0000U) /* clear PWM output delay control register */ + +/* + PWM output delay control register 1 (PWMDLY1) +*/ +/* Control of PWM output delay time of TAU0 TO01 */ +#define _0000_TO01_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0004_TO01_OUTPUT_DELAY_1 (0x0004U) /* delay 1 cycle */ +#define _0008_TO01_OUTPUT_DELAY_2 (0x0008U) /* delay 2 cycles */ +#define _000C_TO01_OUTPUT_DELAY_3 (0x000CU) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO02 */ +#define _0000_TO02_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0010_TO02_OUTPUT_DELAY_1 (0x0010U) /* delay 1 cycle */ +#define _0020_TO02_OUTPUT_DELAY_2 (0x0020U) /* delay 2 cycles */ +#define _0030_TO02_OUTPUT_DELAY_3 (0x0030U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO03 */ +#define _0000_TO03_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0040_TO03_OUTPUT_DELAY_1 (0x0040U) /* delay 1 cycle */ +#define _0080_TO03_OUTPUT_DELAY_2 (0x0080U) /* delay 2 cycles */ +#define _00C0_TO03_OUTPUT_DELAY_3 (0x00C0U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO04 */ +#define _0000_TO04_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0100_TO04_OUTPUT_DELAY_1 (0x0100U) /* delay 1 cycle */ +#define _0200_TO04_OUTPUT_DELAY_2 (0x0200U) /* delay 2 cycles */ +#define _0300_TO04_OUTPUT_DELAY_3 (0x0300U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO05 */ +#define _0000_TO05_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0400_TO05_OUTPUT_DELAY_1 (0x0400U) /* delay 1 cycle */ +#define _0800_TO05_OUTPUT_DELAY_2 (0x0800U) /* delay 2 cycles */ +#define _0C00_TO05_OUTPUT_DELAY_3 (0x0C00U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO06 */ +#define _0000_TO06_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _1000_TO06_OUTPUT_DELAY_1 (0x1000U) /* delay 1 cycle */ +#define _2000_TO06_OUTPUT_DELAY_2 (0x2000U) /* delay 2 cycles */ +#define _3000_TO06_OUTPUT_DELAY_3 (0x3000U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU0 TO07 */ +#define _0000_TO07_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _4000_TO07_OUTPUT_DELAY_1 (0x4000U) /* delay 1 cycle */ +#define _8000_TO07_OUTPUT_DELAY_2 (0x8000U) /* delay 2 cycles */ +#define _C000_TO07_OUTPUT_DELAY_3 (0xC000U) /* delay 3 cycles */ + +/* + PWM output delay control register 2 (PWMDLY2) +*/ +/* Control of PWM output delay time of TAU1 TO11 */ +#define _0000_TO11_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0004_TO11_OUTPUT_DELAY_1 (0x0004U) /* delay 1 cycle */ +#define _0008_TO11_OUTPUT_DELAY_2 (0x0008U) /* delay 2 cycles */ +#define _000C_TO11_OUTPUT_DELAY_3 (0x000CU) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU1 TO12 */ +#define _0000_TO12_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0010_TO12_OUTPUT_DELAY_1 (0x0010U) /* delay 1 cycle */ +#define _0020_TO12_OUTPUT_DELAY_2 (0x0020U) /* delay 2 cycles */ +#define _0030_TO12_OUTPUT_DELAY_3 (0x0030U) /* delay 3 cycles */ +/* Control of PWM output delay time of TAU1 TO13 */ +#define _0000_TO13_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0040_TO13_OUTPUT_DELAY_1 (0x0040U) /* delay 1 cycle */ +#define _0080_TO13_OUTPUT_DELAY_2 (0x0080U) /* delay 2 cycles */ +#define _00C0_TO13_OUTPUT_DELAY_3 (0x00C0U) /* delay 3 cycles */ + +/* + Noise Filter Enable Register 1 (NFEN1) +*/ +/* Enable/disable using noise filter of TI07 pin input signal (TNFEN07) */ +#define _00_TAU_CH7_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _80_TAU_CH7_NOISE_ON (0x80U) /* noise filter ON */ +/* Enable/disable using noise filter of TI06 pin input signal (TNFEN06) */ +#define _00_TAU_CH6_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _40_TAU_CH6_NOISE_ON (0x40U) /* noise filter ON */ +/* Enable/disable using noise filter of TI05 pin input signal (TNFEN05) */ +#define _00_TAU_CH5_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _20_TAU_CH5_NOISE_ON (0x20U) /* noise filter ON */ +/* Enable/disable using noise filter of TI04 pin input signal (TNFEN04) */ +#define _00_TAU_CH4_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _10_TAU_CH4_NOISE_ON (0x10U) /* noise filter ON */ +/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */ +#define _00_TAU_CH3_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _08_TAU_CH3_NOISE_ON (0x08U) /* noise filter ON */ +/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */ +#define _00_TAU_CH2_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _04_TAU_CH2_NOISE_ON (0x04U) /* noise filter ON */ +/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */ +#define _00_TAU_CH1_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _02_TAU_CH1_NOISE_ON (0x02U) /* noise filter ON */ +/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */ +#define _00_TAU_CH0_NOISE_OFF (0x00U) /* noise filter OFF */ +#define _01_TAU_CH0_NOISE_ON (0x01U) /* noise filter ON */ + +/* + Format of Peripheral Enable Register 1 (PER1) +*/ +/* Control of timer RJ0 input clock supply (TRJ0EN) */ +#define _00_TMRJ_CLOCK_STOP (0x00U) /* stops input clock supply */ +#define _01_TMRJ_CLOCK_ENABLE (0x01U) /* enables input clock supply */ + +/* + Timer RJ Control Register (TRJCR0) +*/ +/* Timer RJ count start bit (TSTART) */ +#define _00_TMRJ_COUNT_STOP (0x00U) /* count stops */ +#define _01_TMRJ_COUNT_START (0x01U) /* count starts */ +/* Timer RJ count status flag (TCSTF) */ +#define _00_TMRJ_STATUS_STOP (0x00U) /* count stops */ +#define _02_TMRJ_STATUS_COUNT (0x02U) /* during count */ +/* Timer RJ count forcible stop bit (TSTOP) */ +#define _00_TMRJ_FORCIBLE_STOP_DISABLE (0x00U) /* the count is not forcibly stopped */ +#define _04_TMRJ_FORCIBLE_STOP_ENABLE (0x04U) /* the count is forcibly stopped */ +/* Active edge judgment flag (TEDGF) */ +#define _00_TMRJ_ACTIVE_EDGE_RECEIVED (0x00U) /* active edge not received */ +#define _10_TMRJ_ACTIVE_EDGE_UNRECEIVED (0x10U) /* active edge received (end of measurement period) */ +/* Timer RJ underflow flag (TUNDF) */ +#define _00_TMRJ_UNDERFLOW_NOOCCUR (0x00U) /* no underflow */ +#define _20_TMRJ_UNDERFLOW_OCCUR (0x20U) /* underflow */ + +/* + Timer RJ I/O Control Register (TRJIOC0) +*/ +#define _00_TMRJ_TRJIOC_INITIAL_VALUE (0x00U) +/* TRJIO polarity switch bit (TEDGSEL) */ +#define _00_TMRJ_TRJIO_POLARITY_0 (0x00U) /* TRJIO polarity switch bit = 0 */ +#define _01_TMRJ_TRJIO_POLARITY_1 (0x01U) /* TRJIO polarity switch bit = 1 */ +/* TRJO output enable bit (TOENA) */ +#define _00_TMRJ_TRJO_OUTPUT_DISABLE (0x00U) /* TRJO output disable */ +#define _04_TMRJ_TRJO_OUTPUT_ENABLE (0x04U) /* TRJO output */ +/* TRJIO input filter select bit (TIPF1, TIPF0) */ +#define _00_TMRJ_TRJIO_FILTER_UNUSED (0x00U) /* no filter */ +#define _10_TMRJ_TRJIO_FILTER_FCLK (0x10U) /* filter with fCLK sampling */ +#define _20_TMRJ_TRJIO_FILTER_FCLK8 (0x20U) /* filter with fCLK/8 sampling */ +#define _30_TMRJ_TRJIO_FILTER_FCLK32 (0x30U) /* filter with fCLK/32 sampling */ +/* TRJIO event input control bit (TIOGT1, TIOGT0) */ +#define _00_TMRJ_EVENT_ENABLE_ALWAYS (0x00U) /* event is counted */ +#define _40_TMRJ_EVENT_ENABLE_INTP4 (0x40U) /* event is counted during INTP4 specified period */ +#define _80_TMRJ_EVENT_ENABLE_PWM (0x80U) /* event is counted during PWM signal period */ + +/* + Timer RJ Mode Register (TRJMR0) +*/ +/* Timer RJ operating mode select bit (TMOD2 - TMOD0) */ +#define _00_TMRJ_MODE_TIMER (0x00U) /* timer mode */ +#define _01_TMRJ_MODE_PULSE_OUTPUT (0x01U) /* pulse output mode */ +#define _02_TMRJ_MODE_EVENT_COUNTER (0x02U) /* event counter mode */ +#define _03_TMRJ_MODE_PULSE_WIDTH (0x03U) /* pulse width measurement mode */ +#define _04_TMRJ_MODE_PULSE_PERIOD (0x04U) /* pulse period measurement mode */ +/* TRJIO input polarity select bit (TEDGPL) */ +#define _00_TMRJ_TRJIO_POLARITY_ONE (0x00U) /* one edge */ +#define _08_TMRJ_TRJIO_POLARITY_BOTH (0x08U) /* both edges */ +/* Timer RJ count source select bit (TCK2 - TCK0) */ +#define _00_TMRJ_COUNT_SOURCE_FCLK (0x00U) /* fCLK */ +#define _10_TMRJ_COUNT_SOURCE_FCLK8 (0x10U) /* fCLK8 */ +#define _30_TMRJ_COUNT_SOURCE_FCLK2 (0x30U) /* fCLK2 */ +#define _40_TMRJ_COUNT_SOURCE_FIL (0x40U) /* fIL */ +#define _60_TMRJ_COUNT_SOURCE_FSL (0x60U) /* fSL */ + +/* + Timer RJ event pin selection register 0 (TRJISR0) +*/ +/* PWM signal selection (RCCPSEL1, RCCPSEL0) */ +#define _00_TMRJ_PWM_TRDIOD1 (0x00U) /* TRDIOD1 */ +#define _01_TMRJ_PWM_TRDIOC1 (0x01U) /* TRDIOC1 */ +#define _02_TMRJ_PWM_TO02 (0x02U) /* TO02 */ +#define _03_TMRJ_PWM_TO03 (0x03U) /* TO03 */ +/* PWM signal and INTP4 polarity selection (RCCPSEL2) */ +#define _00_TMRJ_PWM_POLARITY_L (0x00U) /* L period is counted */ +#define _04_TMRJ_PWM_POLARITY_H (0x04U) /* H period is counted */ + +/* + Peripheral enable register 1 (PER1) +*/ +/* Control of timer RD input clock supply (TRD0EN) */ +#define _00_TMRD_NOSUPPLY (0x00U) /* stops input clock supply */ +#define _10_TMRD_SUPPLY (0x10U) /* enables input clock supply */ + +/* + Timer RD ELC Register (TRDELC) +*/ +/* ELC event input 0 select for timer RD input capture D0 (ELCICE0) */ +#define _00_TMRD0_INPUTCAPTURE (0x00U) /* input capture D0 is selected */ +#define _01_TMRD0_ELC (0x01U) /* the event link controller (ELC) is not selected */ +/* ELC event input 0 enable for timer RD pulse output forced cutoff (ELCOBE0) */ +#define _00_TMRD0_CUTOFF_DISABLED (0x00U) /* forced cutoff is disabled */ +#define _02_TMRD0_CUTOFF_ENABLED (0x02U) /* forced cutoff is enabled */ +/* ELC event input 1 select for timer RD input capture D1 (ELCICE1) */ +#define _00_TMRD1_INPUTCAPTURE (0x00U) /* input capture D1 is selected */ +#define _10_TMRD1_ELC (0x10U) /* event link controller (ELC) is selected */ +/* ELC event input 1 enable for timer RD pulse output forced cutoff (ELCOBE1) */ +#define _00_TMRD1_CUTOFF_DISABLED (0x00U) /* forced cutoff is disabled */ +#define _20_TMRD1_CUTOFF_ENABLED (0x20U) /* forced cutoff is enabled */ + +/* + Timer RD Start Register (TRDSTR) +*/ +#define _03_TRD_COUNT_STATR_INITIAL_VALUE (0x03U) /* trd0/trd1 count satrts */ +/* TRD0 count start flag (TSTART0) */ +#define _00_TMRD_TRD0_COUNT_STOP (0x00U) /* trd0 count stops */ +#define _01_TMRD_TRD0_COUNT_START (0x01U) /* trd0 count starts */ +/* TRD1 count start flag (TSTART1) */ +#define _00_TMRD_TRD1_COUNT_STOP (0x00U) /* trd1 count stops */ +#define _02_TMRD_TRD1_COUNT_START (0x02U) /* trd1 count starts */ +/* TRD0 count operation select bit (CSEL0) */ +#define _00_TMRD_TRD0_COUNT_STOP_MATCH (0x00U) /* count stops at the compare match */ +#define _04_TMRD_TRD0_COUNT_CONTINUES (0x04U) /* count continues after the compare match */ +/* TRD1 count operation select bit (CSEL1) */ +#define _00_TMRD_TRD1_COUNT_STOP_MATCH (0x00U) /* count stops at the compare match */ +#define _08_TMRD_TRD1_COUNT_CONTINUES (0x08U) /* count continues after the compare match */ + +/* + Timer RD Mode Register (TRDMR) +*/ +/* Timer RD synchronous bit (SYNC) */ +#define _00_TMRD_INDEPENDENTLY (0x00U) /* registers TRD0 and TRD1 operate independently */ +#define _01_TMRD_SYNCHRONOUSLY (0x01U) /* registers TRD0 and TRD1 operate synchronously */ +/* TRDGRC0 register function select bit (BFC0) */ +#define _00_TMRD_TRDGRC0_GENERAL (0x00U) /* general register */ +#define _10_TMRD_TRDGRC0_BUFFER (0x10U) /* buffer register of TRDGRA0 register */ +/* TRDGRD0 register function select bit (BFD0) */ +#define _00_TMRD_TRDGRD0_GENERAL (0x00U) /* general register */ +#define _20_TMRD_TRDGRD0_BUFFER (0x20U) /* buffer register of TRDGRB0 register */ +/* TRDGRC1 register function select bit (BFC1) */ +#define _00_TMRD_TRDGRC1_GENERAL (0x00U) /* general register */ +#define _40_TMRD_TRDGRC1_BUFFER (0x40U) /* buffer register of TRDGRA1 register */ +/* TRDGRD1 register function select bit (BFD1) */ +#define _00_TMRD_TRDGRD1_GENERAL (0x00U) /* general register */ +#define _80_TMRD_TRDGRD1_BUFFER (0x80U) /* buffer register of TRDGRB1 register */ + +/* + Timer RD PWM Mode Register (TRDPMR) +*/ +/* PWM mode of TRDIOB0 select bit (PWMB0) */ +#define _00_TMRD_TRDIOB0_TIMER_MODE (0x00U) /* TRDIOB0 used as timer mode */ +#define _01_TMRD_TRDIOB0_PWM_MODE (0x01U) /* TRDIOB0 used as PWM mode */ +/* PWM mode of TRDIOC0 select bit (PWMC0) */ +#define _00_TMRD_TRDIOC0_TIMER_MODE (0x00U) /* TRDIOC0 used as timer mode */ +#define _02_TMRD_TRDIOC0_PWM_MODE (0x02U) /* TRDIOC0 used as PWM mode */ +/* PWM mode of TRDIOD0 select bit (PWMD0) */ +#define _00_TMRD_TRDIOD0_TIMER_MODE (0x00U) /* TRDIOD0 used as timer mode */ +#define _04_TMRD_TRDIOD0_PWM_MODE (0x04U) /* TRDIOD0 used as PWM mode */ +/* PWM mode of TRDIOB1 select bit (PWMB1) */ +#define _00_TMRD_TRDIOB1_TIMER_MODE (0x00U) /* TRDIOB1 used as timer mode */ +#define _10_TMRD_TRDIOB1_PWM_MODE (0x10U) /* TRDIOB1 used as PWM mode */ +/* PWM mode of TRDIOC1 select bit (PWMC1) */ +#define _00_TMRD_TRDIOC1_TIMER_MODE (0x00U) /* TRDIOC1 used as timer mode */ +#define _20_TMRD_TRDIOC1_PWM_MODE (0x20U) /* TRDIOC1 used as PWM mode */ +/* PWM mode of TRDIOD1 select bit (PWMD1) */ +#define _00_TMRD_TRDIOD1_TIMER_MODE (0x00U) /* TRDIOD1 used as timer mode */ +#define _40_TMRD_TRDIOD1_PWM_MODE (0x40U) /* TRDIOD1 used as PWM mode */ + +/* + Timer RD Function Control Register (TRDFCR) +*/ +/* Combination mode select bit (CMD1, CMD0) */ +#define _00_TMRD_TRANSFER_DEFAULT (0x00U) /* in timer mode, PWM mode, or PWM3 mode */ +#define _01_TMRD_TRANSFER_RESET_SYNCHRONOUS (0x01U) /* in reset synchronous PWM mode */ +#define _02_TMRD_TRANSFER_TMRD1_UNDERFLOW (0x02U) /* transfer from buffer register to general register */ +#define _03_TMRD_TRANSFER_TMRD0_MATCH (0x03U) /* transfer from buffer register to general register */ +/* Normal-phase output level select bit (OLS0) */ +#define _00_TMRD_NORMAL_PHASE_LEVEl_HL (0x00U) /* initial output "H", Active level "L" */ +#define _04_TMRD_NORMAL_PHASE_LEVEl_LH (0x04U) /* initial output "L", Active level "H" */ +/* Counter-phase output level select bit (OLS1) */ +#define _00_TMRD_COUNTER_PHASE_LEVEl_HL (0x00U) /* initial output "H", Active level "L" */ +#define _08_TMRD_COUNTER_PHASE_LEVEl_LH (0x08U) /* initial output "L", Active level "H" */ +/* External clock input select bit (STCLK) */ +#define _00_TMRD_EXTERNAL_CLOCK_DISABLE (0x00U) /* external clock input disabled */ +#define _40_TMRD_EXTERNAL_CLOCK_ENABLE (0x40U) /* external clock input enabled */ +/* PWM3 mode select bit (PWM3) */ +#define _00_TMRD_PWM3_MODE (0x00U) /* PWM3 mode */ +#define _80_TMRD_OTHER_MODE (0x80U) /* other mode */ + +/* + Timer RD Output Master Enable Register 1 (TRDOER1) +*/ +#define _F0_TMRD_CHANNEL0_OUTPUT_DEFAULT (0xF0U) +#define _0F_TMRD_CHANNEL1_OUTPUT_DEFAULT (0x0FU) +/* TRDIOA0 output disable bit (EA0) */ +#define _00_TMRD_TRDIOA0_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _01_TMRD_TRDIOA0_OUTPUT_DISABLE (0x01U) /* disable output */ +/* TRDIOB0 output disable bit (EB0) */ +#define _00_TMRD_TRDIOB0_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _02_TMRD_TRDIOB0_OUTPUT_DISABLE (0x02U) /* disable output */ +/* TRDIOC0 output disable bit (EC0) */ +#define _00_TMRD_TRDIOC0_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _04_TMRD_TRDIOC0_OUTPUT_DISABLE (0x04U) /* disable output */ +/* TRDIOD0 output disable bit (ED0) */ +#define _00_TMRD_TRDIOD0_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _08_TMRD_TRDIOD0_OUTPUT_DISABLE (0x08U) /* disable output */ +/* TRDIOA1 output disable bit (EA1) */ +#define _00_TMRD_TRDIOA1_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _10_TMRD_TRDIOA1_OUTPUT_DISABLE (0x10U) /* disable output */ +/* TRDIOB1 output disable bit (EB1) */ +#define _00_TMRD_TRDIOB1_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _20_TMRD_TRDIOB1_OUTPUT_DISABLE (0x20U) /* disable output */ +/* TRDIOC1 output disable bit (EC1) */ +#define _00_TMRD_TRDIOC1_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _40_TMRD_TRDIOC1_OUTPUT_DISABLE (0x40U) /* disable output */ +/* TRDIOD1 output disable bit (ED1) */ +#define _00_TMRD_TRDIOD1_OUTPUT_ENABLE (0x00U) /* enable output */ +#define _80_TMRD_TRDIOD1_OUTPUT_DISABLE (0x80U) /* disable output */ + +/* + Timer RD Output Master Enable Register 2 (TRDOER2) +*/ +/* INT0 of pulse output forced cutoff signal input enabled bit (PTO) */ +#define _00_TMRD_ALL_OUTPUT_DISABLE (0x00U) /* pulse output forced cutoff input disabled */ +#define _80_TMRD_ALL_OUTPUT_ENABLE (0x80U) /* pulse output forced cutoff input enabled */ +/* Forced cutoff flag (SHUTS) */ +#define _00_TMRD_INTERCEPTION_STOP (0x00U) /* not forcibly cut off */ +#define _01_TMRD_INTERCEPTION (0x01U) /* forcibly cut off */ + +/* + Timer RD Output Control Register (TRDOCR) +*/ +/* TRDIOA0 output level select bit (TOA0) */ +#define _00_TMRD_TRDIOA0_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _01_TMRD_TRDIOA0_INITIAL_OUTPUT_H (0x01U) /* initial output "H" or active level */ +/* TRDIOB0 output level select bit (TOB0) */ +#define _00_TMRD_TRDIOB0_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _02_TMRD_TRDIOB0_INITIAL_OUTPUT_H (0x02U) /* initial output "H" or active level */ +/* TRDIOC0 output level select bit (TOC0) */ +#define _00_TMRD_TRDIOC0_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _04_TMRD_TRDIOC0_INITIAL_OUTPUT_H (0x04U) /* initial output "H" or active level */ +/* TRDIOD0 output level select bit (TOD0) */ +#define _00_TMRD_TRDIOD0_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _08_TMRD_TRDIOD0_INITIAL_OUTPUT_H (0x08U) /* initial output "H" or active level */ +/* TRDIOA1 output level select bit (TOA1) */ +#define _00_TMRD_TRDIOA1_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _10_TMRD_TRDIOA1_INITIAL_OUTPUT_H (0x10U) /* initial output "H" or active level */ +/* TRDIOB1 output level select bit (TOB1) */ +#define _00_TMRD_TRDIOB1_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _20_TMRD_TRDIOB1_INITIAL_OUTPUT_H (0x20U) /* initial output "H" or active level */ +/* TRDIOC1 output level select bit (TOC1) */ +#define _00_TMRD_TRDIOC1_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _40_TMRD_TRDIOC1_INITIAL_OUTPUT_H (0x40U) /* initial output "H" or active level */ +/* TRDIOD1 output level select bit (TOD1) */ +#define _00_TMRD_TRDIOD1_INITIAL_OUTPUT_L (0x00U) /* initial output "L" or inactive level */ +#define _80_TMRD_TRDIOD1_INITIAL_OUTPUT_H (0x80U) /* initial output "H" or active level */ + +/* + Timer RD Digital Filter Function Select Register i (TRDDFi) +*/ +/* TRDIOA pin digital filter function select bit (DFA) */ +#define _00_TMRD_TRDIOA_DIGITAL_FILTER_DISABLE (0x00U) /* TRDIOA pin digital filter function is not used */ +#define _01_TMRD_TRDIOA_DIGITAL_FILTER_ENABLE (0x01U) /* TRDIOA pin digital filter function is used */ +/* TRDIOB pin digital filter function select bit (DFB) */ +#define _00_TMRD_TRDIOB_DIGITAL_FILTER_DISABLE (0x00U) /* TRDIOB pin digital filter function is not used */ +#define _02_TMRD_TRDIOB_DIGITAL_FILTER_ENABLE (0x02U) /* TRDIOB pin digital filter function is used */ +/* TRDIOD pin pulse forced cutoff control (DFB, DFA) */ +#define _00_TMRD_TRDIOD_FORCEDCUTOFF_DISABLE (0x00U) /* forced cutoff disabled */ +#define _01_TMRD_TRDIOD_HIGHIMPEDANCE_OUTPUT (0x01U) /* high-impedance output */ +#define _02_TMRD_TRDIOD_LOW_OUTPUT (0x02U) /* low output */ +#define _03_TMRD_TRDIOD_HIGH_OUTPUT (0x03U) /* high output */ +/* TRDIOC pin digital filter function select bit (DFC) */ +#define _00_TMRD_TRDIOC_DIGITAL_FILTER_DISABLE (0x00U) /* TRDIOC pin digital filter function is not used */ +#define _04_TMRD_TRDIOC_DIGITAL_FILTER_ENABLE (0x04U) /* TRDIOC pin digital filter function is used */ +/* TRDIOD pin digital filter function select bit (DFD) */ +#define _00_TMRD_TRDIOD_DIGITAL_FILTER_DISABLE (0x00U) /* TRDIOD pin digital filter function is not used */ +#define _08_TMRD_TRDIOD_DIGITAL_FILTER_ENABLE (0x08U) /* TRDIOD pin digital filter function is used */ +/* TRDIOC pin pulse forced cutoff control (DFD, DFC) */ +#define _00_TMRD_TRDIOC_FORCEDCUTOFF_DISABLE (0x00U) /* forced cutoff disabled */ +#define _04_TMRD_TRDIOC_HIGHIMPEDANCE_OUTPUT (0x04U) /* high-impedance output */ +#define _08_TMRD_TRDIOC_LOW_OUTPUT (0x08U) /* low output */ +#define _0C_TMRD_TRDIOC_HIGH_OUTPUT (0x0CU) /* high output */ +/* TRDIOB pin pulse forced cutoff control (PENB1, PENB0) */ +#define _00_TMRD_TRDIOB_FORCEDCUTOFF_DISABLE (0x00U) /* forced cutoff disabled */ +#define _10_TMRD_TRDIOB_HIGHIMPEDANCE_OUTPUT (0x10U) /* high-impedance output */ +#define _20_TMRD_TRDIOB_LOW_OUTPUT (0x20U) /* low output */ +#define _30_TMRD_TRDIOB_HIGH_OUTPUT (0x30U) /* high output */ +/* Clock select bits for digital filter function (DFCK1, DFCK0) */ +#define _00_TMRD_DIGITAL_FILTER_CLOCK_F32 (0x00U) /* fTRD/2^5 */ +#define _40_TMRD_DIGITAL_FILTER_CLOCK_F8 (0x40U) /* fTRD/2^3 */ +#define _80_TMRD_DIGITAL_FILTER_CLOCK_F1 (0x80U) /* fTRD */ +#define _C0_TMRD_DIGITAL_FILTER_CLOCK_SOURCE (0xC0U) /* count source */ +/* TRDIOA pin pulse forced cutoff control (DFCK1, DFCK0) */ +#define _00_TMRD_TRDIOA_FORCEDCUTOFF_DISABLE (0x00U) /* forced cutoff disabled */ +#define _40_TMRD_TRDIOA_HIGHIMPEDANCE_OUTPUT (0x40U) /* high-impedance output */ +#define _80_TMRD_TRDIOA_LOW_OUTPUT (0x80U) /* low output */ +#define _C0_TMRD_TRDIOA_HIGH_OUTPUT (0xC0U) /* high output */ + +/* + Timer RD Control Register i (TRDCRi) +*/ +/* Count source select bit (TCK2 - TCK0) */ +#define _00_TMRD_INTERNAL_CLOCK_F1 (0x00U) /* fTRD */ +#define _00_TMRD_INTERNAL_CLOCK_FIH (0x00U) /* fIH */ +#define _00_TMRD_INTERNAL_CLOCK_FPLL (0x00U) /* fPLL */ +#define _00_TMRD_INTERNAL_CLOCK_FSL (0x00U) /* fSL */ +#define _01_TMRD_INTERNAL_CLOCK_F2 (0x01U) /* fTRD/2 */ +#define _02_TMRD_INTERNAL_CLOCK_F4 (0x02U) /* fTRD/2^2 */ +#define _03_TMRD_INTERNAL_CLOCK_F8 (0x03U) /* fTRD/2^3 */ +#define _04_TMRD_INTERNAL_CLOCK_F32 (0x04U) /* fTRD/2^5 */ +#define _05_TMRD_INTERNAL_CLOCK_TRDCLK (0x05U) /* TRDCLK input */ +/* External clock edge select bit (CKEG1, CKEG0) */ +#define _00_TMRD_EXTERNAL_CLOCK_EDGE_RISING (0x00U) /* count at the rising edge */ +#define _08_TMRD_EXTERNAL_CLOCK_EDGE_FALLING (0x08U) /* count at the falling edge */ +#define _10_TMRD_EXTERNAL_CLOCK_EDGE_BOTH (0x10U) /* count at both edges */ +/* TRDi counter clear select bit (CCLR2 - CCLR0) */ +#define _00_TMRD_COUNTER_CLEAR_DISABLE (0x00U) /* disable clear (free-running operation) */ +#define _20_TMRD_COUNTER_CLEAR_TRDGRA (0x20U) /* clear with the TRDGRAi register */ +#define _40_TMRD_COUNTER_CLEAR_TRDGRB (0x40U) /* clear with the TRDGRBi register */ +#define _60_TMRD_COUNTER_CLEAR_SYNCHRONOUS (0x60U) /* synchronous clear */ +#define _A0_TMRD_COUNTER_CLEAR_TRDGRC (0xA0U) /* clear by input capture with TRDGRCi register */ +#define _C0_TMRD_COUNTER_CLEAR_TRDGRD (0xC0U) /* clear by input capture with TRDGRDi register */ + +/* + Timer RD I/O Control Register Ai (TRDIORAi) +*/ +/* TRDGRA control bit (IOA1, IOA0) */ +#define _00_TMRD_TRDGRA_CAPTURE_RISING (0x00U) /* input capture to the TRDGRAi register at the rising edge */ +#define _01_TMRD_TRDGRA_CAPTURE_FALLING (0x01U) /* input capture to TRDGRAi register at falling edge */ +#define _02_TMRD_TRDGRA_CAPTURE_BOTH (0x02U) /* input capture to the TRDGRAi register at the both edges */ +#define _00_TMRD_TRDGRA_COMPARE_OUTPUT_DISABLE (0x00U) /* pin output by compare match is disabled */ +#define _01_TMRD_TRDGRA_COMPARE_OUTPUT_LOW (0x01U) /* "L" output by compare match with the TRDGRAi register */ +#define _02_TMRD_TRDGRA_COMPARE_OUTPUT_HIGH (0x02U) /* "H" output by compare match with the TRDGRAi register */ +#define _03_TMRD_TRDGRA_COMPARE_OUTPUT_TOGGLE (0x03U) /* toggle output by compare match with the TRDGRAi register */ +/* TRDGRA mode select bit (IOA2) */ +#define _00_TMRD_TRDGRA_COMPARE (0x00U) /* output compare */ +#define _04_TMRD_TRDGRA_CAPTURE (0x04U) /* input capture */ +/* TRDGRB control bit (IOB1, IOB0) */ +#define _00_TMRD_TRDGRB_CAPTURE_RISING (0x00U) /* input capture to the TRDGRBi register at the rising edge */ +#define _10_TMRD_TRDGRB_CAPTURE_FALLING (0x10U) /* input capture to TRDGRBi register at falling edge */ +#define _20_TMRD_TRDGRB_CAPTURE_BOTH (0x20U) /* input capture to the TRDGRBi register at the both edges */ +#define _00_TMRD_TRDGRB_COMPARE_OUTPUT_DISABLE (0x00U) /* disable output prohibition by compare agreement */ +#define _10_TMRD_TRDGRB_COMPARE_OUTPUT_LOW (0x10U) /* "L" output by compare match with the TRDGRBi register */ +#define _20_TMRD_TRDGRB_COMPARE_OUTPUT_HIGH (0x20U) /* "H" output by compare match with the TRDGRBi register */ +#define _30_TMRD_TRDGRB_COMPARE_OUTPUT_TOGGLE (0x30U) /* toggle output by compare match with the TRDGRBi register */ +/* TRDGRB mode select bit (IOB2) */ +#define _00_TMRD_TRDGRB_COMPARE (0x00U) /* output compare */ +#define _40_TMRD_TRDGRB_CAPTURE (0x40U) /* input capture */ + +/* + Timer RD I/O Control Register Ci (TRDIORCi) +*/ +/* TRDGRC control bit (IOC1, IOC0) */ +#define _00_TMRD_TRDGRC_CAPTURE_RISING (0x00U) /* input capture to the TRDGRCi register at rising edge */ +#define _01_TMRD_TRDGRC_CAPTURE_FALLING (0x01U) /* input capture to TRDGRCi register at falling edge */ +#define _02_TMRD_TRDGRC_CAPTURE_BOTH (0x02U) /* input capture to the TRDGRCi register at the both edges */ +#define _00_TMRD_TRDGRC_COMPARE_OUTPUT_DISABLE (0x00U) /* disable pin output by the compare match */ +#define _01_TMRD_TRDGRC_COMPARE_OUTPUT_LOW (0x01U) /* "L" output by compare match with the TRDGRCi register */ +#define _02_TMRD_TRDGRC_COMPARE_OUTPUT_HIGH (0x02U) /* "H" output by compare match with the TRDGRCi register */ +#define _03_TMRD_TRDGRC_COMPARE_OUTPUT_TOGGLE (0x03U) /* toggle output by compare match with the TRDGRCi register */ +/* TRDGRC mode select bit (IOC2) */ +#define _00_TMRD_TRDGRC_COMPARE (0x00U) /* output compare */ +#define _04_TMRD_TRDGRC_CAPTURE (0x04U) /* input capture */ +/* TRDGRC register function select bit (IOC3) */ +#define _00_TMRD_TRDGRC_OUTPUT_REGISTER (0x00U) /* output register */ +#define _08_TMRD_TRDGRC_GENERAL_BUFFER_REGISTER (0x08U) /* general register or buffer register */ +/* TRDGRD control bit (IOD1, IOD0) */ +#define _00_TMRD_TRDGRD_CAPTURE_RISING (0x00U) /* input capture to TRDGRDi register at rising edge */ +#define _10_TMRD_TRDGRD_CAPTURE_FALLING (0x10U) /* input capture to TRDGRDi register at falling edge */ +#define _20_TMRD_TRDGRD_CAPTURE_BOTH (0x20U) /* input capture to TRDGRDi register at both edges */ +#define _00_TMRD_TRDGRD_COMPARE_OUTPUT_DISABLE (0x00U) /* disable pin output by the compare match */ +#define _10_TMRD_TRDGRD_COMPARE_OUTPUT_LOW (0x10U) /* "L" output by compare match with the TRDGRDi register */ +#define _20_TMRD_TRDGRD_COMPARE_OUTPUT_HIGH (0x20U) /* "H" output by compare match with the TRDGRDi register */ +#define _30_TMRD_TRDGRD_COMPARE_OUTPUT_TOGGLE (0x30U) /* toggle output by compare match with the TRDGRDi register */ +/* TRDGRD mode select bit (IOD2) */ +#define _00_TMRD_TRDGRD_COMPARE (0x00U) /* output compare */ +#define _40_TMRD_TRDGRD_CAPTURE (0x40U) /* input capture */ +/* TRDGRD register function select bit (IOD3) */ +#define _00_TMRD_TRDGRD_OUTPUT_REGISTER (0x00U) /* output register */ +#define _80_TMRD_TRDGRD_GENERAL_BUFFER_REGISTER (0x80U) /* general register or buffer register */ + +/* + Timer RD Status Register 0 (TRDSR0) +*/ +#define _E0_TMRD_TRDSR0_DEFAULT_VALUR (0xE0U) /* TRDSR0 register default value */ +/* Input capture/compare match flag A (IMFA) */ +#define _00_TMRD0_INTA_FLAG_CLEAR (0x00U) /* interrupt A not generate */ +#define _01_TMRD0_INTA_GENERATE_FLAG (0x01U) /* interrupt A generate */ +/* Input capture/compare match flag B (IMFB) */ +#define _00_TMRD0_INTB_FLAG_CLEAR (0x00U) /* interrupt B not generate */ +#define _02_TMRD0_INTB_GENERATE_FLAG (0x02U) /* interrupt B generate */ +/* Input capture/compare match flag C (IMFC) */ +#define _00_TMRD0_INTC_FLAG_CLEAR (0x00U) /* interrupt C not generate */ +#define _04_TMRD0_INTC_GENERATE_FLAG (0x04U) /* interrupt C generate */ +/* Input capture/compare match flag D (IMFD) */ +#define _00_TMRD0_INTD_FLAG_CLEAR (0x00U) /* interrupt D not generate */ +#define _08_TMRD0_INTD_GENERATE_FLAG (0x08U) /* interrupt D generate */ +/* Overflow flag (OVF) */ +#define _00_TMRD0_INTOV_FLAG_CLEAR (0x00U) /* interrupt overflow not generate */ +#define _10_TMRD0_INTOV_GENERATE_FLAG (0x10U) /* interrupt overflow generate */ + +/* + Timer RD Status Register 1 (TRDSR1) +*/ +#define _C0_TMRD_TRDSR1_DEFAULT_VALUR (0xC0U) /* TRDSR1 register default value */ +/* Input capture/compare match flag A (IMFA) */ +#define _00_TMRD1_INTA_FLAG_CLEAR (0x00U) /* interrupt A not generate */ +#define _01_TMRD1_INTA_GENERATE_FLAG (0x01U) /* interrupt A generate */ +/* Input capture/compare match flag B (IMFB) */ +#define _00_TMRD1_INTB_FLAG_CLEAR (0x00U) /* interrupt B not generate */ +#define _02_TMRD1_INTB_GENERATE_FLAG (0x02U) /* interrupt B generate */ +/* Input capture/compare match flag C (IMFC) */ +#define _00_TMRD1_INTC_FLAG_CLEAR (0x00U) /* interrupt C not generate */ +#define _04_TMRD1_INTC_GENERATE_FLAG (0x04U) /* interrupt C generate */ +/* Input capture/compare match flag D (IMFD) */ +#define _00_TMRD1_INTD_FLAG_CLEAR (0x00U) /* interrupt D not generate */ +#define _08_TMRD1_INTD_GENERATE_FLAG (0x08U) /* interrupt D generate */ +/* Overflow flag (OVF) */ +#define _00_TMRD1_INTOV_FLAG_CLEAR (0x00U) /* interrupt overflow not generate */ +#define _10_TMRD1_INTOV_GENERATE_FLAG (0x10U) /* interrupt overflow generate */ + +/* + Timer RD Interrupt Enable Register i (TRDIERi) +*/ +/* Input capture/compare match interrupt enable bit A (IMIEA) */ +#define _00_TMRD_IMIA_DISABLE (0x00U) /* disable interrupt (IMIA) by the IMFA bit */ +#define _01_TMRD_IMIA_ENABLE (0x01U) /* enable interrupt (IMIA) by the IMFA bit */ +/* Input capture/compare match interrupt enable bit B (IMIEB) */ +#define _00_TMRD_IMIB_DISABLE (0x00U) /* disable interrupt (IMIB) by the IMFB bit */ +#define _02_TMRD_IMIB_ENABLE (0x02U) /* enable interrupt (IMIB) by the IMFB bit */ +/* Input capture/compare match interrupt enable bit C (IMIEC) */ +#define _00_TMRD_IMIC_DISABLE (0x00U) /* disable interrupt (IMIC) by the IMFC bit */ +#define _04_TMRD_IMIC_ENABLE (0x04U) /* enable interrupt (IMIC) by the IMFC bit */ +/* Input capture/compare match interrupt enable bit D (IMIED) */ +#define _00_TMRD_IMID_DISABLE (0x00U) /* disable interrupt (IMID) by the IMFD bit */ +#define _08_TMRD_IMID_ENABLE (0x08U) /* enable interrupt (IMId) by the IMFD bit */ +/* Overflow/underflow interrupt enable bit (OVIE) */ +#define _00_TMRD_OVIE_DISABLE (0x00U) /* disable interrupt (OVI) by the OVF or UDF bit */ +#define _10_TMRD_OVIE_ENABLE (0x10U) /* enable interrupt (OVI) by the OVF or UDF bit */ + +#define _0000_TMRD_PWM_DELAY_CLEAR (0x0000U) /* clear PWM output delay control register */ + +/* + PWM output delay control register 0 (PWMDLY0) +*/ +/* Control of PWM output delay time of TRDIOA0 */ +#define _0000_TMRD_TRDIOA0_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0001_TMRD_TRDIOA0_OUTPUT_DELAY_1 (0x0001U) /* delay 1 cycle */ +#define _0002_TMRD_TRDIOA0_OUTPUT_DELAY_2 (0x0002U) /* delay 2 cycles */ +#define _0003_TMRD_TRDIOA0_OUTPUT_DELAY_3 (0x0003U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOB0 */ +#define _0000_TMRD_TRDIOB0_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0004_TMRD_TRDIOB0_OUTPUT_DELAY_1 (0x0004U) /* delay 1 cycle */ +#define _0008_TMRD_TRDIOB0_OUTPUT_DELAY_2 (0x0008U) /* delay 2 cycles */ +#define _000C_TMRD_TRDIOB0_OUTPUT_DELAY_3 (0x000CU) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOC0 */ +#define _0000_TMRD_TRDIOC0_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0010_TMRD_TRDIOC0_OUTPUT_DELAY_1 (0x0010U) /* delay 1 cycle */ +#define _0020_TMRD_TRDIOC0_OUTPUT_DELAY_2 (0x0020U) /* delay 2 cycles */ +#define _0030_TMRD_TRDIOC0_OUTPUT_DELAY_3 (0x0030U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOD0 */ +#define _0000_TMRD_TRDIOD0_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0040_TMRD_TRDIOD0_OUTPUT_DELAY_1 (0x0040U) /* delay 1 cycle */ +#define _0080_TMRD_TRDIOD0_OUTPUT_DELAY_2 (0x0080U) /* delay 2 cycles */ +#define _00C0_TMRD_TRDIOD0_OUTPUT_DELAY_3 (0x00C0U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOA1 */ +#define _0000_TMRD_TRDIOA1_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0100_TMRD_TRDIOA1_OUTPUT_DELAY_1 (0x0100U) /* delay 1 cycle */ +#define _0200_TMRD_TRDIOA1_OUTPUT_DELAY_2 (0x0200U) /* delay 2 cycles */ +#define _0300_TMRD_TRDIOA1_OUTPUT_DELAY_3 (0x0300U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOB1 */ +#define _0000_TMRD_TRDIOB1_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _0400_TMRD_TRDIOB1_OUTPUT_DELAY_1 (0x0400U) /* delay 1 cycle */ +#define _0800_TMRD_TRDIOB1_OUTPUT_DELAY_2 (0x0800U) /* delay 2 cycles */ +#define _0C00_TMRD_TRDIOB1_OUTPUT_DELAY_3 (0x0C00U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOC1 */ +#define _0000_TMRD_TRDIOC1_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _1000_TMRD_TRDIOC1_OUTPUT_DELAY_1 (0x1000U) /* delay 1 cycle */ +#define _2000_TMRD_TRDIOC1_OUTPUT_DELAY_2 (0x2000U) /* delay 2 cycles */ +#define _3000_TMRD_TRDIOC1_OUTPUT_DELAY_3 (0x3000U) /* delay 3 cycles */ +/* Control of PWM output delay time of TRDIOD1 */ +#define _0000_TMRD_TRDIOD1_OUTPUT_DELAY_0 (0x0000U) /* no delay */ +#define _4000_TMRD_TRDIOD1_OUTPUT_DELAY_1 (0x4000U) /* delay 1 cycle */ +#define _8000_TMRD_TRDIOD1_OUTPUT_DELAY_2 (0x8000U) /* delay 2 cycles */ +#define _C000_TMRD_TRDIOD1_OUTPUT_DELAY_3 (0xC000U) /* delay 3 cycles */ + +/* + Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) +*/ +/* PWM mode output level control bit B (POLB) */ +#define _00_TMRD_TRDIOB_OUTPUT_ACTIVE_L (0x00U) /* "L" active TRDIOBi output level is selected */ +#define _01_TMRD_TRDIOB_OUTPUT_ACTIVE_H (0x01U) /* "H" active TRDIOBi output level is selected */ +/* PWM mode output level control bit C (POLC) */ +#define _00_TMRD_TRDIOC_OUTPUT_ACTIVE_L (0x00U) /* "L" active TRDIOCi output level is selected */ +#define _02_TMRD_TRDIOC_OUTPUT_ACTIVE_H (0x02U) /* "H" active TRDIOCi output level is selected */ +/* PWM mode output level control bit D (POLD) */ +#define _00_TMRD_TRDIOD_OUTPUT_ACTIVE_L (0x00U) /* "L" active TRDIODi output level is selected */ +#define _04_TMRD_TRDIOD_OUTPUT_ACTIVE_H (0x04U) /* "H" active TRDIODi output level is selected */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* 16-bit timer data register 00 (TDR00) */ +#define _7CFF_TAU_TDR00_VALUE (0x7CFFU) +/* Clock divisor for TAU0 channel 0 */ +#define _0001_TAU0_CHANNEL0_DIVISOR (0x0001U) +/* 16-bit timer data register 01 (TDR01) */ +#define _7CFF_TAU_TDR01_VALUE (0x7CFFU) +/* Clock divisor for TAU0 channel 1 */ +#define _0001_TAU0_CHANNEL1_DIVISOR (0x0001U) +/* 16-bit timer data register 04 (TDR04) */ +#define _7CFF_TAU_TDR04_VALUE (0x7CFFU) +/* 16-bit timer data register 05 (TDR05) */ +#define _3E80_TAU_TDR05_VALUE (0x3E80U) +/* Clock divisor for TAU0 channel 4 */ +#define _0001_TAU0_CHANNEL4_DIVISOR (0x0001U) +/* Clock divisor for TAU0 channel 5 */ +#define _0001_TAU0_CHANNEL5_DIVISOR (0x0001U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef enum +{ + TMCHANNELA, + TMCHANNELB, + TMCHANNELC, + TMCHANNELD, + TMCHANNELELC +} timer_channel_t; + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_TAU0_Create(void); +void R_TAU0_Channel0_Start(void); +void R_TAU0_Channel0_Stop(void); +void R_TAU0_Channel1_Start(void); +void R_TAU0_Channel1_Stop(void); +void R_TAU0_Channel4_Start(void); +void R_TAU0_Channel4_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_timer_user.c b/app/r_cg_timer_user.c new file mode 100644 index 0000000..be781be --- /dev/null +++ b/app/r_cg_timer_user.c @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_timer_user.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for TAU module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_timer.h" +/* Start user code for include. Do not edit comment generated here */ +#include "appTask.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_tau0_channel0_interrupt(vect=INTTM00) +#pragma interrupt r_tau0_channel1_interrupt(vect=INTTM01) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_tau0_channel0_interrupt +* Description : This function is INTTM00 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_tau0_channel0_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + Timer_Pro(); + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: r_tau0_channel1_interrupt +* Description : This function is INTTM01 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_tau0_channel1_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_userdefine.h b/app/r_cg_userdefine.h new file mode 100644 index 0000000..34d7811 --- /dev/null +++ b/app/r_cg_userdefine.h @@ -0,0 +1,39 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file includes user definition. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ + +/* Start user code for function. Do not edit comment generated here */ +#define RLIN_Master +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_wdt.c b/app/r_cg_wdt.c new file mode 100644 index 0000000..e1229cb --- /dev/null +++ b/app/r_cg_wdt.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_WDT_Create +* Description : This function initializes the watchdogtimer. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_WDT_Create(void) +{ + WDTIMK = 1U; /* disable INTWDTI interrupt */ + WDTIIF = 0U; /* clear INTWDTI interrupt flag */ + /* Set INTWDTI low priority */ + WDTIPR1 = 1U; + WDTIPR0 = 1U; + WDTIMK = 0U; /* enable INTWDTI interrupt */ +} + +/*********************************************************************************************************************** +* Function Name: R_WDT_Restart +* Description : This function restarts the watchdog timer. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_WDT_Restart(void) +{ + WDTE = 0xACU; /* restart watchdog timer */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_cg_wdt.h b/app/r_cg_wdt.h new file mode 100644 index 0000000..24cdeef --- /dev/null +++ b/app/r_cg_wdt.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt.h +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +#ifndef WDT_H +#define WDT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_WDT_Create(void); +void R_WDT_Restart(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/app/r_cg_wdt_user.c b/app/r_cg_wdt_user.c new file mode 100644 index 0000000..50abf75 --- /dev/null +++ b/app/r_cg_wdt_user.c @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_wdt_user.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements device driver for WDT module. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +#pragma interrupt r_wdt_interrupt(vect=INTWDTI) +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_wdt_interrupt +* Description : This function is INTWDTI interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void __near r_wdt_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_main.c b/app/r_main.c new file mode 100644 index 0000000..d7c190a --- /dev/null +++ b/app/r_main.c @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_main.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements main function. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_adc.h" +#include "r_cg_timer.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +#include "appTask.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +void R_MAIN_UserInit(void); + +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + value_init(); + while (1U) + { + Apply_task(); + } + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + + EI(); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/r_systeminit.c b/app/r_systeminit.c new file mode 100644 index 0000000..e2d182b --- /dev/null +++ b/app/r_systeminit.c @@ -0,0 +1,93 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_systeminit.c +* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021] +* Device(s) : R5F10AGF +* Tool-Chain : CCRL +* Description : This file implements system initializing function. +* Creation Date: 2024-01-08 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_adc.h" +#include "r_cg_timer.h" +#include "r_cg_wdt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Set periperal I/O redirection */ + PIOR0 = 0x00U; + PIOR1 = 0x20U; + PIOR4 = 0x00U; + PIOR5 = 0x00U; + PIOR7 = 0x00U; + R_CGC_Get_ResetSource(); + R_CGC_Create(); + R_PORT_Create(); + R_ADC_Create(); + R_TAU0_Create(); + R_WDT_Create(); + + /* Set invalid memory access detection control */ + IAWCTL = 0x00U; +} + + +/*********************************************************************************************************************** +* Function Name: hdwinit +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void hdwinit(void) +{ + DI(); + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/app/stkinit.asm b/app/stkinit.asm new file mode 100644 index 0000000..ed79566 --- /dev/null +++ b/app/stkinit.asm @@ -0,0 +1,77 @@ +;/********************************************************************************************************************** +; * DISCLAIMER +; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +; * applicable laws, including copyright laws. +; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO +; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +; * this software. By using this software, you agree to the additional terms and conditions found by accessing the +; * following link: +; * http://www.renesas.com/disclaimer +; * +; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +; *********************************************************************************************************************/;--------------------------------------------------------------------- +; _stkinit +; +; void _stkinit(void __near * stackbss); +; +; input: +; stackbss = AX (#LOWW(_stackend)) +; output: +; NONE +;--------------------------------------------------------------------- + +; NOTE : THIS IS A TYPICAL EXAMPLE. + + .PUBLIC _stkinit + +.textf .CSEG TEXTF +_stkinit: + MOVW HL,AX ; stack_end_addr + MOV [SP+3],#0x00 ; [SP+0]-[SP+2] for return address + MOVW AX,SP + SUBW AX,HL ; SUBW AX,#LOWW _@STEND + BNH $LSTINIT3 ; goto end + SHRW AX,5 ; loop count for 32 byte transfer + MOVW BC,AX + CLRW AX +LSTINIT1: + CMPW AX,BC + BZ $LSTINIT2 + MOVW [HL],AX + MOVW [HL+2],AX + MOVW [HL+4],AX + MOVW [HL+6],AX + MOVW [HL+8],AX + MOVW [HL+10],AX + MOVW [HL+12],AX + MOVW [HL+14],AX + MOVW [HL+16],AX + MOVW [HL+18],AX + MOVW [HL+20],AX + MOVW [HL+22],AX + MOVW [HL+24],AX + MOVW [HL+26],AX + MOVW [HL+28],AX + MOVW [HL+30],AX + XCHW AX,HL + ADDW AX,#0x20 + XCHW AX,HL + DECW BC + BR $LSTINIT1 +LSTINIT2: + MOVW AX,SP + CMPW AX,HL + BZ $LSTINIT3 ; goto end + CLRW AX + MOVW [HL],AX + INCW HL + INCW HL + BR $LSTINIT2 +LSTINIT3: + RET diff --git a/app/user/MotorCtrl.c b/app/user/MotorCtrl.c new file mode 100644 index 0000000..b172af8 --- /dev/null +++ b/app/user/MotorCtrl.c @@ -0,0 +1,900 @@ + +#include "MotorCtrl.h" + +#include "hwCtrl.h" +#include "PINdef.h" +#include "appTask.h" +#include "pfdl.h" + + +uint8_t MotorState[6],MotorStateReal[6]; +uint16_t MotorHallLoc[6],MotorHardStop1[6],MotorHardStop2[6]; +uint8_t MotorLearnState[6]; +uint8_t MotorErr[6]; +uint16_t current1,current2,current3; + +static uint8_t AutoCalState; + +uint8_t EEL_SAVE_REQUIRE_FLAG; +uint16_t EEL_SAVE_Counter; +#define OVMOTORKB 1 +#define OVMOTORZY 2 + +uint8_t OC1flag,OC2flag,OC3flag; + +typedef struct +{ + uint16_t MotorStopLoc1; + uint16_t MotorStopLoc2; + uint16_t MotorNowLoc; +}MOTOR_DATA; + +MOTOR_DATA MotorData[6]; +uint16_t MemoryLoc[3][6]; + +typedef struct +{ + uint16_t start_flag; + MOTOR_DATA MotorData[6]; + uint16_t MemoryLoc[3][6]; + uint16_t checksum; + uint16_t stop_flag; +}MEMORY_DATA; +MEMORY_DATA MemoryData; + +uint16_t GetCheckSum(uint16_t * addr,uint8_t len) +{ + uint16_t sum=0; + while (len --) + { + sum += *addr; + } + sum ^= 0xffff; + + return sum; +} +#define START_FLAG 0x55aa +#define STOP_FLAG 0xaa55 +void WriteMotorMemory(void) +{ + uint8_t i; + if (EEL_SAVE_REQUIRE_FLAG == 0 || EEL_SAVE_Counter > 0) + { + return; + } + + MemoryData.start_flag = START_FLAG; + MemoryData.stop_flag = STOP_FLAG; + for (i = 0; i < 6; i++) + { + MemoryData.MotorData[i].MotorNowLoc = MotorHallLoc[i]; + MemoryData.MotorData[i].MotorStopLoc1 = MotorHardStop1[i]; + MemoryData.MotorData[i].MotorStopLoc2 = MotorHardStop2[i]; + MemoryData.MemoryLoc[0][i] = MemoryLoc[0][i]; + MemoryData.MemoryLoc[1][i] = MemoryLoc[1][i]; + MemoryData.MemoryLoc[2][i] = MemoryLoc[2][i]; + } + + + MemoryData.checksum = GetCheckSum(&MemoryData.MotorData[0].MotorStopLoc1,36); + if(WriteDataflash(&MemoryData,0x000F1000,sizeof(MemoryData)) == 0x11) + { + EEL_SAVE_REQUIRE_FLAG=0; + } +} + + +void ReadMotorMemory(void) +{ + uint16_t checksum; + uint8_t i; + ReadFlashData(&MemoryData,0x000F1000,sizeof(MemoryData)); + checksum = GetCheckSum(&MemoryData.MotorData[0].MotorStopLoc1,36); + if (MemoryData.start_flag == START_FLAG && MemoryData.stop_flag == STOP_FLAG && checksum == MemoryData.checksum)// + { + for (i = 0; i < 6; i++) + { + MotorHallLoc[i] = MemoryData.MotorData[i].MotorNowLoc; + MotorHardStop1[i] = MemoryData.MotorData[i].MotorStopLoc1; + MotorHardStop2[i] = MemoryData.MotorData[i].MotorStopLoc2; + MemoryLoc[0][i] = MemoryData.MemoryLoc[0][i]; + MemoryLoc[1][i] = MemoryData.MemoryLoc[1][i]; + MemoryLoc[2][i] = MemoryData.MemoryLoc[2][i]; + } + + } + else + { + for (i = 0; i < 6; i++) + { + MotorHallLoc[i] = 0x8000; + MotorHardStop1[i] = 0; + MotorHardStop2[i] = 0; + MemoryLoc[0][i] = 0; + MemoryLoc[1][i] = 0; + MemoryLoc[2][i] = 0; + } + + } +} + + +void MotorValueInit(void) +{ + uint8_t i; + for (i = 0; i < 6; i++) + { + MotorHallLoc[i] = 0x8000; + MotorErr[i] = 0; + } + //ReadMotorMemory(); +} + +void setMotorState(uint8_t motorid,uint8_t act) +{ + //motorid-=1; + if (act <= ACT_XH && motorid < 6) + { + MotorState[motorid] = act; + } +} +uint16_t MotorTarget[6] = {0}; +void setMotorTarget(uint8_t motorid,uint16_t target) +{ + + MotorTarget[motorid] = target; +} + + + + +#define AUTOCAL_STOP 0 +#define AUTOCAL_START 1 +#define AUTOCAL_ACT1 2 +#define AUTOCAL_ACT2 3 +#define AUTOCAL_END 4 + +void StartAutoCal(void) +{ + AutoCalState = AUTOCAL_START; + +} +void StopAutoCal(void) +{ + if (AutoCalState != AUTOCAL_STOP) + { + AutoCalState = AUTOCAL_STOP; + setMotorState(MOTOR1,ACT_NOACT); + setMotorState(MOTOR2,ACT_NOACT); + setMotorState(MOTOR3,ACT_NOACT); + setMotorState(MOTOR4,ACT_NOACT); + setMotorState(MOTOR5,ACT_NOACT); + setMotorState(MOTOR6,ACT_NOACT); + } +} + + + +void AutoCalCtrl(void) +{ + static uint16_t autocalcounter[3]; + static uint8_t MotorArr1state,MotorArr2state,MotorArr3state; + static uint8_t wait1,wait2,wait3; + uint8_t i; + uint32_t temp; + switch (AutoCalState) + { + case AUTOCAL_STOP: + MotorArr1state = AUTOCAL_STOP; + MotorArr2state = AUTOCAL_STOP; + MotorArr3state = AUTOCAL_STOP; + return; + case AUTOCAL_START: + MotorArr1state = 1; + MotorArr2state = 1; + MotorArr3state = 1; + setMotorState(MOTOR1,ACT_XQ); + setMotorState(MOTOR3,ACT_XQ); + setMotorState(MOTOR5,ACT_XQ); + autocalcounter[0] = 0; + autocalcounter[1] = 0; + autocalcounter[2] = 0; + AutoCalState++; + for (i = 0; i < 6; i++) + { + MotorHardStop1[i] = 0; + MotorHardStop2[i] = 0; + MotorHallLoc[i] = 0x8000; + } + break; + case AUTOCAL_ACT1: + if (MotorArr1state == 0 && MotorArr2state == 0 && MotorArr3state == 0) + { + for (i = 0; i < 6; i++) + { + temp = MotorHardStop1[i]; + temp += MotorHardStop2[i]; + setMotorTarget(i,temp/2); + } + + } + + + + break; + case AUTOCAL_ACT2: + + break; + + default: + break; + } + //1 + switch (MotorArr1state) + { + case 1://motor1 xq + autocalcounter[0]++; + if (MotorHardStop1[MOTOR1] != 0) + { + MotorArr1state++; + wait1 = 0; + setMotorState(MOTOR1,ACT_NOACT); + } + if (autocalcounter[0] > 3000 || MotorErr[MOTOR1] != 0) + { + MotorArr1state = 4; + wait1 = 0; + setMotorState(MOTOR1,ACT_NOACT); + } + break; + case 2://wait + wait1++; + if (wait1 > 50) + { + MotorArr1state++; + setMotorState(MOTOR1,ACT_XH); + autocalcounter[0] = 0; + } + break; + case 3://motor1 xh + autocalcounter[0]++; + if (MotorHardStop2[MOTOR1] != 0) + { + MotorArr1state++; + wait1 = 0; + setMotorState(MOTOR1,ACT_NOACT); + } + if (autocalcounter[0] > 3000 || MotorErr[MOTOR1] != 0) + { + MotorArr1state = 4; + wait1 = 0; + setMotorState(MOTOR1,ACT_NOACT); + } + break; + case 4://wait + wait1++; + if (wait1 > 50) + { + MotorArr1state++; + setMotorState(MOTOR2,ACT_XQ); + autocalcounter[0] = 0; + } + break; + case 5://motor2 xq + autocalcounter[0]++; + if (MotorHardStop1[MOTOR2] != 0) + { + MotorArr1state++; + wait1 = 0; + setMotorState(MOTOR2,ACT_NOACT); + } + if (autocalcounter[0] > 3000 || MotorErr[MOTOR2] != 0) + { + MotorArr1state = 0; + setMotorState(MOTOR2,ACT_NOACT); + } + break; + case 6://wait + wait1++; + if (wait1 > 50) + { + MotorArr1state++; + setMotorState(MOTOR2,ACT_XH); + autocalcounter[0] = 0; + } + break; + case 7: + autocalcounter[0]++; + if (MotorHardStop2[MOTOR2] != 0) + { + MotorArr1state=0; + wait1 = 0; + setMotorState(MOTOR2,ACT_NOACT); + } + if (autocalcounter[0] > 3000 || MotorErr[MOTOR2] != 0) + { + MotorArr1state = 0; + setMotorState(MOTOR2,ACT_NOACT); + } + break; + default: + break; + } + + //2 + switch (MotorArr2state) + { + case 1://motor3 xq + autocalcounter[1]++; + if (MotorHardStop1[MOTOR3] != 0) + { + MotorArr2state++; + wait2 = 0; + setMotorState(MOTOR3,ACT_NOACT); + } + if (autocalcounter[1] > 3000 || MotorErr[MOTOR3] != 0) + { + MotorArr2state = 4; + wait2 = 0; + setMotorState(MOTOR3,ACT_NOACT); + } + break; + case 2://wait + wait2++; + if (wait2 > 50) + { + MotorArr2state++; + setMotorState(MOTOR3,ACT_XH); + autocalcounter[1] = 0; + } + break; + case 3://motor3 xh + autocalcounter[1]++; + if (MotorHardStop2[MOTOR3] != 0) + { + MotorArr2state++; + wait2 = 0; + setMotorState(MOTOR3,ACT_NOACT); + } + if (autocalcounter[1] > 3000 || MotorErr[MOTOR3] != 0) + { + MotorArr2state = 4; + wait2 = 0; + setMotorState(MOTOR3,ACT_NOACT); + } + break; + case 4://wait + wait2++; + if (wait2 > 50) + { + MotorArr2state++; + setMotorState(MOTOR4,ACT_XQ); + autocalcounter[1] = 0; + } + break; + case 5://motor4 xq + autocalcounter[1]++; + if (MotorHardStop1[MOTOR4] != 0) + { + MotorArr2state++; + wait2 = 0; + setMotorState(MOTOR4,ACT_NOACT); + } + if (autocalcounter[1] > 3000 || MotorErr[MOTOR4] != 0) + { + MotorArr2state = 0; + setMotorState(MOTOR4,ACT_NOACT); + } + break; + case 6://wait + wait2++; + if (wait2 > 50) + { + MotorArr2state++; + setMotorState(MOTOR4,ACT_XH); + autocalcounter[1] = 0; + } + break; + case 7: + autocalcounter[1]++; + if (MotorHardStop2[MOTOR4] != 0) + { + MotorArr2state=0; + wait2 = 0; + setMotorState(MOTOR4,ACT_NOACT); + } + if (autocalcounter[1] > 3000 || MotorErr[MOTOR4] != 0) + { + MotorArr2state = 0; + setMotorState(MOTOR4,ACT_NOACT); + } + break; + default: + break; + } + switch (MotorArr3state) + { + case 1://motor5 xq + autocalcounter[2]++; + if (MotorHardStop1[MOTOR5] != 0) + { + MotorArr3state++; + wait3 = 0; + setMotorState(MOTOR5,ACT_NOACT); + } + if (autocalcounter[2] > 3000 || MotorErr[MOTOR5] != 0) + { + MotorArr3state = 4; + wait3 = 0; + setMotorState(MOTOR5,ACT_NOACT); + } + break; + case 2://wait + wait3++; + if (wait3 > 50) + { + MotorArr3state++; + setMotorState(MOTOR5,ACT_XH); + autocalcounter[2] = 0; + } + break; + case 3://motor5 xh + autocalcounter[2]++; + if (MotorHardStop2[MOTOR5] != 0) + { + MotorArr3state++; + wait3 = 0; + setMotorState(MOTOR5,ACT_NOACT); + } + if (autocalcounter[2] > 3000 || MotorErr[MOTOR5] != 0) + { + MotorArr3state = 4; + wait3 = 0; + setMotorState(MOTOR5,ACT_NOACT); + } + break; + case 4://wait + wait3++; + if (wait3 > 50) + { + MotorArr3state++; + setMotorState(MOTOR6,ACT_XQ); + autocalcounter[2] = 0; + } + break; + case 5://motor6 xq + autocalcounter[2]++; + if (MotorHardStop1[MOTOR6] != 0) + { + MotorArr3state++; + wait3 = 0; + setMotorState(MOTOR6,ACT_NOACT); + } + if (autocalcounter[2] > 3000 || MotorErr[MOTOR6] != 0) + { + MotorArr3state = 0; + setMotorState(MOTOR6,ACT_NOACT); + } + break; + case 6://wait + wait3++; + if (wait3 > 50) + { + MotorArr3state++; + setMotorState(MOTOR6,ACT_XH); + autocalcounter[2] = 0; + } + break; + case 7: + autocalcounter[2]++; + if (MotorHardStop2[MOTOR6] != 0) + { + MotorArr3state=0; + wait3 = 0; + setMotorState(MOTOR6,ACT_NOACT); + } + if (autocalcounter[2] > 3000 || MotorErr[MOTOR6] != 0) + { + MotorArr3state = 0; + setMotorState(MOTOR6,ACT_NOACT); + } + break; + default: + break; + } +} +uint8_t flagMotorMemoryKeyStart,flagMotorMemoryKeyLongPress,flagKEYM1press; +uint16_t countMotorMemoryKeyStart; +uint16_t countMotorMemoryKeyLongPress; +void MotorMemoryKeyMMPress(void) +{ + + flagMotorMemoryKeyLongPress = 1; + + countMotorMemoryKeyLongPress = 0; +} + +void MotorMemoryKeyMMRelease(void) +{ + if (countMotorMemoryKeyLongPress >= 300) + { + flagMotorMemoryKeyLongPress = 2; + countMotorMemoryKeyLongPress = 500; + flagKEYM1press = 0; + } + else + { + flagMotorMemoryKeyStart = 1; + countMotorMemoryKeyStart = 0; + flagMotorMemoryKeyLongPress = 0; + countMotorMemoryKeyLongPress = 0; + + } +} + +void MotorMemoryKeyM1Press(void) +{ + +} +void MotorMemoryKeyM1Release(void) +{ + uint8_t i; + if (flagMotorMemoryKeyLongPress == 2) + { + flagKEYM1press++; + if (flagKEYM1press >= 3) + { + StartAutoCal(); + } + + } + if (flagMotorMemoryKeyStart == 1) + { + flagMotorMemoryKeyStart = 0; + for (i = 0; i < 6; i++) + { + + if (MotorHardStop1[i]!=0 && MotorHardStop2[i]!=0) + { + MemoryLoc[0][i] = MotorHallLoc[i]; + } + EEL_SAVE_Counter = 1000; + EEL_SAVE_REQUIRE_FLAG = 1; + } + } + else + { + for (i = 0; i < 6; i++) + { + setMotorTarget(i,MemoryLoc[0][i]); + } + } +} + +void MotorMemoryKeyM2Press(void) +{ + +} +void MotorMemoryKeyM2Release(void) +{ + uint8_t i; + if (flagMotorMemoryKeyStart == 1) + { + flagMotorMemoryKeyStart = 0; + for (i = 0; i < 6; i++) + { + if (MotorHardStop1[i]!=0 && MotorHardStop2[i]!=0) + { + MemoryLoc[1][i] = MotorHallLoc[i]; + } + } + EEL_SAVE_Counter = 1000; + EEL_SAVE_REQUIRE_FLAG = 1; + } + else + { + for (i = 0; i < 6; i++) + { + setMotorTarget(i,MemoryLoc[1][i]); + } + } +} + +void MotorMemoryKeyM3Press(void) +{ + +} +void MotorMemoryKeyM3Release(void) +{ + uint8_t i; + if (flagMotorMemoryKeyStart == 1) + { + flagMotorMemoryKeyStart = 0; + for (i = 0; i < 6; i++) + { + if (MotorHardStop1[i]!=0 && MotorHardStop2[i]!=0) + { + MemoryLoc[2][i] = MotorHallLoc[i]; + } + } + EEL_SAVE_Counter = 1000; + EEL_SAVE_REQUIRE_FLAG = 1; + } + else + { + for (i = 0; i < 6; i++) + { + setMotorTarget(i,MemoryLoc[2][i]); + } + } + +} + +void MotorCtrl(void)//10ms +{ + uint8_t i; + //WriteMotorMemory(); //TODO + AutoCalCtrl(); + if (flagMotorMemoryKeyStart == 1) + { + countMotorMemoryKeyStart++; + if (countMotorMemoryKeyStart > 500)//5S + { + flagMotorMemoryKeyStart = 0; + countMotorMemoryKeyStart = 0; + } + } + if (flagMotorMemoryKeyLongPress == 1 && countMotorMemoryKeyLongPress < 1000) + { + countMotorMemoryKeyLongPress++; + } + if (flagMotorMemoryKeyLongPress == 2 && countMotorMemoryKeyLongPress > 0) + { + countMotorMemoryKeyLongPress--; + if (countMotorMemoryKeyLongPress == 0) + { + flagMotorMemoryKeyLongPress = 0; + } + + } + + + + + if (OC1flag == 1) + { + OC1flag = 0; + if (MotorState[0] == ACT_XQ) + { + MotorHardStop1[0] = MotorHallLoc[0]; + } + else if (MotorState[0] == ACT_XH) + { + MotorHardStop2[0] = MotorHallLoc[0]; + } + else if (MotorState[1] == ACT_XQ) + { + MotorHardStop1[1] = MotorHallLoc[1]; + } + else if (MotorState[1] == ACT_XH) + { + MotorHardStop2[1] = MotorHallLoc[1]; + } + MotorState[MOTOR1] = ACT_NOACT; + MotorState[MOTOR2] = ACT_NOACT; + } + if (OC2flag == 1) + { + OC2flag = 0; + if (MotorState[2] == ACT_XQ) + { + MotorHardStop1[2] = MotorHallLoc[2]; + } + else if (MotorState[2] == ACT_XH) + { + MotorHardStop2[2] = MotorHallLoc[2]; + } + else if (MotorState[3] == ACT_XQ) + { + MotorHardStop1[3] = MotorHallLoc[3]; + } + else if (MotorState[3] == ACT_XH) + { + MotorHardStop2[3] = MotorHallLoc[3]; + } + MotorState[MOTOR3] = ACT_NOACT; + MotorState[MOTOR4] = ACT_NOACT; + } + if (OC3flag == 1) + { + OC3flag = 0; + if (MotorState[4] == ACT_XQ) + { + MotorHardStop1[4] = MotorHallLoc[4]; + } + else if (MotorState[4] == ACT_XH) + { + MotorHardStop2[4] = MotorHallLoc[4]; + } + else if (MotorState[5] == ACT_XQ) + { + MotorHardStop1[5] = MotorHallLoc[5]; + } + else if (MotorState[5] == ACT_XH) + { + MotorHardStop2[5] = MotorHallLoc[5]; + } + MotorState[MOTOR5] = ACT_NOACT; + MotorState[MOTOR6] = ACT_NOACT; + } + + for (i = 0; i < 6; i++) + { + MotorStateReal[i] = MotorState[i]; + if (MotorState[i] == ACT_NOACT && MotorHardStop1[i] != 0 && MotorHardStop2[i] != 0 ) + { + if (MotorTarget[i]!=0 && MotorHardStop1[i] > MotorTarget[i] && MotorTarget[i] > MotorHardStop2[i]) + { + if (MotorTarget[i] > MotorHallLoc[i]+10) + { + MotorStateReal[i] = ACT_XQ; + } + else if (MotorTarget[i] < MotorHallLoc[i]-10) + { + MotorStateReal[i] = ACT_XH; + } + else + { + MotorTarget[i] = 0; + } + } + + } + else if (MotorHardStop1[i] != 0 && MotorHardStop2[i] != 0) + { + if (MotorHallLoc[i] > (MotorHardStop1[i]-20) && MotorStateReal[i] == ACT_XQ) + { + MotorStateReal[i] = ACT_NOACT; + } + if (MotorHallLoc[i] < (MotorHardStop2[i] + 20) && MotorStateReal[i] == ACT_XH) + { + MotorStateReal[i] = ACT_NOACT; + } + + } + + else + { + MotorTarget[i] = 0; + } + } + + MOTOR1Ctrl(MotorStateReal[MOTOR1]); + MOTOR2Ctrl(MotorStateReal[MOTOR2]); + MOTOR3Ctrl(MotorStateReal[MOTOR3]); + MOTOR4Ctrl(MotorStateReal[MOTOR4]); + MOTOR5Ctrl(MotorStateReal[MOTOR5]); + MOTOR6Ctrl(MotorStateReal[MOTOR6]); +} + + + +#define OC_10A 100 +#define OC_500mS 500 +#define OC_50mS 50 + + + +void CurrentDetecte(void) +{ + + static uint16_t OC_Count1=0,OC_Count2=0,OC_Count3 = 0; + + current1 = getAdval(ADCH_RLY3); + current2 = getAdval(ADCH_RLY2); + current3 = getAdval(ADCH_RLY1); + + if (current1 > 100U && OC1flag == 0) + { + OC_Count1++; + if (OC_Count1 >= 100) + { + OC_Count1 = 0; + OC1flag = 1; + } + } + else + { + OC_Count1 = 0; + } + + if (current2 > 100U && OC2flag == 0) + { + OC_Count2++; + if (OC_Count2 >= 100) + { + OC_Count2 = 0; + OC2flag = 1; + } + + } + else + { + OC_Count2 = 0; + } + + if (current3 > 100U && OC3flag == 0) + { + OC_Count3++; + if (OC_Count3 >= 100) + { + OC_Count3 = 0; + OC3flag = 1; + } + + } + else + { + OC_Count3 = 0; + } + +} + +void OverCurrentPro(uint8_t ovmotor) +{ + +} + +#define HALLDELAYMAX 2 + +uint16_t HallErrorCount[6]; +void HallDetecte(void) +{ + static uint8_t HallLastState[6],HallDelay[6]; + uint8_t i,hallstate; + for (i = 0; i < 6; i++) + { + hallstate = GetIOState(i+1); + if (hallstate != HallLastState[i]) + { + HallDelay[i]++; + if (HallDelay[i] > HALLDELAYMAX) + { + if (MotorStateReal[i] == ACT_XQ) + { + MotorHallLoc[i]++; + } + else if (MotorStateReal[i] == ACT_XH) + { + MotorHallLoc[i]--; + } + HallLastState[i] = hallstate; + } + HallErrorCount[i] = 0; + MotorErr[i] = 0; + EEL_SAVE_Counter = 1000; + EEL_SAVE_REQUIRE_FLAG = 1; + } + else + { + HallDelay[i] = 0; + if (MotorStateReal[i] != ACT_NOACT) + { + HallErrorCount[i]++; + if (HallErrorCount[i] > 500) + { + HallErrorCount[i] = 500; + MotorErr[i] = 1; + } + + } + + } + } + + if (EEL_SAVE_Counter > 0) + { + EEL_SAVE_Counter--; + } + +} diff --git a/app/user/MotorCtrl.h b/app/user/MotorCtrl.h new file mode 100644 index 0000000..7e3a7a8 --- /dev/null +++ b/app/user/MotorCtrl.h @@ -0,0 +1,37 @@ +#ifndef __MOTORCTRL_H__ +#define __MOTORCTRL_H__ + +#include "r_cg_macrodriver.h" + +#define MOTOR1 0 +#define MOTOR2 1 +#define MOTOR3 2 +#define MOTOR4 3 +#define MOTOR5 4 +#define MOTOR6 5 + +void OverCurrentPro(uint8_t ovmotor); +void CurrentDetecte(void); +void MotorCtrl(void); +void HallDetecte(void); +void MotorValueInit(void); + + +void StartAutoCal(void); +void StopAutoCal(void); + + + + +void setMotorState(uint8_t motorid,uint8_t act); + +void MotorMemoryKeyM1Press(void); +void MotorMemoryKeyM1Release(void); +void MotorMemoryKeyM2Press(void); +void MotorMemoryKeyM2Release(void); +void MotorMemoryKeyM3Press(void); +void MotorMemoryKeyM3Release(void); +void MotorMemoryKeyMMPress(void); +void MotorMemoryKeyMMRelease(void); + +#endif diff --git a/app/user/PINdef.h b/app/user/PINdef.h new file mode 100644 index 0000000..e4479b4 --- /dev/null +++ b/app/user/PINdef.h @@ -0,0 +1,70 @@ +#ifndef __PINDEF_H__ +#define __PINDEF_H__ + +#include "iodefine.h" + + + + + +#define KEYID_KBXQ 0 +#define KEYID_KBXH 1 +#define KEYID_HGXQ 2 +#define KEYID_HGXH 3 +#define KEYID_ZDUP 4 +#define KEYID_ZDDOWN 5 +#define KEYID_TTUP 6 +#define KEYID_TTDOWN 7 +#define KEYID_TP 8 +#define KEYID_FW 9 +#define KEYID_SET 10 +#define KEYID_M1 11 +#define KEYID_M2 12 +#define KEYID_M3 13 + +#define SIGID_HALL1 14 +#define SIGID_HALL2 15 +#define SIGID_HALL3 16 +#define SIGID_HALL4 17 + + + +#define IN_HALL1 P6_bit.no0 +#define IN_HALL2 P6_bit.no1 +#define IN_HALL3 P6_bit.no2 +#define IN_HALL4 P6_bit.no3 + +#define IN_KEY_KBXH P8_bit.no2 +#define IN_KEY_HGXH P8_bit.no3 +#define IN_KEY_ZDDOWN P8_bit.no4 +#define IN_KEY_TTDOWN P8_bit.no5 +#define IN_KEY_TTUP P8_bit.no6 +#define IN_KEY_ZDUP P8_bit.no7 +#define IN_KEY_HGXQ P9_bit.no1 +#define IN_KEY_KBXQ P9_bit.no2 +#define IN_KEY_TP P12_bit.no5 +#define IN_KEY_FW P12_bit.no0 + + +#define OUT_RLY1P P3_bit.no0//KB +#define OUT_RLY1N P14_bit.no0 +#define OUT_RLY2P P7_bit.no0//HG +#define OUT_RLY2N P3_bit.no2 +#define OUT_RLY3P P13_bit.no0//ZD +#define OUT_RLY3N P7_bit.no1 +#define OUT_RLY4P P7_bit.no2//TT +#define OUT_RLY4N P7_bit.no3 + + + + + +#define ADCH_JYKEY 3 +#define ADCH_RLY2 0 +#define ADCH_RLY1 2 +#define ADCH_BAT 1 + + + +#endif + diff --git a/app/user/appTask.c b/app/user/appTask.c new file mode 100644 index 0000000..cc304ed --- /dev/null +++ b/app/user/appTask.c @@ -0,0 +1,424 @@ +/** + * @file appTask.c + * @author sunbeam + * @brief + * @version 0.1 + * @date 2023-11-14 + * + * @copyright Copyright (c) 2023 + * + */ + +#include "appTask.h" +#include "iodefine.h" +#include "r_cg_adc.h" +#include "PINdef.h" +#include "hwCtrl.h" +#include "MotorCtrl.h" +#include "RLIN_driver.h" +#include "r_cg_wdt.h" +#include "r_cg_timer.h" + +static uint8_t EEL_BUF[50]; + +unsigned char IGN_Voltage_error_flag, IGN_Voltage_error_count; + +unsigned char Timer_1ms_flag; +unsigned char Timer_5ms_flag; +unsigned char Timer_10ms_flag; +unsigned char Timer_20ms_flag; +unsigned char Timer_50ms_flag; +unsigned char Timer_1000ms_flag; + +/***************************************************/ +static unsigned int EEL_SAVE_CNT_DOWN_TIMER; +static uint8_t EEL_SAVE_ENABLE; + +MotorStateEE_Type MotorStateEE; +MotorStateEE_Type *pEE; + + +void MotorCtrl(void); +void HallDetecte(void); +void LIN_Task(void); +void TfJr_CtrlTask(void); +extern uint8_t OC1flag,OC2flag,OC3flag; +uint8_t TfState,JrState; +unsigned char keybyte1,keybyte2,keybyte3; + +void Apply_task(void) +{ + //static uint8_t temp; + + if (Timer_1ms_flag == 1) + { + Timer_1ms_flag = 0; + KeyScan(); + HallDetecte(); + CurrentDetecte(); + if (EEL_SAVE_CNT_DOWN_TIMER > 0) + { + EEL_SAVE_CNT_DOWN_TIMER--; + } + } + if (Timer_5ms_flag == 1) + { + Timer_5ms_flag = 0; + + KeyPro(); + } + + if (Timer_10ms_flag == 1) + { + Timer_10ms_flag = 0; + MotorCtrl(); + LIN_Task(); + } + if (Timer_20ms_flag == 1) + { + Timer_20ms_flag = 0; + //R_WDT_Restart(); + } + if (Timer_50ms_flag == 1) + { + Timer_50ms_flag = 0; + TfJr_CtrlTask(); + } + if (Timer_1000ms_flag == 1) + { + Timer_1000ms_flag = 0; + //temp = !temp; + //MOTOR1Ctrl(temp); + } + +} +extern uint8_t Master_TxData1[]; +void LIN_Task(void) +{ + static uint8_t lin_sch_count=0; + switch (lin_sch_count) + { + case 0: + Master_TxData1[0] = (JrState<<4)|(TfState<<6); + Master_TxData1[1] = keybyte3; + RLIN_Master_HeaderTransmit(0x80); + break; + case 1: + RLIN_Master_HeaderTransmit(0x99); + break; + case 2: + RLIN_Master_HeaderTransmit(0x61); + break; + case 3: + break; + default: + lin_sch_count = 0; + break; + } + lin_sch_count++; + if (lin_sch_count > 2) + { + lin_sch_count = 0; + } + +} + +void LIN_Rx_Handle(uint8_t pid,uint8_t *data) +{ + uint8_t id = pid & 0x3f; + switch (id) + { + case 0x21: + keybyte3 = data[4]; + break; + case 0x19: + //MOTOR1Ctrl(1); + keybyte1 = data[0]; + keybyte2 = data[1]; + break; + default: + break; + } +} + + +void KeyPressLogic(uint8_t keyid) +{ + switch (keyid) + { + case KEYID_MOTOR1_XQ: + setMotorState(MOTOR1,ACT_XQ); + break; + case KEYID_MOTOR1_XH: + setMotorState(MOTOR1,ACT_XH); + break; + case KEYID_MOTOR2_XQ: + setMotorState(MOTOR2,ACT_XQ); + break; + case KEYID_MOTOR2_XH: + setMotorState(MOTOR2,ACT_XH); + break; + case KEYID_MOTOR3_XQ: + setMotorState(MOTOR3,ACT_XQ); + break; + case KEYID_MOTOR3_XH: + setMotorState(MOTOR3,ACT_XH); + break; + case KEYID_MOTOR4_XQ: + setMotorState(MOTOR4,ACT_XQ); + break; + case KEYID_MOTOR4_XH: + setMotorState(MOTOR4,ACT_XH); + break; + case KEYID_MOTOR5_XQ: + setMotorState(MOTOR5,ACT_XQ); + break; + case KEYID_MOTOR5_XH: + setMotorState(MOTOR5,ACT_XH); + break; + case KEYID_MOTOR6_XQ: + setMotorState(MOTOR6,ACT_XQ); + break; + case KEYID_MOTOR6_XH: + setMotorState(MOTOR6,ACT_XH); + break; + case KEYID_MM: + MotorMemoryKeyMMPress(); + break; + case KEYID_M1: + break; + case KEYID_M2: + break; + case KEYID_M3: + break; + case KEYID_K4: + JrState++; + TfState = 0; + if (JrState > 3) + { + JrState = 0; + } + + break; + case KEYID_K3: + TfState++; + JrState = 0; + if (TfState > 3) + { + TfState = 0; + } + break; + case KEYID_K2: + break; + case KEYID_K1: + break; + default: + break; + } +} + +void KeyReleaseLogic(uint8_t keyid) +{ + switch (keyid) + { + case KEYID_MOTOR1_XQ: + setMotorState(MOTOR1,ACT_NOACT); + break; + case KEYID_MOTOR1_XH: + setMotorState(MOTOR1,ACT_NOACT); + break; + case KEYID_MOTOR2_XQ: + setMotorState(MOTOR2,ACT_NOACT); + break; + case KEYID_MOTOR2_XH: + setMotorState(MOTOR2,ACT_NOACT); + break; + case KEYID_MOTOR3_XQ: + setMotorState(MOTOR3,ACT_NOACT); + break; + case KEYID_MOTOR3_XH: + setMotorState(MOTOR3,ACT_NOACT); + break; + case KEYID_MOTOR4_XQ: + setMotorState(MOTOR4,ACT_NOACT); + break; + case KEYID_MOTOR4_XH: + setMotorState(MOTOR4,ACT_NOACT); + break; + case KEYID_MOTOR5_XQ: + setMotorState(MOTOR5,ACT_NOACT); + break; + case KEYID_MOTOR5_XH: + setMotorState(MOTOR5,ACT_NOACT); + break; + case KEYID_MOTOR6_XQ: + setMotorState(MOTOR6,ACT_NOACT); + break; + case KEYID_MOTOR6_XH: + setMotorState(MOTOR6,ACT_NOACT); + break; + case KEYID_MM: + MotorMemoryKeyMMRelease(); + break; + case KEYID_M1: + MotorMemoryKeyM1Release(); + break; + case KEYID_M2: + MotorMemoryKeyM2Release(); + break; + case KEYID_M3: + MotorMemoryKeyM3Release(); + break; + default: + break; + } +} + + +void KeyPro(void) +{ + uint8_t keyid; + for (keyid = 0; keyid < KEY_NUM; keyid++) + { + if (getKeyPressFlag(keyid)) + { + KeyPressLogic(keyid+1); + StopAutoCal(); + } + if (getKeyReleaseFlag(keyid)) + { + KeyReleaseLogic(keyid+1); + } + + } + +} + + + + +void EEL_READ(void) +{ + uint16_t checksum; + uint8_t *src,*des,i; + //ReadFlashData(EEL_BUF, 0x000F1000, sizeof(MotorStateEE)); + pEE = (MotorStateEE_Type *)EEL_BUF; + checksum = pEE->kbsoft1 + pEE->kbsoft2 + pEE->kbnow + pEE->zysoft1 + pEE->zysoft2 + pEE->zynow; + if (pEE ->start == 0x55AA && pEE->stop == 0xAA55 && checksum == pEE->checksum) + { + des = &MotorStateEE; + src = EEL_BUF; + for (i = 0; i < sizeof(MotorStateEE); i++) + { + des[i] = src[i]; + } + } + +} + + + +uint16_t SupplyVoltage; +void IGN_Voltage_Detect(void) +{ + uint32_t adval; + adval = getAdval(ADCH_BAT); + SupplyVoltage = (adval*57*5)>>10; + if (adval <= 305 ) + { + IGN_Voltage_error_count++; + if (IGN_Voltage_error_count >= 250) + { + IGN_Voltage_error_count = 0; + IGN_Voltage_error_flag = 1; + } + } + else if (adval >= 592 )//16.5 + { + IGN_Voltage_error_count++; + if (IGN_Voltage_error_count >= 250) + { + IGN_Voltage_error_count = 0; + IGN_Voltage_error_flag = 2; + } + } + else if (adval >= 323 && adval <= 574) + { + IGN_Voltage_error_count = 0; + IGN_Voltage_error_flag = 0; + } + + + if (IGN_Voltage_error_flag != 0) + { + // TAU0_Channel1_ChangeDuty(0); + } +} + + +void value_init(void) +{ + R_TAU0_Channel0_Start(); + R_TAU0_Channel2_Start(); + + R_ADC_Start(); + R_ADC_Set_OperationOn(); + R_TMR_RJ0_Start(); + + + MotorValueInit(); + +} + + + +void Timer_Pro(void) +{ + static unsigned int Timer_1ms_tick_count; + Timer_1ms_tick_count++; + Timer_1ms_flag=1; + if(Timer_1ms_tick_count%5==0) + { + Timer_5ms_flag=1; + } + if(Timer_1ms_tick_count%10==0) + { + Timer_10ms_flag=1; + } + if(Timer_1ms_tick_count%20==0) + { + Timer_20ms_flag=1; + } + if(Timer_1ms_tick_count%50==0) + { + Timer_50ms_flag=1; + } + if(Timer_1ms_tick_count%1000==0) + { + Timer_1000ms_flag = 1; + } + if(Timer_1ms_tick_count>=5000) + { + Timer_1ms_tick_count=0; + } +} + + +const uint8_t TfDutyTable[4] = {0,100,80,50};//{0,100,80,50}; +const uint8_t JrDutyTable[4] = {0,100,80,50};//{0,100,80,50}; +void TfJr_CtrlTask(void) +{ + if (JrState < 4) + { + SetJrDuty(JrDutyTable[JrState]); + } + if (TfState < 4) + { + SetTfDuty(TfDutyTable[TfState]); + } + +} + + + + diff --git a/app/user/appTask.h b/app/user/appTask.h new file mode 100644 index 0000000..07b3356 --- /dev/null +++ b/app/user/appTask.h @@ -0,0 +1,43 @@ +#ifndef _DMK_VF12_03_H +#define _DMK_VF12_03_H + + +#include "r_cg_macrodriver.h" + +#include "r_cg_userdefine.h" + + + +/***********************************************/ +typedef struct{ + unsigned int start; + unsigned int zysoft1; + unsigned int zysoft2; + unsigned int zynow; + unsigned int kbsoft1; + unsigned int kbsoft2; + unsigned int kbnow; + unsigned int checksum; + unsigned int stop; +}MotorStateEE_Type; +extern MotorStateEE_Type MotorStateEE; + + +extern unsigned int EEL_SAVE_CNT_DOWN_TIMER; + + +extern unsigned char Timer_1ms_flag; +extern unsigned char Timer_5ms_flag; +extern unsigned char Timer_10ms_flag; +extern unsigned char Timer_20ms_flag; +extern unsigned char Timer_50ms_flag; +extern unsigned char Timer_1000ms_flag; + +void KeyPro(void); +void value_init(void); +void Timer_Pro(void); +void Apply_task(void); +void EEL_READ(void); +void IGN_Voltage_Detect(void); + +#endif \ No newline at end of file diff --git a/app/user/buzzer.c b/app/user/buzzer.c new file mode 100644 index 0000000..b653d75 --- /dev/null +++ b/app/user/buzzer.c @@ -0,0 +1,28 @@ + + +#include "buzzer.h" + +void buzzer_init(void) +{ + + +} + + + +void buzzer_start(void) +{ + +} + +void buzzer_stop(void) +{ + +} + +void buzzer_task(void) +{ + +} + + diff --git a/app/user/buzzer.h b/app/user/buzzer.h new file mode 100644 index 0000000..1862393 --- /dev/null +++ b/app/user/buzzer.h @@ -0,0 +1,8 @@ +#ifndef __BUZZER_H__ +#define __BUZZER_H__ + +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +#endif + diff --git a/app/user/hwCtrl.c b/app/user/hwCtrl.c new file mode 100644 index 0000000..7d6ac8a --- /dev/null +++ b/app/user/hwCtrl.c @@ -0,0 +1,277 @@ + +#include "hwCtrl.h" +#include "r_cg_port.h" +#include "iodefine.h" +#include "PINdef.h" +#include "r_cg_adc.h" +static uint8_t keystate[KEY_NUM] = {0,0,0,0,0,0}; +static uint8_t keyPressFlag[KEY_NUM] = {0,0,0,0,0,0}; +static uint8_t keyReleaseFlag[KEY_NUM] = {0,0,0,0,0,0}; +static uint16_t keydelay[KEY_NUM] = {0,0,0,0,0,0}; +extern uint16_t g_adval[4]; + +#define KEY_DELAY_TIMES 20 //20Ms +void ClearKeyState(void) +{ + uint8_t i; + for (i = 0; i < KEY_NUM; i++) + { + keystate[i] = 0; + } +} +void setKeyPressFlag(uint8_t id) +{ + if (id < KEY_NUM) + { + keyPressFlag[id] = KEY_PRESSED; + } +} +void setKeyReleaseFlag(uint8_t id) +{ + + if (id < KEY_NUM) + { + keyReleaseFlag[id] = KEY_PRESSED; + } +} +uint8_t getKeyPressFlag(uint8_t id) +{ + uint8_t retVal = KEY_NOPRESSED; + if (id < KEY_NUM) + { + retVal = keyPressFlag[id]; + keyPressFlag[id] = KEY_NOPRESSED; + } + return retVal; +} +uint8_t getKeyReleaseFlag(uint8_t id) +{ + uint8_t retVal = KEY_NOPRESSED; + if (id < KEY_NUM) + { + retVal = keyReleaseFlag[id]; + keyReleaseFlag[id] = KEY_NOPRESSED; + } + return retVal; +} + + +extern unsigned char keybyte1,keybyte2,keybyte3; +void KeyScan(void) +{ + uint8_t i,key,key_nopress; + key_nopress = 0; + for (i = 0; i < KEY_NUM; i++) + { + if (i<8) + { + key = (keybyte1 & 0x01<= KEY_DELAY_TIMES) + { + keystate[i] = KEY_PRESSED; + setKeyPressFlag(i); + } + } + else if(key == KEY_NOPRESSED) + { + if (keydelay[i] > 0) + { + keydelay[i]--; + } + else + { + if (keystate[i] == KEY_PRESSED) + { + setKeyReleaseFlag(i); + } + keystate[i] = KEY_NOPRESSED; + key_nopress++; + } + } + } + +} + + +uint8_t GetIOState(uint8_t keyno) +{ + switch (keyno) + { + case KEYID_KBXQ: + return IN_KEY_KBXQ; + case KEYID_KBXH: + return IN_KEY_KBXH; + + case SIGID_HALL1: + return IN_HALL1; + case SIGID_HALL2: + return IN_HALL2; + case SIGID_HALL3: + return IN_HALL3; + case SIGID_HALL4: + return IN_HALL4; + default: + return 0; + } +} + +uint8_t GetKeyState(uint8_t keyno) +{ + if (keyno > 0 && keyno <= 16) + { + return keystate[keyno-1]; + } + return KEY_NOPRESSED; +} + +#define OUT_OFF 0 +#define OUT_ON 1 + +void MOTOR1Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY1P = OUT_OFF; + OUT_RLY1N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY1P = OUT_ON; + OUT_RLY1N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY1P = OUT_OFF; + OUT_RLY1N = OUT_ON; + break; + default: + break; + } +} + +void MOTOR2Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY2P = OUT_OFF; + OUT_RLY2N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY2P = OUT_ON; + OUT_RLY2N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY2P = OUT_OFF; + OUT_RLY2N = OUT_ON; + break; + default: + break; + } +} +void MOTOR3Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY3P = OUT_OFF; + OUT_RLY3N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY3P = OUT_ON; + OUT_RLY3N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY3P = OUT_OFF; + OUT_RLY3N = OUT_ON; + break; + default: + break; + } +} +void MOTOR4Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY4P = OUT_OFF; + OUT_RLY4N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY4P = OUT_ON; + OUT_RLY4N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY4P = OUT_OFF; + OUT_RLY4N = OUT_ON; + break; + default: + break; + } +} +void MOTOR5Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY5P = OUT_OFF; + OUT_RLY5N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY5P = OUT_ON; + OUT_RLY5N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY5P = OUT_OFF; + OUT_RLY5N = OUT_ON; + break; + default: + break; + } +} +void MOTOR6Ctrl(uint8_t act) +{ + switch (act) + { + case ACT_NOACT: + OUT_RLY6P = OUT_OFF; + OUT_RLY6N = OUT_OFF; + break; + case ACT_XH: + OUT_RLY6P = OUT_ON; + OUT_RLY6N = OUT_OFF; + break; + case ACT_XQ: + OUT_RLY6P = OUT_OFF; + OUT_RLY6N = OUT_ON; + break; + default: + break; + } +} + +uint16_t getAdval(uint8_t ch) +{ + if (ch < 4) + { + return g_adval[ch]; + } + + return 0; +} + + + + diff --git a/app/user/hwCtrl.h b/app/user/hwCtrl.h new file mode 100644 index 0000000..393c354 --- /dev/null +++ b/app/user/hwCtrl.h @@ -0,0 +1,64 @@ + +#ifndef __HWCTRL_H__ +#define __HWCTRL_H__ +#include "r_cg_macrodriver.h" + + + + +#define KEY_PRESSED 1 +#define KEY_NOPRESSED 0 + +#define KEY_NUM 20 + +#define ACT_NOACT 0 +#define ACT_XQ 1 +#define ACT_XH 2 + +#define KEYID_K1 17 +#define KEYID_K2 18 +#define KEYID_K3 19 +#define KEYID_K4 20 + +#define KEYID_MOTOR1_XQ 13 +#define KEYID_MOTOR1_XH 16 +#define KEYID_MOTOR2_XQ 14 +#define KEYID_MOTOR2_XH 15 + +#define KEYID_MOTOR3_XQ 9 +#define KEYID_MOTOR3_XH 12 +#define KEYID_MOTOR4_XQ 10 +#define KEYID_MOTOR4_XH 11 + +#define KEYID_MOTOR5_XQ 1 +#define KEYID_MOTOR5_XH 2 +#define KEYID_MOTOR6_XQ 3 +#define KEYID_MOTOR6_XH 4 +#define KEYID_MM 5 +#define KEYID_M1 8 +#define KEYID_M2 7 +#define KEYID_M3 6 + +void ad_handle(void); +uint16_t getAdval(uint8_t ch); + +void KeyScan(void); +void ClearKeyState(void); +uint8_t GetKeyState(uint8_t keyno); +uint8_t getKeyReleaseFlag(uint8_t id); +uint8_t getKeyPressFlag(uint8_t id); +uint8_t GetIOState(uint8_t keyno); + + + +void MOTOR1Ctrl(uint8_t act); +void MOTOR2Ctrl(uint8_t act); +void MOTOR3Ctrl(uint8_t act); +void MOTOR4Ctrl(uint8_t act); +void MOTOR5Ctrl(uint8_t act); +void MOTOR6Ctrl(uint8_t act); + +void SetTfDuty(uint8_t duty); +void SetJrDuty(uint8_t duty); + +#endif