/*
 * Instance header file for ATSAME51N20A
 *
 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries.
 *
 * Subject to your compliance with these terms, you may use Microchip software and any derivatives
 * exclusively with Microchip products. It is your responsibility to comply with third party license
 * terms applicable to your use of third party software (including open source software) that may
 * accompany Microchip software.
 *
 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
 * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
 * FITNESS FOR A PARTICULAR PURPOSE.
 *
 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
 * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
 * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *
 */

/* file generated from device description version 2023-03-17T09:49:56Z */
#ifndef _SAME51_ADC0_INSTANCE_
#define _SAME51_ADC0_INSTANCE_


/* ========== Instance Parameter definitions for ADC0 peripheral ========== */
#define ADC0_BANDGAP                             (27)       /* MUXPOS value to select BANDGAP */
#define ADC0_CTAT                                (29)       /* MUXPOS value to select CTAT */
#define ADC0_DMAC_ID_RESRDY                      (68)       /* index of DMA RESRDY trigger */
#define ADC0_DMAC_ID_SEQ                         (69)       /* Index of DMA SEQ trigger */
#define ADC0_EXTCHANNEL_MSB                      (15)       /* Number of external channels */
#define ADC0_GCLK_ID                             (40)       /* index of Generic Clock */
#define ADC0_INSTANCE_ID                         (103)      /* Instance index for ADC0 */
#define ADC0_MASTER_SLAVE_MODE                   (1)        /* ADC Master/Slave Mode */
#define ADC0_OPAMP01                             (0)        /* MUXPOS value to select OPAMP01 */
#define ADC0_OPAMP2                              (0)        /* MUXPOS value to select OPAMP2 */
#define ADC0_PTAT                                (28)       /* MUXPOS value to select PTAT */
#define ADC0_TOUCH_IMPLEMENTED                   (1)        /* TOUCH implemented or not */
#define ADC0_TOUCH_LINES_NUM                     (32)       /* Number of touch lines */

#endif /* _SAME51_ADC0_INSTANCE_ */
