commit 6e1014a6b3de657cbab8f5df7c05f81cb9146953 Author: sunbeam Date: Wed Jul 3 21:57:00 2024 +0800 初版 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..47b4ece --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +/firmware/p417_SWTR.X/dist +/firmware/p417_SWTR.X/debug +/firmware/p417_SWTR.X/build +/firmware/p417_SWTR.X/.generated_files diff --git a/firmware/p417_SWTR.X/Makefile b/firmware/p417_SWTR.X/Makefile new file mode 100644 index 0000000..fca8e2c --- /dev/null +++ b/firmware/p417_SWTR.X/Makefile @@ -0,0 +1,113 @@ +# +# There exist several targets which are by default empty and which can be +# used for execution of your targets. These targets are usually executed +# before and after some main targets. They are: +# +# .build-pre: called before 'build' target +# .build-post: called after 'build' target +# .clean-pre: called before 'clean' target +# .clean-post: called after 'clean' target +# .clobber-pre: called before 'clobber' target +# .clobber-post: called after 'clobber' target +# .all-pre: called before 'all' target +# .all-post: called after 'all' target +# .help-pre: called before 'help' target +# .help-post: called after 'help' target +# +# Targets beginning with '.' are not intended to be called on their own. +# +# Main targets can be executed directly, and they are: +# +# build build a specific configuration +# clean remove built files from a configuration +# clobber remove all built files +# all build all configurations +# help print help mesage +# +# Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and +# .help-impl are implemented in nbproject/makefile-impl.mk. +# +# Available make variables: +# +# CND_BASEDIR base directory for relative paths +# CND_DISTDIR default top distribution directory (build artifacts) +# CND_BUILDDIR default top build directory (object files, ...) +# CONF name of current configuration +# CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration) +# CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration) +# CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration) +# CND_PACKAGE_DIR_${CONF} directory of package (current configuration) +# CND_PACKAGE_NAME_${CONF} name of package (current configuration) +# CND_PACKAGE_PATH_${CONF} path to package (current configuration) +# +# NOCDDL + + +# Environment +MKDIR=mkdir +CP=cp +CCADMIN=CCadmin +RANLIB=ranlib + + +# build +build: .build-post + +.build-pre: +# Add your pre 'build' code here... + +.build-post: .build-impl +# Add your post 'build' code here... + + +# clean +clean: .clean-post + +.clean-pre: +# Add your pre 'clean' code here... +# WARNING: the IDE does not call this target since it takes a long time to +# simply run make. Instead, the IDE removes the configuration directories +# under build and dist directly without calling make. +# This target is left here so people can do a clean when running a clean +# outside the IDE. + +.clean-post: .clean-impl +# Add your post 'clean' code here... + + +# clobber +clobber: .clobber-post + +.clobber-pre: +# Add your pre 'clobber' code here... + +.clobber-post: .clobber-impl +# Add your post 'clobber' code here... + + +# all +all: .all-post + +.all-pre: +# Add your pre 'all' code here... + +.all-post: .all-impl +# Add your post 'all' code here... + + +# help +help: .help-post + +.help-pre: +# Add your pre 'help' code here... + +.help-post: .help-impl +# Add your post 'help' code here... + + + +# include project implementation makefile +include nbproject/Makefile-impl.mk + +# include project make variables +include nbproject/Makefile-variables.mk diff --git a/firmware/p417_SWTR.X/nbproject/Makefile-genesis.properties b/firmware/p417_SWTR.X/nbproject/Makefile-genesis.properties new file mode 100644 index 0000000..88d1405 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Makefile-genesis.properties @@ -0,0 +1,14 @@ +# +#Thu May 11 23:18:16 CST 2023 +mcal.com-microchip-mplab-nbide-toolchain-xc32-XC32LanguageToolchain.md5=e4472a864cace3fb7127149b7c727f38 +mcal.com-microchip-mplab-mdbcore-JLink-JLinkImpl.md5=8332ec366749fd298fb19bb5f792dea3 +conf.ids=mcal +mcal.languagetoolchain.version=4.10 +host.id=1f09-swyu-sw +configurations-xml=b6a2991bf0bcf61ed74bd7af80d0c072 +mcal.Pack.dfplocation=D\:\\MPLABX\\v6.00\\packs\\Microchip\\SAME51_DFP\\3.5.104 +com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=6e02ca5e9f5042ffd365b42ab82d3a9b +user-defined-mime-resolver-xml=none +proj.dir=G\:\\WorkSpace\\Ongoing\\XY_Modification\\20230508\\P417_SWTR\\firmware\\p417_SWTR.X +mcal.languagetoolchain.dir=D\:\\Microchip_xc32\\v4.10\\bin +host.platform=windows diff --git a/firmware/p417_SWTR.X/nbproject/Makefile-impl.mk b/firmware/p417_SWTR.X/nbproject/Makefile-impl.mk new file mode 100644 index 0000000..de15c84 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Makefile-impl.mk @@ -0,0 +1,69 @@ +# +# Generated Makefile - do not edit! +# +# Edit the Makefile in the project folder instead (../Makefile). Each target +# has a pre- and a post- target defined where you can add customization code. +# +# This makefile implements macros and targets common to all configurations. +# +# NOCDDL + + +# Building and Cleaning subprojects are done by default, but can be controlled with the SUB +# macro. If SUB=no, subprojects will not be built or cleaned. The following macro +# statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf +# and .clean-reqprojects-conf unless SUB has the value 'no' +SUB_no=NO +SUBPROJECTS=${SUB_${SUB}} +BUILD_SUBPROJECTS_=.build-subprojects +BUILD_SUBPROJECTS_NO= +BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}} +CLEAN_SUBPROJECTS_=.clean-subprojects +CLEAN_SUBPROJECTS_NO= +CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}} + + +# Project Name +PROJECTNAME=p417_SWTR.X + +# Active Configuration +DEFAULTCONF=mcal +CONF=${DEFAULTCONF} + +# All Configurations +ALLCONFS=mcal + + +# build +.build-impl: .build-pre + ${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-conf + + +# clean +.clean-impl: .clean-pre + ${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .clean-conf + +# clobber +.clobber-impl: .clobber-pre .depcheck-impl + ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=mcal clean + + + +# all +.all-impl: .all-pre .depcheck-impl + ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=mcal build + + + +# dependency checking support +.depcheck-impl: +# @echo "# This code depends on make tool being used" >.dep.inc +# @if [ -n "${MAKE_VERSION}" ]; then \ +# echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \ +# echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \ +# echo "include \$${DEPFILES}" >>.dep.inc; \ +# echo "endif" >>.dep.inc; \ +# else \ +# echo ".KEEP_STATE:" >>.dep.inc; \ +# echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \ +# fi diff --git a/firmware/p417_SWTR.X/nbproject/Makefile-local-mcal.mk b/firmware/p417_SWTR.X/nbproject/Makefile-local-mcal.mk new file mode 100644 index 0000000..3ecf33f --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Makefile-local-mcal.mk @@ -0,0 +1,39 @@ +# +# Generated Makefile - do not edit! +# +# +# This file contains information about the location of compilers and other tools. +# If you commmit this file into your revision control server, you will be able to +# to checkout the project and build it from the command line with make. However, +# if more than one person works on the same project, then this file might show +# conflicts since different users are bound to have compilers in different places. +# In that case you might choose to not commit this file and let MPLAB X recreate this file +# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at +# least once so the file gets created and the project can be built. Finally, you can also +# avoid using this file at all if you are only building from the command line with make. +# You can invoke make with the values of the macros: +# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ... +# +SHELL=cmd.exe +PATH_TO_IDE_BIN=E:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/ +# Adding MPLAB X bin directory to path. +PATH:=E:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/:$(PATH) +# Path to java used to run MPLAB X when this makefile was created +MP_JAVA_PATH="E:\Program Files\Microchip\MPLABX\v6.00\sys\java\zulu8.54.0.21-ca-fx-jre8.0.292-win_x64/bin/" +OS_CURRENT="$(shell uname -s)" +MP_CC="E:\Program Files\Microchip\xc32\v4.10\bin\xc32-gcc.exe" +MP_CPPC="E:\Program Files\Microchip\xc32\v4.10\bin\xc32-g++.exe" +# MP_BC is not defined +MP_AS="E:\Program Files\Microchip\xc32\v4.10\bin\xc32-as.exe" +MP_LD="E:\Program Files\Microchip\xc32\v4.10\bin\xc32-ld.exe" +MP_AR="E:\Program Files\Microchip\xc32\v4.10\bin\xc32-ar.exe" +DEP_GEN=${MP_JAVA_PATH}java -jar "E:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/extractobjectdependencies.jar" +MP_CC_DIR="E:\Program Files\Microchip\xc32\v4.10\bin" +MP_CPPC_DIR="E:\Program Files\Microchip\xc32\v4.10\bin" +# MP_BC_DIR is not defined +MP_AS_DIR="E:\Program Files\Microchip\xc32\v4.10\bin" +MP_LD_DIR="E:\Program Files\Microchip\xc32\v4.10\bin" +MP_AR_DIR="E:\Program Files\Microchip\xc32\v4.10\bin" +# MP_BC_DIR is not defined +CMSIS_DIR=E:/Program Files/Microchip/MPLABX/v6.00/packs/arm/CMSIS/5.4.0 +DFP_DIR=E:/Program Files/Microchip/MPLABX/v6.00/packs/Microchip/SAME51_DFP/3.5.104 diff --git a/firmware/p417_SWTR.X/nbproject/Makefile-mcal.mk b/firmware/p417_SWTR.X/nbproject/Makefile-mcal.mk new file mode 100644 index 0000000..d6979fa --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Makefile-mcal.mk @@ -0,0 +1,1307 @@ +# +# Generated Makefile - do not edit! +# +# Edit the Makefile in the project folder instead (../Makefile). Each target +# has a -pre and a -post target defined where you can add customized code. +# +# This makefile implements configuration specific macros and targets. + + +# Include project Makefile +ifeq "${IGNORE_LOCAL}" "TRUE" +# do not include local makefile. User is passing all local related variables already +else +include Makefile +# Include makefile containing local settings +ifeq "$(wildcard nbproject/Makefile-local-mcal.mk)" "nbproject/Makefile-local-mcal.mk" +include nbproject/Makefile-local-mcal.mk +endif +endif + +# Environment +MKDIR=gnumkdir -p +RM=rm -f +MV=mv +CP=cp + +# Macros +CND_CONF=mcal +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +IMAGE_TYPE=debug +OUTPUT_SUFFIX=elf +DEBUGGABLE_SUFFIX=elf +FINAL_IMAGE=${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} +else +IMAGE_TYPE=production +OUTPUT_SUFFIX=hex +DEBUGGABLE_SUFFIX=elf +FINAL_IMAGE=${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} +endif + +ifeq ($(COMPARE_BUILD), true) +COMPARISON_BUILD=-mafrlcsj +else +COMPARISON_BUILD= +endif + +ifdef SUB_IMAGE_ADDRESS + +else +SUB_IMAGE_ADDRESS_COMMAND= +endif + +# Object Directory +OBJECTDIR=build/${CND_CONF}/${IMAGE_TYPE} + +# Distribution Directory +DISTDIR=dist/${CND_CONF}/${IMAGE_TYPE} + +# Source Files Quoted if spaced +SOURCEFILES_QUOTED_IF_SPACED=../src/Calibration/calib.c ../src/config/mcal/peripheral/adc/plib_adc0.c ../src/config/mcal/peripheral/adc/plib_adc1.c ../src/config/mcal/peripheral/can/plib_can1.c ../src/config/mcal/peripheral/clock/plib_clock.c ../src/config/mcal/peripheral/cmcc/plib_cmcc.c ../src/config/mcal/peripheral/dac/plib_dac.c ../src/config/mcal/peripheral/evsys/plib_evsys.c ../src/config/mcal/peripheral/nvic/plib_nvic.c ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c ../src/config/mcal/peripheral/port/plib_port.c ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c ../src/config/mcal/peripheral/systick/plib_systick.c ../src/config/mcal/peripheral/tc/plib_tc0.c ../src/config/mcal/peripheral/tcc/plib_tcc0.c ../src/config/mcal/peripheral/wdt/plib_wdt.c ../src/config/mcal/stdio/xc32_monitor.c ../src/config/mcal/touch/touch.c ../src/config/mcal/touch/touch_example.c ../src/config/mcal/initialization.c ../src/config/mcal/interrupts.c ../src/config/mcal/exceptions.c ../src/config/mcal/startup_xc32.c ../src/config/mcal/libc_syscalls.c ../src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c ../src/DiagnosticR/Dem/Dem.c ../src/DiagnosticR/Dem/Dem_Debounce.c ../src/DiagnosticR/Dem/Dem_Extension.c ../src/DiagnosticR/Dem/Dem_LCfg.c ../src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c ../src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c ../src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c ../src/DiagnosticR/UDS/UDS_CoreServices_CB.c ../src/DiagnosticR/UDS/UDS_DIDNvm.c ../src/DiagnosticR/UDS/UDS_DiDRead_CB.c ../src/DiagnosticR/UDS/UDS_DiDWrite_CB.c ../src/DiagnosticR/UDS/UDS_IORoutineControl.c ../src/DiagnosticR/UDS/UDS_Services_Common.c ../src/forceSnsr/forcedetect.c ../src/forceSnsr/forceSnsr.c ../src/forceSnsr/forceSnsr_Cfg.c ../src/FunctionState/FunctionState.c ../src/OsekCom/OsekCom.c ../src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c ../src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c ../src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c ../src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c ../src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c ../src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c ../src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c ../src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c ../src/RTE/RTE.c ../src/smartEE/smartee.c ../src/Speaker/SA51024.c ../src/Speaker/SA51024_Cfg.c ../src/Speaker/Speaker.c ../src/TLE9263/TLE926x.c ../src/TLE9263/TLE926x_SPI.c ../src/TLE9263/TLE926x_Main.c ../src/TouchPanel/TouchPanel.c ../src/main.c + +# Object Files Quoted if spaced +OBJECTFILES_QUOTED_IF_SPACED=${OBJECTDIR}/_ext/1958549552/calib.o ${OBJECTDIR}/_ext/1982922760/plib_adc0.o ${OBJECTDIR}/_ext/1982922760/plib_adc1.o ${OBJECTDIR}/_ext/1982924600/plib_can1.o ${OBJECTDIR}/_ext/1374606986/plib_clock.o ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o ${OBJECTDIR}/_ext/1982925550/plib_dac.o ${OBJECTDIR}/_ext/1372457500/plib_evsys.o ${OBJECTDIR}/_ext/1341468282/plib_nvic.o ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o ${OBJECTDIR}/_ext/1341521433/plib_port.o ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o ${OBJECTDIR}/_ext/750815918/plib_systick.o ${OBJECTDIR}/_ext/74581497/plib_tc0.o ${OBJECTDIR}/_ext/1982940988/plib_tcc0.o ${OBJECTDIR}/_ext/1982943919/plib_wdt.o ${OBJECTDIR}/_ext/118864466/xc32_monitor.o ${OBJECTDIR}/_ext/118073756/touch.o ${OBJECTDIR}/_ext/118073756/touch_example.o ${OBJECTDIR}/_ext/779798284/initialization.o ${OBJECTDIR}/_ext/779798284/interrupts.o ${OBJECTDIR}/_ext/779798284/exceptions.o ${OBJECTDIR}/_ext/779798284/startup_xc32.o ${OBJECTDIR}/_ext/779798284/libc_syscalls.o ${OBJECTDIR}/_ext/652846568/Timer.o ${OBJECTDIR}/_ext/22353991/TP_Functions.o ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o ${OBJECTDIR}/_ext/22353991/TP_Rx.o ${OBJECTDIR}/_ext/22353991/TP_RxFun.o ${OBJECTDIR}/_ext/22353991/TP_Rx_Full.o ${OBJECTDIR}/_ext/22353991/TP_Rx_Lite.o ${OBJECTDIR}/_ext/22353991/TP_Tx.o ${OBJECTDIR}/_ext/22353991/TP_Tx_Full.o ${OBJECTDIR}/_ext/22353991/TP_Tx_Lite.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_EcuResetTask.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_Funcions.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_RequestRespondCtrl.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_SessionCtrlTask.o ${OBJECTDIR}/_ext/1802317902/Dem.o ${OBJECTDIR}/_ext/1802317902/Dem_Debounce.o ${OBJECTDIR}/_ext/1802317902/Dem_Extension.o ${OBJECTDIR}/_ext/1802317902/Dem_LCfg.o ${OBJECTDIR}/_ext/467908807/SysDiagDetect.o ${OBJECTDIR}/_ext/1498712618/TP_CFG.o ${OBJECTDIR}/_ext/605365704/UdsServerCallbacks_H61L.o ${OBJECTDIR}/_ext/1802333190/UDS_CoreServices_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_DIDNvm.o ${OBJECTDIR}/_ext/1802333190/UDS_DiDRead_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_DiDWrite_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_IORoutineControl.o ${OBJECTDIR}/_ext/1802333190/UDS_Services_Common.o ${OBJECTDIR}/_ext/2142047477/forcedetect.o ${OBJECTDIR}/_ext/2142047477/forceSnsr.o ${OBJECTDIR}/_ext/2142047477/forceSnsr_Cfg.o ${OBJECTDIR}/_ext/984511487/FunctionState.o ${OBJECTDIR}/_ext/206316669/OsekCom.o ${OBJECTDIR}/_ext/905407901/ACT_control_20ms.o ${OBJECTDIR}/_ext/905407901/CAN_0x307_1000ms_Control.o ${OBJECTDIR}/_ext/905407901/CAN_0x307_25ms_Control.o ${OBJECTDIR}/_ext/905407901/Get_0x309_CRC_10ms.o ${OBJECTDIR}/_ext/905407901/illumination_control_10ms.o ${OBJECTDIR}/_ext/905407901/LED_Control_10ms.o ${OBJECTDIR}/_ext/905407901/P417_SWTR_App.o ${OBJECTDIR}/_ext/905407901/P417_SWTR_App_data.o ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_0.o ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_5.o ${OBJECTDIR}/_ext/905407901/Set_0x309_RC_10ms.o ${OBJECTDIR}/_ext/905407901/Set_Diag_20ms.o ${OBJECTDIR}/_ext/905407901/TouchBoardXY_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_0x307_Send_And_ACT_Req_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_0x309_Send_And_ACT_Req_10ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Center_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Down_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_Right_Slide_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_MENU_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Right_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Up_Down_Slide_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_up_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_VOICE_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_VOL_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_X_handle_10ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Y_handle_10ms.o ${OBJECTDIR}/_ext/659835465/RTE.o ${OBJECTDIR}/_ext/1916463407/smartee.o ${OBJECTDIR}/_ext/624783131/SA51024.o ${OBJECTDIR}/_ext/624783131/SA51024_Cfg.o ${OBJECTDIR}/_ext/624783131/Speaker.o ${OBJECTDIR}/_ext/798729495/TLE926x.o ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o ${OBJECTDIR}/_ext/1720498337/TouchPanel.o ${OBJECTDIR}/_ext/1360937237/main.o +POSSIBLE_DEPFILES=${OBJECTDIR}/_ext/1958549552/calib.o.d ${OBJECTDIR}/_ext/1982922760/plib_adc0.o.d ${OBJECTDIR}/_ext/1982922760/plib_adc1.o.d ${OBJECTDIR}/_ext/1982924600/plib_can1.o.d ${OBJECTDIR}/_ext/1374606986/plib_clock.o.d ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o.d ${OBJECTDIR}/_ext/1982925550/plib_dac.o.d ${OBJECTDIR}/_ext/1372457500/plib_evsys.o.d ${OBJECTDIR}/_ext/1341468282/plib_nvic.o.d ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o.d ${OBJECTDIR}/_ext/1341521433/plib_port.o.d ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o.d ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o.d ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o.d ${OBJECTDIR}/_ext/750815918/plib_systick.o.d ${OBJECTDIR}/_ext/74581497/plib_tc0.o.d ${OBJECTDIR}/_ext/1982940988/plib_tcc0.o.d ${OBJECTDIR}/_ext/1982943919/plib_wdt.o.d ${OBJECTDIR}/_ext/118864466/xc32_monitor.o.d ${OBJECTDIR}/_ext/118073756/touch.o.d ${OBJECTDIR}/_ext/118073756/touch_example.o.d ${OBJECTDIR}/_ext/779798284/initialization.o.d ${OBJECTDIR}/_ext/779798284/interrupts.o.d ${OBJECTDIR}/_ext/779798284/exceptions.o.d ${OBJECTDIR}/_ext/779798284/startup_xc32.o.d ${OBJECTDIR}/_ext/779798284/libc_syscalls.o.d ${OBJECTDIR}/_ext/652846568/Timer.o.d ${OBJECTDIR}/_ext/22353991/TP_Functions.o.d ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o.d ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o.d ${OBJECTDIR}/_ext/22353991/TP_Rx.o.d ${OBJECTDIR}/_ext/22353991/TP_RxFun.o.d ${OBJECTDIR}/_ext/22353991/TP_Rx_Full.o.d ${OBJECTDIR}/_ext/22353991/TP_Rx_Lite.o.d ${OBJECTDIR}/_ext/22353991/TP_Tx.o.d ${OBJECTDIR}/_ext/22353991/TP_Tx_Full.o.d ${OBJECTDIR}/_ext/22353991/TP_Tx_Lite.o.d ${OBJECTDIR}/_ext/22353990/Iso15765_3_EcuResetTask.o.d ${OBJECTDIR}/_ext/22353990/Iso15765_3_Funcions.o.d ${OBJECTDIR}/_ext/22353990/Iso15765_3_RequestRespondCtrl.o.d ${OBJECTDIR}/_ext/22353990/Iso15765_3_SessionCtrlTask.o.d ${OBJECTDIR}/_ext/1802317902/Dem.o.d ${OBJECTDIR}/_ext/1802317902/Dem_Debounce.o.d ${OBJECTDIR}/_ext/1802317902/Dem_Extension.o.d ${OBJECTDIR}/_ext/1802317902/Dem_LCfg.o.d ${OBJECTDIR}/_ext/467908807/SysDiagDetect.o.d ${OBJECTDIR}/_ext/1498712618/TP_CFG.o.d ${OBJECTDIR}/_ext/605365704/UdsServerCallbacks_H61L.o.d ${OBJECTDIR}/_ext/1802333190/UDS_CoreServices_CB.o.d ${OBJECTDIR}/_ext/1802333190/UDS_DIDNvm.o.d ${OBJECTDIR}/_ext/1802333190/UDS_DiDRead_CB.o.d ${OBJECTDIR}/_ext/1802333190/UDS_DiDWrite_CB.o.d ${OBJECTDIR}/_ext/1802333190/UDS_IORoutineControl.o.d ${OBJECTDIR}/_ext/1802333190/UDS_Services_Common.o.d ${OBJECTDIR}/_ext/2142047477/forcedetect.o.d ${OBJECTDIR}/_ext/2142047477/forceSnsr.o.d ${OBJECTDIR}/_ext/2142047477/forceSnsr_Cfg.o.d ${OBJECTDIR}/_ext/984511487/FunctionState.o.d ${OBJECTDIR}/_ext/206316669/OsekCom.o.d ${OBJECTDIR}/_ext/905407901/ACT_control_20ms.o.d ${OBJECTDIR}/_ext/905407901/CAN_0x307_1000ms_Control.o.d ${OBJECTDIR}/_ext/905407901/CAN_0x307_25ms_Control.o.d ${OBJECTDIR}/_ext/905407901/Get_0x309_CRC_10ms.o.d ${OBJECTDIR}/_ext/905407901/illumination_control_10ms.o.d ${OBJECTDIR}/_ext/905407901/LED_Control_10ms.o.d ${OBJECTDIR}/_ext/905407901/P417_SWTR_App.o.d ${OBJECTDIR}/_ext/905407901/P417_SWTR_App_data.o.d ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_0.o.d ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_5.o.d ${OBJECTDIR}/_ext/905407901/Set_0x309_RC_10ms.o.d ${OBJECTDIR}/_ext/905407901/Set_Diag_20ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoardXY_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_0x307_Send_And_ACT_Req_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_0x309_Send_And_ACT_Req_10ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Center_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Down_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_Right_Slide_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_MENU_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Right_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Up_Down_Slide_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_up_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_VOICE_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_VOL_handle_4ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_X_handle_10ms.o.d ${OBJECTDIR}/_ext/905407901/TouchBoard_Y_handle_10ms.o.d ${OBJECTDIR}/_ext/659835465/RTE.o.d ${OBJECTDIR}/_ext/1916463407/smartee.o.d ${OBJECTDIR}/_ext/624783131/SA51024.o.d ${OBJECTDIR}/_ext/624783131/SA51024_Cfg.o.d ${OBJECTDIR}/_ext/624783131/Speaker.o.d ${OBJECTDIR}/_ext/798729495/TLE926x.o.d ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o.d ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o.d ${OBJECTDIR}/_ext/1720498337/TouchPanel.o.d ${OBJECTDIR}/_ext/1360937237/main.o.d + +# Object Files +OBJECTFILES=${OBJECTDIR}/_ext/1958549552/calib.o ${OBJECTDIR}/_ext/1982922760/plib_adc0.o ${OBJECTDIR}/_ext/1982922760/plib_adc1.o ${OBJECTDIR}/_ext/1982924600/plib_can1.o ${OBJECTDIR}/_ext/1374606986/plib_clock.o ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o ${OBJECTDIR}/_ext/1982925550/plib_dac.o ${OBJECTDIR}/_ext/1372457500/plib_evsys.o ${OBJECTDIR}/_ext/1341468282/plib_nvic.o ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o ${OBJECTDIR}/_ext/1341521433/plib_port.o ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o ${OBJECTDIR}/_ext/750815918/plib_systick.o ${OBJECTDIR}/_ext/74581497/plib_tc0.o ${OBJECTDIR}/_ext/1982940988/plib_tcc0.o ${OBJECTDIR}/_ext/1982943919/plib_wdt.o ${OBJECTDIR}/_ext/118864466/xc32_monitor.o ${OBJECTDIR}/_ext/118073756/touch.o ${OBJECTDIR}/_ext/118073756/touch_example.o ${OBJECTDIR}/_ext/779798284/initialization.o ${OBJECTDIR}/_ext/779798284/interrupts.o ${OBJECTDIR}/_ext/779798284/exceptions.o ${OBJECTDIR}/_ext/779798284/startup_xc32.o ${OBJECTDIR}/_ext/779798284/libc_syscalls.o ${OBJECTDIR}/_ext/652846568/Timer.o ${OBJECTDIR}/_ext/22353991/TP_Functions.o ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o ${OBJECTDIR}/_ext/22353991/TP_Rx.o ${OBJECTDIR}/_ext/22353991/TP_RxFun.o ${OBJECTDIR}/_ext/22353991/TP_Rx_Full.o ${OBJECTDIR}/_ext/22353991/TP_Rx_Lite.o ${OBJECTDIR}/_ext/22353991/TP_Tx.o ${OBJECTDIR}/_ext/22353991/TP_Tx_Full.o ${OBJECTDIR}/_ext/22353991/TP_Tx_Lite.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_EcuResetTask.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_Funcions.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_RequestRespondCtrl.o ${OBJECTDIR}/_ext/22353990/Iso15765_3_SessionCtrlTask.o ${OBJECTDIR}/_ext/1802317902/Dem.o ${OBJECTDIR}/_ext/1802317902/Dem_Debounce.o ${OBJECTDIR}/_ext/1802317902/Dem_Extension.o ${OBJECTDIR}/_ext/1802317902/Dem_LCfg.o ${OBJECTDIR}/_ext/467908807/SysDiagDetect.o ${OBJECTDIR}/_ext/1498712618/TP_CFG.o ${OBJECTDIR}/_ext/605365704/UdsServerCallbacks_H61L.o ${OBJECTDIR}/_ext/1802333190/UDS_CoreServices_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_DIDNvm.o ${OBJECTDIR}/_ext/1802333190/UDS_DiDRead_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_DiDWrite_CB.o ${OBJECTDIR}/_ext/1802333190/UDS_IORoutineControl.o ${OBJECTDIR}/_ext/1802333190/UDS_Services_Common.o ${OBJECTDIR}/_ext/2142047477/forcedetect.o ${OBJECTDIR}/_ext/2142047477/forceSnsr.o ${OBJECTDIR}/_ext/2142047477/forceSnsr_Cfg.o ${OBJECTDIR}/_ext/984511487/FunctionState.o ${OBJECTDIR}/_ext/206316669/OsekCom.o ${OBJECTDIR}/_ext/905407901/ACT_control_20ms.o ${OBJECTDIR}/_ext/905407901/CAN_0x307_1000ms_Control.o ${OBJECTDIR}/_ext/905407901/CAN_0x307_25ms_Control.o ${OBJECTDIR}/_ext/905407901/Get_0x309_CRC_10ms.o ${OBJECTDIR}/_ext/905407901/illumination_control_10ms.o ${OBJECTDIR}/_ext/905407901/LED_Control_10ms.o ${OBJECTDIR}/_ext/905407901/P417_SWTR_App.o ${OBJECTDIR}/_ext/905407901/P417_SWTR_App_data.o ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_0.o ${OBJECTDIR}/_ext/905407901/rt_sys_P417_SWTR_App_5.o ${OBJECTDIR}/_ext/905407901/Set_0x309_RC_10ms.o ${OBJECTDIR}/_ext/905407901/Set_Diag_20ms.o ${OBJECTDIR}/_ext/905407901/TouchBoardXY_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_0x307_Send_And_ACT_Req_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_0x309_Send_And_ACT_Req_10ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Center_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Down_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Left_Right_Slide_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_MENU_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Right_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Up_Down_Slide_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_up_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_VOICE_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_VOL_handle_4ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_X_handle_10ms.o ${OBJECTDIR}/_ext/905407901/TouchBoard_Y_handle_10ms.o ${OBJECTDIR}/_ext/659835465/RTE.o ${OBJECTDIR}/_ext/1916463407/smartee.o ${OBJECTDIR}/_ext/624783131/SA51024.o ${OBJECTDIR}/_ext/624783131/SA51024_Cfg.o ${OBJECTDIR}/_ext/624783131/Speaker.o ${OBJECTDIR}/_ext/798729495/TLE926x.o ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o ${OBJECTDIR}/_ext/1720498337/TouchPanel.o ${OBJECTDIR}/_ext/1360937237/main.o + +# Source Files +SOURCEFILES=../src/Calibration/calib.c ../src/config/mcal/peripheral/adc/plib_adc0.c ../src/config/mcal/peripheral/adc/plib_adc1.c ../src/config/mcal/peripheral/can/plib_can1.c ../src/config/mcal/peripheral/clock/plib_clock.c ../src/config/mcal/peripheral/cmcc/plib_cmcc.c ../src/config/mcal/peripheral/dac/plib_dac.c ../src/config/mcal/peripheral/evsys/plib_evsys.c ../src/config/mcal/peripheral/nvic/plib_nvic.c ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c ../src/config/mcal/peripheral/port/plib_port.c ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c ../src/config/mcal/peripheral/systick/plib_systick.c ../src/config/mcal/peripheral/tc/plib_tc0.c ../src/config/mcal/peripheral/tcc/plib_tcc0.c ../src/config/mcal/peripheral/wdt/plib_wdt.c ../src/config/mcal/stdio/xc32_monitor.c ../src/config/mcal/touch/touch.c ../src/config/mcal/touch/touch_example.c ../src/config/mcal/initialization.c ../src/config/mcal/interrupts.c ../src/config/mcal/exceptions.c ../src/config/mcal/startup_xc32.c ../src/config/mcal/libc_syscalls.c ../src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c ../src/DiagnosticR/Dem/Dem.c ../src/DiagnosticR/Dem/Dem_Debounce.c ../src/DiagnosticR/Dem/Dem_Extension.c ../src/DiagnosticR/Dem/Dem_LCfg.c ../src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c ../src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c ../src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c ../src/DiagnosticR/UDS/UDS_CoreServices_CB.c ../src/DiagnosticR/UDS/UDS_DIDNvm.c ../src/DiagnosticR/UDS/UDS_DiDRead_CB.c ../src/DiagnosticR/UDS/UDS_DiDWrite_CB.c ../src/DiagnosticR/UDS/UDS_IORoutineControl.c ../src/DiagnosticR/UDS/UDS_Services_Common.c ../src/forceSnsr/forcedetect.c ../src/forceSnsr/forceSnsr.c ../src/forceSnsr/forceSnsr_Cfg.c ../src/FunctionState/FunctionState.c ../src/OsekCom/OsekCom.c ../src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c ../src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c ../src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c ../src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c ../src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c ../src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c ../src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c ../src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c ../src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c ../src/RTE/RTE.c ../src/smartEE/smartee.c ../src/Speaker/SA51024.c ../src/Speaker/SA51024_Cfg.c ../src/Speaker/Speaker.c ../src/TLE9263/TLE926x.c ../src/TLE9263/TLE926x_SPI.c ../src/TLE9263/TLE926x_Main.c ../src/TouchPanel/TouchPanel.c ../src/main.c + +# Pack Options +PACK_COMMON_OPTIONS=-I "${CMSIS_DIR}/CMSIS/Core/Include" + + + +CFLAGS= +ASFLAGS= +LDLIBSOPTIONS= + +############# Tool locations ########################################## +# If you copy a project from one host to another, the path where the # +# compiler is installed may be different. # +# If you open this project with MPLAB X in the new host, this # +# makefile will be regenerated and the paths will be corrected. # +####################################################################### +# fixDeps replaces a bunch of sed/cat/printf statements that slow down the build +FIXDEPS=fixDeps + +.build-conf: ${BUILD_SUBPROJECTS} +ifneq ($(INFORMATION_MESSAGE), ) + @echo $(INFORMATION_MESSAGE) +endif + ${MAKE} -f nbproject/Makefile-mcal.mk ${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} + +MP_PROCESSOR_OPTION=ATSAME51J19A +MP_LINKER_FILE_OPTION=,--script="..\src\config\mcal\ATSAME51J19A.ld" +# ------------------------------------------------------------------------------------ +# Rules for buildStep: assemble +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +else +endif + +# ------------------------------------------------------------------------------------ +# Rules for buildStep: assembleWithPreprocess +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +else +endif + +# ------------------------------------------------------------------------------------ +# Rules for buildStep: compile +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +${OBJECTDIR}/_ext/1958549552/calib.o: ../src/Calibration/calib.c .generated_files/flags/mcal/6b90a597921237fc0828ece9a7c5e308866ae7d6 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1958549552" + @${RM} ${OBJECTDIR}/_ext/1958549552/calib.o.d + @${RM} ${OBJECTDIR}/_ext/1958549552/calib.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1958549552/calib.o.d" -o ${OBJECTDIR}/_ext/1958549552/calib.o ../src/Calibration/calib.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982922760/plib_adc0.o: ../src/config/mcal/peripheral/adc/plib_adc0.c .generated_files/flags/mcal/bb9bcfcc0c49cd5f14498b4f91b26f7a7ec066d8 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982922760" + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc0.o.d + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc0.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982922760/plib_adc0.o.d" -o ${OBJECTDIR}/_ext/1982922760/plib_adc0.o ../src/config/mcal/peripheral/adc/plib_adc0.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982922760/plib_adc1.o: ../src/config/mcal/peripheral/adc/plib_adc1.c .generated_files/flags/mcal/bcf0aae74e9b9b2925e0b917aae3732c531f87ab .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982922760" + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc1.o.d + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc1.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982922760/plib_adc1.o.d" -o ${OBJECTDIR}/_ext/1982922760/plib_adc1.o ../src/config/mcal/peripheral/adc/plib_adc1.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982924600/plib_can1.o: ../src/config/mcal/peripheral/can/plib_can1.c .generated_files/flags/mcal/4494f743d11983f3a9e749bd22ef744a2ebc3821 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982924600" + @${RM} ${OBJECTDIR}/_ext/1982924600/plib_can1.o.d + @${RM} ${OBJECTDIR}/_ext/1982924600/plib_can1.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982924600/plib_can1.o.d" -o ${OBJECTDIR}/_ext/1982924600/plib_can1.o ../src/config/mcal/peripheral/can/plib_can1.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1374606986/plib_clock.o: ../src/config/mcal/peripheral/clock/plib_clock.c .generated_files/flags/mcal/f63cc01ebaf830c0fdb60489ef8ea5b63c64ace8 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1374606986" + @${RM} ${OBJECTDIR}/_ext/1374606986/plib_clock.o.d + @${RM} ${OBJECTDIR}/_ext/1374606986/plib_clock.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1374606986/plib_clock.o.d" -o ${OBJECTDIR}/_ext/1374606986/plib_clock.o ../src/config/mcal/peripheral/clock/plib_clock.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341131746/plib_cmcc.o: ../src/config/mcal/peripheral/cmcc/plib_cmcc.c .generated_files/flags/mcal/a3cfca733acf14eb3b9ded7ea7e3f32a0f305e2a .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341131746" + @${RM} ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o.d + @${RM} ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341131746/plib_cmcc.o.d" -o ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o ../src/config/mcal/peripheral/cmcc/plib_cmcc.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982925550/plib_dac.o: ../src/config/mcal/peripheral/dac/plib_dac.c .generated_files/flags/mcal/4f504c7647897bb666720e6cd822fc6c3f09c630 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982925550" + @${RM} ${OBJECTDIR}/_ext/1982925550/plib_dac.o.d + @${RM} ${OBJECTDIR}/_ext/1982925550/plib_dac.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982925550/plib_dac.o.d" -o ${OBJECTDIR}/_ext/1982925550/plib_dac.o ../src/config/mcal/peripheral/dac/plib_dac.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1372457500/plib_evsys.o: ../src/config/mcal/peripheral/evsys/plib_evsys.c .generated_files/flags/mcal/cb240c41a42ae9bfac95c1464c7dafafedc59594 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1372457500" + @${RM} ${OBJECTDIR}/_ext/1372457500/plib_evsys.o.d + @${RM} ${OBJECTDIR}/_ext/1372457500/plib_evsys.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1372457500/plib_evsys.o.d" -o ${OBJECTDIR}/_ext/1372457500/plib_evsys.o ../src/config/mcal/peripheral/evsys/plib_evsys.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341468282/plib_nvic.o: ../src/config/mcal/peripheral/nvic/plib_nvic.c .generated_files/flags/mcal/669ee48c13a03195591643db33206393b2cbacd7 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341468282" + @${RM} ${OBJECTDIR}/_ext/1341468282/plib_nvic.o.d + @${RM} ${OBJECTDIR}/_ext/1341468282/plib_nvic.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341468282/plib_nvic.o.d" -o ${OBJECTDIR}/_ext/1341468282/plib_nvic.o ../src/config/mcal/peripheral/nvic/plib_nvic.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + 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-I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o.d" -o ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341521433/plib_port.o: ../src/config/mcal/peripheral/port/plib_port.c .generated_files/flags/mcal/5d2eaf9de8a6e0a45f9dc03774ccc63dbe3365bb .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341521433" + @${RM} ${OBJECTDIR}/_ext/1341521433/plib_port.o.d + @${RM} ${OBJECTDIR}/_ext/1341521433/plib_port.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections 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-I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341521433/plib_port.o.d" -o ${OBJECTDIR}/_ext/1341521433/plib_port.o ../src/config/mcal/peripheral/port/plib_port.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + 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-I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o.d" -o ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o: ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c .generated_files/flags/mcal/369940fd07d65861bd67034ca5124ad45b83c024 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/24027325" + @${RM} ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o.d + @${RM} ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x 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-I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o.d" -o ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/750815918/plib_systick.o: ../src/config/mcal/peripheral/systick/plib_systick.c .generated_files/flags/mcal/d8fe4c598a044cae4f0e780e6616d38efb3db809 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + 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-I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror 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-I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/652846568/Timer.o.d" -o ${OBJECTDIR}/_ext/652846568/Timer.o ../src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/22353991/TP_Functions.o: ../src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c 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-I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/22353991/TP_Functions.o.d" -o ${OBJECTDIR}/_ext/22353991/TP_Functions.o ../src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o: ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c .generated_files/flags/mcal/1de90a26c97c194780746714d87e032961381a2f .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/22353991" + @${RM} ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o.d + @${RM} ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Rx.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections 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$(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o: ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c .generated_files/flags/mcal/e21cdbd061847d80342fbfe5463c9e80fd36331b .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/22353991" + @${RM} ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o.d + @${RM} ${OBJECTDIR}/_ext/22353991/TP_NetworkLayerLowerInterface_Tx.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" 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-I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/624783131/SA51024.o.d" -o ${OBJECTDIR}/_ext/624783131/SA51024.o ../src/Speaker/SA51024.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) 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"${OBJECTDIR}/_ext/798729495/TLE926x_Main.o.d" -o ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o ../src/TLE9263/TLE926x_Main.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1720498337/TouchPanel.o: ../src/TouchPanel/TouchPanel.c .generated_files/flags/mcal/90c7a666987a149a0bf95c7ae190af33b9d21b6f .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1720498337" + @${RM} ${OBJECTDIR}/_ext/1720498337/TouchPanel.o.d + @${RM} ${OBJECTDIR}/_ext/1720498337/TouchPanel.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1720498337/TouchPanel.o.d" -o ${OBJECTDIR}/_ext/1720498337/TouchPanel.o ../src/TouchPanel/TouchPanel.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1360937237/main.o: ../src/main.c .generated_files/flags/mcal/8ab33370a9c8da4b0400db4bf658f4a4391f10d8 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1360937237" + @${RM} ${OBJECTDIR}/_ext/1360937237/main.o.d + @${RM} ${OBJECTDIR}/_ext/1360937237/main.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +else +${OBJECTDIR}/_ext/1958549552/calib.o: ../src/Calibration/calib.c .generated_files/flags/mcal/50c066d9583f5deb15a2fec4b93429c06dc409ad .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1958549552" + @${RM} ${OBJECTDIR}/_ext/1958549552/calib.o.d + @${RM} ${OBJECTDIR}/_ext/1958549552/calib.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1958549552/calib.o.d" -o ${OBJECTDIR}/_ext/1958549552/calib.o ../src/Calibration/calib.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982922760/plib_adc0.o: ../src/config/mcal/peripheral/adc/plib_adc0.c .generated_files/flags/mcal/f1640a5d2b24984700fe49c22d1c373ca02b85db .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982922760" + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc0.o.d + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc0.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982922760/plib_adc0.o.d" -o ${OBJECTDIR}/_ext/1982922760/plib_adc0.o ../src/config/mcal/peripheral/adc/plib_adc0.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982922760/plib_adc1.o: ../src/config/mcal/peripheral/adc/plib_adc1.c .generated_files/flags/mcal/e2083944fc74f8e7b06bed7c9feb832143b407aa .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982922760" + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc1.o.d + @${RM} ${OBJECTDIR}/_ext/1982922760/plib_adc1.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982922760/plib_adc1.o.d" -o ${OBJECTDIR}/_ext/1982922760/plib_adc1.o ../src/config/mcal/peripheral/adc/plib_adc1.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982924600/plib_can1.o: ../src/config/mcal/peripheral/can/plib_can1.c .generated_files/flags/mcal/a462457cfb8a2ffe8f7174c398067b0475de1c3 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982924600" + @${RM} ${OBJECTDIR}/_ext/1982924600/plib_can1.o.d + @${RM} ${OBJECTDIR}/_ext/1982924600/plib_can1.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982924600/plib_can1.o.d" -o ${OBJECTDIR}/_ext/1982924600/plib_can1.o ../src/config/mcal/peripheral/can/plib_can1.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1374606986/plib_clock.o: ../src/config/mcal/peripheral/clock/plib_clock.c .generated_files/flags/mcal/6de560ebcfb77db7c7dbe09fdca778a5a30e428f .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1374606986" + @${RM} ${OBJECTDIR}/_ext/1374606986/plib_clock.o.d + @${RM} ${OBJECTDIR}/_ext/1374606986/plib_clock.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1374606986/plib_clock.o.d" -o ${OBJECTDIR}/_ext/1374606986/plib_clock.o ../src/config/mcal/peripheral/clock/plib_clock.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341131746/plib_cmcc.o: ../src/config/mcal/peripheral/cmcc/plib_cmcc.c .generated_files/flags/mcal/f6e01ae9f9bfa5f8fbb092ce0cd504a4a19ea79c .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341131746" + @${RM} ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o.d + @${RM} ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341131746/plib_cmcc.o.d" -o ${OBJECTDIR}/_ext/1341131746/plib_cmcc.o ../src/config/mcal/peripheral/cmcc/plib_cmcc.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982925550/plib_dac.o: ../src/config/mcal/peripheral/dac/plib_dac.c .generated_files/flags/mcal/a5777412b001c6f24e0a7825d0b845af22b4e027 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982925550" + @${RM} ${OBJECTDIR}/_ext/1982925550/plib_dac.o.d + @${RM} ${OBJECTDIR}/_ext/1982925550/plib_dac.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982925550/plib_dac.o.d" -o ${OBJECTDIR}/_ext/1982925550/plib_dac.o ../src/config/mcal/peripheral/dac/plib_dac.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1372457500/plib_evsys.o: ../src/config/mcal/peripheral/evsys/plib_evsys.c .generated_files/flags/mcal/11a87519a3fb10a0fbaadaa4772a4510c0eebf22 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1372457500" + @${RM} ${OBJECTDIR}/_ext/1372457500/plib_evsys.o.d + @${RM} ${OBJECTDIR}/_ext/1372457500/plib_evsys.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1372457500/plib_evsys.o.d" -o ${OBJECTDIR}/_ext/1372457500/plib_evsys.o ../src/config/mcal/peripheral/evsys/plib_evsys.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341468282/plib_nvic.o: ../src/config/mcal/peripheral/nvic/plib_nvic.c .generated_files/flags/mcal/803488213ab0fabbf932a49ac5822470d80bac92 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341468282" + @${RM} ${OBJECTDIR}/_ext/1341468282/plib_nvic.o.d + @${RM} ${OBJECTDIR}/_ext/1341468282/plib_nvic.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341468282/plib_nvic.o.d" -o ${OBJECTDIR}/_ext/1341468282/plib_nvic.o ../src/config/mcal/peripheral/nvic/plib_nvic.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o: ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c .generated_files/flags/mcal/6576b4b7a2488e18a544bc4e641270db8a117feb .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/985291016" + @${RM} ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o.d + @${RM} ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o.d" -o ${OBJECTDIR}/_ext/985291016/plib_nvmctrl.o ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1341521433/plib_port.o: ../src/config/mcal/peripheral/port/plib_port.c .generated_files/flags/mcal/38aac6b319ee2a461072e122e9c2e53f1fe8ab6e .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1341521433" + @${RM} ${OBJECTDIR}/_ext/1341521433/plib_port.o.d + @${RM} ${OBJECTDIR}/_ext/1341521433/plib_port.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1341521433/plib_port.o.d" -o ${OBJECTDIR}/_ext/1341521433/plib_port.o ../src/config/mcal/peripheral/port/plib_port.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o: ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c .generated_files/flags/mcal/2e7d415edab7d6b7fdabd99e4271ecf81122778e .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1982939593" + @${RM} ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o.d + @${RM} ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o.d" -o ${OBJECTDIR}/_ext/1982939593/plib_rtc_timer.o ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o: 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-I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o.d" -o ${OBJECTDIR}/_ext/24027325/plib_sercom1_i2c_master.o ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o: ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c .generated_files/flags/mcal/6bddc0229b619be8d795df35d51fd52a2345767d .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/467207317" + @${RM} ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o.d + @${RM} ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c 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-I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o.d" -o ${OBJECTDIR}/_ext/467207317/plib_sercom0_spi_master.o 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-I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1802317902/Dem_Extension.o.d" -o ${OBJECTDIR}/_ext/1802317902/Dem_Extension.o ../src/DiagnosticR/Dem/Dem_Extension.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1802317902/Dem_LCfg.o: ../src/DiagnosticR/Dem/Dem_LCfg.c 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-I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" 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-I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/659835465/RTE.o.d" -o ${OBJECTDIR}/_ext/659835465/RTE.o ../src/RTE/RTE.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" 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${OBJECTDIR}/_ext/798729495/TLE926x.o ../src/TLE9263/TLE926x.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o: ../src/TLE9263/TLE926x_SPI.c .generated_files/flags/mcal/3a4c064546d130657fdba830964f3dab97e15a34 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/798729495" + @${RM} ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o.d + @${RM} ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o.d" -o ${OBJECTDIR}/_ext/798729495/TLE926x_SPI.o ../src/TLE9263/TLE926x_SPI.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/798729495/TLE926x_Main.o: ../src/TLE9263/TLE926x_Main.c .generated_files/flags/mcal/d5fc1b9dc39df6f7deff508a0e0476c40cb72be6 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/798729495" + @${RM} ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o.d + @${RM} ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/798729495/TLE926x_Main.o.d" -o ${OBJECTDIR}/_ext/798729495/TLE926x_Main.o ../src/TLE9263/TLE926x_Main.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1720498337/TouchPanel.o: ../src/TouchPanel/TouchPanel.c .generated_files/flags/mcal/26a817df27e09f6e375202d8452d8a436b67f7a2 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1720498337" + @${RM} ${OBJECTDIR}/_ext/1720498337/TouchPanel.o.d + @${RM} ${OBJECTDIR}/_ext/1720498337/TouchPanel.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1720498337/TouchPanel.o.d" -o ${OBJECTDIR}/_ext/1720498337/TouchPanel.o ../src/TouchPanel/TouchPanel.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +${OBJECTDIR}/_ext/1360937237/main.o: ../src/main.c .generated_files/flags/mcal/a69208d30d3648a9adafb0cce4dc8ddff2273171 .generated_files/flags/mcal/19aca898974f639a5713d79f6a59fd61d4a277f5 + @${MKDIR} "${OBJECTDIR}/_ext/1360937237" + @${RM} ${OBJECTDIR}/_ext/1360937237/main.o.d + @${RM} ${OBJECTDIR}/_ext/1360937237/main.o + ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -fdata-sections -fno-toplevel-reorder -fno-common -I"../src" -I"../src/config/mcal" -I"../src/packs/ATSAME51J19A_DFP" -I"../src/packs/CMSIS/" -I"../src/packs/CMSIS/CMSIS/Core/Include" -I"../src/Calibration" -I"../src/DiagnosticR" -I"../src/DiagnosticR/Comp_HAL_Autosar_Wrappers" -I"../src/DiagnosticR/Comp_ISO_15765_2" -I"../src/DiagnosticR/Comp_ISO_15765_3" -I"../src/DiagnosticR/Dem" -I"../src/DiagnosticR/FicOsek" -I"../src/DiagnosticR/Sys_Diag_Detect" -I"../src/DiagnosticR/UDS" -I"../src/DiagnosticR/UDS/Iso15765_layer2" -I"../src/DiagnosticR/UDS/Iso15765_layer3" -I"../src/DiagnosticR/UDS/Iso15765_layer3/_h61" -I"../src/DiagnosticR/UDS/ModelsInterfaces" -I"../src/DiagnosticR/_configurations" -I"../src/DiagnosticR/rte" -I"../src/FunctionState" -I"../src/OsekCom" -I"../src/P417_SWTR_App_ert_rtw" -I"../src/RTE" -I"../src/Speaker" -I"../src/TLE9263" -I"../src/TouchPanel" -I"../src/config/mcal/mcal.mhc" -I"../src/config/mcal/peripheral/adc" -I"../src/config/mcal/peripheral/can" -I"../src/config/mcal/peripheral/clock" -I"../src/config/mcal/peripheral/cmcc" -I"../src/config/mcal/peripheral/dac" -I"../src/config/mcal/peripheral/evsys" -I"../src/config/mcal/peripheral/nvic" -I"../src/config/mcal/peripheral/nvmctrl" -I"../src/config/mcal/peripheral/port" -I"../src/config/mcal/peripheral/rtc" -I"../src/config/mcal/peripheral/sercom" -I"../src/config/mcal/peripheral/systick" -I"../src/config/mcal/peripheral/tc" -I"../src/config/mcal/peripheral/tcc" -I"../src/config/mcal/stdio" -I"../src/config/mcal/touch" -I"../src/config/mcal/touch/lib" -I"../src/forceSnsr" -I"../src/packs/ATSAME51J19A_DFP/component" -I"../src/packs/ATSAME51J19A_DFP/instance" -I"../src/packs/ATSAME51J19A_DFP/pio" -I"../src/smartEE" -Werror -Wall -MP -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -mdfp="${DFP_DIR}" ${PACK_COMMON_OPTIONS} + +endif + +# ------------------------------------------------------------------------------------ +# Rules for buildStep: compileCPP +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +else +endif + +# ------------------------------------------------------------------------------------ +# Rules for buildStep: link +ifeq ($(TYPE_IMAGE), DEBUG_RUN) +${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk ../src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a ../src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a ../src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a ../src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a ../src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a ../src/config/mcal/ATSAME51J19A.ld + @${MKDIR} ${DISTDIR} + ${MP_CC} $(MP_EXTRA_LD_PRE) -g -mprocessor=$(MP_PROCESSOR_OPTION) -mno-device-startup-code -o ${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} ${OBJECTFILES_QUOTED_IF_SPACED} ..\src\config\mcal\touch\lib\qtm_acq_same51_0x000f.X.a ..\src\config\mcal\touch\lib\qtm_touch_key_cm4_0x0002.X.a ..\src\config\mcal\touch\lib\qtm_scroller_cm4_0x000b.X.a ..\src\config\mcal\touch\lib\qtm_freq_hop_cm4_0x0006.X.a ..\src\config\mcal\touch\lib\qtm_surface_cs_cm4_0x0021.X.a -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -Wl,--defsym=__MPLAB_BUILD=1$(MP_EXTRA_LD_POST)$(MP_LINKER_FILE_OPTION),--defsym=__ICD2RAM=1,--defsym=__MPLAB_DEBUG=1,--defsym=__DEBUG=1,-D=__DEBUG_D,--defsym=_min_heap_size=512,--gc-sections,-Map="${DISTDIR}/${PROJECTNAME}.${IMAGE_TYPE}.map",--memorysummary,${DISTDIR}/memoryfile.xml -mdfp="${DFP_DIR}" + +else +${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk ../src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a ../src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a ../src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a ../src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a ../src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a ../src/config/mcal/ATSAME51J19A.ld + @${MKDIR} ${DISTDIR} + ${MP_CC} $(MP_EXTRA_LD_PRE) -mprocessor=$(MP_PROCESSOR_OPTION) -mno-device-startup-code -o ${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} ${OBJECTFILES_QUOTED_IF_SPACED} ..\src\config\mcal\touch\lib\qtm_acq_same51_0x000f.X.a ..\src\config\mcal\touch\lib\qtm_touch_key_cm4_0x0002.X.a ..\src\config\mcal\touch\lib\qtm_scroller_cm4_0x000b.X.a ..\src\config\mcal\touch\lib\qtm_freq_hop_cm4_0x0006.X.a ..\src\config\mcal\touch\lib\qtm_surface_cs_cm4_0x0021.X.a -DXPRJ_mcal=$(CND_CONF) $(COMPARISON_BUILD) -Wl,--defsym=__MPLAB_BUILD=1$(MP_EXTRA_LD_POST)$(MP_LINKER_FILE_OPTION),--defsym=_min_heap_size=512,--gc-sections,-Map="${DISTDIR}/${PROJECTNAME}.${IMAGE_TYPE}.map",--memorysummary,${DISTDIR}/memoryfile.xml -mdfp="${DFP_DIR}" + ${MP_CC_DIR}\\xc32-bin2hex ${DISTDIR}/p417_SWTR.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} +endif + + +# Subprojects +.build-subprojects: + + +# Subprojects +.clean-subprojects: + +# Clean Targets +.clean-conf: ${CLEAN_SUBPROJECTS} + ${RM} -r ${OBJECTDIR} + ${RM} -r ${DISTDIR} + +# Enable dependency checking +.dep.inc: .depcheck-impl + +DEPFILES=$(shell mplabwildcard ${POSSIBLE_DEPFILES}) +ifneq (${DEPFILES},) +include ${DEPFILES} +endif diff --git a/firmware/p417_SWTR.X/nbproject/Makefile-variables.mk b/firmware/p417_SWTR.X/nbproject/Makefile-variables.mk new file mode 100644 index 0000000..73b86e0 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Makefile-variables.mk @@ -0,0 +1,10 @@ +# +# Generated - do not edit! +# +# NOCDDL +# +CND_BASEDIR=`pwd` +# mcal configuration +CND_ARTIFACT_DIR_mcal=dist/mcal/production +CND_ARTIFACT_NAME_mcal=p417_SWTR.X.production.hex +CND_ARTIFACT_PATH_mcal=dist/mcal/production/p417_SWTR.X.production.hex diff --git a/firmware/p417_SWTR.X/nbproject/Package-mcal.bash b/firmware/p417_SWTR.X/nbproject/Package-mcal.bash new file mode 100644 index 0000000..cc2cc64 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/Package-mcal.bash @@ -0,0 +1,73 @@ +#!/bin/bash -x + +# +# Generated - do not edit! +# + +# Macros +TOP=`pwd` +CND_CONF=mcal +CND_DISTDIR=dist +TMPDIR=build/${CND_CONF}/${IMAGE_TYPE}/tmp-packaging +TMPDIRNAME=tmp-packaging +OUTPUT_PATH=dist/${CND_CONF}/${IMAGE_TYPE}/p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} +OUTPUT_BASENAME=p417_SWTR.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX} +PACKAGE_TOP_DIR=p417swtr.x/ + +# Functions +function checkReturnCode +{ + rc=$? + if [ $rc != 0 ] + then + exit $rc + fi +} +function makeDirectory +# $1 directory path +# $2 permission (optional) +{ + mkdir -p "$1" + checkReturnCode + if [ "$2" != "" ] + then + chmod $2 "$1" + checkReturnCode + fi +} +function copyFileToTmpDir +# $1 from-file path +# $2 to-file path +# $3 permission +{ + cp "$1" "$2" + checkReturnCode + if [ "$3" != "" ] + then + chmod $3 "$2" + checkReturnCode + fi +} + +# Setup +cd "${TOP}" +mkdir -p ${CND_DISTDIR}/${CND_CONF}/package +rm -rf ${TMPDIR} +mkdir -p ${TMPDIR} + +# Copy files and create directories and links +cd "${TOP}" +makeDirectory ${TMPDIR}/p417swtr.x/bin +copyFileToTmpDir "${OUTPUT_PATH}" "${TMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 + + +# Generate tar file +cd "${TOP}" +rm -f ${CND_DISTDIR}/${CND_CONF}/package/p417swtr.x.tar +cd ${TMPDIR} +tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/package/p417swtr.x.tar * +checkReturnCode + +# Cleanup +cd "${TOP}" +rm -rf ${TMPDIR} diff --git a/firmware/p417_SWTR.X/nbproject/configurations.xml b/firmware/p417_SWTR.X/nbproject/configurations.xml new file mode 100644 index 0000000..3be1b6c --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/configurations.xml @@ -0,0 +1,1747 @@ + + + + + + + + + ../src/config/mcal/peripheral/adc/plib_adc_common.h + ../src/config/mcal/peripheral/adc/plib_adc0.h + ../src/config/mcal/peripheral/adc/plib_adc1.h + + + ../src/config/mcal/peripheral/can/plib_can_common.h + ../src/config/mcal/peripheral/can/plib_can1.h + + + ../src/config/mcal/peripheral/clock/plib_clock.h + + + ../src/config/mcal/peripheral/cmcc/plib_cmcc.h + + + ../src/config/mcal/peripheral/dac/plib_dac.h + + + ../src/config/mcal/peripheral/evsys/plib_evsys.h + + + ../src/config/mcal/peripheral/nvic/plib_nvic.h + + + ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.h + + + ../src/config/mcal/peripheral/port/plib_port.h + + + ../src/config/mcal/peripheral/rtc/plib_rtc.h + + + + ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h + ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h + + + ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.h + ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h + + + + ../src/config/mcal/peripheral/systick/plib_systick.h + + + ../src/config/mcal/peripheral/tc/plib_tc_common.h + ../src/config/mcal/peripheral/tc/plib_tc0.h + + + ../src/config/mcal/peripheral/tcc/plib_tcc0.h + ../src/config/mcal/peripheral/tcc/plib_tcc_common.h + + + ../src/config/mcal/peripheral/wdt/plib_wdt.h + + + + ../src/config/mcal/touch/qtm_acq_same51_0x000f_api.h + ../src/config/mcal/touch/qtm_acq_same54_0x000f_api.h + ../src/config/mcal/touch/qtm_common_components_api.h + ../src/config/mcal/touch/qtm_touch_key_0x0002_api.h + ../src/config/mcal/touch/qtm_freq_hop_0x0006_api.h + ../src/config/mcal/touch/qtm_surface_cs_0x0021_api.h + ../src/config/mcal/touch/touch.h + ../src/config/mcal/touch/touch_api_ptc.h + ../src/config/mcal/touch/touch_example.h + ../src/config/mcal/touch/qtm_scroller_0x000b_api.h + + ../src/config/mcal/device.h + ../src/config/mcal/device_cache.h + ../src/config/mcal/toolchain_specifics.h + ../src/config/mcal/definitions.h + ../src/config/mcal/interrupts.h + ../src/config/mcal/device_vectors.h + + + + + + ../src/packs/ATSAME51J19A_DFP/component/ac.h + ../src/packs/ATSAME51J19A_DFP/component/adc.h + ../src/packs/ATSAME51J19A_DFP/component/aes.h + ../src/packs/ATSAME51J19A_DFP/component/can.h + ../src/packs/ATSAME51J19A_DFP/component/ccl.h + ../src/packs/ATSAME51J19A_DFP/component/cmcc.h + ../src/packs/ATSAME51J19A_DFP/component/dac.h + ../src/packs/ATSAME51J19A_DFP/component/dmac.h + ../src/packs/ATSAME51J19A_DFP/component/dsu.h + ../src/packs/ATSAME51J19A_DFP/component/eic.h + ../src/packs/ATSAME51J19A_DFP/component/evsys.h + ../src/packs/ATSAME51J19A_DFP/component/freqm.h + ../src/packs/ATSAME51J19A_DFP/component/fuses.h + ../src/packs/ATSAME51J19A_DFP/component/gclk.h + ../src/packs/ATSAME51J19A_DFP/component/hmatrixb.h + ../src/packs/ATSAME51J19A_DFP/component/i2s.h + ../src/packs/ATSAME51J19A_DFP/component/icm.h + ../src/packs/ATSAME51J19A_DFP/component/mclk.h + ../src/packs/ATSAME51J19A_DFP/component/nvmctrl.h + ../src/packs/ATSAME51J19A_DFP/component/osc32kctrl.h + ../src/packs/ATSAME51J19A_DFP/component/oscctrl.h + ../src/packs/ATSAME51J19A_DFP/component/pac.h + ../src/packs/ATSAME51J19A_DFP/component/pcc.h + ../src/packs/ATSAME51J19A_DFP/component/pdec.h + ../src/packs/ATSAME51J19A_DFP/component/pm.h + ../src/packs/ATSAME51J19A_DFP/component/port.h + ../src/packs/ATSAME51J19A_DFP/component/pukcc.h + ../src/packs/ATSAME51J19A_DFP/component/qspi.h + ../src/packs/ATSAME51J19A_DFP/component/ramecc.h + ../src/packs/ATSAME51J19A_DFP/component/rstc.h + ../src/packs/ATSAME51J19A_DFP/component/rtc.h + ../src/packs/ATSAME51J19A_DFP/component/sdhc.h + ../src/packs/ATSAME51J19A_DFP/component/sercom.h + ../src/packs/ATSAME51J19A_DFP/component/supc.h + ../src/packs/ATSAME51J19A_DFP/component/tc.h + ../src/packs/ATSAME51J19A_DFP/component/tcc.h + ../src/packs/ATSAME51J19A_DFP/component/trng.h + ../src/packs/ATSAME51J19A_DFP/component/usb.h + ../src/packs/ATSAME51J19A_DFP/component/wdt.h + + + ../src/packs/ATSAME51J19A_DFP/instance/ac.h + ../src/packs/ATSAME51J19A_DFP/instance/adc0.h + ../src/packs/ATSAME51J19A_DFP/instance/adc1.h + ../src/packs/ATSAME51J19A_DFP/instance/aes.h + ../src/packs/ATSAME51J19A_DFP/instance/can0.h + ../src/packs/ATSAME51J19A_DFP/instance/can1.h + ../src/packs/ATSAME51J19A_DFP/instance/ccl.h + ../src/packs/ATSAME51J19A_DFP/instance/cmcc.h + ../src/packs/ATSAME51J19A_DFP/instance/dac.h + ../src/packs/ATSAME51J19A_DFP/instance/dmac.h + ../src/packs/ATSAME51J19A_DFP/instance/dsu.h + ../src/packs/ATSAME51J19A_DFP/instance/eic.h + ../src/packs/ATSAME51J19A_DFP/instance/evsys.h + ../src/packs/ATSAME51J19A_DFP/instance/freqm.h + ../src/packs/ATSAME51J19A_DFP/instance/fuses.h + ../src/packs/ATSAME51J19A_DFP/instance/gclk.h + ../src/packs/ATSAME51J19A_DFP/instance/hmatrix.h + ../src/packs/ATSAME51J19A_DFP/instance/i2s.h + ../src/packs/ATSAME51J19A_DFP/instance/icm.h + ../src/packs/ATSAME51J19A_DFP/instance/mclk.h + ../src/packs/ATSAME51J19A_DFP/instance/nvmctrl.h + ../src/packs/ATSAME51J19A_DFP/instance/osc32kctrl.h + ../src/packs/ATSAME51J19A_DFP/instance/oscctrl.h + ../src/packs/ATSAME51J19A_DFP/instance/pac.h + ../src/packs/ATSAME51J19A_DFP/instance/pcc.h + ../src/packs/ATSAME51J19A_DFP/instance/pdec.h + ../src/packs/ATSAME51J19A_DFP/instance/pm.h + ../src/packs/ATSAME51J19A_DFP/instance/port.h + ../src/packs/ATSAME51J19A_DFP/instance/qspi.h + ../src/packs/ATSAME51J19A_DFP/instance/ramecc.h + ../src/packs/ATSAME51J19A_DFP/instance/rstc.h + ../src/packs/ATSAME51J19A_DFP/instance/rtc.h + ../src/packs/ATSAME51J19A_DFP/instance/sdhc0.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom0.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom1.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom2.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom3.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom4.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom5.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom6.h + ../src/packs/ATSAME51J19A_DFP/instance/sercom7.h + ../src/packs/ATSAME51J19A_DFP/instance/supc.h + ../src/packs/ATSAME51J19A_DFP/instance/tc0.h + ../src/packs/ATSAME51J19A_DFP/instance/tc1.h + ../src/packs/ATSAME51J19A_DFP/instance/tc2.h + ../src/packs/ATSAME51J19A_DFP/instance/tc3.h + ../src/packs/ATSAME51J19A_DFP/instance/tc4.h + ../src/packs/ATSAME51J19A_DFP/instance/tc5.h + ../src/packs/ATSAME51J19A_DFP/instance/tc6.h + ../src/packs/ATSAME51J19A_DFP/instance/tc7.h + ../src/packs/ATSAME51J19A_DFP/instance/tcc0.h + ../src/packs/ATSAME51J19A_DFP/instance/tcc1.h + ../src/packs/ATSAME51J19A_DFP/instance/tcc2.h + ../src/packs/ATSAME51J19A_DFP/instance/tcc3.h + ../src/packs/ATSAME51J19A_DFP/instance/tcc4.h + ../src/packs/ATSAME51J19A_DFP/instance/trng.h + ../src/packs/ATSAME51J19A_DFP/instance/usb.h + ../src/packs/ATSAME51J19A_DFP/instance/wdt.h + + + ../src/packs/ATSAME51J19A_DFP/pio/same51j19a.h + + ../src/packs/ATSAME51J19A_DFP/same51j19a.h + + + + + + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h + ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h + ../src/packs/CMSIS/CMSIS/Core/Include/core_cm4.h + ../src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h + ../src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h + + + + + + + + + + ../src/config/mcal/ATSAME51J19A.ld + + + + + + ../src/Calibration/calib.c + + + + + + ../src/config/mcal/peripheral/adc/plib_adc0.c + ../src/config/mcal/peripheral/adc/plib_adc1.c + + + ../src/config/mcal/peripheral/can/plib_can1.c + + + ../src/config/mcal/peripheral/clock/plib_clock.c + + + ../src/config/mcal/peripheral/cmcc/plib_cmcc.c + + + ../src/config/mcal/peripheral/dac/plib_dac.c + + + ../src/config/mcal/peripheral/evsys/plib_evsys.c + + + ../src/config/mcal/peripheral/nvic/plib_nvic.c + + + ../src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c + + + ../src/config/mcal/peripheral/port/plib_port.c + + + ../src/config/mcal/peripheral/rtc/plib_rtc_timer.c + + + + ../src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c + + + ../src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c + + + + ../src/config/mcal/peripheral/systick/plib_systick.c + + + ../src/config/mcal/peripheral/tc/plib_tc0.c + + + ../src/config/mcal/peripheral/tcc/plib_tcc0.c + + + ../src/config/mcal/peripheral/wdt/plib_wdt.c + + + + ../src/config/mcal/stdio/xc32_monitor.c + + + ../src/config/mcal/touch/touch.c + ../src/config/mcal/touch/touch_example.c + + ../src/config/mcal/initialization.c + ../src/config/mcal/interrupts.c + ../src/config/mcal/exceptions.c + ../src/config/mcal/startup_xc32.c + ../src/config/mcal/libc_syscalls.c + + + + + + + ../src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c + + + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c + ../src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c + + + ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c + ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c + ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c + ../src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c + + + ../src/DiagnosticR/Dem/Dem.c + ../src/DiagnosticR/Dem/Dem_Debounce.c + ../src/DiagnosticR/Dem/Dem_Extension.c + ../src/DiagnosticR/Dem/Dem_LCfg.c + + + + + + + ../src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c + + + + ../src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c + + + + ../src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c + + + + + ../src/DiagnosticR/UDS/UDS_CoreServices_CB.c + ../src/DiagnosticR/UDS/UDS_DIDNvm.c + ../src/DiagnosticR/UDS/UDS_DiDRead_CB.c + ../src/DiagnosticR/UDS/UDS_DiDWrite_CB.c + ../src/DiagnosticR/UDS/UDS_IORoutineControl.c + ../src/DiagnosticR/UDS/UDS_Services_Common.c + + + + ../src/forceSnsr/forcedetect.c + ../src/forceSnsr/forceSnsr.c + ../src/forceSnsr/forceSnsr_Cfg.c + + + ../src/FunctionState/FunctionState.c + + + ../src/OsekCom/OsekCom.c + + + ../src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c + ../src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c + ../src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c + ../src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c + ../src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c + ../src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c + ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c + ../src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c + ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c + ../src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c + ../src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c + ../src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c + ../src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c + + + ../src/RTE/RTE.c + + + ../src/smartEE/smartee.c + + + ../src/Speaker/SA51024.c + ../src/Speaker/SA51024_Cfg.c + ../src/Speaker/Speaker.c + + + ../src/TLE9263/TLE926x.c + ../src/TLE9263/TLE926x_SPI.c + ../src/TLE9263/TLE926x_Main.c + + + ../src/TouchPanel/TouchPanel.c + + ../src/main.c + + + + ../src/config/mcal/mcal.mhc/adc0.yml + ../src/config/mcal/mcal.mhc/adc1.yml + ../src/config/mcal/mcal.mhc/can1.yml + ../src/config/mcal/mcal.mhc/cmsis.yml + ../src/config/mcal/mcal.mhc/core.yml + ../src/config/mcal/mcal.mhc/dac.yml + ../src/config/mcal/mcal.mhc/dfp.yml + ../src/config/mcal/mcal.mhc/evsys.yml + ../src/config/mcal/mcal.mhc/GraphSettings.yml + ../src/config/mcal/mcal.mhc/lib_qtouch.yml + ../src/config/mcal/mcal.mhc/nvmctrl.yml + ../src/config/mcal/mcal.mhc/project.yml + ../src/config/mcal/mcal.mhc/ptc.yml + ../src/config/mcal/mcal.mhc/rtc.yml + ../src/config/mcal/mcal.mhc/sercom0.yml + ../src/config/mcal/mcal.mhc/sercom1.yml + ../src/config/mcal/mcal.mhc/settings.yml + ../src/config/mcal/mcal.mhc/tc0.yml + ../src/config/mcal/mcal.mhc/tcc0.yml + + Makefile + ../src/config/mcal/harmony-manifest-success.yml + ../src/config/mcal/pin_configurations.csv + + + + ../src + ../../../P417_SWTL/firmware/src/DiagnosticL + ../../../P417_SWTL/firmware/src/Calibration + ../../../P417_SWTL/firmware/src/smartEE + + Makefile + + + + localhost + ATSAME51J19A + + + noID + XC32 + 4.10 + 3 + + + + + + + + + + + ../src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a + ../src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a + ../src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a + ../src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a + ../src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a + + + + + + false + false + + + + + + + false + false + + false + + false + false + false + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/p417_SWTR.X/nbproject/private/.LCKconfigurations.xml~ b/firmware/p417_SWTR.X/nbproject/private/.LCKconfigurations.xml~ new file mode 100644 index 0000000..5f0342a --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/private/.LCKconfigurations.xml~ @@ -0,0 +1 @@ +F:\FCB_project\P417\CODE\20231017\P417_SWTR\firmware\p417_SWTR.X\nbproject\private\configurations.xml \ No newline at end of file diff --git a/firmware/p417_SWTR.X/nbproject/private/configurations.xml b/firmware/p417_SWTR.X/nbproject/private/configurations.xml new file mode 100644 index 0000000..38270a8 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/private/configurations.xml @@ -0,0 +1,25 @@ + + + Makefile + 0 + + + noToolString + E:\Program Files\Microchip\xc32\v4.10\bin + + place holder 1 + place holder 2 + + + + + true + 0 + 0 + 0 + + + + + + diff --git a/firmware/p417_SWTR.X/nbproject/private/private.xml b/firmware/p417_SWTR.X/nbproject/private/private.xml new file mode 100644 index 0000000..52917f6 --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/private/private.xml @@ -0,0 +1,9 @@ + + + + + + file:/F:/FCB_project/P417/CODE/20240523/MCC_TEST/P417_SWTL/firmware/src/DiagnosticL/Sys_Diag_Detect/SysDiagDetect.c + + + diff --git a/firmware/p417_SWTR.X/nbproject/project.properties b/firmware/p417_SWTR.X/nbproject/project.properties new file mode 100644 index 0000000..e69de29 diff --git a/firmware/p417_SWTR.X/nbproject/project.xml b/firmware/p417_SWTR.X/nbproject/project.xml new file mode 100644 index 0000000..f57127b --- /dev/null +++ b/firmware/p417_SWTR.X/nbproject/project.xml @@ -0,0 +1,32 @@ + + + com.microchip.mplab.nbide.embedded.makeproject + + + p417_SWTR + e54023e9-3948-44ef-bf6f-29d8b223e555 + 0 + c + + h + + ISO-8859-1 + + + ../src + ../../../P417_SWTL/firmware/src/DiagnosticL + ../../../P417_SWTL/firmware/src/Calibration + ../../../P417_SWTL/firmware/src/smartEE + + + + mcal + 2 + + + + false + + + + diff --git a/firmware/src/Calibration/calib.c b/firmware/src/Calibration/calib.c new file mode 100644 index 0000000..7d94bb8 --- /dev/null +++ b/firmware/src/Calibration/calib.c @@ -0,0 +1,100 @@ +#include "calib_public.h" +#include "calib_private.h" + +int8_t Calib_Init(void) +{ + int8_t ret = 0; + uint8_t i = 0; + + for(i=0; i= Calib_Buffer_size) + { + CalibDataCtl[i].data.def.value = Calib_FilterData(CalibDataCtl[i].buffer); + CalibDataCtl[i].data.def.sign = Calib_Data_Sign; + Calib_Write(CalibDataCtl[i].addr, CalibDataCtl[i].data.byte, Calib_Data_Size); + CalibDataCtl[i].status &= ~Calib_RequestBit; + CalibDataCtl[i].status |= Calib_FinishedBit; + CalibDataCtl[i].index = 0; + } + } + } +} + +int8_t Calib_Trigger(uint8_t index, uint16_t data) +{ + int8_t ret = 0; + + if(data > 0) + { + CalibDataCtl[index].data.def.value = data; + CalibDataCtl[index].data.def.sign = Calib_Data_Sign; + Calib_Write(CalibDataCtl[index].addr, CalibDataCtl[index].data.byte, Calib_Data_Size); + }else + { + CalibDataCtl[index].status |= Calib_RequestBit; + } + + return ret; +} + +int8_t Calib_FinishCheck(uint8_t index) +{ + int8_t ret = -1; + + if((CalibDataCtl[index].status&Calib_FinishedBit) == Calib_FinishedBit) + { + CalibDataCtl[index].status = 0; + ret = 0; + } + + return ret; +} + +uint16_t Calib_FilterData(uint16_t * data) +{ + uint32_t Sum = 0; + uint8_t i = 0; + + for(i=0; i a notification is required +| FALSE -> no notification requiered +| idtp: Idtp of the frame that will be transmited +| len: Data bytes length of the frame +| can_data: Adress of the variable that have the data to be transmited. If +| no data is wanted to be transmited, the user can put a 0 in the +| len parameter and a NULL in the can_data parameter. +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: TBD cpu cycles | O(n): CTE +| Tmax Int En : TBD cpu cycles | O(n): CTE +| Tmax Total : TBD cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +//void CanTx(t_can_handler can_handler, BOOL notif, t_idtp idtp, UI_8 len,t_can_data can_data); + + +/***************************************************************************** +| Routine: CanReadStatus +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to check the current CAN driver state +|--------------------------------------------------------------------------- +| Parameters explanation: +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: TBD cpu cycles | O(n): CTE +| Tmax Int En : TBD cpu cycles | O(n): CTE +| Tmax Total : TBD cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_can_status CanReadStatus(t_can_handler can_handler); + + +/***************************************************************************** +| Routine: CanBufQueryDataLen +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to get the hw buffer status. +|--------------------------------------------------------------------------- +| Parameters explanation: +| can_handler: Identifier of CAN handler +| result: TRUE - buffer free +| FALSE - buffer full +/---------------------------------------------------------------------------*/ +BOOL CanQueryTxBufEmpty(t_can_handler can_handler); + + +/***************************************************************************** +| Routine: CanBufQueryDataLen +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to get a hardware buffer data length. +|--------------------------------------------------------------------------- +| Parameters explanation: +| bhdl: buffer hardware handler from which the information is required +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: TBD cpu cycles | O(n): CTE +| Tmax Int En : TBD cpu cycles | O(n): CTE +| Tmax Total : TBD cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ + +#define CAN_BUF_QUERY_DATA_LEN(HwCtl, bhdl) (CanBufQueryDataLen(HwCtl, bhdl)) +UI_8 CanBufQueryDataLen(t_can_handler can_handler, t_can_buf_hdl bhdl); + +/***************************************************************************** +| Routine: CanBufQueryDataByte +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to get a hardware buffer data bytes. +|--------------------------------------------------------------------------- +| Parameters explanation: +| bhdl: buffer hardware handler from which the information is required +| byte: data byte index required [0..7] +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: TBD cpu cycles | O(n): CTE +| Tmax Int En : TBD cpu cycles | O(n): CTE +| Tmax Total : TBD cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +//#define CAN_BUF_QUERY_DATA_BYTE(HwCtl, bhdl, byte) (CanBufQueryDataByte(HwCtl, bhdl, byte)) +//UI_8 CanBufQueryDataByte(t_can_handler can_handler, t_can_buf_hdl bhdl, UI_8 index); + +/***************************************************************************** +| Routine: CanQueryRxActivity +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine that says if there was CAN activity since last check +|--------------------------------------------------------------------------- +| Parameters explanation: +| return: TRUE if has been CAN activity since last check +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL CanQueryRxActivity(t_can_handler can_handler); + +#endif diff --git a/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c b/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c new file mode 100644 index 0000000..6f11371 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.c @@ -0,0 +1,367 @@ + +/* ------------------------------ Includes ---------------------------------- */ +//#include "Global.h" +#include "Std_Types.h" +//#include "Gpt.h" +#include "P417_SWTR_App_ert_rtw/P417_SWTR_App.h" +#include "Timer.h" + +/* ------------------------------ Constants --------------------------------- */ +#if (TIMER_TIME_UNIT == U_SECONDS) + +#if ((TIMER_TIME_TICK < 1) || (TIMER_TIME_TICK > 1625)) + #error "Value not supported for TIMER_TIME_TICK" +#else + #define TIMER_VALOR ((UI_16)(TIMER_TIME_TICK*FACTOR_CONVERSIO_FCY_US)) +#endif + +#elif (TIMER_TIME_UNIT == M_SECONDS) + +#if ((TIMER_TIME_TICK < 1) || (TIMER_TIME_TICK > 104)) + #error "Value not supported for TIMER_TIME_TICK" +#else + #define TIMER_VALOR ((UI_16)(((UI_16)TIMER_TIME_TICK)*((UI_16)(FACTOR_CONVERSIO_FCY_MS)))) +#endif + +#else + #error "Time unit not defined." +#endif /* TIMER_TIME_UNIT */ + +/* Timer time max value definition */ +#if(T_TIMER_TIME_SIZE == T_TIMER_TIME_1_BYTE) + #define T_TIMER_TICK_MAX_VALUE ((UI_8)0xFF) +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_2_BYTE) + #define T_TIMER_TICK_MAX_VALUE ((UI_16)0xFFFF) +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_4_BYTE) + #define T_TIMER_TICK_MAX_VALUE ((UI_32)0xFFFFFFFF) +#else + #error "Size definition for t_timer_time is missing in FicosarCfg.h" +#endif + +/* --------------------------- Global Variables ----------------------------- */ + +/* Variable that contain current tick */ +static volatile t_timer_tick current_tick = (t_timer_tick)0; + +/* Variable to control last cycle tick synchronized */ +static volatile t_timer_tick cycle_tick = (t_timer_tick)0; + +/* ------------------------------ Functions --------------------------------- */ + +#ifdef TIMER_TICK_CALLBACK + void TIMER_TICK_CALLBACK (void); +#endif + + + +/****************************************************************************** +| Routine: TimerInit +| ---------------------------------------------------------------------------- +| Operations contract: +| This routine initializes the AUTOSAR GPT module to control the time according +| to the parameters given and permit to synchronize the main program cycle +| at each required point. +|----------------------------------------------------------------------------- +| Parameters explanation: +| All the configuration parameters are defined in FicoTimeWrapper.h +/---------------------------------------------------------------------------*/ +void TimerInit(void) +{ + // UI_32 value; + /* Initialization of tick counters */ + current_tick = (t_timer_tick)0; + cycle_tick = (t_timer_tick)0; + + /* Value calculation to load counter register */ + #if (TIMER_TIME_UNIT == U_SECONDS) + value=(TIMER_TIME_TICK * FREQ_SYS_CLOCK) - ((UI_8)1); + #elif (TIMER_TIME_UNIT == M_SECONDS) + // value=(TIMER_TIME_TICK * ((UI_32)1000) * FREQ_SYS_CLOCK)- ((UI_8)1); + #endif + /* Initialization of the GPT Driver */ + //Gpt_Init(GPT_CONFIG_SET_0); + /* Enabling the Notification */ + //Gpt_EnableNotification(GPT_CONFIG_CHANNEL_0); + /* Starting the Timer */ + //Gpt_StartTimer(GPT_CONFIG_CHANNEL_0, value); + +} /* TimerInit */ + +/****************************************************************************** +| Routine: TimerReset +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine reinitialize the actual tick counter. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +/---------------------------------------------------------------------------*/ +void TimerReset(void) +{ + //UI_32 value; + + /* Value calculation to load counter register */ + #if (TIMER_TIME_UNIT == U_SECONDS) + value=(TIMER_TIME_TICK * FREQ_SYS_CLOCK) - ((UI_8)1); + #elif (TIMER_TIME_UNIT == M_SECONDS) + // value=(TIMER_TIME_TICK * ((UI_32)1000) * FREQ_SYS_CLOCK)- ((UI_8)1); + #endif + + /* Disabling the Notification */ + //Gpt_DisableNotification(GPT_CONFIG_CHANNEL_0); + /* Stopping the Timer */ + //Gpt_StopTimer(GPT_CONFIG_CHANNEL_0); + + /* Enabling the Notification */ + // Gpt_EnableNotification(GPT_CONFIG_CHANNEL_0); + /* Starting the Timer */ + //Gpt_StartTimer(GPT_CONFIG_CHANNEL_0, value); + +} /* TimerReset */ + +/****************************************************************************** +| Routine: TimerSyncTick +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine is optional and only have to be called from the main program +| cycle +| * This routine is used to make an active wait to synchronize the main +| program cycle with a tick chosen between one of the number of ticks in +| which the main cycle has been divided +| * The user must be sure that if he makes different synchronizations inside +| the main program cycle, he increments the num_tick parameter given in +| each of the call. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| num_tick: number of tick in which the user want to synchronize the main +| program cycle. This parameter must be inside the range +| [1..TIMER_TICKS_CICLE-1] +| num_ticks = TIMER_TICKS_CICLE is reserved to TimerSyncCycle +| result: ERROR_OK if the timer didn't reach the synchronization point +| num_tick before the call +| ERROR_GENERIC if the timer reached the synchronization point +| num_tick before the call +/---------------------------------------------------------------------------*/ +t_error TimerSyncTick(t_timer_tick num_tick) +{ + t_error resultat = ERROR_OK; + BOOL synchronized; + t_timer_tick enter_loop_tick = 0; + + /* Case in which next cycle tick overflows the ticks variable */ + if(cycle_tick > (T_TIMER_TICK_MAX_VALUE - num_tick)) { + /* Mutex to avoid that RSI could modify the value during the calculation */ + // DISABLE_INTERRUPTS(); + synchronized = (current_tick < cycle_tick) && (current_tick >= ((t_timer_tick) (cycle_tick + num_tick))); + //ENABLE_INTERRUPTS(); + /* Check if next tick to synchronize is already reached*/ + if (synchronized == TRUE) { + /* Notify that cycle was already expired, the current main loop */ + /* path was larger than expected by design */ + resultat = ERROR_GENERIC; + } + else { + /* Active waiting to synchronize to given tick */ + while (synchronized == FALSE) { + /* Mutex to avoid that RSI could modify the value during the calculation */ + // DISABLE_INTERRUPTS(); + synchronized = (current_tick < cycle_tick) && (current_tick >= ((t_timer_tick) (cycle_tick + num_tick))); + // ENABLE_INTERRUPTS(); + } + } + } + /* Case in which next cycle tick does not overflow the ticks variable */ + else { + /* Mutex to avoid that RSI could modify the value during the calculation */ + // DISABLE_INTERRUPTS(); + synchronized = (current_tick >= ((t_timer_tick) (cycle_tick + num_tick))); + //ENABLE_INTERRUPTS(); + /* Check if next tick to synchronize is already reached */ + if (synchronized == TRUE) { + /* Notify that cycle was already expired, the current main loop */ + /* path was larger than expected by design */ + resultat = ERROR_GENERIC; + } + else { + //DISABLE_INTERRUPTS(); + enter_loop_tick = current_tick; + //ENABLE_INTERRUPTS(); + /* Active waiting to synchronize to given tick */ + while (synchronized == FALSE) { + /* Mutex to avoid that RSI could modify the value during the calculation */ + // DISABLE_INTERRUPTS(); + if(current_tick >= enter_loop_tick) { + synchronized = (current_tick >= ((t_timer_tick) (cycle_tick + num_tick))); + }else{ + synchronized = TRUE; + } + //ENABLE_INTERRUPTS(); + } + } + } + + return resultat; +} + +/****************************************************************************** +| Routine: TimerSyncCicle +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine is mandatory in critical real time clock systems, and must +| be called one time at the end of the main program cycle. +| * This routine is used to make an active wait to synchronize the main +| program cycle with the cycle number of ticks configured +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: ERROR_OK if the time didn't expired the synchronization point +| of the last tick +| ERROR_GENERIC if the time expired the synchronization point +| of the last tick +/---------------------------------------------------------------------------*/ +t_error TimerSyncCicle(void) +{ + t_error resultat; + + /* Synchronize with configured ticks cycle */ + resultat = TimerSyncTick(TIMER_TICKS_CICLE); + + /* Case which synchronization cycle was correctly performed */ + if(resultat == ERROR_OK) { + /* Set next cycle initial tick as current cycle initial tick plus + the number ticks of a cycle */ + cycle_tick += TIMER_TICKS_CICLE; + } + /* Case which synchronization point was already reached so the main loop */ + /* path was larger than what was expected by design */ + else { + /* Set next cycle initial tick as next current tick to assure next cycle + will have a complete TIMER_TICKS_CICLE ticks */ + /* Mutex to avoid that RSI could modify the value during the calculation */ + //DISABLE_INTERRUPTS(); + cycle_tick = current_tick + (UI_8)1; + //ENABLE_INTERRUPTS(); + } + + return resultat; +} + +/***************************************************************************** +| Routine: TimerGetCurrentTick +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to request the current tick at one point inside the main program +| cycle. +| * This routine shall be called when any FSM or function wants to start +| using a timer. At the timer initialization, the tick should be taken +| using this routine. Then with the TimerDeltaTime function the timer +| will be increased at each FSM or function execution and the tick will be +| directly updated by the TimerDeltaTime routine. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: current tick +/---------------------------------------------------------------------------*/ +t_timer_tick TimerGetCurrentTick(void) +{ + t_timer_tick aux_tick; + + /* Mutex to avoid that RSI could modify the value during the calculation */ + //DISABLE_INTERRUPTS(); + aux_tick = current_tick; + //ENABLE_INTERRUPTS(); + + return aux_tick; +} + +/***************************************************************************** +| Routine: TimerDeltaTime +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to compute the spent time between a tick given from the last task +| execution and the current tick at the moment of the call. +| * The precision is one clock tick. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| old_tick: Input/output parameter. +| As input, certain time tick obtained on the previous or current program +| cycle with the routine TimerGetCurrentTick or with the last +| call of TimerDeltaTime. +| As output return the current tick. +| result: spend time between the old_tick and the current tick. +| The units are in ticks. +| The equivalence between one tick and time is defined in HalCfg. +/---------------------------------------------------------------------------*/ +t_timer_time TimerDeltaTime(t_timer_tick *old_tick) +{ + t_timer_time time_diff; + t_timer_tick aux_tick; + + /* Mutex to avoid that RSI could modify the value during the calculation */ + //DISABLE_INTERRUPTS(); + aux_tick = current_tick; + //ENABLE_INTERRUPTS(); + + /* Case in which current tick overflows the maximum tick*/ + if(aux_tick < (*old_tick)){ + time_diff = (T_TIMER_TIME_MAX_VALUE - (*old_tick)) + aux_tick + (UI_8)1; + } + /* Case in which current tick does not overflow the maximum tick*/ + else{ + /* Get the difference between given tick with current tick*/ + time_diff = (t_timer_time)(aux_tick - (*old_tick)); + } + + /* Return the new tick */ + *old_tick = aux_tick; + + /* Return the difference of current tick compared to initial tick */ + return time_diff; +} + +/***************************************************************************** +| Routine: TimerIncrTime +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to increase the timer current tick time with a specific amount +| of time. This routine shall be called due to an operation which normally +| freezes the CPU and makes that the normal timer interrupt is not raised +| during some amount of time. Examples: +| - Execution of erasing or programming operations where CPU freezes +| - Usage of sleep functions or CPU low power operation modes where +| timer interrupt is not working +| * The precision is one clock tick. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| incr_time: time in which the timer shall increase its internal tick due to +| an external operation that avoids the normal counting of timer. +| This parameter shall be given using one of the macros: +| TIMER_MS_TO_TIME(x) or TIMER_US_TO_TIME(x) +/---------------------------------------------------------------------------*/ +void TimerIncrTime(t_timer_time incr_time) +{ + /* Mutex to avoid that RSI could modify the value during the calculation */ + //DISABLE_INTERRUPTS(); + current_tick += incr_time; + cycle_tick += incr_time; + //ENABLE_INTERRUPTS(); +} + +void SystemTimerGPT_callback(void) +{ + /* Increase tick counter */ + current_tick++; + +#ifdef TIMER_TICK_CALLBACK + TIMER_TICK_CALLBACK(); +#endif +} diff --git a/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h b/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h new file mode 100644 index 0000000..bb8216d --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h @@ -0,0 +1,450 @@ + +#ifndef TIMER_H_ +#define TIMER_H_ + +/* Allowed values for TIMER_TIME_UNIT */ +#define M_SECONDS (1) +#define U_SECONDS (2) + +/* ------------------------------ Includes ---------------------------------- */ +//#include "Global.h" +#include "Std_Types.h" +#include "DiagnosticR/_configurations/FicosarCfg.h" + +/* ------------------------------ Constants --------------------------------- */ + +/* Allowed956 values for T_TIMER_TIME_SIZE */ +#define T_TIMER_TIME_1_BYTE (1) +#define T_TIMER_TIME_2_BYTE (2) +#define T_TIMER_TIME_4_BYTE (3) + +/* Timer time max value definition */ +#if(T_TIMER_TIME_SIZE == T_TIMER_TIME_1_BYTE) +#define T_TIMER_TIME_MAX_VALUE ((UI_8)0xFF) +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_2_BYTE) +#define T_TIMER_TIME_MAX_VALUE ((UI_16)0xFFFF) +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_4_BYTE) +#define T_TIMER_TIME_MAX_VALUE ((UI_32)0xFFFFFFFF) +#else +#error "Size definition for t_timer_time is missing in FicosarCfg.h" +#endif + +/* ------------------------------- Macros ---------------------------------- */ + +/***************************************************************************** +| Macro: TIMER_MS_TO_TIME +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts a time value in milliseconds to time in the units of +| internal Timer clock according to the configuration selected. +| * The result value is rounded to the most near natural value. +| * This macro is used if the requested time has to be approximately accomplished. +| For example, with request 100ms the time could expire at 100ms+/-(x ms), +| where x is the error that it could be happen due to tick minimum configuration. +| * With this macro the time may not be reached exactly according of the timer +| configuration or cycle time +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| t: time period in milliseconds +| result: nearest internal timer time units of t miliseconds. +| The return type is a t_timer_time type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#if (TIMER_TIME_UNIT == M_SECONDS) + #if (TIMER_TIME_TICK>1) + #if ( (t % TIMER_TIME_TICK) >= TIMER_TIME_TICK/2) + #define TIMER_MS_TO_TIME(t) (t_timer_time)(((UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)1) + #else + #define TIMER_MS_TO_TIME(t) (t_timer_time)(((UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)0) + #endif + #else + #define TIMER_MS_TO_TIME(t) ( (t_timer_time) (t) ) + #endif +#elif (TIMER_TIME_UNIT == U_SECONDS) + #if (TIMER_TIME_TICK>1) + #if ( ((1000*(t)) % (TIMER_TIME_TICK) ) > 0 ) + #define TIMER_MS_TO_TIME(t) (t_timer_time)((1000*(UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)1) + #else + #define TIMER_MS_TO_TIME(t) (t_timer_time)((1000*(UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)0) + #endif + #else + #define TIMER_MS_TO_TIME(t) ( (t_timer_time) (1000 * (UI_32)(t)) ) + #endif +#endif + +/***************************************************************************** +| Macro: TIMER_MS_TO_TIME_RESTRICTIVE +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts a time value in milliseconds to time in the units of +| internal Timer clock according to the configuration selected. +| * This macro is used if requested time always has to be accomplished +| With this macro the time will always be reached and according configuration +| timer may be exceeded until in 2 timer ticks. +| * For example, with request 100ms the time could expire at 100ms+(x*2 ms), +| where x is the error that it could be happen due to tick minimum configuration. +| * The configured time will always be accomplished +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| t: time period in milliseconds. +| result: internal timer time units of at least t miliseconds. +| The return type is a t_timer_time type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#if (TIMER_TIME_UNIT == M_SECONDS) + #if (TIMER_TIME_TICK>1) + #if ( (t % TIMER_TIME_TICK) >= (TIMER_TIME_TICK / 2)) + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) (t_timer_time)(((UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)2) + #else + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) (t_timer_time)(((UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)1) + #endif + #else + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) ( (t_timer_time) ((t)+(UI_8)1) ) + #endif +#elif (TIMER_TIME_UNIT == U_SECONDS) + #if (TIMER_TIME_TICK>1) + #if ( ((1000*(t)) % (TIMER_TIME_TICK) ) >= (TIMER_TIME_TICK / 2) ) + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) (t_timer_time)((1000*(UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)2) + #else + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) (t_timer_time)((1000*(UI_32)(t))/((UI_8)TIMER_TIME_TICK) + (UI_8)1) + #endif + #else + #define TIMER_MS_TO_TIME_RESTRICTIVE(t) ( (t_timer_time) (1000 * (UI_32)((t)+(UI_8)1)) ) + #endif +#endif + +/***************************************************************************** +| Macro: TIMER_US_TO_TIME +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts a time value in microseconds to time in the units of +| internal Timer clock according to the configuration selected. +| * The result value is rounded to the most near natural value. +| * This macro is used if the requested time has to be approximately accomplished. +| For example, with request 100us the time could expire at 100us+/-(x us), +| where x is the error that it could be happen due to tick minimum configuration. +| * With this macro the time may not be reached exactly according of the timer +| configuration or cycle time +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| t: time period in microseconds. +| result: nearest internal timer time units of t microseconds. +| The return type is a t_timer_time type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#if (TIMER_TIME_UNIT == M_SECONDS) + #define TIMER_US_TO_TIME(t) \ + ((t_timer_time)((((UI_32)(t))/((UI_8)TIMER_TIME_TICK * (UI_16)1000)) + \ + (((((UI_32)(t))%((UI_8)TIMER_TIME_TICK * (UI_16)1000)) >= ((UI_8)TIMER_TIME_TICK * (UI_16)500)) ? \ + (UI_8)1 : (UI_8)0))) +#elif (TIMER_TIME_UNIT == U_SECONDS) +#define TIMER_US_TO_TIME(t) \ + (((UI_8)TIMER_TIME_TICK > (UI_8)1) ? \ + ((t_timer_time)((((UI_32)(t))/((UI_8)TIMER_TIME_TICK)) + \ + (((((UI_32)(t))%((UI_8)TIMER_TIME_TICK)) >= (((UI_8)TIMER_TIME_TICK/(UI_8)2))) ? (UI_8)1 : (UI_8)0))) : \ + ((t_timer_time)(t))) +#endif + +/***************************************************************************** +| Macro: TIMER_US_TO_TIME_RESTRICTIVE +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts a time value in microseconds to time in the units of +| internal Timer clock according to the configuration selected. +| * This macro is used if requested time always has to be accomplished +| With this macro the time will always be reached and according configuration +| timer may be exceeded until in 2 timer ticks. +| * For example, with request 100us the time could expire at 100us+(x*2 us), +| where x is the error that it could be happen due to tick minimum configuration. +| * The configured time will always be accomplished +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| t: time period in microseconds. +| result: internal timer time units of at least t microseconds. +| The return type is a t_timer_time type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#if (TIMER_TIME_UNIT == M_SECONDS) + #define TIMER_US_TO_TIME_RESTRICTIVE(t) \ + ((t_timer_time)((((UI_32)(t))/((UI_8)TIMER_TIME_TICK * (UI_16)1000)) + (UI_8)1 + \ + (((((UI_32)(t))%((UI_8)TIMER_TIME_TICK * (UI_16)1000)) >= ((UI_8)TIMER_TIME_TICK * (UI_16)500)) ? \ + (UI_8)1 : (UI_8)0))) +#elif (TIMER_TIME_UNIT == U_SECONDS) +#define TIMER_US_TO_TIME_RESTRICTIVE(t) \ + (((UI_8)TIMER_TIME_TICK > (UI_8)1) ? \ + ((t_timer_time)((((UI_32)(t))/((UI_8)TIMER_TIME_TICK)) + (UI_8)1 + \ + (((((UI_32)(t))%((UI_8)TIMER_TIME_TICK)) >= (((UI_8)TIMER_TIME_TICK/(UI_8)2))) ? (UI_8)1 : (UI_8)0))) : \ + ((t_timer_time)((t) + (UI_8)1))) +#endif + +/***************************************************************************** +| Macro: TIMER_1SEG_TO_TIME +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts 1 second to time in the units of internal Timer +| clock according to the configuration selected. +| * The result value is rounded to the most near natural value. +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: internal timer time of 1 second. The return type is a t_timer_time +| type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#define TIMER_1SEG_TO_TIME() (TIMER_MS_TO_TIME((UI_16)1000)) + +/***************************************************************************** +| Macro: TIMER_1MIN_TO_TIME +|---------------------------------------------------------------------------- +| Operations contract: +| * This macro converts 1 minute to time in the units of internal Timer +| clock according to the configuration selected. +| * The result value is rounded to the most near natural value. +| * This macro is thought to be solved during compiling time +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: internal timer time of 1 second. The return type is a t_timer_time +| type +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: 0 cpu cycles | O(n): CTE +| Tmax Int En : 0 cpu cycles | O(n): CTE +| Tmax Total : 0 cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#define TIMER_1MIN_TO_TIME() (TIMER_MS_TO_TIME((UI_16)60000)) + +/* ------------------------------ Data Types -------------------------------- */ + +/* Timer tick and time types definition */ +#if(T_TIMER_TIME_SIZE == T_TIMER_TIME_1_BYTE) +typedef UI_8 t_timer_time; +typedef UI_8 t_timer_tick; +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_2_BYTE) +typedef UI_16 t_timer_time; +typedef UI_16 t_timer_tick; +#elif(T_TIMER_TIME_SIZE == T_TIMER_TIME_4_BYTE) +typedef UI_32 t_timer_time; +typedef UI_32 t_timer_tick; +#else +#error "Size definition for t_timer_time is missing in HalCFG" +#endif + +/* ------------------------------ Functions --------------------------------- */ + +/****************************************************************************** +| Routine: TimerInit +| ---------------------------------------------------------------------------- +| Operations contract: +| This routine initializes the TIM peripheral to control the time according +| to the parameters given and permit to synchronize the main program cycle +| at each required point. +|----------------------------------------------------------------------------- +| Parameters explanation: +| All the configuration parameters are defined in HalCFG.h +|----------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TimerInit(void); + +/****************************************************************************** +| Routine: TimerReset +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine reinitialize the actual tick counter. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TimerReset(void); + +/****************************************************************************** +| Routine: TimerSyncTick +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine is optional and only have to be called from the main program +| cycle +| * This routine is used to make an active wait to synchronize the main +| program cycle with a tick chosen between one of the number of ticks in +| which the main cycle has been divided +| * The user must be sure that if he makes different synchronizations inside +| the main program cycle, he increments the num_tick parameter given in +| each of the call. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| num_tick: number of tick in which the user want to synchronize the main +| program cycle. This parameter must be inside the range +| [1..TIMER_TICKS_CICLE-1] +| result: ERROR_OK if the time didn't expired the synchronization point +| given as a parameter +| ERROR_GENERIC if the time expired the synchronization point +| given as a parameter +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_error TimerSyncTick(t_timer_tick num_tick); + +/****************************************************************************** +| Routine: TimerSyncCicle +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine is mandatory in critical real time clock systems, and must +| be called one time at the end of the main program cycle. +| * This routine is used to make an active wait to synchronize the main +| program cycle with the cycle number of ticks configured +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: ERROR_OK if the time didn't expired the synchronization point +| of the last tick +| ERROR_GENERIC if the time expired the synchronization point +| of the last tick +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_error TimerSyncCicle(void); + +/***************************************************************************** +| Routine: TimerGetCurrentTick +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to request the current tick at one point inside the main program +| cycle. +| * This routine shall be called when any FSM or function wants to start +| using a timer. At the timer initialization, the tick should be taken +| using this routine. Then with the TimerDeltaTime function the timer +| will be increased at each FSM or function execution and the tick will be +| directly updated by the TimerDeltaTime routine. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| result: current tick +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_timer_tick TimerGetCurrentTick(void); + +/***************************************************************************** +| Routine: TimerDeltaTime +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to compute the spent time between a tick given from the last task +| execution and the current tick at the moment of the call. +| * The precision is one clock tick. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| ini_tick: certain time tick obtained on the previous or current program +| cycle with the routine TimerGetCurrentTick or with the last +| call of TimerDeltaTime +| result: spend time between the ini_tick tick and the current tick. The +| units are the ones configured in the TimerInit call. +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_timer_time TimerDeltaTime(t_timer_tick *old_tick); + +/***************************************************************************** +| Routine: TimerIncrTime +|---------------------------------------------------------------------------- +| Operations contract: +| * Routine to increase the timer current tick time with a specific amount +| of time. This routine shall be called due to an operation which normally +| freezes the CPU and makes that the normal timer interrupt is not raised +| during some amount of time. Examples: +| - Execution of erasing or programming operations where CPU freezes +| - Usage of sleep functions or CPU low power operation modes where +| timer interrupt is not working +| * The precision is one clock tick. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +| incr_time: time in which the timer shall increase its internal tick due to +| an external operation that avoids the normal counting of timer. +| This parameter shall be given using one of the macros: +| TIMER_MS_TO_TIME(x) or TIMER_US_TO_TIME(x) +|--------------------------------------------------------------------------- +| Execution time: +| Tmax Int Dis: ??? cpu cycles | O(n): CTE +| Tmax Int En : ??? cpu cycles | O(n): CTE +| Tmax Total : ??? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TimerIncrTime(t_timer_time incr_time); + +/****************************************************************************** +| Routine: SystemTimerGPT_callback +| ---------------------------------------------------------------------------- +| Operations contract: +| * This routine is the callback routine of AUTOSAR GPT (Timer) and it is called +| every tick of the clock. +| * This routine reinitialize the actual tick counter. +| * Before calling this routine, the driver must have been initialized with +| the TimerInit routine. +|--------------------------------------------------------------------------- +| Parameters explanation: +|--------------------------------------------------------------------------- +| Execution time: +| +/---------------------------------------------------------------------------*/ +void SystemTimerGPT_callback(void); + +//ACF deprecated +typedef t_timer_time t_clock; +#define TIMER_US_TO_TICKS(t) (TIMER_US_TO_TIME((t))) +#define TIMER_MS_TO_TICKS(t) (TIMER_MS_TO_TIME((t))) +#define TIMER_1SEG_TO_TICKS() (TIMER_1SEG_TO_TIME()) +#define TIMER_1MIN_TO_TICKS() (TIMER_1MIN_TO_TIME()) +#define TimerDeltaCicleConsulta() ((UI_16)(TIMER_TICKS_CICLE)) +#define T_CLOCK_MAX_VALUE (T_TIMER_TIME_MAX_VALUE) + +#endif /* FICOSARTIMER_H_ */ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP.h b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP.h new file mode 100644 index 0000000..0d3479c --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP.h @@ -0,0 +1,291 @@ +/*************** COPYRIGHT (c) 2002-2007 FICOSA INTERNATIONAL ************** +| Language: | MISRA C +| Controller: | Generic +| Spec. Document: | ISO15765-2-E.pdf +|-----------------|------------------------------------------------------------ +| Project: | ISO15765-2 +| Reference: | +|------------------------------------------------------------------------------ +| Date - Cod. - Rev. - App. - Description +| 12/09/02 AM Implementation of the kwp2000 for PSA. +| 19/08/04 DT Split ISO15765_2 protocol from the KWP2000 +| because they are different modules. +| 24/04/09 DC Modification to guarantee the requirements SR1431, +| SR1438, SR1681. +| 15/12/10 AC Converted ISO15765_2 protocol to multi-instance. +| 13/11/11 AC Converted ISO15765_2 to full-duplex +| 09/01/12 AC Changed file, routines and variable naming to +| make it a standard component improving his +| comprehension and having a similar naming style +| with MPDT. +|------------------------------------------------------------------------------ +| DESCRIPTION: +| User interface for the transport protocol ISO15765_2 on CAN. +| ISO15765_2 protocol is a transport protocol that permits the sending and +| reception of frames until 4096 bytes on a network protocol with frames of +| lower size. The original frame is segemented and sent with flow control +| data that allows to the reception node to mount again the original frame. +| GENERAL CONSIDERATIONS +| - This implementation allows full duplex communications. +| - This implementation allows for each instance a communication channel +| with physical address in which both transmission and receptions could +| be done and a funcional address for only receptions. +| - The functional address channel only supports frames with less than +| 8 bytes of data. +| - This header must be included by the application as it contains the +| definitions of the ISO15765_2 shared structures that allow the ISO15765_2 +| and the application to communicate and interact. +******************************************************************************/ +#ifndef __TP_H +#define __TP_H + +/*----------------------------- INCLUDES ---------------------------------*/ +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" +#include "OsekCom/OsekCom.h" +//#include "Global.h" +#include "Std_Types.h" + +/*----------------------------- DEFINES ----------------------------------*/ + +/* Macro to calculate the size of the buffer that must allocate the */ +/* transport protocol frame */ +#define SIZE_ALLOC_BUFFER(val) \ + (((val) <= 7) ? (7) : \ + ((val) + (((((val) - 6) % 7) > 0) ? (7 - (((val) - 6) % 7)) : (0)))) + +/*-------------------------- DATA TYPES ----------------------------------*/ + +/* List of the possible types of flow controls */ +typedef enum { + TP_FLOW_STS_CTS = 0, /* Clear to Send */ + TP_FLOW_STS_WT = 1, /* Wait */ + TP_FLOW_STS_OVFLW = 2 /* Buffer Overflow */ +} t_tp_flow_sts; + +/* List of the possible status for transmiting */ +typedef enum { + TP_TX_REQUESTED = 0, /* Transmission requested */ + TP_TX_ON_GOING = 1, /* Transmission ongoing */ + TP_TX_CONFIRMED = 2, /* Transmission confirmed */ + TP_TX_ERROR = 3 /* Transmission error */ +} t_tp_tx_sts; + +/* List of the possible types of transport protocol received frames */ +typedef enum { + TP_RX_SF = 0, /* Received Single Frame (SF) */ + TP_RX_FF = 1, /* Received First Frame (FF) */ + TP_RX_CF = 2, /* Received Consecutive Frame (CF) */ + TP_RX_NO_FRM = 3 /* No recognized frame received */ +} t_tp_rx_frm; + +/* List of the possible status of flow control */ +typedef enum { + TP_FC = 0, /* Received Flow Control Frame (FC) */ + TP_NO_FC_FRM = 1 /* No recognized FC received */ +} t_tp_fc_frm; + +/* List of the possible status of reception */ +typedef enum { + TP_FRM_RX_IDLE = 0, /* Idle status of RX, nothing new */ + TP_FRM_RX_IN_PRG = 1, /* Reception in progress */ + TP_FRM_RX_NOTIF = 2, /* Notification to higher layer of a full reception */ + TP_FRM_RX_ERR_NOTIF = 3, /* Notification to higher layer of error during a reception */ + TP_FRM_RX_FINISHED = 4, /* CF reception finished and pending to be notified to higher layer */ + TP_FRM_RX_ERR_FINISHED = 5 /* Error reception finished and pending to be notified to higher layer */ +} t_tp_frm_sts_rx; + +/* List of the possible status of transmission */ +typedef enum { + TP_FRM_TX_IDLE = 0, /* No TX in progress and last TX OK */ + TP_FRM_TX_REQ = 1, /* Transmission requested and pending */ + TP_FRM_TX_ERR_NOTIF = 2, /* Error occurred during last transmission */ + TP_FRM_TX_PENDING = 3 /* Transmission needed pending to be given */ +} t_tp_frm_sts_tx; + +/* Types of frame that TP have pending to send */ +typedef enum { + TP_TX_TYPE_NONE = 0, /* TP do not have any frame to be sent */ + TP_TX_TYPE_FC = 1, /* TP is going to send a FC */ + TP_TX_TYPE_SF_FF_CF = 2 /* TP is going to send a SF, FF or CF */ +} t_tp_tx_type; + +/* Structure that contains all the information for the physical reception and transmission */ +typedef struct { + UI_8* data_tx; /* Pointer to the buffer that will be transmitted when requested */ + UI_8* data_rx; /* Pointer to the physical reception buffer */ + UI_16 size_tx; /* Size of the transmission requested */ + UI_16 size_rx; /* Size of the last reception */ + t_tp_frm_sts_tx sts_tx; /* Status of the transmission */ + t_tp_frm_sts_rx sts_rx; /* Status of the phyisical reception */ + BOOL unblock_after_tx; /* Flag to unblock the ISO15765_2 reception at the end of the current transmission */ + BOOL iso15765_2_block_rx; /* Flag to block the reception of new frames. To be used for example in diagnostics where a */ + /* request must always be answered before receiving another request */ + BOOL iso15765_2_block_tx; /* Flag that blocks the transmission of diagnostics on the ISO15765_2. To be used for example */ + /* when the TCU is acting as a UDS client and is doing autodiagnostics */ +} t_tp_frm; + +/* Structure that contains the functional reception frame information */ +typedef struct { + UI_8 *data_rx; /* Pointer to the physical reception buffer */ + UI_8 size; /* Size of the received functional data */ + t_tp_frm_sts_rx sts_rx; /* Status of the functional reception */ +} t_tp_fun_frm; + +/* Structure that must be used to initialize an instance of the ISO15765_2 module. This structure must */ +/* be defined in the stack in a ISO15765_2 callback routine inside the application space that must be */ +/* named Iso15765_2_DynamicParametersInitCallback and will be directly called by the */ +/* InicialitzaIso15765_2Task routine that must be the only one called from the initializations in main. */ +typedef struct { + UI_16 max_frm_size; /* Maximum size allowed for the TP RX buffer. The protocol allows */ + /* frames until 4096 bytes. The buffer must be reserved having into */ + /* account the MACRO "SIZE_ALLOC_BUFFER" to avoid overflows. */ + BOOL frm_size_fixed; /* Flag to configure fixed or variable length in the CAN frames TX */ + /* Allowed values: */ + /* TRUE -> all the TP frames are sent with 8 bytes and the non useful */ + /* ones are padded with the value tx_padding_value */ + /* FALSE -> all the TP frames are sent only with the length needed to */ + /* send all the valid data */ + BOOL rx_padding_sensitive; /* Flag to be taken into account if frm_size_fixed is defined as TRUE. */ + /* Allowed values: */ + /* TRUE -> RX TP frames with less than 8 bytes are ignored */ + /* FALSE -> RX TP frames with less than 8 bytes are processed */ + /* correctly if the frame has a correct TP format */ + UI_8 tx_padding_value; /* Padding value for the non valid bytes in case that */ + /* np_can_frm_size_fixed is configured to TRUE */ + UI_16 cr_timer; /* Maximum timeout measured in ms between Consecutive frames before */ + /* aborting the reception due to time out */ + UI_16 bs_timer; /* Time in ms between the first frame and the firs flow control or */ + /* between the last consecutive frame of a block and the flow control */ + /* before aborting the transmission due to timeout */ + UI_16 stmin_timer; /* Time in ms between consecutive frames of the transmitter to allow */ + /* ourself to process the received frames without losing anyone */ + /* If the block size if different from 1, this time must be minimum the */ + /* cycle frequency, otherwise if this is 1 the stmin could be 0 */ + UI_8 block_size; /* Number of consecutive frames that the ECU will send without waiting */ + /* for a flow control before continuing. If the block size is set to 0 */ + /* means that only one flow control is needed after receiving the first */ + /* frame */ + UI_8 max_fc_wait; /* Maximum FC wait that TP can handle in a row */ + UI_8 * tx_phy_buffer; /* Pointer to the TX physical buffer. Must be declared with the size to */ + /* hold the maximum trasmission length */ + UI_8 * rx_phy_buffer; /* Pointer to the RX physical buffer. Must be declared with the size to */ + /* hold the maximum reception length */ + UI_8 * rx_fun_buffer; /* Pointer to the RX functional buffer. The size of the buffer must be 7 */ + t_can_handler can_handler; //ACF must be called OsekCom_Handler + t_symbolic_name sig_np_rx_phy; /* OSEKCOM signal to get the RX physical frame */ + t_symbolic_name sig_np_tx_phy; /* OSEKCOM signal to request the transmission of the TX */ + /* physical frame */ + t_symbolic_name sig_np_rx_fun; /* OSEKCOM signal to get the RX functional frame */ +} t_tp_init; + +/*--------------------------- GLOBAL VARIABLES --------------------------*/ + +/* Declaration of the tp_frm phisical structures. This structure is declared extern because will be the */ +/* input and output structure between the application and the ISO15765_2 transport protocol */ +extern t_tp_frm tp_frm[TP_NUM_INSTANCES]; + +/* Declaration of the tp_frm functional structures. This structure is declared extern because will be */ +/* the input and output structure between the application and the ISO15765_2 transport protocol */ +extern t_tp_fun_frm tp_fun_frm[TP_NUM_INSTANCES]; + +/*---------------------------- ROUTINE PROTOTYPES --------------------------*/ + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to initialize one ISO15765_2 transport protocol instance. This +| routine should be called once in the main initializations and will call +| to the Iso15765_2_DynamicParametersInitCallback callback routine to +| configure dynamically the transport protocol instance with the parameters +| needed by the application. +| This routine should be called once for each ISO15765_2 instance defined. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler of the instance that will be initialized. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InicialitzaTPTask(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Task that must be executed once in each main cycle and that will trigger +| all the tasks needed to assure the transport protocol correct functionality. +| This routine should be called once for each ISO15765_2 instance defined. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPTask(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to initialize an ISO15765_2 instance with the configuration +| parameters needed by the application. +| This routine must be called from the callback routine in which the user +| must configure the dynamic parameters that must be called +| TPDynamicParametersInitCallback +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| init_data: ISO15765_2 configuration parameters to be taken by the +| given handler +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPInitData(UI_8 tp_hdl, t_tp_init * init_data); + +#ifdef ENABLE_INCREMENT_EXTERNAL_TIMERS +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to increment the timers used in the RX task. This routine should be called +| in case of a known desviation of the main program cycle which the user know that +| all the timers should be incremented additionally with a certain value. +|--------------------------------------------------------------------------- +| Parameters Explanation: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPRxIncrTimers(UI_8 tp_hdl, UI_16 ticks); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to increment the timers used in the TX task. This routine should be called +| in case of a known desviation of the main program cycle which the user know that +| all the timers should be incremented additionally with a certain value. +|--------------------------------------------------------------------------- +| Parameters Explanation: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPTxIncrTimers(UI_8 tp_hdl, UI_16 ticks); +#endif /* #ifdef ENABLE_INCREMENT_EXTERNAL_TIMERS */ + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_C b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_C new file mode 100644 index 0000000..1cbffe3 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_C @@ -0,0 +1,195 @@ +/************ Copyright 2004-2009 FICOSA CORPORATIVE ELECTRONICS ************ +| Language: | MISRA C +| Controller: | dsPIC33 +| Requirements: +|-------------|------------------------------------------------------------ +| Project: | 082_TCU01_F1_TCU_EMU_RSA +|------------------------------------------------------------------------------ +| HISTORY OF MODIFICATIONS +| Date - Coder - Description +| 07/02/10 AC Creation of the file. +|------------------------------------------------------------------------------ +| FILE DESCRIPTION: +| Configuration source file of the transport protocol (ISO15765_2) layer. +| This source file must contain the transport protocol callback routine +| TPDynamicParametersInitCallback to initialize the dynamic configuration +| parameters for each TP instance defined in TP_CFG.h. +******************************************************************************/ + +/* -------------------------------- Includes -------------------------------- */ +#include "Global.h" +#include "ProjectCFG.h" +#include "TP.h" +#include "TP_CFG.h" +#include "FicOsekCom.h" +#include "Iso15765_3_CFG.h" +#include "Iso15765_3.h" + +/* -------------------------------- Defines --------------------------------- */ + +/* Size of the buffer that must store the largest frame for the */ +/* MPDT TX and RX instances */ +/* The size of the buffer must be declared using the macro */ +/* SIZE_ALLOC_BUFFER to assure that no overflows will happen during */ +/* transmission or reception of frames larger than single frames */ +#define TP_MPDT_TX_LEN (SIZE_ALLOC_BUFFER(30)) +#define TP_MPDT_RX_LEN (SIZE_ALLOC_BUFFER(30)) + +/* For diagnostics TP instance I have the length of the buffers already */ +/* defined in the Iso15765_3 layer */ + +/* ------------------------------- Data Types ------------------------------- */ + +/* ---------------------------- Global Variables ---------------------------- */ + +/* Definition of the buffer to allocate functional frames. As functional */ +/* frames are not needed in any of my TP instances I declare it as a dummy */ +/* buffer. The size of the functional buffer must be always of 7 bytes */ +/* because this is the maximum length that could be send in a SF */ +static UI_8 dummy_buf[7] = { 0,0,0,0,0,0,0 }; + +/* Definition of the transmission and reception TP buffers for MPDT */ +static UI_8 tp_mpdt_tx_buf[TP_MPDT_TX_LEN]; +static UI_8 tp_mpdt_rx_buf[TP_MPDT_RX_LEN]; + +/* For diagnostics TP instance I have the buffers already defined in the */ +/* Iso15765_3 layer */ + +/* --------------------------- Routine prototypes --------------------------- */ + +/* -------------------------------- Routines -------------------------------- */ + +/***************************************************************************** +| Portability: General +|---------------------------------------------------------------------------- +| Routine description: +| * It is responsability of the user to declare this routine. +| * This routine is a callback routine that will be called each time that the +| InicialitzaTPTask is executed. This InicialitzaTPTask must be called at +| the initializations in main and must be called once for each instance +| defined in the TP_CFG.h. +| * Routine to initializate dynamically the parameters of each defined +| transport protocol instance. The way to configure each transport protocol +| instance is using the structure t_tp_init which must be given as a pointer +| to TPInitData routine. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void TPDynamicParametersInitCallback(UI_8 tp_hdl) +{ + /* Declare the initialization ISO15765_2 structure as a local variable */ + /* in order to not use space in the stack */ + t_tp_init tp_init; + + /* Switch for each instance of ISO15765_2 declared (TP_NUM_INSTANCES) */ + switch(tp_hdl) { + /* Initialize the user configuration parameters of the transport protocol instance used for diagnostics */ + case ISO15765_2_DIAGONCAN_HANDLER: + /* Maximum size allowed for the diagnostics RX buffer. */ + /* The buffer must be reserved having into account the MACRO "SIZE_ALLOC_BUFFER" to avoid overflows */ + tp_init.max_frm_size = (UI_16)TP_DIAG_RX_TX_LEN; + /* Flag to configure fixed or variable length in the CAN frames TX */ + /* Diagnostics frm_size_fixed = TRUE: Defined in the renault document 36-02-031--A_Gb.pdf, page 9, chapter 6 */ + tp_init.frm_size_fixed = TRUE; + /* Flag to configure if TP RX frames are sensitive to have a fixed length. TRUE indicates that we will ignore TP RX frames */ + /* that have less than 8 bytes */ + tp_init.rx_padding_sensitive = TRUE; + /* Special value 0x50 is requiered in the padding value for diagnostics TX (only cares if frame size is configured as fixed) */ + /* Defined in the renault document CRS_TCU_NT65612_2009_80_v1.1DRAFT.pdf page 6 */ + tp_init.tx_padding_value = 0x50; + /* Maximum timeout in ms between Consecutive frames before aborting the reception due to time out */ + /* Diagnostics CR timer: Defined in the renault document 36-02-031--A_Gb.pdf, pages 7 and 17 */ + tp_init.cr_timer = (UI_16)1000; + /* Time in ms between the first frame and the firs flow control or between the last consecutive frame of a block */ + /* and the flow control before aborting the transmission due to timeout */ + /* Diagnostics BS timer: Defined in the renault document 36-02-031--A_Gb.pdf, pages 7 and 17 */ + tp_init.bs_timer = (UI_16)1000; + /* Time in ms between consecutive frames of the transmitter to allow ourself to process the received frames */ + /* without losing anyone. If the block size if different from 1, this time must be minimum the cycle frequency, */ + /* otherwise if this is 1 the stmin could be 0 */ + /* For diagnostics this requirement is defined in the renault document 36-02-031--A_Gb.pdf, page 7 as 0 */ + tp_init.stmin_timer = (UI_16)0; + /* Number of consecutive frames that the diagnostics TP will send without waiting for a flow control before continuing. */ + /* If the block size is set to 0 means that only one flow control is needed after receiving the first */ + tp_init.block_size = (UI_8)1; + /* Number of FC wait the TP can handle before rising directly an error during the transmission when a FC wait is received */ + tp_init.max_fc_wait = (UI_8) 0xFF; + /* Initialize the buffer pointer where the diagnostics TX positive response physical information is set */ + tp_init.tx_phy_buffer = diag_tx_buf; + /* Initialize the buffer pointer where the diagnostics RX physical request information is set */ + tp_init.rx_phy_buffer = diag_rx_buf; + /* Initialize the buffer pointer where the diagnostics RX functional request information is set */ + tp_init.rx_fun_buffer = dummy_buf; + /* Initialize the pointer of the diagnostics OSEKCOM routine that notifies the reception of the physical frame */ + tp_init.np_get_rx_phy_notif = &ReadFlagRxSigDToolToTcu; + /* Initialize the pointer of the diagnostics OSEKCOM routine that notifies the transmission of the physical frame */ + tp_init.np_get_tx_phy_notif = &ReadFlagTxSigTcuToDTool; + /* Initialize the pointer of the diagnostics OSEKCOM routine that notifies the timeout error of the TX physical frame. */ + /* This OSEKCOM routine will be created when the TX notification error is requested and the timeout for this must be */ + /* set to the AR/AS timeout. For diagnostics we have a timeout of 1000 ms for AR/AS configured in the CAN database. */ + tp_init.np_err_tx_phy_notif = &ReadFlagTxErrorSigTcuToDTool; + /* Set the OSEKCOM diagnostics signal to get the RX physical frame */ + tp_init.sig_np_rx_phy = SIG_DTOOLTOTCU; + /* Set the OSEKCOM signal to request the transmission of the diagnostics TX physical frame */ + tp_init.sig_np_tx_phy = SIG_TCUTODTOOL; + /* Initialize the diagnostics RX functional notification routine to NULL because we must not receive functional frames */ + tp_init.np_get_rx_fun_notif = NULL; + /* Initialize the signal of the diagnostics RX functional frame to DUMMY signal becuase we must not receive functional frames */ + tp_init.sig_np_rx_fun = SIGDUMMY; + /* Call the ISO15765_2 configuration routine to initialize the diagnostics instance with the configured parameters */ + TPInitData(tp_hdl, &tp_init); + break; + /* Initialize the user configuration parameters of the transport protocol instance used for MPDT */ + case ISO15765_2_MPDT_HANDLER: + /* Maximum size allowed for the MDPT buffer. */ + /* The buffer must be reserved having into account the MACRO "SIZE_ALLOC_BUFFER" to avoid overflows */ + tp_init.max_frm_size = TP_MPDT_RX_LEN; //ACF optimitzar rps=30, tps=20 DOC: CRS + /* Flag to configure fixed or variable length in the CAN frames TX */ + /* MPDT frm_size_fixed = TRUE: Defined in the renault document CRS */ + tp_init.frm_size_fixed = TRUE; + /* Special value 0xFF is requiered in the padding value of MPDT, defined in the renault document CRS */ + tp_init.tx_padding_value = 0xFF; + /* Maximum timeout in ms between Consecutive frames before aborting the reception due to time out */ + /* MPDT CR timer: Defined in the renault document CRS, pages 7 and 17 */ + tp_init.cr_timer = (UI_16)500; + /* Time in ms between the first frame and the firs flow control or between the last consecutive frame of a block */ + /* and the flow control before aborting the transmission due to timeout */ + /* MPDT BS timer: Defined in the renault document CRS, pages 7 and 17 */ + tp_init.bs_timer = (UI_16)500; + /* Time in ms between consecutive frames of the transmitter to allow ourself to process the received frames */ + /* without losing anyone. If the block size if different from 1, this time must be minimum the cycle frequency, */ + /* otherwise if this is 1 the stmin could be 0 */ + /* For MDPT this requirement is defined in the renault document CRS */ + tp_init.stmin_timer = (UI_16)10; + /* Number of consecutive frames that the MPDT TP will send without waiting for a flow control before continuing. */ + /* If the block size is set to 0 means that only one flow control is needed after receiving the first */ + tp_init.block_size = (UI_8)0; + /* Initialize the buffer pointer where the MPDT TX positive response physical information is set */ + tp_init.tx_phy_buffer = tp_mpdt_tx_buf; + /* Initialize the buffer pointer where the MPDT RX physical request information is set */ + tp_init.rx_phy_buffer = tp_mpdt_rx_buf; + /* Initialize the buffer pointer where the MPDT RX functional request information is set */ + tp_init.rx_fun_buffer = dummy_buf; + /* Initialize the pointer of the MPDT OSEKCOM routine that notifies the reception of the physical frame */ + tp_init.np_get_rx_phy_notif = &ReadFlagRxSigTcuRxMpdt; + /* Initialize the pointer of the MPDT OSEKCOM routine that notifies the transmission of the physical frame */ + tp_init.np_get_tx_phy_notif = &ReadFlagTxSigTcuTxMpdt; + /* Initialize the pointer of the MPDT OSEKCOM routine that notifies the timeout error of the TX physical frame */ + /* This OSEKCOM routine will be created when the TX notification error is requested and the timeout for this must be */ + /* set to the AR/AS timeout. For MPDT we have a timeout of 50 ms for AR/AS configured in the CAN database. */ + tp_init.np_err_tx_phy_notif = &ReadFlagTxErrorSigTcuTxMpdt; + /* Set the MPDT OSEKCOM signal to get the RX physical frame */ + tp_init.sig_np_rx_phy = SIG_TCURXMPDT; + /* Set the OSEKCOM signal to request the MPDT transmission of the TX physical frame */ + tp_init.sig_np_tx_phy = SIG_TCUTXMPDT; + /* Initialize the MPDT RX functional notification routine to NULL because we must not receive functional frames */ + tp_init.np_get_rx_fun_notif = NULL; + /* Initialize the signal of the MPDT RX functional frame to DUMMY signal becuase we must not receive functional frames */ + tp_init.sig_np_rx_fun = SIGDUMMY; + /* Call the ISO15765_2 configuration routine to initialize the MPDT instance with the configured parameters */ + TPInitData(tp_hdl, &tp_init); + break; + default: + break; + } +} diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_H b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_H new file mode 100644 index 0000000..bf1f673 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_CFG.TEMPLATE_H @@ -0,0 +1,73 @@ +/************ Copyright 2004-2009 FICOSA CORPORATIVE ELECTRONICS ************ +| Language: | MISRA C +| Controller: | dsPIC33 +| Requirements: +|-------------|------------------------------------------------------------ +| Project: | 082_TCU01_F1_TCU_EMU_RSA +|------------------------------------------------------------------------------ +| HISTORY OF MODIFICATIONS +| Date - Coder - Description +| 07/02/10 AC Creation of the file. +|------------------------------------------------------------------------------ +| FILE DESCRIPTION: +| Configuration header file of the transport protocol (ISO15765_2) layer. +| This header must define if the transport protocol used is FULL or LITE which +| implies if frames till 4096 bytes can be send or only single frames till 7 +| bytes can be send. +| This header must configure the number of transport protocol instances that +| the application need. +| This header must also contain the declaration of the callback routine to +| initialize the transport protocol dynamic configuration parameters which must +| be called TPDynamicParametersInitCallback +******************************************************************************/ +#ifndef __TP_CFG_H +#define __TP_CFG_H + +/*---------------------------- includes ----------------------------------*/ +#include "ProjectCFG.h" + +/*----------------------------- defines ----------------------------------*/ + +/* Select the mode of ISO15765_2 used. This will apply for all the */ +/* transport protocol instances defined */ +/* TP_MODE_LITE -> Only single frames can be sent and received */ +/* TP_MODE_FULL -> Frames till 4096 bytes can be sent and received */ +#define TP_MODE_FULL + +/* Number of Transport Protocol instances that will be defined. One */ +/* instance must be defined for example for each of the following upper */ +/* layters: */ +/* - Diagnostics client */ +/* - Diagnostics server */ +/* - MPDT */ +#define TP_NUM_INSTANCES ((UI_8)2) + +#define ISO15765_2_REPROGONCAN_HANDLER ((UI_8)0) + +/* Ticks between task periodic calls */ +#define TP_TASK_TICKS ((t_timer_time)1) + +/* Minimum length of a flow control frame to be accepted */ +#define CAN_FRM_FC_SIZE ((UI_8)8) + +/*------------------------- prototips de funcions ------------------------*/ + +/***************************************************************************** +| Portability: General +|---------------------------------------------------------------------------- +| Routine description: +| * It is responsability of the user to declare this routine. +| * This routine is a callback routine that will be called each time that the +| InicialitzaTPTask is executed. This InicialitzaTPTask must be called at +| the initializations in main and must be called once for each instance +| defined in the TP_CFG.h. +| * Routine to initializate dynamically the parameters of each defined +| transport protocol instance. The way to configure each transport protocol +| instance is using the structure t_tp_init which must be given as a pointer +| to TPInitData routine. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void TPDynamicParametersInitCallback(UI_8 tp_hdl); + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c new file mode 100644 index 0000000..decb0f6 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.c @@ -0,0 +1,1424 @@ +/*************** COPYRIGHT (c) 2002-2007 FICOSA INTERNATIONAL ************** +| Language: | MISRA C +| Controller: | Generic +| Spec. Document: | ISO15765-2-E.pdf +|-----------------|------------------------------------------------------------ +| Project: | ISO15765-2 +| Reference: | +|------------------------------------------------------------------------------ +| Date - Cod. - Rev. - App. - Description +| 12/09/02 AM Implementation of the kwp2000 for PSA. +| 19/08/04 DT Split ISO15765_2 protocol from the KWP2000 +| because they are different modules. +| 24/04/09 DC Modification to guarantee the requirements SR1431, +| SR1438, SR1681. +| 15/07/09 AC Corrected bug in ReadCF because it didn't count +| correctly the blocks +| 15/12/10 AC Converted ISO15765_2 protocol to multi-instance. +| 13/11/11 AC Converted ISO15765_2 to full-duplex +| 09/01/11 AC Changed file, routines and variable naming to +| make it a standard component and to have a +| similar naming style with MPDT. +|------------------------------------------------------------------------------ +| DESCRIPTION: +| User interface for the transport protocol ISO15765_2 on CAN. +| ISO15765_2 protocol is a transport protocol that permits the sending and +| reception of frames until 4096 bytes on a network protocol with frames of +| lower size. The original frame is segemented and sent with flow control +| data that allows to the reception node to mount again the original frame. +| GENERAL CONSIDERATIONS +| - This implementation allows full duplex communications. +| - This implementation allows for each instance a communication channel +| with physical address in which both transmission and receptions could +| be done and a funcional address for only receptions. +| - The functional address channel only supports frames with less than +| 8 bytes of data. +******************************************************************************/ + +/*----------------------------- INCLUDES ---------------------------------*/ +//#include "Global.h" +//#include "Timer.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +#include "TP_Task.h" +#include "TP_Functions.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" + +/*----------------------------- DEFINES ----------------------------------*/ + +/* Constant that define the maximum value that could have the segment number */ +#define MAX_NUM_SEG ((UI_8)15) + +/* Possible values of the first 4 bits of the first transport protocol byte */ +/* which define the type of TP frame */ +#define SF_TYPE ((UI_8)0) +#define FF_TYPE ((UI_8)1) +#define CF_TYPE ((UI_8)2) +#define FC_TYPE ((UI_8)3) + +/*------------------------------ DATA TYPES ------------------------------*/ + +/*--------------------------- GLOBAL VARIABLES ---------------------------*/ + +/* Declaration of the TP data structure */ +t_tp_data tp_data[TP_NUM_INSTANCES]; + +/* Declaration of the tp_frm phisical structure */ +t_tp_frm tp_frm[TP_NUM_INSTANCES]; + +/* Declaration of the tp_frm functional structure */ +t_tp_fun_frm tp_fun_frm[TP_NUM_INSTANCES]; + + +/*--------------------------- ROUTINE PROTOTYPES -------------------------*/ + +/*-------------------------------- ROUTINES ------------------------------*/ + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to initialize the transport protocol strucutres. +| This routine must be called once from Initializations of main +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: TP handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InicialitzaTPTask(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* INITIALIZE FLOW CONTROL DATA STRUCTURE */ +#ifdef TP_MODE_FULL + /* Flow control status */ + tp_data[tp_hdl].fc_data.flow_status = TP_FLOW_STS_CTS; + /* BS received by the FC of the tool */ + tp_data[tp_hdl].fc_data.rx_bs = 0xFF; + /* STMIN time received by the FC of the tool */ + tp_data[tp_hdl].fc_data.stmin = 0x7F; + /* Flag that indicates if it is the first FC */ + tp_data[tp_hdl].fc_data.first_fc = TRUE; + /* Flag that indicates the reception of a FC */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + /* Counter of the current block size sent in order to know when a FC must expected */ + tp_data[tp_hdl].fc_data.block_size_cnt = 0xFF; + /* Counter of the consecutive frames sent before waiting a FC */ + tp_data[tp_hdl].fc_data.num_fc_wait = 0; +#endif + /* INITIALIZE THE TP_FRM STRUCTURE */ + tp_frm[tp_hdl].size_tx = (UI_16)0; + tp_frm[tp_hdl].size_rx = (UI_16)0; + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_IDLE; + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_IDLE; + tp_frm[tp_hdl].unblock_after_tx = FALSE; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + tp_frm[tp_hdl].iso15765_2_block_tx = FALSE; + /* INITIALIZE THE TP_FUN_FRM STRUCTURE */ + tp_fun_frm[tp_hdl].size = (UI_8)0; + tp_fun_frm[tp_hdl].sts_rx = TP_FRM_RX_IDLE; + /* INITIALIZE THE TX RX STATUS STRUCTURE */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + tp_data[tp_hdl].tx_st.ack_tx = FALSE; + tp_data[tp_hdl].tx_st.frame_tx_sts = TP_TX_CONFIRMED; +#ifdef TP_MODE_FULL + tp_data[tp_hdl].rx_st.byte_actual_rx = (UI_16)0; + tp_data[tp_hdl].tx_st.byte_actual_tx = (UI_16)0; + tp_data[tp_hdl].rx_st.frame_fc_type = TP_NO_FC_FRM; + tp_data[tp_hdl].rx_st.next_segm_num_rx = (UI_8)0; + tp_data[tp_hdl].tx_st.next_segm_num_tx = (UI_8)0; + tp_data[tp_hdl].rx_st.num_frames_before_fc = (UI_16)0; + tp_data[tp_hdl].tx_st.frame_tx_fc_sts = TP_TX_CONFIRMED; +#endif + + /* INITIALIZE THE TP TIMERS */ + tp_data[tp_hdl].timers.n_as = (t_clock)0; +#ifdef TP_MODE_FULL + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + tp_data[tp_hdl].timers.n_ar = (t_clock)0; + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; +#endif + + /* Initialize the TP user dynamic configuration parameters */ + TPDynamicParametersInitCallback(tp_hdl); + +#ifdef TP_MODE_FULL + /* Initialize the TP task to receive the CAN frames */ + TP_NetworkLayerLowerInterface_RxInicialitza(tp_hdl); + /* Initialize the TP TX FSM */ + TP_Tx_FullInicialitza(tp_hdl); + /* Initialize the TP RX FSM */ + TP_Rx_FullInicialitza(tp_hdl); + /* Initialize the TP funtional RX FSM */ + TP_RxFunInicialitza(tp_hdl); + /* Initialize the TP task to transmit the CAN frames */ + TP_NetworkLayerLowerInterface_TxInicialitza(tp_hdl); +#else + /* Initialize the TP task to receive the CAN frames */ + TP_NetworkLayerLowerInterface_RxInicialitza(tp_hdl); + /* Initialize the TP TX FSM */ + TP_Tx_LiteInicialitza(tp_hdl); + /* Initialize the TP RX FSM */ + TP_Rx_LiteInicialitza(tp_hdl); + /* Initialize the TP funtional RX FSM */ + TP_RxFunInicialitza(tp_hdl); + /* Initialize the TP task to transmit the CAN frames */ + TP_NetworkLayerLowerInterface_TxInicialitza(tp_hdl); +#endif + + } +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that execute all the FSM tasks that are involved in the transport +| protocol sending and reception. +| This routine must be called at each program cycle in main. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: TP handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPTask(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + +#ifdef TP_MODE_FULL + /* Execute the TP task to receive the CAN frames */ + TP_NetworkLayerLowerInterface_Rx(tp_hdl); + /* Execute the TP TX task */ + TP_Tx_Full(tp_hdl); + /* Execute the TP RX task */ + TP_Rx_Full(tp_hdl); + /* Execute the TP RX functional task */ + TP_RxFun(tp_hdl); + /* Execute the TP task to transmit the CAN frames */ + TP_NetworkLayerLowerInterface_Tx(tp_hdl); +#else + /* Execute the TP task to receive the CAN frames */ + TP_NetworkLayerLowerInterface_Rx(tp_hdl); + /* Execute the TP TX task */ + TP_Tx_Lite(tp_hdl); + /* Execute the TP RX task */ + TP_Rx_Lite(tp_hdl); + /* Execute the TP RX functional task */ + TP_RxFun(tp_hdl); + /* Execute the TP task to transmit the CAN frames */ + TP_NetworkLayerLowerInterface_Tx(tp_hdl); +#endif + + } +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to initialize an ISO15765_2 instance with the configuration +| parameters needed by the application. +| This routine must be called from the callback routine in which the user +| must configure the dynamic parameters that must be called +| TPDynamicParametersInitCallback +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| init_data: ISO15765_2 configuration parameters to be taken by the +| given handler +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPInitData(UI_8 tp_hdl, t_tp_init * init_data) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Initialize the dynamic parameters with the init value given by the user */ +#ifdef TP_MODE_FULL + tp_data[tp_hdl].cfg.np_max_frm_size = init_data->max_frm_size; + tp_data[tp_hdl].cfg.n_cr_max = init_data->cr_timer; + tp_data[tp_hdl].cfg.n_bs_max = init_data->bs_timer; + tp_data[tp_hdl].cfg.stmin = init_data->stmin_timer; + tp_data[tp_hdl].cfg.block_size = init_data->block_size; + tp_data[tp_hdl].cfg.n_wftmax = init_data->max_fc_wait; +#endif + tp_data[tp_hdl].cfg.np_can_frm_size_fixed = init_data->frm_size_fixed; + tp_data[tp_hdl].cfg.np_rx_padding_sensitive = init_data->rx_padding_sensitive; + tp_data[tp_hdl].cfg.np_tx_padding_value = init_data->tx_padding_value; + tp_data[tp_hdl].can_phy.can_handler = init_data->can_handler; + tp_data[tp_hdl].can_phy.sig_np_rx = init_data->sig_np_rx_phy; + tp_data[tp_hdl].can_phy.sig_np_tx = init_data->sig_np_tx_phy; + tp_data[tp_hdl].can_fun.sig_np_rx = init_data->sig_np_rx_fun; + tp_frm[tp_hdl].data_tx = init_data->tx_phy_buffer; + tp_frm[tp_hdl].data_rx = init_data->rx_phy_buffer; + tp_fun_frm[tp_hdl].data_rx = init_data->rx_fun_buffer; + + } +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to process the last received physical CAN frame. This routine +| will get the data bytes, the length and the type of transport protocol +| frame using the CAN interfaces. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPProcessRxCanPhyFrame(UI_8 tp_hdl) +{ // uint8 index; + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + BOOL test_can_frm_size; + UI_8 rx_can_frame[CAN_FRM_MAX_SIZE]; + UI_8 rx_can_len, type, i; + + /* Receive the physical CAN frame */ + + + + (void)ReceiveDynamicMessage(tp_data[tp_hdl].can_phy.sig_np_rx, + (t_application_data_ref)rx_can_frame, + (t_length_ref)&rx_can_len); + + //<< + //AlwaysEntry + //>> + + /* Check if TP is configured with fixed size and RX length case sensitive */ + if((tp_data[tp_hdl].cfg.np_can_frm_size_fixed == TRUE) && + (tp_data[tp_hdl].cfg.np_rx_padding_sensitive == TRUE)) { + /* Check that the received frame has 8 bytes of length */ + test_can_frm_size = (rx_can_len == CAN_FRM_MAX_SIZE); + } + else { + /* Check that the frame at least has one byte of data */ + test_can_frm_size = (rx_can_len > 0); + } + + /* Check that we received a frame with correct data size according configuration of TP */ + if(test_can_frm_size == TRUE) { + /* Get the TP frame type */ + type = rx_can_frame[0] >> (UI_8)4; + /* Check if the frame is a valid TP frame type */ + switch(type) { + case SF_TYPE: + /* Set the SINGLE FRAME type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_SF; + /* Copy the received data to the structure */ + for(i=0; i<8; i++) { + tp_data[tp_hdl].rx_st.frame_rx_data[i] = rx_can_frame[i]; + } + /* Copy the received data length to the structure */ + tp_data[tp_hdl].rx_st.frame_rx_len = rx_can_len; + break; +#ifdef TP_MODE_FULL + case FF_TYPE: + /* A first frame must have maximum CAN length */ + if(rx_can_len == CAN_FRM_MAX_SIZE) { + /* Set the FIRST FRAME type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_FF; + /* Copy the received data to the structure */ + for(i=0; i<8; i++) { + tp_data[tp_hdl].rx_st.frame_rx_data[i] = rx_can_frame[i]; + } + /* Copy the received data length to the structure */ + tp_data[tp_hdl].rx_st.frame_rx_len = rx_can_len; + } + else { + /* Non valid FF */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + } + break; + case CF_TYPE: + /* Check if the length is valid according to CF. It shall be 8 bytes */ + /* except for the case of last CF */ + if((rx_can_len != CAN_FRM_MAX_SIZE) && ((tp_data[tp_hdl].rx_st.byte_actual_rx + (UI_16)(rx_can_len-(UI_8)1)) < tp_frm[tp_hdl].size_rx)) { + /* Ignore CF as it is not the last CF and length is different from 8 bytes */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + } + else { + /* Set the CONSECUTIVE FRAME type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_CF; + /* Copy the received data to the structure */ + for(i=0; i<8; i++) { + tp_data[tp_hdl].rx_st.frame_rx_data[i] = rx_can_frame[i]; + } + /* Copy the received data length to the structure */ + tp_data[tp_hdl].rx_st.frame_rx_len = rx_can_len; + } + break; + case FC_TYPE: + /* Set the FLOW CONTROL type */ + tp_data[tp_hdl].rx_st.frame_fc_type = TP_FC; + /* Copy the received data to the structure */ + for(i=0; i<8; i++) { + tp_data[tp_hdl].rx_st.frame_rx_fc_data[i] = rx_can_frame[i]; + } + /* Copy the received data length to the structure */ + tp_data[tp_hdl].rx_st.frame_rx_fc_len = rx_can_len; + break; +#endif + default: + /* No valid frame has been received */ + break; + } + } + else { + /* Do nothing */ + } + } +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if any of the possible pending transport protocol +| transmission frames are pending to be transmitted. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: boolean that indicates if transmission is pending +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckTxCanFrame(UI_8 tp_hdl, t_tp_tx_type *tp_tx_type) +{ + BOOL result = FALSE; + //uint8 index_3; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + +#ifdef TP_MODE_FULL + /* Check if a FC will be the next TP frame to be sent */ + if(tp_data[tp_hdl].tx_st.frame_tx_fc_sts == TP_TX_REQUESTED) { + /* Notify that FC frame will be the next */ + result = TRUE; + *tp_tx_type = TP_TX_TYPE_FC; + } + /* Check if a SF, FF or CF will be the next TP frame to be sent */ + else if(tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_REQUESTED) { + /* Notify that SF, FF or CF frame will be the next */ + result = TRUE; + *tp_tx_type = TP_TX_TYPE_SF_FF_CF; + } + else { + /* Notify that no frame is pending */ + result = FALSE; + *tp_tx_type = TP_TX_TYPE_NONE; + } +#else + /* Check if a SF will be the next TP frame to be sent */ + if(tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_REQUESTED) { + /* Notify that SF frame will be the next */ + result = TRUE; + *tp_tx_type = TP_TX_TYPE_SF_FF_CF; + } + else { + /* Notify that no frame is pending */ + result = FALSE; + *tp_tx_type = TP_TX_TYPE_NONE; + } +#endif + + } + return result; +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that triggers the sending of a transport protocol frame (SF, FF, CF +| or flow control). The priority of the transmission frames will be given by +| the order of checking each of the flags in the IF condition. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPProcessTxCanFrame(UI_8 tp_hdl) +{ + //uint8 index_1; + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + /* Test here*/ + if (tp_hdl < TP_NUM_INSTANCES){ + +#ifdef TP_MODE_FULL + if(tp_data[tp_hdl].tx_st.frame_tx_fc_sts == TP_TX_REQUESTED) { + //<> + + /* Send the flow control on CAN */ + (void)SendDynamicMessage(tp_data[tp_hdl].can_phy.sig_np_tx, + (t_application_data_ref)&tp_data[tp_hdl].tx_st.frame_tx_fc_data[0], + (t_length_ref)&tp_data[tp_hdl].tx_st.frame_tx_fc_len); + /* Update the FC status of transmission */ + tp_data[tp_hdl].tx_st.frame_tx_fc_sts = TP_TX_ON_GOING; + } + /* Check if any of the transmission frames are pending */ + else if(tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_REQUESTED) { +#else + /* Check if any of the transmission frames are pending */ + if(tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_REQUESTED) { +#endif + + + //<> + /* Send the TX frame on CAN */ + (void)SendDynamicMessage(tp_data[tp_hdl].can_phy.sig_np_tx, + (t_application_data_ref)&tp_data[tp_hdl].tx_st.frame_tx_data[0], + (t_length_ref)&tp_data[tp_hdl].tx_st.frame_tx_len); + /* Update the status of frame the transmission */ + tp_data[tp_hdl].tx_st.frame_tx_sts = TP_TX_ON_GOING; + } + else { + /* Do nothing */ + } + } + + //<> +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if Osekcom notified the transmission of the TX last +| frame +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: TRUE if transmission has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckCanFrameConfirmation(UI_8 tp_hdl) +{ + t_flag_value tx_phy_notif; + BOOL result = FALSE; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Check if transmission has been confirmed */ + tx_phy_notif = ReadFlagTxSig(tp_data[tp_hdl].can_phy.sig_np_tx); + /* Check if has been confirmed */ + if(tx_phy_notif == COM_TRUE) { + /* Notify the TX confirmation */ + result = TRUE; + } + else { + /* Do nothing */ + } + } + + return result; +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if for a given transmission frame (which could be +| a "Flow Control", a "First Frame, a "Consecutive Frame" or a "Single Frame") +| his transmission has been confirmed. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| tx_sts: current transmission status of the requested frame +| result: TRUE if transmission has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckTxConfirmed(UI_8 tp_hdl, t_tp_tx_sts tx_sts) +{ + BOOL result = TRUE; + BOOL can_conf; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Check if the frame TX status has been already confirmed */ + if(tx_sts == TP_TX_CONFIRMED) { + /* Do nothing */ + } + else { + /* Get CAN frame confirmation */ + can_conf = TPCheckCanFrameConfirmation(tp_hdl); + /* Check if CAN frame has been confirmed after last execution of NetworkLayerLowerInterface */ + /* and we let the TP_Tx_Full FSM to continue in order to avoid waiting 5 ms */ + if((tx_sts == TP_TX_ON_GOING) && (can_conf == TRUE)) { + /* Do nothing */ + } + else { + /* Notify that transmission is still not confirmed */ + result = FALSE; + } + } + } + return result; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to notify a new transmission frame status for a transmission +| which still has his status as ongoing +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| tx_sts: new status to be set instead of ongoing +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPNotifyCanFrmTx(UI_8 tp_hdl, t_tp_tx_sts tx_sts) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Check which frame was being sent */ + if(tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_ON_GOING) { + /* Update TX frame status as confirmed */ + tp_data[tp_hdl].tx_st.frame_tx_sts = tx_sts; + //<>// + } +#ifdef TP_MODE_FULL + else if(tp_data[tp_hdl].tx_st.frame_tx_fc_sts == TP_TX_ON_GOING) { + /* Update TX FC status as confirmed */ + tp_data[tp_hdl].tx_st.frame_tx_fc_sts = tx_sts; + } +#endif + else { + /* Do nothing */ + } + } +} + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if there are still more frames pending to be sent. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: TRUE if there are not more pending frames to be sent. +| FALSE if there are still more pending frames to be sent +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPTestEndFrame(UI_8 tp_hdl) +{ + BOOL test_value = FALSE; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + +#ifdef TP_MODE_FULL + /* Check if the requested TP TX size has been already requested */ + /* to be transmitted to the low layer (OSEKCOM) */ + if(tp_frm[tp_hdl].size_tx <= tp_data[tp_hdl].tx_st.byte_actual_tx) { + /* Notify that the frame TX is finished */ + test_value = TRUE; + } + else { + /* Notify that the frame TX is not finished */ + test_value = FALSE; + } +#else + /* In lite mode only single frames are transmitted so once the frame is sent */ + /* we are sure that the whole length of data has been sent */ + test_value = TRUE; +#endif + + } + return test_value; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a single frame. Remember that a SF is +| used only to sent network frames with equal ore less than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendSF(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + #ifdef TP_MODE_FULL + /* Reset flow control reception notification */ + tp_data[tp_hdl].rx_st.frame_fc_type = TP_NO_FC_FRM; + #endif + + /* Indicacio de que es tracta d'un single frame i volcat de la mida de les dades */ + /* NPCI = 0x0X; (0x00 = SingleFrame) or (0x0X = numero de bytes de datos) */ + tp_data[tp_hdl].tx_st.frame_tx_data[0] = (UI_8)tp_frm[tp_hdl].size_tx; + + /* Volcat de les dades */ + tp_data[tp_hdl].tx_st.frame_tx_data[1] = tp_frm[tp_hdl].data_tx[0]; + tp_data[tp_hdl].tx_st.frame_tx_data[2] = tp_frm[tp_hdl].data_tx[1]; + tp_data[tp_hdl].tx_st.frame_tx_data[3] = tp_frm[tp_hdl].data_tx[2]; + tp_data[tp_hdl].tx_st.frame_tx_data[4] = tp_frm[tp_hdl].data_tx[3]; + tp_data[tp_hdl].tx_st.frame_tx_data[5] = tp_frm[tp_hdl].data_tx[4]; + tp_data[tp_hdl].tx_st.frame_tx_data[6] = tp_frm[tp_hdl].data_tx[5]; + tp_data[tp_hdl].tx_st.frame_tx_data[7] = tp_frm[tp_hdl].data_tx[6]; + +#ifdef TP_MODE_FULL + /* Set the size of the single frame data sent */ + tp_data[tp_hdl].tx_st.byte_actual_tx = tp_frm[tp_hdl].size_tx; +#endif + + /* Check if the size of the diagnostic frames must be fixed (8 bytes) */ + if(tp_data[tp_hdl].cfg.np_can_frm_size_fixed == TRUE) { + UI_8 aux; + /* Omplenat amb zeros dels bytes no utils i indicacio de la mida de les dades */ + for (aux=(UI_8)tp_frm[tp_hdl].size_tx + (UI_8)1; aux < CAN_FRM_MAX_SIZE; aux++) { + tp_data[tp_hdl].tx_st.frame_tx_data[aux] = tp_data[tp_hdl].cfg.np_tx_padding_value; + } + /* Set the maximum CAN frame length */ + tp_data[tp_hdl].tx_st.frame_tx_len = CAN_FRM_MAX_SIZE; + } + else { + /* Set the SF length */ + tp_data[tp_hdl].tx_st.frame_tx_len = (UI_8)(tp_frm[tp_hdl].size_tx + (UI_8)1); + } + + /* Check if TP must be unblocked */ + if(tp_frm[tp_hdl].unblock_after_tx == TRUE) { + /* Allow new requests */ + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + } + else { + /* Do nothing */ + } + + /* Request the transmission of the frame */ + //<>// + tp_data[tp_hdl].tx_st.frame_tx_sts = TP_TX_REQUESTED; + + } +} + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a first frame. Remember that a first +| frame is used to send the initial network frame with more than 8 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendFF(UI_8 tp_hdl) +{ + UI_16 npci; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Reset flow control reception notification */ + tp_data[tp_hdl].rx_st.frame_fc_type = TP_NO_FC_FRM; + + /* Indicacio de que es tracta d'un first frame i volcat de la mida de les dades */ + /* NPCI = 0x1XXX; (0x10 = FirstFrame) or (0x0XXX = numero de bytes de datos) */ + npci = tp_frm[tp_hdl].size_tx | (UI_16)0x1000; + /* La parte alta en el byte 0 */ + tp_data[tp_hdl].tx_st.frame_tx_data[0] = (UI_8)(npci >> 8); + /* La parte baja del NPCI ira en el byte 1. */ + tp_data[tp_hdl].tx_st.frame_tx_data[1] = (UI_8)npci; + /* Apuntador al byte actual */ + tp_data[tp_hdl].tx_st.byte_actual_tx = (UI_8)6; + /* Num del proxim segment */ + tp_data[tp_hdl].tx_st.next_segm_num_tx = (UI_8)1; + /* Volcat de les dades */ + tp_data[tp_hdl].tx_st.frame_tx_data[2] = tp_frm[tp_hdl].data_tx[0]; + tp_data[tp_hdl].tx_st.frame_tx_data[3] = tp_frm[tp_hdl].data_tx[1]; + tp_data[tp_hdl].tx_st.frame_tx_data[4] = tp_frm[tp_hdl].data_tx[2]; + tp_data[tp_hdl].tx_st.frame_tx_data[5] = tp_frm[tp_hdl].data_tx[3]; + tp_data[tp_hdl].tx_st.frame_tx_data[6] = tp_frm[tp_hdl].data_tx[4]; + tp_data[tp_hdl].tx_st.frame_tx_data[7] = tp_frm[tp_hdl].data_tx[5]; + /* Set the maximum CAN length frame */ + tp_data[tp_hdl].tx_st.frame_tx_len = CAN_FRM_MAX_SIZE; + + /* Request the transmission of the frame */ + tp_data[tp_hdl].tx_st.frame_tx_sts = TP_TX_REQUESTED; + } +} +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a consecutive frame. Remember that CF +| are used after sending a FF when the network frame has more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendCF(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Reset flow control reception notification */ + tp_data[tp_hdl].rx_st.frame_fc_type = TP_NO_FC_FRM; + + /* Indicacio de que es tracta d'un cosecutive frame i volcat del numero de segment */ + /* NPCI = 0x2X; (0x20 = ConsecutiveFrame) or (0x0X = numero de segmento) */ + tp_data[tp_hdl].tx_st.frame_tx_data[0] = tp_data[tp_hdl].tx_st.next_segm_num_tx | (UI_8)0x20; + if (tp_data[tp_hdl].tx_st.next_segm_num_tx >= MAX_NUM_SEG) { + tp_data[tp_hdl].tx_st.next_segm_num_tx = (UI_8)0; + } + else { + tp_data[tp_hdl].tx_st.next_segm_num_tx++; + } + + /* Volcat de les dades */ + tp_data[tp_hdl].tx_st.frame_tx_data[1] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[2] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[3] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[4] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[5] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[6] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + tp_data[tp_hdl].tx_st.frame_tx_data[7] = tp_frm[tp_hdl].data_tx[tp_data[tp_hdl].tx_st.byte_actual_tx]; + tp_data[tp_hdl].tx_st.byte_actual_tx++; + + if (tp_frm[tp_hdl].size_tx <= tp_data[tp_hdl].tx_st.byte_actual_tx) { + /* Check if the size of the diagnostic frames must be fixed (8 bytes) */ + if(tp_data[tp_hdl].cfg.np_can_frm_size_fixed == TRUE) { + UI_8 aux; + /* Omplenat amb zeros dels bytes no utils i indicacio de la mida de les dades */ + for (aux=(UI_8)0 ; aux < tp_data[tp_hdl].tx_st.byte_actual_tx - tp_frm[tp_hdl].size_tx ; aux++) { + /* Polyspace Defensive code to make the tool to understand that padding is only applicable to last frame. */ + if (aux < 6) { + tp_data[tp_hdl].tx_st.frame_tx_data[CAN_FRM_MAX_SIZE - ((UI_8)1) - aux] = tp_data[tp_hdl].cfg.np_tx_padding_value; + } + else { + /* Do nothing */ + } + } + /* Set the maximum CAN length frame */ + tp_data[tp_hdl].tx_st.frame_tx_len = CAN_FRM_MAX_SIZE; + } + else { + /* Set the consecutive frame length */ + tp_data[tp_hdl].tx_st.frame_tx_len = (UI_8)(CAN_FRM_MAX_SIZE + tp_frm[tp_hdl].size_tx - tp_data[tp_hdl].tx_st.byte_actual_tx); + } + + /* Check if TP must be unblocked */ + if(tp_frm[tp_hdl].unblock_after_tx==TRUE) { + /* Allow new requests */ + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + } + else { + /* Do nothing */ + } + } + else { + /* Set the maximum CAN frame length size */ + tp_data[tp_hdl].tx_st.frame_tx_len = CAN_FRM_MAX_SIZE; + } + + /* Request the transmission of the frame */ + tp_data[tp_hdl].tx_st.frame_tx_sts = TP_TX_REQUESTED; + } +} +#endif + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Single Frame" with physical +| address. Remember that a SF is a frame with equal or less than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadSF(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + UI_8 rx_sf_size; + + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + + /* Get the received SF length */ + rx_sf_size = tp_data[tp_hdl].rx_st.frame_rx_data[0] & ((UI_8)(0x0F)); + + /* Check if the size is correct and the ISO_2 is not blocked */ + if ((tp_frm[tp_hdl].iso15765_2_block_rx == FALSE) && + (rx_sf_size < tp_data[tp_hdl].rx_st.frame_rx_len) && + (rx_sf_size > (UI_8)0) && + (rx_sf_size <= NP_SF_MAX_SIZE)) { + /* Volcat de la mida de les dades */ + tp_frm[tp_hdl].size_rx = rx_sf_size; + /* Comprovacio de que la mida de les dades indicada a la trama no es igual a 0 seguint SR1431 */ + if ((tp_frm[tp_hdl].size_rx != (UI_8)(0x00)) && (tp_frm[tp_hdl].size_rx <= NP_SF_MAX_SIZE)) { + /* Volcat de les dades */ + tp_frm[tp_hdl].data_rx[0] = tp_data[tp_hdl].rx_st.frame_rx_data[1]; + tp_frm[tp_hdl].data_rx[1] = tp_data[tp_hdl].rx_st.frame_rx_data[2]; + tp_frm[tp_hdl].data_rx[2] = tp_data[tp_hdl].rx_st.frame_rx_data[3]; + tp_frm[tp_hdl].data_rx[3] = tp_data[tp_hdl].rx_st.frame_rx_data[4]; + tp_frm[tp_hdl].data_rx[4] = tp_data[tp_hdl].rx_st.frame_rx_data[5]; + tp_frm[tp_hdl].data_rx[5] = tp_data[tp_hdl].rx_st.frame_rx_data[6]; + tp_frm[tp_hdl].data_rx[6] = tp_data[tp_hdl].rx_st.frame_rx_data[7]; + + /* Notificacio a la capa superior de l'arribada d'una nova trama */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_NOTIF; + /* Block TP reception */ + tp_frm[tp_hdl].iso15765_2_block_rx = TRUE; + } + else { + /* Ignorar la trama */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + } + } + else { + /* Ignorar la trama */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + } + } +} + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "First Frame" and request directly +| the sending of a Flow Control as always after receiving a FF a FC must +| be sent by protocol. Remember that a FF is a frame with more than 7 +| bytes. Remember that a FC is used to control the flow of the reception +| of a frame with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadFFSendFC(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + + /* Check that conditions are correct to receive a FF */ + if (tp_data[tp_hdl].rx_st.frame_rx_len == CAN_FRM_MAX_SIZE) { + /* Volcat de la mida de les dades */ + tp_frm[tp_hdl].size_rx =(UI_8)(tp_data[tp_hdl].rx_st.frame_rx_data[0] & ((UI_8)(0x0F))); + tp_frm[tp_hdl].size_rx <<= (UI_8)8; + tp_frm[tp_hdl].size_rx |= tp_data[tp_hdl].rx_st.frame_rx_data[1]; + tp_data[tp_hdl].rx_st.byte_actual_rx = (UI_8)6; + + /* Comprovacio que la trama en proces de recepcio cap */ + /* dins del buffer de recepcio */ + if (tp_frm[tp_hdl].size_rx <= tp_data[tp_hdl].cfg.np_max_frm_size) { + /* Comprovacio que la mida de la trama es major que el */ + /* tamany maxim d'un SF seguint SR1681 */ + if(tp_frm[tp_hdl].size_rx > NP_SF_MAX_SIZE) { + + /* Volcat del num del proxim segment */ + tp_data[tp_hdl].rx_st.next_segm_num_rx = (UI_8)1; + + /* Volcat de les dades */ + tp_frm[tp_hdl].data_rx[0] = tp_data[tp_hdl].rx_st.frame_rx_data[2]; + tp_frm[tp_hdl].data_rx[1] = tp_data[tp_hdl].rx_st.frame_rx_data[3]; + tp_frm[tp_hdl].data_rx[2] = tp_data[tp_hdl].rx_st.frame_rx_data[4]; + tp_frm[tp_hdl].data_rx[3] = tp_data[tp_hdl].rx_st.frame_rx_data[5]; + tp_frm[tp_hdl].data_rx[4] = tp_data[tp_hdl].rx_st.frame_rx_data[6]; + tp_frm[tp_hdl].data_rx[5] = tp_data[tp_hdl].rx_st.frame_rx_data[7]; + + /* Notificacio a la capa superior de l'arribada d'una nova trama */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_IN_PRG; + + /* Enviar FC positivament */ + TPSendFC(tp_hdl, TP_FLOW_STS_CTS); + } + else { + /* Ignorar la trama */ + } + } + else { + /* Notificacio a la capa superior de l'arribada d'una nova trama amb error */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_FINISHED; + /* Enviar FC notificant l'overflow en el tamany de dades */ + TPSendFC(tp_hdl, TP_FLOW_STS_OVFLW); + } + } + else { + /* Ignorar la trama */ + } + } +} +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a flow control. Remember that a FC is +| used to control the flow of the reception of a frame with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| flow_control_type: type of the flow control that must be sent +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendFC(UI_8 tp_hdl, t_tp_flow_sts flow_control_type) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Enviament de de la trama flow control */ + /* Indicacio de que es tracta d'un flow control */ + /* frame i volcat Flow control status */ + tp_data[tp_hdl].tx_st.frame_tx_fc_data[0]= (UI_8)flow_control_type | ((UI_8)0x30); + /* Volcat del BS */ + tp_data[tp_hdl].tx_st.frame_tx_fc_data[1]=tp_data[tp_hdl].cfg.block_size; + /* Volcat del ST_MIN */ + tp_data[tp_hdl].tx_st.frame_tx_fc_data[2]=(UI_8)tp_data[tp_hdl].cfg.stmin; + + /* Check if the size of the frame shall be fixed to 8 bytes */ + if(tp_data[tp_hdl].cfg.np_can_frm_size_fixed == TRUE) { + /* Omplenat amb zeros dels bytes no utils i */ + /* indicacio de la mida de les dades */ + tp_data[tp_hdl].tx_st.frame_tx_fc_data[3] = tp_data[tp_hdl].cfg.np_tx_padding_value; + tp_data[tp_hdl].tx_st.frame_tx_fc_data[4] = tp_data[tp_hdl].cfg.np_tx_padding_value; + tp_data[tp_hdl].tx_st.frame_tx_fc_data[5] = tp_data[tp_hdl].cfg.np_tx_padding_value; + tp_data[tp_hdl].tx_st.frame_tx_fc_data[6] = tp_data[tp_hdl].cfg.np_tx_padding_value; + tp_data[tp_hdl].tx_st.frame_tx_fc_data[7] = tp_data[tp_hdl].cfg.np_tx_padding_value; + /* Set the length to the maximum CAN frame size */ + tp_data[tp_hdl].tx_st.frame_tx_fc_len = CAN_FRM_MAX_SIZE; + } + else { + /* Set the flow control length */ + tp_data[tp_hdl].tx_st.frame_tx_fc_len = (UI_8)3; + } + + /* Request the transmission of the frame */ + tp_data[tp_hdl].tx_st.frame_tx_fc_sts = TP_TX_REQUESTED; + } +} +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Consecutive Frame". Remember +| that consecutive frames are received after receiving the first frame +| with network frames with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadCF(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + UI_8 segm_num; + UI_8 aux; + + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + + /* Check if the received length of the frame is correct */ + if (tp_frm[tp_hdl].iso15765_2_block_rx == FALSE) { + segm_num = (UI_8)(tp_data[tp_hdl].rx_st.frame_rx_data[0] & ((UI_8)0x0F)); + if (segm_num == tp_data[tp_hdl].rx_st.next_segm_num_rx) { + if (tp_data[tp_hdl].rx_st.next_segm_num_rx >= MAX_NUM_SEG) { + tp_data[tp_hdl].rx_st.next_segm_num_rx = (UI_8)0; + } + else { + tp_data[tp_hdl].rx_st.next_segm_num_rx++; + } + + /* Volcat de les dades */ + for (aux=(UI_8)1; aux < tp_data[tp_hdl].rx_st.frame_rx_len; aux++) { + tp_frm[tp_hdl].data_rx[tp_data[tp_hdl].rx_st.byte_actual_rx] = tp_data[tp_hdl].rx_st.frame_rx_data[aux]; + tp_data[tp_hdl].rx_st.byte_actual_rx++; + } + + if (tp_frm[tp_hdl].size_rx <= tp_data[tp_hdl].rx_st.byte_actual_rx) { + /* Notificacio a la capa superior de l'arribada d'una nova trama */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_FINISHED; + /* Block TP reception */ + tp_frm[tp_hdl].iso15765_2_block_rx = TRUE; + } + else if (tp_data[tp_hdl].rx_st.frame_rx_len != CAN_FRM_MAX_SIZE) { + /* Notificacio a la capa superior de l'arribada d'una nova trama amb error */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_FINISHED; + } + else { + /* No fer res */ + } + } + else { + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_FINISHED; + } + } + else { + /* Ignorar la trama */ + } + } +} +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Consecutive Frame". Remember +| that consecutive frames are received after receiving the first frame +| with network frames with more than 7 bytes. This routine in case that +| the received frame is consistent and has the correct format will request +| the sending of a flow control. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadCFSendFC(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Read the consecutive frame */ + TPReadCF(tp_hdl); + + /* Check if the consecutive frame have the correct format */ + if(tp_frm[tp_hdl].sts_rx != TP_FRM_RX_ERR_FINISHED) { + /* Send a flow control */ + TPSendFC(tp_hdl, TP_FLOW_STS_CTS); + } + else { + /* Do nothing */ + } + } +} +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Flow Control" and request +| the sending of a "Consecutive Frame". Remember that "Flow Control" frames +| are used to control the flow of the transmission in case of network +| frames with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +/---------------------------------------------------------------------------*/ +void TPReadFCSendCF(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_fc_type = TP_NO_FC_FRM; + + /* Check if the size of the received frame is correct */ + if (tp_data[tp_hdl].rx_st.frame_rx_fc_len >= CAN_FRM_FC_SIZE) { + tp_data[tp_hdl].fc_data.flow_status = (t_tp_flow_sts)(tp_data[tp_hdl].rx_st.frame_rx_fc_data[0] & ((UI_8)0x0F)); + + /* Aixequem el flag de recepcio de flow control */ + tp_data[tp_hdl].fc_data.fc_rx = TRUE; + + /* Check if the flow control type is correct */ + if ((tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_CTS) || + (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_WT) || + (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_OVFLW)) { + + /* Check if this is the first flow control */ + if (tp_data[tp_hdl].fc_data.first_fc == TRUE) { + tp_data[tp_hdl].fc_data.first_fc = FALSE; + tp_data[tp_hdl].fc_data.rx_bs = tp_data[tp_hdl].rx_st.frame_rx_fc_data[1]; + /* Cas valors 0..127 */ + if (tp_data[tp_hdl].rx_st.frame_rx_fc_data[2] <= (UI_8)0x7F) { + tp_data[tp_hdl].fc_data.stmin = tp_data[tp_hdl].rx_st.frame_rx_fc_data[2]; + } + /* Cas valors F1..F9 i valors reservats */ + else { + /* Renault specification in document 36-02-031--A_Gb.pdf page 15 */ + tp_data[tp_hdl].fc_data.stmin = (UI_8)0x7F; + } + } + else { + /* Ignorar bs i stmin */ + } + /* Cas en que el Flow Control indica ClearToSend */ + if (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_CTS) { + /* Enviar el primer Consecutive Frame */ + TPSendCF(tp_hdl); + } + /* Cas en que el Flow Control no indica ClearToSend */ + else { + /* Esperar proxim Flow Control */ + } + } + else { + /* Do nothing */ + } + } + else { + /* Ignorar la trama */ + } + } +} +#endif + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a functional CAN frame. Remember that in functional +| channel any frame with a type different from SF will be ignored as the +| maximum allowed size for this channel is 7. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadFunFrm(UI_8 tp_hdl) +{ + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + UI_8 rx_can_frame[CAN_FRM_MAX_SIZE]; + UI_8 rx_can_len,rx_sf_size; + //BOOL test_can_frm_size; + + /* Receive the CAN frame */ + (void)ReceiveDynamicMessage(tp_data[tp_hdl].can_fun.sig_np_rx, + (t_application_data_ref)rx_can_frame, + (t_length_ref)&rx_can_len); + + /* Check that the notified RX length is correct according to the received CAN frame length */ + /* Longitud 0 Payload shall be rejected */ + rx_sf_size = rx_can_frame[0] & ((UI_8)(0x0F)); + + /* Verificacio de la mida i del tipus de trama */ + if (((rx_can_frame[0] >> (UI_8)4) == TP_RX_SF) && + (rx_sf_size > (UI_8)0) && + ((rx_can_frame[0] & (UI_8)0x0F) <= NP_SF_MAX_SIZE)) { + /* Volcat de la mida de les dades */ + tp_fun_frm[tp_hdl].size = (UI_8)(rx_can_frame[0] & (UI_8)0x0F); + /* Save the received data */ + tp_fun_frm[tp_hdl].data_rx[0] = rx_can_frame[1]; + tp_fun_frm[tp_hdl].data_rx[1] = rx_can_frame[2]; + tp_fun_frm[tp_hdl].data_rx[2] = rx_can_frame[3]; + tp_fun_frm[tp_hdl].data_rx[3] = rx_can_frame[4]; + tp_fun_frm[tp_hdl].data_rx[4] = rx_can_frame[5]; + tp_fun_frm[tp_hdl].data_rx[5] = rx_can_frame[6]; + tp_fun_frm[tp_hdl].data_rx[6] = rx_can_frame[7]; + /* Notificacio a la capa superior de l'arribada d'una nova trama */ + tp_fun_frm[tp_hdl].sts_rx = TP_FRM_RX_NOTIF; + } + else { + /* Ignorar la trama */ + } + } +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check if the timeout of the transmission frame has been notfied. +| Remember that this timeout must be configured in the OSEKCOM database with +| the specified AX timeout defined. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if timeout has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckAxTimeout(UI_8 tp_hdl) +{ + t_flag_value ax_timeout = 0; + BOOL result =FALSE; + + /* To avoid Polyspace warning : "pointer may be outside its bounds" */ + if (tp_hdl < TP_NUM_INSTANCES){ + + /* Get the AX timeout from OSEKCOM */ + //ax_timeout = ReadFlagTxErrorSig(tp_data[tp_hdl].can_phy.sig_np_tx); + + /* Check if the timeout is confirmed */ + if(ax_timeout == COM_TRUE) { + result = TRUE; + } + else { + result = FALSE; + } + } + return result; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check that all the physical interface routines with OSEKCOM layer +| are correctly initialized +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if configuration is correct, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckPhyCfgData(UI_8 tp_hdl) +{ + BOOL result; + + /* Check that CAN interface routines are correctly initialized */ + result = ((BOOL)GetComApplicationMode() == (BOOL)COM_NORMAL_MODE); + + return result; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check that all the functional interface routines with OSEKCOM layer +| are correctly initialized +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if configuration is correct, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckFunCfgData(UI_8 tp_hdl) +{ + BOOL result; + + /* Check that CAN interface routines are correctly initialized */ + result = ((BOOL)GetComApplicationMode() == (BOOL)COM_NORMAL_MODE); + + return result; +} + diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.h b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.h new file mode 100644 index 0000000..0f6f614 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Functions.h @@ -0,0 +1,648 @@ +/*************** COPYRIGHT (c) 2002-2007 FICOSA INTERNATIONAL ************** +| Language: | MISRA C +| Controller: | Generic +| Spec. Document: | ISO15765-2-E.pdf +|-----------------|------------------------------------------------------------ +| Project: | ISO15765-2 +| Reference: | +|------------------------------------------------------------------------------ +| Date - Cod. - Rev. - App. - Description +| 12/09/02 AM Implementation of the kwp2000 for PSA. +| 19/08/04 DT Split ISO15765_2 protocol from the KWP2000 +| because they are different modules. +| 24/04/09 DC Modification to guarantee the requirements SR1431, +| SR1438, SR1681. +| 15/07/09 AC Corrected bug in ReadCF because it didn't count +| correctly the blocks +| 15/12/10 AC Converted ISO15765_2 protocol to multi-instance. +| 13/11/11 AC Converted ISO15765_2 to full-duplex +| 09/01/11 AC Changed file, routines and variable naming to +| make it a standard component and to have a +| similar naming style with MPDT. +| 07/05/15 FPR Removed TIMER_MS_TO_TICKS_R_UP macro. Now new macro +| TIMER_MS_TO_TIME_RESTRICTIVE is used instead. +| New macro implemented in HAL DSPIC (Timer.h). +|------------------------------------------------------------------------------ +| DESCRIPTION: +| User interface for the transport protocol ISO15765_2 on CAN. +| ISO15765_2 protocol is a transport protocol that permits the sending and +| reception of frames until 4096 bytes on a network protocol with frames of +| lower size. The original frame is segemented and sent with flow control +| data that allows to the reception node to mount again the original frame. +| GENERAL CONSIDERATIONS +| - This implementation allows full duplex communications. +| - This implementation allows for each instance a communication channel +| with physical address in which both transmission and receptions could +| be done and a funcional address for only receptions. +| - The functional address channel only supports frames with less than +| 8 bytes of data. +| - This header must only be included in the ISO15765_2 transport protocol +| source files but is forbidden to be included by the application as it +| contains the private data of the ISO15765_2 module. +******************************************************************************/ +#ifndef _TP_FUNCTIONS_H +#define _TP_FUNCTIONS_H + +/*----------------------------- INCLUDES ---------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP.h" + +/*----------------------------- MACROS ---------------------------------*/ + +/*----------------------------- DEFINES ----------------------------------*/ + +/* Maximum data bytes that a CAN frame can allocate */ +#define NP_SF_MAX_SIZE ((UI_8)7) + +/* Maximum useful data size that a Single Frame can allocate in bytes */ +#define CAN_FRM_MAX_SIZE ((UI_8)8) + +/* Maximum useful data size that a Consecutive Frame can allocate in bytes */ +#define CF_DATA_LEN ((UI_8)7) + +/*-------------------------- DATA TYEPS ----------------------------------*/ + +/* Interface between FICOSEKCOM and TP for physical frames */ +typedef struct { + t_can_handler can_handler; //ACF must be called OsekCom_Handler + t_symbolic_name sig_np_rx; /* OSEKCOM signal to receive the physical frame */ + t_symbolic_name sig_np_tx; /* OSEKCOM signal to request the sending of the phisical frame */ +} t_tp_can_phy_interface; + +/* Interface between FICOSEKCOM and TP for functional frames */ +typedef struct { + t_symbolic_name sig_np_rx; /* OSEKCOM signal to receive the functional frame */ +} t_tp_can_fun_interface; + +/* States of the TX PHYSICAL FRAME FSM */ +typedef enum { + ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_WAITINGTXCONFIRMATION = 1, + ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND = 2, + ESTAT_0_TP_NETWORKLAYERLOWERINTERFACE_TX = 0 +} t_estat_tp_networklayerlowerinterface_tx; + +/* If the ISO15765_2 is defined in full mode, define all the structures */ +/* that allow transport protocol communications with more than 7 data */ +/* bytes (one single frame) */ +#ifdef TP_MODE_FULL + +/* States of the RX FULL PHYSICAL FSM */ +typedef enum { + ESTAT_TP_RX_FULL_INICIO = 1, + ESTAT_TP_RX_FULL_RXCF = 2, + ESTAT_TP_RX_FULL_CONFIRMAFC = 3, + ESTAT_0_TP_RX_FULL = 0 +} t_estat_tp_rx_full; + +/* States of the TX FULL PHYSICAL FSM */ +typedef enum { + ESTAT_TP_TX_FULL_INICI = 1, + ESTAT_TP_TX_FULL_ESPERAFC = 2, + ESTAT_TP_TX_FULL_CONFIRMATX = 3, + ESTAT_0_TP_TX_FULL = 0 +} t_estat_tp_tx_full; + +/* Configuration parameters of the TP FULL */ +typedef struct { + UI_16 np_max_frm_size; /* Maximum size allowed for the diagnostics buffer. The protocol allows */ + /* frames until 4096 bytes. The buffer must be reserved having into */ + /* account the MACRO "SIZE_ALLOC_BUFFER" to avoid overflows. */ + BOOL np_can_frm_size_fixed; /* Flag to configure fixed or variable length in the CAN frames */ + /* Allowed values: */ + /* TRUE -> Totes les trames Tx s'envien amb 8 bytes amb els bytes no */ + /* utils a valor de padding configurat amb el parametre */ + /* np_tx_padding_value. Les trames Rx de menys de 8 bytes son */ + /* ignorades */ + /* FALSE -> Totes les trames s'envien i es reben amb la mida en funcio */ + /* dels bytes utils que contenen */ + BOOL np_rx_padding_sensitive;/* Flag to be taken into account if frm_size_fixed is defined as TRUE. */ + /* Allowed values: */ + /* TRUE -> RX TP frames with less than 8 bytes are ignored */ + /* FALSE -> RX TP frames with less than 8 bytes are processed */ + /* correctly if the frame has a correct TP format */ + UI_8 np_tx_padding_value; /* Padding value for the non valid bytes in case that */ + /* np_can_frm_size_fixed is configured to TRUE */ + UI_16 n_cr_max; /* Maximum timeout measured in ms between Consecutive frames before */ + /* aborting the reception due to time out */ + UI_16 n_bs_max; /* Time in ms between the first frame and the firs flow control or */ + /* between the last consecutive frame of a block and the flow control */ + /* before aborting the transmission due to timeout */ + UI_16 stmin; /* Time in ms between consecutive frames of the transmitter to allow */ + /* ourself to process the received frames without losing anyone */ + /* If the block size if different from 1, this time must be minimum the */ + /* cycle frequency, otherwise if this is 1 the stmin could be 0 */ + UI_8 block_size; /* Number of consecutive frames that the ECU will send without waiting */ + /* for a flow control before continuing. If the block size is set to 0 */ + /* means that only one flow control is needed after receiving the first */ + /* frame */ + UI_8 n_wftmax; /* Maximum number of FC wait that TP can handle in a row */ +} t_tp_cfg_full; + +/* Parameters to manage the Flow Controls in multiple frames */ +typedef struct { + t_tp_flow_sts flow_status; /* Flow control type */ + UI_8 rx_bs; /* Block size received from the other part that we must guarantee in a TX */ + UI_8 stmin; /* Stmin received from the other part that we must garantee between CF */ + BOOL first_fc; /* Flag that indicates if this is the first FC after a FF */ + BOOL fc_rx; /* Flag that notifies of the reception of a flow control */ + UI_8 block_size_cnt; /* Counter of the consecutive frames sent before waiting a FC */ + UI_8 num_fc_wait; /* Counter of the FC wait received */ +} t_tp_fc_data; + +/* Parameters to manage the TP FULL reception */ +typedef struct { + UI_8 next_segm_num_rx; /* Counter to manage the number of receive consecutive segments. */ + UI_16 byte_actual_rx; /* Counter to manage the number of received bytes. */ + UI_16 num_frames_before_fc; /* Number of consecutive frames received since last FC sent, in order to be */ + /* aware when another FC must be sent */ + t_tp_rx_frm frame_rx_type; /* Type of the last received CAN frame */ + UI_8 frame_rx_data[8]; /* Last RX frame received */ + UI_8 frame_rx_len; /* Last RX length */ + t_tp_fc_frm frame_fc_type; /* Type of the last received FC frame */ + UI_8 frame_rx_fc_data[8]; /* Last FC frame received */ + UI_8 frame_rx_fc_len; /* Last FC length */ +} t_tp_rx_status_full; + +/* Parameters to manage the TP FULL transmission */ +typedef struct { + BOOL ack_tx; /* Flag that notifies if the CAN layer has notified the TX of the last frame */ + UI_8 next_segm_num_tx; /* Counter to manage the number of sent consecutive segments. */ + UI_16 byte_actual_tx; /* Counter to manage the number of transmitted bytes. */ + t_tp_tx_sts frame_tx_sts; /* Flag that notifies the status of a TX data frame */ + UI_8 frame_tx_data[8]; /* TX frame data required */ + UI_8 frame_tx_len; /* TX length required */ + t_tp_tx_sts frame_tx_fc_sts;/* Flag that notifies the status of a FC data frame */ + UI_8 frame_tx_fc_data[8]; /* FC frame data required */ + UI_8 frame_tx_fc_len; /* FC length required */ +} t_tp_tx_status_full; + +/* Timers to control the TP FULL timeouts */ +typedef struct { + t_clock n_cr; /* Timer variable that controls the TP CR timeout */ + t_clock n_ar; /* Timer variable that controls the TP AR timeout */ + t_clock n_bs; /* Timer variable that controls the TP BS timeout */ + t_clock n_cs; /* Timer variable that controls the TP CS timeout */ + t_clock n_as; /* Timer variable that controls the TP AS timeout */ +} t_tp_timers_full; + +/* Structure that contains all the data needed for an TP FULL instance */ +typedef struct { + t_estat_tp_tx_full state_tx; /* State of the TP TX PHYSICAL FSM */ + t_estat_tp_rx_full state_rx; /* State of the TP RX PHYSICAL FSM */ + t_estat_tp_networklayerlowerinterface_tx state_can_phy_tx; /* State of the TP Network layer lower inteface FSM */ + t_tp_can_phy_interface can_phy; /* Interface with the network protocoal physical CAN structure */ + t_tp_can_fun_interface can_fun; /* Interface with the network protocoal functional CAN structure */ + t_tp_cfg_full cfg; /* Configuration of the TP */ + t_tp_fc_data fc_data; /* Estructura de dades de gestio del control de fluxe */ + t_tp_rx_status_full rx_st; /* Status of the TP transmission/reception */ + t_tp_tx_status_full tx_st; /* Status of the TP transmission/reception */ + t_tp_timers_full timers; /* Timers to control and assure the expected TP managment */ +} t_tp_data; + +/* If the ISO15765_2 is defined in lite mode, define all the structures */ +/* simplified that allow transport protocol communications equal or */ +/* less than 7 data bytes (only single frames) */ +#else + +/* States of the TX LITE PHYSICAL FSM */ +typedef enum { + ESTAT_TP_TX_LITE_INIT = 1, + ESTAT_TP_TX_LITE_CONFIRMTX = 2, + ESTAT_0_TP_TX_LITE = 0 +} t_estat_tp_tx_lite; + +/* Configuration parameters of the TP LITE */ +typedef struct { + BOOL np_can_frm_size_fixed; /* Flag to configure fixed or variable length in the CAN frames */ + /* Allowed values: */ + /* TRUE -> Totes les trames Tx s'envien amb 8 bytes amb els bytes no */ + /* utils a valor de padding configurat amb el parametre */ + /* np_tx_padding_value. Les trames Rx de menys de 8 bytes son */ + /* ignorades */ + /* FALSE -> Totes les trames s'envien i es reben amb la mida en funcio */ + /* dels bytes utils que contenen */ + BOOL np_rx_padding_sensitive;/* Flag to be taken into account if frm_size_fixed is defined as TRUE. */ + /* Allowed values: */ + /* TRUE -> RX TP frames with less than 8 bytes are ignored */ + /* FALSE -> RX TP frames with less than 8 bytes are processed */ + /* correctly if the frame has a correct TP format */ + UI_8 np_tx_padding_value; /* Padding value for the non valid bytes in case that */ + /* np_can_frm_size_fixed is configured to TRUE */ +} t_tp_cfg_lite; + +/* Parameters to manage the TP LITE reception */ +typedef struct { + t_tp_rx_frm frame_rx_type; /* Type of the last received CAN frame */ + UI_8 frame_rx_data[8]; /* Last RX frame received */ + UI_8 frame_rx_len; /* Last RX length */ +} t_tp_rx_status_lite; + +/* Parameters to manage the TP LITE transmission */ +typedef struct { + BOOL ack_tx; /* Flag that notifies if the CAN layer has notified the TX of the last frame */ + t_tp_tx_sts frame_tx_sts; /* Flag that notifies the status of a TX data frame */ + UI_8 frame_tx_data[8]; /* TX frame data required */ + UI_8 frame_tx_len; /* TX length required */ +} t_tp_tx_status_lite; + +/* Timers to control the TP LITE timeouts */ +typedef struct { + t_clock n_as; /* Timer variable that controls the TP AS timeout */ +} t_tp_timers_lite; + +/* Structure that contains all the data needed for an TP LITE instance */ +typedef struct { + t_estat_tp_tx_lite state_tx; /* State of the TP TX PHYSICAL FSM */ + t_estat_tp_networklayerlowerinterface_tx state_can_phy_tx; + t_tp_can_phy_interface can_phy; /* Interface with the network protocoal physical CAN structure */ + t_tp_can_fun_interface can_fun; /* Interface with the network protocoal functional CAN structure */ + t_tp_cfg_lite cfg; /* Configuration of the TP */ + t_tp_rx_status_lite rx_st; /* Status of the TP reception */ + t_tp_tx_status_lite tx_st; /* Status of the TP transmission */ + t_tp_timers_lite timers; /* Timers to control and assure the expected TP managment */ +} t_tp_data; + +#endif + +/*--------------------------- GLOBAL VARIABLES ---------------------------*/ + +/* Declaration of the tp_frm phisical and functional defined structures */ +extern t_tp_data tp_data[TP_NUM_INSTANCES]; + +/*--------------------------- ROUTINE PROTOTYPES ------------------------*/ + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to process the last received physical CAN frame. This routine +| will get the data bytes, the length and the type of transport protocol +| frame using the CAN interfaces. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPProcessRxCanPhyFrame(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if any of the possible pending transport protocol +| transmission frames are pending to be transmitted. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: boolean that indicates if transmission is pending +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckTxCanFrame(UI_8 tp_hdl, t_tp_tx_type *tp_tx_type); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that triggers the sending of a transport protocol frame (SF, FF, CF +| or flow control). The priority of the transmission frames will be given by +| the order of checking each of the flags in the IF condition. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPProcessTxCanFrame(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if Osekcom notified the transmission of the TX last +| frame +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: TRUE if transmission has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckCanFrameConfirmation(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if for a given transmission frame (which could be +| a "Flow Control", a "First Frame, a "Consecutive Frame" or a "Single Frame") +| his transmission has been confirmed. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| tx_sts: current transmission status of the requested frame +| result: TRUE if transmission has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckTxConfirmed(UI_8 tp_hdl, t_tp_tx_sts tx_sts); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to notify a new transmission frame status for a transmission +| which still has his status as ongoing +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| tx_sts: new status to be set instead of ongoing +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPNotifyCanFrmTx(UI_8 tp_hdl, t_tp_tx_sts tx_sts); + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine that checks if there are still more frames pending to be sent. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| result: TRUE if there are not more pending frames to be sent. +| FALSE if there are still more pending frames to be sent +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPTestEndFrame(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a single frame. Remember that a SF is +| used only to sent network frames with equal ore less than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendSF(UI_8 tp_hdl); + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a first frame. Remember that a first +| frame is used to send the initial network frame with more than 8 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendFF(UI_8 tp_hdl); +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a consecutive frame. Remember that CF +| are used after sending a FF when the network frame has more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendCF(UI_8 tp_hdl); +#endif + +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Single Frame" with physical +| address. Remember that a SF is a frame with equal or less than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadSF(UI_8 tp_hdl); + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "First Frame" and request directly +| the sending of a Flow Control as always after receiving a FF a FC must +| be sent by protocol. Remember that a FF is a frame with more than 7 +| bytes. Remember that a FC is used to control the flow of the reception +| of a frame with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadFFSendFC(UI_8 tp_hdl); +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to request the sending of a flow control. Remember that a FC is +| used to control the flow of the reception of a frame with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| flow_control_type: type of the flow control that must be sent +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPSendFC(UI_8 tp_hdl, t_tp_flow_sts flow_control_type); +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Consecutive Frame". Remember +| that consecutive frames are received after receiving the first frame +| with network frames with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadCF(UI_8 tp_hdl); +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Consecutive Frame". Remember +| that consecutive frames are received after receiving the first frame +| with network frames with more than 7 bytes. This routine in case that +| the received frame is consistent and has the correct format will request +| the sending of a flow control. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadCFSendFC(UI_8 tp_hdl); +#endif + +#ifdef TP_MODE_FULL +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a CAN frame of the type "Flow Control" and request +| the sending of a "Consecutive Frame". Remember that "Flow Control" frames +| are used to control the flow of the transmission in case of network +| frames with more than 7 bytes. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +/---------------------------------------------------------------------------*/ +void TPReadFCSendCF(UI_8 tp_hdl); +#endif + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to read a functional CAN frame. Remember that in functional +| channel any frame with a type different from SF will be ignored as the +| maximum allowed size for this channel is 7. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void TPReadFunFrm(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check if the timeout of the transmission frame has been notfied. +| Remember that this timeout must be configured in the OSEKCOM database with +| the specified AX timeout defined. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if timeout has been confirmed, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckAxTimeout(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check that all the physical interface routines with OSEKCOM layer +| are correctly initialized +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if configuration is correct, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckPhyCfgData(UI_8 tp_hdl); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| Routine to check that all the functional interface routines with OSEKCOM layer +| are correctly initialized +|--------------------------------------------------------------------------- +| Parameters Explanation: +| tp_hdl: ISO15765_2 handler to be used +| return: TRUE if configuration is correct, FALSE otherwise +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL TPCheckFunCfgData(UI_8 tp_hdl); + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c new file mode 100644 index 0000000..3939abb --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Rx.c @@ -0,0 +1,108 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_NetworkLayerLowerInterface_Rx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | Iso15765_2_Full +| System: | Iso15765_2_Task_Full +| Diagram: | TP_NetworkLayerLowerInterface_Rx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 14/11/2011 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 1 +| Numero de transicions: 0 +| Estats inicials: 0 +| +| Variables d'entrada: +| Variables de sortida: +| Variables d'entrada/sortida: +| Variables locals: +| +| ++++ Descripcio del proces implementat ++++ +| +| Task responsible of notifying the CAN Frame Rx type +to upper layers. +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task.h" + + +#include "TP_Functions.h" + +/*------------------------------ user code --------------------------------*/ + + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------ variables --------------------------------*/ + + + +/*------------------------------ funcions ---------------------------------*/ +void TP_NetworkLayerLowerInterface_RxInicialitza(UI_8 tp_hdl) +{ + /* -- no hi ha inicialitzacio a les funcions simples -- */ +} + +/**************************************************************************** +| Nom de la funcio: TP_NetworkLayerLowerInterface_Rx +|---------------------------------------------------------------------------- +| Funcionalitat: +| Diagrama d'un sol estat d'un model Edi. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| Sortides: + ****************************************************************************/ +void TP_NetworkLayerLowerInterface_Rx(UI_8 tp_hdl) +{ + t_flag_value received_frame = 0; + + /* Check that the RX notif routine has been configured */ + if (TPCheckPhyCfgData(tp_hdl) == TRUE) { + /* Get the RX flag from OsekCom */ + received_frame = ReadFlagRxSig(tp_data[tp_hdl].can_phy.sig_np_rx); + + if(received_frame == 0) + { + + } + else + { + + } + + + /* Case a new frame has been received */ + if (received_frame == COM_TRUE) { + TPProcessRxCanPhyFrame(tp_hdl); + } + else { + /* Do nothing */ + } + } + else { + /* Do nothing */ + } + +} /* TP_NetworkLayerLowerInterface_Rx */ + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c new file mode 100644 index 0000000..9621eaf --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_NetworkLayerLowerInterface_Tx.c @@ -0,0 +1,258 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_NetworkLayerLowerInterface_Tx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | Iso15765_2_Full +| System: | Iso15765_2_Task_Full +| Diagram: | TP_NetworkLayerLowerInterface_Tx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 14/11/2011 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 2 +| Numero de transicions: 4 +| Estats inicials: 1 +| +| Variables d'entrada: +| Variables de sortida: +| Variables d'entrada/sortida: +| Variables locals: +| +| ++++ Descripcio del proces implementat ++++ +| +| Task responsible of assuring TTmin time between 2 Tx Can +frames. +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task.h" + + +#include "TP_Functions.h" + +/*------------------------------ user code --------------------------------*/ + + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + + +/*------------------------------ variables --------------------------------*/ + + + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void TP_NetworkLayerLowerInterface_Tx0(UI_8 tp_hdl); +static void WaitingTxConfirmation(UI_8 tp_hdl); +static void ReadyToSend(UI_8 tp_hdl); +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats TP_NetworkLayerLowerInterface_Tx +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| estat_tp_networklayerlowerinterface_tx +| +****************************************************************************/ +void TP_NetworkLayerLowerInterface_TxInicialitza(UI_8 tp_hdl) +{ + /* Inicialitzacio de la variable d estat */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_0_TP_NETWORKLAYERLOWERINTERFACE_TX; + + /* Execucio del cicle inicial de la maquina d estats */ + TP_NetworkLayerLowerInterface_Tx(tp_hdl); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats TP_NetworkLayerLowerInterface_Tx. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_tp_networklayerlowerinterface_tx +| +| Sortides: +| estat_tp_networklayerlowerinterface_tx +| +****************************************************************************/ +void TP_NetworkLayerLowerInterface_Tx(UI_8 tp_hdl) +{ + //<> + /* Estudi per casos del estat actual */ + switch (tp_data[tp_hdl].state_can_phy_tx){ + case ESTAT_0_TP_NETWORKLAYERLOWERINTERFACE_TX: + TP_NetworkLayerLowerInterface_Tx0(tp_hdl); + //<tp_data[tp_hdl].state_can_phy_tx TO 002 REDAYTOSEND>> + break; + case ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_WAITINGTXCONFIRMATION: + WaitingTxConfirmation(tp_hdl); + break; + case ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND: + ReadyToSend(tp_hdl); + //<> + break; + default: + tp_data[tp_hdl].state_can_phy_tx = ESTAT_0_TP_NETWORKLAYERLOWERINTERFACE_TX; + break; + } + +} + + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces TP_NetworkLayerLowerInterface_Tx +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void TP_NetworkLayerLowerInterface_Tx0(UI_8 tp_hdl) +{ + if (TPCheckPhyCfgData(tp_hdl) == TRUE) { + /* Avaluem condicio de start del estat ReadyToSend */ + + /* Canviem l estat inicial */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND; + } + else { + /* No s ha activat cap condicio inicial: ens quedem a l estat actual */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_0_TP_NETWORKLAYERLOWERINTERFACE_TX; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat WaitingTxConfirmation. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_tp_networklayerlowerinterface_tx +| +| Sortides: +| estat_tp_networklayerlowerinterface_tx +| +****************************************************************************/ +static void WaitingTxConfirmation(UI_8 tp_hdl) +{ + /* -- codi de l estat actual -- */ + BOOL tx_confirmation, ax_timeout; + BOOL tx_requested = FALSE; + t_tp_tx_type tp_tx_type; + // uint8 index_1; + + /* Check if CAN transmission has been confirmed */ + tx_confirmation = TPCheckCanFrameConfirmation(tp_hdl); + /* Check if the TX timeout error has been confirmed */ + ax_timeout = TPCheckAxTimeout(tp_hdl); + //<>// + /* Case in which transmission is confirmed */ + if(tx_confirmation == TRUE) { + //<>/ + /* Notify the TX confirmation */ + TPNotifyCanFrmTx(tp_hdl, TP_TX_CONFIRMED); + /* Check if another TX is pending */ + tx_requested = TPCheckTxCanFrame(tp_hdl, &tp_tx_type); + } + else { + /* Do nothing */ + } + + if ((tx_confirmation == TRUE) && (tx_requested == FALSE)) { + /* Cas en que executem la transicio */ + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND; + } + else if ((ax_timeout == TRUE) && (tx_confirmation == FALSE)) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + TPNotifyCanFrmTx(tp_hdl, TP_TX_ERROR); + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND; + } + else if ((tx_confirmation == TRUE) && (tx_requested == TRUE)) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + TPProcessTxCanFrame(tp_hdl); + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_WAITINGTXCONFIRMATION; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_WAITINGTXCONFIRMATION; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat ReadyToSend. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_tp_networklayerlowerinterface_tx +| +| Sortides: +| estat_tp_networklayerlowerinterface_tx +| +****************************************************************************/ +static void ReadyToSend(UI_8 tp_hdl) +{ + /* -- codi de l estat actual -- */ + BOOL tx_requested; + t_tp_tx_type tp_tx_type; + // uint8 index_2; + + tx_requested = TPCheckTxCanFrame(tp_hdl, &tp_tx_type); + + if (tx_requested == TRUE) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + TPProcessTxCanFrame(tp_hdl); + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_WAITINGTXCONFIRMATION; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_can_phy_tx = ESTAT_TP_NETWORKLAYERLOWERINTERFACE_TX_READYTOSEND; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c new file mode 100644 index 0000000..2b8c03d --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx.c @@ -0,0 +1,53 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | Iso15765_2_Rx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | Iso15765_2 +| System: | Iso15765_2_Task +| Diagram: | Iso15765_2_Rx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 18/5/2009 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 1 +| Numero de transicions: 3 +| Estats inicials: 1 +| +| Variables d'entrada: +| NP_CAN_RX_NOTIF (BOOL) +| NP_CAN_RX_SIZE (UI_8) +| NP_CAN_RX_DATA (UI_8) +| Variables de sortida: +| tp_frm (t_tp_frm) +| Variables d'entrada/sortida: +| Variables locals: +| timer_n_cr (t_clock) +| +| ++++ Descripcio del proces implementat ++++ +| +| Maquina 0x1 + ISO 15765: CAN -> KWP +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" + +#ifdef TP_MODE_FULL + //#include "TP_Rx_Full.c" +#else + #include "TP_Rx_Lite.c" +#endif + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c new file mode 100644 index 0000000..ae1110a --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_RxFun.c @@ -0,0 +1,95 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_RxFun.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | TP_Full +| System: | TP_Task_Full +| Diagram: | TP_RxFun +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 28/2/2011 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 1 +| Numero de transicions: 0 +| Estats inicials: 0 +| +| Variables d'entrada: +| Variables de sortida: +| Variables d'entrada/sortida: +| Variables locals: +| +| ++++ Descripcio del proces implementat ++++ +| +| +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task.h" + + +/*------------------------------ user code --------------------------------*/ + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "TP_Functions.h" + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------ variables --------------------------------*/ + + + +/*------------------------------ funcions ---------------------------------*/ +void TP_RxFunInicialitza(UI_8 tp_hdl) +{ + /* -- no hi ha inicialitzacio a les funcions simples -- */ +} + +/**************************************************************************** +| Nom de la funcio: TP_RxFun +|---------------------------------------------------------------------------- +| Funcionalitat: +| Diagrama d'un sol estat d'un model Edi. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| Sortides: + ****************************************************************************/ +void TP_RxFun(UI_8 tp_hdl) +{ + t_flag_value received_frame; + + /* Check that the functional RX notif routine has been configured */ + if(TPCheckFunCfgData(tp_hdl) == TRUE) { + /* Get the RX flag from OsekCom */ + received_frame = ReadFlagRxSig(tp_data[tp_hdl].can_fun.sig_np_rx); + if (received_frame == COM_TRUE) { + TPReadFunFrm(tp_hdl); + } + else { + /* Do nothing */ + } + } + else { + /* Do nothing */ + } + +} /* TP_RxFun */ + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c new file mode 100644 index 0000000..4acf1d7 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Full.c @@ -0,0 +1,432 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_Rx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | TP_FULL +| System: | TP_Task +| Diagram: | TP_Rx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 18/10/2010 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 3 +| Numero de transicions: 14 +| Estats inicials: 1 +| +| Variables d'entrada: +| NP_CAN_RX_NOTIF (BOOL) +| NP_CAN_RX_SIZE (UI_8) +| NP_CAN_RX_DATA (UI_8) +| Variables de sortida: +| tp_frm (t_tp_frm) +| Variables d'entrada/sortida: +| Variables locals: +| timer_n_cr (t_clock) +| num_frames_before_fc (UI_16) +| timer_n_ar (t_clock) +| +| ++++ Descripcio del proces implementat ++++ +| +| Maquina 0x1 + ISO 15765: CAN -> KWP +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task.h" + + +/*------------------------------ user code --------------------------------*/ + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "TP_Functions.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" + +/*-------------------------------- macros ---------------------------------*/ + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +/*------------------------------ variables --------------------------------*/ + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void TP_Rx_Full0(UI_8 tp_hdl); +static void Inicio(UI_8 tp_hdl); +static void RxCF(UI_8 tp_hdl); +static void ConfirmaFC(UI_8 tp_hdl); +//<< +//void TP_Rx_FullInicialitza(UI_8 iso2_hdl); +//void TP_Rx_Full(UI_8 iso2_hdl); +//>> + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats TP_Rx +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| +| tp_frm +****************************************************************************/ +#if 1 +void TP_Rx_FullInicialitza(UI_8 tp_hdl) +{ + /* Inicialitzacio de la variable d estat */ + tp_data[tp_hdl].state_rx = ESTAT_0_TP_RX_FULL; + + /* Execucio del cicle inicial de la maquina d estats */ + TP_Rx_Full(tp_hdl); +} +#endif + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats TP_Rx. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| NP_CAN_RX_NOTIF +| NP_CAN_RX_SIZE +| NP_CAN_RX_DATA +| Sortides: +| +| tp_frm +****************************************************************************/ +#if 1 +void TP_Rx_Full(UI_8 tp_hdl) +{ + /* Estudi per casos del estat actual */ + switch (tp_data[tp_hdl].state_rx){ + case ESTAT_0_TP_RX_FULL: + TP_Rx_Full0(tp_hdl); + break; + case ESTAT_TP_RX_FULL_INICIO: + Inicio(tp_hdl); + break; + case ESTAT_TP_RX_FULL_RXCF: + RxCF(tp_hdl); + break; + case ESTAT_TP_RX_FULL_CONFIRMAFC: + ConfirmaFC(tp_hdl); + break; + default: + tp_data[tp_hdl].state_rx = ESTAT_0_TP_RX_FULL; + break; + } + + /* Increment del temps de cicle als timers */ + if (tp_data[tp_hdl].timers.n_cr < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_cr += TP_TASK_TICKS; + } +} +#endif +#ifdef ENABLE_INCREMENT_EXTERNAL_TIMERS +void TPRxIncrTimers(UI_8 tp_hdl, UI_16 ticks) +{ + if (tp_data[tp_hdl].timers.n_cr < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_cr += ticks; + } +} +#endif + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces TP_Rx +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void TP_Rx_Full0(UI_8 tp_hdl) +{ + /* -- reset dels timers t_clock -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + if (TPCheckPhyCfgData(tp_hdl) == TRUE) { + /* Canviem l estat inicial */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else { + /* No s ha activat cap condicio inicial: ens quedem a l estat actual */ + tp_data[tp_hdl].state_rx = ESTAT_0_TP_RX_FULL; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Inicio. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| NP_CAN_RX_NOTIF +| NP_CAN_RX_SIZE +| NP_CAN_RX_DATA +| Sortides: +| +| tp_frm +****************************************************************************/ +static void Inicio(UI_8 tp_hdl) +{ + if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_SF) && + ((tp_frm[tp_hdl].sts_rx == TP_FRM_RX_IDLE) || (tp_frm[tp_hdl].sts_rx == TP_FRM_RX_ERR_NOTIF))) { + /* Cas en que executem la transicio RxSF */ + + /* -- action de la transicio -- */ + if(tp_frm[tp_hdl].iso15765_2_block_rx == FALSE ) { + TPReadSF(tp_hdl); + } + else { + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + } + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_FF) && (tp_frm[tp_hdl].iso15765_2_block_rx == TRUE)) { + /* Cas en que executem la transicio RxFFTxFCBlocked */ + + /* -- action de la transicio -- */ + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_FF) && (tp_frm[tp_hdl].iso15765_2_block_rx == FALSE) && ((tp_frm[tp_hdl].sts_rx == TP_FRM_RX_IDLE) || (tp_frm[tp_hdl].sts_rx == TP_FRM_RX_ERR_NOTIF))) { + /* Cas en que executem la transicio RxFFTxFCNotBlocked */ + + /* -- action de la transicio -- */ + TPReadFFSendFC(tp_hdl); + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_CONFIRMAFC; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat RxCF. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| NP_CAN_RX_NOTIF +| NP_CAN_RX_SIZE +| NP_CAN_RX_DATA +| Sortides: +| +| tp_frm +****************************************************************************/ +static void RxCF(UI_8 tp_hdl) +{ + if ((tp_data[tp_hdl].timers.n_cr > TIMER_MS_TO_TICKS(tp_data[tp_hdl].cfg.n_cr_max) ) && (tp_frm[tp_hdl].sts_rx != TP_FRM_RX_FINISHED)) { + /* Cas en que executem la transicio TimeOutSigSegmento */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if (tp_frm[tp_hdl].sts_rx == TP_FRM_RX_ERR_FINISHED) { + /* Cas en que executem la transicio ErrorCF */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tp_frm[tp_hdl].sts_rx != TP_FRM_RX_FINISHED) && ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_SF) || (tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_FF))) { + /* Cas en que executem la transicio UnexpectedFForSF */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tp_frm[tp_hdl].sts_rx == TP_FRM_RX_FINISHED)) { + /* Cas en que executem la transicio RxAcabada */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_CF) && (tp_data[tp_hdl].cfg.block_size > (UI_8)0) && (tp_data[tp_hdl].rx_st.num_frames_before_fc >= (tp_data[tp_hdl].cfg.block_size - (UI_8)1)) && (tp_data[tp_hdl].rx_st.byte_actual_rx < (tp_frm[tp_hdl].size_rx - CF_DATA_LEN))) { + /* Cas en que executem la transicio TPSendFC */ + + /* -- action de la transicio -- */ + TPReadCFSendFC(tp_hdl); + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_CONFIRMAFC; + } + else if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_CF) && ((tp_data[tp_hdl].cfg.block_size == (UI_8)0) || (tp_data[tp_hdl].rx_st.num_frames_before_fc < (tp_data[tp_hdl].cfg.block_size - (UI_8)1)) || (tp_data[tp_hdl].rx_st.byte_actual_rx >= (tp_frm[tp_hdl].size_rx - CF_DATA_LEN)))) { + /* Cas en que executem la transicio ReceivedCFNoFC */ + + /* -- action de la transicio -- */ + TPReadCF(tp_hdl); + tp_data[tp_hdl].rx_st.num_frames_before_fc++; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_RXCF; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_RXCF; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat ConfirmaFC. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| NP_CAN_RX_NOTIF +| NP_CAN_RX_SIZE +| NP_CAN_RX_DATA +| Sortides: +| +| tp_frm +****************************************************************************/ +static void ConfirmaFC(UI_8 tp_hdl) +{ + BOOL tx_confirmed; + + /* Check if the transmission has been confirmed */ + tx_confirmed = TPCheckTxConfirmed(tp_hdl, tp_data[tp_hdl].tx_st.frame_tx_fc_sts); + + if ((tx_confirmed == TRUE) && (tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_NO_FRM)) { + /* Cas en que executem la transicio ConfirmatFCNoReceivedCF */ + + /* -- action de la transicio -- */ + tp_data[tp_hdl].rx_st.num_frames_before_fc = (UI_16)0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_RXCF; + } + else if (tp_data[tp_hdl].tx_st.frame_tx_fc_sts == TP_TX_ERROR) { + + /* Cas en que executem la transicio TimeOutAr */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else if ((tx_confirmed == TRUE) && (tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_CF) && (tp_data[tp_hdl].cfg.block_size == (UI_8)1) && (tp_data[tp_hdl].rx_st.byte_actual_rx < (tp_frm[tp_hdl].size_rx - CF_DATA_LEN))) { + /* Cas en que executem la transicio ConfirmatFCReceivedCFSendFC */ + + /* -- action de la transicio -- */ + TPReadCFSendFC(tp_hdl); + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_CONFIRMAFC; + } + else if ((tx_confirmed == TRUE) && (tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_CF) && ((tp_data[tp_hdl].cfg.block_size != (UI_8)1) || (tp_data[tp_hdl].rx_st.byte_actual_rx >= (tp_frm[tp_hdl].size_rx - CF_DATA_LEN)))) { + /* Cas en que executem la transicio ConfirmatFCReceivedCFNotSendFC */ + + /* -- action de la transicio -- */ + TPReadCF(tp_hdl); + tp_data[tp_hdl].rx_st.num_frames_before_fc = (UI_16)1; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_RXCF; + } + else if ((tp_frm[tp_hdl].sts_rx != TP_FRM_RX_FINISHED) && ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_SF) || (tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_FF))) { + /* Cas en que executem la transicio UnexpectedSForFF */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_rx = TP_FRM_RX_ERR_NOTIF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_cr = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_INICIO; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_rx = ESTAT_TP_RX_FULL_CONFIRMAFC; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c new file mode 100644 index 0000000..ef6f7ad --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Rx_Lite.c @@ -0,0 +1,94 @@ + +/************************* FICOSA INTERNATIONAL **************************** +| File: | TP_Rx_Lite.c +|----------------------------------------------------------------------------- +| Author: | Abel Casas +|----------------------------------------------------------------------------- +| Project: | TP_Lite +| System: | TP_Task_Lite +| Diagram: | TP_Rx_Lite +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 10/1/2012 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 1 +| Numero de transicions: 0 +| Estats inicials: 0 +| +| Variables d'entrada: +| Variables de sortida: +| tp_frm (t_tp_frm) +| Variables d'entrada/sortida: +| Variables locals: +| +| ++++ Descripcio del proces implementat ++++ +| +| Task responsible of controlling all the flow of a reception of +a transport protocol frame. This task is responsible of checking +the correct reception of SF and sending the FC +when is needed according to the configuration of the +ISO15765_2. Finally this task will notify to the application when +a new complete RX frame is available. +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task_Lite.h" + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "TP_Functions.h" +#include "TP.h" + +/*-------------------------------- defines ---------------------------------*/ + + + +/*------------------------------ variables --------------------------------*/ + + + +/*------------------------------ user code --------------------------------*/ + + +/*------------------------------ functions ---------------------------------*/ +void TP_Rx_LiteInicialitza(UI_8 tp_hdl) +{ + /* -- no hi ha inicialitzacio a les funcions simples -- */ +} + +/**************************************************************************** +| Nom de la funcio: TP_Rx_Lite +|---------------------------------------------------------------------------- +| Funcionalitat: +| Diagrama d'un sol estat d'un model Edi. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| Sortides: tp_frm + ****************************************************************************/ +void TP_Rx_Lite(UI_8 tp_hdl) +{ + /* Check if a new SF has been received */ + if ((tp_data[tp_hdl].rx_st.frame_rx_type == TP_RX_SF) && + ((tp_frm[tp_hdl].sts_rx == TP_FRM_RX_IDLE) || (tp_frm[tp_hdl].sts_rx == TP_FRM_RX_ERR_NOTIF)) && + (tp_frm[tp_hdl].iso15765_2_block_rx == FALSE)) { + TPReadSF(tp_hdl); + } + else { + /* Reset the frame reception type */ + tp_data[tp_hdl].rx_st.frame_rx_type = TP_RX_NO_FRM; + } + +} /* TP_Rx_Lite */ + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task.h b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task.h new file mode 100644 index 0000000..6d1f8bf --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task.h @@ -0,0 +1,61 @@ +/*************** COPYRIGHT (c) 2002-2007 FICOSA INTERNATIONAL ************** +| Language: | MISRA C +| Controller: | Generic +| Spec. Document: | ISO15765-2-E.pdf +|-----------------|------------------------------------------------------------ +| Project: | ISO15765-2 +| Reference: | +|------------------------------------------------------------------------------ +| Date - Cod. - Rev. - App. - Description +| 12/09/02 AM Implementation of the kwp2000 for PSA. +| 19/08/04 DT Split ISO15765_2 protocol from the KWP2000 +| because they are different modules. +| 24/04/09 DC Modification to guarantee the requirements SR1431, +| SR1438, SR1681. +| 15/12/10 AC Converted ISO15765_2 protocol to multi-instance. +| 13/11/11 AC Converted ISO15765_2 to full-duplex +| 09/01/12 AC Changed file, routines and variable naming to +| make it a standard component improving his +| comprehension and having a similar naming style +| with MPDT. +|------------------------------------------------------------------------------ +| DESCRIPTION: +| User interface for the transport protocol ISO15765_2 on CAN. +| ISO15765_2 protocol is a transport protocol that permits the sending and +| reception of frames until 4096 bytes on a network protocol with frames of +| lower size. The original frame is segemented and sent with flow control +| data that allows to the reception node to mount again the original frame. +| GENERAL CONSIDERATIONS +| - This implementation allows full duplex communications. +| - This implementation allows for each instance a communication channel +| with physical address in which both transmission and receptions could +| be done and a funcional address for only receptions. +| - The functional address channel only supports frames with less than +| 8 bytes of data. +| - This header must be included by the application as it contains the +| definitions of the tasks to send and receive transport protocol frames. +******************************************************************************/ +#ifndef _TP_TASK_H +#define _TP_TASK_H + +/*----------------------------- INCLUDES ---------------------------------*/ + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" + +#ifdef TP_MODE_FULL + #include "TP_Task_Full.h" +#else + #include "TP_Task_Lite.h" +#endif + +/*----------------------------- DEFINES ----------------------------------*/ + +/*-------------------------- DATA TYEPS ----------------------------------*/ + +/*--------------------------- GLOBAL VARIABLES ---------------------------*/ + +/*--------------------------- ROUTINE PROTOTYPES ------------------------*/ + +/********************************** FI **************************************/ + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Full.h b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Full.h new file mode 100644 index 0000000..34f340a --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Full.h @@ -0,0 +1,57 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_Task_Lite.h +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | TP_Lite +| System: | TP_Task_Lite +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeH Version: | 1.01 +| Codification Date: | 28/2/2011 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un sistema Edi +| +| +| +************************** FI DE LA CAPCALERA ****************************/ +#ifndef _TPTASKFULL_H +#define _TPTASKFULL_H +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" + +/*----------------------------- user includes -----------------------------*/ + + +/*---------------- estructura de les variables del sistema ----------------*/ + + +/*------------------------ capcaleres de funcions -------------------------*/ + + +void TP_Rx_FullInicialitza(UI_8 iso2_hdl); +void TP_Rx_Full(UI_8 iso2_hdl); + +void TP_Tx_FullInicialitza(UI_8 iso2_hdl); +void TP_Tx_Full(UI_8 iso2_hdl); + +void TP_RxFunInicialitza(UI_8 iso2_hdl); +void TP_RxFun(UI_8 iso2_hdl); + +void TP_NetworkLayerLowerInterface_TxInicialitza(UI_8 iso2_hdl); +void TP_NetworkLayerLowerInterface_Tx(UI_8 iso2_hdl); + +void TP_NetworkLayerLowerInterface_RxInicialitza(UI_8 iso2_hdl); +void TP_NetworkLayerLowerInterface_Rx(UI_8 iso2_hdl); + +/*------------------------ function-like macros ----------------------------*/ + + + + +/********************************** FI **************************************/ + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Lite.h b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Lite.h new file mode 100644 index 0000000..ed72553 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Task_Lite.h @@ -0,0 +1,56 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_Task_Lite.h +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | TP_Lite +| System: | TP_Task_Lite +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeH Version: | 1.01 +| Codification Date: | 28/2/2011 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un sistema Edi +| +| +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" + +/*----------------------------- user includes -----------------------------*/ + + +/*---------------- estructura de les variables del sistema ----------------*/ + + +/*------------------------ capcaleres de funcions -------------------------*/ + + +void TP_Rx_LiteInicialitza(UI_8 iso2_hdl); +void TP_Rx_Lite(UI_8 iso2_hdl); + +void TP_Tx_LiteInicialitza(UI_8 iso2_hdl); +void TP_Tx_Lite(UI_8 iso2_hdl); + +void TP_RxFunInicialitza(UI_8 iso2_hdl); +void TP_RxFun(UI_8 iso2_hdl); + +void TP_NetworkLayerLowerInterface_TxInicialitza(UI_8 iso2_hdl); +void TP_NetworkLayerLowerInterface_Tx(UI_8 iso2_hdl); + +void TP_NetworkLayerLowerInterface_RxInicialitza(UI_8 iso2_hdl); +void TP_NetworkLayerLowerInterface_Rx(UI_8 iso2_hdl); + + +/*------------------------ function-like macros ----------------------------*/ + + + + +/********************************** FI **************************************/ + diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c new file mode 100644 index 0000000..5d632ce --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx.c @@ -0,0 +1,55 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | Iso15765_2_Tx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | Iso15765_2 +| System: | Iso15765_2_Task +| Diagram: | Iso15765_2_Tx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 18/5/2009 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 1 +| Numero de transicions: 1 +| Estats inicials: 1 +| +| Variables d'entrada: +| tp_frm (t_tp_frm) +| Variables de sortida: +| NP_CAN_TX_DATA (UI_8) +| NP_CAN_TX_SIZE (UI_8) +| Variables d'entrada/sortida: +| Variables locals: +| block_size (UI_8) +| fc_data (t_fc_data) +| timer_n_bs (t_clock) +| timer_n_cs (t_clock) +| fc_rx (BOOL) +| +| ++++ Descripcio del proces implementat ++++ +| +| Maquina 0x2 + ISO 15765: KWP -> CAN +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" + +#ifdef TP_MODE_FULL + //#include "TP_Tx_Full.c" +#else + #include "TP_Tx_Lite.c" +#endif + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c new file mode 100644 index 0000000..24790dc --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Full.c @@ -0,0 +1,442 @@ + +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | TP_Tx.c +|----------------------------------------------------------------------------- +| Author: | Author +|----------------------------------------------------------------------------- +| Project: | TP +| System: | TP_Task +| Diagram: | TP_Tx +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 18/10/2010 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 3 +| Numero de transicions: 12 +| Estats inicials: 1 +| +| Variables d'entrada: +| tp_frm (t_tp_frm) +| fc_data (t_fc_data) +| Variables de sortida: +| NP_CAN_TX_DATA (UI_8) +| NP_CAN_TX_SIZE (UI_8) +| Variables d'entrada/sortida: +| Variables locals: +| block_size (UI_8) +| timer_n_bs (t_clock) +| timer_n_cs (t_clock) +| timer_n_as (t_clock) +| ack_tx (BOOL) +| +| ++++ Descripcio del proces implementat ++++ +| +| Maquina 0x2 + ISO 15765: KWP -> CAN +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task.h" +#include "TP.h" + + +/*------------------------------ user code --------------------------------*/ + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "TP_Functions.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +/*------------------------------ variables --------------------------------*/ + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void TP_Tx_Full0(UI_8 tp_hdl); +static void Inici(UI_8 tp_hdl); +static void EsperaFC(UI_8 tp_hdl); +static void ConfirmaTx(UI_8 tp_hdl); +void TP_Tx_Full(UI_8 tp_hdl); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats TP_Tx +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| +| NP_CAN_TX_DATA +| NP_CAN_TX_SIZE +****************************************************************************/ +#if 1 +void TP_Tx_FullInicialitza(UI_8 tp_hdl) +{ + /* Inicialitzacio de la variable d estat */ + tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_FULL; + + /* Execucio del cicle inicial de la maquina d estats */ + TP_Tx_Full(tp_hdl); +} +#endif + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats TP_Tx. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| tp_frm +| fc_data +| Sortides: +| +| NP_CAN_TX_DATA +| NP_CAN_TX_SIZE +****************************************************************************/ +void TP_Tx_Full(UI_8 tp_hdl) +{ + /* Estudi per casos del estat actual */ + switch (tp_data[tp_hdl].state_tx){ + case ESTAT_0_TP_TX_FULL: + TP_Tx_Full0(tp_hdl); + break; + case ESTAT_TP_TX_FULL_INICI: + Inici(tp_hdl); + break; + case ESTAT_TP_TX_FULL_ESPERAFC: + EsperaFC(tp_hdl); + break; + case ESTAT_TP_TX_FULL_CONFIRMATX: + ConfirmaTx(tp_hdl); + break; + default: + tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_FULL; + break; + } + + /* Increment del temps de cicle als timers */ + if (tp_data[tp_hdl].timers.n_bs < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_bs += TP_TASK_TICKS; + } + if (tp_data[tp_hdl].timers.n_cs < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_cs += TP_TASK_TICKS; + } +} + +#ifdef ENABLE_INCREMENT_EXTERNAL_TIMERS +void TPTxIncrTimers(UI_8 tp_hdl, UI_16 ticks) +{ + if (tp_data[tp_hdl].timers.n_bs < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_bs += ticks; + } + if (tp_data[tp_hdl].timers.n_cs < MAX_COMPTADOR_TEMPS) { + tp_data[tp_hdl].timers.n_cs += ticks; + } +} +#endif + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces TP_Tx +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void TP_Tx_Full0(UI_8 tp_hdl) +{ + /* -- reset dels timers t_clock -- */ + tp_data[tp_hdl].timers.n_bs= (t_clock)0; + tp_data[tp_hdl].timers.n_cs= (t_clock)0; + + if (TPCheckPhyCfgData(tp_hdl) == TRUE) { + /* Canviem l estat inicial */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else { + /* No s ha activat cap condicio inicial: ens quedem a l estat actual */ + tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_FULL; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Inici. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| tp_frm +| fc_data +| Sortides: +| +| NP_CAN_TX_DATA +| NP_CAN_TX_SIZE +****************************************************************************/ +static void Inici(UI_8 tp_hdl) +{ + if ((tp_frm[tp_hdl].sts_tx == TP_FRM_TX_REQ) && (tp_frm[tp_hdl].size_tx <= NP_SF_MAX_SIZE) && (tp_frm[tp_hdl].iso15765_2_block_tx == FALSE)) { + /* Cas en que executem la transicio TxSF */ + + /* -- action de la transicio -- */ + TPSendSF(tp_hdl); + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_CONFIRMATX; + } + else if ((tp_frm[tp_hdl].sts_tx == TP_FRM_TX_REQ) && (tp_frm[tp_hdl].size_tx > NP_SF_MAX_SIZE) && (tp_frm[tp_hdl].iso15765_2_block_tx == FALSE)) { + /* Cas en que executem la transicio TxFF */ + + /* -- action de la transicio -- */ + TPSendFF(tp_hdl); + tp_data[tp_hdl].fc_data.first_fc = TRUE; + tp_data[tp_hdl].fc_data.block_size_cnt = 0xFF; + tp_data[tp_hdl].fc_data.rx_bs = 0xFF; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_CONFIRMATX; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat EsperaFC. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| tp_frm +| fc_data +| Sortides: +| +| NP_CAN_TX_DATA +| NP_CAN_TX_SIZE +****************************************************************************/ +static void EsperaFC(UI_8 tp_hdl) +{ + /* -- codi de l estat actual -- */ + if (tp_data[tp_hdl].rx_st.frame_fc_type == TP_FC) { + TPReadFCSendCF(tp_hdl); + } + else { + /* Do nothing */ + } + + if ((tp_data[tp_hdl].fc_data.fc_rx == TRUE) && (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_WT) && (tp_data[tp_hdl].fc_data.num_fc_wait < tp_data[tp_hdl].cfg.n_wftmax)) { + /* Cas en que executem la transicio ArribaFCWaitAccepted */ + + /* -- action de la transicio -- */ + /* Reset the FC reception flag */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + /* Increment number of FC wait received */ + tp_data[tp_hdl].fc_data.num_fc_wait++; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_ESPERAFC; + } + else if ((tp_data[tp_hdl].fc_data.fc_rx == TRUE) && (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_WT) && (tp_data[tp_hdl].fc_data.num_fc_wait >= tp_data[tp_hdl].cfg.n_wftmax)) { + /* Cas en que executem la transicio ArribaFCWaitRejected */ + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_ERR_NOTIF; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + tp_data[tp_hdl].fc_data.num_fc_wait = 0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else if ((tp_data[tp_hdl].fc_data.fc_rx == FALSE) && (tp_data[tp_hdl].timers.n_bs >= TIMER_MS_TO_TICKS(tp_data[tp_hdl].cfg.n_bs_max) )) { + /* Cas en que executem la transicio TimeOutFC */ + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_ERR_NOTIF; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + tp_data[tp_hdl].fc_data.num_fc_wait = 0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else if ((tp_data[tp_hdl].fc_data.fc_rx == TRUE) && (tp_data[tp_hdl].fc_data.flow_status != TP_FLOW_STS_WT) && (tp_data[tp_hdl].fc_data.flow_status != TP_FLOW_STS_CTS)) { + /* Cas en que executem la transicio ArribaFCError */ + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_ERR_NOTIF; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + tp_data[tp_hdl].fc_data.num_fc_wait = 0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else if ((tp_data[tp_hdl].fc_data.fc_rx == TRUE) && (tp_data[tp_hdl].fc_data.flow_status == TP_FLOW_STS_CTS)) { + /* Cas en que executem la transicio TxPrimerCF */ + + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.block_size_cnt = (UI_8)1; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_CONFIRMATX; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_ESPERAFC; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat ConfirmaTx. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| +| tp_frm +| fc_data +| Sortides: +| +| NP_CAN_TX_DATA +| NP_CAN_TX_SIZE +****************************************************************************/ +static void ConfirmaTx(UI_8 tp_hdl) +{ + BOOL tx_confirmed, end_frame; + + /* Check if the transmission has been confirmed */ + tx_confirmed = TPCheckTxConfirmed(tp_hdl, tp_data[tp_hdl].tx_st.frame_tx_sts); + + /* -- codi de l estat actual -- */ + if (tx_confirmed == TRUE) { + tp_data[tp_hdl].tx_st.ack_tx = TRUE; + } + else { + tp_data[tp_hdl].tx_st.ack_tx = FALSE; + tp_data[tp_hdl].timers.n_cs = 0; + } + + /* Check if the TX is finished */ + end_frame = TPTestEndFrame(tp_hdl); + + if ((tp_data[tp_hdl].tx_st.ack_tx == FALSE) && (tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_ERROR)) { + /* Cas en que executem la transicio TimeOutTxCF */ + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_ERR_NOTIF; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + tp_data[tp_hdl].fc_data.num_fc_wait = 0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else if ((tp_data[tp_hdl].tx_st.ack_tx == TRUE) && (end_frame == TRUE)) { + /* Cas en que executem la transicio TxAcabada */ + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_IDLE; + tp_data[tp_hdl].fc_data.num_fc_wait = 0; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_INICI; + } + else if ((tp_data[tp_hdl].tx_st.ack_tx == TRUE) && (end_frame == FALSE) && (tp_data[tp_hdl].fc_data.rx_bs > (UI_8)0) && (tp_data[tp_hdl].fc_data.block_size_cnt >= tp_data[tp_hdl].fc_data.rx_bs)) { + /* Cas en que executem la transicio EndBlockSize */ + + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.fc_rx = FALSE; + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_ESPERAFC; + } + else if ((tp_data[tp_hdl].tx_st.ack_tx == TRUE) && (end_frame == FALSE) && (tp_data[tp_hdl].timers.n_cs >= TIMER_MS_TO_TIME_RESTRICTIVE((t_clock)(tp_data[tp_hdl].fc_data.stmin))) && ((tp_data[tp_hdl].fc_data.block_size_cnt < tp_data[tp_hdl].fc_data.rx_bs) || (tp_data[tp_hdl].fc_data.rx_bs == 0))) { + /* Cas en que executem la transicio TxSeguentCF */ + + /* -- action de la transicio -- */ + tp_data[tp_hdl].fc_data.block_size_cnt++; + TPSendCF(tp_hdl); + + /* -- reset del timer -- */ + tp_data[tp_hdl].timers.n_bs = (t_clock)0; + tp_data[tp_hdl].timers.n_cs = (t_clock)0; + + /* -- canviem l estat -- */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_CONFIRMATX; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + tp_data[tp_hdl].state_tx = ESTAT_TP_TX_FULL_CONFIRMATX; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c new file mode 100644 index 0000000..fe896e3 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/TP_Tx_Lite.c @@ -0,0 +1,249 @@ + +/************************* FICOSA INTERNATIONAL **************************** +| File: | TP_Tx_Lite.c +|----------------------------------------------------------------------------- +| Author: | Abel Casas +|----------------------------------------------------------------------------- +| Project: | TP_Lite +| System: | TP_Task_Lite +| Diagram: | TP_Tx_Lite +| Model Version: | 1.0 +| Model Date: | Thursday, February 26, 2009 - 14:47:56 +|----------------------------------------------------------------------------- +| CodeC Version: | 1.0 +| Codification Date: | 10/1/2012 +|----------------------------------------------------------------------------- +| Description: +| Codificacio automatica d'un diagrama d'estats +| +| ++++ Informacio del Diagrama d'Estats +++++ +| +| Numero d'estats: 2 +| Numero de transicions: 3 +| Estats inicials: 1 +| +| Variables d'entrada: +| Variables de sortida: +| tp_frm (t_tp_frm) +| Variables d'entrada/sortida: +| Variables locals: +| +| ++++ Descripcio del proces implementat ++++ +| +| Task responsible of controlling all the flow of a transmission of +a transport protocol frame. This task is responsible of sending +correctly SF. +| +************************** FI DE LA CAPCALERA ****************************/ + +/*------------------------------- includes --------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "TP_Task_Lite.h" + +#include "DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h" +#include "TP_Functions.h" + +/*-------------------------------- defines ---------------------------------*/ + +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + + +/*------------------------------ variables --------------------------------*/ + + +/*------------------------------ user code --------------------------------*/ + + + +/*------------------------- capcaleres de funcions ------------------------*/ + +//static void TP_Tx_Lite0(UI_8 tp_hdl); +//static void Init(UI_8 tp_hdl); +//static void ConfirmTx(UI_8 tp_hdl); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats TP_Tx_Lite +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| tp_data[tp_hdl].state_tx +| +| tp_frm +****************************************************************************/ +void TP_Tx_LiteInicialitza(UI_8 tp_hdl) +{ + /* Inicialitzacio de la variable d estat */ +// tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_LITE; + + /* Execucio del cicle inicial de la maquina d estats */ + //TP_Tx_Lite(tp_hdl); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats TP_Tx_Lite. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| tp_data[tp_hdl].state_tx +| +| Sortides: +| tp_data[tp_hdl].state_tx +| +| tp_frm +****************************************************************************/ + +void TP_Tx_Lite(UI_8 tp_hdl) +{ +#if 0 + /* Estudi per casos del estat actual */ + switch (tp_data[tp_hdl].state_tx){ + case ESTAT_0_TP_TX_LITE: + TP_Tx_Lite0(tp_hdl); + break; + case ESTAT_TP_TX_LITE_INIT: + Init(tp_hdl); + break; + case ESTAT_TP_TX_LITE_CONFIRMTX: + ConfirmTx(tp_hdl); + break; + default: + tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_LITE; + break; + } + #endif + +} + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces TP_Tx_Lite +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +#if 0 +static void TP_Tx_Lite0(UI_8 tp_hdl) +{ + + if (TPCheckPhyCfgData(tp_hdl) == TRUE) { + /* Avaluem condicio de start del estat Init */ + + /* Canviem l estat inicial */ + // tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_INIT; + } + else { + /* No s ha activat cap condicio inicial: ens quedem a l estat actual */ + // tp_data[tp_hdl].state_tx = ESTAT_0_TP_TX_LITE; + } +} +#endif +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Init. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| tp_data[tp_hdl].state_tx +| +| Sortides: +| tp_data[tp_hdl].state_tx +| +| tp_frm +****************************************************************************/ +#if 0 +static void Init(UI_8 tp_hdl) +{ + if ((tp_frm[tp_hdl].sts_tx == TP_FRM_TX_REQ) && (tp_frm[tp_hdl].size_tx <= NP_SF_MAX_SIZE) && (tp_frm[tp_hdl].iso15765_2_block_tx == FALSE)) { + /* Cas en que executem la transicio TxSF */ + + /* -- action de la transicio -- */ + TPSendSF(tp_hdl); + + /* -- canviem l estat -- */ + // tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_CONFIRMTX; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + // tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_INIT; + } +} +#endif +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat ConfirmTx. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| tp_data[tp_hdl].state_tx +| +| Sortides: +| tp_data[tp_hdl].state_tx +| +| tp_frm +****************************************************************************/ +#if 0 +static void ConfirmTx(UI_8 tp_hdl) +{ + /* -- codi de l estat actual -- */ + BOOL tx_confirmed, end_frame; + + /* Check if the transmission has been confirmed */ + tx_confirmed = TPCheckTxConfirmed(tp_hdl, tp_data[tp_hdl].tx_st.frame_tx_sts); + + /* -- codi de l estat actual -- */ + if (tx_confirmed == TRUE) { + tp_data[tp_hdl].tx_st.ack_tx = TRUE; + } + else { + tp_data[tp_hdl].tx_st.ack_tx = FALSE; + } + + /* Check if the TX is finished */ + end_frame = TPTestEndFrame(tp_hdl); + + + if ((tp_data[tp_hdl].tx_st.ack_tx == FALSE) && (tp_data[tp_hdl].tx_st.frame_tx_sts == TP_TX_ERROR)) { + /* Cas en que executem la transicio TimeOutTxCF */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_ERR_NOTIF; + tp_frm[tp_hdl].iso15765_2_block_rx = FALSE; + + /* -- canviem l estat -- */ + // tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_INIT; + } + else if ((tp_data[tp_hdl].tx_st.ack_tx == TRUE) && (end_frame == TRUE)) { + /* Cas en que executem la transicio TxFinished */ + + /* -- action de la transicio -- */ + tp_frm[tp_hdl].sts_tx = TP_FRM_TX_IDLE; + + /* -- canviem l estat -- */ + //tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_INIT; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + // tp_data[tp_hdl].state_tx = ESTAT_TP_TX_LITE_CONFIRMTX; + } +} +#endif + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_2/wscript b/firmware/src/DiagnosticR/Comp_ISO_15765_2/wscript new file mode 100644 index 0000000..c022991 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_2/wscript @@ -0,0 +1,23 @@ +#!python -u +#------------------------------------------------------------------------------- +# Purpose: Waf build script. +# +# Author: F59AMD0 +# +# Copyright: (c) FICOSA 2015 +# Licence: +#------------------------------------------------------------------------------- + +def build(bld): + bld.env.RINCLUDES += [ + "." , + ] + + bld.env.RSOURCES += [ + ("TP_Functions.c", {}), + ("TP_NetworkLayerLowerInterface_Rx.c", {}), + ("TP_NetworkLayerLowerInterface_Tx.c", {}), + ("TP_Rx.c", {}), + ("TP_RxFun.c", {}), + ("TP_Tx.c", {}), + ] \ No newline at end of file diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h new file mode 100644 index 0000000..5bf5628 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h @@ -0,0 +1,1090 @@ +#ifndef _ISO15765_3_H +#define _ISO15765_3_H + +/*----------------------------- includes ---------------------------------*/ + +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +#include "DiagnosticR/UDS/Iso15765_layer3/Iso15765_3_CFG.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" + +/*----------------------------- defines ----------------------------------*/ + +/* Mascara de bits d'obtencio de la subfuncio */ +#define UDS_SUBFUNCTION_MASK ((UI_8)0x7F) + +/* Positive Reponse Calculation Code */ +#define UDS_POS_RESP_CODE ((UI_8)0x40) + +/* Negative Response Code and Size */ +#define UDS_NEG_RESP_CODE ((UI_8)0x7F) +#define UDS_NEG_RESP_SIZE ((UI_16)0x03) + +/* UDS Session Identifiers */ +#define UDS_DEFAULT_SESSION ((UI_8)0x01) +#define UDS_PROGRAMMING_SESSION ((UI_8)0x02) +#define UDS_EXT_DIAG_SESSION ((UI_8)0x03) +//#define UDS_SAFETY_SYSTEM_DIAGNOSTIC_SESSION ((UI_8)0x04) NOT IMPLEMENTED YET +/* UDS Session Identifiers Mask */ +#define UDS_DEFAULT_SESSION_MASK ((UI_8)0x01) +#define UDS_PROGRAMMING_SESSION_MASK ((UI_8)0x02) +#define UDS_EXT_DIAG_SESSION_MASK ((UI_8)0x04) +//#define UDS_SAFETY_SYSTEM_DIAGNOSTIC_SESSION_MASK ((UI_8)0x08) NOT IMPLEMENTED YET +#define UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK ((UI_8)0x10) +#define UDS_ALL_SESSION_MASK ((UI_8)0xFF) +#define UDS_DEFAULT_VALUE_SESSION_MASK ((UI_8)0x00) + + +#if ((ISO15765_3_VARIANT == ISO15765_3_UDS)||(ISO15765_3_VARIANT == ISO15765_3_FIAT)||(ISO15765_3_VARIANT == ISO15765_3_UDS_ONLY_SF)||(ISO15765_3_VARIANT == ISO15765_3_GAC)) +/* LIN Services Identifiers */ +#define LIN_ASSIGN_FRAME_IDENTIFIER ((UI_8)0xB1) +#define LIN_ASSIGN_FRAME_IDENTIFIER_RANGE ((UI_8)0xB7) +#define LIN_READ_BY_IDENTIFIER ((UI_8)0xB2) +#define LIN_ASSIGN_NAD ((UI_8)0xB0) +#define LIN_CONDITIONAL_CHANGE_NAD ((UI_8)0xB3) + +/* UDS Services Identifiers */ +#define UDS_DIAGNOSTIC_SESSION_CONTROL ((UI_8)0x10) +#define UDS_ECU_RESET ((UI_8)0x11) +#define UDS_CLEAR_DIAGNOSTIC_INFORMATION ((UI_8)0x14) +#define UDS_READ_DTC_INFORMATION ((UI_8)0x19) +#define UDS_READ_DATA_BY_IDENTIFIER ((UI_8)0x22) +#define UDS_READ_MEMORY_BY_ADDRESS ((UI_8)0x23) +#define UDS_READ_SCALING_DATA_BY_IDENTIFIER ((UI_8)0x24) +#define UDS_SECURITY_ACCESS ((UI_8)0x27) +#define UDS_COMMUNICATION_CONTROL ((UI_8)0x28) +#define UDS_READ_DATA_BY_PERIODIC_IDENTIFIER ((UI_8)0x2A) +#define UDS_DYNAMICALLY_DEFINE_DATA_IDENTIFIER ((UI_8)0x2C) +#define UDS_WRITE_DATA_BY_IDENTIFIER ((UI_8)0x2E) +#define UDS_INPUT_OUTPUT_CONTROL_BY_ID ((UI_8)0x2F) +#define UDS_CONTROL_ROUTINE ((UI_8)0x31) +#define UDS_REQUEST_DOWNLOAD ((UI_8)0x34) +#define UDS_REQUEST_UPLOAD ((UI_8)0x35) +#define UDS_TRANSFER_DATA ((UI_8)0x36) +#define UDS_REQUEST_TRANSFER_EXIT ((UI_8)0x37) +#define UDS_WRITE_MEMORY_BY_ADDRESS ((UI_8)0x3D) +#define UDS_TESTER_PRESENT ((UI_8)0x3E) +#define UDS_ACCES_TIMING_PARAMETER ((UI_8)0x83) +#define UDS_SECURE_DATA_TRANSMISSION ((UI_8)0x84) +#define UDS_CONTROL_DTC_SETTING ((UI_8)0x85) +#define UDS_RESPONSE_ON_EVENT ((UI_8)0x86) +#define UDS_LINK_CONTROL ((UI_8)0x87) +#elif (ISO15765_3_VARIANT == ISO15765_3_RSA) +/* RSA Services Identifiers */ +#define RSA_START_ROUTINE_BY_LOCAL_ID ((UI_8)0x31) +#define RSA_STOP_ROUTINE_BY_LOCAL_ID ((UI_8)0x32) +#define RSA_READ_DATA_BY_LOCAL_ID ((UI_8)0x21) +#define RSA_REQUEST_UPLOAD ((UI_8)0x35) +#define RSA_WRITE_DATA_BY_LOCAL_ID ((UI_8)0x3B) +#define RSA_INPUT_OUTPUT_CONTROL_BY_LOCAL_ID ((UI_8)0x30) +#define RSA_READ_DATA_BY_IDENTIFIER ((UI_8)0x22) +#define RSA_REQUEST_DOWNLOAD ((UI_8)0x34) +#endif + +/* Iso15765_3SendResponse Valid Response Identifiers */ +#define ISO15765_3_POSITIVE_RESPONSE ((UI_8)0x01) +#define UDS_ERR_GENERAL_REJECT ((UI_8)0x10) +#define UDS_ERR_SERVICE_NOT_SUPPORTED ((UI_8)0x11) +#define UDS_ERR_SUBFUNCTION_NOT_SUPPORTED ((UI_8)0x12) +#define UDS_ERR_INVALID_FORMAT ((UI_8)0x13) +#define UDS_ERR_BUSY_REPEAT_REQUEST ((UI_8)0x21) +#define UDS_ERR_CONDITIONS_NOT_CORRECT ((UI_8)0x22) +#define UDS_ERR_ROUTINE_NOT_COMPLETE ((UI_8)0x23) +#define UDS_ERR_REQUEST_SEQUENCE_ERROR ((UI_8)0x24) +#define UDS_ERR_REQUEST_OUT_OF_RANGE ((UI_8)0x31) +#define UDS_ERR_SECURITY_ACCESS_DENIED ((UI_8)0x33) +#define UDS_ERR_INVALID_KEY ((UI_8)0x35) +#define UDS_ERR_EXCEEDED_NUMBER_OF_ATTEMPTS ((UI_8)0x36) +#define UDS_ERR_REQUIRED_TIME_DELAY_NOT_EXPIRED ((UI_8)0x37) +#define UDS_ERR_UPLOAD_DOWNLOAD_NOT_ACCEPTED ((UI_8)0x70) +#define UDS_ERR_TRANSFER_SUSPENDED ((UI_8)0x71) +#define UDS_ERR_GENERAL_PROGRAMMING_FAILURE ((UI_8)0x72) +#define UDS_ERR_WRONG_BLOCK_SEQUENCE ((UI_8)0x73) +#define UDS_ERR_RESPONSE_PENDING ((UI_8)0x78) +#define UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION ((UI_8)0x7E) +#define UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION ((UI_8)0x7F) + +/* Session Control Defines */ +#define UDS_DEFAULT_SESSION ((UI_8)0x01) + +/* Multidevice defines */ +#define DEVICE_0 ((UI_8)0x00) +#define DEVICE_1 ((UI_8)0x01) +#define DEVICE_2 ((UI_8)0x02) +#define DEVICE_3 ((UI_8)0x03) +typedef UI_8 t_device_addressed; + +#define UDS_REQUEST_DOWNLOAD_ERROR_INVALID_DEVICE ((UI_8)0x00) +#define UDS_REQUEST_DOWNLOAD_ERROR_INCOMPATIBLE_TYPE ((UI_8)0x01) +#define UDS_REQUEST_DOWNLOAD_ERROR_ECU_LOCKED ((UI_8)0x02) + +#define UDS_TRANSFER_DATA_ERROR_INVALID_BLOCK ((UI_8)0x00) +#define UDS_TRANSFER_DATA_ERROR_OUT_OF_RANGE ((UI_8)0x01) + + +/* Download Status Defines */ +#define DOWNLOAD_STATUS_IDLE ((UI_8)0x00) +#define DOWNLOAD_STATUS_ONGOING ((UI_8)0x01) +#define DOWNLOAD_STATUS_FINISHED_OK ((UI_8)0x02) +#define DOWNLOAD_STATUS_FINISHED_NOK ((UI_8)0x03) +typedef UI_8 t_download_status; + +/* Routine Control Types */ +#define UDS_START_ROUTINE ((UI_8)0x01) +#define UDS_STOP_ROUTINE ((UI_8)0x02) +#define UDS_REQUEST_ROUTINE_RESULTS ((UI_8)0x03) + +/* Download Address Size */ +#define ISO3_16BIT_ADDRESS (1) +#define ISO3_32BIT_ADDRESS (2) + +/* MASKS FOR STATUS PROGRAMMING */ +#define SETPROGRAMMING_STATUS_ECU_STATUS_VALID ((UI_32)0xFFFFFFFFU) +#define SETPROGRAMMING_STATUS_ECU_STATUS_NO_VALID ((UI_32)0xF9FFFFFFU) +#define SETPROGRAMMING_STATUS_DOWNLOAD_INCM_TYPE ((UI_32)0xF9FFBFFFU) +#define SETPROGRAMMING_STATUS_DOWNLOAD_INCM_AREA ((UI_32)0xF9FFDFFFU) +#define SETPROGRAMMING_STATUS_DOWNLOAD_INCM_SIZE ((UI_32)0xF9FF7FFFU) +#define SETPROGRAMMING_STATUS_WRONG_SECURITY_ACCESS ((UI_32)0xFFFFEFFFU) +#define SETPROGRAMMING_STATUS_TRANS_INCML_SIZE ((UI_32)0xF9FDFFFFU) +#define SETPROGRAMMING_STATUS_CHK_INCM_AREA ((UI_32)0xF9DFFFFFU) +#define SETPROGRAMMING_STATUS_CHK_INCM_SIZE ((UI_32)0xF9BFFFFFU) +#define SETPROGRAMMING_STATUS_WRONG_CHK ((UI_32)0xF97FFFFFU) +#define SETPROGRAMMING_STATUS_ERA_WR_ADDRR ((UI_32)0xF9EFFFFFU) +#define SETPROGRAMMING_STATUS_ERA_WR_SIZE ((UI_32)0xF9F7FFFFU) + +#define SETPROGRAMMING_STATUS_SEQ_TRANS ((UI_32)0xF9FEFFFFU) +#define SETPROGRAMMING_STATUS_SEQ_ERASE ((UI_32)0xF9FFFDFFU) +#define SETPROGRAMMING_STATUS_SEQ_WRDID ((UI_32)0xFFFFFEFFU) +#define SETPROGRAMMING_STATUS_SEQ_CHCKSUM ((UI_32)0xF9FFF7FFU) +#define SETPROGRAMMING_STATUS_HW_SW_INCMPL ((UI_32)0xF9FFFFFEU) //Return 0x13 +#define SETPROGRAMMING_STATUS_SW_RELEASE_INCMPL ((UI_32)0xF9FFFFFDU) //Return 0x70 + +/* EcuReset Subfunctions According to ISO15765_3 */ +#define UDS_HARD_RESET ((UI_8)0x01) +#define UDS_KEY_ON_OFF_RESET ((UI_8)0x02) +#define UDS_SOFT_RESET ((UI_8)0x03) +#define UDS_ENABLE_RAPID_POWER_SHUT_DOWN ((UI_8)0x04) +#define UDS_DISABLE_RAPID_POWER_SHUT_DOWN ((UI_8)0x05) + +/* Security Levels */ +#define UDS_ECU_LOCKED ((UI_8)0) +#define UDS_ECU_UNLOCKED_LEVEL1 ((UI_8)1) + +/* Control routine subfunctions */ +#define UDS_CTRL_ROUTINE_START ((UI_8)0x01) +#define UDS_CTRL_ROUTINE_STOP ((UI_8)0x02) +#define UDS_CTRL_ROUTINE_RESULTS ((UI_8)0x03) + +/* DTCs */ +/* DTCs CONTROL SETTINGS */ +#define UDS_DTCS_ON ((UI_8)0x01) +#define UDS_DTCS_OFF ((UI_8)0x02) +/* DTCs PARAMETER SUBFUNCTION */ +#define REPORT_NUMBER_OF_DTC_BY_STATUS_MASK ((UI_8)0x01) +#define REPORT_DTC_BY_STATUS_MASK ((UI_8)0x02) +#define REPORT_DTC_SNAPSHOT_IDENTIFICATION ((UI_8)0x03) +#define REPORT_DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER ((UI_8)0x04) +#define REPORT_DTC_SNAPSHOT_RECORD_BY_RECORD_NUMBER ((UI_8)0x05) +#define REPORT_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER ((UI_8)0x06) +#define REPORT_NUMBER_OF_DTC_BY_SEVERITY_MASK_RECORD ((UI_8)0x07) +#define REPORT_DTC_BY_SEVERITY_MASK_RECORD ((UI_8)0x08) +#define REPORT_SEVERITY_INFORMATION_OF_DTC ((UI_8)0x09) +#define REPORT_SUPPORTED_DTC ((UI_8)0x0A) +#define REPORT_FIRST_TEST_FAILED_DTC ((UI_8)0x0B) +#define REPORT_FIRST_CONFIRMED_DTC ((UI_8)0x0C) +#define REPORT_MOST_RECENT_TEST_FAILED_DTC ((UI_8)0x0D) +#define REPORT_MOST_RECENT_CONFIRMED_DTC ((UI_8)0x0E) +#define REPORT_MIRROR_MEMORY_DTC_BY_STATUS_MASK ((UI_8)0x0F) +#define REPORT_MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER ((UI_8)0x10) +#define REPORT_NUMBER_OF_MIRROR_MEMORY_DTC_BY_STATUS_MASK ((UI_8)0x11) +#define REPORT_NUMBER_OF_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK ((UI_8)0x12) +#define REPORT_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK ((UI_8)0x13) +#define REPORT_DTC_FAULT_DETECTION_COUNTER ((UI_8)0x14) +#define REPORT_DTC_WITH_PERMANENT_STATUS ((UI_8)0x15) +/* DTC STATUS MASK */ +#define DTC_TEST_FAILED_MASK ((UI_8)0x01) +#define DTC_TEST_FAILED_THIS_MONITORING_CYCLE_MASK ((UI_8)0x02) +#define DTC_PENDING_MASK ((UI_8)0x04) +#define DTC_CONFIRMED_MASK ((UI_8)0x08) +#define DTC_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR_MASK ((UI_8)0x10) +#define DTC_TEST_FAILED_SINCE_LAST_CLEAR_MASK ((UI_8)0x20) +#define DTC_TEST_NOT_COMPLETED_THIS_MONITORING_CYCLE_MASK ((UI_8)0x40) +#define DTC_TEST_WARNING_INDICATOR_REQUESTED_MASK ((UI_8)0x80) + + + +/* COMMUNICATION CONTROL */ +/* COMMUNICATION CONTROL SUBFUNCTIONS */ +#define UDS_ENABLE_RX_AND_TX ((UI_8)0x00) +#define UDS_ENABLE_RX_AND_DISABLE_TX ((UI_8)0x01) +#define UDS_DISABLE_RX_AND_DISABLE_TX ((UI_8)0x03) +/* COMMUNICATION CONTROL COMMUNICATION TYPE */ +#define UDS_NORMAL_COMM_MESSAGES ((UI_8)0x01) +#define UDS_NETWORK_MNG_COMM_MESSAGES ((UI_8)0x02) +#define UDS_DIAG_COMM_MESSAGES ((UI_8)0x04) + + +/*-------------------------- Data Types ----------------------------------*/ + +#if (DOWNLOAD_ADDRESS_SIZE == ISO3_16BIT_ADDRESS) +typedef UI_16 t_iso3_addr; +#elif (DOWNLOAD_ADDRESS_SIZE == ISO3_32BIT_ADDRESS) +typedef UI_32 t_iso3_addr; +#else + #error "Set the ISO3 Address Size" +#endif + +typedef enum { + ISO15765_3_FUN_REQUEST = 0, + ISO15765_3_PHY_REQUEST = 1 +} t_iso15765_3_req_mode; + +/* Tipus de dades adecuat per la resposta positiva a la peticio de */ +/* cada un dels serveis */ +/* Nomes es poden fer servir UI_8 perque l'endianes i l'alineament de */ +/* les dades a memoria pot variar entre plataformes */ + + +#if ((ISO15765_3_VARIANT == ISO15765_3_UDS) || (ISO15765_3_VARIANT == ISO15765_3_FIAT) || (ISO15765_3_VARIANT == ISO15765_3_UDS_ONLY_SF)) +/********************************************************************** +| Service: LIN_READ_BY_IDENTIFIER +|---------------------------------------------------------------------- +| Case ID==0: LIN Product ID +| Parameters: +| supplierId_L: LSB of LIN Supplier ID +| supplierId_H: MSB of LIN Supplier ID +| functionId_L: LSB of LIN Function ID +| functionId_H: MSB of LIN Function ID +| variant: variant version of the product +|---------------------------------------------------------------------- +| Size: 5 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 supplierId_L; + UI_8 supplierId_H; + UI_8 functionId_L; + UI_8 functionId_H; + UI_8 variant; +} * tp_lin_read_by_id_0_resp; + +/********************************************************************** +| Service: LIN_READ_BY_IDENTIFIER +|---------------------------------------------------------------------- +| Case ID==1: Serial number +| Parameters: +| serial_0: LSB of Serial Number +| serial_1: Serial Number part 2 +| serial_2: Serial Number part 3 +| serial_3: MSB of of Serial Number +|---------------------------------------------------------------------- +| Size: 4 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 serial_0; + UI_8 serial_1; + UI_8 serial_2; + UI_8 serial_3; +} * tp_lin_read_by_id_1_resp; + +/********************************************************************** +| Service: LIN_READ_BY_IDENTIFIER +|---------------------------------------------------------------------- +| Case ID>=16 && ID<=31: MessageID +| Parameters: +| messageID_LSB: LSB of requested message id +| messageID_MSB: MSB of requested message id +| protectedID: protectedID +|---------------------------------------------------------------------- +| Size: 3 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 messageID_LSB; + UI_8 messageID_MSB; + UI_8 protectedID; +} * tp_lin_read_by_id_2_resp; + +/********************************************************************** +| Service: LIN_READ_BY_IDENTIFIER +|---------------------------------------------------------------------- +| Case ID==32-63: User defined +| Parameters: +| user_def_0: user defined parameter +| user_def_1: user defined parameter +| user_def_2: user defined parameter +| user_def_3: user defined parameter +| user_def_4: user defined parameter +|---------------------------------------------------------------------- +| Size: 5 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 user_def_0; + UI_8 user_def_1; + UI_8 user_def_2; + UI_8 user_def_3; + UI_8 user_def_4; +} * tp_lin_read_by_id_userdef_resp; + +/********************************************************************** +| Servei: Diagnostic Session Control +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| ctrl_type: echo of the subfunction parameter from the request message +|---------------------------------------------------------------------- +| Mida: 5 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 ctrl_type; +} * tp_uds_communication_control_resp; + +/********************************************************************** +| Servei: Diagnostic Session Control +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| diagnostic_session: Ha de ser el mateix valor que s'ha passat +| com a parametre en la peticio del servei +| p2_high: MSB del valor del P2 que es pot oferir durant la nova sessio +| p2_low: LSB del valor del P2 que es pot oferir durant la nova sessio +| p2_high: MSB del valor del P2 extended que es pot oferir durant +| la nova sessio +| p2_high: MSB del valor del P2 extended que es pot oferir durant +| la nova sessio +|---------------------------------------------------------------------- +| Mida: 5 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 diagnostic_session; + UI_8 p2_high; + UI_8 p2_low; + UI_8 p2_ext_high; + UI_8 p2_ext_low; +} * tp_uds_diagnostic_session_control_resp; + +/********************************************************************** +| Servei: Ecu Reset +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| reset_mode: Ha de ser el mateix valor que s'ha passat +| com a parametre en la peticio del servei +|---------------------------------------------------------------------- +| Mida: 1 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 reset_mode; +} * tp_uds_ecu_reset_resp; + +/********************************************************************** +| Servei: Tester Present +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| zero: Ha de ser 0 +|---------------------------------------------------------------------- +| Mida: 1 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 zero; +} * tp_uds_tester_present_resp; + +/********************************************************************** +| Servei: Read Memory By Address +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| buffer_dades: Buffer per les dades demanades +|---------------------------------------------------------------------- +| Mida: mida buffer_dades +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 buffer_dades[(TP_DIAG_TX_LEN - (UI_8)1)]; +} * tp_uds_read_memory_by_address_resp; + +/********************************************************************** +| Servei: Security Access Seed +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| access_mode: El mateix access_mode que s'ha passat com a parametre +| a la rutina d'atencio al servei +| seed: La llavor calculada. +|---------------------------------------------------------------------- +| Mida: 1 + mida seed +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 access_mode; + UI_8 seed[(TP_DIAG_TX_LEN - (UI_8)2)]; +} * tp_uds_security_access_seed_resp; + +/********************************************************************** +| Servei: Security Access Key +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| access_mode: El mateix access_mode que s'ha passat com a parametre +| a la rutina d'atencio al servei +| security_access_status: ?? 0x34 +|---------------------------------------------------------------------- +| Mida: 2 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 access_mode; +} * tp_uds_security_access_key_resp; + +/********************************************************************** +| Servei: Write Data By Identifier +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| id_high: MSB del id passat com a parametre a la rutina d'atencio +| al servei. +| id_low: LSB del id passat com a parametre a la rutina d'atencio +| al servei. +|---------------------------------------------------------------------- +| Mida: 2 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 id_high; + UI_8 id_low; +} * tp_uds_write_data_by_identifier; + +/********************************************************************** +| Servei: Input Output Control By Identifier +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| io_ctrl_data_id: 2 bytes passats com a parametre a la rutina +| d'atencio al servei. +| io_ctrl_type: io_ctrl_param passat com a parametre a la rutina +| d'atencio al servei. +| control_state: buffer amb informacio control option record + +| control enable mask. +|---------------------------------------------------------------------- +| Mida: +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 id_high; + UI_8 id_low; + UI_8 io_ctrl_type; + UI_8 control_state[(TP_DIAG_TX_LEN - (UI_8)4)]; +} * tp_uds_input_output_control_by_id; + +/********************************************************************** +| Servei: Control Rountine +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| routine_ctrl_type: routine ctrl type passed during the service +| request +| routine_id: routine_local_id passat com a parametre a la +| rutina d'atencio al servei +| routine_results: Buffer de dades amb el resultat +|---------------------------------------------------------------------- +| Mida: 3 + mida routine_results +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 routine_ctrl_type; + UI_8 routine_id_high; + UI_8 routine_id_low; + UI_8 routine_status[(TP_DIAG_TX_LEN - (UI_8)4)]; +} * tp_uds_control_routine; + +/********************************************************************** +| Servei: Read Data By Local Identifier +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| id_high: MSB del identificador de la informacio demanada passada +| com a parametre a la rutina d'atencio al servei. +| id_low: LSB del identificador de la informacio demanada passada +| com a parametre a la rutina d'atencio al servei. +| buffer_dades: Buffer per les dades d'identificacio demanades +|---------------------------------------------------------------------- +| Mida: 1 + mida buffer_dades +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 buffer_dades[(TP_DIAG_TX_LEN - (UI_8)3)]; +} * tp_uds_read_data_by_identifier_resp; + + +/********************************************************************** +| Servei: Read DTC Information +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| id_high: MSB del identificador de la informacio demanada passada +| com a parametre a la rutina d'atencio al servei. +| id_low: LSB del identificador de la informacio demanada passada +| com a parametre a la rutina d'atencio al servei. +| buffer_dades: Buffer per les dades d'identificacio demanades +|---------------------------------------------------------------------- +| Mida: 1 + mida buffer_dades +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 subservice; + UI_8 buffer_dades[(TP_DIAG_TX_LEN - (UI_8)2)]; +}* tp_uds_read_dtc_information_resp; + +/********************************************************************** +| Servei: Control DTC Setting +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| buffer_dades: Buffer per les dades d'identificacio demanades +|---------------------------------------------------------------------- +| Mida: 1 + mida buffer_dades +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 dtc_setting_type; +} * tp_uds_control_dtc_setting_resp; + +/********************************************************************** +| Servei: Request Download +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| len_format_id: bit [7..4]: Length (number of bytes) of the +| max_num_of_block_len parameter. +| bit [3..0]: zero +| max_num_of_block_len: mida del buffer de transferencia +|---------------------------------------------------------------------- +| Mida: 1 + mida max_num_of_block_len +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 len_format_id; + UI_8 max_num_of_block_len[(TP_DIAG_TX_LEN - (UI_8)2)]; +} * tp_uds_request_download; + +/********************************************************************** +| Servei: Transfer data +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| block_seq: Numero de sequencia de TranferData que s'ha passat en +| la peticio del servei +| data: Buffer de dades +|---------------------------------------------------------------------- +| Mida: 1 + mida de data +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 block_seq; + UI_8 data_buf[(TP_DIAG_TX_LEN - (UI_8)2)]; +} * tp_uds_transfer_data; + +/********************************************************************** +| Servei: Request Transfer Exit +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| data: Buffer de dades +|---------------------------------------------------------------------- +| Mida: mida de data +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 data_buf[(TP_DIAG_TX_LEN - (UI_8)1)]; +} * tp_uds_request_transfer_exit; + +/********************************************************************** +| Servei: Write Memory By Address +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 1 + mida buffer_dades +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 addr_data_length_id; + UI_8 buffer_dades[(TP_DIAG_TX_LEN - (UI_8)2)]; +} * tp_uds_write_memory_by_address; + + +#elif (ISO15765_3_VARIANT == ISO15765_3_RSA) +/********************************************************************** +| Servei: Start Routine By Local Id de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +| routine_id: identifier of the routine to start +| routine_params: +|---------------------------------------------------------------------- +| Mida: 2 + mida routine_params +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 routine_id; + UI_8 routine_status; + UI_8 routine_params[(TP_DIAG_TX_LEN - (UI_8)3)]; +} * tp_rsa_start_routine_by_local_id; + +/********************************************************************** +| Servei: ReadDataByLocalId de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 1 + mida data +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 read_id; + UI_8 data_buf[(TP_DIAG_TX_LEN - (UI_8)2)]; +} * tp_rsa_read_data_by_local_id; + +/********************************************************************** +| Servei: StopRoutineByLocalId de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 2 + mida routine_results +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 routine_id; + UI_8 routine_status; + UI_8 routine_params[(TP_DIAG_TX_LEN - (UI_8)3)]; +} * tp_rsa_stop_routine_by_local_id; + +/********************************************************************** +| Servei: RequestUpload de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: mida de upload_resp +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 upload_resp[(TP_DIAG_TX_LEN - (UI_8)1)]; +} * tp_rsa_request_upload; + +/********************************************************************** +| Servei: WriteDataByLocalId de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 1 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 write_id; +} * tp_rsa_write_data_by_local_id; + +/********************************************************************** +| Servei: InputOutputControlByLocalId de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 2 + mida de data +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 input_output_id; + UI_8 control_status; + UI_8 data_buf[(TP_DIAG_TX_LEN - (UI_8)3)]; +} * tp_rsa_input_output_control_by_local_id; + +/********************************************************************** +| Servei: ReadDataByIdentifier de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: mida de id_with_data +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 id_with_data[TP_DIAG_TX_LEN - (UI_8)1]; +} * tp_rsa_read_data_by_identifier; +#endif + +/********************************************************************** +| Servei: RequestDownload de RSA +|---------------------------------------------------------------------- +| Explicacio dels parametres: +|---------------------------------------------------------------------- +| Mida: 1 +/--------------------------------------------------------------------*/ +typedef struct { + UI_8 status; +} * tp_rsa_request_download; + +typedef struct { + t_download_status download_status; + t_device_addressed device_addressed; + UI_8 download_compression; + UI_8 download_encrypting; + t_iso3_addr base_addr; + t_iso3_addr dest_addr; + t_iso3_addr last_addr; + UI_8 block_seq; + UI_16 block_size; + t_iso3_addr block_ptr; +}t_download_control; + +typedef struct { + UI_8 local_seed[SECURITY_SEED_SIZE]; + UI_8 host_key[SECURITY_KEY_SIZE]; +}t_security_control; + +/*--------------------------- variables globals --------------------------*/ + +/* Answer Control */ +extern UI_8 force_response; +extern t_clock timer_s3; +extern t_clock timer_p2; +extern BOOL iso15765_3_supress_pos_resp; +extern UI_8 iso15765_3_current_service; +extern UI_8 pending_response_mode; +extern BOOL pending_response; +extern t_iso15765_3_req_mode iso15765_3_request_mode; + +/* Download Control */ +extern t_download_control download_control; + +/* Security Session Control */ +extern t_security_control security_control; + +/* Phisical and functional diagnostic config structures */ +extern UI_8 diag_phy_rx_buf[TP_DIAG_RX_LEN]; +#if (FUN_DIAG_STATUS == FUN_DIAG_DISABLED) +extern UI_8 diag_fun_rx_buf[TP_DIAG_FUN_RX_LEN]; +#endif + +#ifdef LIN_ISO3 + extern UI_8 diag_tx_buf[TP_DIAG_RX_TX_LEN]; +#else + extern UI_8 diag_tx_buf[TP_DIAG_TX_LEN]; +#endif + +/*------------------------- prototips de funcions ------------------------*/ +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'inicialitzacio del kwp2000. +|--------------------------------------------------------------------------- +| Parameters Explanation: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InicialitzaIso15765_3Task(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Tasca principal del kwp2000 que ha de ser cridada de forma periodica en +| el bucle principal del programa. +|--------------------------------------------------------------------------- +| Parameters Explanation: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3Task(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Macro d'acces al buffer de resposta d'una peticio de servei. +| * El contigut del buffer nomes es valid fins que es retorna del context +| de la rutina que n'ha obtingut l'acces. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| t_kwp_resp_data: Tipus de dades de la resposta per la cual es vol obtenir +| acces al buffer. +| resultat: variable del tipus de la resposta demanat. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#define ISO15765_3_GET_RESP_DATA(t_uds_resp_data) ((t_uds_resp_data)&diag_tx_buf[1]) + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by the callbacks to increment the size of the positive response +|--------------------------------------------------------------------------- +| Arguments: +| resp_frm_size: NUmber of bytes added to the response buffer +| by the callback +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3IncrementResponseSize(UI_16 resp_frm_size); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by the callbacks to increment the size of the positive response +|--------------------------------------------------------------------------- +| Arguments: +| resp_frm_size: NUmber of bytes added to the response buffer +| by the callback +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_16 Iso15765_3GetResponseSize(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'enviament de resposta a una peticio de servei. +| * Tot servei ha d'acabar amb la crida a aquesta rutina. +| * Quan s'envia com a resposta ISO16765_3_ERR_RESPONSE_PENDING s'activa +| l'enviament periodic de respostes negatives amb peticio d'extensio +| de temps fins que s'envia amb aquesta rutina una altre resposta. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3SendResponse(UI_8 resp_mode); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina de canvi de la sessio activa actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| new_session: Valor de la que sera la nova sessio activa +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3ChangeActiveSession(UI_8 new_session); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Funcio de consulta de la sessio activa actual +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: Numero de la sessio activa actual. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_8 Iso15765_3QueryActiveSession(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Funcio de consulta de la sessio activa actual +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: Numero de la sessio activa actual. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_8 Iso15765_3QueryActiveSessionMask(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina de canvi del nivell d'acces de seguretat +|--------------------------------------------------------------------------- +| Parameters Explanation: +| new_sec_acc_sts: Nou nivell d'acces de seguretat +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsChangeSecurityAccessStatus(UI_8 new_sec_acc_sts); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Funcio de consulta del nivell de seguretat. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: Valor del nivell d'acces de seguretat actual +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_8 UdsSecurityTaskQueryAccessStatus(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Check if request seed is consecutive or the first request. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: true if consecutive, false is first +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL UdsSecurityTaskQueryIfConsecutiveRequestSeed(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Provide the random number for seed generic. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: random number +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_8 UdsSecurityTaskSeedGeneric(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Funcio de consulta del mode d'adreçament de la peticio de servei actual +|--------------------------------------------------------------------------- +| Parameters Explanation: +| resultat: KWP_PHY_REQUEST si s'ha fet una peticio fisica (punt a punt) +| KWP_FUN_REQUEST si s'ha fet una peticio funcional (broadcast) +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_iso15765_3_req_mode Iso15765_3QueryRequestMode(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by any function to know the size of the digan frame +|--------------------------------------------------------------------------- +| +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_16 Iso15765_3QueryRequestSize( void ); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina descodificadora del servei requerit en la peticio de servei actual +|--------------------------------------------------------------------------- +| Parameters Explanation: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3Servicios(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina que s'ha de cridar de forma sincrona que desancadena l'enviament +| de resposta a la capa inferior +| * Aquesta rutina nomes pot ser cridada de forma sincrona dins la maquina +| d'estats de capa 3 +|--------------------------------------------------------------------------- +| Arguments: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code (neg response) +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3SendResponseSync(UI_8 resp_mode); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Routine that check if a response has been sent. This routine must be +| called after sending a response to check when this response has been +| sent. +|--------------------------------------------------------------------------- +| Arguments: +| * return TRUE if the response has been sent or if a TX problem has been +| detected. Return FALSE if the response is still pending to be sent. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL Iso15765_3GetResponseSent(void); + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'atencio al servei Diagnostic Session Control +| * Aquest servei s'utilitza per gestionar la sessio de diagnostic activa +| * La seva implementacio es obligatoria +| * S'ha d'enviar la resposta positiva abans que la nova sessio s'activi +| * Les diferents rutines i funcions del protocol ISO15765_· que es poden +| fer servir per implementar aquest servei son: +| Iso15765_3ChangeActiveSession(...) per canviar la sessio activa +| Iso15765_3QueryActiveSession() per consultar la sessio activa actual. +| Iso_15765_3QuerySecurityAccessStatus() per consultar el nivell de +| seguretat actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| session: Nova sessio que es vol que sigui la sessio activa +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#ifdef UDS_SERVICE_SESSION_CONTROL +void UDServiceSessionCtrl(UI_8 session, UI_8 size); +void Iso15765_3_ForceSessionChange ( UI_8 session, BOOL supress_positive_response ); +#endif + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina que recupera la ISO15765_3 en cas que la capa d'aplicacio no +| hagi donat resposta durant un timeout de error maxim. Aquesta rutina +| posara la capa 2 i la capa 3 en estat idle per tornar a acceptar peticions +| de diagnostic. +|--------------------------------------------------------------------------- +| Arguments: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code (neg response) +| unblock_iso2: flag that says to ISO15765_2 if has to unblock himself +| at the end of this next transmission +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3AbortResponse(void); + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_CFG_TEMPLATE.h b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_CFG_TEMPLATE.h new file mode 100644 index 0000000..2e39c45 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_CFG_TEMPLATE.h @@ -0,0 +1,591 @@ +#ifndef _ISO15765_3_CFG_H_ +#define _ISO15765_3_CFG_H_ + + +/* ISO15765_3 VARIANTS */ +#define ISO15765_3_UDS (0x00) +#define ISO15765_3_RSA (0x01) +#define ISO15765_3_FIAT (0x02) +#define ISO15765_3_VARIANT (ISO15765_3_UDS) + +/* ISO15765_3 MODE */ +#define ISO15765_3_APP (0x00) +#define ISO15765_3_BL (0x01) +#define ISO_3_MODE (ISO15765_3_BL) + +/* FICOSA_SYSTEM_SUPPLIER_SESSION */ +/* 0x60 - 0x7E systemSupplierSpecific: this range of values is reserved for system-supplier-specific use.*/ +/* ISO 14229-1:2006(E) pag 39 */ +#define UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID ((UI_8)0x60) + +/* Size of the buffer that must store the largest frame for the */ +/* diagnostic server instance (ISO15765_3) */ +/* The size of the buffer must be declared using the macro */ +/* SIZE_ALLOC_BUFFER to assure that no overflows will happen during */ +/* transmission or reception of frames larger than single frames */ +//DMP: It cannot be integrated with the current ISO 2 +//#define FUN_DIAG_DISABLED (0x00) +//#define FUN_DIAG_ENABLED (0x01) +//#define FUN_DIAG_STATUS (FUN_DIAG_ENABLED) +//#if (FUN_DIAG_STATUS == FUN_DIAG_ENABLED) +#define TP_DIAG_FUN_RX_LEN (SIZE_ALLOC_BUFFER(8)) +//#endif +//NO ES POT ENGANCHAR AMB ISO_2 +#define TP_DIAG_RX_LEN (SIZE_ALLOC_BUFFER(4096)) +#define TP_DIAG_TX_LEN (SIZE_ALLOC_BUFFER(4096)) + +/* Used ISO15765_2 stack in order to send and receive */ +/* the diagnostics */ +#define DIAG_ISO15765_2_HDL (ISO15765_2_REPROGONCAN_HANDLER) + +/*****************************************************************************/ +/* TIMING */ +/*****************************************************************************/ +/* Max time allowed to answer a request. In milliseconds */ +#define P2_MAX ((UI_16)50) + +/* Max time between a UDS_ERR_RESPONSE_PENDING and the next answer. In ms */ +#define P2_EXT_MAX ((UI_16)1000) + +/* Max counter between a UDS_ERR_RESPONSE_PENDING and the next answer. */ +#define P2_EXT_MAX_COUNTER ((UI_16)5) + +/* Session Expiration Timeout. In ms */ +#define S3_MAX ((UI_16)5000) + +/*****************************************************************************/ +/* DATA TYPES */ +/*****************************************************************************/ +/* Specify the Download Addresses size: */ +/* Possible values: ISO3_16BIT_ADDRESS, ISO3_32BIT_ADDRESS */ +#define DOWNLOAD_ADDRESS_SIZE (ISO3_32BIT_ADDRESS) + +/*****************************************************************************/ +/* UDS SERVICES */ +/*****************************************************************************/ +/* SECURITY ACCESS ENABLED/DISABLED */ +#define SERVICE_DISABLED (0x00) +#define SERVICE_ENABLED (0x01) + +#define LIN_ASSIGN_FRAME_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ +#define LIN_READ_BY_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define LIN_ASSIGN_NAD_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ +#define LIN_CONDITIONAL_CHANGE_NAD_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ + +#define UDS_SERVICE_SESSION_CONTROL_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_ECU_RESET_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_SECURITY_ACCESS_STATUS (SERVICE_DISABLED) +#define UDS_SERVICE_TESTER_PRESENT_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_CONTROL_DTC_SETTING_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS_STATUS (SERVICE_DISABLED)//NOT IMPLEMENTED YET +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_STATUS (SERVICE_DISABLED)//NOT IMPLEMENTED YET +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_DTC_INFORMATION_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_IO_CTRL_BY_ID_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_ROUTINE_CONTROL_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_REQUEST_DOWNLOAD_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_TRANSFER_DATA_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_REQUEST_TRANSFER_EXIT_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_COMMUNICATION_CONTROL_STATUS (SERVICE_ENABLED) + +#if (LIN_ASSIGN_FRAME_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * ASSIGN FRAME IDENTIFIER (0xB7) + ***************************************************************************** + * This service IS ONLY VALID in LIN version 2.0 + * CALLBACKS: + * LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK(UI_8 supplierID_LSB, UI_8 supplierID_MSB, UI_8 messageID_LSB, UI_8 messageID_MSB, UI_8 new_pid): + * 'supplierID' defines the product vendor identifier. + * 'messageID' defines the message identifier as in section in Lin Description File. + * 'new_pid' defines the new pid to identify the frame with the selected messageID. + * A response shall be sent if the assignation is successful. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK (LinAssignFrameId) +#endif + +#if (LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * ASSIGN FRAME IDENTIFIER RANGE (0xB7) + ***************************************************************************** + * This service IS MANDATORY in all three LIN diagnostics classes + * (See 4.2.5.5 on LIN Spec 2.2) + * CALLBACKS: + * LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK(UI_8 index, const UI_8* new_pid_list): + * 'index' defines the protected identifier (pid) start from the pid list available. + * 'new_pid_lis' defines a buffer where are specified the four new pids for change + * counting from index. + * - 0x00: Disable service. + * - 0xFF: Do not change PID. + * - 0xXX: Change pid. + * The system shall only response if NAD matched. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER_RANGE (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK (LinAssignFrameIdRange) +#endif + + +#if (LIN_READ_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ BY IDENTIFIER (0xB2) + ***************************************************************************** + * This service IS MANDATORY in all three LIN diagnostics classes for ID = 0x00 + * The rest of identifier are optional. + * (See 4.2.6.1 on LIN Spec 2.2) + * CALLBACKS: + * LIN_READ_BY_IDENTIFIER_CALLBACK(UI_8 id): + * 'id' defines the identifier requested. + * - 0x00: LIN Product identification: SupplierID, FunctionID & Variant. + * - 0x01: Serial Number. + * - 0x32-0x63: User defined. + * - The rest of identifiers are reserved. + * The system shall accordingly to each request. (See 4.2.6.1 on LIN Spec 2.2) + ****************************************************************************/ +#define LIN_SERVICE_READ_BY_IDENTIFIER (UDS_DEFAULT_SESSION_MASK) +#define LIN_READ_BY_IDENTIFIER_CALLBACK (LinReadByID) +#endif + + +#if (LIN_ASSIGN_NAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * LIN ASSIGN NAD (0xB0) + ***************************************************************************** + * This service CAN be enabled/disabled + * (See 4.2.5.1 on LIN Spec 2.2) + * CALLBACKS: + * LIN_ASSIGN_NAD_CALLBACK(UI_16 supplierId, UI_16 functionId, UI_8 new_nad): + * - 'supplierId' and 'functionId' must be the same as defined in the system, + * otherwise the NAD won't be assigned. + * - 'new_nad' is the new NAD to be assigned + * The system shall response with the initial NAD to confirm the change. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_NAD (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_NAD_CALLBACK (LinAssignNAD) +#endif + + +#if (LIN_CONDITIONAL_CHANGE_NAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * LIN CONDITIONAL CHANGE NAD (0xB3) + ***************************************************************************** + * This service CAN be enabled/disabled + * (See 4.2.5.2 on LIN Spec 2.2) + * CALLBACKS: + * LIN_CONDITIONAL_CHANGE_NAD_CALLBACK(UI_8 id, UI_8 byte, UI_8 mask, UI_8 invert, UI_8 new_nad): + * 1. 'id' Get the identifier specified by the function LinReadByID. + * 2. Extract the data byte selected by Byte (Byte = 1 corresponds to the first byte, D1). + * 3. Do a bitwise XOR with Invert. + * 4. Do a bitwise AND with Mask. + * 5. If the final result is zero then change the NAD to New NAD. + * The system shall response with the new NAD to confirm the change. + ****************************************************************************/ +#define LIN_SERVICE_CONDITIONAL_CHANGE_NAD (UDS_DEFAULT_SESSION_MASK) +#define LIN_CONDITIONAL_CHANGE_NAD_CALLBACK (LinConditionalChangeNAD) +#endif + + +#if (UDS_SERVICE_SESSION_CONTROL_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * DIAGNOSTICS SESSION CONTROL (0x10) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * .- UDS_INI_SESSION_CALLBACK: The user MAY implement this callback. + * Called when layer 3 changes session + * DEFINES: + * .- UDS_USER_DEFINED_SESSION. Valid User Defined Session ID + ****************************************************************************/ +#define UDS_SERVICE_SESSION_CONTROL (UDS_ALL_SESSION_MASK) +#define UDS_USER_DEFINED_SESSION (UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID) +#define UDS_INI_SESSION_CALLBACK (UdsIniSession) + +#endif + +#if (UDS_SERVICE_ECU_RESET_STATUS == SERVICE_ENABLED) +/**************************************************************************** + * ECU RESET (0x11) + **************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * BOOL CHECK_RESET_POSSIBLE(UI_8 reset_type): + * Asks the user if this reset type is allowed at this point in time. + * Return TRUE if yes + * void EXECUTE_RESET(UI_8 reset_type): + * Execute the reset type requested + ****************************************************************************/ +#define UDS_SERVICE_ECU_RESET (UDS_PROGRAMMING_SESSION_MASK | UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define CHECK_RESET_POSSIBLE (UdsCheckResetIsPossible) +#define EXECUTE_RESET (UdsExecuteResetNow) + +#endif + +#if (UDS_SERVICE_SECURITY_ACCESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * SECURITY ACCESS(0x27) + **************************************************************************** + * This service can be enabled/disabled + * CALLBACKS: + * void UDS_SECURITY_REQUEST_SEED_CALLBACK(UI_8* p_local_seed): + * Generate a Random Seed and place it in p_local_seed (4 bytes) + * BOOL UDS_SECURITY_CHECK_KEY_CALLBACK(UI_8* p_local_seed, UI_8* p_tool_key): + * Check the key returned by the tool. Return TRUE is ok + * DEFINES + * UDS_SERVICE_SECURITY_ACCESS: set the session which accepts this service. + * SECURITY_INIT_DELAY: Set to SECURITY_DELAY, to introduce 10 secs + * delay after Reset, before accepting security resets. Set to + * SECURITY_NO_DELAY if no delay is wanted. + * MAX_SECURITY_ATTEMPTS: Number of failed attempts before starting the penalty + * SECURITY_PENALTY_TIME: Time to wait before next attempt. + * SECURITY_SEED_SIZE: Number of bytes of the security seed (max = 4) + * SECURITY_KEY_SIZE: Number of bytes of the security seed (max = 4) + * UDS_SECURITY_COUNTER_NVM_CALLBACK: Callback to store a new value of the counter in NVM. + * - Signature: void UDS_SECURITY_COUNTER_NVM_CALLBACK(UI_8 *value) + * - (legacy) If not defined, then value will not be stored in NVM. + * UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK: Callback to retrieve the value of the counter from NVM, tipically + * at the beginning of the execution. + * - Signature: UI_8 UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK(void) + * - (legacy) If not defined, then value will be loaded as zero (check startup strategy for penalty delay + * using SECURITY_INIT_DELAY). + ****************************************************************************/ + ****************************************************************************/ +#define UDS_SERVICE_SECURITY_ACCESS (UDS_EXT_DIAG_SESSION_MASK) +#define UDS_SECURITY_REQUEST_SEED_CALLBACK (UdsSecurityGetSeed) +#define UDS_SECURITY_CHECK_KEY_CALLBACK (UdsSecurityCheckKey) +#define SECURITY_INIT_DELAY (SECURITY_NO_DELAY) +#define MAX_SECURITY_ATTEMPTS ((UI_8) 2) +#define SECURITY_PENALTY_TIME ((UI_16) 10000) +#define SECURITY_SEED_SIZE ((UI_8) 4) +#define SECURITY_KEY_SIZE ((UI_8) 4) +#define UDS_SECURITY_COUNTER_NVM_CALLBACK () +#define UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK () + +#endif + +#if (UDS_SERVICE_TESTER_PRESENT_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TESTER PRESENT (0x3E) + ***************************************************************************** + * This service CAN be enabled/disabled + * No User CALLBACK Needed + ****************************************************************************/ +#define UDS_SERVICE_TESTER_PRESENT (UDS_ALL_SESSION_MASK) + +#endif + + +#if (UDS_SERVICE_READ_DATA_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ DATA BY ID(0x22) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK(UI_8 id_high, + * UI_8 id_low): Pass the ID to the user to + * process the request. The user is responsible for checking the security + * status for each parameter, and to send the appropiate response. + *****************************************************************************/ +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK (UdsReadDataByIdentifier) + +#endif + +#if (UDS_SERVICE_READ_MEMORY_BY_ADDRESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ MEMORY BY ADDRESS(0x23) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK(UI_8 mem_size_len, + * UI_8 mem_addr_len, UI_8* mem_addr, UI_8* mem_size): The user must + * retrieve the requested memory address buffer and return it to the host + *****************************************************************************/ +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS (UDS_DEFAULT_SESSION_MASK) +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK (UdsReadMemoryByAddress) + +#endif + + +#if (UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * WRITE DATA BY IDENTIFIER(0x2E) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UI_16 id, + * UI_8* p_buf, UI_16 size): This callback is + * responsible for starting the writting process to get the data written + * in the apporpiate memory position / device and to + * return the command that must be sent back to the tool + * id: The id to modify + * p_buf: Id data as sent by the diagnostics tool + * size: Amount of ID data bytes received + *****************************************************************************/ +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UdsWriteDataByIdentifier) + +#endif + +#if (UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * WRITE MEMORY BY ADDRES(0x3D) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UI_8 id_high, + * UI_8 id_low, UI_8* p_buf, UI_16 size): + * This callback is used by the user to write the data identified with id + * in the appropiate mamory / device. The data sent by the host is passed + * in p_buf/size + *****************************************************************************/ +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS (UDS_DEFAULT_SESSION_MASK) +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_CALLBACK (UdsWriteMemoryByAddr) + +#endif + + +#if (UDS_SERVICE_CONTROL_DTC_SETTING_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * CONTROL DTC SETTING (0x85) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK(UI_8 dtc_setting_mode, + * UI_8* buf_data_rx, I_16 size): + * size: size of the dtc option record received + * buf_data_rx: pointer to the dtc option record received + * This callback is responsible for sending the appropiate response + ****************************************************************************/ +#define UDS_SERVICE_CONTROL_DTC_SETTING (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK (UdsControlDtcSetting) + +#endif + + +#if (UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * CLEAR DTC INFORMATION(0x14) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK(UI_8* p_dtc_group) + * Clear all DTC codes identified by the p_dtc_group reference + *****************************************************************************/ +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK (UdsClearDtc) + +#endif + + +#if (UDS_SERVICE_READ_DTC_INFORMATION_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ DTC INFORMATION(0x19) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK (UI_16 id, + * UI_8* p_buf, UI_16 size): + * Retrieve and send the Diagnostics Info identified by id. + *****************************************************************************/ +#define UDS_SERVICE_READ_DTC_INFORMATION (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK (UdsReadDtc) + +#endif + + +#if (UDS_SERVICE_IO_CTRL_BY_ID_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * I/O CONTROL BY ID(0x2F) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_INPUT_OUTPUT_CONTROL_BY_ID(UI_8 *data_buffer, UI_8 size) +*****************************************************************************/ +#define UDS_SERVICE_IO_CTRL_BY_ID (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_IO_CTRL_BY_ID_CALLBACK (UdsInputOutputControlByIdentifier) + +#endif + + +#if (UDS_SERVICE_ROUTINE_CONTROL_STATUS == SERVICE_ENABLED) +/**************************************************************************** + * ROUTINE CONTROL(0x31) + **************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_ROUTINE_CONTROL_START_CALLBACK(UI_8 id_high, UI_8 id_low, + * UI_16 size, UI_8 *data_buffer); + * Host wants to start a control routine. + * User is responsible for returning the appropiate response code. + ****************************************************************************/ +#define UDS_SERVICE_ROUTINE_CONTROL (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_ROUTINE_CONTROL_CALLBACK (UdsControlRoutine) + +#endif + + +#if (UDS_SERVICE_REQUEST_DOWNLOAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * REQUEST DOWNLOAD(0x34) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACK: + * UI_8 DEVICE_0_REQUEST_DOWNLOAD_CALLBACK(t_addr base_addr, t_addr last_addr) + * The host wnats to start a download from address dl_base with a size + * of dl_size in bytes. Calculate if this is possible. And give an answer + * Define one callback for each device in the system that may receive + * data through a downlonad. + ****************************************************************************/ +#define UDS_SERVICE_REQUEST_DOWNLOAD (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_REQUEST_DOWNLOAD_CALLBACK (UdsPlm2BLRequestDownload)*/ + +#endif + + +#if (UDS_SERVICE_TRANSFER_DATA_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TRANSFER DATA(0x36) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS + * UI_8 DEVICE_0_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size) + * A data block is sent by the host, program it in the right memory. + * The right destination address is responsability of the user callback + * Define one callback per each device that can receive the data + ****************************************************************************/ +#define UDS_SERVICE_TRANSFER_DATA (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_TRANSFER_DATA_CALLBACK (UdsPlm2BLTransferData)*/ + +#endif + + +#if (UDS_SERVICE_REQUEST_TRANSFER_EXIT_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TRANSFER EXIT(0x37) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACK: + * UI_8 DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size) + * The host informs us that the download process is finished + ****************************************************************************/ +#define UDS_SERVICE_REQUEST_TRANSFER_EXIT (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK (UdsPlm2BLTransferExit)*/ + +#endif + +#if (UDS_SERVICE_COMMUNICATION_CONTROL_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * COMMUNICATION CONTROL (0x28) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * .- UDS_COMMUNICATION_CONTROL_CALLBACK: The user MAY implement this callback. + * DEFINES: + * .- UDS_COMMUNICATION_CONTROL. Session in which the service will be supported + ****************************************************************************/ +#define UDS_SERVICE_COMMUNICATION_CONTROL (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_COMMUNICATION_CONTROL_CALLBACK (UdsCommunicationControl) + +#endif + +/*************** Extra services configuration *************/ +/** In order to allow new services to be developed, proceed to configure them as follows + ** In this example, we have added an extra service B01 called GEELY_ECHO */ + +#define UDS_SERVICE_GEELY_ECHO_STATUS (SERVICE_DISABLED) /*!< Geely custom echo test service -SR2372*/ + +#if (UDS_SERVICE_GEELY_ECHO_STATUS == SERVICE_ENABLED) +typedef struct { + UI_8 buffer_dades[(TP_DIAG_TX_LEN - (UI_8)1)]; +} * tp_uds_geely_echo_resp; + +/** Mechansim to allow the creation of new services */ +#define UDS_EXTRA_SERVICES +#define UDS_EXTRA_SERVICES_CALLBACK (UdsExtraServices) + +/***************************************************************************** + * Custom service Geely TEST ECHO (0xB0) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * .- UDS_SERVICE_GEELY_ECHO_CALLBACK: The user MAY implement this callback. + * DEFINES: + * .- UDS_SERVICE_GEELY_ECHO. Session in which the service will be supported + ****************************************************************************/ +#define UDS_GEELY_ECHO ((UI_8)0xB0) +#define UDS_SERVICE_GEELY_ECHO (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_GEELY_ECHO_CALLBACK (UdsGeelyEcho) + +#endif + + +/***************************************************************************** + * Security attempts counter section + ***************************************************************************** + * The security attempts counters can be unique or level dependent. + * Increment and decrement values and maximum security attempts can be configured. + * Allows definition of NVM callbacks to store the counter in flash. + * If this section is NOT configured (previous CFG files): + * - the increment will be 1 + * - the decrement will be MAX_SECURITY_ATTEMPTS (clear the counter) + * - there is only one counter for whole system + * - threshold will be equal to MAX_SECURITY_ATTEMPTS + * - Leaves the NVM callbacks undefined (no NVM support). + * ... in order to keep backwards compatibility + ****************************************************************************/ + +/*** BEGIN Example of configuration +- Uses (or not) counters by level. +- Maximum counter is equaled to MAX_SECURITY_ATTEMPTS. +- The count is exceeded when equal to MAX_SECURITY_ATTEMPTS +- Increments 1 +- Decrements MAX_SECURITY_ATTEMPTS (so after waiting penalty time will clear the count). +If no SECURITY_ATTEMPT_COUNTERS_BY_LEVEL defined, this configuration is same than before introducing this feature, but allowing NVM storage of the counter. +**** +#ifdef SECURITY_ATTEMPT_COUNTERS_BY_LEVEL + +#define UDS_NUMBER_OF_SECURITY_LEVELS ((UI_8)3) /*< Number of different security levels +#define UDS_SESSION_IDENTIFIERS_VECTOR {UDS_ECU_UNLOCKED_LEVEL1, UDS_ECU_UNLOCKED_LEVEL11, UDS_ECU_UNLOCKED_LEVEL61} /*< Identifiers of the security level (index table) +#define UDS_SECURITY_ACCESS_MAX_VECTOR {MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS} /*< Maximum values for each counter +#define UDS_SECURITY_ACCESS_INCR_VECTOR {((UI_8)1),((UI_8)1),((UI_8)1)} /*< Increment delta for counting +#define UDS_SECURITY_ACCESS_DECR_VECTOR {MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS} /*< Decrement delta for counting +#define UDS_SECURITY_ACCESS_THRESHOLD_VECTOR {MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS} /*< Threshold to determine if the number of attempts has been exceeded for each counter + +#else + +#define UDS_SECURITY_ACCESS_INCR ((UI_8)1) /*< Value to increment on each wrong access +#define UDS_SECURITY_ACCESS_DECR ((UI_8)1) /*< Value to decrement when penalty delay is done +#define UDS_SECURITY_ACCESS_PENALTY_THRESHOLD MAX_SECURITY_ATTEMPTS /*< Value to decide if the penalty delay must be applied + +#endif + +#define UDS_SECURITY_COUNTER_NVM_CALLBACK (UdsSecurityCounterNvmCallback) /*< Callback to perform NVM storage of the counter +#define UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK (UdsSecurityCounterNvmLoadCallback) /*< Callback to retrieve the counter from EEPROM + +********** END Example of configuration ***************/ + +/* #define SECURITY_ATTEMPT_COUNTERS_BY_LEVEL */ /* Uncomment to activate different security access failed attempt counters per security level */ + +#ifdef SECURITY_ATTEMPT_COUNTERS_BY_LEVEL + +#define UDS_NUMBER_OF_SECURITY_LEVELS ((UI_8)3) /*< Number of different security levels +#define UDS_SESSION_IDENTIFIERS_VECTOR {UDS_ECU_UNLOCKED_LEVEL1, UDS_ECU_UNLOCKED_LEVEL11, UDS_ECU_UNLOCKED_LEVEL61} /*< Identifiers of the security level (index table) +#define UDS_SECURITY_ACCESS_MAX_VECTOR {MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS} /*< Maximum values for each counter +#define UDS_SECURITY_ACCESS_INCR_VECTOR {((UI_8)1),((UI_8)1),((UI_8)1)} /*< Increment delta for counting +#define UDS_SECURITY_ACCESS_DECR_VECTOR {((UI_8)1),((UI_8)1),((UI_8)1)} /*< Decrement delta for counting +#define UDS_SECURITY_ACCESS_THRESHOLD_VECTOR {MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS,MAX_SECURITY_ATTEMPTS} /*< Threshold to determine if the number of attempts has been exceeded for each counter + +#else + +#define UDS_SECURITY_ACCESS_INCR ((UI_8)1) /*< Value to increment on each wrong access +#define UDS_SECURITY_ACCESS_DECR ((UI_8)1) /*< Value to decrement when penalty delay is done +#define UDS_SECURITY_ACCESS_PENALTY_THRESHOLD MAX_SECURITY_ATTEMPTS /*< Value to decide if the penalty delay must be applied + +#endif + +#define UDS_SECURITY_COUNTER_NVM_CALLBACK () /*< Callback to perform NVM storage of the counter +#define UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK () /*< Callback to retrieve the counter from EEPROM + +#endif diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c new file mode 100644 index 0000000..8c7c3b1 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_EcuResetTask.c @@ -0,0 +1,338 @@ + +/*------------------------------- includes --------------------------------*/ +//#include "Global.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h" + + +/*------------------------------ user code --------------------------------*/ + +#include "Iso15765_3.h" + +#define RESET_NO_REQUEST ((UI_8)0) +#define RESET_REQUESTED ((UI_8)1) +#define RESET_REQUESTED_PENDING ((UI_8)2) + +#define TIMEOUT_RESET ((UI_16) 5000) + +static UI_8 reset_request; +static UI_8 reset_type; + +void UDSResetRequest(UI_8 req_reset_type, UI_8 size) +{ +if(CHECK_RESET_TYPE(req_reset_type) == TRUE){ +if(size == 1){ +reset_type=req_reset_type; +reset_request=RESET_REQUESTED; +} +else{ +Iso15765_3SendResponse(UDS_ERR_INVALID_FORMAT); +} +} +else{ +Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); +} +} + +static void SendResetResponse(UI_8 err) +{ +tp_uds_ecu_reset_resp resp; +resp=ISO15765_3_GET_RESP_DATA(tp_uds_ecu_reset_resp); + +if(err == ISO15765_3_POSITIVE_RESPONSE){ +resp->reset_mode = reset_type; +Iso15765_3IncrementResponseSize(1); +} +Iso15765_3SendResponse(err); +} + + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +typedef enum { + ESTAT_ISO15765_3_ECURESETTASK_WAITING_FOR_RESET = 1, + ESTAT_ISO15765_3_ECURESETTASK_ANSWERING_RESET = 2, + ESTAT_ISO15765_3_ECURESETTASK_RESET_EXECUTE = 3, + ESTAT_ISO15765_3_ECURESETTASK_WAITINGTODORESET = 4, + ESTAT_0_ISO15765_3_ECURESETTASK = 0 +} t_estat_iso15765_3_ecuresettask; + + +/*------------------------------ variables --------------------------------*/ + +/* Variables d estat */ +static t_estat_iso15765_3_ecuresettask estat_iso15765_3_ecuresettask = ESTAT_0_ISO15765_3_ECURESETTASK; + +/* Timers implicits */ +static t_clock temps_iso15765_3_ecuresettask = (t_clock)0; + + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void Iso15765_3_EcuResetTask0(void); +static void Waiting_For_Reset(void); +static void Answering_Reset(void); +static void Reset_Execute(void); +static void WaitingToDoReset(void); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats Iso15765_3_EcuResetTask +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +void Iso15765_3_EcuResetTaskInicialitza(void) +{ + /* Inicialitzacio de la variable d estat */ + estat_iso15765_3_ecuresettask = ESTAT_0_ISO15765_3_ECURESETTASK; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* Execucio del cicle inicial de la maquina d estats */ + Iso15765_3_EcuResetTask(); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats Iso15765_3_EcuResetTask. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +void Iso15765_3_EcuResetTask(void) +{ + /* Estudi per casos del estat actual */ + switch (estat_iso15765_3_ecuresettask){ + case ESTAT_0_ISO15765_3_ECURESETTASK: + Iso15765_3_EcuResetTask0(); + break; + case ESTAT_ISO15765_3_ECURESETTASK_WAITING_FOR_RESET: + Waiting_For_Reset(); + break; + case ESTAT_ISO15765_3_ECURESETTASK_ANSWERING_RESET: + Answering_Reset(); + break; + case ESTAT_ISO15765_3_ECURESETTASK_RESET_EXECUTE: + Reset_Execute(); + break; + case ESTAT_ISO15765_3_ECURESETTASK_WAITINGTODORESET: + WaitingToDoReset(); + break; + default: + estat_iso15765_3_ecuresettask = ESTAT_0_ISO15765_3_ECURESETTASK; + break; + } + + /* Increment del temps de cicle al timer implicit */ + if (temps_iso15765_3_ecuresettask < MAX_COMPTADOR_TEMPS) { + temps_iso15765_3_ecuresettask += TimerDeltaCicleConsulta(); + } +} + + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces Iso15765_3_EcuResetTask +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void Iso15765_3_EcuResetTask0(void) +{ + /* Transicio per defecte */ + + /* -- entry de l estat -- */ + reset_request = RESET_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* Canviem l estat inicial */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_WAITING_FOR_RESET; +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Waiting_For_Reset. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +static void Waiting_For_Reset(void) +{ + if (((reset_request == RESET_REQUESTED) || (reset_request == RESET_REQUESTED_PENDING)) && (CHECK_RESET_POSSIBLE(reset_type)==TRUE) && (CHECK_RESET_TYPE(reset_type)==TRUE)) { + /* Cas en que executem la transicio Check_Reset_Possible */ + + /* -- action de la transicio -- */ + SendResetResponse(ISO15765_3_POSITIVE_RESPONSE); + + /* -- entry de l estat Answering_Reset -- */ + reset_request = RESET_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_ANSWERING_RESET; + } + else if (((reset_request == RESET_REQUESTED) || (reset_request == RESET_REQUESTED_PENDING)) && (CHECK_RESET_TYPE(reset_type)==TRUE) && (CHECK_RESET_POSSIBLE(reset_type)==FALSE)) { + /* Cas en que executem la transicio Reset_Not_Possible_Now */ + + /* -- action de la transicio -- */ + SendResetResponse(UDS_ERR_RESPONSE_PENDING); + reset_request = RESET_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_WAITINGTODORESET; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_WAITING_FOR_RESET; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Answering_Reset. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +static void Answering_Reset(void) +{ + if ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE ) && (pending_response == FALSE)) { + /* Cas en que executem la transicio Wait_answer_sent */ + + /* -- entry de l estat Reset_Execute -- */ + EXECUTE_RESET(reset_type); + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_RESET_EXECUTE; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_ANSWERING_RESET; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Reset_Execute. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +static void Reset_Execute(void) +{ + /* Aquest es un estat pou. Ja no es canviara d estat */ + /* Per redundancia es reassigna el mateix estat */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_RESET_EXECUTE; +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat WaitingToDoReset. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +| Sortides: +| estat_iso15765_3_ecuresettask +| temps_iso15765_3_ecuresettask +****************************************************************************/ +static void WaitingToDoReset(void) +{ + if ((CHECK_RESET_POSSIBLE(reset_type)==TRUE)) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + SendResetResponse(ISO15765_3_POSITIVE_RESPONSE); + + /* -- entry de l estat Answering_Reset -- */ + reset_request = RESET_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_ANSWERING_RESET; + } + else if (temps_iso15765_3_ecuresettask >= TIMER_MS_TO_TICKS(TIMEOUT_RESET)) { + /* Cas en que executem la transicio TimeoutReset */ + + /* -- action de la transicio -- */ + SendResetResponse(UDS_ERR_BUSY_REPEAT_REQUEST); + reset_request = RESET_NO_REQUEST; + + /* -- entry de l estat Waiting_For_Reset -- */ + reset_request = RESET_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_ecuresettask= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_WAITING_FOR_RESET; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_ecuresettask = ESTAT_ISO15765_3_ECURESETTASK_WAITINGTODORESET; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c new file mode 100644 index 0000000..f892def --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Funcions.c @@ -0,0 +1,2040 @@ + +/*----------------------------- includes ---------------------------------*/ +//#include "Global.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" + +//#include "TP.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +//#include "Iso15765_3_CFG.h" +#include "DiagnosticR/UDS/Iso15765_layer3/Iso15765_3_CFG.h" +#include "Iso15765_3_Task.h" +#include "Iso15765_3.h" +#include "DiagnosticR/ProjectCfg.h" + +/*-------------------------- Secondary State Machines ---------------------*/ + + +/*----------------------------- macros -----------------------------------*/ + +/* Decode if asnwer is wanted to UDS request */ +#define SET_POS_RESP_SUPRESS_FLAG(flag) \ + flag=((buf_data_rx[(UI_8)1]&UDS_SUPRESS_POS_RESP_IND)==UDS_SUPRESS_POS_RESP_IND) + +/*----------------------------- defines ----------------------------------*/ + +/* UdsControRoutine: Supported Compression and Encryption Methode */ +#define COMPRESSION_METHOD_NONE ((UI_8)0) +#define ENCRYPTING_METHOD_NONE ((UI_8)0) + +/* Download Process Maximum Size of each Data Block */ +#define MAX_BLOCK_LENGTH ((UI_16)(MAX(TP_DIAG_RX_BUFFER,TP_DIAG_TX_BUFFER)-2)) + +/* Size of a diagnostic negative response */ +#define TP_FRM_NEG_BUF_SIZE ((UI_8)3) + +/* Bit de subfuncio indicatiu de supresio de resposta positiva */ +#define UDS_SUPRESS_POS_RESP_IND ((UI_8)0x80) + +/* P2 is the maximum time between request-response */ +#define TIMER_P2_RESET (TimerDeltaCicleConsulta()) + +#define REQUEST_SEED_MASK ((UI_8)0x01) + +/*-------------------------- Data Types ----------------------------------*/ + +/*--------------------------- variables globals --------------------------*/ + +/* Force a Response without having a request: Usefull on start-up answers */ +/* Called from Iso15765_3_RequestRespondCtrl.c */ +UI_8 force_response = (UI_8) 0x00; + +/* Download Control */ +t_download_control download_control; + + +/* Global variables of Security Task*/ +#if(UDS_SERVICE_SECURITY_ACCESS_STATUS==SERVICE_ENABLED) +t_security_control security_control; +#endif + +/* Response Control */ +BOOL iso15765_3_supress_pos_resp; +UI_8 iso15765_3_current_service = (UI_8) 0; +BOOL pending_response = FALSE; +UI_8 pending_response_mode; +t_clock timer_p2; +t_clock timer_s3; +t_iso15765_3_req_mode iso15765_3_request_mode; + +//DMP: It cannot be integrated with the current ISO 2 +//#if (FUN_DIAG_STATUS == FUN_DIAG_ENABLED) +/* Buffer used to receive TP diagnostic requests FUN */ +UI_8 diag_fun_rx_buf[TP_DIAG_FUN_RX_LEN]; +//#endif + +#ifdef LIN_ISO3 +/* Buffer used to receive TP diagnostic requests */ +UI_8 diag_rx_buf[TP_DIAG_RX_TX_LEN]; +/* Buffer used to send TP positive responses frames */ +UI_8 diag_tx_buf[TP_DIAG_RX_TX_LEN]; +#else +/* Buffer used to receive TP diagnostic requests PHY */ +UI_8 diag_phy_rx_buf[TP_DIAG_RX_LEN]; +/* Buffer used to send TP positive responses frames */ +UI_8 diag_tx_buf[TP_DIAG_TX_LEN]; +#endif +/* Buffer used to send TP negative responses frames */ +UI_8 diag_tx_neg[TP_FRM_NEG_BUF_SIZE]; +/* Size of the last diagnostic received */ +UI_16 iso15765_3_last_frame_size = (UI_16) 0; + +/* Size of the constructed transmission diagnostic frame that will be sent */ +static UI_16 diag_tx_size_pos; + +/*------------------------- Prototypes Local Functions ---------------------*/ +#ifdef UDS_SERVICE_REQUEST_DOWNLOAD +static void UdsRequestDownload(UI_8 data_format, UI_8 addr_len_format, + UI_8 *mem_addr, UI_8 *mem_size); +#endif +#ifdef UDS_SERVICE_TRANSFER_DATA +static void UdsTransferData(UI_8 block_seq, UI_16 size, UI_8 *data_buf); +#endif +#ifdef UDS_SERVICE_REQUEST_TRANSFER_EXIT +static void UdsTransferExit(UI_16 size, UI_8 *data_buf); +#endif + +#ifndef UDS_SERVICE_SECURITY_ACCESS + +UI_8 UdsSecurityTaskQueryAccessStatus(void) { + return UDS_ECU_UNLOCKED_LEVEL1; +} +#endif + +/*-------------------------------- Functions ------------------------------*/ +#ifdef UDS_INI_DEFAULT_SESSION_FROM_BOOTLOADER +extern void UDS_INI_DEFAULT_SESSION_FROM_BOOTLOADER(void); +#endif + +#ifdef UDS_READ_APP_VALID +extern BOOL UDS_READ_APP_VALID(void); +#endif + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina d'inicialitzacio del Uds. +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InicialitzaIso15765_3Task(void) { + /* Global Initializations */ + iso15765_3_current_service = (UI_8) 0; + download_control.download_status = DOWNLOAD_STATUS_IDLE; + + /* Compulsary State Machines Inits */ + Iso15765_3_RequestRespondCtrlInicialitza(); + + /* Optional State Machines Initialization */ +#ifdef UDS_SERVICE_SESSION_CONTROL + Iso15765_3_SessionCtrlTaskInicialitza(); +#endif +#ifdef UDS_SERVICE_ECU_RESET + Iso15765_3_EcuResetTaskInicialitza(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + // Iso15765_3_SecurityTaskInicialitza(); +#endif + +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Tasca principal del Uds que ha de ser cridada de forma periodica en +| el bucle principal del programa. +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3Task(void) { + /* Compulsary State Machines */ + Iso15765_3_RequestRespondCtrl(); + + /* Optional State Machines */ +#ifdef UDS_SERVICE_SESSION_CONTROL + Iso15765_3_SessionCtrlTask(); +#endif +#ifdef UDS_SERVICE_ECU_RESET + Iso15765_3_EcuResetTask(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + // Iso15765_3_SecurityTask(); +#endif + +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by the callbacks to increment the size of the positive response +|--------------------------------------------------------------------------- +| Arguments: +| resp_frm_size: NUmber of bytes added to the response buffer +| by the callback +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3IncrementResponseSize(UI_16 resp_frm_size) { + diag_tx_size_pos += resp_frm_size; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by the callbacks to increment the size of the positive response +|--------------------------------------------------------------------------- +| Arguments: +| resp_frm_size: NUmber of bytes added to the response buffer +| by the callback +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_16 Iso15765_3GetResponseSize(void) { + return diag_tx_size_pos; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina que activa el mecanisme de resposta a una peticio de servei de +| forma asincrona. +| * Tot servei ha d'acabar amb la crida a aquesta rutina. +| * Quan s'envia com a resposta ISO15765_3_ERR_RESPONSE_PENDING s'activa +| l'enviament periodic de respostes negatives amb peticio d'extensio +| de temps fins que s'envia amb aquesta rutina una altre resposta. +|--------------------------------------------------------------------------- +| Arguments: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code (neg response) +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3SendResponse(UI_8 resp_mode)//DMP: Revisar bug TCU on respostes sincrones xocaven amb request asincrones +{ + /* JCL: ISO14299 -> If the response is a NRC = PENDING the positive + answer must be sent. */ + if (resp_mode == UDS_ERR_RESPONSE_PENDING) { + iso15765_3_supress_pos_resp = FALSE; + } + /* Save the asynchronous response pending type */ + pending_response_mode = resp_mode; + /* Set the flag to indicate the response pending to the synchronous mechanism */ + pending_response = TRUE; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina que s'ha de cridar de forma sincrona que desancadena l'enviament +| de resposta a la capa inferior +| * Aquesta rutina nomes pot ser cridada de forma sincrona dins la maquina +| d'estats de capa 3 +|--------------------------------------------------------------------------- +| Arguments: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code (neg response) +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3SendResponseSync(UI_8 resp_mode)//DMP: Revisar bug TCU on respoestes sincrones xocaven amb request asincrones +{ /* ISO3_SEND */ + /* Reset the unblock_after_tx flag, will be set only in specific cases */ + tp_frm[DIAG_ISO15765_2_HDL].unblock_after_tx = FALSE; + + /* Positive Response */ + if (resp_mode == ISO15765_3_POSITIVE_RESPONSE) { + /* Positive response disabled by the service for this request */ + if (iso15765_3_supress_pos_resp == TRUE) { + if (iso15765_3_request_mode == ISO15765_3_FUN_REQUEST) { + tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; + } else { + tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; + } + }/* Positive response requested */ + else { + /* Make sure no funcional answer is triggered */ + if (iso15765_3_request_mode == ISO15765_3_FUN_REQUEST) { + tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; + } + /* Book the positive sending */ + tp_frm[DIAG_ISO15765_2_HDL].size_tx = diag_tx_size_pos; + tp_frm[DIAG_ISO15765_2_HDL].data_tx = diag_tx_buf; + tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + tp_frm[DIAG_ISO15765_2_HDL].sts_tx = TP_FRM_TX_REQ; + tp_frm[DIAG_ISO15765_2_HDL].unblock_after_tx = TRUE; + } + }/* Response Pending */ + else if (resp_mode == UDS_ERR_RESPONSE_PENDING) { + diag_tx_neg[0] = UDS_NEG_RESP_CODE; + /* Get the id serviced directly from the RX buffer because this */ + /* service has not been processed */ + diag_tx_neg[1] = tp_frm[DIAG_ISO15765_2_HDL].data_rx[0]; + diag_tx_neg[2] = resp_mode; + + tp_frm[DIAG_ISO15765_2_HDL].data_tx = diag_tx_neg; + tp_frm[DIAG_ISO15765_2_HDL].size_tx = UDS_NEG_RESP_SIZE; + tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + tp_frm[DIAG_ISO15765_2_HDL].sts_tx = TP_FRM_TX_REQ; + tp_frm[DIAG_ISO15765_2_HDL].unblock_after_tx = TRUE; + + timer_p2 = TIMER_P2_RESET; + }/* Negative Response */ + else { + /* Response not needed */ + /* ISO makes us to remove the response in the following cases */ + if ((iso15765_3_request_mode == ISO15765_3_FUN_REQUEST) && + ((resp_mode == UDS_ERR_SERVICE_NOT_SUPPORTED) || + (resp_mode == UDS_ERR_SUBFUNCTION_NOT_SUPPORTED) || + (resp_mode == UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION) || + /* DMN: No response should be sent in functional: page 23-24 of ISO 14229-1: "Road vehicles - Unified diagnostic services (UDS)" */ + (resp_mode == UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION) || + (resp_mode == UDS_ERR_REQUEST_OUT_OF_RANGE))) { + //tp_fun_frm.sts=TP_FRM_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + //UnblockIso15765_2(); + tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; + }/* Needed Response */ + else { + /* Make sure no funcional answer is triggered */ + if (iso15765_3_request_mode == ISO15765_3_FUN_REQUEST) { + tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + /* Unblock ISO15765_2 to accept the entry of new services */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; + } + diag_tx_neg[0] = UDS_NEG_RESP_CODE; + diag_tx_neg[1] = iso15765_3_current_service; + diag_tx_neg[2] = resp_mode; + tp_frm[DIAG_ISO15765_2_HDL].data_tx = diag_tx_neg; + tp_frm[DIAG_ISO15765_2_HDL].size_tx = UDS_NEG_RESP_SIZE; + tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + tp_frm[DIAG_ISO15765_2_HDL].sts_tx = TP_FRM_TX_REQ; + tp_frm[DIAG_ISO15765_2_HDL].unblock_after_tx = TRUE; + } + } + + /* Clear the asyncrhonous response pending flag */ + pending_response = FALSE; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina que recupera la ISO15765_3 en cas que la capa d'aplicacio no +| hagi donat resposta durant un timeout de error maxim. Aquesta rutina +| posara la capa 2 i la capa 3 en estat idle per tornar a acceptar peticions +| de diagnostic. +|--------------------------------------------------------------------------- +| Arguments: +| resp_mode: ISO15765_3_POSITIVE_RESPONSE positive response +| ISO15765_3_ERR_RESPONSE_PENDING pending response +| Any other value is considered an error code (neg response) +| unblock_iso2: flag that says to ISO15765_2 if has to unblock himself +| at the end of this next transmission +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3AbortResponse(void) { + + /* Check the last request mode */ + if (iso15765_3_request_mode == ISO15765_3_FUN_REQUEST) { + /* Set the diagnostic status as idle to be prepared for new requests */ + tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + } else { + /* Set the diagnostic status as idle to be prepared for new requests */ + tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; + tp_frm[DIAG_ISO15765_2_HDL].sts_tx = TP_FRM_TX_IDLE; + } + /* Unblock ISO2 to allow new requests be processed */ + tp_frm[DIAG_ISO15765_2_HDL].iso15765_2_block_rx = FALSE; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Funcio de consulta del mode d'adreçament de la peticio de servei actual +|--------------------------------------------------------------------------- +| Arguments: +| resultat: KWP_PHY_REQUEST si s'ha fet una peticio fisica (punt a punt) +| KWP_FUN_REQUEST si s'ha fet una peticio funcional (broadcast) +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_iso15765_3_req_mode Iso15765_3QueryRequestMode(void) { + return iso15765_3_request_mode; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| Used by any function to know the size of the digan frame +|--------------------------------------------------------------------------- +| +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_16 Iso15765_3QueryRequestSize(void) { + return iso15765_3_last_frame_size; +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Rutina descodificadora del servei requerit en la peticio de servei actual +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3Servicios(void) { /* ISO3_ENTRY */ + + BOOL request_size_ok = TRUE; + BOOL error_detected = FALSE; + UI_8 *buf_data_rx = NULL; + SI_8 service_subfunction = 0; + UI_16 size = 0; + UI_16 aux_index = 0; + UI_8 current_session_mask = 0; + UI_8 response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + UI_8 response_mode_aux = UDS_ERR_REQUEST_OUT_OF_RANGE; + + /* Get the addressing mode */ + /* Physical requests get priority */ + if (tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF) { + iso15765_3_request_mode = ISO15765_3_PHY_REQUEST; + buf_data_rx = &tp_frm[DIAG_ISO15765_2_HDL].data_rx[0]; + size = tp_frm[DIAG_ISO15765_2_HDL].size_rx; + } else if (tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF) { + iso15765_3_request_mode = ISO15765_3_FUN_REQUEST; + buf_data_rx = &tp_fun_frm[DIAG_ISO15765_2_HDL].data_rx[0]; + size = tp_fun_frm[DIAG_ISO15765_2_HDL].size; + } else { + buf_data_rx = NULL; + error_detected = TRUE; + } + + /* By default, we set the suppression of pos response to FALSE */ + /* Each service will modify this according to the incoming frame */ + /* if needed */ + iso15765_3_supress_pos_resp = FALSE; + + /* Save the iso15765_3 frame size to be able to get it from other functions */ + iso15765_3_last_frame_size = size; + + /* Get the requested service */ + if ((size >= (UI_8) 1) && (error_detected == FALSE) && (buf_data_rx != NULL)) { + iso15765_3_current_service = buf_data_rx[(UI_8) 0]; + service_subfunction = (buf_data_rx[(UI_8) 1] & UDS_SUBFUNCTION_MASK); + /* Set the byte 0 of the positive response frame */ + /* Reset the counter of TX Frame Length */ + diag_tx_buf[0] = iso15765_3_current_service + UDS_POS_RESP_CODE; + diag_tx_size_pos = 1; + } else { + iso15765_3_current_service = (UI_8) 0; + } + + /* Integrated Session Control Checking */ + current_session_mask = Iso15765_3QueryActiveSessionMask(); + + /* Switch to the requested service routine */ + switch (iso15765_3_current_service) { +#ifdef LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER + case LIN_ASSIGN_FRAME_IDENTIFIER: + if ((current_session_mask & LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size >= (UI_8) 5) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK(buf_data_rx[(UI_8) 1], buf_data_rx[(UI_8) 2], buf_data_rx[(UI_8) 3], buf_data_rx[(UI_8) 4], buf_data_rx[(UI_8) 5]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif + +#ifdef LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER_RANGE + case LIN_ASSIGN_FRAME_IDENTIFIER_RANGE: + if ((current_session_mask & LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER_RANGE) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size >= (UI_8) 5) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK(buf_data_rx[(UI_8) 1], &buf_data_rx[(UI_8) 2]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif + +#ifdef LIN_SERVICE_READ_BY_IDENTIFIER + case LIN_READ_BY_IDENTIFIER: + if ((current_session_mask & LIN_SERVICE_READ_BY_IDENTIFIER) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size >= (UI_8) 1) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + LIN_READ_BY_IDENTIFIER_CALLBACK(buf_data_rx[(UI_8) 1]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif + +#ifdef LIN_SERVICE_ASSIGN_NAD + case LIN_ASSIGN_NAD: + if ((current_session_mask & LIN_SERVICE_ASSIGN_NAD) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size >= (UI_8) 5) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + LIN_ASSIGN_NAD_CALLBACK(*(UI_16*) & buf_data_rx[(UI_8) 1], *(UI_16*) & buf_data_rx[(UI_8) 3], buf_data_rx[(UI_8) 5]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif + + +#ifdef LIN_SERVICE_CONDITIONAL_CHANGE_NAD + case LIN_CONDITIONAL_CHANGE_NAD: + if ((current_session_mask & LIN_SERVICE_CONDITIONAL_CHANGE_NAD) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size >= (UI_8) 5) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + LIN_CONDITIONAL_CHANGE_NAD_CALLBACK(buf_data_rx[(UI_8) 1], buf_data_rx[(UI_8) 2], buf_data_rx[(UI_8) 3], buf_data_rx[(UI_8) 4], buf_data_rx[(UI_8) 5]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif + + +#ifdef UDS_SERVICE_SESSION_CONTROL + case UDS_DIAGNOSTIC_SESSION_CONTROL: + if ((current_session_mask & UDS_SERVICE_SESSION_CONTROL) != 0x00) { +#ifndef ISO15765_3_GEELY + /* In GEELY UDS the first thing to check is the adressing. Should not respond with + bad format in functional mode*/ + if (size >= (UI_8) 2) { +#endif + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); +#if (ISO_3_MODE == ISO15765_3_BL) +#ifndef ISO15765_3_GEELY + /* For this reason the changes are under compiler defines */ + if ((current_session_mask == UDS_PROGRAMMING_SESSION_MASK) && (service_subfunction == UDS_EXT_DIAG_SESSION)) { +#else + /* In bootloader, we support an extended session, however, we do not support to transition from programming to extended */ + /* In bootloader, we support an extended session, however, we do not support to transition from programming to extended */ + /* In Geely specification, we can only reach programming session from extended session */ + if ( + ((current_session_mask == UDS_PROGRAMMING_SESSION_MASK) && (service_subfunction == UDS_EXT_DIAG_SESSION)) || + (((current_session_mask != UDS_EXT_DIAG_SESSION_MASK) && (current_session_mask != UDS_PROGRAMMING_SESSION_MASK)) && (service_subfunction == UDS_PROGRAMMING_SESSION)) + ) { +#endif + /* Negative response: We do not support this in active programming session */ + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + }/* Call service routine only in Phy request and no prog session*/ + else if ((iso15765_3_request_mode != ISO15765_3_FUN_REQUEST) || ((UI_8) service_subfunction != UDS_PROGRAMMING_SESSION)) { +#ifdef ISO15765_3_GEELY + /* In GEELY UDS the first thing to check is the adressing. Should not respond with + bad format in functional mode*/ + if (size >= (UI_8) 2) { +#endif + request_size_ok = TRUE; + UDServiceSessionCtrl(service_subfunction, size); +#ifdef ISO15765_3_GEELY + /* In GEELY UDS the first thing to check is the adressing. Should not respond with + bad format in functional mode*/ + } else { + request_size_ok = FALSE; + } +#endif + } else if (size > (UI_8) 2) { + /* Programming session in functional addressing with wrong size -> Invalid format*/ + request_size_ok = FALSE; + } else { + /* Programming session in functional addressing with correct size -> Subfunction not supported (not sent in functional addressing)*/ + request_size_ok = TRUE; + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } +#else + /* Call service routine only in Phy request and no prog session*/ + if ((iso15765_3_request_mode != ISO15765_3_FUN_REQUEST) || ((UI_8) service_subfunction != UDS_PROGRAMMING_SESSION)) { +#ifndef ISO15765_3_GEELY + if (size >= (UI_8) 2) { + request_size_ok = TRUE; + UDServiceSessionCtrl(service_subfunction, size); +#else + /* In Geely specification, we can only reach programming session from extended session */ + /* For this reason the changes are under compiler defines */ + if ((current_session_mask != UDS_EXT_DIAG_SESSION_MASK) && (service_subfunction == UDS_PROGRAMMING_SESSION)) { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } else { + if (size >= (UI_8) 2) { + request_size_ok = TRUE; + UDServiceSessionCtrl(service_subfunction, size); + } else { + request_size_ok = FALSE; + } + } +#endif +#ifndef ISO15765_3_GEELY + } else { + request_size_ok = FALSE; + } +#endif + } else if (size > (UI_8) 2) { + /* Programming session in functional addressing with wrong size -> Invalid format*/ + request_size_ok = FALSE; + } else { + /* Programming session in functional addressing with correct size -> Subfunction not supported (not sent in functional addressing)*/ + request_size_ok = TRUE; + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } +#endif +#ifndef ISO15765_3_GEELY + /* In GEELY UDS the first thing to check is the adressing. Should not respond with + bad format in functional mode*/ + } else { + request_size_ok = FALSE; + } +#endif + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_ECU_RESET + case UDS_ECU_RESET: + if ((current_session_mask & UDS_SERVICE_ECU_RESET) != 0x00) { + /* ISO14229-1 - Only 2 bytes in this service */ + if (size == (UI_8) 2) { + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Call service routine */ + UDSResetRequest(service_subfunction, (size - 1)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + case UDS_SECURITY_ACCESS: + if ((current_session_mask & UDS_SERVICE_SECURITY_ACCESS) != 0x00) { + if ((size >= (UI_8) 2) && (Iso15765_3QueryRequestMode() == ISO15765_3_PHY_REQUEST)) { + /* Check positive-response-not-requested flag, + * Suppress bit not supported in Geely */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + if ((service_subfunction & 0x03) != 0) { +#if(ISO15765_3_VARIANT == ISO15765_3_FIAT) + /* CHECK VALID SEED REQUESTS FOR FIAT */ + if (((current_session_mask == UDS_PROGRAMMING_SESSION_MASK) && (service_subfunction == 0x01)) || + ((current_session_mask == UDS_EXT_DIAG_SESSION_MASK) && (service_subfunction == 0x05))) { + /* ECU is requesting a seed */ + if (size == 2) { + UdsSecurityTaskRequestSeed(service_subfunction); + } else { + request_size_ok = FALSE; + } + } else if ((service_subfunction == 0x01) || (service_subfunction == 0x05)) { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } + +#else + + if(service_subfunction == 0x03) + { + if(size == 2) + { + /* GO DIRECTLY TO THE REQUEST SEED CALLBACK */ + /* ECU is requesting a seed */ + //UdsSecurityTaskRequestSeed(service_subfunction); + }else{ + request_size_ok = FALSE; + } + }else{ + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } +#endif + } else { +#if(ISO15765_3_VARIANT == ISO15765_3_FIAT) + /* FIRST CHECK THE VALID SUBFUNCTIONS FOR FIAT */ + if (((current_session_mask == UDS_PROGRAMMING_SESSION_MASK) && (service_subfunction == 0x02)) || + ((current_session_mask == UDS_EXT_DIAG_SESSION_MASK) && (service_subfunction == 0x06))) { + if (size == ((UI_8) 2 + SECURITY_KEY_SIZE)) { + /* ECU is sending the security key */ + UdsSecurityTaskCheckKey(service_subfunction, &buf_data_rx[2]); + } else { + request_size_ok = FALSE; + } + } else if ((service_subfunction == 0x02) || (service_subfunction == 0x06)) { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } +#else +#ifndef ISO15765_3_GEELY + if(service_subfunction == 0x04) + { + /* We don't know the valid subfunctions, go directly to the FSM. */ + if (size >= ((UI_8) 2 + SECURITY_KEY_SIZE)) { + /* ECU is sending the security key */ + //UdsSecurityTaskCheckKey(service_subfunction, &buf_data_rx[2]); + } else { + request_size_ok = FALSE; + } + }else{ + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } +#else + /* In Geely the sessions are checked before checking the length */ + switch (service_subfunction) { + case 0x12: + if (current_session_mask == UDS_PROGRAMMING_SESSION_MASK) { + if (size == ((UI_8) 2 + SECURITY_KEY_SIZE)) { + /* ECU is sending the security key */ + UdsSecurityTaskCheckKey(service_subfunction, &buf_data_rx[2]); + } else { + request_size_ok = FALSE; + } + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; + case 0x02: + if (current_session_mask == UDS_EXT_DIAG_SESSION_MASK) { + if (size == ((UI_8) 2 + SECURITY_KEY_SIZE)) { + /* ECU is sending the security key */ + UdsSecurityTaskCheckKey(service_subfunction, &buf_data_rx[2]); + } else { + request_size_ok = FALSE; + } + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; + case 0x62: + if (current_session_mask == UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) { + if (size == ((UI_8) 2 + SECURITY_KEY_SIZE)) { + /* ECU is sending the security key */ + UdsSecurityTaskCheckKey(service_subfunction, &buf_data_rx[2]); + } else { + request_size_ok = FALSE; + } + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; + default: + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + break; + } + +#endif +#endif + } +#ifndef ISO15765_3_GEELY + } else if ((size >= (UI_8) 2) && (Iso15765_3QueryRequestMode() != ISO15765_3_PHY_REQUEST)) { + request_size_ok = TRUE; + /* Service not supported in functional addressing */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); + } else { + /* Wrong size */ + request_size_ok = FALSE; + } +#else + /* In Geely we must answer service not supported in functional, even before + checking the number of paramters */ + } else if (Iso15765_3QueryRequestMode() != ISO15765_3_PHY_REQUEST) { + /* Service not supported in functional addressing */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); + } else { + if (size >= (UI_8) 2) { + request_size_ok = TRUE; + } else { + /* Wrong size */ + request_size_ok = FALSE; + } + } +#endif + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_TESTER_PRESENT + case UDS_TESTER_PRESENT: + if ((current_session_mask & UDS_SERVICE_TESTER_PRESENT) != 0x00) { + if ((size == (UI_8) 2) && (service_subfunction == (UI_8) 0x00)) { + tp_uds_tester_present_resp resp; + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Send Tester Present Echo */ + resp = ISO15765_3_GET_RESP_DATA(tp_uds_tester_present_resp); + resp->zero = (UI_8) 0; + Iso15765_3IncrementResponseSize(1); + Iso15765_3SendResponse(ISO15765_3_POSITIVE_RESPONSE); + request_size_ok = TRUE; + } else if ((size >= (UI_8) 2) && (service_subfunction != (UI_8) 0x00)) { + /* According to ISO 14229, other subfunctions */ + /* different to 0 are reserved */ + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_CONTROL_DTC_SETTING + case UDS_CONTROL_DTC_SETTING: + if ((current_session_mask & UDS_SERVICE_CONTROL_DTC_SETTING) != 0x00) { + if (size >= (UI_8) 2) { + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Call service routine */ + UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK( + service_subfunction, + (UI_8*) (&buf_data_rx[(UI_8) 2]), + (size - 2)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_READ_DATA_BY_IDENTIFIER + case UDS_READ_DATA_BY_IDENTIFIER: + if ((current_session_mask & UDS_SERVICE_READ_DATA_BY_IDENTIFIER) != 0x00) { + if (size == (UI_8) 3) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + response_mode = UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK( + (UI_8) buf_data_rx[1], + (UI_8) buf_data_rx[2]); + Iso15765_3SendResponse(response_mode); + request_size_ok = TRUE; + }/* multi-parameters */ + else if ((size >= (UI_16) 5) && ((size % (UI_16) 2) == (UI_16) 1)) { + aux_index = 1; + while ((aux_index < size)&&(response_mode != UDS_ERR_BUSY_REPEAT_REQUEST)) { + response_mode_aux = UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK( + (UI_8) buf_data_rx[aux_index], + (UI_8) buf_data_rx[aux_index + (UI_16) 1]); + aux_index = aux_index + (UI_16) 2; + + /* If any of the RDIs is POSITIVE -> the answer will be positive*/ + if (response_mode_aux == ISO15765_3_POSITIVE_RESPONSE) { + response_mode = ISO15765_3_POSITIVE_RESPONSE; + }/* If any of the RDIs response is BUSY -> cancel the operation and send the BUSY response */ + else if (response_mode_aux == UDS_ERR_BUSY_REPEAT_REQUEST) { + response_mode = UDS_ERR_BUSY_REPEAT_REQUEST; + } + } + Iso15765_3SendResponse(response_mode); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_READ_MEMORY_BY_ADDRESS //NOT IMPLEMENTED YET + case UDS_READ_MEMORY_BY_ADDRESS: + if ((current_session_mask & UDS_SERVICE_READ_MEMORY_BY_ADDRESS) != 0x00) { + if (size >= (UI_8) 2) { + /* Get Parameter: Size in bytes of mem_addr */ + UI_8 mem_addr_len = buf_data_rx[1] & (UI_8) 0x0F; + /* Get Parameter: Size in bytes of mem_size */ + UI_8 mem_size_len = buf_data_rx[1] >> (UI_8) 0x04; + + if (size >= (mem_addr_len + mem_size_len + (UI_8) 2)) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK(mem_size_len, + mem_addr_len, + &buf_data_rx[(UI_8) 2], + &buf_data_rx[(UI_8) 2 + mem_addr_len]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER + case UDS_WRITE_DATA_BY_IDENTIFIER: + if ((current_session_mask & UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER) != 0x00) { + +#ifndef ISO15765_3_GEELY + /* In Geely we must discard first by functional and then by format */ + if (size < (UI_8) 2) { + request_size_ok = FALSE; + } else +#endif + if (Iso15765_3QueryRequestMode() == ISO15765_3_PHY_REQUEST) { +#ifndef ISO15765_3_GEELY + if (size >= (UI_8) 4) { +#else + /* For GEELY there is no need of data, as the security must be + checked before checking the format */ + if (size >= (UI_8) 3) { +#endif + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK( + (UI_8) buf_data_rx[1], + (UI_8) buf_data_rx[2], + (UI_8*)&(buf_data_rx[3]), + (UI_16) (size - 3)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { +#ifndef ISO15765_3_GEELY + /* This is a service without subfunction, according to that + * we should send a CONDITIONS NOT CORRECT if we are in + * functional addressing */ + Iso15765_3SendResponse(UDS_ERR_CONDITIONS_NOT_CORRECT); +#else + /* If we are in functional, we should not answer */ + request_size_ok = TRUE; + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); +#endif + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS + case UDS_WRITE_MEMORY_BY_ADDRESS: //NOT IMPLEMENTED YET + if ((current_session_mask & UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS) != 0x00) { + if (size >= (UI_8) 6) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_CALLBACK(buf_data_rx[(UI_8) 1], + &buf_data_rx[(UI_8) 2], + (size - 2)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION + case UDS_CLEAR_DIAGNOSTIC_INFORMATION: + if ((current_session_mask & UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION) != 0x00) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + if (size == (UI_8) 4) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK(buf_data_rx[(UI_8) 1], buf_data_rx[(UI_8) 2], buf_data_rx[(UI_8) 3]); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_READ_DTC_INFORMATION + case UDS_READ_DTC_INFORMATION: + if ((current_session_mask & UDS_SERVICE_READ_DTC_INFORMATION) != 0x00) { + if (size >= (UI_8) 2) { + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Call service routine */ + UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK(service_subfunction, + &buf_data_rx[(UI_8) 2], + (size - (UI_8) 2)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_IO_CTRL_BY_ID + case UDS_INPUT_OUTPUT_CONTROL_BY_ID: + if ((current_session_mask & UDS_SERVICE_IO_CTRL_BY_ID) != 0x00) { + + if (size >= (UI_8) 3) { + /* Leave positive-response-not-requested flag to FALSE */ + /* Call service routine */ + // UDS_SERVICE_IO_CTRL_BY_ID_CALLBACK(buf_data_rx[(UI_8) 1], + // buf_data_rx[(UI_8) 2], + // buf_data_rx[(UI_8) 3], + // (UI_8*) (&(buf_data_rx[(UI_8) 4])), + // (size - 3)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_ROUTINE_CONTROL + case UDS_CONTROL_ROUTINE: + if ((current_session_mask & UDS_SERVICE_ROUTINE_CONTROL) != 0x00) { +#ifndef ISO15765_3_GEELY + if (size > (UI_8) 1) { +#endif + if (Iso15765_3QueryRequestMode() == ISO15765_3_PHY_REQUEST) { +#ifdef ISO15765_3_GEELY + /* In Geely we must first discard functional addressing requests and + then discard by format */ + if (size > (UI_8) 1) { +#endif + if ((service_subfunction == UDS_CTRL_ROUTINE_START) || + (service_subfunction == UDS_CTRL_ROUTINE_STOP) || + (service_subfunction == UDS_CTRL_ROUTINE_RESULTS)) { + if (size >= (UI_8) 4) { + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Call service routine */ + UDS_SERVICE_ROUTINE_CONTROL_CALLBACK( + service_subfunction, + (UI_8) buf_data_rx[2], + (UI_8) buf_data_rx[3], + &(buf_data_rx[(UI_8) 4]), + (UI_16) (size - (UI_8) 4)); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } +#ifdef ISO15765_3_GEELY + } else { + request_size_ok = FALSE; + } +#endif + } else { + /* Not supported in functional addressing */ + request_size_ok = TRUE; + Iso15765_3SendResponse(UDS_ERR_SUBFUNCTION_NOT_SUPPORTED); + } +#ifndef ISO15765_3_GEELY + } else { + request_size_ok = FALSE; + } +#endif + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_COMMUNICATION_CONTROL + case UDS_COMMUNICATION_CONTROL: + if ((current_session_mask & UDS_SERVICE_COMMUNICATION_CONTROL) != 0x00) { + if (size > (UI_8) 1) { /* We can check the subfunction */ +#ifndef ISO15765_3_GEELY + if (size == (UI_8) 3) { +#endif + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + /* Call service routine */ +#ifndef ISO15765_3_GEELY + // UDS_COMMUNICATION_CONTROL_CALLBACK(service_subfunction, (UI_8) buf_data_rx[2]); +#else + UDS_COMMUNICATION_CONTROL_CALLBACK(service_subfunction, (UI_8) buf_data_rx[2], size); +#endif + request_size_ok = TRUE; +#ifndef ISO15765_3_GEELY + } else { + request_size_ok = FALSE; + } +#endif + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } + break; +#endif +#ifdef UDS_SERVICE_REQUEST_DOWNLOAD + case UDS_REQUEST_DOWNLOAD: +#ifdef ISO15765_3_GEELY + /* In Geely, this service is not allowed in functiona mode */ + if (iso15765_3_request_mode != ISO15765_3_FUN_REQUEST){ +#endif + if ((current_session_mask & UDS_SERVICE_REQUEST_DOWNLOAD) != 0x00) { + if (size >= (UI_8) 2) { + UI_8 mem_addr_len = buf_data_rx[2] & (UI_8) 0x0F; + UI_8 mem_size_len = buf_data_rx[2] >> (UI_8) 0x04; + if (size == (mem_addr_len + mem_size_len + (UI_8) 3)) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UdsRequestDownload(buf_data_rx[1], + buf_data_rx[2], + &(buf_data_rx[3]), + &(buf_data_rx[3 + mem_addr_len])); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } +#ifdef ISO15765_3_GEELY + } else { + /* In functional mode, the service is not supported */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); + } +#endif + break; +#endif +#ifdef UDS_SERVICE_TRANSFER_DATA + case UDS_TRANSFER_DATA: +#ifdef ISO15765_3_GEELY + /* In Geely, this service is not allowed in functiona mode */ + if (iso15765_3_request_mode != ISO15765_3_FUN_REQUEST){ +#endif + if ((current_session_mask & UDS_SERVICE_TRANSFER_DATA) != 0x00) { + if (size >= (UI_8) 3) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UdsTransferData(buf_data_rx[(UI_8) 1], + (size - (UI_8) 2), + &(buf_data_rx[(UI_8) 2])); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } +#ifdef ISO15765_3_GEELY + } else { + /* In functional mode, the service is not supported */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); + } +#endif + + break; +#endif +#ifdef UDS_SERVICE_REQUEST_TRANSFER_EXIT + case UDS_REQUEST_TRANSFER_EXIT: +#ifdef ISO15765_3_GEELY + /* In Geely, this service is not allowed in functiona mode */ + if (iso15765_3_request_mode != ISO15765_3_FUN_REQUEST){ +#endif + if ((current_session_mask & UDS_SERVICE_REQUEST_TRANSFER_EXIT) != 0x00) { + if (size >= (UI_8) 1) { + /* Leave positive-response-not-requested flag to FALSE*/ + /* Call service routine */ + UdsTransferExit((size - (UI_16) 1), + &(buf_data_rx[(UI_8) 1])); + request_size_ok = TRUE; + } else { + request_size_ok = FALSE; + } + } else { + /* Service not supported in current session */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION); + } +#ifdef ISO15765_3_GEELY + } else { + /* In functional mode, the service is not supported */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); + } +#endif + break; +#endif + default: +#ifndef UDS_EXTRA_SERVICES + /* Unknown service: Send negative response */ + /* Enviament de la resposta negativa */ + Iso15765_3SendResponse(UDS_ERR_SERVICE_NOT_SUPPORTED); +#else + /* Check positive-response-not-requested flag */ + SET_POS_RESP_SUPRESS_FLAG(iso15765_3_supress_pos_resp); + UDS_EXTRA_SERVICES_CALLBACK(iso15765_3_current_service, service_subfunction, buf_data_rx, size); +#endif + break; + + } + + /* Wrong format detected in request frame */ + if (request_size_ok == FALSE) { + /* Send Negative Response */ + Iso15765_3SendResponse(UDS_ERR_INVALID_FORMAT); + } else { + /* N/A */ + } +} + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'atencio al servei Diagnostic Session Control +| * Aquest servei s'utilitza per gestionar la sessio de diagnostic activa +| * La seva implementacio es obligatoria +| * S'ha d'enviar la resposta positiva abans que la nova sessio s'activi +| * Les diferents rutines i funcions del protocol ISO15765_· que es poden +| fer servir per implementar aquest servei son: +| Iso15765_3ChangeActiveSession(...) per canviar la sessio activa +| Iso15765_3QueryActiveSession() per consultar la sessio activa actual. +| Iso_15765_3QuerySecurityAccessStatus() per consultar el nivell de +| seguretat actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| session: Nova sessio que es vol que sigui la sessio activa +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#ifdef UDS_SERVICE_SESSION_CONTROL + +void UDServiceSessionCtrl(UI_8 session, UI_8 size) { + UI_8 response_mode; + tp_uds_diagnostic_session_control_resp resp; + + /* Obtenim la variable que ens dona acces */ + /* als camps de dades de la resposta */ + resp = ISO15765_3_GET_RESP_DATA(tp_uds_diagnostic_session_control_resp); + +#ifdef UDS_USER_DEFINED_SESSION + if ((session == UDS_DEFAULT_SESSION) || + (session == UDS_EXT_DIAG_SESSION) || + (session == UDS_PROGRAMMING_SESSION) || + (session == UDS_USER_DEFINED_SESSION)) { +#else + if ((session == UDS_DEFAULT_SESSION) || + (session == UDS_EXT_DIAG_SESSION) || + (session == UDS_PROGRAMMING_SESSION)) { +#endif + if (size == 2) { + /* Prepare Response */ + resp->diagnostic_session = session; + resp->p2_high = (UI_8) (P2_MAX >> ((UI_8) 8)); + resp->p2_low = (UI_8) (P2_MAX); + resp->p2_ext_high = (UI_8) (P2_EXT_MAX >> ((UI_8) 8)); + resp->p2_ext_low = (UI_8) (P2_EXT_MAX); + Iso15765_3IncrementResponseSize(5); +#if (ISO_3_MODE == ISO15765_3_BL) +#ifdef UDS_READ_APP_VALID + if ((session == UDS_DEFAULT_SESSION) && (UDS_READ_APP_VALID() == TRUE)) { + /* IRIS_031_330AI_S3_005432: Do not respond positive response */ + /* until we are sure that the application is running */ + response_mode = UDS_ERR_RESPONSE_PENDING; +#ifdef UDS_INI_DEFAULT_SESSION_FROM_BOOTLOADER + /* Indicate to the application that it must respond the ACK */ + UDS_INI_DEFAULT_SESSION_FROM_BOOTLOADER(); +#endif +#else + if (FALSE) { + /* Always positive response if not defined UDS_READ_APP_VALID */ +#endif + } else { + response_mode = ISO15765_3_POSITIVE_RESPONSE; + } +#else + response_mode = ISO15765_3_POSITIVE_RESPONSE; +#endif + + /* Inform the state machine about the request */ + Iso15765_3ChangeActiveSession(session); + } else { + response_mode = UDS_ERR_INVALID_FORMAT; + } + } else { + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + +#if (ISO_3_MODE == ISO15765_3_BL) + /* Send the answer to the request */ + Iso15765_3SendResponse(response_mode); +#else + if ((response_mode == ISO15765_3_POSITIVE_RESPONSE) && (session == UDS_PROGRAMMING_SESSION)) { + Iso15765_3SendResponse(UDS_ERR_RESPONSE_PENDING); + } else { + /* Send the answer to the request */ + Iso15765_3SendResponse(response_mode); + } +#endif +} /* UDServiceSessionCtrl */ + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Routine to force the system to enter in PROGRAMMING SESSION. +| * This is used when changing from default to programming session (in most +| * of the cases this implies a reset). +| * This allows to send the response from the correct session. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| session: Nova sessio que es vol que sigui la sessio activa +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? CPU cycles | O(n): CTE +| Tmax Int En : ? CPU cycles | O(n): CTE +| Tmax Total : ? CPU cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void Iso15765_3_ForceSessionChange(UI_8 session, BOOL supress_positive_response) { + /* Call directly the diagnostic UDS service with the requested programming session */ + + /* Set the type of the request */ + iso15765_3_request_mode = ISO15765_3_PHY_REQUEST; + /* Set the current service ID */ + iso15765_3_current_service = UDS_DIAGNOSTIC_SESSION_CONTROL; + /* Positive response supression flag */ + iso15765_3_supress_pos_resp = supress_positive_response; + /* Force the response */ + force_response = 0x10; + + UDServiceSessionCtrl(session, 2); +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif + + +} + +#endif + +/***************************************************************************** +| Portability: Generica +|---------------------------------------------------------------------------- +| Description: +| * Routine that check if a response has been sent. This routine must be +| called after sending a response to check when this response has been +| sent. +|--------------------------------------------------------------------------- +| Arguments: +| * return TRUE if the response has been sent or if a TX problem has been +| detected. Return FALSE if the response is still pending to be sent. +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL Iso15765_3GetResponseSent(void) { + BOOL response_sent; + //t_iso15765_3_req_mode result; + + // result = Iso15765_3QueryRequestMode(); + /* Check if the response has been sent */ + if ((pending_response == FALSE) && + ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF))) { + response_sent = TRUE; + } else { + response_sent = FALSE; + } + + return response_sent; +} + + +/***************************************************************************** +| Portability: DZ60 +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'atencio al servei Request Download +| * Aquest servei s'utilitza per indicar i configurar l'inici d'una +| transferencia de dades de l'eina de verificacio cap a l'ECU +| * Les diferents rutines i funcions del protocol Iso15765_3 que es poden +| fer servir per implementar aquest servei son: +| Iso15765_3QueryActiveSession() per consultar la sessio activa actual. +| Iso15765_3QuerySecurityAccessStatus() per consultar el nivell de seguretat +| actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| data_format: bit [7..4]: Compression method. +| bit [3..0]: Encrypting method. +| The value 0x00 specifies no compression nor encrypting is used. +| addr_len_format: bit [7..4]: Length in bytes of the mem_size parameter +| bit [3..0]: Length in bytes of the mem_addr parameter +| mem_addr: adreça de memoria on comença el buffer que s'ha d'omplir +| mem_size: numero de bytes que s'han de transferir. +/---------------------------------------------------------------------------*/ +#ifdef UDS_SERVICE_REQUEST_DOWNLOAD + +static void UdsRequestDownload(UI_8 data_format, UI_8 addr_len_format, + UI_8 *mem_addr, UI_8 *mem_size) { + UI_8 response_mode; + tp_uds_request_download resp; + /* Temporal Working Register */ + UI_32 work_reg; + BOOL dev_ready = FALSE; + + asm("debug_request_download:"); + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_request_download); + /* By default, set negative response */ + response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* Programming session? */ + if (Iso15765_3QueryActiveSession() != UDS_DEFAULT_SESSION) { + /* security level ok */ + if (UdsSecurityTaskQueryAccessStatus() > UDS_ECU_LOCKED) { + /* Comprovem que no estiguem ja en proces de download */ + if (download_control.download_status != DOWNLOAD_STATUS_ONGOING) { + /* download process initialization */ + download_control.download_compression = (UI_8) (data_format >> (UI_8) 4); + download_control.download_encrypting = (UI_8) (data_format & (UI_8) 0x0F); + + /* Comprovacio dels metodes de compressio i encriptacio */ + if ((download_control.download_compression == COMPRESSION_METHOD_NONE) && + (download_control.download_encrypting == ENCRYPTING_METHOD_NONE)) { + + /* Parse Address and Size parameters Length */ + UI_8 mem_addr_len = addr_len_format & (UI_8) 0x0F; + UI_8 mem_size_len = addr_len_format >> (UI_8) 0x04; + UI_8 i; + + /* Cas en que la mida dels parametres mem_addr i */ + /* mem_size es correcte */ + /* multidevice extended address (5 bytes) */ + if ((mem_addr_len <= (UI_8) 5) && (mem_addr_len > (UI_8) 0) && + (mem_size_len <= (UI_8) 4) && (mem_size_len > (UI_8) 0)) { + if (mem_addr_len >= ISO15765_3_MIN_ADDRESS_LENGTH_MULTIDEVICE) { + /* mem_adr[0] is the device selection byte */ + download_control.device_addressed = mem_addr[0]; + } else { + /* If the memory address is 2 bytes or less we + consider that we can only have one device. */ + download_control.device_addressed = DEVICE_0; + } +#ifdef UDS_REQUEST_DOWNLOAD_DEVICE_READY + dev_ready = UDS_REQUEST_DOWNLOAD_DEVICE_READY(download_control.device_addressed); +#else + dev_ready = TRUE; +#endif + if (dev_ready == TRUE) { + /* Parse base address (starts at byte 1) */ + if (mem_addr_len >= ISO15765_3_MIN_ADDRESS_LENGTH_MULTIDEVICE) { + work_reg = mem_addr[1]; + for (i = 2; i < mem_addr_len; i++) { + work_reg <<= (UI_8) 8; + work_reg |= mem_addr[i]; + } + + }/* For addresses with less than ISO15765_3_MIN_ADDRESS_LENGTH_MULTIDEVICE + * bytes we must count the + * addres from position 0 */ + else { + work_reg = mem_addr[0]; + for (i = 1; i < mem_addr_len; i++) { + work_reg <<= (UI_8) 8; + work_reg |= mem_addr[i]; + } + } + + download_control.base_addr = (t_iso3_addr) work_reg; + + + /* Parse Total Download Size */ + work_reg = mem_size[0]; + for (i = 1; i < mem_size_len; i++) { + work_reg <<= (UI_8) 8; + work_reg |= mem_size[i]; + } + download_control.last_addr = download_control.base_addr + + (t_iso3_addr) work_reg - (t_iso3_addr) 1; + /* Prepare Response Buffer in case the response is ok */ + +#if (ISO15765_3_VARIANT == ISO15765_3_FIAT) + /* IT SEEMS THAT DIANALYZER HAS A BUG!!! */ + resp->len_format_id = 0x20; +#else + resp->len_format_id = 0; +#endif + + /* Set Maximum Size for a Tranfer Request */ + resp->max_num_of_block_len[0] = (UI_8) (MAX_BLOCK_LENGTH >> (UI_8) 8); + resp->max_num_of_block_len[1] = (UI_8) MAX_BLOCK_LENGTH; + Iso15765_3IncrementResponseSize(3); + + /* Download Status Variables Init */ + download_control.dest_addr = download_control.base_addr; + download_control.block_seq = 1; + + /* Callback to the correct device */ + switch (download_control.device_addressed) { +#ifdef DEVICE_0_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_0: + response_mode = DEVICE_0_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif +#ifdef DEVICE_1_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_1: + response_mode = DEVICE_1_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif +#ifdef DEVICE_2_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_2: + response_mode = DEVICE_2_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif +#ifdef DEVICE_3_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_3: + response_mode = DEVICE_3_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif +#ifdef DEVICE_4_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_4: + response_mode = DEVICE_4_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif +#ifdef DEVICE_5_REQUEST_DOWNLOAD_CALLBACK + case DEVICE_5: + response_mode = DEVICE_5_REQUEST_DOWNLOAD_CALLBACK( + download_control.base_addr, download_control.last_addr); + break; +#endif + default: +#ifdef UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK + response_mode = UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK(UDS_REQUEST_DOWNLOAD_ERROR_INVALID_DEVICE); + if (response_mode == 0xFF) { + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; + } +#else + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; +#endif + break; + } + if ((response_mode == ISO15765_3_POSITIVE_RESPONSE) || (response_mode == UDS_ERR_RESPONSE_PENDING)) { + download_control.download_status = DOWNLOAD_STATUS_ONGOING; + } + } else { + response_mode = UDS_ERR_BUSY_REPEAT_REQUEST; + } + } else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } /* end if/else check max length addr and size */ + } else { +#ifdef UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK + response_mode = UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK(UDS_REQUEST_DOWNLOAD_ERROR_INCOMPATIBLE_TYPE); + if (response_mode == 0xFF) { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } +#else + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; +#endif + } /* end if/else download methodes checking */ + } else { + /* Download already on going. This request is a sequence error */ + response_mode = UDS_ERR_REQUEST_SEQUENCE_ERROR; + } /* end if/else state process */ + } else { +#ifdef UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK + response_mode = UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK(UDS_REQUEST_DOWNLOAD_ERROR_ECU_LOCKED); + if (response_mode == 0xFF) { + response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; + } +#else + response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; +#endif + } + } else { + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } /* end if/else comprovacio sessio */ + + Iso15765_3SendResponse(response_mode); +} /* UdsRequestDownload */ +#endif + +/***************************************************************************** +| Portability: DZ60 +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'atencio al servei Transfer Data +| * Aquest servei s'utilitza per transferencia de dades. +| * Es pot enviar resposta negativa UDS_ERR_RESPONSE_PENDING per mantenir +| el contingut del buffer de dades si s'ha configurat el parametre +| NP_TX_RX_OFFSET amb valor major o igual a 3 +| * Les diferents rutines i funcions del protocolIso15765_3 que es poden +| fer servir per implementar aquest servei son: +| Iso15765_3QueryActiveSession() per consultar la sessio activa actual. +| Iso15765_3QuerySecurityAccessStatus() per consultar el nivell de seguretat +| actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| block_seq: Numero de sequencia de TranferData desde el Up/DownLoad Request +| começa per 0x01 i al arribar a 0xFF continua per 0x00 +| size: Mida del buffer de dades +| data: Buffer de dades +/---------------------------------------------------------------------------*/ +#ifdef UDS_SERVICE_TRANSFER_DATA + +static void UdsTransferData(UI_8 block_seq, UI_16 size, UI_8 *data_buf) { + UI_8 response_mode; + tp_uds_transfer_data resp; + t_iso3_addr transfer_end_addr; + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_transfer_data); + response_mode = ISO15765_3_POSITIVE_RESPONSE; + + /* Programming session */ + if (Iso15765_3QueryActiveSession() != UDS_DEFAULT_SESSION) { + + /* Comprovem que estiguem en proces de download */ + if (download_control.download_status == DOWNLOAD_STATUS_ONGOING) { + + /* We assume here. We are always doing downloads: PC -> ECU */ + /* Get the Response frame ready */ + resp->block_seq = block_seq; + Iso15765_3IncrementResponseSize(1); + + /* Comprovacio de la mida del bloc */ + transfer_end_addr = download_control.dest_addr + + (t_iso3_addr) size - (t_iso3_addr) 1; + if ((size <= MAX_BLOCK_LENGTH) && + (transfer_end_addr <= download_control.last_addr)) { + + /* Comprovacio de block sequence */ + if (download_control.block_seq == block_seq) { + /* Keep the size of the data buffer being processed */ + download_control.block_size = size; + download_control.block_ptr = (t_iso3_addr) (* data_buf); + + /* Callback to the correct device */ + switch (download_control.device_addressed) { +#ifdef DEVICE_0_TRANSFER_DATA_CALLBACK + case DEVICE_0: + response_mode = DEVICE_0_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif +#ifdef DEVICE_1_TRANSFER_DATA_CALLBACK + case DEVICE_1: + response_mode = DEVICE_1_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif +#ifdef DEVICE_2_TRANSFER_DATA_CALLBACK + case DEVICE_2: + response_mode = DEVICE_2_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif +#ifdef DEVICE_3_TRANSFER_DATA_CALLBACK + case DEVICE_3: + response_mode = DEVICE_3_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif +#ifdef DEVICE_4_TRANSFER_DATA_CALLBACK + case DEVICE_4: + response_mode = DEVICE_4_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif +#ifdef DEVICE_5_TRANSFER_DATA_CALLBACK + case DEVICE_5: + response_mode = DEVICE_5_TRANSFER_DATA_CALLBACK(data_buf, size); + break; +#endif + default: + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; + break; + } + /* Check if the transfer data wants to abort download */ + if (response_mode == UDS_ERR_TRANSFER_SUSPENDED) { + download_control.download_status = DOWNLOAD_STATUS_FINISHED_NOK; + } else { + /* N/A */ + } + } else { +#ifdef UDS_TRANSFER_DATA_ERROR_CALLBACK + response_mode = UDS_TRANSFER_DATA_ERROR_CALLBACK(UDS_TRANSFER_DATA_ERROR_INVALID_BLOCK); + if (response_mode == 0xFF) { + response_mode = UDS_ERR_WRONG_BLOCK_SEQUENCE; + } +#else + response_mode = UDS_ERR_WRONG_BLOCK_SEQUENCE; +#endif + + } /* end if/else block_seq */ + } else { +#ifdef UDS_TRANSFER_DATA_ERROR_CALLBACK + response_mode = UDS_TRANSFER_DATA_ERROR_CALLBACK(UDS_TRANSFER_DATA_ERROR_OUT_OF_RANGE); + if (response_mode == 0xFF) { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } +#else + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; +#endif + } /* end if/else size check */ + } else { + /* Download sequence error */ + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; + } /* end if/else status check */ + } else { + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } /* end if/else session check */ + + Iso15765_3SendResponse(response_mode); + +} /* UdsTransferData */ +#endif + + +/***************************************************************************** +| Portability: DZ60 +|---------------------------------------------------------------------------- +| Functionalities Contract Description: +| * Rutina d'atencio al servei Request Transfer Exit +| * Aquest servei s'utilitza per indicar el final d'una transferencia de +| dades. +| * Es pot enviar resposta negativa UDS_ERR_RESPONSE_PENDING per mantenir +| el contingut del buffer de dades si s'ha configurat el parametre +| NO_TX_RX_OFFSET amb valor major o igual a 2 +| * Les diferents rutines i funcions del modul protocolIso15765_3 que es +| poden fer servir per implementar aquest servei son: +| Iso15765_3QueryActiveSession() per consultar la sessio activa actual. +| Iso15765_3QuerySecurityAccessStatus() per consultar el nivell de +| seguretat actual. +|--------------------------------------------------------------------------- +| Parameters Explanation: +| size: Mida del buffer de dades +| data_buf: Buffer de dades +/---------------------------------------------------------------------------*/ +#ifdef UDS_SERVICE_REQUEST_TRANSFER_EXIT + +static void UdsTransferExit(UI_16 size, UI_8 *data_buf) { + UI_8 response_mode; + + /* By default set negative response */ + response_mode = ISO15765_3_POSITIVE_RESPONSE; + + /* Comprovem si estem en sessio de programacio */ + if (Iso15765_3QueryActiveSession() != UDS_DEFAULT_SESSION) { + if (Iso15765_3QueryRequestMode() == ISO15765_3_PHY_REQUEST) { + /* Comprovem que estiguem en proces de download */ + if (download_control.download_status == DOWNLOAD_STATUS_ONGOING) { + + switch (download_control.device_addressed) { +#ifdef DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_0: + response_mode = DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif +#ifdef DEVICE_1_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_1: + response_mode = DEVICE_1_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif +#ifdef DEVICE_2_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_2: + response_mode = DEVICE_2_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif +#ifdef DEVICE_3_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_3: + response_mode = DEVICE_3_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif +#ifdef DEVICE_4_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_4: + response_mode = DEVICE_4_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif +#ifdef DEVICE_5_REQUEST_TRANSFER_EXIT_CALLBACK + case DEVICE_5: + response_mode = DEVICE_5_REQUEST_TRANSFER_EXIT_CALLBACK( + data_buf, size); + break; +#endif + default: + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; + break; + } + /* callback function examines whether the download process + has finished or not by looking at if + download_offset >= download_size */ + if (response_mode == ISO15765_3_POSITIVE_RESPONSE) { + download_control.download_status = DOWNLOAD_STATUS_FINISHED_OK; + } else { + download_control.download_status = DOWNLOAD_STATUS_FINISHED_NOK; + } + } else { + /* Download Sequence Error */ + response_mode = UDS_ERR_REQUEST_SEQUENCE_ERROR; + } /* end if/else process status */ + } else { + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; + } + } else { + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } /* end if/else sessio status */ + + /* Respones Sending */ + Iso15765_3SendResponse(response_mode); +} /* UdsRequestTransferExit */ +#endif + + +/************************************************ + Security failed attempts counter section + * This section implements the security failed attempts counter + * structured data type, including its actions and accessors. + */ + +UI_8 security_failed_attempts = 0; /*!< The internal counter */ + +/** + * Initialize the security attempts counter. + * - When no NVM support, equals to zero. + * - When NVM support, call the callback function to load the data in NVM. + */ +void Iso15765_3SecurityAttemptsInitialize(void) { +#ifdef UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK + security_failed_attempts = UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK(); + if (security_failed_attempts >= MAX_SECURITY_ATTEMPTS) { + security_failed_attempts = MAX_SECURITY_ATTEMPTS; + } +#else + security_failed_attempts = (UI_8) 0; +#endif +} + +/** + * Clears the counter. + * If NVM support, execute the callback to store the new value in NVM. + */ +void Iso15765_3SecurityAttemptsClear(void) { + if (security_failed_attempts != (UI_8) 0) { + security_failed_attempts = 0; +#ifdef UDS_SECURITY_COUNTER_NVM_CALLBACK + // UDS_SECURITY_COUNTER_NVM_CALLBACK(&security_failed_attempts); +#endif + } +} + +/** + * Increments the counter. + * If NVM support, execute the callback to store the new value in NVM. + */ +void Iso15765_3SecurityAttemptsIncrement(void) { + if (security_failed_attempts < MAX_SECURITY_ATTEMPTS) { + if ((security_failed_attempts + (UI_8) 1) >= MAX_SECURITY_ATTEMPTS) { + security_failed_attempts = MAX_SECURITY_ATTEMPTS; + } else { + security_failed_attempts += (UI_8) 1; + } +#ifdef UDS_SECURITY_COUNTER_NVM_CALLBACK + // UDS_SECURITY_COUNTER_NVM_CALLBACK(&security_failed_attempts); +#endif + } +} + +/** + * Decrements the counter. + * If NVM support, execute the callback to store the new value in NVM. + */ +void Iso15765_3SecurityAttemptsDecrement(void) { + if (security_failed_attempts > (UI_8) 0) { + if (security_failed_attempts <= (UI_8) 1) { + security_failed_attempts = (UI_8) 0; + } else { + security_failed_attempts -= (UI_8) 1; + } +#ifdef UDS_SECURITY_COUNTER_NVM_CALLBACK + // UDS_SECURITY_COUNTER_NVM_CALLBACK(&security_failed_attempts); +#endif + } +} + +/** + * Checks if the maximum number of attempts has been reached. + */ +BOOL Iso15765_3SecurityAttemptsExceeded(void) { + BOOL ret = FALSE; + if (security_failed_attempts >= MAX_SECURITY_ATTEMPTS) { + ret = TRUE; + } + return ret; +} + +/** + * Function to determine if the allowed attempts have been reached (about to be exceeded on next try) + */ +/* +BOOL Iso15765_3SecurityAttemptsReached(void) { + BOOL ret = FALSE; + if (security_failed_attempts >= (MAX_SECURITY_ATTEMPTS-(UI_8)1)) { + ret = TRUE; + } + return ret; +} +*/ +/** + * Accessor for the counter value. + * @return the current value of the counter. + */ +UI_8 Iso15765_3SecurityAttemptsGet(void) { + UI_8 ret = 0xFF; + ret = security_failed_attempts; + return ret; +} +/** + * Determines if the consecutive seed request must be considered as failed attempts, + * depending on the UDS variant. + * @return TRUE if a consecutive seed request must increment the failed attempts counter. + */ +BOOL Iso15765_3VariantConsecutiveSeedIncrAttempt(void){ +#ifdef ISO15765_3_GAC + return TRUE; +#else +#ifdef ISO15765_3_GEELY + return TRUE; +#else + return FALSE; +#endif +#endif +} diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c new file mode 100644 index 0000000..a51c728 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.c @@ -0,0 +1,480 @@ + +/*------------------------------- includes --------------------------------*/ +//#include "Global.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h" + + +/*------------------------------ user code --------------------------------*/ + +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +#include "DiagnosticR/UDS/Iso15765_layer3/Iso15765_3_CFG.h" +#include "Iso15765_3.h" + +#define MAX_TIME_ACTION ((UI_16)10000) + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +typedef enum { + ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST = 1, + ESTAT_ISO15765_3_REQUESTRESPONDCTRL_REQUESTINPROGRES = 2, + ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING = 3, + ESTAT_ISO15765_3_REQUESTRESPONDCTRL_EXTTIMERESPOND = 4, + ESTAT_0_ISO15765_3_REQUESTRESPONDCTRL = 0 +} t_estat_iso15765_3_requestrespondctrl; + + +/*------------------------------ variables --------------------------------*/ + +/* Variables d estat */ +static t_estat_iso15765_3_requestrespondctrl estat_iso15765_3_requestrespondctrl = ESTAT_0_ISO15765_3_REQUESTRESPONDCTRL; + +/* Timers implicits */ +static t_clock temps_iso15765_3_requestrespondctrl = (t_clock)0; +static UI_8 p2extcounter = 0; +static BOOL response_sent = 0; + + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void Iso15765_3_RequestRespondCtrl0(void); +static void WaitingRequest(void); +static void RequestInProgres(void); +static void Responding(void); +static void ExtTimeRespond(void); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats Iso15765_3_RequestRespondCtrl +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +void Iso15765_3_RequestRespondCtrlInicialitza(void) +{ + /* Inicialitzacio de la variable d estat */ + estat_iso15765_3_requestrespondctrl = ESTAT_0_ISO15765_3_REQUESTRESPONDCTRL; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* Execucio del cicle inicial de la maquina d estats */ + Iso15765_3_RequestRespondCtrl(); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats Iso15765_3_RequestRespondCtrl. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +void Iso15765_3_RequestRespondCtrl(void) +{ + /* Estudi per casos del estat actual */ + switch (estat_iso15765_3_requestrespondctrl){ + case ESTAT_0_ISO15765_3_REQUESTRESPONDCTRL: + Iso15765_3_RequestRespondCtrl0(); + break; + case ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST: + WaitingRequest(); + break; + case ESTAT_ISO15765_3_REQUESTRESPONDCTRL_REQUESTINPROGRES: + RequestInProgres(); + break; + case ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING: + Responding(); + break; + case ESTAT_ISO15765_3_REQUESTRESPONDCTRL_EXTTIMERESPOND: + ExtTimeRespond(); + break; + default: + estat_iso15765_3_requestrespondctrl = ESTAT_0_ISO15765_3_REQUESTRESPONDCTRL; + break; + } + + /* Increment del temps de cicle al timer implicit */ + if (temps_iso15765_3_requestrespondctrl < MAX_COMPTADOR_TEMPS) { + temps_iso15765_3_requestrespondctrl += TimerDeltaCicleConsulta(); + } +} + + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces Iso15765_3_RequestRespondCtrl +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void Iso15765_3_RequestRespondCtrl0(void) +{ + /* Transicio per defecte */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* Canviem l estat inicial */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat WaitingRequest. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +static void WaitingRequest(void) +{ + if ((tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_IN_PRG)) { + /* Cas en que executem la transicio ReqInProgNotif1 */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_REQUESTINPROGRES; + } + else if ((tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF) || (tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF)) { + /* Cas en que executem la transicio ReqNotif1 */ + + /* -- action de la transicio -- */ + Iso15765_3Servicios(); + response_sent = FALSE; + + + /* -- entry de l estat Responding -- */ + if(tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } if(tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } + else if (temps_iso15765_3_requestrespondctrl >= TIMER_MS_TO_TICKS(S3_MAX)) { + /* Cas en que executem la transicio SessionExpired */ + + /* -- action de la transicio -- */ + session_expired = TRUE; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else if (force_response > (UI_8)0x00) { + /* Cas en que executem la transicio ForceResponse */ + + /* -- action de la transicio -- */ + tp_frm[DIAG_ISO15765_2_HDL].data_rx[0] = force_response; + iso15765_3_current_service = force_response; + iso15765_3_request_mode = ISO15765_3_PHY_REQUEST; + + tp_frm[DIAG_ISO15765_2_HDL].data_tx[0]= force_response + UDS_POS_RESP_CODE; + Iso15765_3IncrementResponseSize((UI_8)1); + force_response = (UI_8)0x00; + response_sent = FALSE; + + + /* -- entry de l estat Responding -- */ + if(tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } if(tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat RequestInProgres. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +static void RequestInProgres(void) +{ + if ((tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_ERR_NOTIF)) { + /* Cas en que executem la transicio RxError */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else if ((tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF)) { + /* Cas en que executem la transicio ReqNotif2 */ + + /* -- action de la transicio -- */ + Iso15765_3Servicios(); + response_sent = FALSE; + + + /* -- entry de l estat Responding -- */ + if(tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } if(tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } + else if (temps_iso15765_3_requestrespondctrl >= TIMER_MS_TO_TICKS(MAX_TIME_ACTION)) { + /* Cas en que executem la transicio UnknowProblem */ + + /* -- action de la transicio -- */ + Iso15765_3AbortResponse(); + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_REQUESTINPROGRES; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Responding. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +static void Responding(void) +{ + /* -- during de l estat actual -- */ + + if ((pending_response == TRUE) && (pending_response_mode != UDS_ERR_RESPONSE_PENDING) && + ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE))) { + Iso15765_3SendResponseSync(pending_response_mode); + response_sent = TRUE; + } + + + if (((Iso15765_3QueryRequestMode()==ISO15765_3_PHY_REQUEST) && (response_sent == TRUE) && ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF)))) { + /* Cas en que executem la transicio PhyRespondEnd */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else if ((pending_response == TRUE) && (pending_response_mode == UDS_ERR_RESPONSE_PENDING) && ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE))) { + /* Cas en que executem la transicio NegRespExtTime */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponseSync(pending_response_mode); + p2extcounter = 0; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_EXTTIMERESPOND; + } + else if (((Iso15765_3QueryRequestMode()==ISO15765_3_FUN_REQUEST) && (response_sent == TRUE) && ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF)) && (tp_frm[DIAG_ISO15765_2_HDL].sts_tx != TP_FRM_TX_REQ))) { + /* Cas en que executem la transicio FunRequestEnd */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else if ((tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_IN_PRG)) { + /* Cas en que executem la transicio RxInprogressWhilewaiting for TxConfirmation */ + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_REQUESTINPROGRES; + } + else if ((pending_response == FALSE) && ( (tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF) )) { + /* Cas en que executem la transicio RxOKWhileWaitingTxConfirmation */ + + /* -- action de la transicio -- */ + Iso15765_3Servicios(); + response_sent = FALSE; + + /* -- entry de l estat Responding -- */ + if(tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } if(tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } + else if (temps_iso15765_3_requestrespondctrl >= TIMER_MS_TO_TICKS(MAX_TIME_ACTION)) { + /* Cas en que executem la transicio UnknowProblem */ + + /* -- action de la transicio -- */ + Iso15765_3AbortResponse(); + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else if ((pending_response == FALSE) && (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF)) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + Iso15765_3AbortResponse(); + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat ExtTimeRespond. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| Sortides: +| estat_iso15765_3_requestrespondctrl +| temps_iso15765_3_requestrespondctrl +| tp_frm +| session_expired +****************************************************************************/ +static void ExtTimeRespond(void) +{ + if ((temps_iso15765_3_requestrespondctrl >= TIMER_MS_TO_TICKS(P2_EXT_MAX*10)) && + ((pending_response == FALSE) && ((tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_ERR_NOTIF) || (tp_frm[DIAG_ISO15765_2_HDL].sts_tx == TP_FRM_TX_IDLE)))) { + /* Cas en que executem la transicio TimerP2TimeOut */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponseSync(UDS_ERR_RESPONSE_PENDING); + p2extcounter++; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_EXTTIMERESPOND; + } + else if ((pending_response == TRUE) && (tp_frm[DIAG_ISO15765_2_HDL].sts_tx != TP_FRM_TX_REQ) && (pending_response_mode != UDS_ERR_RESPONSE_PENDING)) { + /* Cas en que executem la transicio FinalResponseAfterExtTime */ + + /* -- action de la transicio -- */ + response_sent = FALSE; + + /* -- entry de l estat Responding -- */ + if(tp_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } if(tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx == TP_FRM_RX_NOTIF){ tp_fun_frm[DIAG_ISO15765_2_HDL].sts_rx = TP_FRM_RX_IDLE; } + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_RESPONDING; + } + else if (p2extcounter > P2_EXT_MAX_COUNTER) { + /* Cas en que executem la transicio p2ExtTimesExhausted */ + + /* -- action de la transicio -- */ + Iso15765_3AbortResponse(); + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_requestrespondctrl= (t_clock)0; + + /* -- canviem l estat -- */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_WAITINGREQUEST; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_requestrespondctrl = ESTAT_ISO15765_3_REQUESTRESPONDCTRL_EXTTIMERESPOND; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.h b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.h new file mode 100644 index 0000000..eb34f3e --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_RequestRespondCtrl.h @@ -0,0 +1,8 @@ + +#ifndef ISO15765_3_REQUESTRESPONDCTRL_H_ +#define ISO15765_3_REQUESTRESPONDCTRL_H_ + +void Iso15765_3_RequestRespondCtrl(void); + + +#endif /* ISO15765_3_REQUESTRESPONDCTRL_H_ */ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SecurityTask.c b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SecurityTask.c new file mode 100644 index 0000000..e4e4eb7 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SecurityTask.c @@ -0,0 +1,805 @@ + +/*------------------------------- includes --------------------------------*/ +//#include "Global.h" +#include "Std_Types.h" +//#include "Timer.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" + +#include "Iso15765_3_Task.h" + +#include "Iso15765_3.h" +//#include "Iso15765_3_CFG.h" +#include "DiagnosticR/UDS/Iso15765_layer3/Iso15765_3_CFG.h" + +#define SECURED_DIAGNOSTICS_ENABLED ((UI_8)0x34) + +#define SEC_NO_REQUEST ((UI_8)0) +#define SEC_REQUEST_SEED ((UI_8)1) +#define SEC_CHECK_KEY ((UI_8)2) +#define SEC_SESSION_CHANGED ((UI_8)3) + +static UI_8 security_status = UDS_ECU_LOCKED; +static UI_8 force_unlock = UDS_ECU_LOCKED; +static UI_8 sec_request = SEC_NO_REQUEST; +static UI_8 key_type = 0; +static UI_8 seed_type = 0; +static BOOL key_ok = FALSE; +static BOOL consecutive_seed_requests = FALSE; + +/*------------------------------ user code --------------------------------*/ + + +UI_8 UdsSecurityTaskQueryAccessStatus(void) +{ + return security_status; +} + +BOOL UdsSecurityTaskQueryIfConsecutiveRequestSeed(void) +{ + return consecutive_seed_requests; +} + +static void SendZeroSeed(void) +{ + UI_8 i; + tp_uds_security_access_seed_resp resp; + + if (Iso15765_3QueryRequestSize() == (UI_16) 2) { +#ifdef ISO15765_3_GEELY + /* Check positive-response-not-requested flag, + * Suppress bit not supported in Geely */ + if (iso15765_3_supress_pos_resp == FALSE) { +#endif + resp = ISO15765_3_GET_RESP_DATA(tp_uds_security_access_seed_resp); + resp->access_mode = seed_type; + for (i = 0; i < SECURITY_SEED_SIZE; i++) { + resp->seed[i] = (UI_8) 0; + } + Iso15765_3IncrementResponseSize((UI_8) 1 + SECURITY_SEED_SIZE); + Iso15765_3SendResponse(ISO15765_3_POSITIVE_RESPONSE); +#ifdef ISO15765_3_GEELY + } else { + /* Check positive-response-not-requested flag, + * Suppress bit not supported in Geely */ + Iso15765_3SendResponse(UDS_ERR_REQUEST_OUT_OF_RANGE); + } +#endif + } else { + Iso15765_3SendResponse(UDS_ERR_INVALID_FORMAT); + } +} + +void UdsSecurityTaskRequestSeed(UI_8 level) +{ + /* Requesting seed */ + sec_request = SEC_REQUEST_SEED; + /* Save the level to match with the correct send key level */ + seed_type = level; + key_type = 0; +} + +void UdsSecurityTaskCheckKey(UI_8 level, UI_8* key) +{ + UI_8 i; + /* Send Key */ + sec_request = SEC_CHECK_KEY; + key_type = level; + for (i = 0; i < SECURITY_KEY_SIZE; i++) { + security_control.host_key[i] = key[i]; + } +} + +void UDSSecurityTaskNotifySessionChanged(void) +{ + sec_request = SEC_SESSION_CHANGED; +} + +void UdsSecurityTaskForceLockState(UI_8 state) +{ + force_unlock = state; + security_status = state; +} + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +typedef enum { + ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST = 1, + ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY = 2, + ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY = 3, + ESTAT_ISO15765_3_SECURITYTASK_UNLOCK = 4, + ESTAT_ISO15765_3_SECURITYTASK_CHECKKEY = 5, + ESTAT_ISO15765_3_SECURITYTASK_GETSEED = 6, + ESTAT_0_ISO15765_3_SECURITYTASK = 0 +} t_estat_iso15765_3_securitytask; + + +/*------------------------------ variables --------------------------------*/ + +/* Variables d estat */ +static t_estat_iso15765_3_securitytask estat_iso15765_3_securitytask = ESTAT_0_ISO15765_3_SECURITYTASK; + +/* Timers implicits */ +static t_clock temps_iso15765_3_securitytask = (t_clock) 0; +static UI_8 response = 0; + + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void Iso15765_3_SecurityTask0(void); +static void Wait_Seed_Request(void); +static void Penalty_Delay(void); +static void Wait_Tool_Key(void); +static void Unlock(void); +static void Checkkey(void); +static void GetSeed(void); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats Iso15765_3_SecurityTask +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +void Iso15765_3_SecurityTaskInicialitza(void) +{ + /* Inicialitzacio de la variable d estat */ + estat_iso15765_3_securitytask = ESTAT_0_ISO15765_3_SECURITYTASK; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* Execucio del cicle inicial de la maquina d estats */ + Iso15765_3_SecurityTask(); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats Iso15765_3_SecurityTask. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +void Iso15765_3_SecurityTask(void) +{ + /* Estudi per casos del estat actual */ + switch (estat_iso15765_3_securitytask) { + case ESTAT_0_ISO15765_3_SECURITYTASK: + Iso15765_3_SecurityTask0(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST: + Wait_Seed_Request(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY: + Penalty_Delay(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY: + Wait_Tool_Key(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_UNLOCK: + Unlock(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_CHECKKEY: + Checkkey(); + break; + case ESTAT_ISO15765_3_SECURITYTASK_GETSEED: + GetSeed(); + break; + default: + estat_iso15765_3_securitytask = ESTAT_0_ISO15765_3_SECURITYTASK; + break; + } + + /* Increment del temps de cicle al timer implicit */ + if (temps_iso15765_3_securitytask < MAX_COMPTADOR_TEMPS) { + temps_iso15765_3_securitytask += TimerDeltaCicleConsulta(); + } +} + + +/*------------------------- funcions d'estats -----------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces Iso15765_3_SecurityTask +|---------------------------------------------------------------------------- +| Interficie: - + ****************************************************************************/ +static void Iso15765_3_SecurityTask0(void) +{ + + if (SECURITY_INIT_DELAY == SECURITY_NO_DELAY) { + /* Avaluem condicio de start del estat Wait_Seed_Request */ + + /* -- action de la transicio inicial -- */ + seed_type = (UI_8) 0; + key_type = (UI_8) 0; + sec_request = SEC_NO_REQUEST; + Iso15765_3SecurityAttemptsInitialize(); + force_unlock = UDS_ECU_LOCKED; + + /* -- entry de l estat -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* Canviem l estat inicial */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if (SECURITY_INIT_DELAY == SECURITY_DELAY) { + /* Avaluem condicio de start del estat Penalty_Delay */ + + /* -- action de la transicio inicial -- */ + seed_type = (UI_8) 0; + key_type = (UI_8) 0; + sec_request = SEC_NO_REQUEST; + Iso15765_3SecurityAttemptsInitialize(); + + /* -- entry de l estat -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* Canviem l estat inicial */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY; + } else { + /* No s ha activat cap condicio inicial: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_0_ISO15765_3_SECURITYTASK; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Wait_Seed_Request. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void Wait_Seed_Request(void) +{ + /* -- during de l estat actual -- */ + + security_status = UDS_ECU_LOCKED; + + if ((Iso15765_3SecurityAttemptsExceeded() == FALSE) && (sec_request == SEC_CHECK_KEY)) { + /* Cas en que executem la transicio Asking_Key_Wrong_State */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(UDS_ERR_REQUEST_SEQUENCE_ERROR); + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((Iso15765_3SecurityAttemptsExceeded() == FALSE) && (sec_request == SEC_REQUEST_SEED)) { + /* Cas en que executem la transicio Seed request */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat GetSeed -- */ + consecutive_seed_requests = FALSE; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_GETSEED; + } else if ((Iso15765_3SecurityAttemptsExceeded() == FALSE) && sec_request == SEC_SESSION_CHANGED) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((Iso15765_3SecurityAttemptsExceeded() == FALSE) && force_unlock != UDS_ECU_LOCKED) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + security_status = seed_type; + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else if ((Iso15765_3SecurityAttemptsExceeded() == TRUE)) { + /* Cas en que executem la transicio */ + + /* -- entry de l estat Penalty_Delay -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Penalty_Delay. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void Penalty_Delay(void) +{ + /* -- during de l estat actual -- */ + + if (sec_request != SEC_NO_REQUEST) { + if (sec_request != SEC_SESSION_CHANGED) { + if (sec_request == SEC_REQUEST_SEED) { + Iso15765_3SendResponse(UDS_ERR_REQUIRED_TIME_DELAY_NOT_EXPIRED); + } else { + /* Send key received */ + Iso15765_3SendResponse(UDS_ERR_REQUEST_SEQUENCE_ERROR); + } + } + consecutive_seed_requests = FALSE; + sec_request = SEC_NO_REQUEST; + } + + + if (temps_iso15765_3_securitytask >= TIMER_MS_TO_TICKS(SECURITY_PENALTY_TIME)) { + /* Cas en que executem la transicio Penalty_Ended */ + + /* -- action de la transicio -- */ + Iso15765_3SecurityAttemptsDecrement(); + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Wait_Tool_Key. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void Wait_Tool_Key(void) +{ + if ((Iso15765_3VariantConsecutiveSeedIncrAttempt() == TRUE) && (sec_request == SEC_REQUEST_SEED) && (Iso15765_3SecurityAttemptsReached() == FALSE) && (sec_request != SEC_SESSION_CHANGED)) { + /* Cas en que executem la transicio Asking_Seed_Wrong_State */ + + /* -- action de la transicio -- */ + /* NRC does not apply, request seed to application again */ + /* Parameter signals consectutive */ + consecutive_seed_requests = TRUE; + response = UDS_SECURITY_REQUEST_SEED_CALLBACK(seed_type, security_control.local_seed); + Iso15765_3SecurityAttemptsIncrement(); + Iso15765_3SendResponse(response); + + /* -- entry de l estat Wait_Tool_Key -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY; + } else if (sec_request == SEC_SESSION_CHANGED) { + /* Cas en que executem la transicio Locked_due_to_session_change */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((sec_request == SEC_CHECK_KEY) && (Iso15765_3QueryRequestSize() >= ((UI_16) 2 + SECURITY_KEY_SIZE)) && (sec_request != SEC_SESSION_CHANGED)) { + /* Cas en que executem la transicio Key Received */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_CHECKKEY; + } else if ((sec_request == SEC_CHECK_KEY) && (Iso15765_3QueryRequestSize() < ((UI_16) 2 + SECURITY_KEY_SIZE)) && (sec_request != SEC_SESSION_CHANGED)) { + /* Cas en que executem la transicio Key Received with wrong size */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(UDS_ERR_INVALID_FORMAT); + + /* -- entry de l estat Wait_Tool_Key -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY; + } else if ((Iso15765_3VariantConsecutiveSeedIncrAttempt() == TRUE) && (sec_request == SEC_REQUEST_SEED) && (Iso15765_3SecurityAttemptsReached() == TRUE) && (sec_request != SEC_SESSION_CHANGED)) { + /* Cas en que executem la transicio AskingConsecutiveSeedCausesCounterToExceed */ + + /* -- action de la transicio -- */ + /* NRC does not apply, request seed to application again */ + /* Parameter signals consectutive */ + consecutive_seed_requests = TRUE; + Iso15765_3SecurityAttemptsIncrement(); + Iso15765_3SendResponse(UDS_ERR_REQUIRED_TIME_DELAY_NOT_EXPIRED); + + /* -- entry de l estat Penalty_Delay -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Unlock. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void Unlock(void) +{ + if (sec_request == SEC_SESSION_CHANGED) { + /* Cas en que executem la transicio Locked_due_to_session_change */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + force_unlock = UDS_ECU_LOCKED; + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((sec_request == SEC_REQUEST_SEED) && (seed_type == security_status)) { + /* Cas en que executem la transicio Seed_requested */ + + /* -- action de la transicio -- */ + SendZeroSeed(); + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else if ((sec_request == SEC_CHECK_KEY)) { + /* Cas en que executem la transicio Send Key Unlocked */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(UDS_ERR_REQUEST_SEQUENCE_ERROR); + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else if ((sec_request == SEC_REQUEST_SEED) && (seed_type != security_status)) { + /* Cas en que executem la transicio Another level required */ + + /* -- action de la transicio -- */ + sec_request = SEC_NO_REQUEST; + + /* -- entry de l estat GetSeed -- */ + consecutive_seed_requests = FALSE; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_GETSEED; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat Checkkey. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void Checkkey(void) +{ + /* -- codi de l estat actual -- */ + key_ok = UDS_SECURITY_CHECK_KEY_CALLBACK(key_type, security_control.local_seed, + security_control.host_key, &response); + + if ((key_ok == TRUE) && ((response == ISO15765_3_POSITIVE_RESPONSE) || (response == UDS_ERR_RESPONSE_PENDING))) { + /* Cas en que executem la transicio Key Valid */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(response); + sec_request = SEC_NO_REQUEST; + Iso15765_3SecurityAttemptsClear(); + security_status = seed_type; + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else if ((security_status == UDS_ECU_LOCKED) && (key_ok == FALSE) && (Iso15765_3SecurityAttemptsReached() == FALSE)) { + /* Cas en que executem la transicio Key Invalid && ECU locked */ + + /* -- action de la transicio -- */ + Iso15765_3SecurityAttemptsIncrement(); + Iso15765_3SendResponse(UDS_ERR_INVALID_KEY); + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((key_ok == FALSE) && (Iso15765_3SecurityAttemptsReached() == TRUE)) { + /* Cas en que executem la transicio Key Invalid, max attempts reached */ + + /* -- action de la transicio -- */ + Iso15765_3SecurityAttemptsIncrement(); + Iso15765_3SendResponse(UDS_ERR_EXCEEDED_NUMBER_OF_ATTEMPTS); + + /* -- entry de l estat Penalty_Delay -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_PENALTY_DELAY; + } else if ((response != ISO15765_3_POSITIVE_RESPONSE) && (response != UDS_ERR_INVALID_KEY) && (response != UDS_ERR_RESPONSE_PENDING) && (Iso15765_3SecurityAttemptsReached() == FALSE)) { + /* Cas en que executem la transicio Invalid key type */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(response); + + /* -- entry de l estat Wait_Tool_Key -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY; + } else if ((security_status != UDS_ECU_LOCKED) && (key_ok == FALSE) && (Iso15765_3SecurityAttemptsReached() == FALSE)) { + /* Cas en que executem la transicio Key failed && ecu unlocked */ + + /* -- action de la transicio -- */ + Iso15765_3SecurityAttemptsIncrement(); + Iso15765_3SendResponse(response); + sec_request = SEC_NO_REQUEST; + seed_type = security_status; + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_CHECKKEY; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat GetSeed. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| tool_key +| access_mode +| security_failed_attempts +| Sortides: +| estat_iso15765_3_securitytask +| temps_iso15765_3_securitytask +| local_seed +| security_failed_attempts + ****************************************************************************/ +static void GetSeed(void) +{ + /* -- during de l estat actual -- */ + + response = UDS_SECURITY_REQUEST_SEED_CALLBACK(seed_type, security_control.local_seed); + + if ((response == ISO15765_3_POSITIVE_RESPONSE) || (response == UDS_ERR_RESPONSE_PENDING)) { + /* Cas en que executem la transicio */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(response); + + /* -- entry de l estat Wait_Tool_Key -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_TOOL_KEY; + } else if ((response != ISO15765_3_POSITIVE_RESPONSE) && (response != UDS_ERR_RESPONSE_PENDING) && (security_status == UDS_ECU_LOCKED)) { + /* Cas en que executem la transicio Wrong seed type */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(response); + + /* -- entry de l estat Wait_Seed_Request -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_WAIT_SEED_REQUEST; + } else if ((response != ISO15765_3_POSITIVE_RESPONSE) && (response != UDS_ERR_RESPONSE_PENDING) && (security_status != UDS_ECU_LOCKED)) { + /* Cas en que executem la transicio Wrong seed access when unlocked */ + + /* -- action de la transicio -- */ + Iso15765_3SendResponse(response); + + /* -- entry de l estat Unlock -- */ + sec_request = SEC_NO_REQUEST; + + /* Inicialitzacio del timer implicit */ + temps_iso15765_3_securitytask = (t_clock) 0; + + /* -- canviem l estat -- */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_UNLOCK; + } else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_securitytask = ESTAT_ISO15765_3_SECURITYTASK_GETSEED; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c new file mode 100644 index 0000000..8294748 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_SessionCtrlTask.c @@ -0,0 +1,299 @@ + +/*------------------------------- includes --------------------------------*/ +//#include "Global.h" +#include "Std_Types.h" +//#include "Timer.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/Timer.h" +#include "Iso15765_3_Task.h" + +#include "Iso15765_3.h" + +#define SESSION_NO_REQUEST ((UI_8)0) +#define SESSION_DEFAULT ((UI_8)1) +#define SESSION_NOT_DEFAULT ((UI_8)2) + +BOOL session_expired; + +static UI_8 active_session; +static UI_8 active_session_mask; +static UI_8 session_request; + + +/*------------------------------ user code --------------------------------*/ + + +UI_8 Iso15765_3QueryActiveSessionMask(void) +{ +switch(active_session){ +case UDS_DEFAULT_SESSION: +active_session_mask = UDS_DEFAULT_SESSION_MASK; +break; +case UDS_PROGRAMMING_SESSION: +active_session_mask = UDS_PROGRAMMING_SESSION_MASK; +break; +case UDS_EXT_DIAG_SESSION: +active_session_mask = UDS_EXT_DIAG_SESSION_MASK; +break; +case UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID: +active_session_mask = UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK; +break; +default: +active_session_mask = 0x00;/* There is an error in the session control */ +break; +} + +return active_session_mask; +} + +void Iso15765_3ChangeActiveSession(UI_8 session_change) +{ + active_session = session_change; + if ((session_change & UDS_SUBFUNCTION_MASK) != UDS_DEFAULT_SESSION) + { + session_request = SESSION_NOT_DEFAULT; + } else + { + session_request = UDS_DEFAULT_SESSION; + } +} + +UI_8 Iso15765_3QueryActiveSession(void) +{ +return active_session; +} + +/*-------------------------------- macros ---------------------------------*/ + + + + + +/*------------------------------- defines ---------------------------------*/ +/* Maxim valor del compteig del temps */ +#define MAX_COMPTADOR_TEMPS ((UI_16)65000) + +/*---------------------------- tipus de dades -----------------------------*/ + +typedef enum { + ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION = 1, + ESTAT_ISO15765_3_SESSIONCTRLTASK_NONDEFAULTSESSION = 2, + ESTAT_0_ISO15765_3_SESSIONCTRLTASK = 0 +} t_estat_iso15765_3_sessionctrltask; + + +/*------------------------------ variables --------------------------------*/ + +/* Variables d estat */ +static t_estat_iso15765_3_sessionctrltask estat_iso15765_3_sessionctrltask = ESTAT_0_ISO15765_3_SESSIONCTRLTASK; + + +/*------------------------- capcaleres de funcions ------------------------*/ + +static void Iso15765_3_SessionCtrlTask0(void); +static void DefaultSession(void); +static void NonDefaultSession(void); + + +/*----------------------- funcions d'inicialitzacio -----------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Inicialitzacio del diagrama d estats Iso15765_3_SessionCtrlTask +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: - +| Sortides: +| estat_iso15765_3_sessionctrltask +| +****************************************************************************/ +void Iso15765_3_SessionCtrlTaskInicialitza(void) +{ + /* Inicialitzacio de la variable d estat */ + estat_iso15765_3_sessionctrltask = ESTAT_0_ISO15765_3_SESSIONCTRLTASK; + + /* Execucio del cicle inicial de la maquina d estats */ + Iso15765_3_SessionCtrlTask(); +} + + +/*------------------------- rutines principals ---------------------------*/ + +/**************************************************************************** +| Funcionalitat: +| Rutina principal del diagrama d estats Iso15765_3_SessionCtrlTask. +| Invoca a la funcio corresponent a l estat actual. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_sessionctrltask +| +| session_expired +| Sortides: +| estat_iso15765_3_sessionctrltask +| +****************************************************************************/ +void Iso15765_3_SessionCtrlTask(void) +{ + /* Estudi per casos del estat actual */ + switch (estat_iso15765_3_sessionctrltask){ + case ESTAT_0_ISO15765_3_SESSIONCTRLTASK: + Iso15765_3_SessionCtrlTask0(); + break; + case ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION: + DefaultSession(); + break; + case ESTAT_ISO15765_3_SESSIONCTRLTASK_NONDEFAULTSESSION: + NonDefaultSession(); + break; + default: + estat_iso15765_3_sessionctrltask = ESTAT_0_ISO15765_3_SESSIONCTRLTASK; + break; + } +} + + +/*------------------------- funcions d'estats -----------------------------*/ + + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat inicial del proces Iso15765_3_SessionCtrlTask +|---------------------------------------------------------------------------- +| Interficie: - +****************************************************************************/ +static void Iso15765_3_SessionCtrlTask0(void) +{ + /* Transicio per defecte */ + + /* -- entry de l estat -- */ + session_expired = FALSE; + session_request = SESSION_NO_REQUEST; + active_session = UDS_DEFAULT_SESSION; + /* User Callback: Session being Initialized */ +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + //UDSSecurityTaskNotifySessionChanged(); +#endif + + /* Canviem l estat inicial */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION; +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat DefaultSession. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_sessionctrltask +| +| session_expired +| Sortides: +| estat_iso15765_3_sessionctrltask +| +****************************************************************************/ +static void DefaultSession(void) +{ + if (session_request == SESSION_NOT_DEFAULT) { + /* Cas en que executem la transicio ChangeToNonDefSession */ + + /* -- entry de l estat NonDefaultSession -- */ + session_expired = FALSE; + session_request = SESSION_NO_REQUEST; + /* User Callback: Session being Initialized */ +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + //UDSSecurityTaskNotifySessionChanged(); +#endif + + /* -- canviem l estat -- */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_NONDEFAULTSESSION; + } + else if (session_request == SESSION_DEFAULT) { + /* Cas en que executem la transicio ReIniDefSession */ + + /* -- entry de l estat DefaultSession -- */ + session_expired = FALSE; + session_request = SESSION_NO_REQUEST; + active_session = UDS_DEFAULT_SESSION; + /* User Callback: Session being Initialized */ +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + //UDSSecurityTaskNotifySessionChanged(); +#endif + + /* -- canviem l estat -- */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION; + } +} + +/**************************************************************************** +| Funcionalitat: +| Funcio corresponent a l estat NonDefaultSession. +|---------------------------------------------------------------------------- +| Interficie: +| Entrades: +| estat_iso15765_3_sessionctrltask +| +| session_expired +| Sortides: +| estat_iso15765_3_sessionctrltask +| +****************************************************************************/ +static void NonDefaultSession(void) +{ + if ((session_expired == TRUE) || (session_request == SESSION_DEFAULT)) { + /* Cas en que executem la transicio ChangeToDefSession */ + + /* -- entry de l estat DefaultSession -- */ + session_expired = FALSE; + session_request = SESSION_NO_REQUEST; + active_session = UDS_DEFAULT_SESSION; + /* User Callback: Session being Initialized */ +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + //UDSSecurityTaskNotifySessionChanged(); +#endif + + /* -- canviem l estat -- */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_DEFAULTSESSION; + } + else if (session_request == SESSION_NOT_DEFAULT) { + /* Cas en que executem la transicio ChangeBetweenNonDefSessions */ + + /* -- entry de l estat NonDefaultSession -- */ + session_expired = FALSE; + session_request = SESSION_NO_REQUEST; + /* User Callback: Session being Initialized */ +#ifdef UDS_INI_SESSION_CALLBACK + UDS_INI_SESSION_CALLBACK(); +#endif +#ifdef UDS_SERVICE_SECURITY_ACCESS + //UDSSecurityTaskNotifySessionChanged(); +#endif + + /* -- canviem l estat -- */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_NONDEFAULTSESSION; + } + else { + + /* No s ha activat cap transicio: ens quedem a l estat actual */ + estat_iso15765_3_sessionctrltask = ESTAT_ISO15765_3_SESSIONCTRLTASK_NONDEFAULTSESSION; + } +} + + +/********************************** FI **************************************/ diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h new file mode 100644 index 0000000..654ecb4 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h @@ -0,0 +1,216 @@ + +#ifndef ISO15765_3_TASK_H_ +#define ISO15765_3_TASK_H_ + +/*----------------------------- Icludes ----------------------------------*/ + +//#include "Global.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" + +/*----------------------------- Defines ----------------------------------*/ + +#if(UDS_SERVICE_SECURITY_ACCESS_STATUS==SERVICE_ENABLED) +/* Security Control */ +#define SECURITY_DELAY ((UI_8)0) +#define SECURITY_NO_DELAY ((UI_8)1) +#endif + +/*----------------------------- Globals ----------------------------------*/ + +extern BOOL session_expired; + +/*-------------------------- Function Prototypes -------------------------*/ + +/* Response Control */ +void Iso15765_3_RequestRespondCtrlInicialitza(void); +void Iso15765_3_RequestRespondCtrl(void); +void SessionChangeRequest(UI_8 session_change); + +/* Session Control */ +#ifdef UDS_SERVICE_SESSION_CONTROL +void Iso15765_3_SessionCtrlTaskInicialitza(void); +void Iso15765_3_SessionCtrlTask(void); +void UDSSecuritySessionChanged(void); +#endif + +#ifdef UDS_SERVICE_ECU_RESET +void Iso15765_3_EcuResetTaskInicialitza(void); +void UDSResetRequest(UI_8 req_reset_type, UI_8 size); +#endif + +/* Security Access */ +#ifdef UDS_SERVICE_SECURITY_ACCESS +void Iso15765_3_SecurityTaskInicialitza(void); +void Iso15765_3_SecurityTask(void); +void UDSSecurityRequest(UI_8 req_acces_mode, UI_8* sec_buf); +void UDSSecuritySessionChanged(void); +void UdsSecurityTaskRequestSeed(UI_8 level); +void UdsSecurityTaskCheckKey(UI_8 level, UI_8* key); +void UDSSecurityTaskNotifySessionChanged(void); +void UdsSecurityTaskForceLockState(UI_8 state); +#endif + +/* Reset Control */ +#ifdef UDS_SERVICE_ECU_RESET +void Iso15765_3_SEcuResetTaskInicialitza(void); +void Iso15765_3_EcuResetTask(void); +void Iso15765_3_ResetRequest(UI_8 req_reset_type); +#endif + +/*---------------- Configurable LIN Services Prototypes -------------------*/ +#ifdef LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER +void LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK(UI_8 supplierID_LSB, UI_8 supplierID_MSB, UI_8 messageID_LSB, UI_8 messageID_MSB, UI_8 new_pid); +#endif + +#ifdef LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER_RANGE +void LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK(UI_8 index, const UI_8* new_pid_list); +#endif + +#ifdef LIN_SERVICE_READ_BY_IDENTIFIER +void LIN_READ_BY_IDENTIFIER_CALLBACK(UI_8 id); +#endif + +#ifdef LIN_SERVICE_ASSIGN_NAD +void LIN_ASSIGN_NAD_CALLBACK(UI_16 supplierId, UI_16 functionId, UI_8 new_nad); +#endif + +#ifdef LIN_SERVICE_CONDITIONAL_CHANGE_NAD +void LIN_CONDITIONAL_CHANGE_NAD_CALLBACK(UI_8 id, UI_8 byte, UI_8 mask, UI_8 invert, UI_8 new_nad); +#endif + +/*---------------- Configurable UDS Services Prototypes -------------------*/ + +#ifdef UDS_INI_SESSION_CALLBACK +void UDS_INI_SESSION_CALLBACK(void); +#endif + +#ifdef UDS_SERVICE_ECU_RESET +BOOL CHECK_RESET_POSSIBLE(UI_8 reset_type); +BOOL CHECK_RESET_TYPE(UI_8 reset_type); +void EXECUTE_RESET(UI_8 reset_type); +#endif + +#ifdef UDS_SERVICE_SECURITY_ACCESS +UI_8 UDS_SECURITY_REQUEST_SEED_CALLBACK(UI_8 seed_type, UI_8* p_local_seed); +BOOL UDS_SECURITY_CHECK_KEY_CALLBACK(UI_8 key_type, UI_8* p_local_seed, UI_8* p_tool_key, UI_8* response); +#endif + +#ifdef UDS_SERVICE_CONTROL_DTC_SETTING +void UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK(UI_8 dtc_setting_type, UI_8* buf_data_rx, UI_16 size); +#endif + +#ifdef UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION +void UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK(UI_8 groupOfDTCHighByte, UI_8 groupOfDTCMiddleByte, UI_8 groupOfDTCLowByte); +#endif + +#ifdef UDS_SERVICE_READ_DTC_INFORMATION +void UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK(UI_8 id, UI_8 *data, UI_16 size); +#endif + +#ifdef UDS_SERVICE_READ_MEMORY_BY_ADDRESS +void UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK(UI_8 mem_size_len, + UI_8 mem_addr_len, UI_8* mem_addr, UI_8* mem_size); +#endif + +#ifdef UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER +void UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK(UI_8 id_high, UI_8 id_low, UI_8* buf_data_rx, UI_16 size); +#endif + +#ifdef UDS_SERVICE_READ_DATA_BY_IDENTIFIER +UI_8 UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK(UI_8 id_high, UI_8 id_low); +#endif + +#ifdef UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS +void UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_CALLBACK(UI_8 data_len_format, + UI_8* p_buf, UI_16 size); +#endif + +#ifdef UDS_SERVICE_IO_CTRL_BY_ID +void UdsInputOutputControlByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 io_ctrl_type, UI_8* buf_data_rx, UI_16 size); +#endif + +#ifdef UDS_SERVICE_ROUTINE_CONTROL +void UDS_SERVICE_ROUTINE_CONTROL_CALLBACK(UI_8 routine_ctrl_type, UI_8 id_high, UI_8 id_low, UI_8 *routine_entry_option, UI_16 size); +#endif + +#ifdef UDS_SERVICE_COMMUNICATION_CONTROL +#ifndef ISO15765_3_GEELY +void UDS_COMMUNICATION_CONTROL_CALLBACK(UI_8 ctrl_type, UI_8 com_type); +#else +void UDS_COMMUNICATION_CONTROL_CALLBACK(UI_8 ctrl_type, UI_8 com_type, UI_8 size); +#endif +#endif + +#ifdef UDS_REQUEST_DOWNLOAD_DEVICE_READY +BOOL UDS_REQUEST_DOWNLOAD_DEVICE_READY(UI_8 dev); +#endif + +#ifdef UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK +UI_8 UDS_REQUEST_DOWNLOAD_ERROR_CALLBACK(UI_8 error_code); +#endif + +#ifdef DEVICE_0_REQUEST_DOWNLOAD_CALLBACK +UI_8 DEVICE_0_REQUEST_DOWNLOAD_CALLBACK(t_iso3_addr base_addr, t_iso3_addr last_addr); +#endif +#ifdef DEVICE_1_REQUEST_DOWNLOAD_CALLBACK +UI_8 DEVICE_1_REQUEST_DOWNLOAD_CALLBACK(t_iso3_addr base_addr, t_iso3_addr last_addr); +#endif +#ifdef DEVICE_2_REQUEST_DOWNLOAD_CALLBACK +UI_8 DEVICE_2_REQUEST_DOWNLOAD_CALLBACK(t_iso3_addr base_addr, t_iso3_addr last_addr); +#endif +#ifdef DEVICE_3_REQUEST_DOWNLOAD_CALLBACK +UI_8 DEVICE_3_REQUEST_DOWNLOAD_CALLBACK(t_iso3_addr base_addr, t_iso3_addr last_addr); +#endif + +#ifdef DEVICE_0_TRANSFER_DATA_CALLBACK +UI_8 DEVICE_0_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_1_TRANSFER_DATA_CALLBACK +UI_8 DEVICE_1_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_2_TRANSFER_DATA_CALLBACK +UI_8 DEVICE_2_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_3_TRANSFER_DATA_CALLBACK +UI_8 DEVICE_3_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size); +#endif + +#ifdef UDS_TRANSFER_DATA_ERROR_CALLBACK +UI_8 UDS_TRANSFER_DATA_ERROR_CALLBACK(UI_8 error_code); +#endif + +#ifdef DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK +UI_8 DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_1_REQUEST_TRANSFER_EXIT_CALLBACK +UI_8 DEVICE_1_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_2_REQUEST_TRANSFER_EXIT_CALLBACK +UI_8 DEVICE_2_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size); +#endif +#ifdef DEVICE_3_REQUEST_TRANSFER_EXIT_CALLBACK +UI_8 DEVICE_3_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size); +#endif + + +/***************************************************************************** + * Security attempts counter section + *****************************************************************************/ + +void Iso15765_3SecurityAttemptsIncrement(void); /*!< Function that increments the attempts counter */ +void Iso15765_3SecurityAttemptsDecrement(void); /*!< Function that decrements the attempts counter, f.i. when penalty time expires */ +BOOL Iso15765_3SecurityAttemptsExceeded(void); /*!< Function to determine if the allowed attempts have been exceeded */ +BOOL Iso15765_3SecurityAttemptsReached(void); /*!< Function to determine if the allowed attempts have been reached (about to be exceeded on next try) */ +void Iso15765_3SecurityAttemptsClear(void); /*!< Function to clear the attempt counter, f.i. when successful attempt is done */ +void Iso15765_3SecurityAttemptsInitialize(void); /*!< Function to initialize the counter structure, loading (if defined) the NVM counter */ +UI_8 Iso15765_3SecurityAttemptsGet(void); /*!< Accessor getter function for the counter */ + +/**************************************************************************** +* Variant section +*****************************************************************************/ + +BOOL Iso15765_3VariantConsecutiveSeedIncrAttempt(void); /*!< Function to know if the UDS variant considers consecutive seed requests as failed security attempts */ + +#endif + diff --git a/firmware/src/DiagnosticR/Comp_ISO_15765_3/UdsServerCallbacksDEVICE_NAME_TEMPLATE.h b/firmware/src/DiagnosticR/Comp_ISO_15765_3/UdsServerCallbacksDEVICE_NAME_TEMPLATE.h new file mode 100644 index 0000000..52a2b59 --- /dev/null +++ b/firmware/src/DiagnosticR/Comp_ISO_15765_3/UdsServerCallbacksDEVICE_NAME_TEMPLATE.h @@ -0,0 +1,464 @@ +/*************** COPYRIGHT (c) 2007-2011 FICOSA INTERNATIONAL ************** +| Language: | MISRA C +| Controller: | +| Spec. Document: | ISO15765_3 ISO14229 +|-----------------|------------------------------------------------------------ +| Project: | Unified Diagnostics Services Layer +| Reference: | +|------------------------------------------------------------------------------ +| HISTORY OF MODIFICATIONS +| Date - Coder - Description +| 25/02/10 AC File creation +| 21/06/12 DM Integrated with TP tag 20120530. +|------------------------------------------------------------------------------ +| FILE DESCRIPTION: +| Implementacio dels serveis de diagnostics segons el standard ISO 15765-3 +******************************************************************************/ +#ifndef __UDSSERVERCALLBACKS_H +#define __UDSSERVERCALLBACKS_H + +/* ------------------------------ Includes --------------------------------- */ +#include "Global.h" +#include "Iso15765_3_CFG.h" +#include "ProjectCFG.h" + +/* --------------------------- Type Definitions ---------------------------- */ + +/* ------------------------------- Defines --------------------------------- */ + +/* POSSIBLE START ROUTINE BY LOCAL ID TYPES */ +#define START_ROUTINE_CONTROL ((UI_8)0x00) +#define REQUEST_ROUTINE_CONTROL ((UI_8)0x01) + +/* POSSIBLE START ROUTINE BY LOCAL ID RESPONSE STATUS */ +#define ROUTINE_IN_PROGRESS ((UI_8)1) +#define ROUTINE_COMPLETED_AND_OK ((UI_8)2) +#define ROUTINE_COMPLETED_AND_NO_OK ((UI_8)3) +#define ROUTINE_TO_BE_ANSWERED_BY_TELEM ((UI_8)4) + +/* Reset types accepted with the EcuReset diagnostic service */ +#define RESET_ALL_HW ((UI_8)0x01) +#define RESET_KEY_ON_OFF ((UI_8)0x02) +#define RESET_CONFIGURATION_PARAMETERS ((UI_8)0x40) +#define RESET_TEST_PARAMETERS ((UI_8)0x41) +#define RESET_TELEM ((UI_8)0x60) +#define RESET_PMC ((UI_8)0x61) +#define RESET_RTC ((UI_8)0x62) +#define RESET_WIFI ((UI_8)0x63) + +/* SUPPORTED LOCAL DATA IDENTIFIERS FOR READDATABYLOCALID AND WRITEDATABYLOCAL SERVICES */ +#define USER_COLLATION_R_ID ((UI_8)0x01) + + +/* LENGTH OF LOCAL DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES */ +#define USER_COLLATION_R_LEN ((UI_8)100) + + +/* SUPPORTED DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES */ +#define CURRENT_AND_VOLTAGE_STATUS_ID ((UI_16)0x0100) +#define TIP_HALL_SENSORS_STATUS_ID ((UI_16)0x0101) +#define DUAL_DIE_MELEXIS_ANGLE_STATUS_ID ((UI_16)0x0102) +#define PARKING_SWITCH_VOLTAGE_STATUS_ID ((UI_16)0x0103) +#define SHIFT_LOCK_FAIL_STATUS_ID ((UI_16)0x0104) + + + +/* LENGTH OF DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES */ +#define CURRENT_AND_VOLTAGE_STATUS_LEN ((UI_8)34) +#define TIP_HALL_SENSORS_STATUS_LEN ((UI_8)8) +#define DUAL_DIE_MELEXIS_ANGLE_STATUS_LEN ((UI_8)16) +#define PARKING_SWITCH_VOLTAGE_STATUS_LEN ((UI_8)4) +#define SHIFT_LOCK_FAIL_STATUS_LEN ((UI_8)1) + + + +/* SUPPORTED LOCAL IDENTIFIERS FOR INPUTOUTPUTCONTROLBYLOCALID SERVICE */ +#define SHIFTLOCK_ACTIVATION_IOCTRL_ID ((UI_8)0x01) +#define LED_M_ACTIVATION_IOCTRL_ID ((UI_8)0x02) +#define LED_D_ACTIVATION_IOCTRL_ID ((UI_8)0x03) +#define LED_N_ACTIVATION_IOCTRL_ID ((UI_8)0x04) +#define LED_R_ACTIVATION_IOCTRL_ID ((UI_8)0x05) +#define LED_P_ACTIVATION_IOCTRL_ID ((UI_8)0x06) +#define BACKLIGHT_ACTIVATION_IOCTRL_ID ((UI_8)0x07) +#define OVERLIGHT_ACTIVATION_IOCTRL_ID ((UI_8)0x08) + + +/* LENGTH OF LOCAL IDENTIFIERS FOR INPUTOUTPUTCONTROLBYLOCALID SERVICE */ +#define SHIFTLOCK_IOCTRL_LEN ((UI_8)1) +#define LED_M_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define LED_D_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define LED_N_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define LED_R_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define LED_P_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define BACKLIGHT_ACTIVATION_IOCTRL_LEN ((UI_8)1) +#define OVERLIGHT_ACTIVATION_IOCTRL_LEN ((UI_8)1) + + + +/* SUPPORTED LOCAL IDENTIFIERS FOR STARTROUTINEBYLOCALID SERVICE */ +#define GLOBAL_CHECK_CONNECTION_SRBLID_ID ((UI_8)0x02) + + +/* LENGTH OF LOCAL IDENTIFIERS FOR STARTROUTINEBYLOCALID SERVICE */ +#define GLOBAL_CHECK_CONNECTION_SRBLID_LEN ((UI_8)0) + + + + +/*--------------------------- Global variables ---------------------------- */ + +/* ------------------------- Function prototypes --------------------------- */ + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands all the ReadDataByIdentifier diagnostics and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - id_h: higher byte of the identifier requested +| - id_h: lower byte of the identifier requested +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsReadDataByIdentifier(UI_8 id_h, UI_8 id_l); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands all the WriteDataByIdentifier diagnostics and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - id_h: higher byte of the identifier requested +| - id_h: lower byte of the identifier requested +| - data_buffer: data pointer of the received parameters for the write +| - size: length of the parameters received for the write +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsWriteDataByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 *data_buffer, UI_16 size); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands all the RoutineControl diagnostics and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - routine_ctrl_type: type of the routine control requested. Can be a start, +| a stop or a request results +| - id: identifier requested +| - size: length of the parameters received for the write +| - routine_entry_option: data pointer of the received parameters for the write +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void StartRoutineByLocalId(UI_8 routine_ctrl_type, UI_8 id, + UI_16 size, UI_8 *routine_entry_option); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands UdsStopRoutineByLocalId diagnostic service and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - id: identifier of the DTC requested +| - size: length of the data received +| - data: data pointer to the buffer of the requested information +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void StopRoutineByLocalId(UI_8 id, UI_16 size, UI_8 *data); + +/***************************************************************************** +| Portability: +|---------------------------------------------------------------------------- +| Description: +| * Routine that updates Routine status. +|--------------------------------------------------------------------------- +| Arguments: +| - id: identifier requested +| - status: status of the routine, allowed values: +| * ROUTINE_IN_PROGRESS +| * ROUTINE_COMPLETED_AND_OK +| * ROUTINE_COMPLETED_AND_NO_OK +| * ROUTINE_TO_BE_ANSWERED_BY_TELEM + +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void StartRoutineUpdateStatusByLocalId(UI_8 id,UI_8 status); + + +/***************************************************************************** +| Portability: +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the ClearDiagnosticInfo diagnostic service and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - dtc_hb: higher byte of the requested clear dignostic type received +| - dtc_mb: medium byte of the requested clear dignostic type received +| - dtc_lb: lower byte of the requested clear dignostic type received +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsClearDiagnosticInformation(UI_8 dtc_hb, UI_8 dtc_mb, UI_8 dtc_lb); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the TcuUdsReadMemoryByAddress diagnostic service +| and is responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - mem_size_len: length of the requested size in bytes +| - mem_addr_len: length of the requested address in bytes +| - mem_addr: data pointer to the requested initial memory address to be read +| - mem_size: data pointer to the requested memory size to be read +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsReadMemoryByAddress(UI_8 mem_size_len, UI_8 mem_addr_len, + UI_8 *mem_addr, UI_8 *mem_size); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the TcuUdsWriteMemoryByAddress diagnostic service +| and is responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - addr_data_size: the first four bits cointains the data size length in +| bytes and the last four bits contains the address size +| length in bytes +| - data_buffer: data pointer where to find the requested initial write +| address, the requested write length and the values to write +| in memory +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsWriteMemoryByAddress(UI_8 addr_data_size, UI_8 *data_buffer); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Configured callback routine to be notified about the expiration of the +| previous non default session. This routine must undo all the special +| diagnostic features done during the especial session +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsReturnToDefaultSession(UI_8 old_session, UI_8 new_session); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the TcuUdsTesterPresent diagnostic service and is +| responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - tp_type: tester present type requested +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsTesterPresent(UI_8 tp_type); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the TcuUdsDiagnosticSessionControl diagnostic +| service and is responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - session: requested new session +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsDiagnosticSessionControl(UI_8 session); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the ReadDataByLocalIdentifier diagnostic +| service and is responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - id: identifier requested to read his data +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsRsaReadDataByLocalId(UI_8 id); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the WriteByLocalIdentifier diagnostic +| service and is responsible for giving the final answer to ISO_3 layer. +|--------------------------------------------------------------------------- +| Arguments: +| - id: identifier of the data to be written +| - data: data pointer to the received parameters to be written +| - size: length of the data to be written +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsRsaWriteDataByLocalId(UI_8 id, UI_8 *data, UI_16 size); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the EcuReset diagnostic service and is responsible +| for giving the final answer to ISO_3 layer before performing the reset +|--------------------------------------------------------------------------- +| Arguments: +| - reset_mode: type of reset requested +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsEcuReset(UI_8 reset_mode); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * Routine that commands the InputOutputControlByLocalId diagnostic +| service and is responsible for giving the final answer to ISO_3 layer +|--------------------------------------------------------------------------- +| Arguments: +| - id: identifier of the requested input output control +| - ctr_type: requested control type for the received id +| - size: length of the data received to control +| - data: data pointer to the received control data +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsInputOutputControlByIdentifier(UI_16 id, UI_8 ctr_type, UI_16 size, UI_8 *data); + + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * UdServices diagnostic initialitzation task. This routine should only +| be called one time at the microcontroller initialization +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsServerCallbacksInit(void); + +/***************************************************************************** +| Portability: TCU Project +|---------------------------------------------------------------------------- +| Description: +| * UdServices diagnostic task executed in every main cycle +|--------------------------------------------------------------------------- +| Arguments: +|--------------------------------------------------------------------------- +| Timing: +| Tmax Int Dis: ? cicles cpu | O(n): CTE +| Tmax Int En : ? cicles cpu | O(n): CTE +| Tmax Total : ? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +void UdsServerCallbacksTask(void); + +/*************** Extra services example of implementation ******************/ + +#if (UDS_SERVICE_GEELY_ECHO_STATUS == SERVICE_ENABLED) +/** + * Extra services dispatcher. Will be executed in case of unrecognized service + * @param service current unrecognized service + * @param subfunction current unrecognized subfunction + * @param buf_data_rx rx data buffer with the request + * @param size size of the request + */ +void UdsExtraServices(UI_8 service,UI_8 subfunction,UI_8 *buf_data_rx, UI_8 size); + +/** + * Geely ECHO service. It returns same data has received from the request + * @param data buffer data with the request + * @param size size of the request + * @return response mode + */ +UI_8 UdsGeelyEcho(UI_8 *data, UI_8 size); +#endif +#endif diff --git a/firmware/src/DiagnosticR/Dem/CalibrationData.h b/firmware/src/DiagnosticR/Dem/CalibrationData.h new file mode 100644 index 0000000..c24b4be --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/CalibrationData.h @@ -0,0 +1,45 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + + +#ifndef CALIBRATIONDATA_H_ +#define CALIBRATIONDATA_H_ + +//#include "Calibration_Settings.h" + +#ifdef CALIBRATION_ENABLED +/* Section data from linker script. */ +extern char __CALIB_RAM_START; +extern char __CALIB_RAM_END; +extern char __CALIB_ROM_START; + + +#ifdef __CWCC__ +#pragma section RW ".calibration_data" ".calibration" +#define ARC_DECLARE_CALIB(type, name) __declspec(section ".calibration_data") type name +#else +#define ARC_DECLARE_CALIB(type, name) type __attribute__((section (".calibration"))) name +#define ARC_DECLARE_CALIB_SHARED(type, name) type __attribute__((section (".calib_shared"))) name +#define ARC_DECLARE_CALIB_EXTERN(type, name) extern type name +#define ARC_DECLARE_CALIB_COMPONENT(type, name) type __attribute__((section (".calib_component"))) name +#endif/* __CWCC__ */ + +#else +#define ARC_DECLARE_CALIB(type, name) type name +#define ARC_DECLARE_CALIB_SHARED(type, name) type name +#define ARC_DECLARE_CALIB_EXTERN(type, name) extern type name +#define ARC_DECLARE_CALIB_COMPONENT(type, name) type name +#endif /* CALIBRATION_ENABLED */ + +#endif /* CALIBRATIONDATA_H_ */ diff --git a/firmware/src/DiagnosticR/Dem/Dem.c b/firmware/src/DiagnosticR/Dem/Dem.c new file mode 100644 index 0000000..d7a27d1 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem.c @@ -0,0 +1,7198 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ +/*lint -w1 */ + +/* INPROVEMENT: This note should be enabled */ +/*lint -e9025 */ + +/* + * General requirements + */ +/* @req DEM126 */ +/* !req DEM151 Partially */ +/* @req DEM152 */ +/* !req DEM013 Only 14229-1 format supported */ +/* @req DEM645 Both UDS and OBD format supported */ +/* @req DEM277 Both UDS and OBD format supported */ +/* @req DEM113 */ +/* @req DEM267 */ +/* !req DEM268 */ +/* @req DEM364 */ +/* @req DEM114 */ +/* @req DEM124 */ +/* @req DEM370 */ +/* @req DEM386 UDS status bit 0 transitions */ +/* @req DEM389 UDS status bit 1 transitions */ +/* @req DEM390 UDS status bit 2 transitions */ +/* @req DEM391 UDS status bit 3 transitions */ +/* @req DEM392 UDS status bit 4 transitions */ +/* @req DEM393 UDS status bit 5 transitions */ +/* @req DEM394 UDS status bit 6 transitions */ +/* @req DEM395 UDS status bit 7 transitions */ +/* @req 4.2.2/SWS_Dem_01102 DTC suppression shall not stop event processing of the corresponding DTC. */ + + +#include + + +#if defined(USE_NVM) +#include "NvM.h" /** @req DEM176.NvM */ +#endif + +//#include "SchM_Dem.h" +//#include "MemMap.h" +//#include "Cpu.h" +#include "Dem_Types.h" +#include "DiagnosticR/Dem/Dem_Lcfg.h" +#include "DiagnosticR/Dem/Dem_Internal.h" +#include "DiagnosticR/Dem/Dem_Cfg.h" +#include "DiagnosticR/Dem/Dem.h" + + +#if defined(USE_DEM_EXTENSION) +#include "Dem_Extension.h" +#endif +#define USE_DEBUG_PRINTF +//#include "debug.h" + +#if defined(USE_RTE) +/*lint -e18 duplicate declarations hidden behinde ifdef */ +#include "Rte_Dem.h" +#endif + +#if (DEM_TRIGGER_DLT_REPORTS == STD_ON) +#include "Dlt.h" +#endif + +/* + * Local defines + */ +#define DEM_EXT_DATA_IN_PRE_INIT (DEM_MAX_NUMBER_EXT_DATA_PRE_INIT > 0) +#define DEM_EXT_DATA_IN_PRI_MEM (DEM_MAX_NUMBER_EXT_DATA_PRI_MEM > 0) +#define DEM_EXT_DATA_IN_SEC_MEM (DEM_MAX_NUMBER_EXT_DATA_SEC_MEM > 0) +#define DEM_FF_DATA_IN_PRE_INIT (DEM_MAX_NUMBER_FF_DATA_PRE_INIT > 0) +#define DEM_FF_DATA_IN_PRI_MEM (DEM_MAX_NUMBER_FF_DATA_PRI_MEM > 0) +#define DEM_FF_DATA_IN_SEC_MEM (DEM_MAX_NUMBER_FF_DATA_SEC_MEM > 0) +#define DEM_DEFAULT_EVENT_STATUS (DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE) + +#define DEM_PID_IDENTIFIER_SIZE_OF_BYTES 1 // OBD +#define DEM_FAILURE_CNTR_MAX 255 +#define DEM_AGING_CNTR_MAX 255 +#define DEM_INDICATOR_CNTR_MAX 255 +#define DEM_OCCURENCE_COUNTER_MAX 0xFFFF + +#define MOST_RECENT_FF_RECORD 0xFF + +#define ALL_EXTENDED_DATA_RECORDS 0xFF +#define IS_VALID_EXT_DATA_RECORD(_x) ((0x01 <= (_x)) && (0xEF >= (_x))) + +//#define IS_VALID_EVENT_ID(_x) (((_x) > 0) && ((_x) <= DEM_EVENT_ID_LAST_VALID_ID)) + +#define IS_VALID_INDICATOR_ID(_x) ((_x) < DEM_NOF_INDICATORS) + +#define IS_SUPPORTED_ORIGIN(_x) ((DEM_DTC_ORIGIN_PRIMARY_MEMORY == (_x)) || (DEM_DTC_ORIGIN_SECONDARY_MEMORY == (_x))) + + + +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +#define NUM_STORED_BITS 2u +#define NOF_EVENTS_PER_BYTE (8u/NUM_STORED_BITS) +#define GET_UDSBIT_BYTE_INDEX(_eventId) (((_eventId)-1u)/NOF_EVENTS_PER_BYTE) +#define GET_UDS_STARTBIT(_eventId) ((((_eventId)-1u)%NOF_EVENTS_PER_BYTE)*2u) +#define UDS_BITMASK 3u +#define UDS_TFSLC_BIT 0u +#define UDS_TNCSLC_BIT 1u +#define UDS_STATUS_BIT_MAGIC UDS_BITMASK +#define UDS_STATUS_BIT_MAGIC_INDEX ((DEM_MAX_NUMBER_EVENT + (NOF_EVENTS_PER_BYTE - 1u))/NOF_EVENTS_PER_BYTE) +#endif + +#if 0 +#define VALIDATE_RV(_exp,_api,_err,_rv ) \ + if( !(_exp) ) { \ + DET_REPORTERROR(MODULE_ID_DEM, 0, _api, _err); \ + return _rv; \ + } + +#define VALIDATE_NO_RV(_exp,_api,_err ) \ + if( !(_exp) ) { \ + DET_REPORTERROR(MODULE_ID_DEM, 0, _api, _err); \ + return; \ + } +#endif + +#if (DEM_OBD_SUPPORT == STD_ON) +#error "DEM_OBD_SUPPORT is set to STD_ON, this is not supported by the code." +#endif + +#if (DEM_PTO_SUPPORT == STD_ON) +#error "DEM_PTO_SUPPORT is set to STD_ON, this is not supported by the code." +#endif + +#if !((DEM_TYPE_OF_DTC_SUPPORTED == DEM_DTC_TRANSLATION_ISO15031_6) || (DEM_TYPE_OF_DTC_SUPPORTED == DEM_DTC_TRANSLATION_ISO14229_1)) +#error "DEM_TYPE_OF_DTC_SUPPORTED is not set to ISO15031-6 or ISO14229-1. Only these are supported by the code." +#endif + +#if !defined(USE_DEM_EXTENSION) +#if defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) +#error "DEM_FREEZE_FRAME_CAPTURE cannot be DEM_TRIGGER_EXTENSION since Dem extension is not used!" +#endif +#if defined(DEM_EXTENDED_DATA_CAPTURE_EXTENSION) +#error "DEM_EXTENDED_DATA_CAPTURE cannot be DEM_TRIGGER_EXTENSION since Dem extension is not used!" +#endif +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) +#error "DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION cannot be used since Dem extension is not used!" +#endif +#if defined(DEM_FAILURE_PROCESSING_DEM_EXTENSION) +#error "DEM_FAILURE_PROCESSING_DEM_EXTENSION cannot be used since Dem extension is not used!" +#endif +#if defined(DEM_AGING_PROCESSING_DEM_EXTENSION) +#error "DEM_AGING_PROCESSING_DEM_EXTENSION cannot be used since Dem extension is not used!" +#endif +#endif +#if defined(DEM_EXTENDED_DATA_CAPTURE_EVENT_MEMORY_STORAGE) +#error "DEM_EXTENDED_DATA_CAPTURE_EVENT_MEMORY_STORAGE is not supported!" +#endif + +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) || (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) +#define DEM_USE_MEMORY_FUNCTIONS +#endif +#if defined(USE_NVM) && (DEM_USE_NVM == STD_ON) +#define DEM_ASSERT(_exp) switch (1) {case 0: break; case _exp: break; } +#endif + +#if (DEM_TEST_FAILED_STORAGE == STD_ON) +#define GET_STORED_STATUS_BITS(_x) ((_x) & (DEM_TEST_FAILED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_PENDING_DTC | DEM_CONFIRMED_DTC | DEM_TEST_FAILED)) +#else +#define GET_STORED_STATUS_BITS(_x) ((_x) & (DEM_TEST_FAILED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_PENDING_DTC | DEM_CONFIRMED_DTC)) + +#endif + +#define IS_VALID_EVENT_STATUS(_x) ((DEM_EVENT_STATUS_PREPASSED == _x) || (DEM_EVENT_STATUS_PASSED == _x) || (DEM_EVENT_STATUS_PREFAILED == _x) || (DEM_EVENT_STATUS_FAILED == _x)) + +#if (DEM_NOF_EVENT_INDICATORS > 0) +#define DEM_USE_INDICATORS +#endif + +#define TO_OBD_FORMAT(_x) ((_x)<<8u) +#define IS_VALID_DTC_FORMAT(_x) ((DEM_DTC_FORMAT_UDS == (_x)) || (DEM_DTC_FORMAT_OBD == (_x))) + + +/* + * Local types + */ +#if !defined(USE_NVM) && !defined(USE_RTE) +/* NvM_BlockIdType is defined in the RTE when used or in NvM when used + * If neither is used, typedef it here since used by DEM + */ +typedef uint16 NvM_BlockIdType; +#endif + +// DtcFilterType +typedef struct { + Dem_EventStatusExtendedType dtcStatusMask; + Dem_DTCKindType dtcKind; + Dem_DTCOriginType dtcOrigin; + Dem_FilterWithSeverityType filterWithSeverity; + Dem_DTCSeverityType dtcSeverityMask; + Dem_FilterForFDCType filterForFaultDetectionCounter; + uint16 faultIndex; + Dem_DTCFormatType dtcFormat; +} DtcFilterType; + +// FreezeFrameRecordFilterType +typedef struct { + uint16 ffIndex; + Dem_DTCFormatType dtcFormat; +} FreezeFrameRecordFilterType; + +// DisableDtcStorageType +typedef struct { + boolean settingDisabled; + Dem_DTCGroupType dtcGroup; + Dem_DTCKindType dtcKind; +} DisableDtcSettingType; + + +// State variable +typedef enum +{ + DEM_UNINITIALIZED = 0, + DEM_PREINITIALIZED, + DEM_INITIALIZED +} Dem_StateType; /** @req DEM169 */ + + + +static Dem_StateType demState = DEM_UNINITIALIZED; + +// Help pointer to configuration set +static const Dem_ConfigSetType *configSet; + +/* + * Allocation of DTC filter parameters + */ +static DtcFilterType dtcFilter; + +/* + * Allocation of freeze frame record filter + */ +static FreezeFrameRecordFilterType ffRecordFilter; + + +/* + * Allocation of Disable/Enable DTC setting parameters + */ +static DisableDtcSettingType disableDtcSetting; + +/* + * Allocation of operation cycle state list + */ +/* NOTE: Do not change this without also changing generation of measurement tags */ +static Dem_OperationCycleStateType operationCycleStateList[DEM_OPERATION_CYCLE_ID_ENDMARK]; + +/* + * Allocation of local event status buffer + */ +/* NOTE: Do not change this without also changing generation of measurement tags */ +static EventStatusRecType eventStatusBuffer[DEM_MAX_NUMBER_EVENT]; + +/* + * Allocation of pre-init event memory (used between pre-init and init). Only one + * memory regardless of event destination. + */ +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static FreezeFrameRecType preInitFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRE_INIT]; +#endif +#if ( DEM_EXT_DATA_IN_PRE_INIT ) +static ExtDataRecType preInitExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRE_INIT]; +#endif + +/* + * Allocation of primary event memory ramlog (after init) in uninitialized memory + */ +#define ADMIN_MAGIC 0xBABE +/** @req DEM162 */ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) +#define PRI_MEM_EVENT_BUFFER_ADMIN_INDEX DEM_MAX_NUMBER_EVENT_PRI_MEM +EventRecType priMemEventBuffer[DEM_MAX_NUMBER_EVENT_PRI_MEM + 1];/* + 1 for admin data */ +static boolean priMemOverflow = FALSE;/* @req DEM397 */ +#if ( DEM_FF_DATA_IN_PRI_MEM ) +FreezeFrameRecType priMemFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRI_MEM]; +#endif +#if (DEM_EXT_DATA_IN_PRI_MEM) +ExtDataRecType priMemExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRI_MEM]; +#endif +#endif + + +/* + * Allocation of secondary event memory ramlog (after init) in uninitialized memory + */ +/** @req DEM162 */ +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) +#define SEC_MEM_EVENT_BUFFER_ADMIN_INDEX DEM_MAX_NUMBER_EVENT_SEC_MEM +EventRecType secMemEventBuffer[DEM_MAX_NUMBER_EVENT_SEC_MEM + 1];/* + 1 for admin data */ +static boolean secMemOverflow = FALSE;/* @req DEM397 */ +#if (DEM_FF_DATA_IN_SEC_MEM) +FreezeFrameRecType secMemFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_SEC_MEM]; +#endif +#if (DEM_EXT_DATA_IN_SEC_MEM) +ExtDataRecType secMemExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_SEC_MEM]; +#endif +#endif + +#if defined(DEM_USE_MEMORY_FUNCTIONS) && (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +/* Buffer for storing subset of UDS status bits for all events */ +uint8 statusBitSubsetBuffer[DEM_MEM_STATUSBIT_BUFFER_SIZE]; +#endif + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +/* Timestamp for events */ +static uint32 Event_TimeStamp = 0; + +/* Timestamp for extended data */ +static uint32 ExtData_TimeStamp = 0; + +/* +*Allocation of freezeFrame storage timestamp,record the time order +*/ +/**private variable for freezeframe */ +static uint32 FF_TimeStamp = 0; +#endif + +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) +typedef struct { + boolean SuppressedByDTC:1;/*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean SuppressedByEvent:1;/*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ +}DemDTCSuppressionType; +static DemDTCSuppressionType DemDTCSuppressed[DEM_NOF_DTCS]; +#endif + +typedef struct { + NvM_BlockIdType blockId; + Dem_DTCOriginType origin; + boolean dataModified; /* true if buffer changed */ +} BufferInfo_t; + + +/* This buffers keep track of the buffer modifications */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +static void setEventBlockChanged(Dem_DTCOriginType origin); +static BufferInfo_t FFIsModified[DEM_MAX_NR_OF_EVENT_DESTINATION]; + +static BufferInfo_t EventIsModified[DEM_MAX_NR_OF_EVENT_DESTINATION]; +static BufferInfo_t ExtendedDataIsModified[DEM_MAX_NR_OF_EVENT_DESTINATION]; +#if defined(DEM_USE_INDICATORS) +static BufferInfo_t IndicatorsAreModified; +#endif +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +static BufferInfo_t StatusBitsAreModified; +#endif +#endif + +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) +static boolean DemEnableConditions[DEM_NUM_ENABLECONDITIONS]; +#endif + +#define NO_DTC_DISABLED 0xFFFFFFFFUL + +typedef struct { + uint32 DTC; + Dem_DTCOriginType Origin; +}DtcRecordUpdateDisableType; + +static DtcRecordUpdateDisableType DTCRecordDisabled; + +#if defined(DEM_USE_INDICATORS) +/* @req DEM499 */ +#define INDICATOR_FAILED_DURING_FAILURE_CYCLE 1u +#define INDICATOR_PASSED_DURING_FAILURE_CYCLE (1u<<1u) +#define INDICATOR_FAILED_DURING_HEALING_CYCLE (1u<<2u) +#define INDICATOR_PASSED_DURING_HEALING_CYCLE (1u<<3u) + +typedef struct { + Dem_EventIdType EventID; + uint16 InternalIndicatorId; + uint8 FailureCounter; + uint8 HealingCounter; + uint8 OpCycleStatus; +}IndicatorStatusType; + +typedef struct { + Dem_EventIdType EventID; + uint8 IndicatorId; + uint8 FailureCounter; + uint8 HealingCounter; +}IndicatorNvRecType; + +/* Buffer for storing event indicators internally */ +static IndicatorStatusType indicatorStatusBuffer[DEM_NOF_EVENT_INDICATORS]; + +#if defined(DEM_USE_MEMORY_FUNCTIONS) +/* Buffer for storing event indicator status in NvRam */ +IndicatorNvRecType indicatorBuffer[DEM_NOF_EVENT_INDICATORS]; +#endif +#endif +/* + * Local functions + * */ +#if 1 //W +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +static void SetDefaultUDSStatusBitSubset(void); +#endif + +#if ( DEM_FF_DATA_IN_PRE_INIT || DEM_FF_DATA_IN_PRI_MEM ) +static boolean storeOBDFreezeFrameDataMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame, + FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, + Dem_DTCOriginType origin); +#endif + +#if ( DEM_FF_DATA_IN_PRE_INIT || DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM ) +static boolean storeFreezeFrameDataMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame, + FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, + Dem_DTCOriginType origin); +#endif + +static boolean deleteFreezeFrameDataMem(const Dem_EventParameterType *eventParam, Dem_DTCOriginType origin); +static boolean deleteExtendedDataMem(const Dem_EventParameterType *eventParam, Dem_DTCOriginType origin); +#endif + +static Std_ReturnType getEventFailed(Dem_EventIdType eventId, boolean *eventFailed); + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +#if (DEM_UNIT_TEST == STD_ON) +void rearrangeEventTimeStamp(uint32 *timeStamp); +#else +static void rearrangeEventTimeStamp(uint32 *timeStamp); +#endif +#endif + +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) +static void storeEventIndicators(const Dem_EventParameterType *eventParam); +static void setIndicatorBlockChanged(void); +#endif + + +static Std_ReturnType getEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended); + +#if (DEM_UNIT_TEST == STD_ON) +/* + * Procedure: zeroPriMemBuffers + * Description: Fill the primary buffers with zeroes + */ +/*lint -efunc(714, demZeroPriMemBuffers) */ +void demZeroPriMemBuffers(void) +{ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + memset(priMemEventBuffer, 0, sizeof(priMemEventBuffer)); + priMemOverflow = FALSE; +#if (DEM_FF_DATA_IN_PRI_MEM) + memset(priMemFreezeFrameBuffer, 0, sizeof(priMemFreezeFrameBuffer)); +#endif +#if (DEM_EXT_DATA_IN_PRI_MEM) + memset(priMemExtDataBuffer, 0, sizeof(priMemExtDataBuffer)); +#endif +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) + memset(indicatorBuffer, 0, sizeof(indicatorBuffer)); +#endif +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) + memset(statusBitSubsetBuffer, 0, sizeof(statusBitSubsetBuffer)); +#endif +#endif +} + +void demZeroSecMemBuffers(void) +{ +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + memset(secMemEventBuffer, 0, sizeof(secMemEventBuffer)); + secMemOverflow = FALSE; +#if ( DEM_FF_DATA_IN_SEC_MEM ) + memset(secMemFreezeFrameBuffer, 0, sizeof(secMemFreezeFrameBuffer)); +#endif +#if ( DEM_EXT_DATA_IN_SEC_MEM ) + memset(secMemExtDataBuffer, 0, sizeof(secMemExtDataBuffer)); +#endif +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) + memset(statusBitSubsetBuffer, 0, sizeof(statusBitSubsetBuffer)); +#endif +#endif +} + +#endif + + +#ifdef DEM_USE_MEMORY_FUNCTIONS +static boolean eventIsStoredInMem(Dem_EventIdType eventId, const EventRecType* eventBuffer, uint32 eventBufferSize) +{ + boolean eventIdFound = FALSE; + + for (uint16 i = 0;((i < eventBufferSize) && (eventIdFound==FALSE)); i++) { + eventIdFound = (eventBuffer[i].EventData.eventId == eventId); + } + return eventIdFound; +} +#endif + +/** + * Determines if a DTC is available or not + * @param DTCClass + * @return TRUE: DTC available, FALSE: DTC NOT available + */ +static boolean DTCIsAvailable(const Dem_DTCClassType *DTCClass) +{ + if( DTCClass->DTCRef->DTCUsed +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) + && !DemDTCSuppressed[DTCClass->DTCIndex].SuppressedByDTC + && !DemDTCSuppressed[DTCClass->DTCIndex].SuppressedByEvent +#endif + ) { + return TRUE; + } else { + return FALSE; + } +} + +/* + * Procedure: checkDtcKind + * Description: Return TRUE if "dtcKind" match the events DTCKind or "dtcKind" + * is "DEM_DTC_KIND_ALL_DTCS" otherwise FALSE. + */ +static boolean checkDtcKind(Dem_DTCKindType dtcKind, const Dem_EventParameterType *eventParam) +{ + boolean result = FALSE; + if( (NULL != eventParam->DTCClassRef) && (DTCIsAvailable(eventParam->DTCClassRef)==TRUE) ) { + result = (dtcKind == DEM_DTC_KIND_ALL_DTCS) || (eventParam->DTCClassRef->DTCKind == dtcKind); + } + + return result; +} + +/** + * Checks if DTC is available on specific format + * @param eventParam + * @param dtcFormat + * @return TRUE: DTC is available on specific format, FALSE: Event is not available on specific format. + */ +static boolean eventHasDTCOnFormat(const Dem_EventParameterType *eventParam, Dem_DTCFormatType dtcFormat) +{ + boolean ret = FALSE; + if(( NULL != eventParam) && (NULL != eventParam->DTCClassRef) ) { + ret = ( ((DEM_DTC_FORMAT_UDS == dtcFormat) && (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->UDSDTC)) || + ((DEM_DTC_FORMAT_OBD == dtcFormat) && (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->OBDDTC))); + } + return ret; +} + +/** + * Checks if dtc is a DTC group + * @param dtc + * @param dtcFormat + * @param groupLower + * @param groupUpper + * @return TRUE: dtc is group, FALSE: dtc is NOT a group + */ +static boolean dtcIsGroup(uint32 dtc, Dem_DTCFormatType dtcFormat, uint32 *groupLower, uint32 *groupUpper) +{ + const Dem_GroupOfDtcType * DTCGroups = configSet->GroupOfDtc; + boolean groupFound = FALSE; + if( DEM_DTC_FORMAT_UDS == dtcFormat ) { + while( (FALSE == DTCGroups->Arc_EOL) && (FALSE == groupFound) ) { + if( dtc == DTCGroups->DemGroupDTCs ) { + *groupLower = DTCGroups->DemGroupDTCs; + groupFound = TRUE; + } + DTCGroups++; + } + *groupUpper = DTCGroups->DemGroupDTCs - 1u; + } + + return groupFound; +} + +/* + * Procedure: checkDtcGroup + * Description: Return TRUE if "dtc" match the events DTC or "dtc" is + * "DEM_DTC_GROUP_ALL_DTCS" otherwise FALSE. + */ +/** + * Checks is event has DTC matching "dtc". "dtc" can be a group or a specific DTC + * @param dtc + * @param eventParam + * @param dtcFormat + * @param checkFormat + * @return TRUE: event has DTC matching "dtc", FALSE: DTC does NOT have DTC matching "dtc" + */ +static boolean checkDtcGroup(uint32 dtc, const Dem_EventParameterType *eventParam, Dem_DTCFormatType dtcFormat) +{ + /* NOTE: dtcFormat determines the format of dtc */ + boolean result = FALSE; + + if( (NULL != eventParam->DTCClassRef) && DTCIsAvailable(eventParam->DTCClassRef) ) { + if( DEM_DTC_GROUP_ALL_DTCS == dtc ) { + result = (DEM_DTC_FORMAT_UDS == dtcFormat) ? (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->UDSDTC) : (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->OBDDTC); + } + else if( DEM_DTC_GROUP_EMISSION_REL_DTCS == dtc ) { + result = (DEM_DTC_FORMAT_UDS == dtcFormat) ? ((DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->UDSDTC) && (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->OBDDTC)) : (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->OBDDTC); + } + else { + /* Not "ALL DTCs" */ + if( eventHasDTCOnFormat(eventParam, dtcFormat) ) { + uint32 DTCGroupLower; + uint32 DTCGroupUpper; + if( TRUE == dtcIsGroup(dtc, dtcFormat, &DTCGroupLower, &DTCGroupUpper) ) { + if( DEM_DTC_FORMAT_UDS == dtcFormat ) { + result = (eventParam->DTCClassRef->DTCRef->UDSDTC >= DTCGroupLower) && (eventParam->DTCClassRef->DTCRef->UDSDTC < DTCGroupUpper); + } + else { + result = (eventParam->DTCClassRef->DTCRef->OBDDTC >= DTCGroupLower) && (eventParam->DTCClassRef->DTCRef->OBDDTC < DTCGroupUpper); + } + } + else { + result = (DEM_DTC_FORMAT_UDS == dtcFormat) ? (dtc == eventParam->DTCClassRef->DTCRef->UDSDTC) : (dtc == TO_OBD_FORMAT(eventParam->DTCClassRef->DTCRef->OBDDTC)); + } + } + } + } + + return result; +} + + +/* + * Procedure: checkDtcOrigin + * Description: Return TRUE if "dtcOrigin" match any of the events DTCOrigin otherwise FALSE. + */ +static inline boolean checkDtcOrigin(Dem_DTCOriginType dtcOrigin, const Dem_EventParameterType *eventParam) +{ + return (eventParam->EventClass->EventDestination == dtcOrigin); +} + +/* + * Procedure: checkDtcSeverityMask + * Description: Return TRUE if "dtcSeverityMask" match any of the events DTC severity otherwise FALSE. + */ +static boolean checkDtcSeverityMask(Dem_DTCSeverityType dtcSeverityMask, const Dem_EventParameterType *eventParam) +{ + return (NULL != eventParam->DTCClassRef) && ( 0 != (eventParam->DTCClassRef->DTCSeverity & dtcSeverityMask)); + +} + + +/* + * Procedure: checkDtcFaultDetectionCounterMask + * Description: TBD. + */ +static boolean checkDtcFaultDetectionCounter(Dem_EventIdType EventId) +{ + boolean result = FALSE; +#if 0 + /* Should be match if fdc is between 1 and 0x7e, + * i.e. event is prefailed. + * Currently not supported. */ + sint8 fdc = 0; + if( E_OK == getFaultDetectionCounter(EventId, &fdc) ) { + if( (fdc > 0) && (fdc < DEM_UDS_TEST_FAILED_TRESHOLD) ) { + result = TRUE; + } + } +#else + (void)EventId; +#endif + return result; +} + + + + +/* + * Procedure: lookupEventStatusRec + * Description: Returns the pointer to event id parameters of "eventId" in "*eventStatusBuffer", + * if not found NULL is returned. + */ +void lookupEventStatusRec(Dem_EventIdType eventId, EventStatusRecType **const eventStatusRec) +{ +// if ( IS_VALID_EVENT_ID(eventId)) { + // *eventStatusRec = &eventStatusBuffer[eventId - 1]; + // } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_UNEXPECTED_EXECUTION); + // *eventStatusRec = NULL; + //} +} + +/* + * Procedure: lookupEventIdParameter + * Description: Returns the pointer to event id parameters of "eventId" in "*eventIdParam", + * if not found NULL is returned. + */ +void lookupEventIdParameter(Dem_EventIdType eventId, const Dem_EventParameterType **const eventIdParam) +{ + // const Dem_EventParameterType *EventIdParamList = configSet->EventParameter; + //if (IS_VALID_EVENT_ID(eventId)) { + // *eventIdParam = &EventIdParamList[eventId - 1]; + //} else { + // *eventIdParam = NULL; + // } +} +/* + * Procedure: checkEntryValid + * Description: Returns whether event id "eventId" is a valid entry in primary memory + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +static boolean checkEntryValid(Dem_EventIdType eventId, Dem_DTCOriginType origin){ + const Dem_EventParameterType *EventIdParam = NULL; + EventStatusRecType *eventStatusRec = NULL; + boolean isValid = FALSE; + + lookupEventIdParameter(eventId, &EventIdParam); + if (NULL != EventIdParam) { + // Event was found + lookupEventStatusRec(eventId, &eventStatusRec); + // Event should be stored in destination memory? + isValid = checkDtcOrigin(origin, EventIdParam) && (NULL != eventStatusRec) && eventStatusRec->isAvailable; + } else { + // The event did not exist + } + return isValid; +} +#endif + +/** + * Checks if an operation cycle is started + * @param opCycle + * @return + */ +boolean operationCycleIsStarted(Dem_OperationCycleIdType opCycle) +{ + boolean isStarted = FALSE; + if (opCycle < DEM_OPERATION_CYCLE_ID_ENDMARK) { + if (operationCycleStateList[opCycle] == DEM_CYCLE_STATE_START) { + isStarted = TRUE; + } + } + return isStarted; +} + +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) +static boolean failureCycleIsStarted(const Dem_EventParameterType *eventParam) +{ + return operationCycleIsStarted(eventParam->EventClass->FailureCycleRef); +} + +static boolean faultConfirmationCriteriaFulfilled(const Dem_EventParameterType *eventParam, const EventStatusRecType *eventStatusRecPtr) +{ + if((eventParam->EventClass->FailureCycleRef != DEM_OPERATION_CYCLE_ID_ENDMARK) && + (eventStatusRecPtr->failureCounter >= eventParam->EventClass->FailureCycleCounterThresholdRef->Threshold) ) { + return TRUE; + } else { + return FALSE; + } +} +static void handleFaultConfirmation(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatusRecPtr) +{ + if( failureCycleIsStarted(eventParam) && !eventStatusRecPtr->failedDuringFailureCycle ) { + if( eventStatusRecPtr->failureCounter < DEM_FAILURE_CNTR_MAX ) { + eventStatusRecPtr->failureCounter++; + eventStatusRecPtr->errorStatusChanged = TRUE; + } + + /* @req DEM530 */ + if( faultConfirmationCriteriaFulfilled(eventParam, eventStatusRecPtr )) { + eventStatusRecPtr->eventStatusExtended |= DEM_CONFIRMED_DTC; + eventStatusRecPtr->errorStatusChanged = TRUE; + } + eventStatusRecPtr->failedDuringFailureCycle = TRUE; + } +} +#endif + + +#if defined(DEM_USE_INDICATORS) +/** + * Resets healing and failure counter for event indicators + * @param eventParam + * @return TRUE: counter value changed, FALSE: no change + */ +static boolean resetIndicatorCounters(const Dem_EventParameterType *eventParam) +{ + boolean countersChanged = FALSE; + if( NULL != eventParam->EventClass->IndicatorAttribute ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventParam->EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL) { + if( (0 != indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter) || (0 != indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter)) { + countersChanged = TRUE; + } + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter = 0; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter = 0; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus = 0; + indAttrPtr++; + } + } +#if defined(DEM_USE_MEMORY_FUNCTIONS) + if(countersChanged) { + storeEventIndicators(eventParam); + } +#endif + return countersChanged; +} + +/** + * Checks if indicator failure cycle is started + * @param eventParam + * @param indAttr + * @return TRUE: Failure cycle is started, FALSE: failure cycle not started + */ +static boolean indicatorFailureCycleIsStarted(const Dem_EventParameterType *eventParam, const Dem_IndicatorAttributeType *indAttr) +{ + if(DEM_FAILURE_CYCLE_INDICATOR == indAttr->IndicatorFailureCycleSource) { + return operationCycleIsStarted(indAttr->IndicatorFailureCycle); + } else { + return operationCycleIsStarted(eventParam->EventClass->FailureCycleRef); + } +} + +/** + * Checks if failure criteria for indicator is fulfilled + * @param eventParam + * @param indicatorAttribute + * @return TRUE: criteria fulfilled, FALSE: criteria not fulfilled + */ +static boolean indicatorFailFulfilled(const Dem_EventParameterType *eventParam, const Dem_IndicatorAttributeType *indicatorAttribute) +{ + boolean fulfilled = FALSE; + uint8 thresHold; + Dem_OperationCycleIdType opCyc; + + if( DEM_FAILURE_CYCLE_INDICATOR == indicatorAttribute->IndicatorFailureCycleSource ) { + thresHold = indicatorAttribute->IndicatorFailureCycleThreshold; + opCyc = indicatorAttribute->IndicatorFailureCycle; + } else { + thresHold = eventParam->EventClass->FailureCycleCounterThresholdRef->Threshold; + opCyc = eventParam->EventClass->FailureCycleRef; + } + /* @req DEM501 */ + if( (opCyc < DEM_OPERATION_CYCLE_ID_ENDMARK) && (indicatorStatusBuffer[indicatorAttribute->IndicatorBufferIndex].FailureCounter >= thresHold) ) { + fulfilled = TRUE; + } + return fulfilled; +} + +/** + * Checks if warningIndicatorOnCriteria is fulfilled for an event + * @param eventParam + * @return TRUE: criteria fulfilled, FALSE: criteria not fulfilled + */ +static boolean warningIndicatorOnCriteriaFulfilled(const Dem_EventParameterType *eventParam) +{ + boolean fulfilled = FALSE; + if( NULL != eventParam->EventClass->IndicatorAttribute ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventParam->EventClass->IndicatorAttribute; + /* @req DEM566 */ + while( !indAttrPtr->Arc_EOL && !fulfilled) { + fulfilled = indicatorFailFulfilled(eventParam, indAttrPtr); + indAttrPtr++; + } + } + return fulfilled; +} + +/** + * Checks if indicator healing cycle is started + * @param indAttr + * @return TRUE: Healing cycle is started, FALSE: Healing cycle not started + */ +static boolean indicatorHealingCycleIsStarted(const Dem_IndicatorAttributeType *indAttr) +{ + return operationCycleIsStarted(indAttr->IndicatorHealingCycle); +} + +/** + * Prepares indicator status for a new failure/healing cycle + * @param operationCycleId + */ +static void indicatorOpCycleStart(Dem_OperationCycleIdType operationCycleId) { + Dem_OperationCycleIdType failCyc; + const Dem_EventParameterType *eventIdParamList = configSet->EventParameter; + uint16 indx = 0; + while( !eventIdParamList[indx].Arc_EOL ) { + if( NULL != eventIdParamList[indx].EventClass->IndicatorAttribute ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventIdParamList[indx].EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL) { + if( operationCycleId == indAttrPtr->IndicatorHealingCycle ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus &= (uint8)~(INDICATOR_FAILED_DURING_HEALING_CYCLE | INDICATOR_PASSED_DURING_HEALING_CYCLE); + } + if( DEM_FAILURE_CYCLE_INDICATOR == indAttrPtr->IndicatorFailureCycleSource ) { + failCyc = indAttrPtr->IndicatorFailureCycle; + } else { + failCyc = eventIdParamList[indx].EventClass->FailureCycleRef; + } + if( operationCycleId == failCyc ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus &= (uint8)~(INDICATOR_FAILED_DURING_FAILURE_CYCLE | INDICATOR_PASSED_DURING_FAILURE_CYCLE); + } + indAttrPtr++; + } + } + indx++; + } +} + +/** + * Checks if warningIndicatorOffCriteria is fulfilled for an event + * @param eventParam + * @return TRUE: criteria fulfilled, FALSE: criteria not fulfilled + */ +static boolean warningIndicatorOffCriteriaFulfilled(const Dem_EventParameterType *eventParam) +{ + return (FALSE == warningIndicatorOnCriteriaFulfilled(eventParam)); +} + +/** + * Handles end of operation cycles for indicators + * @param operationCycleId + * @param eventStatusRecPtr + * @return TRUE: Counter updated for at least one event + */ +static boolean indicatorOpCycleEnd(Dem_OperationCycleIdType operationCycleId, EventStatusRecType *eventStatusRecPtr) { + /* @req DEM502 */ + /* @req DEM505 */ + Dem_OperationCycleIdType failCyc; + boolean counterChanged = FALSE; + uint8 healingCounterOld = 0; + uint8 failureCounterOld = 0; + const Dem_EventParameterType *eventParam = eventStatusRecPtr->eventParamRef; + + if( (NULL != eventParam) && (NULL != eventParam->EventClass->IndicatorAttribute) ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventParam->EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL) { + healingCounterOld = indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter; + failureCounterOld = indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter; + if( (operationCycleId == indAttrPtr->IndicatorHealingCycle) && + (0 == (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_FAILED_DURING_HEALING_CYCLE)) && + (0 != (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_PASSED_DURING_HEALING_CYCLE)) && + indicatorFailFulfilled(eventParam, indAttrPtr)) { + /* Passed and didn't fail during the healing cycle */ + if( indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter < DEM_INDICATOR_CNTR_MAX ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter++; + } + if( indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter >= indAttrPtr->IndicatorHealingCycleThreshold ) { + /* @req DEM503 */ + /* Healing condition fulfilled. + * Should we reset failure counter here? */ + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter = 0; + } + } + + if( DEM_FAILURE_CYCLE_INDICATOR == indAttrPtr->IndicatorFailureCycleSource ) { + failCyc = indAttrPtr->IndicatorFailureCycle; + } else { + failCyc = eventParam->EventClass->FailureCycleRef; + } + if( (operationCycleId == failCyc) && + (0 == (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_FAILED_DURING_FAILURE_CYCLE)) && + (0 != (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_PASSED_DURING_FAILURE_CYCLE)) && + !indicatorFailFulfilled(eventParam, indAttrPtr)) { + /* Passed and didn't fail during the failure cycle. + * Reset failure counter */ + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter = 0; + } + if( (healingCounterOld != indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter) || + (failureCounterOld != indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter) ) { + counterChanged = TRUE; + } + indAttrPtr++; + } + /* @req DEM533 */ + if( warningIndicatorOffCriteriaFulfilled(eventParam)) { + eventStatusRecPtr->eventStatusExtended &= ~DEM_WARNING_INDICATOR_REQUESTED; + } + +#if defined(DEM_USE_MEMORY_FUNCTIONS) + if(counterChanged) { + storeEventIndicators(eventParam); + } +#endif + } + return counterChanged; +} + +/** + * Performs clearing of indicator healing counter if conditions fulfilled. + * NOTE: This functions should only be called when event is FAILED. + * @param eventParam + * @param indAttrPtr + */ +static inline void handleHealingCounterOnFailed(const Dem_EventParameterType *eventParam, const Dem_IndicatorAttributeType *indAttrPtr) +{ +#if defined(DEM_HEALING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_CYCLE) + if( indicatorFailureCycleIsStarted(eventParam, indAttrPtr) ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter = 0; + } +#elif defined(DEM_HEALING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_OR_HEALING_CYCLE) + if( indicatorFailureCycleIsStarted(eventParam, indAttrPtr) || indicatorHealingCycleIsStarted(indAttrPtr)) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter = 0; + } +#elif defined(DEM_HEALING_COUNTER_CLEAR_ON_ALL_FAIL) + (void)eventParam;/*lint !e920*/ + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter = 0; +#else +#error "Dem: Unknown healing counter clear behavior" +#endif +} + +/** + * Handles updating of indicator failure counter and status bits + * @param eventParam + * @param eventStatusRecPtr + * @param eventStatus + * @return TRUE: counter was updated, FALSE: counter was not updated + */ +static boolean handleIndicators(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatusRecPtr, Dem_EventStatusType eventStatus) +{ + /* @req DEM506 */ + /* @req DEM510 */ + boolean cntrChanged = FALSE; + if( NULL != eventParam->EventClass->IndicatorAttribute ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventParam->EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL) { + switch(eventStatus) { + case DEM_EVENT_STATUS_FAILED: + if( indicatorFailureCycleIsStarted(eventParam, indAttrPtr) ) { + if( (0 == (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_FAILED_DURING_FAILURE_CYCLE)) && + (indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter < DEM_INDICATOR_CNTR_MAX) ) { + /* First fail during this failure cycle and incrementing failure counter would not overflow */ + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter++; + cntrChanged = TRUE; + } + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus |= INDICATOR_FAILED_DURING_FAILURE_CYCLE; + } + if( indicatorHealingCycleIsStarted(indAttrPtr) ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus |= INDICATOR_FAILED_DURING_HEALING_CYCLE; + } + break; + case DEM_EVENT_STATUS_PASSED: + if( indicatorFailureCycleIsStarted(eventParam, indAttrPtr) ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus |= INDICATOR_PASSED_DURING_FAILURE_CYCLE; + } + if( indicatorHealingCycleIsStarted(indAttrPtr) ) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus |= INDICATOR_PASSED_DURING_HEALING_CYCLE; + } + break; + default: + break; + } + if( DEM_EVENT_STATUS_FAILED == eventStatus ) { + handleHealingCounterOnFailed(eventParam, indAttrPtr); + } + indAttrPtr++; + } + /* @req DEM566 */ + if( warningIndicatorOnCriteriaFulfilled(eventParam)) { + eventStatusRecPtr->eventStatusExtended |= DEM_WARNING_INDICATOR_REQUESTED; + } + } + return cntrChanged; +} + +#if defined(DEM_USE_MEMORY_FUNCTIONS) +/** + * Stores indicators for an event in memory destined for NvRam + * @param eventParam + */ +static void storeEventIndicators(const Dem_EventParameterType *eventParam) +{ + const Dem_IndicatorAttributeType *indAttr; + if( NULL != eventParam->EventClass->IndicatorAttribute ) { + indAttr = eventParam->EventClass->IndicatorAttribute; + while( !indAttr->Arc_EOL) { + indicatorBuffer[indAttr->IndicatorBufferIndex].EventID = indicatorStatusBuffer[indAttr->IndicatorBufferIndex].EventID; + indicatorBuffer[indAttr->IndicatorBufferIndex].FailureCounter = indicatorStatusBuffer[indAttr->IndicatorBufferIndex].FailureCounter; + indicatorBuffer[indAttr->IndicatorBufferIndex].HealingCounter = indicatorStatusBuffer[indAttr->IndicatorBufferIndex].HealingCounter; + indicatorBuffer[indAttr->IndicatorBufferIndex].IndicatorId = indAttr->IndicatorId; + indAttr++; + } + } +} + +/** + * Merges indicator status read from NvRam with status held in ram + */ +static void mergeIndicatorBuffers(void) { + const Dem_EventParameterType *eventParam; + const Dem_IndicatorAttributeType *indAttr; + for(uint8 i = 0; i < DEM_NOF_EVENT_INDICATORS; i++) { + if(IS_VALID_EVENT_ID(indicatorBuffer[i].EventID) && IS_VALID_INDICATOR_ID(indicatorBuffer[i].IndicatorId)) { + /* Valid event and indicator. Check that it is a valid indicator for this event */ + eventParam = NULL; + lookupEventIdParameter(indicatorBuffer[i].EventID, &eventParam); + if((NULL != eventParam) && (NULL != eventParam->EventClass->IndicatorAttribute) ) { + indAttr = eventParam->EventClass->IndicatorAttribute; + while(!indAttr->Arc_EOL) { + if( indAttr->IndicatorId == indicatorBuffer[i].IndicatorId ) { + /* Update healing counter. */ + if( (0 != (indicatorStatusBuffer[indAttr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_FAILED_DURING_FAILURE_CYCLE)) || + (0 != (indicatorStatusBuffer[indAttr->IndicatorBufferIndex].OpCycleStatus & INDICATOR_FAILED_DURING_HEALING_CYCLE))) { + /* Failed at some point during PreInit. */ + indicatorStatusBuffer[indAttr->IndicatorBufferIndex].HealingCounter = 0; + } else { + indicatorStatusBuffer[indAttr->IndicatorBufferIndex].HealingCounter = indicatorBuffer[i].HealingCounter; + } + + /* Update failure counter */ + if( (DEM_INDICATOR_CNTR_MAX - indicatorBuffer[i].FailureCounter) > indicatorStatusBuffer[indAttr->IndicatorBufferIndex].FailureCounter) { + indicatorStatusBuffer[indAttr->IndicatorBufferIndex].FailureCounter += indicatorBuffer[i].FailureCounter; + } else { + indicatorStatusBuffer[indAttr->IndicatorBufferIndex].FailureCounter = DEM_INDICATOR_CNTR_MAX; + } + } + indAttr++; + } + } + } + } +#ifdef DEM_USE_MEMORY_FUNCTIONS + /* Transfer content of indicatorStatusBuffer to indicatorBuffer */ + eventParam = configSet->EventParameter; + while( !eventParam->Arc_EOL ) { + storeEventIndicators(eventParam); + eventParam++; + } + /* IMPROVEMENT: Only call this if the content of memory was changed */ + setIndicatorBlockChanged(); +#endif +} + +#endif +#endif +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +static void setEventTimeStamp(EventStatusRecType *eventStatusRecPtr) +{ + if( DEM_INITIALIZED == demState ) { + if( Event_TimeStamp >= DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT ) { + rearrangeEventTimeStamp(&Event_TimeStamp); + + } + eventStatusRecPtr->timeStamp = Event_TimeStamp; + Event_TimeStamp++; + } else { + eventStatusRecPtr->timeStamp = Event_TimeStamp; + if( Event_TimeStamp < DEM_MAX_TIMESTAMP_FOR_PRE_INIT ) { + Event_TimeStamp++; + } + } +} +#endif + +static void notifyEventStatusChange(const Dem_EventParameterType *eventParam, Dem_EventStatusExtendedType oldStatus, Dem_EventStatusExtendedType newStatus) +{ + uint8 j = 0; + if( (NULL != eventParam) && (NULL != eventParam->CallbackEventStatusChanged)) { + /* @req Dem016 */ /* @req Dem615 */ + while( !eventParam->CallbackEventStatusChanged[j].Arc_EOL ) { + if( eventParam->CallbackEventStatusChanged[j].UsePort ) { + (void)eventParam->CallbackEventStatusChanged[j].CallbackEventStatusChangedFnc.eventStatusChangedWithoutId(oldStatus, newStatus); + } else { + (void)eventParam->CallbackEventStatusChanged[j].CallbackEventStatusChangedFnc.eventStatusChangedWithId(eventParam->EventID, oldStatus, newStatus); + } + j++; + } + } + +#if defined(USE_RTE) && (DEM_GENERAL_EVENT_STATUS_CB == STD_ON) + /* @req Dem616 */ + (void)Rte_Call_GeneralCBStatusEvt_EventStatusChanged(eventParam->EventID, oldStatus, newStatus); +#endif + +#if (DEM_TRIGGER_DLT_REPORTS == STD_ON) + /* @req Dem517 */ + Dlt_DemTriggerOnEventStatus(eventParam->EventID, oldStatus, newStatus); +#endif +} + +static void notifyEventDataChanged(const Dem_EventParameterType *eventParam) { + /* @req DEM474 */ + if( (NULL != eventParam) && (NULL != eventParam->CallbackEventDataChanged)) { + /* @req Dem618 */ + if( eventParam->CallbackEventDataChanged->UsePort ) { + (void)eventParam->CallbackEventDataChanged->CallbackEventDataChangedFnc.eventDataChangedWithoutId(); + } else { + (void)eventParam->CallbackEventDataChanged->CallbackEventDataChangedFnc.eventDataChangedWithId(eventParam->EventID); + } + } + +#if defined(USE_RTE) && (DEM_GENERAL_EVENT_DATA_CB == STD_ON) + /* @req Dem619 */ + (void)Rte_Call_GeneralCBDataEvt_EventDataChanged(eventParam->EventID); +#endif +} + +static void setDefaultEventStatus(EventStatusRecType *eventStatusRecPtr) +{ + eventStatusRecPtr->eventId = DEM_EVENT_ID_NULL; + eventStatusRecPtr->eventParamRef = NULL; + eventStatusRecPtr->fdcInternal = 0; + eventStatusRecPtr->UDSFdc = 0; + eventStatusRecPtr->maxUDSFdc = 0; + eventStatusRecPtr->occurrence = 0; + eventStatusRecPtr->eventStatusExtended = DEM_DEFAULT_EVENT_STATUS; + eventStatusRecPtr->errorStatusChanged = FALSE; + eventStatusRecPtr->extensionDataChanged = FALSE; + eventStatusRecPtr->extensionDataStoreBitfield = 0; +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->failureCounter = 0; + eventStatusRecPtr->failedDuringFailureCycle = FALSE; + eventStatusRecPtr->passedDuringFailureCycle = FALSE; +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->agingCounter = 0; + eventStatusRecPtr->passedDuringAgingCycle = FALSE; + eventStatusRecPtr->failedDuringAgingCycle = FALSE; +#endif +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->timeStamp = 0; +#endif +} + +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) +/** + * Handles clearing of aging counter. Should only be called when operation cycle + * is start and event is qualified as FAILED + * @param eventParam + * @param eventStatusRecPtr + */ +static inline void handleAgingCounterOnFailed(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatusRecPtr) +{ +#if defined(DEM_AGING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_CYCLE) + if( operationCycleIsStarted(eventParam->EventClass->FailureCycleRef) ) { + eventStatusRecPtr->agingCounter = 0; + } +#elif defined(DEM_AGING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_OR_AGING_CYCLE) + if( operationCycleIsStarted(eventParam->EventClass->FailureCycleRef) || operationCycleIsStarted(eventParam->EventClass->AgingCycleRef)) { + eventStatusRecPtr->agingCounter = 0; + } +#elif defined(DEM_AGING_COUNTER_CLEAR_ON_ALL_FAIL) + (void)eventParam;/*lint !e920*/ + eventStatusRecPtr->agingCounter = 0; +#else +#error "Dem: Unknown aging counter clear behavior" +#endif +} +#endif + +/** + * Performs event updates when event is qualified as FAILED + * @param eventParam + * @param eventStatusRecPtr + */ +static inline void updateEventOnFAILED(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatusRecPtr) { + if (0 == (eventStatusRecPtr->eventStatusExtended & DEM_TEST_FAILED)) { + if( eventStatusRecPtr->occurrence < DEM_OCCURENCE_COUNTER_MAX ) { + eventStatusRecPtr->occurrence++;/* @req DEM523 *//* @req DEM524 *//* !req DEM625 */ + } + eventStatusRecPtr->errorStatusChanged = TRUE; + } +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + if( operationCycleIsStarted(eventParam->EventClass->AgingCycleRef) ) { + eventStatusRecPtr->failedDuringAgingCycle = TRUE; + } + + handleAgingCounterOnFailed(eventParam, eventStatusRecPtr); +#endif +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + /* Handle fault confirmation *//** @req DEM379.ConfirmedSet */ + handleFaultConfirmation(eventParam, eventStatusRecPtr); +#endif + /** @req DEM036 */ /** @req DEM379.PendingSet */ + eventStatusRecPtr->eventStatusExtended |= (DEM_TEST_FAILED | DEM_TEST_FAILED_THIS_OPERATION_CYCLE | DEM_TEST_FAILED_SINCE_LAST_CLEAR | DEM_PENDING_DTC); + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE); +} + +/** + * Performs event updates when event is qualified as PASSED + * @param eventParam + * @param eventStatusRecPtr + */ +static inline void updateEventOnPASSED(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatusRecPtr) { + if ( 0 != (eventStatusRecPtr->eventStatusExtended & DEM_TEST_FAILED) ) { + eventStatusRecPtr->errorStatusChanged = TRUE; + } + /** @req DEM036 */ + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED; + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE); +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + if( operationCycleIsStarted(eventParam->EventClass->AgingCycleRef) ) { + eventStatusRecPtr->passedDuringAgingCycle = TRUE; + } +#endif +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + if( operationCycleIsStarted(eventParam->EventClass->FailureCycleRef) ) { + eventStatusRecPtr->passedDuringFailureCycle = TRUE; + } +#endif +} +/* + * Procedure: updateEventStatusRec + * Description: Update the status of "eventId" + */ +static void updateEventStatusRec(const Dem_EventParameterType *eventParam, Dem_EventStatusType reportedEventStatus, EventStatusRecType *eventStatusRecPtr) +{ + /* IMPROVEMENT: !req DEM544 */ + Dem_EventStatusType eventStatus = reportedEventStatus; + + if (eventStatusRecPtr != NULL) { + + eventStatus = RunPredebounce(reportedEventStatus, eventStatusRecPtr, eventParam); + eventStatusRecPtr->errorStatusChanged = FALSE; + eventStatusRecPtr->extensionDataChanged = FALSE; + eventStatusRecPtr->indicatorDataChanged = FALSE; + eventStatusRecPtr->extensionDataStoreBitfield = 0; + +#if defined(USE_DEM_EXTENSION) + Dem_EventStatusExtendedType eventStatusExtendedBeforeUpdate = eventStatusRecPtr->eventStatusExtended; +#endif + + switch(eventStatus) { + case DEM_EVENT_STATUS_FAILED: + updateEventOnFAILED(eventParam, eventStatusRecPtr); + break; + case DEM_EVENT_STATUS_PASSED: + updateEventOnPASSED(eventParam, eventStatusRecPtr); + break; + default: + break; + } + +#if defined(DEM_USE_INDICATORS) + /** @req DEM379.WarningIndicatorSet */ + if(handleIndicators(eventParam, eventStatusRecPtr, eventStatus)) { + eventStatusRecPtr->indicatorDataChanged = TRUE; + } +#endif + +#if defined(USE_DEM_EXTENSION) + Dem_Extension_UpdateEventstatus(eventStatusRecPtr, eventStatusExtendedBeforeUpdate, eventStatus); +#endif + + // eventStatusRecPtr->maxUDSFdc = MAX(eventStatusRecPtr->maxUDSFdc, eventStatusRecPtr->UDSFdc); +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( eventStatusRecPtr->errorStatusChanged && (eventStatus == DEM_EVENT_STATUS_FAILED) ) { + /* Test just failed. Need to set timestamp */ + setEventTimeStamp(eventStatusRecPtr); + } +#endif + } +} + + +/* + * Procedure: mergeEventStatusRec + * Description: Update the occurrence counter of status, if not exist a new record is created + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +static boolean mergeEventStatusRec(const EventRecType *eventRec) +{ + EventStatusRecType *eventStatusRecPtr; + const Dem_EventParameterType *eventParam; + boolean statusChanged = FALSE; + + // Lookup event ID + lookupEventStatusRec(eventRec->EventData.eventId, &eventStatusRecPtr); + lookupEventIdParameter(eventRec->EventData.eventId, &eventParam); + + if (eventStatusRecPtr != NULL) { + // Update occurrence counter. + eventStatusRecPtr->occurrence += eventRec->EventData.occurrence; + // Merge event status extended with stored + // TEST_FAILED_SINCE_LAST_CLEAR should be set if set if set in either + eventStatusRecPtr->eventStatusExtended |= (Dem_EventStatusExtendedType)(eventRec->EventData.eventStatusExtended & DEM_TEST_FAILED_SINCE_LAST_CLEAR); + // DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR should cleared if cleared in either + if((eventRec->EventData.eventStatusExtended & eventStatusRecPtr->eventStatusExtended & DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR) == 0u) { + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~(Dem_EventStatusExtendedType)DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR; + } + + // DEM_PENDING_DTC and DEM_CONFIRMED_DTC should be set if set in either + eventStatusRecPtr->eventStatusExtended |= (Dem_EventStatusExtendedType)(eventRec->EventData.eventStatusExtended & (DEM_PENDING_DTC | DEM_CONFIRMED_DTC)); + // DEM_WARNING_INDICATOR_REQUESTED should be set criteria fulfilled +#if defined(DEM_USE_INDICATORS) + if( warningIndicatorOnCriteriaFulfilled(eventParam)) { + eventStatusRecPtr->eventStatusExtended |= DEM_WARNING_INDICATOR_REQUESTED; + } +#endif +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + // Update confirmation counter + if( (DEM_FAILURE_CNTR_MAX - eventRec->EventData.failureCounter) < eventStatusRecPtr->failureCounter) { + /* Would overflow */ + eventStatusRecPtr->failureCounter = DEM_FAILURE_CNTR_MAX; + } else { + eventStatusRecPtr->failureCounter += eventRec->EventData.failureCounter; + } + + if( (NULL != eventParam) && faultConfirmationCriteriaFulfilled(eventParam, eventStatusRecPtr) ) { + eventStatusRecPtr->eventStatusExtended |= (Dem_EventStatusExtendedType)DEM_CONFIRMED_DTC; + } +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + // Update confirmation counter + if( (DEM_AGING_CNTR_MAX - eventRec->EventData.agingCounter) < eventStatusRecPtr->agingCounter) { + /* Would overflow */ + eventStatusRecPtr->agingCounter = DEM_AGING_CNTR_MAX; + } else { + eventStatusRecPtr->agingCounter += eventRec->EventData.agingCounter; + } + +#endif +#if (DEM_TEST_FAILED_STORAGE == STD_ON) + /* @req DEM387 */ + /* @req DEM388 */ + /* @req DEM525 */ + if( 0 != (eventStatusRecPtr->eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE) ) { + /* Test has not been completed this operation cycle. Set test failed bit as in stored */ + eventStatusRecPtr->eventStatusExtended |= (eventRec->EventData.eventStatusExtended & DEM_TEST_FAILED); + } +#endif + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( !(eventStatusRecPtr->eventStatusExtended & DEM_TEST_FAILED_THIS_OPERATION_CYCLE) ) { + /* Test has not failed this operation cycle. Means that the that the timestamp + * should be set to the one read from NvRam */ + eventStatusRecPtr->timeStamp = eventRec->EventData.timeStamp; + } +#endif + + if( (eventStatusRecPtr->occurrence != eventRec->EventData.occurrence) || +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + (eventStatusRecPtr->failureCounter != eventRec->EventData.failureCounter) || +#endif + (GET_STORED_STATUS_BITS(eventStatusRecPtr->eventStatusExtended) != GET_STORED_STATUS_BITS(eventRec->EventData.eventStatusExtended)) ) { + statusChanged = TRUE; + } + + if( 0 == (eventStatusRecPtr->eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE) ) { + /* Test was completed during preInit, means that the eventStatus was changed in some way */ + Dem_EventStatusExtendedType oldStatus = (Dem_EventStatusExtendedType)(GET_STORED_STATUS_BITS(eventRec->EventData.eventStatusExtended)); + notifyEventStatusChange(eventStatusRecPtr->eventParamRef, oldStatus, eventStatusRecPtr->eventStatusExtended); + } + } + + return statusChanged; +} + +/* + * Procedure: resetEventStatusRec + * Description: Reset the status record of "eventParam->eventId" from "eventStatusBuffer". + */ +static void resetEventStatusRec(const Dem_EventParameterType *eventParam) +{ + EventStatusRecType *eventStatusRecPtr; + + // Lookup event ID + lookupEventStatusRec(eventParam->EventID, &eventStatusRecPtr); + + if (eventStatusRecPtr != NULL) { + // Reset event record + resetDebounceCounter(eventStatusRecPtr); + eventStatusRecPtr->eventStatusExtended = DEM_DEFAULT_EVENT_STATUS;/** @req DEM385 */ + eventStatusRecPtr->errorStatusChanged = FALSE; + eventStatusRecPtr->occurrence = 0; +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->failureCounter = 0; + eventStatusRecPtr->failedDuringFailureCycle = FALSE; + eventStatusRecPtr->passedDuringFailureCycle = FALSE; +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->agingCounter = 0; + eventStatusRecPtr->failedDuringAgingCycle = FALSE; + eventStatusRecPtr->passedDuringAgingCycle = FALSE; +#endif +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->timeStamp = 0; +#endif + } + +} +#endif +/* + * Procedure: getEventStatusRec + * Description: Returns the status record of "eventId" in "eventStatusRec" + */ +#if 1 +static void getEventStatusRec(Dem_EventIdType eventId, EventStatusRecType *eventStatusRec) +{ + EventStatusRecType *eventStatusRecPtr; + + // Lookup event ID + lookupEventStatusRec(eventId, &eventStatusRecPtr); + + if (eventStatusRecPtr != NULL) { + // Copy the record + memcpy(eventStatusRec, eventStatusRecPtr, sizeof(EventStatusRecType)); + } + else { + eventStatusRec->eventId = DEM_EVENT_ID_NULL; + } +} +#endif +/** + * Sets overflow indication for a specific memory + * @param origin + * @param overflow + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +static void setOverflowIndication(Dem_DTCOriginType origin, boolean overflow) +{ + switch (origin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + priMemOverflow = overflow; + if(overflow != priMemEventBuffer[PRI_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow) { + priMemEventBuffer[PRI_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.magic = ADMIN_MAGIC; + priMemEventBuffer[PRI_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow = overflow; + setEventBlockChanged(origin); + } +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + secMemOverflow = overflow; + if( overflow != secMemEventBuffer[SEC_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow ) { + secMemEventBuffer[SEC_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.magic = ADMIN_MAGIC; + secMemEventBuffer[SEC_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow = overflow; + setEventBlockChanged(origin); + } +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + break; + } +} +#endif + +/** + * Returns the overflow indication for a specific memory + * @param origin + * @return E_OK: Operation successful, E_NOT_OK: Operation failed + */ +static Std_ReturnType getOverflowIndication(Dem_DTCOriginType origin, boolean *Overflow) +{ + Std_ReturnType ret = E_OK; + switch (origin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + *Overflow = priMemOverflow; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + *Overflow = secMemOverflow; +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + default: + /* Not yet supported */ + ret = E_NOT_OK; + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + } + return ret; +} + +/** + * Reads internal element + * @param eventParameter + * @param elementType + * @param buf + * @param size + */ +static void getInternalElement( const Dem_EventParameterType *eventParameter, Dem_InternalDataElementType elementType, uint8* buf, uint16 size ) +{ + /* !req DEM592 *//* SIGNIFICANCE not supported */ + EventStatusRecType *eventStatusRec; + lookupEventStatusRec(eventParameter->EventID, &eventStatusRec); + + if( (DEM_EVENT_ID_NULL != eventStatusRec->eventId) && (size > 0) ) { + memset(buf, 0, size); + switch(elementType) { + case DEM_OCCCTR: + /* @req DEM471 */ + if(1 == size) { + buf[0] = (uint8)MIN(eventStatusRec->occurrence, 0xFF); + } else { + buf[size - 2] = (eventStatusRec->occurrence & 0xff00u) >> 8u; + buf[size - 1] = eventStatusRec->occurrence & 0xffu; + } + break; + case DEM_FAULTDETCTR: + /* @req OEM_DEM_10185 */ + buf[size - 1] = (uint8)eventStatusRec->UDSFdc; + break; + case DEM_MAXFAULTDETCTR: + buf[size - 1] = (uint8)eventStatusRec->maxUDSFdc; + break; + case DEM_OVFLIND: + { + /* @req DEM473 */ + boolean ovflw = FALSE; + if( E_OK == getOverflowIndication(eventParameter->EventClass->EventDestination, &ovflw) ) { + buf[size - 1] = ovflw ? 1 : 0; + } else { + buf[size - 1] = 0; + } + } + break; +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + case DEM_AGINGCTR: + { + /* @req DEM472 *//* !req DEM644 *//* !req DEM647 */ + /* IMPROVEMENT: External aging.. */ + if( eventParameter->EventClass->AgingAllowed) { + buf[size - 1] = eventStatusRec->agingCounter; + } else { + /* @req DEM646 */ + /* set to 0 by memset above */ + } + } + break; +#endif +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + case DEM_CONFIRMATIONCNTR: + buf[size - 1] = eventStatusRec->failureCounter; + break; +#endif + default: +#if defined(USE_DEM_EXTENSION) + Dem_Extension_GetExtendedDataInternalElement(eventParameter->EventID, elementType, buf, size); +#endif + break; + } + } +} + +/* + * Procedure: lookupDtcEvent + * Description: Returns TRUE if the DTC was found and "eventStatusRec" points + * to the event record found. + */ +/* @req 4.2.2/DEM_00915 */ +static boolean lookupEventOfUdsDTC(uint32 dtc, EventStatusRecType **eventStatusRec) +{ + boolean dtcFound = FALSE; + uint16 i; + + *eventStatusRec = NULL; + + for (i = 0; (i < DEM_MAX_NUMBER_EVENT) && (dtcFound==FALSE); i++) { + if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) { + if (eventStatusBuffer[i].eventParamRef->DTCClassRef != NULL) { + + /* Check DTC. Ignore suppressed DTCs *//* @req DEM587 */ + if ((eventStatusBuffer[i].eventParamRef->DTCClassRef->DTCRef->UDSDTC == dtc) && + (DTCIsAvailable(eventStatusBuffer[i].eventParamRef->DTCClassRef))) { + *eventStatusRec = &eventStatusBuffer[i]; + dtcFound = TRUE; + } + } + } + } + + return dtcFound; +} + +/* + * Procedure: matchEventWithDtcFilter + * Description: Returns TRUE if the event pointed by "event" fulfill + * the "dtcFilter" global filter settings. + */ +static boolean matchEventWithDtcFilter(const EventStatusRecType *eventRec) +{ + boolean dtcMatch = FALSE; + + // Check status + if ((dtcFilter.dtcStatusMask == DEM_DTC_STATUS_MASK_ALL) || (0!= (eventRec->eventStatusExtended & dtcFilter.dtcStatusMask))) { + + if ((eventRec->eventParamRef != NULL) && + (checkDtcKind(dtcFilter.dtcKind, eventRec->eventParamRef)==TRUE) && + (checkDtcOrigin(dtcFilter.dtcOrigin, eventRec->eventParamRef)==TRUE)) { + + // Check severity + if ((dtcFilter.filterWithSeverity == DEM_FILTER_WITH_SEVERITY_NO) || + ((dtcFilter.filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES) && (checkDtcSeverityMask(dtcFilter.dtcSeverityMask, eventRec->eventParamRef)))) { + + // Check fault detection counter + if ((dtcFilter.filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_NO) || + ((dtcFilter.filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_YES) && (checkDtcFaultDetectionCounter(eventRec->eventParamRef->EventID)))) { + + /* Check the DTC */ + if ( (eventRec->eventParamRef->DTCClassRef != NULL) && + DTCIsAvailable(eventRec->eventParamRef->DTCClassRef) && + eventHasDTCOnFormat(eventRec->eventParamRef, dtcFilter.dtcFormat) ) { + dtcMatch = TRUE; + } + } + } + } + } + + return dtcMatch; +} + +/* Function: eventDTCRecordDataUpdateDisabled + * Description: Checks if update of event related data (extended data or freezeframe data) has been disabled + */ +static boolean eventDTCRecordDataUpdateDisabled(const Dem_EventParameterType *eventParam) +{ + boolean disabled = FALSE; + if( (NO_DTC_DISABLED != DTCRecordDisabled.DTC) && /* There is a disabled DTC */ + (NULL != eventParam) && /* Argument ok */ + (NULL != eventParam->DTCClassRef) && /* Event has a DTC */ + (DEM_NO_DTC != eventParam->DTCClassRef->DTCRef->UDSDTC) && /* And a DTC on UDS format */ + (DTCRecordDisabled.DTC == eventParam->DTCClassRef->DTCRef->UDSDTC) && /* The disabled DTC is the DTC of the event */ + (DTCRecordDisabled.Origin == eventParam->EventClass->EventDestination)) { /* The disabled origin is the origin of the event */ + /* DTC record update for this event is disabled */ + disabled = TRUE; + } + return disabled; +} + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +/** + * Returns whether event is considered passive or not + * @param eventId + * @return TRUE: Event passive, FALSE: Event NOT passive + */ +static boolean getEventPassive(Dem_EventIdType eventId) +{ + boolean eventPassive = FALSE; + Dem_EventStatusExtendedType eventStatus; + if(E_OK == getEventStatus(eventId, &eventStatus)) { +#if (DEM_TEST_FAILED_STORAGE == STD_ON) + eventPassive = (0 == (eventStatus & DEM_TEST_FAILED)); +#else + eventPassive = (0 == (eventStatus & (DEM_TEST_FAILED | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE))); +#endif +#if defined(CFG_DEM_TREAT_CONFIRMED_EVENTS_AS_ACTIVE) + eventPassive = (0 != (eventStatus & DEM_CONFIRMED_DTC)) ? FALSE:eventPassive; +#endif + } + return eventPassive; + +} + +static uint8 getEventPriority(Dem_EventIdType eventId) +{ + uint8 priority = 0xFF; + + uint16 indx = 0; + const Dem_EventParameterType *eventIdParamList = configSet->EventParameter; + while( !eventIdParamList[indx].Arc_EOL ) { + if( eventIdParamList[indx].EventID == eventId ) { + priority = eventIdParamList[indx].EventClass->EventPriority; + break; + } + indx++; + } + + return priority; +} + +#if ( DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM || DEM_FF_DATA_IN_PRE_INIT) +static Std_ReturnType getFFEventForDisplacement(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *ffBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + /* See figure 25 in ASR 4.0.3 */ + /* @req DEM403 */ + /* @req DEM404 */ + /* @req DEM405 */ + /* @req DEM406 */ + /* IMPROVEMENT: How do we handle the case when it is an OBD freeze frame that should be stored? + * Should they be handled in the same way as "normal" freeze frames? */ + Std_ReturnType ret = E_NOT_OK; + uint32 removeCandidateIndex = 0; + uint32 oldestPassive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint32 oldestActive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint8 eventPrio = 0xFF; + boolean eventPassive = FALSE; + boolean passiveCandidateFound = FALSE; + boolean activeCandidateFound = FALSE; + boolean eventDataRemovalProhibited = FALSE; + const Dem_EventParameterType *candidateEventParam = NULL; + for( uint32 i = 0; i < bufferSize; i++ ) { + if( (DEM_EVENT_ID_NULL != ffBuffer[i].eventId) && (eventParam->EventID != ffBuffer[i].eventId) && (DEM_FREEZE_FRAME_OBD != ffBuffer[i].kind) ) { + if(NO_DTC_DISABLED != DTCRecordDisabled.DTC) { + lookupEventIdParameter(ffBuffer[i].eventId, &candidateEventParam); + eventDataRemovalProhibited = eventDTCRecordDataUpdateDisabled(candidateEventParam); + } else { + eventDataRemovalProhibited = FALSE; + } + if(!eventDataRemovalProhibited) { + /* Check if priority if the event is higher or equal (low numerical value of priority means high priority..) *//* @req DEM383 */ + eventPrio = getEventPriority(ffBuffer[i].eventId); + eventPassive = getEventPassive(ffBuffer[i].eventId); + /* IMPROVEMENT: Remove the one with lowest priority? */ + if( (eventParam->EventClass->EventPriority <= eventPrio) && eventPassive && (oldestPassive_TimeStamp > ffBuffer[i].timeStamp) ) { + /* This event has lower or equal priority to the reported event, it is passive + * and it is the oldest currently found. A candidate for removal. */ + oldestPassive_TimeStamp = ffBuffer[i].timeStamp; + removeCandidateIndex = i; + passiveCandidateFound = TRUE; + + } + if( !passiveCandidateFound ) { + /* Currently, a passive event with lower or equal priority has not been found. + * Check if the priority is less than for the reported event. Store the oldest. */ + if( (eventParam->EventClass->EventPriority < eventPrio) && (oldestActive_TimeStamp > ffBuffer[i].timeStamp) ) { + oldestActive_TimeStamp = ffBuffer[i].timeStamp; + removeCandidateIndex = i; + activeCandidateFound = TRUE; + } + } + } + } + } + + if( passiveCandidateFound || activeCandidateFound) { + *eventToRemove = ffBuffer[removeCandidateIndex].eventId; + ret = E_OK; + } + return ret; + +} +#endif /* DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM || DEM_FF_DATA_IN_PRE_INIT */ + +static Std_ReturnType getExtDataEventForDisplacement(const Dem_EventParameterType *eventParam, const ExtDataRecType *extDataBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + /* See figure 25 in ASR 4.0.3 */ + /* @req DEM403 */ + /* @req DEM404 */ + /* @req DEM405 */ + /* @req DEM406 */ + Std_ReturnType ret = E_NOT_OK; + uint32 removeCandidateIndex = 0; + uint32 oldestPassive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint32 oldestActive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint8 eventPrio = 0xFF; + boolean eventPassive = FALSE; + boolean passiveCandidateFound = FALSE; + boolean activeCandidateFound = FALSE; + boolean eventDataRemovalProhibited = FALSE; + const Dem_EventParameterType *candidateEventParam = NULL; + for( uint32 i = 0; i < bufferSize; i++ ) { + if( DEM_EVENT_ID_NULL != extDataBuffer[i].eventId ) { + /* Check if we are allowed to remove data for this event */ + if(NO_DTC_DISABLED != DTCRecordDisabled.DTC) { + lookupEventIdParameter(extDataBuffer[i].eventId, &candidateEventParam); + eventDataRemovalProhibited = eventDTCRecordDataUpdateDisabled(candidateEventParam); + } else { + eventDataRemovalProhibited = FALSE; + } + if(!eventDataRemovalProhibited) { + /* Check if priority if the event is higher or equal (low numerical value of priority means high priority..) *//* @req DEM383 */ + eventPrio = getEventPriority(extDataBuffer[i].eventId); + eventPassive = getEventPassive(extDataBuffer[i].eventId); + if( (eventParam->EventClass->EventPriority <= eventPrio) && eventPassive && (oldestPassive_TimeStamp > extDataBuffer[i].timeStamp) ) { + /* This event has lower or equal priority to the reported event, it is passive + * and it is the oldest currently found. A candidate for removal. */ + oldestPassive_TimeStamp = extDataBuffer[i].timeStamp; + removeCandidateIndex = i; + passiveCandidateFound = TRUE; + + } + if( !passiveCandidateFound ) { + /* Currently, a passive event with lower or equal priority has not been found. + * Check if the priority is less than for the reported event. Store the oldest. */ + if( (eventParam->EventClass->EventPriority < eventPrio) && (oldestActive_TimeStamp > extDataBuffer[i].timeStamp) ) { + oldestActive_TimeStamp = extDataBuffer[i].timeStamp; + removeCandidateIndex = i; + activeCandidateFound = TRUE; + } + } + } + } + } + + if( passiveCandidateFound || activeCandidateFound) { + *eventToRemove = extDataBuffer[removeCandidateIndex].eventId; + ret = E_OK; + } + return ret; +} +#ifdef DEM_USE_MEMORY_FUNCTIONS +static Std_ReturnType getEventForDisplacement(const Dem_EventParameterType *eventParam, const EventRecType *eventBuffer, + uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + /* See figure 25 in ASR 4.0.3 */ + /* @req DEM403 */ + /* @req DEM404 */ + /* @req DEM405 */ + /* @req DEM406 */ + Std_ReturnType ret = E_NOT_OK; + uint32 removeCandidateIndex = 0; + uint32 oldestPassive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint32 oldestActive_TimeStamp = DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT; + uint8 eventPrio = 0xFF; + boolean eventPassive = FALSE; + boolean passiveCandidateFound = FALSE; + boolean activeCandidateFound = FALSE; + boolean eventDataRemovalProhibited = FALSE; + const Dem_EventParameterType *candidateEventParam = NULL; + for( uint32 i = 0; i < bufferSize; i++ ) { + if( DEM_EVENT_ID_NULL != eventBuffer[i].EventData.eventId ) { + if(NO_DTC_DISABLED != DTCRecordDisabled.DTC) { + lookupEventIdParameter(eventBuffer[i].EventData.eventId, &candidateEventParam); + eventDataRemovalProhibited = eventDTCRecordDataUpdateDisabled(candidateEventParam); + } else { + eventDataRemovalProhibited = FALSE; + } + if(!eventDataRemovalProhibited) { + /* Check if priority if the event is higher or equal (low numerical value of priority means high priority..) *//* @req DEM383 */ + eventPrio = getEventPriority(eventBuffer[i].EventData.eventId); + eventPassive = getEventPassive(eventBuffer[i].EventData.eventId); + if( (eventParam->EventClass->EventPriority <= eventPrio) && eventPassive && (oldestPassive_TimeStamp > eventBuffer[i].EventData.timeStamp) ) { + /* This event has lower or equal priority to the reported event, it is passive + * and it is the oldest currently found. A candidate for removal. */ + oldestPassive_TimeStamp = eventBuffer[i].EventData.timeStamp; + removeCandidateIndex = i; + passiveCandidateFound = TRUE; + + } + if( !passiveCandidateFound ) { + /* Currently, a passive event with lower or equal priority has not been found. + * Check if the priority is less than for the reported event. Store the oldest. */ + if( (eventParam->EventClass->EventPriority < eventPrio) && (oldestActive_TimeStamp > eventBuffer[i].EventData.timeStamp) ) { + oldestActive_TimeStamp = eventBuffer[i].EventData.timeStamp; + removeCandidateIndex = i; + activeCandidateFound = TRUE; + } + } + } + } + } + + if( passiveCandidateFound || activeCandidateFound) { + *eventToRemove = eventBuffer[removeCandidateIndex].EventData.eventId; + ret = E_OK; + } + return ret; +} +#endif +/* + * Functions for rearranging timestamps + * */ +#if (DEM_UNIT_TEST == STD_ON) +void rearrangeFreezeFrameTimeStamp(uint32 *timeStamp) +#else +static void rearrangeFreezeFrameTimeStamp(uint32 *timeStamp ) +#endif +{ + FreezeFrameRecType temp; + uint32 i; + uint32 j = 0; + uint32 k = 0; + uint32 bufferIndex; + + /* These two arrays are looped below must have the same size */ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM && (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM + uint32 ffBufferSizes[2] = {DEM_MAX_NUMBER_FF_DATA_PRI_MEM, DEM_MAX_NUMBER_FF_DATA_SEC_MEM}; + FreezeFrameRecType* ffBuffers[2] = {priMemFreezeFrameBuffer, secMemFreezeFrameBuffer}; + uint32 nofSupportedDestinations = 2; +#elif (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON && DEM_FF_DATA_IN_PRI_MEM) + uint32 ffBufferSizes[1] = {DEM_MAX_NUMBER_FF_DATA_PRI_MEM}; + FreezeFrameRecType* ffBuffers[1] = {priMemFreezeFrameBuffer}; + uint32 nofSupportedDestinations = 1; +#elif (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM + uint32 ffBufferSizes[1] = {DEM_MAX_NUMBER_FF_DATA_SEC_MEM}; + FreezeFrameRecType* ffBuffers[1] = {secMemFreezeFrameBuffer}; + uint32 nofSupportedDestinations = 1; +#else + uint32 ffBufferSizes[1] = {0}; + FreezeFrameRecType* ffBuffers[1] = {NULL}; + uint32 nofSupportedDestinations = 0; +#endif + + for (bufferIndex = 0; bufferIndex < nofSupportedDestinations; bufferIndex++) { + + FreezeFrameRecType* ffBuffer = ffBuffers[bufferIndex]; + uint32 ffBufferSize = ffBufferSizes[bufferIndex]; + + /* Bubble sort:rearrange ffBuffer from little to big */ + for(i = 0; i < ffBufferSize; i++){ + if(ffBuffer[i].eventId != DEM_EVENT_ID_NULL){ + for( j = ffBufferSize - 1; j > i; j--){ + if(ffBuffer[j].eventId != DEM_EVENT_ID_NULL){ + if(ffBuffer[i].timeStamp > ffBuffer[j].timeStamp){ + //exchange buffer data + memcpy(&temp,&ffBuffer[i],sizeof(FreezeFrameRecType)); + memcpy(&ffBuffer[i],&ffBuffer[j],sizeof(FreezeFrameRecType)); + memcpy(&ffBuffer[j],&temp,sizeof(FreezeFrameRecType)); + } + + } + + } + ffBuffer[i].timeStamp = k++; + } + } + } + + /* update the current timeStamp */ + *timeStamp = k; + +} +#if (DEM_UNIT_TEST == STD_ON) +void rearrangeExtDataTimeStamp(uint32 *timeStamp) +#else +static void rearrangeExtDataTimeStamp(uint32 *timeStamp) +#endif +{ + ExtDataRecType temp; + uint32 i; + uint32 j = 0; + uint32 k = 0; + uint32 bufferIndex; + + /* These two arrays are looped below must have the same size */ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_PRI_MEM && (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_SEC_MEM + uint32 extBufferSizes[2] = {DEM_MAX_NUMBER_EXT_DATA_PRI_MEM, DEM_MAX_NUMBER_EXT_DATA_SEC_MEM}; + ExtDataRecType* extBuffers[2] = {priMemExtDataBuffer, secMemExtDataBuffer}; + uint32 nofDestinations = 2; +#elif (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON && DEM_EXT_DATA_IN_PRI_MEM) + uint32 extBufferSizes[1] = {DEM_MAX_NUMBER_EXT_DATA_PRI_MEM}; + ExtDataRecType* extBuffers[1] = {priMemExtDataBuffer}; + uint32 nofDestinations = 1; +#elif (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON && DEM_EXT_DATA_IN_SEC_MEM) + uint32 extBufferSizes[1] = {DEM_MAX_NUMBER_EXT_DATA_SEC_MEM}; + ExtDataRecType* extBuffers[1] = {secMemExtDataBuffer}; + uint32 nofDestinations = 1; +#else + uint32 extBufferSizes[1] = {0}; + ExtDataRecType* extBuffers[1] = {NULL}; + uint32 nofDestinations = 0; +#endif + + for (bufferIndex = 0; bufferIndex < nofDestinations; bufferIndex++) { + + ExtDataRecType* extBuffer = extBuffers[bufferIndex]; + uint32 extBufferSize = extBufferSizes[bufferIndex]; + + /* Bubble sort:rearrange Buffer from little to big */ + for( i = 0; i < extBufferSize; i++ ){ + if( DEM_EVENT_ID_NULL != extBuffer[i].eventId ){ + for( j = extBufferSize - 1; j > i; j-- ){ + if( DEM_EVENT_ID_NULL != extBuffer[j].eventId ){ + if( extBuffer[i].timeStamp > extBuffer[j].timeStamp ){ + //exchange buffer data + memcpy(&temp, &extBuffer[i], sizeof(ExtDataRecType)); + memcpy(&extBuffer[i], &extBuffer[j], sizeof(ExtDataRecType)); + memcpy(&extBuffer[j], &temp, sizeof(ExtDataRecType)); + } + } + } + extBuffer[i].timeStamp = k++; + } + } + } + + /* update the current timeStamp */ + *timeStamp = k; +} + + +#if (DEM_UNIT_TEST == STD_ON) +void rearrangeEventTimeStamp(uint32 *timeStamp) +#else +static void rearrangeEventTimeStamp(uint32 *timeStamp) +#endif +{ + FreezeFrameRecType temp; + uint32 bufferIndex; + uint32 i; + uint32 j = 0; + uint32 k = 0; + + /* These two arrays are looped below must have the same size */ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + uint32 eventBufferSizes[2] = {DEM_MAX_NUMBER_EVENT_ENTRY_PRI, DEM_MAX_NUMBER_EVENT_ENTRY_SEC}; + EventRecType* eventBuffers[2] = {priMemEventBuffer, secMemEventBuffer}; + uint32 nofDestinations = 2; +#elif (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + uint32 eventBufferSizes[1] = {DEM_MAX_NUMBER_EVENT_ENTRY_PRI}; + EventRecType* eventBuffers[1] = {priMemEventBuffer}; + uint32 nofDestinations = 1; +#elif (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + uint32 eventBufferSizes[1] = {DEM_MAX_NUMBER_EVENT_ENTRY_SEC}; + EventRecType* eventBuffers[1] = {secMemEventBuffer}; + uint32 nofDestinations = 1; +#else + uint32 eventBufferSizes[1] = {0}; + EventRecType* eventBuffers[1] = {NULL}; + uint32 nofDestinations = 0; +#endif + + for (bufferIndex = 0; bufferIndex < nofDestinations; bufferIndex++) { + + EventRecType* eventBuffer = eventBuffers[bufferIndex]; + uint32 eventBufferSize = eventBufferSizes[bufferIndex]; + + /* Bubble sort:rearrange event buffer from little to big */ + for( i = 0; i < eventBufferSize; i++ ){ + if( DEM_EVENT_ID_NULL != eventBuffer[i].EventData.eventId ){ + for( j = (eventBufferSize - 1); j > i; j-- ) { + if( DEM_EVENT_ID_NULL != eventBuffer[j].EventData.eventId ) { + if( eventBuffer[i].EventData.timeStamp > eventBuffer[j].EventData.timeStamp ) { + //exchange buffer data + memcpy(&temp, &eventBuffer[i].EventData, sizeof(EventRecType)); + memcpy(&eventBuffer[i].EventData, &eventBuffer[j].EventData, sizeof(EventRecType)); + memcpy(&eventBuffer[j].EventData, &temp, sizeof(EventRecType)); + } + } + } + eventBuffer[i].EventData.timeStamp = k++; + } + } + } + + /* update the current timeStamp */ + *timeStamp = k; +} + +/* + * Functions for initializing timestamps + * */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +static void initCurrentFreezeFrameTimeStamp(uint32 *timeStampPtr) +{ +#if ( DEM_FF_DATA_IN_PRE_INIT ) + uint32 highestTimeStamp = 0; + + /* Rearrange freeze frames */ + rearrangeFreezeFrameTimeStamp(timeStampPtr); + + for (uint16 i = 0; i highestTimeStamp ) { + highestTimeStamp = preInitFreezeFrameBuffer[i].timeStamp; + } + } + } + *timeStampPtr = highestTimeStamp + 1; +#endif +} + +static void initCurrentExtDataTimeStamp(uint32 *timeStampPtr) +{ +#if ( DEM_EXT_DATA_IN_PRE_INIT && DEM_FF_DATA_IN_PRE_INIT ) + uint32 highestTimeStamp = 0; + + /* Rearrange extended data in primary memory */ + rearrangeExtDataTimeStamp(timeStampPtr); + + /* Increment the timestamps in the pre init ext data buffer */ + for (uint16 i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++){ + if( DEM_EVENT_ID_NULL != preInitExtDataBuffer[i].eventId ){ + preInitExtDataBuffer[i].timeStamp += *timeStampPtr; + if( preInitExtDataBuffer[i].timeStamp > highestTimeStamp ) { + highestTimeStamp = preInitExtDataBuffer[i].timeStamp; + } + } + } + *timeStampPtr = highestTimeStamp + 1; +#endif +} + +static void initCurrentEventTimeStamp(uint32 *timeStampPtr) +{ + uint32 highestTimeStamp = 0; + + /* Rearrange events */ + rearrangeEventTimeStamp(timeStampPtr); + + for (uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++){ + if( DEM_EVENT_ID_NULL != eventStatusBuffer[i].eventId ){ + eventStatusBuffer[i].timeStamp += *timeStampPtr; + if( eventStatusBuffer[i].timeStamp > highestTimeStamp ) { + highestTimeStamp = eventStatusBuffer[i].timeStamp; + } + } + } + *timeStampPtr = highestTimeStamp + 1; +} +#endif +#endif /* DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL */ + +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static boolean lookupFreezeFrameForDisplacementPreInit(const Dem_EventParameterType *eventParam, FreezeFrameRecType **freezeFrame) +{ + boolean freezeFrameFound = FALSE; + Dem_EventIdType eventToRemove = DEM_EVENT_ID_NULL; + +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) + Dem_Extension_GetFFEventForDisplacement(eventParam, preInitFreezeFrameBuffer, DEM_MAX_NUMBER_FF_DATA_PRE_INIT, &eventToRemove); +#elif defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( E_OK != getFFEventForDisplacement(eventParam, preInitFreezeFrameBuffer, DEM_MAX_NUMBER_FF_DATA_PRE_INIT, &eventToRemove) ) { + eventToRemove = DEM_EVENT_ID_NULL; + } +#else +#warning Unsupported displacement +#endif + if( DEM_EVENT_ID_NULL != eventToRemove ) { + /* Freeze frame for a less significant event was found. + * Find the all entries in pre init freeze frame buffer and remove these. */ + for (uint16 indx = 0; (indx < DEM_MAX_NUMBER_FF_DATA_PRE_INIT); indx++) { + if( preInitFreezeFrameBuffer[indx].eventId == eventToRemove ) { + memset(&preInitFreezeFrameBuffer[indx], 0, sizeof(FreezeFrameRecType)); + if( !freezeFrameFound ) { + *freezeFrame = &preInitFreezeFrameBuffer[indx]; + freezeFrameFound = TRUE; + } + } + } +#if defined(USE_DEM_EXTENSION) + if( freezeFrameFound ) { + Dem_Extension_EventFreezeFrameDataDisplaced(eventToRemove); + } +#endif + } else { + /* Buffer is full and the currently stored data is more significant */ + } + return freezeFrameFound; +} +#endif + +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if ( DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM || DEM_FF_DATA_IN_PRE_INIT) +static boolean lookupFreezeFrameForDisplacement(const Dem_EventParameterType *eventParam, FreezeFrameRecType **freezeFrame, + FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize) +{ + boolean freezeFrameFound = FALSE; + Dem_EventIdType eventToRemove = DEM_EVENT_ID_NULL; + const Dem_EventParameterType *eventToRemoveParam = NULL; + +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) + Dem_Extension_GetFFEventForDisplacement(eventParam, freezeFrameBuffer, freezeFrameBufferSize, &eventToRemove); +#elif defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( E_OK != getFFEventForDisplacement(eventParam, freezeFrameBuffer, freezeFrameBufferSize, &eventToRemove) ) { + eventToRemove = DEM_EVENT_ID_NULL; + } +#else +#warning Unsupported displacement +#endif + if( DEM_EVENT_ID_NULL != eventToRemove ) { + /* Freeze frame for a less significant event was found. + * Find the all entries in freeze frame buffer and remove these. */ + for (uint16 indx = 0; (indx < freezeFrameBufferSize); indx++) { + if( freezeFrameBuffer[indx].eventId == eventToRemove ) { + memset(&freezeFrameBuffer[indx], 0, sizeof(FreezeFrameRecType)); + if( !freezeFrameFound ) { + *freezeFrame = &freezeFrameBuffer[indx]; + freezeFrameFound = TRUE; + } + } + } +#if defined(USE_DEM_EXTENSION) + if( freezeFrameFound ) { + Dem_Extension_EventFreezeFrameDataDisplaced(eventToRemove); + } +#endif + if( freezeFrameFound ) { + lookupEventIdParameter(eventToRemove, &eventToRemoveParam); + /* @req DEM475 */ + notifyEventDataChanged(eventToRemoveParam); + } + } else { + /* Buffer is full and the currently stored data is more significant */ + } + + return freezeFrameFound; +} +#endif /* DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM || DEM_FF_DATA_IN_PRE_INIT */ +#endif /* USE_MEMORY_FUNCTIONS */ +#endif /* DEM_EVENT_DISPLACEMENT_SUPPORT */ + +static Std_ReturnType getNofStoredNonOBDFreezeFrames(const Dem_EventParameterType *eventStatusRec, Dem_DTCOriginType origin, uint8 *nofStored) +{ + uint8 nofFound = 0; + const FreezeFrameRecType *ffBufferPtr = NULL; + uint8 bufferSize = 0; + if( DEM_INITIALIZED == demState ) { +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + if (origin == DEM_DTC_ORIGIN_PRIMARY_MEMORY) { + ffBufferPtr = &priMemFreezeFrameBuffer[0]; + bufferSize = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; + } +#endif +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) + if (origin == DEM_DTC_ORIGIN_SECONDARY_MEMORY) { + ffBufferPtr = &secMemFreezeFrameBuffer[0]; + bufferSize = DEM_MAX_NUMBER_FF_DATA_SEC_MEM; + } +#endif + +#if !((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) && \ + !((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) + /* Avoid compiler warning when no FF is used */ + (void)origin; +#endif + + } else { +#if ( DEM_FF_DATA_IN_PRE_INIT ) + ffBufferPtr = &preInitFreezeFrameBuffer[0]; + bufferSize = DEM_MAX_NUMBER_FF_DATA_PRE_INIT; +#endif + } + for( uint8 i = 0; (i < bufferSize) && (ffBufferPtr != NULL); i++) { + if((ffBufferPtr[i].eventId == eventStatusRec->EventID) && (DEM_FREEZE_FRAME_NON_OBD == ffBufferPtr[i].kind)) { + nofFound++; + } + } + *nofStored = nofFound; + return E_OK; +} + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +static void setFreezeFrameTimeStamp(FreezeFrameRecType *freezeFrame) +{ + if( DEM_INITIALIZED == demState ) { + if(FF_TimeStamp >= DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT){ + rearrangeFreezeFrameTimeStamp(&FF_TimeStamp); + } + freezeFrame->timeStamp = FF_TimeStamp; + FF_TimeStamp++; + } else { + freezeFrame->timeStamp = FF_TimeStamp; + if( FF_TimeStamp < DEM_MAX_TIMESTAMP_FOR_PRE_INIT ) { + FF_TimeStamp++; + } + } +} +#endif + + +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) || \ + ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) || \ + (DEM_FF_DATA_IN_PRE_INIT) +/* + * Procedure: getPidData + * Description: get OBD FF data,only called by getFreezeFrameData() + */ +static void getPidData(const Dem_PidOrDidType *const *const *pidClassPtr, FreezeFrameRecType *const *freezeFrame, uint16 *storeIndexPtr) +{ + uint16 storeIndex = 0; +#if (DEM_MAX_NR_OF_PIDS_IN_FREEZEFRAME_DATA > 0) + const Dem_PidOrDidType *const *FFIdClassRef; + Std_ReturnType callbackReturnCode; + uint16 recordSize = 0; + boolean detError = FALSE; + FFIdClassRef = *pidClassPtr; + //get all pids + for (uint16 i = 0; ((i < DEM_MAX_NR_OF_PIDS_IN_FREEZEFRAME_DATA) && (!FFIdClassRef[i]->Arc_EOL) && !detError); i++) { + if(FFIdClassRef[i]->PidOrDidUsePort == FALSE){ + //get pid length + recordSize = FFIdClassRef[i]->PidOrDidSize; + /* read out the pid data */ + if ((storeIndex + recordSize + DEM_PID_IDENTIFIER_SIZE_OF_BYTES) <= DEM_MAX_SIZE_FF_DATA) { + /* store PID */ + (*freezeFrame)->data[storeIndex] = FFIdClassRef[i]->PidIdentifier; + storeIndex++; + + /* store data */ + if(FFIdClassRef[i]->PidReadFnc != NULL){ + callbackReturnCode = FFIdClassRef[i]->PidReadFnc(&(*freezeFrame)->data[storeIndex]); + if (callbackReturnCode != E_OK) { + memset(&(*freezeFrame)->data[storeIndex], DEM_FREEZEFRAME_DEFAULT_VALUE, recordSize); + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_E_NODATAAVAILABLE); + } + storeIndex += recordSize; + + } else { + memset(&(*freezeFrame)->data[storeIndex], DEM_FREEZEFRAME_DEFAULT_VALUE, recordSize); + storeIndex += recordSize; + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_E_FF_TOO_BIG); + detError = TRUE;/* Will break the loop */ + } + } else { + //NOTE: The RTE should provide the port + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_DSP_DID_USE_PORT_IS_TRUE); + detError = TRUE;/* Will break the loop */ + } + } +#else + (void)pidClassPtr;/*lint !e920*/ + (void)freezeFrame;/*lint !e920*/ +#endif + //store storeIndex,it will be used for judge whether FF contains valid data. + *storeIndexPtr = storeIndex; + +} + +/* + * Procedure: getDidData + * Description: get UDS FF data,only called by getFreezeFrameData() + */ + static void getDidData(const Dem_PidOrDidType *const *const *didClassPtr, FreezeFrameRecType *const *freezeFrame, uint16 *storeIndexPtr) +{ + const Dem_PidOrDidType *const *FFIdClassRef; + Std_ReturnType callbackReturnCode; + uint16 storeIndex = 0; + uint16 recordSize = 0; + boolean detError = FALSE; + + FFIdClassRef = *didClassPtr; + //get all dids + for (uint16 i = 0; ((i < DEM_MAX_NR_OF_DIDS_IN_FREEZEFRAME_DATA) && (!FFIdClassRef[i]->Arc_EOL) && !detError); i++) { + if(FFIdClassRef[i]->PidOrDidUsePort == FALSE) { + recordSize = FFIdClassRef[i]->PidOrDidSize; + /* read out the did data */ + if ((storeIndex + recordSize + DEM_DID_IDENTIFIER_SIZE_OF_BYTES) <= DEM_MAX_SIZE_FF_DATA) { + /* store DID */ + (*freezeFrame)->data[storeIndex] = (FFIdClassRef[i]->DidIdentifier>> 8u) & 0xFFu; + storeIndex++; + (*freezeFrame)->data[storeIndex] = FFIdClassRef[i]->DidIdentifier & 0xFFu; + storeIndex++; + /* store data */ + if(FFIdClassRef[i]->DidReadFnc!= NULL) { + callbackReturnCode = FFIdClassRef[i]->DidReadFnc(&(*freezeFrame)->data[storeIndex]); + if (callbackReturnCode != E_OK) { + /* @req DEM463 */ + memset(&(*freezeFrame)->data[storeIndex], DEM_FREEZEFRAME_DEFAULT_VALUE, recordSize); + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_E_NODATAAVAILABLE); + } + storeIndex += recordSize; + } else { + memset(&(*freezeFrame)->data[storeIndex], DEM_FREEZEFRAME_DEFAULT_VALUE, recordSize); + storeIndex += recordSize; + } + } else { + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_E_FF_TOO_BIG); + detError = TRUE;/* Will break the loop */ + } + } else { + //IMPROVEMENT : RTE should provide the port + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_DSP_DID_USE_PORT_IS_TRUE); + detError = TRUE;/* Will break the loop */ + } + } + + //store storeIndex,it will be used for judge whether FF contains valid data. + *storeIndexPtr = storeIndex; +} + + static Std_ReturnType getNextFFRecordNumber(const Dem_EventParameterType *eventParam, uint8 *recNum, Dem_FreezeFrameKindType ffKind, Dem_DTCOriginType origin) + { + /* @req DEM574 */ + Std_ReturnType ret = E_OK; + uint8 nofStored = 0; + if( DEM_FREEZE_FRAME_NON_OBD == ffKind) { + if( 0 != eventParam->MaxNumberFreezeFrameRecords ) { + if( E_OK == getNofStoredNonOBDFreezeFrames(eventParam, origin, &nofStored) ) { + /* Was ok! */ + if( nofStored < eventParam->MaxNumberFreezeFrameRecords ) { + *recNum = eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[nofStored]; + } else { + /* @req DEM585 *//* All records stored so update the latest */ + *recNum = eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[eventParam->MaxNumberFreezeFrameRecords - 1]; + } + } + } else { + /* No freeze frames should be stored for this event */ + ret = E_NOT_OK; + } + } else { + /* Always record 0 for OBD freeze frames */ + *recNum = 0;/* @req DEM291 */ + } + return ret; + } + +/* + * Procedure: getFreezeFrameData + * Description: get FF data according configuration + */ +static void getFreezeFrameData(const Dem_EventParameterType *eventParam, + FreezeFrameRecType *freezeFrame, + Dem_FreezeFrameKindType ffKind, + Dem_DTCOriginType origin) +{ + uint16 storeIndex = 0; + const Dem_FreezeFrameClassType *FreezeFrameLocal = NULL; + + /* clear FF data record */ + memset(freezeFrame, 0, sizeof(FreezeFrameRecType )); + + /* Find out the corresponding FF class */ + if( (DEM_FREEZE_FRAME_NON_OBD == ffKind) && (eventParam->FreezeFrameClassRef != NULL) ) { + FreezeFrameLocal = eventParam->FreezeFrameClassRef; + } else if((DEM_FREEZE_FRAME_OBD == ffKind) && (NULL != configSet->GlobalOBDFreezeFrameClassRef)) { + FreezeFrameLocal = configSet->GlobalOBDFreezeFrameClassRef; + } else { + FreezeFrameLocal = NULL; + } + + /* get the dids */ + if(FreezeFrameLocal != NULL){ + if(FreezeFrameLocal->FFIdClassRef != NULL){ + if( DEM_FREEZE_FRAME_NON_OBD == ffKind ) { + getDidData(&FreezeFrameLocal->FFIdClassRef, &freezeFrame, &storeIndex); + } else if(DEM_FREEZE_FRAME_OBD == ffKind) { + /* Get the pids */ + getPidData(&FreezeFrameLocal->FFIdClassRef, &freezeFrame, &storeIndex); + } else { + /* IMPROVEMENT: Det error */ + } + } + } else { + /* create an empty FF */ + freezeFrame->eventId = DEM_EVENT_ID_NULL; + } + uint8 recNum = 0; + /* Check if any data has been stored and that there is a record number */ + if ( (storeIndex != 0) && (E_OK == getNextFFRecordNumber(eventParam, &recNum, ffKind, origin))) {/*lint !e9007 */ + freezeFrame->eventId = eventParam->EventID; + freezeFrame->dataSize = storeIndex; + freezeFrame->recordNumber = recNum; + freezeFrame->kind = ffKind; +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + setFreezeFrameTimeStamp(freezeFrame); +#endif + } else { + freezeFrame->eventId = DEM_EVENT_ID_NULL; + freezeFrame->dataSize = storeIndex; + } +} +#endif + +#if (defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) && DEM_FF_DATA_IN_PRE_INIT) +static void deleteFreezeFrameDataPreInit(const Dem_EventParameterType *eventParam) +{ + /* Delete all freeze frames */ + for (uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; i++){ + if(preInitFreezeFrameBuffer[i].eventId == eventParam->EventID) { + memset(&preInitFreezeFrameBuffer[i], 0, sizeof(FreezeFrameRecType)); + } + } +} +#endif +/* + * Procedure: storeFreezeFrameDataPreInit + * Description: store FF in before preInitFreezeFrameBuffer DEM's full initialization + */ +#if 0//( DEM_FF_DATA_IN_PRE_INIT ) +static void storeFreezeFrameDataPreInit(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame) +{ + boolean eventIdFound = FALSE; + boolean eventIdFreePositionFound=FALSE; + uint16 i; + /* Check if already stored */ + for (i = 0; (ikind ) { + eventIdFound = ( (preInitFreezeFrameBuffer[i].eventId == eventParam->EventID) && (preInitFreezeFrameBuffer[i].recordNumber == freezeFrame->recordNumber)); + } else { + eventIdFound = ((DEM_EVENT_ID_NULL != preInitFreezeFrameBuffer[i].eventId) && (DEM_FREEZE_FRAME_OBD == preInitFreezeFrameBuffer[i].kind)); + } + } + + if(eventIdFound){ + /* Entry found. Overwrite if not an OBD freeze frame*/ + if( DEM_FREEZE_FRAME_NON_OBD == preInitFreezeFrameBuffer[i-1].kind ) { + /* overwrite existing */ + memcpy(&preInitFreezeFrameBuffer[i-1], freezeFrame, sizeof(FreezeFrameRecType)); + } + } else{ + /* lookup first free position */ + for (i = 0; (iMaxNumberFreezeFrameRecords) && !isValid; i++ ) { + if( eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[i] == recordNumber ) { + isValid = TRUE; + } + } + } + return isValid; +} +#endif + +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static boolean transferNonOBDFreezeFramesEvtMem(Dem_EventIdType eventId, FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, + boolean* eventHandled, Dem_DTCOriginType origin, boolean removeOldFFRecords) +{ + /* Note: Don't touch the OBD freeze frame */ + uint16 nofStoredMemory = 0; + uint16 nofStoredPreInit = 0; + uint16 nofFFToMove; + const Dem_EventParameterType *eventParam; + uint8 recordToFind; + uint16 findRecordStartIndex; + uint16 setRecordStartIndex; + boolean memoryChanged = FALSE; + boolean dataUpdated = FALSE; + lookupEventIdParameter(eventId, &eventParam); + + + /* Count the number of entries in destination memory for the event */ + for( uint16 j = 0; j < freezeFrameBufferSize; j++ ) { + if( (eventId == freezeFrameBuffer[j].eventId) && (DEM_FREEZE_FRAME_NON_OBD == freezeFrameBuffer[j].kind)) { + + if( isValidRecordNumber(eventParam, freezeFrameBuffer[j].recordNumber) ) { + if( removeOldFFRecords) { + /* We should remove the old records. Don't increment nofStoredMemory + * since no records will be stored in the buffer after all have been cleared */ + memset(&freezeFrameBuffer[j], 0, sizeof(FreezeFrameRecType)); + memoryChanged = TRUE; + } else { + nofStoredMemory++; + } + } else { + /* Invalid ff record number */ + memset(&freezeFrameBuffer[j], 0, sizeof(FreezeFrameRecType)); + memoryChanged = TRUE; + } + } + } + + /* Count the number of entries in the pre init memory for the event */ + for( uint16 k = 0; k < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; k++ ) { + if( (eventId == preInitFreezeFrameBuffer[k].eventId) && (DEM_FREEZE_FRAME_NON_OBD == preInitFreezeFrameBuffer[k].kind)) { + nofStoredPreInit++; + } + } + + /* Find out the number of FF to transfer from preInit buffer to memory */ + /* We can assume that we should transfer at least on record from the preInitBuffer + * since we found this event in the preInit buffer*/ + if( eventParam->MaxNumberFreezeFrameRecords == nofStoredMemory ) { + /* All records already stored in primary memory. Just update the last record */ + nofFFToMove = 1; + findRecordStartIndex = nofStoredPreInit - 1; + setRecordStartIndex = eventParam->MaxNumberFreezeFrameRecords - 1; + } else if(eventParam->MaxNumberFreezeFrameRecords > nofStoredMemory) { + nofFFToMove = MIN(nofStoredPreInit, (eventParam->MaxNumberFreezeFrameRecords - nofStoredMemory)); + findRecordStartIndex = nofStoredPreInit - nofFFToMove; + setRecordStartIndex = nofStoredMemory; + } else { + /* To many records stored in primary memory. And they are all valid records + * as we check this. + * IMPROVEMENT: How do we handle this? + * For now, throw all records in buffer and store the ones + * in the preinit buffer. */ + for( uint16 i = 0; i < freezeFrameBufferSize; i++ ) { + if( (eventId == freezeFrameBuffer[i].eventId) && (DEM_FREEZE_FRAME_NON_OBD == freezeFrameBuffer[i].kind)) { + memset(&freezeFrameBuffer[i], 0, sizeof(FreezeFrameRecType)); + } + } + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_MEMORY_CORRUPT); + nofFFToMove = nofStoredPreInit; + findRecordStartIndex = 0; + setRecordStartIndex = 0; + } + + if( 0 != nofFFToMove) { + boolean ffStored = FALSE; + for( uint16 offset = 0; offset < nofFFToMove; offset++ ) { + recordToFind = eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[findRecordStartIndex + offset]; + ffStored = FALSE; + for( uint16 indx = 0; (indx < DEM_MAX_NUMBER_FF_DATA_PRE_INIT) && !ffStored; indx++ ) { + if( (preInitFreezeFrameBuffer[indx].eventId == eventId) && (preInitFreezeFrameBuffer[indx].recordNumber == recordToFind) && + (DEM_FREEZE_FRAME_NON_OBD == preInitFreezeFrameBuffer[indx].kind) && (!eventHandled[indx]) ) { + /* Found the record to update */ + preInitFreezeFrameBuffer[indx].recordNumber = + eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[setRecordStartIndex + offset]; + /* Store the freeze frame */ + if( storeFreezeFrameDataMem(eventParam, &preInitFreezeFrameBuffer[indx], freezeFrameBuffer, freezeFrameBufferSize, origin) ) { + dataUpdated = TRUE; + } + /* Clear the event id in the preInit buffer */ + eventHandled[indx] = TRUE; + ffStored = TRUE; + } + } + } + + if( nofFFToMove < nofStoredPreInit ) { + /* Did not move all freeze frames from the preInit buffer. + * Need to clear the remaining */ + for( uint16 indx = 0; indx < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; indx++ ) { + if( (preInitFreezeFrameBuffer[indx].eventId == eventId) && (DEM_FREEZE_FRAME_NON_OBD == preInitFreezeFrameBuffer[indx].kind) ) { + eventHandled[indx] = TRUE; + } + } + } + } + if( dataUpdated ) { + /* Use errorStatusChanged in eventsStatusBuffer to signal that the event data was updated */ + EventStatusRecType *eventStatusRecPtr; + lookupEventStatusRec(eventParam->EventID, &eventStatusRecPtr); + if( NULL != eventStatusRecPtr ) { + eventStatusRecPtr->errorStatusChanged = TRUE; + } + } + return memoryChanged; +} +#endif + +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static void transferOBDFreezeFramesEvtMem(const FreezeFrameRecType *freezeFrame, FreezeFrameRecType* freezeFrameBuffer, + uint32 freezeFrameBufferSize, Dem_DTCOriginType origin) +{ + const Dem_EventParameterType *eventParam; + lookupEventIdParameter(freezeFrame->eventId, &eventParam); + + if (origin != DEM_DTC_ORIGIN_PRIMARY_MEMORY) { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_OBD_NOT_ALLOWED_IN_SEC_MEM); + } else if( NULL != eventParam ) { + /* Assuming that this function will not store the OBD freeze frame + * if there already is one stored. */ + if( storeOBDFreezeFrameDataMem(eventParam, freezeFrame, freezeFrameBuffer, freezeFrameBufferSize, origin) ) { + /* Use errorStatusChanged in eventsStatusBuffer to signal that the event data was updated */ + EventStatusRecType *eventStatusRecPtr; + lookupEventStatusRec(eventParam->EventID, &eventStatusRecPtr); + if( NULL != eventStatusRecPtr ) { + eventStatusRecPtr->errorStatusChanged = TRUE; + } + } + } else { + /* Bad origin and no config available.. */ + } +} +#endif + +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static boolean transferPreInitFreezeFramesEvtMem(FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, EventRecType* eventBuffer, uint32 eventBufferSize, Dem_DTCOriginType origin) +{ + boolean priMemChanged = FALSE; + boolean removeOldFFRecords; + boolean skipFF; + const Dem_EventParameterType *eventParam; + EventStatusRecType* eventStatusRec; + boolean eventHandled[DEM_MAX_NUMBER_FF_DATA_PRE_INIT] = {FALSE}; + + for( uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; i++ ) { + if( (DEM_EVENT_ID_NULL != preInitFreezeFrameBuffer[i].eventId) && checkEntryValid(preInitFreezeFrameBuffer[i].eventId, origin) ) { + /* Check if this is a freeze frame which should be processed. + * Ignore freeze frames for event not stored in memory or OBD + * freeze frames for event which are not confirmed */ + eventStatusRec = NULL; + eventParam = NULL; + skipFF = TRUE; + lookupEventStatusRec(preInitFreezeFrameBuffer[i].eventId, &eventStatusRec); + lookupEventIdParameter(preInitFreezeFrameBuffer[i].eventId, &eventParam); + if( (NULL != eventStatusRec) && (NULL != eventParam) ) { + skipFF = FALSE; + if( origin == eventParam->EventClass->EventDestination) { + if( !eventIsStoredInMem(preInitFreezeFrameBuffer[i].eventId, eventBuffer, eventBufferSize) || + ((DEM_FREEZE_FRAME_OBD == preInitFreezeFrameBuffer[i].kind) && (0u == (eventStatusRec->eventStatusExtended & DEM_CONFIRMED_DTC))) ) { + /* Event is not stored or FF is OBD and event is not confirmed. Skip FF */ + skipFF = TRUE; + } + } + } + if(!skipFF) { + removeOldFFRecords = FALSE; +#if defined(USE_DEM_EXTENSION) + Dem_Extension_PreTransferPreInitFreezeFrames(preInitFreezeFrameBuffer[i].eventId, &removeOldFFRecords, origin); +#endif + if( DEM_FREEZE_FRAME_NON_OBD == preInitFreezeFrameBuffer[i].kind ) { + if (transferNonOBDFreezeFramesEvtMem(preInitFreezeFrameBuffer[i].eventId, + freezeFrameBuffer, + freezeFrameBufferSize, + eventHandled, + origin, + removeOldFFRecords)) { + priMemChanged = TRUE; + } + } else { + transferOBDFreezeFramesEvtMem(&preInitFreezeFrameBuffer[i], freezeFrameBuffer, + freezeFrameBufferSize, origin); + } + } + } + } + return priMemChanged; +} +#endif + +static Std_ReturnType setNvMBlockChanged(NvM_BlockIdType blockId) { + /* @req DEM329 */ +#if defined(USE_NVM) && (DEM_USE_NVM == STD_ON) + NvM_RequestResultType requestResult = NVM_REQ_PENDING; + Std_ReturnType ret = E_OK; + if( 0 != blockId ) { + ret = NvM_GetErrorStatus(blockId, &requestResult); + if((E_OK == ret) && (requestResult != NVM_REQ_PENDING) ) { +#if (NVM_SET_RAM_BLOCK_STATUS_API == STD_ON) + (void)NvM_SetRamBlockStatus( blockId, TRUE ); +#endif + } else { + ret = E_NOT_OK; + } + } + return ret; + +#else + (void)blockId; + return E_OK; +#endif +} + +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +/** + * Sets UDS status bit subset block as changed + */ +static void setStatusBitBlockChanged(void) { + if( E_OK == setNvMBlockChanged(StatusBitsAreModified.blockId) ) { + StatusBitsAreModified.dataModified = FALSE; + } else { + StatusBitsAreModified.dataModified = TRUE; + } +} +#endif + +#if defined(DEM_USE_INDICATORS) +static void setIndicatorBlockChanged(void) { + if( E_OK == setNvMBlockChanged(IndicatorsAreModified.blockId) ) { + IndicatorsAreModified.dataModified = FALSE; + } else { + IndicatorsAreModified.dataModified = TRUE; + } +} +#endif +static void setEventBlockChanged(Dem_DTCOriginType origin) +{ + uint32 i; + BufferInfo_t* bufferInfo = NULL; + + for (i=0;iblockId) ) { + bufferInfo->dataModified = FALSE; + } else { + bufferInfo->dataModified = TRUE; + } +} + +static void setFreezeFrameBlockChanged(Dem_DTCOriginType origin) +{ + uint32 i; + BufferInfo_t* bufferInfo = NULL; + + for (i=0;iblockId) ) { + bufferInfo->dataModified = FALSE; + } else { + bufferInfo->dataModified = TRUE; + } +} + +static void setExtendedDataBlockChanged(Dem_DTCOriginType origin) +{ + + uint32 i; + BufferInfo_t* bufferInfo = NULL; + + for (i=0;iblockId) ) { + bufferInfo->dataModified = FALSE; + } else { + bufferInfo->dataModified = TRUE; + } + +} + +#endif /* DEM_USE_MEMORY_FUNCTIONS */ + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +#if (DEM_EXT_DATA_IN_PRE_INIT || DEM_EXT_DATA_IN_PRI_MEM || DEM_EXT_DATA_IN_SEC_MEM ) +static void setExtDataTimeStamp(ExtDataRecType *extData) +{ + + if( DEM_INITIALIZED == demState ) { + if(ExtData_TimeStamp >= DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT){ + rearrangeExtDataTimeStamp(&ExtData_TimeStamp); + } + extData->timeStamp = ExtData_TimeStamp; + ExtData_TimeStamp++; + } else { + extData->timeStamp = ExtData_TimeStamp; + if( ExtData_TimeStamp < DEM_MAX_TIMESTAMP_FOR_PRE_INIT ) { + ExtData_TimeStamp++; + } + } + +} +#endif /* DEM_EXT_DATA_IN_PRE_INIT || DEM_EXT_DATA_IN_PRI_MEM || DEM_EXT_DATA_IN_SEC_MEM */ +#endif + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) +static Std_ReturnType lookupExtDataForDisplacement(const Dem_EventParameterType *eventParam, ExtDataRecType *extDataBufPtr, uint32 bufferSize, ExtDataRecType **extData ) +{ + const Dem_EventParameterType *eventToRemoveParam = NULL; + Std_ReturnType ret = E_NOT_OK; + /* @req DEM400 */ + Dem_EventIdType eventToRemove = DEM_EVENT_ID_NULL; + +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) + Dem_Extension_GetExtDataEventForDisplacement(eventParam, extDataBufPtr, bufferSize, &eventToRemove); +#elif defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( E_OK != getExtDataEventForDisplacement(eventParam, extDataBufPtr, bufferSize, &eventToRemove) ) { + eventToRemove = DEM_EVENT_ID_NULL; + } +#else +#warning Unsupported displacement +#endif + if( DEM_EVENT_ID_NULL != eventToRemove ) { + /* Extended data for a less significant event was found. + * Find the entry in ext data buffer. */ + for (uint32 indx = 0; (indx < bufferSize) && (E_OK != ret); indx++) { + if( extDataBufPtr[indx].eventId == eventToRemove ) { + memset(&extDataBufPtr[indx], 0, sizeof(ExtDataRecType)); + *extData = &extDataBufPtr[indx]; + ret = E_OK; +#if defined(USE_DEM_EXTENSION) + Dem_Extension_EventExtendedDataDisplaced(eventToRemove); +#endif + lookupEventIdParameter(eventToRemove, &eventToRemoveParam); + /* @req DEM475 */ + notifyEventDataChanged(eventToRemoveParam); + } + } + } else { + /* Buffer is full and the currently stored data is more significant *//* @req DEM407 */ + } + return ret; +} +#endif + + + + +#if ( DEM_EXT_DATA_IN_PRE_INIT || DEM_EXT_DATA_IN_PRI_MEM || DEM_EXT_DATA_IN_SEC_MEM ) +static boolean StoreExtDataInMem( const Dem_EventParameterType *eventParam, ExtDataRecType *extDataMem, uint16 bufferSize, Dem_DTCOriginType origin, boolean overrideOldData) { + + uint16 storeIndex = 0; + uint16 recordSize; + const Dem_ExtendedDataRecordClassType *extendedDataRecord; + ExtDataRecType *extData = NULL; + boolean eventIdFound = FALSE; + boolean bStoredData = FALSE; + + // Check if already stored + for (uint16 i = 0; (i < bufferSize) && (!eventIdFound); i++){ + eventIdFound = (extDataMem[i].eventId == eventParam->EventID); + extData = &extDataMem[i]; + } + + if( !eventIdFound ) { + extData = NULL; + for (uint16 i = 0; (i < bufferSize) && (NULL == extData); i++){ + if( extDataMem[i].eventId == DEM_EVENT_ID_NULL ) { + extData = &extDataMem[i]; + } + } + if( NULL == extData ) { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) + /* @req DEM400 *//* @req DEM407 */ + if( E_OK != lookupExtDataForDisplacement(eventParam, extDataMem, bufferSize, &extData) ) { + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + return FALSE; + } +#else + /* @req DEM402*//* Displacement supported disabled */ + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_MEM_ID, DEM_E_MEM_EXT_DATA_BUFF_FULL); + return FALSE; +#endif /* DEM_EVENT_DISPLACEMENT_SUPPORT */ + } + } + + // Check if any pointer to extended data class + if ( (NULL != extData) && (eventParam->ExtendedDataClassRef != NULL) ) { + // Request extended data and copy it to the buffer + for (uint16 i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL); i++) { + extendedDataRecord = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]; + if( DEM_UPDATE_RECORD_VOLATILE != extendedDataRecord->UpdateRule ) { + recordSize = extendedDataRecord->DataSize; + if ((storeIndex + recordSize) <= DEM_MAX_SIZE_EXT_DATA) { + if( (DEM_UPDATE_RECORD_YES == extendedDataRecord->UpdateRule) || + ((DEM_UPDATE_RECORD_NO == extendedDataRecord->UpdateRule) && (extData->eventId != eventParam->EventID)) || + overrideOldData) { + /* Either update rule YES, or update rule is NO and extended data was not previously stored for this event */ + if( NULL != extendedDataRecord->CallbackGetExtDataRecord ) { + /** @req DEM282 */ + if (E_OK != extendedDataRecord->CallbackGetExtDataRecord(&extData->data[storeIndex])) { + // Callback data currently not available, clear space. + memset(&extData->data[storeIndex], 0xFF, recordSize); + } + bStoredData = TRUE; + } else if( DEM_NO_ELEMENT != extendedDataRecord->InternalDataElement ) { + getInternalElement( eventParam, extendedDataRecord->InternalDataElement, &extData->data[storeIndex], extendedDataRecord->DataSize ); + bStoredData = TRUE; + } else { + /* No callback and not internal element.. + * IMPROVMENT: Det error */ + } + } else { + /* Should not update */ + } + storeIndex += recordSize; + } else { + // Error: Size of extended data record is bigger than reserved space. + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_EXTENDED_DATA_ID, DEM_E_EXT_DATA_TOO_BIG); + break; // Break the loop + } + } + } + } + + // Check if any data has been stored + if ( (NULL != extData) && bStoredData ) { + extData->eventId = eventParam->EventID; +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + setExtDataTimeStamp(extData); +#endif + +#ifdef DEM_USE_MEMORY_FUNCTIONS + if( DEM_PREINITIALIZED != demState ) { + setExtendedDataBlockChanged(origin); + } +#endif + } + return bStoredData; +} +#endif /* DEM_EXT_DATA_IN_PRE_INIT || DEM_EXT_DATA_IN_PRI_MEM || DEM_EXT_DATA_IN_SEC_MEM */ + + +/* + * Procedure: getExtendedData + * Description: Collects the extended data according to "eventParam" and return it in "extData", + * if not found eventId is set to DEM_EVENT_ID_NULL. + */ +static boolean storeExtendedData(const Dem_EventParameterType *eventParam, boolean overrideOldData) +{ + boolean ret = FALSE; + if( DEM_PREINITIALIZED == demState ) { +#if ( DEM_EXT_DATA_IN_PRE_INIT ) + (void)StoreExtDataInMem(eventParam, preInitExtDataBuffer, DEM_MAX_NUMBER_EXT_DATA_PRE_INIT, DEM_DTC_ORIGIN_NOT_USED, overrideOldData);/* @req DEM468 */ +#endif + } else { + switch (eventParam->EventClass->EventDestination) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_PRI_MEM) + ret = StoreExtDataInMem(eventParam, priMemExtDataBuffer, DEM_MAX_NUMBER_EXT_DATA_PRI_MEM, DEM_DTC_ORIGIN_PRIMARY_MEMORY, overrideOldData);/* @req DEM468 */ +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_SEC_MEM) + ret = StoreExtDataInMem(eventParam, secMemExtDataBuffer, DEM_MAX_NUMBER_EXT_DATA_SEC_MEM, DEM_DTC_ORIGIN_SECONDARY_MEMORY, overrideOldData);/* @req DEM468 */ +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + break; + } + } + return ret; +} + +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) +Std_ReturnType lookupEventForDisplacement(const Dem_EventParameterType *eventParam, EventRecType *eventBuffer, uint32 bufferSize, + EventRecType **memEventStatusRec, Dem_DTCOriginType origin) +{ + Std_ReturnType ret = E_NOT_OK; + Dem_EventIdType eventToRemove = DEM_EVENT_ID_NULL; + /* No free position found. See if any of the stored events may be removed */ +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) + Dem_Extension_GetEventForDisplacement(eventParam, eventBuffer, bufferSize, &eventToRemove); +#elif defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + if( E_OK != getEventForDisplacement(eventParam, eventBuffer, bufferSize, &eventToRemove) ) { + eventToRemove = DEM_EVENT_ID_NULL; + } +#else +#warning Unsupported displacement +#endif + if( DEM_EVENT_ID_NULL != eventToRemove ) { + /* a less significant event was found. + * Find the entry in buffer. */ + const Dem_EventParameterType *removeEventParam = NULL; + for (uint32 i = 0; (i < bufferSize) && (E_OK != ret); i++) { + if( eventBuffer[i].EventData.eventId == eventToRemove ) { + memset(&eventBuffer[i].EventData, 0, sizeof(EventRecType)); + *memEventStatusRec = &eventBuffer[i]; + ret = E_OK; +#if defined(USE_DEM_EXTENSION) + Dem_Extension_EventDataDisplaced(eventToRemove); +#endif + } + } + EventStatusRecType *eventStatusRecPtr; + lookupEventStatusRec(eventToRemove, &eventStatusRecPtr); + if( NULL != eventStatusRecPtr ) { + Dem_EventStatusExtendedType oldStatus = eventStatusRecPtr->eventStatusExtended; + /* @req DEM409 */ + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)(~DEM_CONFIRMED_DTC); +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->failureCounter = 0; + eventStatusRecPtr->failedDuringFailureCycle = FALSE; + eventStatusRecPtr->passedDuringFailureCycle = FALSE; +#endif +#if defined(DEM_aging_PROCESSING_DEM_INTERNAL) + eventStatusRecPtr->agingCounter = 0; + eventStatusRecPtr->failedDuringAgingCycle = FALSE; + eventStatusRecPtr->passedDuringAgingCycle = FALSE; +#endif + removeEventParam = eventStatusRecPtr->eventParamRef; + if( oldStatus != eventStatusRecPtr->eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(removeEventParam, oldStatus, eventStatusRecPtr->eventStatusExtended); + } + } else { + lookupEventIdParameter(eventToRemove, &removeEventParam); + } + if( NULL != removeEventParam ) { + /* Remove all event related data */ + /* @req DEM408 */ + + if( NULL != removeEventParam->FreezeFrameClassRef ) { + (void)deleteFreezeFrameDataMem(removeEventParam, origin); + } + if( NULL!= removeEventParam->ExtendedDataClassRef ) { + (void)deleteExtendedDataMem(removeEventParam, origin); + } +#if defined(DEM_USE_INDICATORS) + if( resetIndicatorCounters(removeEventParam) ) { +#ifdef DEM_USE_MEMORY_FUNCTIONS + setIndicatorBlockChanged(); +#endif + } +#endif + /* @req DEM475 */ + notifyEventDataChanged(removeEventParam); + } + } else { + /* Buffer is full and the currently stored data is more significant */ + } + return ret; +} +#endif +/* + * Procedure: storeEventMem + * Description: Store the event data of "eventStatus->eventId" in eventBuffer (i.e.primary or secondary memory), + * if non existent a new entry is created. + */ +static Std_ReturnType storeEventMem(const Dem_EventParameterType *eventParam, const EventStatusRecType *eventStatus, + EventRecType* buffer, uint32 bufferSize, Dem_DTCOriginType origin) +{ + boolean positionFound = FALSE; + EventRecType *eventStatusRec = NULL; + Std_ReturnType ret = E_OK; + + // Lookup event ID + for (uint16 i = 0; (i < bufferSize) && (!positionFound); i++){ + if( buffer[i].EventData.eventId == eventStatus->eventId ) { + eventStatusRec = &buffer[i]; + positionFound = TRUE; + } + } + + if( !positionFound ) { + /* Event is not already stored, Search for free position */ + for (uint16 i = 0; (i < bufferSize) && (!positionFound); i++){ + if( buffer[i].EventData.eventId == DEM_EVENT_ID_NULL ) { + eventStatusRec = &buffer[i]; + positionFound = TRUE; + } + } + if( !positionFound ) { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) + /* @req DEM400 *//* @req DEM407 */ + if( E_OK == lookupEventForDisplacement(eventParam, buffer, bufferSize, &eventStatusRec, origin) ) { + positionFound = TRUE; + } else { + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + } +#else + /* @req DEM402*/ /* No displacement should be done */ + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); +#endif /* DEM_EVENT_DISPLACEMENT_SUPPORT */ + } + } + + if ((positionFound) && (NULL != eventStatusRec)) { + // Update event found + eventStatusRec->EventData.eventId = eventStatus->eventId; + eventStatusRec->EventData.occurrence = eventStatus->occurrence; + eventStatusRec->EventData.eventStatusExtended = eventStatus->eventStatusExtended; +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + eventStatusRec->EventData.failureCounter = eventStatus->failureCounter; +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + eventStatusRec->EventData.agingCounter = eventStatus->agingCounter; +#endif +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + eventStatusRec->EventData.timeStamp = eventStatus->timeStamp; +#endif + setEventBlockChanged(origin); + } else { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + /* Error: mem event buffer full */ + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EVENT_MEM_ID, DEM_E_MEM_EVENT_BUFF_FULL); +#endif + /* Buffer is full and all stored events are more significant */ + ret = E_NOT_OK; + } + + return ret; +} + +/* + * Procedure: deleteEventMem + * Description: Delete the event data of "eventParam->eventId" from event buffer". + */ +static boolean deleteEventMem(const Dem_EventParameterType *eventParam, EventRecType* eventMemory, uint32 eventMemorySize, Dem_DTCOriginType origin) +{ + boolean eventIdFound = FALSE; + uint16 i; + + for (i = 0; (i < eventMemorySize) && (!eventIdFound); i++){ + eventIdFound = (eventMemory[i].EventData.eventId == eventParam->EventID); + } + + if (eventIdFound) { + memset(&eventMemory[i-1], 0, sizeof(EventRecType)); + setEventBlockChanged(origin); + } + return eventIdFound; +} +#endif /* DEM_USE_MEMORY_FUNCTIONS */ + + +/** + * Deletes DTC data i.e. event data, ff data and extended data for an event. + * @param eventParam - the event which data shall be deleted for + * @param dtcOriginFound - TRUE if origin found otherwise FALSE + * @return TRUE if any data deleted otherwise FALSE + */ +static boolean DeleteDTCData(const Dem_EventParameterType *eventParam, boolean resetEventstatus, boolean *dtcOriginFound) { + + boolean dataDeleted = FALSE; + + switch (eventParam->EventClass->EventDestination) + { +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: + /** @req DEM077 */ + if( deleteEventMem(eventParam, priMemEventBuffer, DEM_MAX_NUMBER_EVENT_PRI_MEM, DEM_DTC_ORIGIN_PRIMARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( deleteFreezeFrameDataMem(eventParam, DEM_DTC_ORIGIN_PRIMARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( deleteExtendedDataMem(eventParam, DEM_DTC_ORIGIN_PRIMARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( resetEventstatus ) { + resetEventStatusRec(eventParam); + } + *dtcOriginFound = TRUE; + break; +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: + if( deleteEventMem(eventParam, secMemEventBuffer, DEM_MAX_NUMBER_EVENT_SEC_MEM, DEM_DTC_ORIGIN_SECONDARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( deleteFreezeFrameDataMem(eventParam, DEM_DTC_ORIGIN_SECONDARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( deleteExtendedDataMem(eventParam, DEM_DTC_ORIGIN_SECONDARY_MEMORY) ) { + dataDeleted = TRUE; + } + if( resetEventstatus ) { + resetEventStatusRec(eventParam); + } + *dtcOriginFound = TRUE; + break; +#endif + default: + *dtcOriginFound = FALSE; + break; + } + return dataDeleted; +} + +#if defined(DEM_USE_MEMORY_FUNCTIONS) +/** + * Checks if an event is stored in its event destination + * @param eventParam + * @return TRUE: Event is stored in event memory, FALSE: Event not stored in event memory + */ +#if 0 +static boolean isInEventMemory(const Dem_EventParameterType *eventParam) +{ + boolean found = FALSE; + uint16 memSize = 0; + const EventRecType *mem = NULL; + switch (eventParam->EventClass->EventDestination) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + mem = priMemEventBuffer; + memSize = DEM_MAX_NUMBER_EVENT_ENTRY_PRI; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + mem = secMemEventBuffer; + memSize = DEM_MAX_NUMBER_EVENT_ENTRY_SEC; +#endif + break; + default: + break; + } + + if( NULL != mem ) { + for(uint16 i = 0; (i < memSize) && !found; i++) { + if( eventParam->EventID == mem[i].EventData.eventId ) { + found = TRUE; + } + } + } + return found; +} +#endif +#endif + +/* + * Procedure: storeEventEvtMem + * Description: Store the event data of "eventStatus->eventId" in event memory according to + * "eventParam" destination option. + */ +static Std_ReturnType storeEventEvtMem(const Dem_EventParameterType *eventParam, const EventStatusRecType *eventStatus) +{ + Std_ReturnType ret = E_NOT_OK; + + switch (eventParam->EventClass->EventDestination) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + ret = storeEventMem(eventParam, eventStatus, priMemEventBuffer, DEM_MAX_NUMBER_EVENT_ENTRY_PRI, DEM_DTC_ORIGIN_PRIMARY_MEMORY); /** @req DEM010 */ +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + ret = storeEventMem(eventParam, eventStatus, secMemEventBuffer, DEM_MAX_NUMBER_EVENT_ENTRY_SEC, DEM_DTC_ORIGIN_SECONDARY_MEMORY); /** @req DEM548 */ +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + break; + } + + return ret; +} + + +/* + * Procedure: getExtendedDataMem + * Description: Get record from buffer if it exists, or pick next free if it doesn't + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if (DEM_EXT_DATA_IN_PRE_INIT ) +static void getExtendedDataMem(const Dem_EventParameterType *eventParam, ExtDataRecType ** const extendedData, + ExtDataRecType* extendedDataBuffer, uint32 extendedDataBufferSize) /** @req DEM041 */ +{ + boolean eventIdFound = FALSE; + boolean eventIdFreePositionFound=FALSE; + uint16 i; + + // Check if already stored + for (i = 0; (iEventID ) { + *extendedData = &extendedDataBuffer[i]; + eventIdFound = TRUE; + } + } + + if (!eventIdFound) { + // No, lookup first free position + for (i = 0; (i < extendedDataBufferSize) && (!eventIdFreePositionFound); i++){ + eventIdFreePositionFound = (extendedDataBuffer[i].eventId == DEM_EVENT_ID_NULL); + } + if (eventIdFreePositionFound) { + *extendedData = &extendedDataBuffer[i-1]; + } else { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) + if(E_OK != lookupExtDataForDisplacement(eventParam, extendedDataBuffer, extendedDataBufferSize, extendedData)) { + *extendedData = NULL; + } +#else + /* Displacement supported disabled */ + /* Error: mem extended data buffer full */ + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_MEM_ID, DEM_E_MEM_EXT_DATA_BUFF_FULL); + +#endif /* DEM_EVENT_DISPLACEMENT_SUPPORT */ + } + } +} +#endif + +/* + * Procedure: deleteExtendedDataMem + * Description: Delete the extended data of "eventParam->eventId" from "priMemExtDataBuffer". + */ +static boolean deleteExtendedDataMem(const Dem_EventParameterType *eventParam, Dem_DTCOriginType origin) +{ + boolean eventIdFound = FALSE; + uint16 i; + + ExtDataRecType* extBuffer = NULL; + uint32 bufferSize = 0; + + switch (origin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_PRI_MEM) + extBuffer = priMemExtDataBuffer; + bufferSize = DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_SEC_MEM) + extBuffer = secMemExtDataBuffer; + bufferSize = DEM_MAX_NUMBER_EXT_DATA_SEC_MEM; +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + break; + } + if( NULL != extBuffer ) { + // Check if already stored + for (i = 0;(iEventID); + } + + if (eventIdFound) { + // Yes, clear record + memset(&extBuffer[i-1], 0, sizeof(ExtDataRecType)); + setExtendedDataBlockChanged(origin); + } + } + return eventIdFound; +} + +/* + * Procedure: storeExtendedDataEvtMem + * Description: Store the extended data in event memory according to + * "eventParam" destination option + */ +#if ( DEM_EXT_DATA_IN_PRE_INIT ) +static boolean mergeExtendedDataEvtMem(const Dem_EventParameterType *eventParam, const ExtDataRecType *extendedData, ExtDataRecType* extendedDataBuffer, + uint32 extendedDataBufferSize, Dem_DTCOriginType origin, boolean updateAllExtData) +{ + uint16 i; + const Dem_ExtendedDataRecordClassType *extendedDataRecordClass; + ExtDataRecType *memExtDataRec = NULL; + uint16 storeIndex = 0; + boolean bCopiedData = FALSE; + + if( eventParam->EventClass->EventDestination == origin ) { + /* Management is only relevant for events stored in destinatio mem (i.e. nvram) */ + + getExtendedDataMem(eventParam, &memExtDataRec, extendedDataBuffer, extendedDataBufferSize); + + if( NULL != memExtDataRec ) { + /* We found an old record or could allocate a new slot */ + + /* Only copy extended data related to event set during pre-init */ + for(i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL); i++) { + extendedDataRecordClass = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]; + if( DEM_UPDATE_RECORD_VOLATILE != extendedDataRecordClass->UpdateRule ) { + if( DEM_UPDATE_RECORD_YES == extendedDataRecordClass->UpdateRule ) { + /* Copy records that failed during pre init */ + memcpy(&memExtDataRec->data[storeIndex], &extendedData->data[storeIndex],extendedDataRecordClass->DataSize); + bCopiedData = TRUE; + } + else if( DEM_UPDATE_RECORD_NO == extendedDataRecordClass->UpdateRule ) { + if( (eventParam->EventID != memExtDataRec->eventId) || updateAllExtData) { + /* Extended data was not previously stored for this event. */ + memcpy(&memExtDataRec->data[storeIndex], &extendedData->data[storeIndex],extendedDataRecordClass->DataSize); + bCopiedData = TRUE; + } + } + else { + /* DET FEL */ + } + storeIndex += extendedDataRecordClass->DataSize; + } + } + if( bCopiedData ) { + memExtDataRec->eventId = extendedData->eventId; +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + memExtDataRec->timeStamp = extendedData->timeStamp; +#endif + setExtendedDataBlockChanged(origin); + } + } + else { + /* DET FEL */ + } + } + return bCopiedData; +} +#endif +#endif /* DEM_USE_MEMORY_FUNCTIONS */ + + +/* + * Procedure: lookupExtendedDataRecNumParam + * Description: Returns TRUE if the requested extended data number was found among the configured records for the event. + * "extDataRecClassPtr" returns a pointer to the record class, "posInExtData" returns the position in stored extended data. + */ +static boolean lookupExtendedDataRecNumParam(uint8 extendedDataNumber, const Dem_EventParameterType *eventParam, Dem_ExtendedDataRecordClassType const **extDataRecClassPtr, uint16 *posInExtData) +{ + boolean recNumFound = FALSE; + + if (eventParam->ExtendedDataClassRef != NULL) { + uint16 byteCnt = 0; + uint16 i; + + // Request extended data and copy it to the buffer + for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL) && (recNumFound==FALSE); i++) { + if (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->RecordNumber == extendedDataNumber) { + *extDataRecClassPtr = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]; + *posInExtData = byteCnt; + recNumFound = TRUE; + } + if(DEM_UPDATE_RECORD_VOLATILE != eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->UpdateRule) { + byteCnt += eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->DataSize; + } + } + } + + return recNumFound; +} + + +/* + * Procedure: lookupExtendedDataMem + * Description: Returns TRUE if the requested event id is found, "extData" points to the found data. + */ +static boolean lookupExtendedDataMem(Dem_EventIdType eventId, ExtDataRecType **extData, Dem_DTCOriginType origin) +{ + boolean eventIdFound = FALSE; + uint16 i; + ExtDataRecType* extBuffer = NULL; + uint32 extBufferSize = 0; + + switch (origin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_PRI_MEM) + extBuffer = priMemExtDataBuffer; + extBufferSize = DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_EXT_DATA_IN_SEC_MEM) + extBuffer = secMemExtDataBuffer; + extBufferSize = DEM_MAX_NUMBER_EXT_DATA_SEC_MEM; +#endif + break; + default: + break; + } + if( NULL == extBuffer ) { + return FALSE; + } + // Lookup corresponding extended data + for (i = 0; (i < extBufferSize) && (!eventIdFound); i++) { + eventIdFound = (extBuffer[i].eventId == eventId); + } + + if (eventIdFound) { + // Yes, return pointer + *extData = &extBuffer[i-1]; + } + + return eventIdFound; +} + +/* + * Procedure: storeFreezeFrameDataMem + * Description: store FreezeFrame data record in primary memory + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if ( DEM_FF_DATA_IN_PRE_INIT || DEM_FF_DATA_IN_PRI_MEM || DEM_FF_DATA_IN_SEC_MEM ) +static boolean storeFreezeFrameDataMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame, + FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, + Dem_DTCOriginType origin) +{ + boolean eventIdFound = FALSE; + boolean eventIdFreePositionFound=FALSE; + boolean ffUpdated = FALSE; + uint16 i; + + /* Check if already stored */ + for (i = 0; (iEventID) && (freezeFrameBuffer[i].recordNumber == freezeFrame->recordNumber)); + } + + if (eventIdFound) { + memcpy(&freezeFrameBuffer[i-1], freezeFrame, sizeof(FreezeFrameRecType)); + ffUpdated = TRUE; + } + else { + for (i = 0; (i < freezeFrameBufferSize) && (!eventIdFreePositionFound); i++){ + eventIdFreePositionFound = (freezeFrameBuffer[i].eventId == DEM_EVENT_ID_NULL); + } + if (eventIdFreePositionFound) { + memcpy(&freezeFrameBuffer[i-1], freezeFrame, sizeof(FreezeFrameRecType)); + ffUpdated = TRUE; + } else { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) + /* @req DEM400 *//* @req DEM407 */ + FreezeFrameRecType *freezeFrameLocal; + if( lookupFreezeFrameForDisplacement(eventParam, &freezeFrameLocal, freezeFrameBuffer, freezeFrameBufferSize) ){ + memcpy(freezeFrameLocal, freezeFrame, sizeof(FreezeFrameRecType)); + ffUpdated = TRUE; + } else { + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + } +#else + /* @req DEM402*/ /* Req is not the Det-error.. */ + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_FF_DATA_MEM_ID, DEM_E_MEM_FF_DATA_BUFF_FULL); +#endif + } + } + + if( ffUpdated ) { + setFreezeFrameBlockChanged(origin); + } + return ffUpdated; +} +#endif + +static boolean deleteFreezeFrameDataMem(const Dem_EventParameterType *eventParam, Dem_DTCOriginType origin) +{ + uint16 i; + boolean ffDeleted = FALSE; + FreezeFrameRecType* freezeFrameBuffer = NULL; + uint32 bufferSize = 0; + + switch (origin) { +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ( DEM_FF_DATA_IN_PRI_MEM ) + freezeFrameBuffer = priMemFreezeFrameBuffer; + bufferSize = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; +#else + freezeFrameBuffer = NULL; + bufferSize = 0; +#endif + break; +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ( DEM_FF_DATA_IN_SEC_MEM ) + freezeFrameBuffer = secMemFreezeFrameBuffer; + bufferSize = DEM_MAX_NUMBER_FF_DATA_SEC_MEM; +#endif + break; +#endif + default: + break; + } + if( NULL != freezeFrameBuffer ) { + for (i = 0; iEventID){ + memset(&freezeFrameBuffer[i], 0, sizeof(FreezeFrameRecType)); + ffDeleted = TRUE; + } + } + + if( ffDeleted ) { + setFreezeFrameBlockChanged(origin); + } + } + return ffDeleted; +} +#endif /* DEM_USE_MEMORY_FUNCTIONS */ +/* + * Procedure: storeFreezeFrameDataEvtMem + * Description: Store the freeze frame data in event memory according to + * "eventParam" destination option + */ +static boolean storeFreezeFrameDataEvtMem(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame, + Dem_FreezeFrameKindType ffKind) +{ + boolean ret = FALSE; + switch (eventParam->EventClass->EventDestination) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + getFreezeFrameData(eventParam, freezeFrame, ffKind, DEM_DTC_ORIGIN_PRIMARY_MEMORY); + if (freezeFrame->eventId != DEM_EVENT_ID_NULL) { + if(freezeFrame->kind == DEM_FREEZE_FRAME_OBD){ + ret = storeOBDFreezeFrameDataMem(eventParam, freezeFrame,priMemFreezeFrameBuffer, + DEM_MAX_NUMBER_FF_DATA_PRI_MEM, DEM_DTC_ORIGIN_PRIMARY_MEMORY); + } + else { + ret = storeFreezeFrameDataMem(eventParam, freezeFrame, priMemFreezeFrameBuffer, + DEM_MAX_NUMBER_FF_DATA_PRI_MEM, DEM_DTC_ORIGIN_PRIMARY_MEMORY); /** @req DEM190 */ + } + } +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) + getFreezeFrameData(eventParam, freezeFrame, ffKind, DEM_DTC_ORIGIN_SECONDARY_MEMORY); + if (freezeFrame->eventId != DEM_EVENT_ID_NULL) { + if(freezeFrame->kind == DEM_FREEZE_FRAME_OBD){ + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_OBD_NOT_ALLOWED_IN_SEC_MEM); + } + else { + ret = storeFreezeFrameDataMem(eventParam, freezeFrame, secMemFreezeFrameBuffer, + DEM_MAX_NUMBER_FF_DATA_SEC_MEM, DEM_DTC_ORIGIN_SECONDARY_MEMORY); /** @req DEM190 */ + } + } +#endif + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + (void)freezeFrame; /*lint !e920 Avoid compiler warning (variable not used) */ + (void)ffKind; + break; + } + return ret; +} + +/* + * Procedure: lookupFreezeFrameDataRecNumParam + * Description: Returns TRUE if the requested freezeFrame data number was found among the configured records for the event. + * "freezeFrameClassPtr" returns a pointer to the record class. + */ +#if 1 +static boolean lookupFreezeFrameDataRecNumParam(uint8 recordNumber, const Dem_EventParameterType *eventParam, Dem_FreezeFrameClassType const **freezeFrameClassPtr) +{ + boolean recNumFound = FALSE; + + if ( (NULL != eventParam->FreezeFrameClassRef) && (NULL != eventParam->FreezeFrameRecNumClassRef)) { + for( uint8 i = 0; (i < eventParam->MaxNumberFreezeFrameRecords) && !recNumFound; i++ ) { + if( eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[i] == recordNumber ) { + recNumFound = TRUE; + *freezeFrameClassPtr = eventParam->FreezeFrameClassRef; + } + } + } + + return recNumFound; +} +#endif +/* + * Procedure: lookupFreezeFrameDataSize + * Description: Returns TRUE if the requested freezeFrame data size was obtained successfully from the configuration. + * "dataSize" returns a pointer to the data size. + */ +#if 1 +static boolean lookupFreezeFrameDataSize(uint8 recordNumber, const Dem_FreezeFrameClassType * const *freezeFrameClassPtr, uint16 *dataSize) +{ + boolean dataSizeFound = FALSE; + uint16 i; + + (void)recordNumber; /* Avoid compiler warning - can this be removed */ + *dataSize = 0; + if (*freezeFrameClassPtr != NULL) { + dataSizeFound = TRUE; + for (i = 0; (i < DEM_MAX_NR_OF_DIDS_IN_FREEZEFRAME_DATA) && ((*freezeFrameClassPtr)->FFIdClassRef[i]->Arc_EOL != TRUE); i++) { + *dataSize += (*freezeFrameClassPtr)->FFIdClassRef[i]->PidOrDidSize + DEM_DID_IDENTIFIER_SIZE_OF_BYTES; + } + } + + return dataSizeFound; +} +#endif +/** + * Looks for a stored freeze frame with correct record number has been stored for an event + * @param eventId + * @param recordNumber + * @param dtcOrigin + * @param freezeFrame + * @return TRUE: if a freeze frame with the correct record number was stored for this event, FALSE: Otherwise + */ +static boolean getStoredFreezeFrame(Dem_EventIdType eventId, uint8 recordNumber, Dem_DTCOriginType dtcOrigin, FreezeFrameRecType **freezeFrame) +{ + boolean ffFound = FALSE; + + FreezeFrameRecType* freezeFrameBuffer = NULL; + uint32 freezeFrameBufferSize = 0; + + switch (dtcOrigin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + freezeFrameBuffer = priMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) + freezeFrameBuffer = secMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_SEC_MEM; +#endif + break; + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + } + + if (freezeFrameBuffer != NULL) { + + for (uint16 i = 0; (i < freezeFrameBufferSize) && (!ffFound); i++) { + ffFound = ((freezeFrameBuffer[i].eventId == eventId) && (freezeFrameBuffer[i].recordNumber == recordNumber)); + if(ffFound) { + *freezeFrame = &freezeFrameBuffer[i]; + } + } + } + return ffFound; +} +/* + * Procedure: lookupFreezeFrameDataPriMem + * Description: Returns TRUE if the requested event id is found, "freezeFrame" points to the found data. + */ +#if 1 +static boolean getFreezeFrameRecord(Dem_EventIdType eventId,uint8 recordNumber, const Dem_FreezeFrameClassType *FFDataRecordClass, + Dem_DTCOriginType dtcOrigin, uint8* destBuffer, uint16* bufSize, const uint16 *FFDataSize) +{ + + boolean ffFound = FALSE; + + FreezeFrameRecType* freezeFrame = NULL; + + if(getStoredFreezeFrame(eventId, recordNumber, dtcOrigin, &freezeFrame)) { + + destBuffer[0] = recordNumber; + destBuffer[1] = 0; + for (uint8 FFIdNumber = 0; FFDataRecordClass->FFIdClassRef[FFIdNumber]->Arc_EOL == FALSE; FFIdNumber++) { + destBuffer[1]++; + } + + memcpy(&destBuffer[2], freezeFrame->data, *FFDataSize); /** @req DEM071 */ + *bufSize = *FFDataSize + 2; + + ffFound = TRUE; + } + return ffFound; +} +#endif +/** + * Gets conditions for data storage + * @param eventFailedNow + * @param eventDataUppdated + * @param extensionStorageBitfield + * @param storeFFData + * @param storeExtData + * @param overrideOldExtdata + */ +static void getStorageConditions(boolean eventFailedNow, boolean eventDataUpdated, uint8 extensionStorageBitfield, boolean *storeFFData, boolean *storeExtData, boolean *overrideOldExtData) +{ +#if defined(DEM_EXTENDED_DATA_CAPTURE_EVENT_MEMORY_STORAGE) + *storeExtData = eventDataUpdated; + *overrideOldExtData = FALSE; +#elif defined(DEM_EXTENDED_DATA_CAPTURE_TESTFAILED) + *storeExtData = eventFailedNow; + *overrideOldExtData = FALSE; +#elif defined(DEM_EXTENDED_DATA_CAPTURE_EXTENSION) + /* @req OEM_DEM_10169 DEM_TRIGGER_EXTENSION */ + *overrideOldExtData = (0 != (extensionStorageBitfield & DEM_EXT_CLEAR_BEFORE_STORE_EXT_DATA_BIT)); + *storeExtData = (0 != (extensionStorageBitfield & DEM_EXT_STORE_EXT_DATA_BIT)); +#else + *storeExtData = FALSE; + *overrideOldExtData = FALSE; +#endif +#if defined(DEM_FREEZE_FRAME_CAPTURE_EVENT_MEMORY_STORAGE) + *storeFFData = eventDataUpdated; +#elif defined(DEM_FREEZE_FRAME_CAPTURE_TESTFAILED) + *storeFFData = eventFailedNow; +#elif defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) + /* @req OEM_DEM_10170 DEM_TRIGGER_EXTENSION */ + *storeFFData = (0 != (extensionStorageBitfield & DEM_EXT_STORE_FF_BIT)); +#else + *storeFFData = FALSE; + (void)eventFailedNow; /* Avoid compiler warning */ + (void)eventDataUpdated; /* Avoid compiler warning */ + (void)extensionStorageBitfield; /* Avoid compiler warning */ +#endif +} + +/* + * Procedure: handlePreInitEvent + * Description: Handle the updating of event status and storing of + * event related data in preInit buffers. + */ +#if 1 +static void handlePreInitEvent(Dem_EventIdType eventId, Dem_EventStatusType eventStatus) +{ + const Dem_EventParameterType *eventParam; + EventStatusRecType *eventStatusRec = NULL; + + lookupEventIdParameter(eventId, &eventParam); + if (eventParam != NULL) { + if ( operationCycleIsStarted(eventParam->EventClass->OperationCycleRef) ) { + lookupEventStatusRec(eventId, &eventStatusRec); + if( NULL != eventStatusRec ) { + updateEventStatusRec(eventParam, eventStatus, eventStatusRec); + if ( (0 != eventStatusRec->errorStatusChanged) || (0 != eventStatusRec->extensionDataChanged) ) { + boolean storeExtData; + boolean overrideOldExtData; + boolean storeFFData; + boolean eventFailedNow = eventStatusRec->errorStatusChanged && (0 != (eventStatusRec->eventStatusExtended & DEM_TEST_FAILED)); + /* Get conditions for data storage */ + getStorageConditions(eventFailedNow, TRUE, eventStatusRec->extensionDataStoreBitfield, &storeFFData, &storeExtData, &overrideOldExtData); + + if( storeExtData && (NULL != eventParam->ExtendedDataClassRef) ) { + (void)storeExtendedData(eventParam, overrideOldExtData); + } +#if( DEM_FF_DATA_IN_PRE_INIT ) + if( storeFFData) { + FreezeFrameRecType freezeFrameLocal; + if(NULL != eventParam->FreezeFrameClassRef ) { +#if defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) + /* Allow extension to decide if ffs should be deleted before storing */ + if( 0 != (eventStatusRec->extensionDataStoreBitfield & DEM_EXT_CLEAR_BEFORE_STORE_FF_BIT) ) { + deleteFreezeFrameDataPreInit(eventParam); + } +#endif + + getFreezeFrameData(eventParam, &freezeFrameLocal, DEM_FREEZE_FRAME_NON_OBD, DEM_DTC_ORIGIN_NOT_USED); + if (freezeFrameLocal.eventId != DEM_EVENT_ID_NULL) { + //storeFreezeFrameDataPreInit(eventParam, &freezeFrameLocal); + } + } + if( (NULL != eventParam->DTCClassRef) && (DEM_DTC_KIND_EMISSION_REL_DTCS == eventParam->DTCClassRef->DTCKind) ) { + getFreezeFrameData(eventParam, &freezeFrameLocal, DEM_FREEZE_FRAME_OBD, DEM_DTC_ORIGIN_NOT_USED); + if (freezeFrameLocal.eventId != DEM_EVENT_ID_NULL) { + // storeFreezeFrameDataPreInit(eventParam, &freezeFrameLocal); + } + } + } +#endif /* DEM_FF_DATA_IN_PRE_INIT */ + } + } + } + else { + // Operation cycle not set or not started + // IMPROVEMENT: Report error? + } + } + else { + // Event ID not configured + // IMPROVEMENT: Report error? + } +} +#endif + +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) +static boolean enableConditionsSet(const Dem_EventClassType *eventClass) +{ + /* @req DEM449 */ + /* @req DEM450 */ + boolean conditionsSet = TRUE; + if( NULL != eventClass->EnableConditionGroupRef ) { + /* Each group must reference at least one enable condition. Or this won't work.. */ + const Dem_EnableConditionGroupType *enableConditionGroupPtr = eventClass->EnableConditionGroupRef; + for( uint8 i = 0; i < enableConditionGroupPtr->nofEnableConditions; i++ ) { + if( !DemEnableConditions[enableConditionGroupPtr->EnableCondition[i]->EnableConditionID] ) { + conditionsSet = FALSE; + } + } + } + return conditionsSet; +} +#endif + +/** + * Checks whether DTC setting for event is disabled. If the event does not have a DTC (or its DTC is suppressed) + * setting is NOT disabled. + * @param eventParam + * @return TRUE: Disabled, FALSE: NOT disabled + */ +static boolean DTCSettingDisabled(const Dem_EventParameterType *eventParam) +{ + /* @req DEM587 */ + boolean eventDTCSettingDisabled = FALSE; + if( (disableDtcSetting.settingDisabled == TRUE) && (NULL != eventParam->DTCClassRef) && (DTCIsAvailable(eventParam->DTCClassRef) == TRUE) ) { + /* DTC setting is disabled and the event has a DTC (which is not suppressed) */ + if( (checkDtcGroup(disableDtcSetting.dtcGroup, eventParam, DEM_DTC_FORMAT_UDS) == TRUE) && + (checkDtcKind(disableDtcSetting.dtcKind, eventParam) == TRUE) ) { + /* Setting of DTC for this event is disabled. */ + eventDTCSettingDisabled = TRUE; + } + } + return eventDTCSettingDisabled; +} + +/** + * Checks whether event processing is allowed + * @param eventParam + * @return TRUE: Processing allowed, FALSE: Processing not allowed + */ +static boolean eventProcessingAllowed(const Dem_EventParameterType *eventParam) +{ + /* Event processing is not allowed if event has DTC and DTC setting has been disabled, + * or if event has enable conditions and these are not set. */ + if ( ( !DTCSettingDisabled(eventParam) ) /* @req DEM626 */ +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) + && (enableConditionsSet(eventParam->EventClass))/* @req DEM447 */ +#endif + ) { + return TRUE; + } else { + return FALSE; + } +} +static boolean checkOBDFFStorageCondition(const Dem_EventParameterType *eventParam, Dem_EventStatusExtendedType oldStatus, Dem_EventStatusExtendedType status) +{ + if( (0u == (oldStatus & DEM_CONFIRMED_DTC)) && (0u != (status & DEM_CONFIRMED_DTC)) ) { + return TRUE; + } else { + return FALSE; + } +} +/* + * Procedure: handleEvent + * Description: Handle the updating of event status and storing of + * event related data in event memory. + */ +Std_ReturnType handleEvent(Dem_EventIdType eventId, Dem_EventStatusType eventStatus) +{ + Std_ReturnType returnCode = E_OK; + const Dem_EventParameterType *eventParam; + EventStatusRecType *eventStatusRec; + FreezeFrameRecType freezeFrameLocal; + Dem_EventStatusExtendedType oldStatus = DEM_DEFAULT_EVENT_STATUS; + Std_ReturnType eventStoreStatus = E_OK; + + lookupEventIdParameter(eventId, &eventParam); + lookupEventStatusRec(eventId, &eventStatusRec); + if ( (eventParam != NULL) && (NULL != eventStatusRec) && eventStatusRec->isAvailable ) { + if ( operationCycleIsStarted(eventParam->EventClass->OperationCycleRef) ) {/* @req DEM481 */ + /* Check if event processing is allowed (DTC setting, enable condition) */ + if ( eventProcessingAllowed(eventParam)) { + oldStatus = eventStatusRec->eventStatusExtended; + updateEventStatusRec(eventParam, eventStatus, eventStatusRec); + + if ( (0 != eventStatusRec->errorStatusChanged) || (0 != eventStatusRec->extensionDataChanged) ) { + eventStoreStatus = storeEventEvtMem(eventParam, eventStatusRec); /** @req DEM184 *//** @req DEM396 */ + boolean storeExtData; + boolean storeFFData; + boolean overrideOldExtData; + boolean eventDataUpdated = (E_OK == eventStoreStatus); + boolean eventFailedNow = eventStatusRec->errorStatusChanged && (0 != (eventStatusRec->eventStatusExtended & DEM_TEST_FAILED)); + + /* Get conditions for data storage */ + getStorageConditions(eventFailedNow, eventDataUpdated, eventStatusRec->extensionDataStoreBitfield, &storeFFData, &storeExtData, &overrideOldExtData); + + if( FALSE == eventDTCRecordDataUpdateDisabled(eventParam) ) { + if (storeExtData && (NULL != eventParam->ExtendedDataClassRef)) { + if( storeExtendedData(eventParam, overrideOldExtData) ) { + eventDataUpdated = TRUE; + } + } + if (storeFFData) { + if(NULL != eventParam->FreezeFrameClassRef){ +#if defined(DEM_USE_MEMORY_FUNCTIONS) && defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) + /* Allow extension to decide if ffs should be deleted before storing */ + if( 0 != (eventStatusRec->extensionDataStoreBitfield & DEM_EXT_CLEAR_BEFORE_STORE_FF_BIT) ) { + if( deleteFreezeFrameDataMem(eventParam, eventParam->EventClass->EventDestination) ) { + eventDataUpdated = TRUE; + } + } +#endif + if( storeFreezeFrameDataEvtMem(eventParam, &freezeFrameLocal, DEM_FREEZE_FRAME_NON_OBD) ) { /** @req DEM190 */ + eventDataUpdated = TRUE; + } + } + if( (NULL != eventParam->DTCClassRef) && (DEM_DTC_KIND_EMISSION_REL_DTCS == eventParam->DTCClassRef->DTCKind) && + eventDataUpdated && checkOBDFFStorageCondition(eventParam, oldStatus, eventStatusRec->eventStatusExtended) ) { + if( storeFreezeFrameDataEvtMem(eventParam, &freezeFrameLocal, DEM_FREEZE_FRAME_OBD) ) { /** @req DEM190 */ + eventDataUpdated = TRUE; + } + } + } + } + if( eventDataUpdated ) { + /* @req DEM475 */ + notifyEventDataChanged(eventParam); + } + } + if( E_NOT_OK == eventStoreStatus ) { + /* Tried to store event but did not succeed (eventStoreStatus initialized to E_OK). + * Make sure confirmed bit is not set. */ + eventStatusRec->eventStatusExtended &= ~DEM_CONFIRMED_DTC; + } + if( oldStatus != eventStatusRec->eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(eventStatusRec->eventParamRef, oldStatus, eventStatusRec->eventStatusExtended); + } +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) + if((TRUE == eventStatusRec->indicatorDataChanged) && isInEventMemory(eventParam)) { + storeEventIndicators(eventParam); + setIndicatorBlockChanged(); + } +#endif + } else { + /* Enable conditions not set or DTC disabled */ + returnCode = E_NOT_OK; + } + } else { + returnCode = E_NOT_OK; // Operation cycle not valid or not started /* @req DEM482 */ + } + } else { + returnCode = E_NOT_OK; // Event ID not configured or set to not available + } + + return returnCode; +} + +/* + * Procedure: resetEventStatus + * Description: Resets the events status of eventId. + */ + +#if 0 +static Std_ReturnType resetEventStatus(Dem_EventIdType eventId) +{ + EventStatusRecType *eventStatusRecPtr; + Std_ReturnType ret = E_OK; + lookupEventStatusRec(eventId, &eventStatusRecPtr); + if (eventStatusRecPtr != NULL) { + if( eventStatusRecPtr->isAvailable && (0 != (eventStatusRecPtr->eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) ) { + Dem_EventStatusExtendedType oldStatus = eventStatusRecPtr->eventStatusExtended; + eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED; /** @req DEM187 */ + resetDebounceCounter(eventStatusRecPtr); + if( oldStatus != eventStatusRecPtr->eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(eventStatusRecPtr->eventParamRef, oldStatus, eventStatusRecPtr->eventStatusExtended); + } + /* NOTE: Should we store in "event destination" if DEM_TEST_FAILED_STORAGE == STD_ON) */ + +#if DEM_TEST_FAILED_STORAGE == STD_ON + if((0 != (oldStatus & DEM_TEST_FAILED)) && (E_OK == storeEventEvtMem(eventStatusRecPtr->eventParamRef, eventStatusRecPtr))) { + notifyEventDataChanged(eventStatusRecPtr->eventParamRef); + } +#endif + + } else { + /* @req DEM638 */ + ret = E_NOT_OK; + } + } + return ret; +} +#endif + +/* + * Procedure: getEventStatus + * Description: Returns the extended event status bitmask of eventId in "eventStatusExtended". + */ +#if 1 +static Std_ReturnType getEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended) +{ + Std_ReturnType ret = E_OK; + EventStatusRecType eventStatusLocal; + + // Get recorded status + getEventStatusRec(eventId, &eventStatusLocal); + if ( (eventStatusLocal.eventId == eventId) && eventStatusLocal.isAvailable) { + *eventStatusExtended = eventStatusLocal.eventStatusExtended; /** @req DEM051 */ + } + else { + // Event Id not found, no report received. + *eventStatusExtended = DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR; + ret = E_NOT_OK; + } + return ret; +} +#endif +/* + * Procedure: getEventFailed + * Description: Returns the TRUE or FALSE of "eventId" in "eventFailed" depending on current status. + */ +#if 1 +static Std_ReturnType getEventFailed(Dem_EventIdType eventId, boolean *eventFailed) +{ + Std_ReturnType ret = E_OK; + EventStatusRecType eventStatusLocal; + + // Get recorded status + getEventStatusRec(eventId, &eventStatusLocal); + if ( (eventStatusLocal.eventId == eventId) && eventStatusLocal.isAvailable) { + if ( 0 != (eventStatusLocal.eventStatusExtended & DEM_TEST_FAILED)) { /** @req DEM052 */ + *eventFailed = TRUE; + } + else { + *eventFailed = FALSE; + } + } + else { + // Event Id not found or not available. + *eventFailed = FALSE; + ret = E_NOT_OK; + } + return ret; +} +#endif +/* + * Procedure: getEventTested + * Description: Returns the TRUE or FALSE of "eventId" in "eventTested" depending on + * current status the "test not completed this operation cycle" bit. + */ +#if 1 +static Std_ReturnType getEventTested(Dem_EventIdType eventId, boolean *eventTested) +{ + Std_ReturnType ret = E_OK; + EventStatusRecType eventStatusLocal; + + // Get recorded status + getEventStatusRec(eventId, &eventStatusLocal); + if ( (eventStatusLocal.eventId == eventId) && eventStatusLocal.isAvailable) { + if ( 0 == (eventStatusLocal.eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) { /** @req DEM053 */ + *eventTested = TRUE; + } + else { + *eventTested = FALSE; + } + } + else { + // Event Id not found, not tested. + *eventTested = FALSE; + ret = E_NOT_OK; + } + return ret; +} +#endif + +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + +static boolean ageEvent(EventStatusRecType* evtStatusRecPtr) { + /* @req DEM643 */ + boolean updatedMemory = FALSE; + boolean dummy; + boolean eventDeleted = FALSE; + Dem_EventStatusExtendedType oldStatus = evtStatusRecPtr->eventStatusExtended; + + /* @req DEM489 *//* If it is confirmed it should be stored in event memory */ + if( (evtStatusRecPtr->eventStatusExtended & DEM_CONFIRMED_DTC)) { + if( evtStatusRecPtr->passedDuringAgingCycle && !evtStatusRecPtr->failedDuringAgingCycle ) { + /* Event was PASSED but NOT FAILED during aging cycle. + * Increment aging counter */ + if( evtStatusRecPtr->agingCounter < DEM_AGING_CNTR_MAX ) { + evtStatusRecPtr->agingCounter++; + /* Set the flag,start up the storage of NVRam in main function. */ + updatedMemory = TRUE; + } + if(evtStatusRecPtr->agingCounter >= evtStatusRecPtr->eventParamRef->EventClass->AgingCycleCounterThreshold) { /* @req DEM493 */ + /* @req DEM497 *//* Delete ff and ext data */ + /* @req DEM161 */ + evtStatusRecPtr->agingCounter = 0; + /* !req DEM498 *//* IMPROVEMNT: Only reset confirmed bit */ + evtStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)(~DEM_CONFIRMED_DTC); + evtStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)(~DEM_PENDING_DTC); + if(DeleteDTCData(evtStatusRecPtr->eventParamRef, FALSE, &dummy)) { + /* Set the flag,start up the storage of NVRam in main function. */ + updatedMemory = TRUE; + eventDeleted = TRUE; + } +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + evtStatusRecPtr->failureCounter = 0; +#endif +#if defined(USE_DEM_EXTENSION) + Dem_Extension_HealedEvent(evtStatusRecPtr->eventId); +#endif + } + } + else if( evtStatusRecPtr->failedDuringAgingCycle && (0u != evtStatusRecPtr->agingCounter)) { + /* Event failed during the aging cycle. Reset aging counter */ + evtStatusRecPtr->agingCounter = 0; + updatedMemory = TRUE; + } else { + /* Do nothing.. */ + } + } + if( oldStatus != evtStatusRecPtr->eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(evtStatusRecPtr->eventParamRef, oldStatus, evtStatusRecPtr->eventStatusExtended); + } + if( updatedMemory ) { + if( !eventDeleted ) { + if(E_OK == storeEventEvtMem(evtStatusRecPtr->eventParamRef, evtStatusRecPtr) ) { + /* @req DEM475 */ + notifyEventDataChanged(evtStatusRecPtr->eventParamRef); + } + } else { + /* Event was deleted. So don't store again but notify event data changed */ + notifyEventDataChanged(evtStatusRecPtr->eventParamRef); + setEventBlockChanged(evtStatusRecPtr->eventParamRef->EventClass->EventDestination); + } + + } + return updatedMemory; +} + + +/* + * Procedure: handleAging + * Description: according to the operation state of "operationCycleId" to "cycleState" , handle the aging relatived data + * Returns E_OK if operation was successful else E_NOT_OK. + */ +static Std_ReturnType handleAging(Dem_OperationCycleIdType operationCycleId) +{ + uint16 i; + Std_ReturnType returnCode = E_OK; + boolean agingUpdatedSecondaryMemory = FALSE; + boolean agingUpdatedPrimaryMemory = FALSE; + + if (operationCycleId < DEM_OPERATION_CYCLE_ID_ENDMARK) { + /** @req Dem490 */ + for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + if(eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL){ + if(eventStatusBuffer[i].eventParamRef != NULL){ + if(eventStatusBuffer[i].eventParamRef->EventClass != NULL){ + if((eventStatusBuffer[i].eventParamRef->EventClass->AgingAllowed == TRUE) + && (eventStatusBuffer[i].eventParamRef->EventClass->AgingCycleRef == operationCycleId)) { + /* Loop all destination memories e.g. primary and secondary */ + Dem_DTCOriginType origin = eventStatusBuffer[i].eventParamRef->EventClass->EventDestination; + if (origin == DEM_DTC_ORIGIN_SECONDARY_MEMORY) { + agingUpdatedSecondaryMemory = ageEvent(&eventStatusBuffer[i]); + } else if (origin == DEM_DTC_ORIGIN_PRIMARY_MEMORY) { + agingUpdatedPrimaryMemory = ageEvent(&eventStatusBuffer[i]); + } + } + } + } + } + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA); + returnCode = E_NOT_OK; + } + + if( agingUpdatedPrimaryMemory ) { + setEventBlockChanged(DEM_DTC_ORIGIN_PRIMARY_MEMORY); + } + if( agingUpdatedSecondaryMemory ) { + setEventBlockChanged(DEM_DTC_ORIGIN_SECONDARY_MEMORY); + } + + return returnCode; + +} +#endif + +/** + * Handles starting an operation cycle + * @param operationCycleId + */ +static void operationCycleStart(Dem_OperationCycleIdType operationCycleId) +{ + Dem_EventStatusExtendedType oldStatus; + operationCycleStateList[operationCycleId] = DEM_CYCLE_STATE_START; + // Lookup event ID + for (uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + if( (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (TRUE == eventStatusBuffer[i].isAvailable) ) { + if( eventStatusBuffer[i].eventParamRef->EventClass->OperationCycleRef == operationCycleId ) { + oldStatus = eventStatusBuffer[i].eventStatusExtended; + eventStatusBuffer[i].eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED_THIS_OPERATION_CYCLE; + eventStatusBuffer[i].eventStatusExtended |= DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE; + resetDebounceCounter(&eventStatusBuffer[i]); + + if( oldStatus != eventStatusBuffer[i].eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(eventStatusBuffer[i].eventParamRef, oldStatus, eventStatusBuffer[i].eventStatusExtended); + } + if( NULL != eventStatusBuffer[i].eventParamRef->CallbackInitMforE ) { + /* @req DEM376 */ + (void)eventStatusBuffer[i].eventParamRef->CallbackInitMforE(DEM_INIT_MONITOR_RESTART); + } + + } +#if defined(USE_DEM_EXTENSION) + Dem_Extension_OperationCycleStart(operationCycleId, &eventStatusBuffer[i]); +#endif + } +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + if( (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (eventStatusBuffer[i].eventParamRef->EventClass->FailureCycleRef == operationCycleId) ) { + eventStatusBuffer[i].failedDuringFailureCycle = FALSE; + eventStatusBuffer[i].passedDuringFailureCycle = FALSE; + } +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + if( (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (eventStatusBuffer[i].eventParamRef->EventClass->AgingCycleRef == operationCycleId) ) { + eventStatusBuffer[i].passedDuringAgingCycle = FALSE; + eventStatusBuffer[i].failedDuringAgingCycle = FALSE; + } +#endif + } +#if defined(DEM_USE_INDICATORS) + indicatorOpCycleStart(operationCycleId); +#endif +} + +/** + * Handles ending an operation cycle + * @param operationCycleId + */ +static void operationCycleEnd(Dem_OperationCycleIdType operationCycleId) +{ + Dem_EventStatusExtendedType oldStatus; + operationCycleStateList[operationCycleId] = DEM_CYCLE_STATE_END; + // Lookup event ID + for (uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + boolean storeEvtMem = FALSE; +#if defined(DEM_USE_INDICATORS) + boolean indicatorsUpdated = FALSE; +#endif + if ((eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (TRUE == eventStatusBuffer[i].isAvailable)) { + oldStatus = eventStatusBuffer[i].eventStatusExtended; +#if defined(DEM_USE_INDICATORS) + if(indicatorOpCycleEnd(operationCycleId, &eventStatusBuffer[i])) { + indicatorsUpdated = TRUE; + } +#endif + if ((0 == (eventStatusBuffer[i].eventStatusExtended & DEM_TEST_FAILED_THIS_OPERATION_CYCLE)) && (0 == (eventStatusBuffer[i].eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE))) { + if( eventStatusBuffer[i].eventParamRef->EventClass->OperationCycleRef == operationCycleId ) { + eventStatusBuffer[i].eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_PENDING_DTC; // Clear pendingDTC bit /** @req DEM379.PendingClear + if( oldStatus != eventStatusBuffer[i].eventStatusExtended ) { + storeEvtMem = TRUE; + } + } + } +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + if( (eventStatusBuffer[i].eventParamRef->EventClass->FailureCycleRef == operationCycleId) && + eventStatusBuffer[i].passedDuringFailureCycle && !eventStatusBuffer[i].failedDuringFailureCycle ) { + /* @dev DEM: Spec. does not say when this counter should be cleared */ + if( 0 != eventStatusBuffer[i].failureCounter ) { + eventStatusBuffer[i].failureCounter = 0; + storeEvtMem = TRUE; + } + } +#endif +#if defined(USE_DEM_EXTENSION) + Dem_Extension_OperationCycleEnd(operationCycleId, &eventStatusBuffer[i]); +#endif + if( oldStatus != eventStatusBuffer[i].eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(eventStatusBuffer[i].eventParamRef, oldStatus, eventStatusBuffer[i].eventStatusExtended); + } + if( storeEvtMem ) { + /* Transfer to event memory. */ + if( E_OK == storeEventEvtMem(eventStatusBuffer[i].eventParamRef, &eventStatusBuffer[i]) ) { + notifyEventDataChanged(eventStatusBuffer[i].eventParamRef); + } + } +#if defined(DEM_USE_INDICATORS) + if( indicatorsUpdated ) { +#ifdef DEM_USE_MEMORY_FUNCTIONS + setIndicatorBlockChanged(); +#endif + } +#endif + } + } +} +/* + * Procedure: setOperationCycleState + * Description: Change the operation state of "operationCycleId" to "cycleState" and updates stored + * event connected to this cycle id. + * Returns E_OK if operation was successful else E_NOT_OK. + */ +static Std_ReturnType setOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState) /** @req DEM338 */ +{ + Std_ReturnType returnCode = E_OK; + /* @req DEM338 */ + if (operationCycleId < DEM_OPERATION_CYCLE_ID_ENDMARK) { + switch (cycleState) { + case DEM_CYCLE_STATE_START: + /* @req DEM483 */ + operationCycleStart(operationCycleId); + break; + + case DEM_CYCLE_STATE_END: + if(operationCycleStateList[operationCycleId] != DEM_CYCLE_STATE_END) { + /* @req DEM484 */ + operationCycleEnd(operationCycleId); +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + (void)handleAging(operationCycleId); +#endif + } + break; + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA); + returnCode = E_NOT_OK; + break; + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA); + returnCode = E_NOT_OK; + } + + return returnCode; +} + + +static inline void initEventStatusBuffer(const Dem_EventParameterType *eventIdParamList) +{ + // Insert all supported events into event status buffer + const Dem_EventParameterType *eventParam = eventIdParamList; + EventStatusRecType *eventStatusRecPtr; + while( !eventParam->Arc_EOL ) { + // Find next free position in event status buffer + lookupEventStatusRec(eventParam->EventID, &eventStatusRecPtr); + if(NULL != eventStatusRecPtr) { + eventStatusRecPtr->eventId = eventParam->EventID; + eventStatusRecPtr->eventParamRef = eventParam; + sint8 startUdsFdc = getDefaultUDSFdc(eventParam->EventID); + eventStatusRecPtr->UDSFdc = startUdsFdc;/* @req DEM438 */ + eventStatusRecPtr->maxUDSFdc = startUdsFdc; + eventStatusRecPtr->fdcInternal = 0; + eventStatusRecPtr->isAvailable = *eventParam->EventClass->EventAvailableByCalibration; + if(FALSE == eventStatusRecPtr->isAvailable) { + eventStatusRecPtr->eventStatusExtended = 0x0u; + } +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) + /* Check if suppression of DTC is affected */ + boolean suppressed = TRUE; + const Dem_EventParameterType *dtcEventParam; + if( (NULL != eventParam->DTCClassRef) && (NULL != eventParam->DTCClassRef->Events) ) { + for( uint16 i = 0; (i < eventParam->DTCClassRef->NofEvents) && suppressed; i++ ) { + dtcEventParam = NULL; + lookupEventIdParameter(eventParam->DTCClassRef->Events[i], &dtcEventParam); + if( (NULL != dtcEventParam) && (TRUE == *dtcEventParam->EventClass->EventAvailableByCalibration) ) { + /* Event is available -> DTC NOT suppressed */ + suppressed = FALSE; + } + } + if( 0 != eventParam->DTCClassRef->NofEvents ) { + DemDTCSuppressed[eventParam->DTCClassRef->DTCIndex].SuppressedByEvent = suppressed; + } + } +#endif + } + eventParam++; + } +} + +#if ( DEM_FF_DATA_IN_PRE_INIT ) +static inline void initPreInitFreezeFrameBuffer(void) +{ + for (uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; i++) { + preInitFreezeFrameBuffer[i].eventId = DEM_EVENT_ID_NULL; + preInitFreezeFrameBuffer[i].dataSize = 0; +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + preInitFreezeFrameBuffer[i].timeStamp = 0; +#endif + for (uint16 j = 0; j < DEM_MAX_SIZE_FF_DATA;j++){ + preInitFreezeFrameBuffer[i].data[j] = 0; + } + } +} +#endif + +static inline void initPreInitExtDataBuffer(void) +{ +#if ( DEM_EXT_DATA_IN_PRE_INIT ) + for (uint16 i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++) { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + preInitExtDataBuffer[i].timeStamp = 0; +#endif + preInitExtDataBuffer[i].eventId = DEM_EVENT_ID_NULL; + for (uint16 j = 0; j < DEM_MAX_SIZE_EXT_DATA;j++){ + preInitExtDataBuffer[i].data[j] = 0; + } + } +#endif +} + +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) +static inline void initEnableConditions(void) +{ + /* Initialize the enable conditions */ + const Dem_EnableConditionType *enableCondition = configSet->EnableCondition; + while( enableCondition->EnableConditionID != DEM_ENABLE_CONDITION_EOL) { + DemEnableConditions[enableCondition->EnableConditionID] = enableCondition->EnableConditionStatus; + enableCondition++; + } +} +#endif + +#ifdef DEM_USE_MEMORY_FUNCTIONS +static boolean validateFreezeFrames(FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, Dem_DTCOriginType origin) +{ + /* IMPROVEMENT: Delete OBD freeze frames if the event is not emission related */ + boolean freezeFrameBlockChanged = FALSE; + // Validate freeze frame records stored in primary memory + for (uint16 i = 0; i < freezeFrameBufferSize; i++) { + if ((freezeFrameBuffer[i].eventId == DEM_EVENT_ID_NULL) || (FALSE == checkEntryValid(freezeFrameBuffer[i].eventId, origin))) { + // Unlegal record, clear the record + memset(&freezeFrameBuffer[i], 0, sizeof(FreezeFrameRecType)); + freezeFrameBlockChanged = TRUE; + } + } + return freezeFrameBlockChanged; +} + +static boolean validateExtendedData(ExtDataRecType* extendedDataBuffer, uint32 extendedDataBufferSize, Dem_DTCOriginType origin) +{ + boolean extendedDataBlockChanged = FALSE; + for (uint16 i = 0; i < extendedDataBufferSize; i++) { + if ((extendedDataBuffer[i].eventId == DEM_EVENT_ID_NULL) || (FALSE == checkEntryValid(extendedDataBuffer[i].eventId, origin))) { + // Unlegal record, clear the record + memset(&extendedDataBuffer[i], 0, sizeof(ExtDataRecType)); + extendedDataBlockChanged = TRUE; + } + } + return extendedDataBlockChanged; +} +#endif /* DEM_USE_MEMORY_FUNCTIONS */ + +/** + * Looks for freeze frame data for a specific record number (a specific record or the most recent). Returns pointer to data, + * the record number found and the type of freeze frame data (OBD or NON-OBD) + * @param eventParam + * @param recNum + * @param freezeFrameData + * @param ffRecNumFound + * @param ffKind + * @return TRUE: freeze frame data found, FALSE: freeze frame data not found + */ +static boolean getFFRecData(const Dem_EventParameterType *eventParam, uint8 recNum, uint8 **freezeFrameData, uint8 *ffRecNumFound, Dem_FreezeFrameKindType *ffKind) +{ + boolean isStored = FALSE; + uint8 nofStoredRecord = 0; + uint8 recordToFind = recNum; + boolean failed = FALSE; + if( (NULL != eventParam->FreezeFrameClassRef) && (NULL != eventParam->FreezeFrameRecNumClassRef) ) { + if( MOST_RECENT_FF_RECORD == recNum ) { + /* Should find the most recent record */ + if(E_OK == getNofStoredNonOBDFreezeFrames(eventParam, eventParam->EventClass->EventDestination, &nofStoredRecord)){ + if( 0 == nofStoredRecord ) { + failed = TRUE; + } else { + recordToFind = eventParam->FreezeFrameRecNumClassRef->FreezeFrameRecordNumber[nofStoredRecord - 1]; + } + } + } + if( !failed ) { + /* Have a record number to look for */ + FreezeFrameRecType *freezeFrame = NULL; + if(getStoredFreezeFrame(eventParam->EventID, recordToFind, eventParam->EventClass->EventDestination, &freezeFrame) && (NULL != freezeFrame)) { + *freezeFrameData = freezeFrame->data; + *ffKind = DEM_FREEZE_FRAME_NON_OBD; + isStored = TRUE; + } + } + } else { +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + /* Could be OBD... */ + recordToFind = 0; /* Always 0 for OBD freeze frame */ + if( (NULL != configSet->GlobalOBDFreezeFrameClassRef) && (NULL != eventParam->DTCClassRef) && (DEM_DTC_KIND_EMISSION_REL_DTCS == eventParam->DTCClassRef->DTCKind)) { + /* Event is event related */ + if( (0 == recNum) || (MOST_RECENT_FF_RECORD == recNum) ) { + /*find the corresponding FF in FF buffer*/ + for(uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++){ + if((DEM_FREEZE_FRAME_OBD == priMemFreezeFrameBuffer[i].kind) && (priMemFreezeFrameBuffer[i].eventId == eventParam->EventID)){ + *freezeFrameData = priMemFreezeFrameBuffer[i].data; + *ffKind = DEM_FREEZE_FRAME_OBD; + isStored = TRUE; + break; + } + } + } + } +#endif + } + *ffRecNumFound = recordToFind; + return isStored; +} + +/** + * Checks if an event may be cleared + * @param eventParam + * @return TRUE: Event may be cleared, FALSE: Event may NOT be cleared + */ +static boolean clearEventAllowed(const Dem_EventParameterType *eventParam) +{ + boolean clearAllowed = TRUE; + /* @req DEM514 */ + if(NULL != eventParam->CallbackClearEventAllowed) { + /* @req DEM515 */ + if( E_OK != eventParam->CallbackClearEventAllowed(&clearAllowed)) { + /* @req DEM516 */ + clearAllowed = TRUE; + } + } + return clearAllowed; +} +//==============================================================================// +// // +// E X T E R N A L F U N C T I O N S // +// // +//==============================================================================// + +/********************************************* + * Interface for upper layer modules (8.3.1) * + *********************************************/ + +/* + * Procedure: Dem_GetVersionInfo + * Reentrant: Yes + */ +// Defined in Dem.h + + +/*********************************************** + * Interface ECU State Manager <-> DEM (8.3.2) * + ***********************************************/ + + +static void InitialModifyBuffers(void) { + + + uint32 indx = 0; +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + //EventIsModified[indx].blockId = DEM_EVENT_PRIMARY_NVM_BLOCK_HANDLE; + EventIsModified[indx].origin = DEM_DTC_ORIGIN_PRIMARY_MEMORY; + EventIsModified[indx].dataModified = FALSE; +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + indx++; +#endif +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + EventIsModified[indx].blockId = DEM_EVENT_SECONDARY_NVM_BLOCK_HANDLE; + EventIsModified[indx].origin = DEM_DTC_ORIGIN_SECONDARY_MEMORY; + EventIsModified[indx].dataModified = FALSE; +#endif + + indx = 0; +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + // FFIsModified[indx].blockId = DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_HANDLE; + FFIsModified[indx].origin = DEM_DTC_ORIGIN_PRIMARY_MEMORY; + FFIsModified[indx].dataModified = FALSE; +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + indx++; +#endif +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + FFIsModified[indx].blockId = DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_HANDLE; + FFIsModified[indx].origin = DEM_DTC_ORIGIN_SECONDARY_MEMORY; + FFIsModified[indx].dataModified = FALSE; +#endif + + indx = 0; +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + // ExtendedDataIsModified[indx].blockId = DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_HANDLE; + ExtendedDataIsModified[indx].origin = DEM_DTC_ORIGIN_PRIMARY_MEMORY; + ExtendedDataIsModified[indx].dataModified = FALSE; +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + indx++; +#endif +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + ExtendedDataIsModified[indx].blockId = DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_HANDLE; + ExtendedDataIsModified[indx].origin = DEM_DTC_ORIGIN_SECONDARY_MEMORY; + ExtendedDataIsModified[indx].dataModified = FALSE; +#endif + +#if defined(DEM_USE_INDICATORS) + IndicatorsAreModified.blockId = DEM_INDICATOR_NVM_BLOCK_HANDLE; + IndicatorsAreModified.dataModified = FALSE; +#endif + +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) + StatusBitsAreModified.blockId = DEM_STATUSBIT_NVM_BLOCK_HANDLE; + StatusBitsAreModified.dataModified = FALSE; +#endif +} + +#if defined(DEM_USE_INDICATORS) +static void initIndicatorStatusBuffer(const Dem_EventParameterType *eventIdParamList) +{ + uint8 indx = 0; + while( !eventIdParamList[indx].Arc_EOL ) { + if( NULL != eventIdParamList[indx].EventClass->IndicatorAttribute ) { + const Dem_IndicatorAttributeType *indAttrPtr = eventIdParamList[indx].EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL) { + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].EventID = eventIdParamList[indx].EventID; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].InternalIndicatorId = indAttrPtr->IndicatorBufferIndex; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].FailureCounter = 0; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].HealingCounter = 0; + indicatorStatusBuffer[indAttrPtr->IndicatorBufferIndex].OpCycleStatus = 0; + indAttrPtr++; + } + } + indx++; + } +} +#endif + +#if defined(USE_NVM) && (DEM_USE_NVM == STD_ON) +/** + * Validates configured NvM block sizes + */ +static void validateNvMBlockSizes(void) +{ + /* Check sizes of used NvM blocks */ +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + //DEM_ASSERT( (0 == DEM_EVENT_PRIMARY_NVM_BLOCK_HANDLE) || + // (DEM_EVENT_PRIMARY_NVM_BLOCK_SIZE == sizeof(priMemEventBuffer))); +#if ( DEM_FF_DATA_IN_PRI_MEM ) + // DEM_ASSERT( (0 == DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_HANDLE) || + (DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_SIZE == sizeof(priMemFreezeFrameBuffer))); +#endif + +#if ( DEM_EXT_DATA_IN_PRI_MEM ) + //DEM_ASSERT( (0 == DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_HANDLE) || + // (DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_SIZE == sizeof(priMemExtDataBuffer))); +#endif +#endif + +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + DEM_ASSERT( (0 == DEM_EVENT_SECONDARY_NVM_BLOCK_HANDLE) || + (DEM_EVENT_SECONDARY_NVM_BLOCK_SIZE == sizeof(secMemEventBuffer))); +#if ( DEM_FF_DATA_IN_SEC_MEM ) + DEM_ASSERT( (0 == DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_HANDLE) || + (DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_SIZE == sizeof(secMemFreezeFrameBuffer))); +#endif +#if ( DEM_EXT_DATA_IN_SEC_MEM ) + DEM_ASSERT( (0 == DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_HANDLE ) || + (DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_SIZE == sizeof(secMemExtDataBuffer))); +#endif +#endif + +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) + DEM_ASSERT( (0 == DEM_INDICATOR_NVM_BLOCK_HANDLE ) || + (DEM_INDICATOR_NVM_BLOCK_SIZE == sizeof(indicatorBuffer))); +#endif +} +#endif + +/* + * Procedure: Dem_PreInit + * Reentrant: No + */ +void Dem_PreInit(const Dem_ConfigType *ConfigPtr) +{ + /** @req DEM180 */ + uint16 i; + + //VALIDATE_NO_RV(ConfigPtr != NULL, DEM_PREINIT_ID, DEM_E_CONFIG_PTR_INVALID); + // VALIDATE_NO_RV(ConfigPtr->ConfigSet != NULL, DEM_PREINIT_ID, DEM_E_CONFIG_PTR_INVALID); + + +#if defined(USE_NVM) && (DEM_USE_NVM == STD_ON) + validateNvMBlockSizes(); +#endif + + InitialModifyBuffers(); + + configSet = ConfigPtr->ConfigSet; + +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) + const Dem_DTCClassType *DTCClass = configSet->DTCClass; + while(!DTCClass->Arc_EOL) { + DemDTCSuppressed[DTCClass->DTCIndex].SuppressedByDTC = FALSE; + DemDTCSuppressed[DTCClass->DTCIndex].SuppressedByEvent = FALSE; + DTCClass++; + } +#endif + + // Initializion of operation cycle states. + for (i = 0; i < DEM_OPERATION_CYCLE_ID_ENDMARK; i++) { + operationCycleStateList[i] = DEM_CYCLE_STATE_END; + } + + // Initialize the event status buffer + for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + setDefaultEventStatus(&eventStatusBuffer[i]); + } + +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) + InitTimeBasedDebounce(); +#endif + +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) && defined(DEM_USE_MEMORY_FUNCTIONS) + SetDefaultUDSStatusBitSubset(); +#endif + + // Initialize the eventstatus buffer (Insert all supported events into event status buffer) + initEventStatusBuffer(configSet->EventParameter); + + /* Initialize the preInit freeze frame buffer */ +#if( DEM_FF_DATA_IN_PRE_INIT ) + initPreInitFreezeFrameBuffer(); +#endif + + /* Initialize the preInit extended data buffer */ + initPreInitExtDataBuffer(); + +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) + /* Initialize the enable conditions */ + initEnableConditions(); +#endif + +#if defined(USE_DEM_EXTENSION) + Dem_Extension_PreInit(ConfigPtr); +#endif + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + /* Reset freze frame time stamp */ + FF_TimeStamp = 0; + + /* Reset event time stamp */ + Event_TimeStamp = 0; + + /* Reset extended data timestamp */ + ExtData_TimeStamp = 0; +#endif + +#if defined(DEM_USE_INDICATORS) + initIndicatorStatusBuffer(configSet->EventParameter); +#endif + + disableDtcSetting.settingDisabled = FALSE; + + (void)setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_START); + + /* Init the DTC record update disable */ + DTCRecordDisabled.DTC = NO_DTC_DISABLED; + +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + priMemOverflow = FALSE; +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + secMemOverflow = FALSE; +#endif + + demState = DEM_PREINITIALIZED; +} + +#ifdef DEM_USE_MEMORY_FUNCTIONS +static boolean ValidateAndMergeEventRecords(EventRecType* eventBuffer, uint32 eventBufferSize, boolean* eventEntryChanged, + uint32* Evt_TimeStamp, Dem_DTCOriginType origin ) { + + + boolean eventBlockChanged = FALSE; + uint32 i; + + // Validate event records stored in memory + for (i = 0; i < eventBufferSize; i++) { + eventEntryChanged[i] = FALSE; + + if ((eventBuffer[i].EventData.eventId == DEM_EVENT_ID_NULL) || (checkEntryValid(eventBuffer[i].EventData.eventId, origin)==FALSE )) { + // Unlegal record, clear the record + memset(&eventBuffer[i], 0, sizeof(EventRecType)); + eventBlockChanged = TRUE; + } + #if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_OFF) + else { + // Valid, update current status + eventEntryChanged[i] = mergeEventStatusRec(&eventBuffer[i]); + } + #endif + } + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + /* initialize the current timestamp and update the timestamp in pre init */ + initCurrentEventTimeStamp(Evt_TimeStamp); +#else + (void)Evt_TimeStamp;/*lint !e920 *//* Avoid compiler warning */ +#endif + /* Merge events read from NvRam */ + for (i = 0; i < eventBufferSize; i++) { + eventEntryChanged[i] = FALSE; + if( DEM_EVENT_ID_NULL != eventBuffer[i].EventData.eventId ) { + eventEntryChanged[i] = mergeEventStatusRec(&eventBuffer[i]); + } + } +#else +(void)*Evt_TimeStamp;/* Avoid compiler warning */ +#endif + + return eventBlockChanged; + +} + +static void MergeBuffer(Dem_DTCOriginType origin) { + + uint16 i; + boolean eventBlockChanged; + boolean extendedDataBlockChanged; + boolean freezeFrameBlockChanged; + boolean eventEntryChanged[DEM_MAX_NUMBER_EVENT_ENTRY] = {0};/*lint !e506 */ + const Dem_EventParameterType *eventParam; + EventRecType* eventBuffer = NULL; + uint32 eventBufferSize = 0; + FreezeFrameRecType* freezeFrameBuffer = NULL; + uint32 freezeFrameBufferSize = 0; + ExtDataRecType* extendedDataBuffer = NULL; + uint32 extendedDataBufferSize = 0; + + /* Setup variables for merging */ + switch (origin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + eventBuffer = priMemEventBuffer; + eventBufferSize = DEM_MAX_NUMBER_EVENT_PRI_MEM; +#if ( DEM_FF_DATA_IN_PRI_MEM ) + freezeFrameBuffer = priMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; +#endif +#if ( DEM_EXT_DATA_IN_PRI_MEM ) + extendedDataBuffer = priMemExtDataBuffer; + extendedDataBufferSize = DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; +#endif +#endif + break; + + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + eventBuffer = secMemEventBuffer; + eventBufferSize = DEM_MAX_NUMBER_EVENT_SEC_MEM; +#if ( DEM_FF_DATA_IN_SEC_MEM ) + freezeFrameBuffer = secMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_SEC_MEM; +#endif +#if ( DEM_EXT_DATA_IN_SEC_MEM ) + extendedDataBuffer = secMemExtDataBuffer; + extendedDataBufferSize = DEM_MAX_NUMBER_EXT_DATA_SEC_MEM; +#endif +#endif + break; + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + + } + +#if !((DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL)) + /* The timestamp isn't actually used. This just to make it compile.. */ + uint32 Event_TimeStamp = 0; +#endif + eventBlockChanged = ValidateAndMergeEventRecords(eventBuffer, eventBufferSize, eventEntryChanged, &Event_TimeStamp, origin); + +#if defined(USE_DEM_EXTENSION) + Dem_Extension_Init_PostEventMerge(origin); +#endif + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + //initialize the current timestamp and update the timestamp in pre init + initCurrentFreezeFrameTimeStamp(&FF_TimeStamp); +#endif + + /* Validate freeze frames stored in memory */ + freezeFrameBlockChanged = validateFreezeFrames(freezeFrameBuffer, freezeFrameBufferSize, origin); + + /* Transfer updated event data to event memory */ + for (i = 0; (i < eventBufferSize) && (NULL != eventBuffer); i++) { + if ( (eventBuffer[i].EventData.eventId != DEM_EVENT_ID_NULL) && eventEntryChanged[i] ) { + EventStatusRecType *eventStatusRecPtr = NULL; + eventParam = NULL; + lookupEventIdParameter(eventBuffer[i].EventData.eventId, &eventParam); + /* Transfer to event memory. */ + lookupEventStatusRec(eventBuffer[i].EventData.eventId, &eventStatusRecPtr); + if( (NULL != eventStatusRecPtr) && (NULL != eventParam) ) { + if( E_OK == storeEventEvtMem(eventParam, eventStatusRecPtr) ) { + /* Use errorStatusChanged in eventsStatusBuffer to signal that the event data was updated */ + eventStatusRecPtr->errorStatusChanged = TRUE; + } + } + } + } + + /* Now we need to store events that was reported during preInit. + * That is, events not already stored in eventBuffer. */ + for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + if( (DEM_EVENT_ID_NULL != eventStatusBuffer[i].eventId) && + (0 == (eventStatusBuffer[i].eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) && + !eventIsStoredInMem(eventStatusBuffer[i].eventId, eventBuffer, eventBufferSize) ) { + + lookupEventIdParameter(eventStatusBuffer[i].eventId, &eventParam); + if( (NULL != eventParam) && (eventParam->EventClass->EventDestination == origin)) { + /* Destination check is needed two avoid notifying status change twice */ + notifyEventStatusChange(eventParam, DEM_DEFAULT_EVENT_STATUS, eventStatusBuffer[i].eventStatusExtended); + } + if( 0 != (eventStatusBuffer[i].eventStatusExtended & DEM_TEST_FAILED_THIS_OPERATION_CYCLE) ) { + if( E_OK == storeEventEvtMem(eventParam, &eventStatusBuffer[i]) ) { + /* Use errorStatusChanged in eventsStatusBuffer to signal that the event data was updated */ + eventStatusBuffer[i].errorStatusChanged = TRUE; + } + } + } + } + + // Validate extended data records stored in primary memory + extendedDataBlockChanged = validateExtendedData(extendedDataBuffer, extendedDataBufferSize, origin); + +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + //initialize the current timestamp and update the timestamp in pre init + initCurrentExtDataTimeStamp(&ExtData_TimeStamp); +#endif + +#if ( DEM_EXT_DATA_IN_PRE_INIT ) + /* Transfer extended data to event memory if necessary */ + for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++) { + if (preInitExtDataBuffer[i].eventId != DEM_EVENT_ID_NULL) { + boolean updateAllExtData = FALSE; + lookupEventIdParameter(preInitExtDataBuffer[i].eventId, &eventParam); +#if defined(USE_DEM_EXTENSION) + Dem_Extension_PreMergeExtendedData(preInitExtDataBuffer[i].eventId, &updateAllExtData); +#endif + if(mergeExtendedDataEvtMem(eventParam, &preInitExtDataBuffer[i], extendedDataBuffer, extendedDataBufferSize, origin, updateAllExtData)) { + /* Use errorStatusChanged in eventsStatusBuffer to signal that the event data was updated */ + EventStatusRecType *eventStatusRecPtr; + lookupEventStatusRec(eventParam->EventID, &eventStatusRecPtr); + if(NULL != eventStatusRecPtr) { + eventStatusRecPtr->errorStatusChanged = TRUE; + } + } + } + } +#endif + + /* Transfer freeze frames stored during preInit to event memory */ +#if ( DEM_FF_DATA_IN_PRE_INIT ) + if( transferPreInitFreezeFramesEvtMem(freezeFrameBuffer, freezeFrameBufferSize, eventBuffer, eventBufferSize, origin) ){ + freezeFrameBlockChanged = TRUE; + } +#endif + if( eventBlockChanged ) { + setEventBlockChanged(origin); + } + if( extendedDataBlockChanged ) { + setExtendedDataBlockChanged(origin); + } + if( freezeFrameBlockChanged ) { + setFreezeFrameBlockChanged(origin); + } +} + +#if (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) +/** + * Set the default value for UDS status bit subset if buffer is considered + * invalid. + */ +static void SetDefaultUDSStatusBitSubset(void) +{ + if( UDS_STATUS_BIT_MAGIC != statusBitSubsetBuffer[UDS_STATUS_BIT_MAGIC_INDEX] ) { + memset(statusBitSubsetBuffer, 0u, sizeof(statusBitSubsetBuffer)); + for(Dem_EventIdType i = (Dem_EventIdType)0u; i < DEM_MAX_NUMBER_EVENT; i++) { + statusBitSubsetBuffer[GET_UDSBIT_BYTE_INDEX(i+1u)] |= 1u<<(GET_UDS_STARTBIT(i+1u) + UDS_TNCSLC_BIT); + } + } + +} + +/** + * Merges UDS status bit subset to event buffer + */ +static void MergeUDSStatusBitSubset(void) +{ + EventStatusRecType *eventStatusRec; + if( UDS_STATUS_BIT_MAGIC == statusBitSubsetBuffer[UDS_STATUS_BIT_MAGIC_INDEX] ) { + for(Dem_EventIdType i = (Dem_EventIdType)0; i < DEM_MAX_NUMBER_EVENT; i++) { + eventStatusRec = NULL; + lookupEventStatusRec(i + 1u, &eventStatusRec); + if( (NULL != eventStatusRec) && eventStatusRec->isAvailable ) { + if( 0 == (statusBitSubsetBuffer[GET_UDSBIT_BYTE_INDEX(i+1u)] & (1u<<(GET_UDS_STARTBIT(i+1u) + UDS_TNCSLC_BIT))) ) { + eventStatusRec->eventStatusExtended &= ~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR); + } + if( 0 != (statusBitSubsetBuffer[GET_UDSBIT_BYTE_INDEX(i+1u)] & (1u<<(GET_UDS_STARTBIT(i+1u) + UDS_TFSLC_BIT))) ) { + eventStatusRec->eventStatusExtended |= DEM_TEST_FAILED_SINCE_LAST_CLEAR; + } + } + } + } +} + +/** + * Transfers subset of UDS status bits from event buffer to buffer for NvM storage + */ +static void StoreUDSStatusBitSubset(void) +{ + Dem_EventStatusExtendedType eventStatus; + const Dem_EventParameterType *eventParam; + + memset(statusBitSubsetBuffer, 0u, sizeof(statusBitSubsetBuffer)); + for(Dem_EventIdType i = (Dem_EventIdType)0; i < DEM_MAX_NUMBER_EVENT; i++) { + if(E_OK == getEventStatus(i + 1u, &eventStatus)) { + eventParam = NULL; + lookupEventIdParameter(i + 1u, &eventParam); + if( (NULL != eventParam) && (DEM_DTC_ORIGIN_NOT_USED != eventParam->EventClass->EventDestination)) { + if( 0 != (eventStatus & DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR) ) { + statusBitSubsetBuffer[GET_UDSBIT_BYTE_INDEX(i+1u)] |= 1u<<(GET_UDS_STARTBIT(i+1u) + UDS_TNCSLC_BIT); + } + if( 0 != (eventStatus & DEM_TEST_FAILED_SINCE_LAST_CLEAR) ) { + statusBitSubsetBuffer[GET_UDSBIT_BYTE_INDEX(i+1u)] |= 1u<<(GET_UDS_STARTBIT(i+1u) + UDS_TFSLC_BIT); + } + } + } + } + statusBitSubsetBuffer[UDS_STATUS_BIT_MAGIC_INDEX] = UDS_STATUS_BIT_MAGIC; + setStatusBitBlockChanged(); +} +#endif +#endif /* DEM_USE_MEMORY_FUNCTIONS */ + +/* + * Procedure: Dem_Init + * Reentrant: No + */ +void Dem_Init(void) +{ + /* @req DEM340 */ + // SchM_Enter_Dem_EA_0(); + for(uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + eventStatusBuffer[i].errorStatusChanged = FALSE; + } + if(DEM_PREINITIALIZED != demState){ + /* + * Dem_PreInit was has not been called since last time Dem_Shutdown was called. + * This suggests that we are resuming from sleep. According to section 5.7 in + * EcuM specification, RAM content is assumed to be still valid from the previous cycle. + * Do not read from saved error log since buffers already contains this data. + */ + (void)setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_START); + + } else { +#if defined(DEM_USE_MEMORY_FUNCTIONS) && (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) + MergeUDSStatusBitSubset(); +#endif +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) + mergeIndicatorBuffers(); +#endif +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + MergeBuffer(DEM_DTC_ORIGIN_PRIMARY_MEMORY); +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + MergeBuffer(DEM_DTC_ORIGIN_SECONDARY_MEMORY); +#endif + } + /* Notify application if event data was updated */ + for(uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + /* @req DEM475 */ + if( 0 != eventStatusBuffer[i].errorStatusChanged ) { + notifyEventDataChanged(eventStatusBuffer[i].eventParamRef); + eventStatusBuffer[i].errorStatusChanged = FALSE; + } + } +#if defined(USE_DEM_EXTENSION) + Dem_Extension_Init_Complete(); +#endif + +#if (DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) + if(ADMIN_MAGIC == priMemEventBuffer[PRI_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.magic) { + priMemOverflow = priMemEventBuffer[PRI_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow; + } +#endif +#if (DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) + if(ADMIN_MAGIC == secMemEventBuffer[SEC_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.magic) { + secMemOverflow = secMemEventBuffer[SEC_MEM_EVENT_BUFFER_ADMIN_INDEX].AdminData.overflow; + } +#endif + // Init the dtc filter + dtcFilter.dtcStatusMask = DEM_DTC_STATUS_MASK_ALL; // All allowed + dtcFilter.dtcKind = DEM_DTC_KIND_ALL_DTCS; // All kinds of DTCs + dtcFilter.dtcOrigin = DEM_DTC_ORIGIN_PRIMARY_MEMORY; // Primary memory + dtcFilter.filterWithSeverity = DEM_FILTER_WITH_SEVERITY_NO; // No Severity filtering + dtcFilter.dtcSeverityMask = DEM_SEVERITY_NO_SEVERITY; // Not used when filterWithSeverity is FALSE + dtcFilter.filterForFaultDetectionCounter = DEM_FILTER_FOR_FDC_NO; // No fault detection counter filtering + + dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT; + + disableDtcSetting.settingDisabled = FALSE; + + ffRecordFilter.ffIndex = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; + ffRecordFilter.dtcFormat = 0xff; + + demState = DEM_INITIALIZED; + + // SchM_Exit_Dem_EA_0(); +} + + +/* + * Procedure: Dem_shutdown + * Reentrant: No + */ +#if 1 +void Dem_Shutdown(void) +{ + // VALIDATE_NO_RV(DEM_INITIALIZED == demState, DEM_SHUTDOWN_ID, DEM_E_UNINIT); + /* @req DEM102 */ + // SchM_Enter_Dem_EA_0(); + + (void)setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_END); +#if defined(DEM_USE_MEMORY_FUNCTIONS) && (DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS == STD_ON) + StoreUDSStatusBitSubset(); +#endif +#if defined(USE_DEM_EXTENSION) + Dem_Extension_Shutdown(); +#endif + demState = DEM_UNINITIALIZED; /** @req DEM368 */ + + // SchM_Exit_Dem_EA_0(); +} +#endif +/* + * Interface for basic software scheduler + */ + +void Dem_MainFunction(void)/** @req DEM125 */ +{ + // VALIDATE_NO_RV(DEM_UNINITIALIZED != demState, DEM_MAINFUNCTION_ID, DEM_E_UNINIT); + +#ifdef DEM_USE_MEMORY_FUNCTIONS + for (uint32 i=0;i IndicatorId, DEM_GETINDICATORSTATUS_ID, DEM_E_PARAM_CONFIG, E_NOT_OK); + Std_ReturnType ret = E_NOT_OK; + const Dem_IndicatorType *indConfig; + const Dem_EventParameterType *eventParam; + uint8 currPrio = 0xff; + if( IndicatorId < DEM_NOF_INDICATORS ) { + indConfig = &configSet->Indicators[IndicatorId]; + *IndicatorStatus = DEM_INDICATOR_OFF; + for( uint8 indx = 0; indx < indConfig->EventListSize; indx++ ) { + eventParam = NULL; + lookupEventIdParameter(indConfig->EventList[indx], &eventParam); + if( (NULL != eventParam) && (NULL != eventParam->EventClass->IndicatorAttribute)) { + const Dem_IndicatorAttributeType *indAttrPtr = eventParam->EventClass->IndicatorAttribute; + while( !indAttrPtr->Arc_EOL ) { + if( indAttrPtr->IndicatorId == IndicatorId ) { + /* Found a match */ + ret = E_OK; + if( indicatorFailFulfilled(eventParam, indAttrPtr) ) { + if( eventParam->EventClass->EventPriority < currPrio ) { + *IndicatorStatus = indAttrPtr->IndicatorBehaviour; + currPrio = eventParam->EventClass->EventPriority; + } + } + } + indAttrPtr++; + } + } + } + } + return ret; +#else + (void)IndicatorId; + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETINDICATORSTATUS_ID, DEM_E_PARAM_CONFIG); + return E_NOT_OK; +#endif +} +#endif +/*************************************************** + * Interface SW-Components via RTE <-> DEM (8.3.3) * + ***************************************************/ + +/* + * Procedure: Dem_SetEventStatus + * Reentrant: Yes + */ +/* @req DEM183 */ +#if 1 +Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, Dem_EventStatusType eventStatus) /** @req DEM330 */ +{ + /* @req DEM330 */ + + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETEVENTSTATUS_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV(IS_VALID_EVENT_STATUS(eventStatus), DEM_SETEVENTSTATUS_ID, DEM_E_PARAM_DATA, E_NOT_OK); + // SchM_Enter_Dem_EA_0(); + + Std_ReturnType returnCode = handleEvent(eventId, eventStatus); + + // SchM_Exit_Dem_EA_0(); + + return returnCode; +} +#endif + +/* + * Procedure: Dem_ResetEventStatus + * Reentrant: Yes + */ +/* @req DEM185 */ +#if 0 +Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId) /** @req DEM331 */ +{ + /* @req DEM331 */ + Std_ReturnType returnCode; + VALIDATE_RV(DEM_INITIALIZED == demState, DEM_RESETEVENTSTATUS_ID, DEM_E_UNINIT, E_NOT_OK); + + SchM_Enter_Dem_EA_0(); + + /* Function resetEventStatus will notify application if there is a change in the status bits */ + returnCode = resetEventStatus(eventId); + + + SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif + +/* + * Procedure: Dem_GetEventStatus + * Reentrant: Yes + */ +#if 1 +Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended) +{ + Std_ReturnType returnCode; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTSTATUS_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV(NULL != eventStatusExtended, DEM_GETEVENTSTATUS_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + // SchM_Enter_Dem_EA_0(); + + returnCode = getEventStatus(eventId, eventStatusExtended); + + //SchM_Exit_Dem_EA_0(); + + return returnCode; +} +#endif + +/* + * Procedure: Dem_GetEventFailed + * Reentrant: Yes + */ +#if 1 +Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed) /** @req DEM333 */ +{ + /* @req DEM333 */ + Std_ReturnType returnCode; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTFAILED_ID, DEM_E_UNINIT, E_NOT_OK); + + //SchM_Enter_Dem_EA_0(); + + returnCode = getEventFailed(eventId, eventFailed); + + //SchM_Exit_Dem_EA_0(); + + return returnCode; +} +#endif + +/* + * Procedure: Dem_GetEventTested + * Reentrant: Yes + */ + #if 1 +Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested) +{ + /* @req DEM333 */ + Std_ReturnType returnCode; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTTESTED_ID, DEM_E_UNINIT, E_NOT_OK); + + // SchM_Enter_Dem_EA_0(); + + returnCode = getEventTested(eventId, eventTested); + + // SchM_Exit_Dem_EA_0(); + + return returnCode; +} + +#endif +/* + * Procedure: Dem_GetFaultDetectionCounter + * Reentrant: No + */ +#if 1 +Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter) +{ + /* @req DEM204 */ + Std_ReturnType returnCode; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_UNINIT, E_NOT_OK); + //SchM_Enter_Dem_EA_0(); + + returnCode = getFaultDetectionCounter(eventId, counter); + + //SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif + +/* + * Procedure: Dem_SetOperationCycleState + * Reentrant: No + */ +#if 1 +Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState) +{ + Std_ReturnType returnCode = E_OK; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_UNINIT, E_NOT_OK); + //SchM_Enter_Dem_EA_0(); + + if( DEM_ACTIVE == operationCycleId ) { + /* Handled internally */ + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_UNEXPECTED_EXECUTION); + returnCode = E_NOT_OK; + } else { + returnCode = setOperationCycleState(operationCycleId, cycleState); + } + + // SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif + +/* + * Procedure: Dem_GetDTCOfEvent + * Reentrant: Yes + */ +#if 1 +Std_ReturnType Dem_GetDTCOfEvent(Dem_EventIdType eventId, Dem_DTCFormatType dtcFormat, uint32* dtcOfEvent) +{ + Std_ReturnType returnCode = E_NO_DTC_AVAILABLE; + const Dem_EventParameterType *eventParam; + EventStatusRecType * eventStatusRec; + + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETDTCOFEVENT_ID, DEM_E_UNINIT, E_NOT_OK); + //VALIDATE_RV(IS_VALID_DTC_FORMAT(dtcFormat), DEM_GETDTCOFEVENT_ID, DEM_E_PARAM_DATA, E_NOT_OK); + + // SchM_Enter_Dem_EA_0(); + + lookupEventIdParameter(eventId, &eventParam); + lookupEventStatusRec(eventId, &eventStatusRec); + if ( (eventParam != NULL) && (NULL != eventStatusRec) && eventStatusRec->isAvailable) { + if ((eventParam->DTCClassRef != NULL) && eventParam->DTCClassRef->DTCRef->DTCUsed) { + if( eventHasDTCOnFormat(eventParam, dtcFormat) ) { + *dtcOfEvent = (DEM_DTC_FORMAT_UDS == dtcFormat) ? eventParam->DTCClassRef->DTCRef->UDSDTC : TO_OBD_FORMAT(eventParam->DTCClassRef->DTCRef->OBDDTC);/** @req DEM269 */ + returnCode = E_OK; + } + } + } else { + // Event Id not found + returnCode = E_NOT_OK; + } + + // SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif + +/******************************************** + * Interface BSW-Components <-> DEM (8.3.4) * + ********************************************/ + +/* + * Procedure: Dem_ReportErrorStatus + * Reentrant: Yes + */ +#if 1 +void Dem_ReportErrorStatus( Dem_EventIdType eventId, Dem_EventStatusType eventStatus ) /** @req DEM206 */ +{ + /* @req DEM330 */ + /* @req DEM107 */ + // VALIDATE_NO_RV(DEM_UNINITIALIZED != demState, DEM_REPORTERRORSTATUS_ID, DEM_E_UNINIT); + // VALIDATE_NO_RV(IS_VALID_EVENT_STATUS(eventStatus), DEM_REPORTERRORSTATUS_ID, DEM_E_PARAM_DATA); + + //SchM_Enter_Dem_EA_0(); + + switch (demState) { + case DEM_PREINITIALIZED: + // Update status and check if is to be stored + if ((eventStatus == DEM_EVENT_STATUS_PASSED) || (eventStatus == DEM_EVENT_STATUS_FAILED)) { + handlePreInitEvent(eventId, eventStatus); /** @req DEM167 */ + } + break; + + case DEM_INITIALIZED: + (void)handleEvent(eventId, eventStatus); + break; + + case DEM_UNINITIALIZED: + default: + // Uninitialized can not do anything + break; + + } // switch (demState) + + //SchM_Exit_Dem_EA_0(); +} +#endif +/********************************* + * Interface DCM <-> DEM (8.3.5) * + *********************************/ +/* + * Procedure: Dem_GetDTCStatusAvailabilityMask + * Reentrant: No + */ +/*lint -esym(793, Dem_GetDTCStatusAvailabilityMask) Function name defined by AUTOSAR. */ +Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask) /** @req DEM014 */ +{ + /** @req DEM060 */ + *dtcStatusMask = DEM_DTC_STATUS_AVAILABILITY_MASK; // User configuration mask + return E_OK; +} + + +/* + * Procedure: Dem_SetDTCFilter + * Reentrant: No + */ +Dem_ReturnSetFilterType Dem_SetDTCFilter(uint8 dtcStatusMask, + Dem_DTCKindType dtcKind, + Dem_DTCFormatType dtcFormat, + Dem_DTCOriginType dtcOrigin, + Dem_FilterWithSeverityType filterWithSeverity, + Dem_DTCSeverityType dtcSeverityMask, + Dem_FilterForFDCType filterForFaultDetectionCounter) +{ + Dem_ReturnSetFilterType returnCode = DEM_FILTER_ACCEPTED; + uint8 dtcStatusAvailabilityMask; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETDTCFILTER_ID, DEM_E_UNINIT, E_NOT_OK); + + // Check dtcKind parameter + //VALIDATE_RV((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + // Check dtcOrigin parameter + //VALIDATE_RV((dtcOrigin == DEM_DTC_ORIGIN_SECONDARY_MEMORY) || (dtcOrigin == DEM_DTC_ORIGIN_PRIMARY_MEMORY), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + // Check filterWithSeverity and dtcSeverityMask parameter + // VALIDATE_RV(((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_NO) + // || ((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES) + // && (0 == (dtcSeverityMask & (Dem_DTCSeverityType)~(DEM_SEVERITY_MAINTENANCE_ONLY | DEM_SEVERITY_CHECK_AT_NEXT_HALT | DEM_SEVERITY_CHECK_IMMEDIATELY))))), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + // Check filterForFaultDetectionCounter parameter + //VALIDATE_RV((filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_YES) || (filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_NO), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + // VALIDATE_RV( IS_VALID_DTC_FORMAT(dtcFormat), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + (void)Dem_GetDTCStatusAvailabilityMask(&dtcStatusAvailabilityMask); + + if( (0u == (dtcStatusMask & dtcStatusAvailabilityMask)) && (DEM_DTC_STATUS_MASK_ALL != dtcStatusMask) ) { + /* No bit in the filter mask supported. */ + returnCode = DEM_WRONG_FILTER; + } else { + // Yes all parameters correct, set the new filters. /** @req DEM057 */ + dtcFilter.dtcStatusMask = dtcStatusMask & dtcStatusAvailabilityMask; + dtcFilter.dtcKind = dtcKind; + dtcFilter.dtcOrigin = dtcOrigin; + dtcFilter.filterWithSeverity = filterWithSeverity; + dtcFilter.dtcSeverityMask = dtcSeverityMask; + dtcFilter.filterForFaultDetectionCounter = filterForFaultDetectionCounter; + dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT; + dtcFilter.dtcFormat = dtcFormat; + } + + return returnCode; +} + + +/* + * Procedure: Dem_GetStatusOfDTC + * Reentrant: No + */ +Dem_ReturnGetStatusOfDTCType Dem_GetStatusOfDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, Dem_EventStatusExtendedType* status) { + /* NOTE: dtc is in UDS format according to DEM212 */ + Dem_ReturnGetStatusOfDTCType returnCode = DEM_STATUS_FAILED; + EventStatusRecType *eventRec; + + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETSTATUSOFDTC_ID, DEM_E_UNINIT, DEM_STATUS_FAILED); + //VALIDATE_RV(IS_SUPPORTED_ORIGIN(dtcOrigin), DEM_GETSTATUSOFDTC_ID, DEM_E_PARAM_DATA, DEM_STATUS_WRONG_DTCORIGIN);/** @req DEM171 */ + + // SchM_Enter_Dem_EA_0(); + + if (lookupEventOfUdsDTC(dtc, &eventRec)==TRUE) { + /* Event found for this DTC */ + if (checkDtcOrigin(dtcOrigin,eventRec->eventParamRef)==TRUE) { + /* NOTE: Should the availability mask be used here? */ + *status = eventRec->eventStatusExtended; /** @req DEM059 */ + returnCode = DEM_STATUS_OK; + + } else { + /* Here we know that dtcOrigin is a supported one */ + returnCode = DEM_STATUS_WRONG_DTC; /** @req DEM172 */ + } + } else { + /* Event has no DTC or DTC is suppressed */ + /* @req 4.2.2/SWS_Dem_01100 *//* @req DEM587 */ + returnCode = DEM_STATUS_WRONG_DTC; + } + + // SchM_Exit_Dem_EA_0(); + + return returnCode; +} + + +/* + * Procedure: Dem_GetNumberOfFilteredDtc + * Reentrant: No + */ +Dem_ReturnGetNumberOfFilteredDTCType Dem_GetNumberOfFilteredDtc(uint16 *numberOfFilteredDTC) { + uint16 i; + uint16 numberOfFaults = 0; + Dem_ReturnGetNumberOfFilteredDTCType returnCode = DEM_NUMBER_OK; + + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETNUMBEROFFILTEREDDTC_ID, DEM_E_UNINIT, DEM_NUMBER_FAILED); + // VALIDATE_RV(NULL != numberOfFilteredDTC, DEM_GETNUMBEROFFILTEREDDTC_ID, DEM_E_PARAM_POINTER, DEM_NUMBER_FAILED); + // SchM_Enter_Dem_EA_0(); + + //Dem_DisableEventStatusUpdate(); + /* Find all DTCs matching filter. Ignore suppressed DTCs *//* @req DEM587 *//* @req 4.2.2/SWS_Dem_01101 */ + for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) { + if (matchEventWithDtcFilter(&eventStatusBuffer[i])==TRUE) { + numberOfFaults++; + } + } + } + + //Dem_EnableEventStatusUpdate(); + + *numberOfFilteredDTC = numberOfFaults; /** @req DEM061 */ + + //SchM_Exit_Dem_EA_0(); + return returnCode; +} + + +/* + * Procedure: Dem_GetNextFilteredDTC + * Reentrant: No + */ +#if 1 +Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredDTC(uint32 *dtc, Dem_EventStatusExtendedType *dtcStatus) +{ + Dem_ReturnGetNextFilteredDTCType returnCode = DEM_FILTERED_OK; + boolean dtcFound = FALSE; + + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETNEXTFILTEREDDTC_ID, DEM_E_UNINIT, DEM_FILTERED_NO_MATCHING_DTC); + // VALIDATE_RV(NULL != dtc, DEM_GETNEXTFILTEREDDTC_ID, DEM_E_PARAM_POINTER, DEM_FILTERED_NO_MATCHING_DTC); + // VALIDATE_RV(NULL != dtcStatus, DEM_GETNEXTFILTEREDDTC_ID, DEM_E_PARAM_POINTER, DEM_FILTERED_NO_MATCHING_DTC); + + //SchM_Enter_Dem_EA_0(); + + /* Find the next DTC matching filter. Ignore suppressed DTCs *//* @req DEM587 *//* @req 4.2.2/SWS_Dem_01101 */ + /* @req DEM217 */ + while ((dtcFound==FALSE) && (dtcFilter.faultIndex != 0)) { + dtcFilter.faultIndex--; + if (eventStatusBuffer[dtcFilter.faultIndex].eventId != DEM_EVENT_ID_NULL) { + if (matchEventWithDtcFilter(&eventStatusBuffer[dtcFilter.faultIndex])==TRUE) { + if( DEM_DTC_FORMAT_UDS == dtcFilter.dtcFormat ) { + *dtc = eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef->DTCRef->UDSDTC; /** @req DEM216 */ + } + else { + *dtc = TO_OBD_FORMAT(eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef->DTCRef->OBDDTC); + } + *dtcStatus = eventStatusBuffer[dtcFilter.faultIndex].eventStatusExtended; + dtcFound = TRUE; + } + } + } + + if (dtcFound == FALSE) { + dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT; + returnCode = DEM_FILTERED_NO_MATCHING_DTC; + } + + //SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif + +/* + * Procedure: Dem_GetTranslationType + * Reentrant: No + */ +#if 0 +Dem_DTCTranslationFormatType Dem_GetTranslationType(void) +{ + return DEM_TYPE_OF_DTC_SUPPORTED; /** @req DEM231 */ +} +#endif +/* + * Procedure: Dem_ClearDTC + * Comment: Stating the dtcOrigin makes no since when reading the reqiurements in the specification. + * Reentrant: No + */ +Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCFormatType dtcFormat, Dem_DTCOriginType dtcOrigin) /** @req DEM009 *//** @req DEM241 */ +{ + Dem_ReturnClearDTCType returnCode = DEM_CLEAR_WRONG_DTCORIGIN; + const Dem_EventParameterType *eventParam; + Dem_EventStatusExtendedType oldStatus; + boolean dataDeleted; +#ifdef DEM_USE_MEMORY_FUNCTIONS + boolean allClearOK = TRUE; +#endif + (void)dtcOrigin; +#if defined(DEM_USE_INDICATORS) && defined(DEM_USE_MEMORY_FUNCTIONS) + boolean indicatorsChanged = FALSE; +#endif + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_CLEARDTC_ID, DEM_E_UNINIT, DEM_CLEAR_FAILED); + // VALIDATE_RV(IS_VALID_DTC_FORMAT(dtcFormat), DEM_CLEARDTC_ID, DEM_E_PARAM_DATA, DEM_CLEAR_FAILED); + //SchM_Enter_Dem_EA_0(); + + for (uint16 i = 0; i < DEM_MAX_NUMBER_EVENT; i++) { + dataDeleted = FALSE; + if ((DEM_EVENT_ID_NULL != eventStatusBuffer[i].eventId) && (NULL != eventStatusBuffer[i].eventParamRef)) { + eventParam = eventStatusBuffer[i].eventParamRef; + if ((DEM_CLEAR_ALL_EVENTS == STD_ON) || (eventParam->DTCClassRef != NULL)) {/*lint !e506 !e774*/ + if (checkDtcGroup(dtc, eventParam, dtcFormat) == TRUE) { + if( eventParam->EventClass->EventDestination == dtcOrigin ) { + if(FALSE == eventDTCRecordDataUpdateDisabled(eventParam)) { + if( clearEventAllowed(eventParam)==TRUE) { + boolean dtcOriginFound = FALSE; + oldStatus = eventStatusBuffer[i].eventStatusExtended; + dataDeleted = DeleteDTCData(eventParam, TRUE, &dtcOriginFound);/* @req DEM343 */ + + if (dtcOriginFound==FALSE) { + returnCode = DEM_CLEAR_WRONG_DTCORIGIN; + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_NOT_IMPLEMENTED_YET); + } else { +#if defined(DEM_USE_INDICATORS) + if( resetIndicatorCounters(eventParam) ) { +#ifdef DEM_USE_MEMORY_FUNCTIONS + indicatorsChanged = TRUE; +#endif + } +#endif +#if defined(USE_DEM_EXTENSION) + Dem_Extension_ClearEvent(eventParam); +#endif + + if( dataDeleted==TRUE) { + /* @req DEM475 */ + notifyEventDataChanged(eventParam); + } + if( oldStatus != eventStatusBuffer[i].eventStatusExtended ) { + /* @req DEM016 */ + notifyEventStatusChange(eventParam, oldStatus, eventStatusBuffer[i].eventStatusExtended); + } + if( NULL != eventParam->CallbackInitMforE ) { + /* @req DEM376 */ + (void)eventParam->CallbackInitMforE(DEM_INIT_MONITOR_CLEAR); + } + /* Have cleared at least one, OK */ + returnCode = DEM_CLEAR_OK; + } + } else { + returnCode = DEM_CLEAR_FAILED; /* CallbackClearEventAllowed returned not allowed to clear */ +#ifdef DEM_USE_MEMORY_FUNCTIONS + /* Clear was not allowed */ + allClearOK = FALSE; +#endif + } + } + } + } else { + if( (((DEM_DTC_FORMAT_UDS == dtcFormat) && (dtc == eventParam->DTCClassRef->DTCRef->UDSDTC)) || + ((DEM_DTC_FORMAT_OBD == dtcFormat) && (dtc == TO_OBD_FORMAT(eventParam->DTCClassRef->DTCRef->OBDDTC)))) + && (DTCIsAvailable(eventParam->DTCClassRef)==FALSE) ) { + /* This DTC is suppressed *//* @req 4.2.2/SWS_Dem_01101 */ + returnCode = DEM_CLEAR_WRONG_DTC; + } + } + } + } else { + // Fatal error, no event parameters found for the event! + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_UNEXPECTED_EXECUTION); + } + } +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if defined(DEM_USE_INDICATORS) + if( indicatorsChanged ==TRUE ) { + setIndicatorBlockChanged(); + } +#endif + if( (DEM_DTC_GROUP_ALL_DTCS == dtc) && (allClearOK==TRUE)) { + /* @req DEM399 */ + setOverflowIndication(dtcOrigin, FALSE); + } +#endif + + // SchM_Exit_Dem_EA_0(); + + return returnCode; +} + + +/* + * Procedure: Dem_DisableDTCStorage + * Reentrant: No + */ +Dem_ReturnControlDTCStorageType Dem_DisableDTCSetting(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind) /** @req DEM035 */ +{ + Dem_ReturnControlDTCStorageType returnCode = DEM_CONTROL_DTC_STORAGE_OK; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_DISABLEDTCSETTING_ID, DEM_E_UNINIT, DEM_CONTROL_DTC_STORAGE_N_OK); + // Check dtcGroup parameter + uint32 DTCGroupLower; + uint32 DTCGroupUpper; + if ( (dtcGroup == DEM_DTC_GROUP_ALL_DTCS) || (DEM_DTC_GROUP_EMISSION_REL_DTCS == dtcGroup) || (TRUE == dtcIsGroup(dtcGroup, DEM_DTC_FORMAT_UDS, &DTCGroupLower, &DTCGroupUpper))) { + // Check dtcKind parameter + if ((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS)) { + /** @req DEM079 */ + disableDtcSetting.dtcGroup = dtcGroup; + disableDtcSetting.dtcKind = dtcKind; + disableDtcSetting.settingDisabled = TRUE; + } else { + returnCode = DEM_CONTROL_DTC_STORAGE_N_OK; + } + } else { + returnCode = DEM_CONTROL_DTC_WRONG_DTCGROUP; + } + + return returnCode; +} + + +/* + * Procedure: Dem_EnableDTCStorage + * Reentrant: No + */ +Dem_ReturnControlDTCStorageType Dem_EnableDTCSetting(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind) +{ + Dem_ReturnControlDTCStorageType returnCode = DEM_CONTROL_DTC_STORAGE_OK; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_ENABLEDTCSETTING_ID, DEM_E_UNINIT, DEM_CONTROL_DTC_STORAGE_N_OK); + + // NOTE: Behavior is not defined if group or kind do not match active settings, therefore the filter is just switched off. + (void)dtcGroup; (void)dtcKind; // Just to make get rid of PC-Lint warnings + disableDtcSetting.settingDisabled = FALSE; /** @req DEM080 */ + + return returnCode; +} + + + +/* + * Procedure: Dem_GetExtendedDataRecordByDTC + * Reentrant: No + */ +Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint16 *bufSize) +{ + /* IMPROVEMENT: Handle record numbers 0xFE and 0xFF */ + /* NOTE: dtc is in UDS format according to DEM239 */ + Dem_ReturnGetExtendedDataRecordByDTCType returnCode = DEM_RECORD_WRONG_DTC; + EventStatusRecType *eventRec; + Dem_ExtendedDataRecordClassType const *extendedDataRecordClass = NULL; + ExtDataRecType *extData; + uint16 posInExtData = 0; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_UNINIT, DEM_RECORD_WRONG_DTC); + //VALIDATE_RV((NULL != destBuffer), DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_PARAM_POINTER, DEM_RECORD_WRONG_DTC); + //VALIDATE_RV((NULL != bufSize), DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_PARAM_POINTER, DEM_RECORD_WRONG_DTC); + // SchM_Enter_Dem_EA_0(); + + if( extendedDataNumber <= DEM_HIGHEST_EXT_DATA_REC_NUM ) { + if (lookupEventOfUdsDTC(dtc, &eventRec)==TRUE) { + if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)==TRUE) { + if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)==TRUE) { + if (*bufSize >= extendedDataRecordClass->DataSize) { + if( extendedDataRecordClass->UpdateRule != DEM_UPDATE_RECORD_VOLATILE ) { + switch (dtcOrigin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: + if (lookupExtendedDataMem(eventRec->eventId, &extData, dtcOrigin)==TRUE) { + // Yes all conditions met, copy the extended data record to destination buffer. + memcpy(destBuffer, &extData->data[posInExtData], extendedDataRecordClass->DataSize); /** @req DEM075 */ + *bufSize = extendedDataRecordClass->DataSize;/* @req DEM076 */ + returnCode = DEM_RECORD_OK; + } else { + /* The record number is legal but no record was found for the DTC *//* @req DEM631 */ + *bufSize = 0; + returnCode = DEM_RECORD_OK; + } + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + returnCode = DEM_RECORD_WRONG_DTCORIGIN; + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + returnCode = DEM_RECORD_WRONG_DTCORIGIN; + break; + } + } else { + if( NULL != extendedDataRecordClass->CallbackGetExtDataRecord ) { + /* IMPROVEMENT: Handle return value? */ + (void)extendedDataRecordClass->CallbackGetExtDataRecord(destBuffer); + *bufSize = extendedDataRecordClass->DataSize; + returnCode = DEM_RECORD_OK; + } else if (DEM_NO_ELEMENT != extendedDataRecordClass->InternalDataElement ) { + getInternalElement( eventRec->eventParamRef, extendedDataRecordClass->InternalDataElement, destBuffer, extendedDataRecordClass->DataSize ); + *bufSize = extendedDataRecordClass->DataSize; + returnCode = DEM_RECORD_OK; + } else { + returnCode = DEM_RECORD_WRONG_DTC; + } + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_PARAM_LENGTH); + returnCode = DEM_RECORD_BUFFERSIZE; + } + } else { + returnCode = DEM_RECORD_NUMBER; + } + } else { + returnCode = DEM_RECORD_WRONG_DTCORIGIN; + } + } else { + /* Event has no DTC or DTC is suppressed */ + /* @req 4.2.2/SWS_Dem_01100 */ + /* @req 4.2.2/SWS_Dem_01101 */ + /* @req DEM587 */ + returnCode = DEM_RECORD_WRONG_DTC; + } + } else { + returnCode = DEM_RECORD_NUMBER; + } + + // SchM_Exit_Dem_EA_0(); + return returnCode; +} + + +/* + * Procedure: Dem_GetSizeOfExtendedDataRecordByDTC + * Reentrant: No + */ +/*lint -esym(793, Dem_GetSizeOfExtendedDataRecordByDTC) Function name defined by AUTOSAR. */ +#if 1 +Dem_ReturnGetSizeOfExtendedDataRecordByDTCType Dem_GetSizeOfExtendedDataRecordByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint16 *sizeOfExtendedDataRecord) +{ + /* NOTE: dtc is in UDS format according to DEM240 */ + Dem_ReturnGetExtendedDataRecordByDTCType returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTC; + EventStatusRecType *eventRec; + Dem_ExtendedDataRecordClassType const *extendedDataRecordClass = NULL; + uint16 posInExtData; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETSIZEOFEXTENDEDDATARECORDBYDTC_ID, DEM_E_UNINIT, DEM_GET_SIZEOFEDRBYDTC_W_DTC); + //VALIDATE_RV(NULL != sizeOfExtendedDataRecord, DEM_GETSIZEOFEXTENDEDDATARECORDBYDTC_ID, DEM_E_PARAM_POINTER, DEM_GET_SIZEOFEDRBYDTC_W_DTC); + //SchM_Enter_Dem_EA_0(); + + /* Check if event has DTC and that the DTC is not suppressed *//* @req DEM587 */ + /* @req 4.2.2/SWS_Dem_01100 */ + /* @req 4.2.2/SWS_Dem_01101 */ + if (lookupEventOfUdsDTC(dtc, &eventRec)==TRUE) { + if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)==TRUE) { + if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)==TRUE) { + *sizeOfExtendedDataRecord = extendedDataRecordClass->DataSize; /** @req DEM076 */ + returnCode = DEM_GET_SIZEOFEDRBYDTC_OK; + } + else { + returnCode = DEM_GET_SIZEOFEDRBYDTC_W_RNUM; + } + } + else { + returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTCOR; + } + } + + // SchM_Exit_Dem_EA_0(); + return returnCode; +} +#endif +/* + * Procedure: Dem_GetFreezeFrameDataByDTC + * Reentrant: No + */ +/** @req DEM236 */ +#if 1 +Dem_ReturnGetFreezeFrameDataByDTCType Dem_GetFreezeFrameDataByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 recordNumber, uint8* destBuffer, uint16* bufSize) +{ + /* !req DEM576 */ + /* NOTE: dtc is in UDS format according to DEM236 */ + Dem_ReturnGetFreezeFrameDataByDTCType returnCode = DEM_GET_FFDATABYDTC_WRONG_DTC; + EventStatusRecType *eventRec; + Dem_FreezeFrameClassType const *FFDataRecordClass = NULL; + uint16 FFDataSize = 0; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETFREEZEFRAMEDATABYDTC_ID, DEM_E_UNINIT, DEM_GET_ID_PENDING); + //VALIDATE_RV((NULL != destBuffer), DEM_GETFREEZEFRAMEDATABYDTC_ID, DEM_E_PARAM_POINTER, DEM_GET_FFDATABYDTC_WRONG_DTC); + //VALIDATE_RV((NULL != bufSize), DEM_GETFREEZEFRAMEDATABYDTC_ID, DEM_E_PARAM_POINTER, DEM_GET_FFDATABYDTC_WRONG_DTC); + // SchM_Enter_Dem_EA_0(); + + if( recordNumber <= DEM_HIGHEST_FF_REC_NUM ) { + if (lookupEventOfUdsDTC(dtc, &eventRec)==TRUE) { + if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)==TRUE) { + if (lookupFreezeFrameDataRecNumParam(recordNumber, eventRec->eventParamRef, &FFDataRecordClass)==TRUE) { + /* NOTE: Handle return value? */ + (void)lookupFreezeFrameDataSize(recordNumber, &FFDataRecordClass, &FFDataSize); + if (*bufSize >= FFDataSize) { + switch (dtcOrigin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: + if (getFreezeFrameRecord(eventRec->eventId, recordNumber, FFDataRecordClass, dtcOrigin, destBuffer, bufSize, &FFDataSize)==TRUE) { + returnCode = DEM_GET_FFDATABYDTC_OK; + } else { + /* @req DEM630 */ + *bufSize = 0; + returnCode = DEM_GET_FFDATABYDTC_OK; + } + break; + case DEM_DTC_ORIGIN_PERMANENT_MEMORY: + case DEM_DTC_ORIGIN_MIRROR_MEMORY: + // Not yet supported + returnCode = DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN; + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFREEZEFRAMEDATABYDTC_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + default: + returnCode = DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN; + break; + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFREEZEFRAMEDATABYDTC_ID, DEM_E_PARAM_LENGTH); + returnCode = DEM_GET_FFDATABYDTC_BUFFERSIZE; + } + } else { + returnCode = DEM_GET_FFDATABYDTC_RECORDNUMBER; + } + } else { + returnCode = DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN; + } + } else { + /* Event has no DTC or DTC is suppressed */ + /* @req 4.2.2/SWS_Dem_01100 */ + /* @req 4.2.2/SWS_Dem_01101 */ + /* @req DEM587 */ + returnCode = DEM_GET_FFDATABYDTC_WRONG_DTC; + + } + } else { + returnCode = DEM_GET_FFDATABYDTC_RECORDNUMBER; + } + + // SchM_Exit_Dem_EA_0(); + + return returnCode; + + +} +#endif +/* + * Procedure: Dem_GetSizeOfFreezeFrame + * Reentrant: No + */ + /** @req DEM238 */ +#if 0 +Dem_ReturnGetSizeOfFreezeFrameType Dem_GetSizeOfFreezeFrameByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 recordNumber, uint16* sizeOfFreezeFrame) +{ + /* NOTE: dtc is in UDS format according to DEM238 */ + Dem_ReturnGetSizeOfFreezeFrameType returnCode = DEM_GET_SIZEOFFF_PENDING; + Dem_FreezeFrameClassType const *FFDataRecordClass = NULL; + EventStatusRecType *eventRec; + uint16 i = 0; + VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETSIZEOFFREEZEFRAMEBYDTC_ID, DEM_E_UNINIT, DEM_GET_SIZEOFFF_PENDING); + VALIDATE_RV((NULL != sizeOfFreezeFrame), DEM_GETSIZEOFFREEZEFRAMEBYDTC_ID, DEM_E_PARAM_POINTER, DEM_GET_SIZEOFFF_WRONG_DTC); + SchM_Enter_Dem_EA_0(); + + if (lookupEventOfUdsDTC(dtc, &eventRec)==TRUE) { + if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)==TRUE) { + if (lookupFreezeFrameDataRecNumParam(recordNumber, eventRec->eventParamRef, &FFDataRecordClass)==TRUE) { + if(FFDataRecordClass->FFIdClassRef != NULL){ + /* Note - there is a function called lookupFreezeFrameDataSize that can be used here */ + *sizeOfFreezeFrame = 0; + for(i = 0; (i < DEM_MAX_NR_OF_DIDS_IN_FREEZEFRAME_DATA) && ((FFDataRecordClass->FFIdClassRef[i]->Arc_EOL ==FALSE)); i++){ + /* read out the did size */ + *sizeOfFreezeFrame += (FFDataRecordClass->FFIdClassRef[i]->PidOrDidSize + DEM_DID_IDENTIFIER_SIZE_OF_BYTES);/** @req DEM074 */ + returnCode = DEM_GET_SIZEOFFF_OK; + } + } else { + returnCode = DEM_GET_SIZEOFFF_WRONG_RNUM; + } + } else { + returnCode = DEM_GET_SIZEOFFF_WRONG_RNUM; + } + } else { + returnCode = DEM_GET_SIZEOFFF_WRONG_DTCOR; + } + } else { + /* Event has no DTC or DTC is suppressed */ + /* @req 4.2.2/SWS_Dem_01100 */ + /* @req 4.2.2/SWS_Dem_01101 */ + /* @req DEM587 */ + returnCode = DEM_GET_SIZEOFFF_WRONG_DTC; + } + + SchM_Exit_Dem_EA_0(); + return returnCode; + + +} +#endif +/** + * + * @param DTCFormat + * @param NumberOfFilteredRecords + * @return + */ +Dem_ReturnSetFilterType Dem_SetFreezeFrameRecordFilter(Dem_DTCFormatType DTCFormat, uint16 *NumberOfFilteredRecords) +{ + Dem_ReturnSetFilterType ret = DEM_WRONG_FILTER; + uint16 nofRecords = 0; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETFREEZEFRAMERECORDFILTER_ID, DEM_E_UNINIT, DEM_WRONG_FILTER); + // VALIDATE_RV((NULL != NumberOfFilteredRecords), DEM_SETFREEZEFRAMERECORDFILTER_ID, DEM_E_PARAM_POINTER, DEM_WRONG_FILTER); + //VALIDATE_RV(IS_VALID_DTC_FORMAT(DTCFormat), DEM_SETFREEZEFRAMERECORDFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER); + + // SchM_Enter_Dem_EA_0(); + + /* @req DEM210 Only applies to primary memory */ +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + for( uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++ ) { + if( DEM_EVENT_ID_NULL != priMemFreezeFrameBuffer[i].eventId ) { + EventStatusRecType *eventStatusRecPtr = NULL; + lookupEventStatusRec(priMemFreezeFrameBuffer[i].eventId, &eventStatusRecPtr); + if( (NULL != eventStatusRecPtr) && eventHasDTCOnFormat(eventStatusRecPtr->eventParamRef, DTCFormat) && + DTCIsAvailable(eventStatusRecPtr->eventParamRef->DTCClassRef) ) { + nofRecords++; + } + } + } +#endif + *NumberOfFilteredRecords = nofRecords; + /* @req DEM595 */ + ffRecordFilter.dtcFormat = DTCFormat; + ffRecordFilter.ffIndex = 0; + + ret = DEM_FILTER_ACCEPTED; + + //SchM_Exit_Dem_EA_0(); + return ret; +} + + +#if 0 +Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredRecord(uint32 *DTC, uint8 *RecordNumber) +{ + /* No requirement on checking the pointers but do it anyway. */ + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETNEXTFILTEREDRECORD_ID, DEM_E_UNINIT, DEM_FILTERED_NO_MATCHING_DTC); + // VALIDATE_RV(NULL != DTC, DEM_GETNEXTFILTEREDRECORD_ID, DEM_E_PARAM_POINTER, DEM_FILTERED_NO_MATCHING_DTC); + // VALIDATE_RV(NULL != RecordNumber, DEM_GETNEXTFILTEREDRECORD_ID, DEM_E_PARAM_POINTER, DEM_FILTERED_NO_MATCHING_DTC); + Dem_ReturnGetNextFilteredDTCType ret = DEM_FILTERED_NO_MATCHING_DTC; + SchM_Enter_Dem_EA_0(); + +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + /* Find the next record which has a DTC */ + EventStatusRecType *eventStatusRecPtr = NULL; + boolean found = FALSE; + for( uint16 i = ffRecordFilter.ffIndex; (i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM) && !found; i++ ) { + if( DEM_EVENT_ID_NULL != priMemFreezeFrameBuffer[i].eventId ) { + lookupEventStatusRec(priMemFreezeFrameBuffer[i].eventId, &eventStatusRecPtr); + /* @req 4.2.2/SWS_Dem_01101 *//* @req DEM587 */ + if( (NULL != eventStatusRecPtr) && eventHasDTCOnFormat(eventStatusRecPtr->eventParamRef, ffRecordFilter.dtcFormat) && + DTCIsAvailable(eventStatusRecPtr->eventParamRef->DTCClassRef) ) { + /* Found one! */ + /* @req DEM225 */ + *RecordNumber = priMemFreezeFrameBuffer[i].recordNumber; + *DTC = (DEM_DTC_FORMAT_UDS == ffRecordFilter.dtcFormat) ? + eventStatusRecPtr->eventParamRef->DTCClassRef->DTCRef->UDSDTC : TO_OBD_FORMAT(eventStatusRecPtr->eventParamRef->DTCClassRef->DTCRef->OBDDTC); + /* @req DEM226 */ + ffRecordFilter.ffIndex = i + 1; + found = TRUE; + ret = DEM_FILTERED_OK; + } + } + } +#endif + + SchM_Exit_Dem_EA_0(); + return ret; + /*lint -e{818} *RecordNumber and *DTC these pointers are updated under DEM_USE_PRIMARY_MEMORY_SUPPORT condition */ +} + +#endif + +#if 0//(DEM_ENABLE_CONDITION_SUPPORT == STD_ON) +/* @req DEM202 */ +Std_ReturnType Dem_SetEnableCondition(uint8 EnableConditionID, boolean ConditionFulfilled) +{ + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETENABLECONDITION_ID, DEM_E_UNINIT, E_NOT_OK); + //VALIDATE_RV((EnableConditionID < DEM_NUM_ENABLECONDITIONS), DEM_SETENABLECONDITION_ID, DEM_E_PARAM_DATA, E_NOT_OK); + + DemEnableConditions[EnableConditionID] = ConditionFulfilled; + + return E_OK; +} +#endif + +/* Function: Dem_GetSeverityOfDTC + * Description: Gets the severity of a DTC + */ + #if 0 +Dem_ReturnGetSeverityOfDTCType Dem_GetSeverityOfDTC(uint32 DTC, Dem_DTCSeverityType* DTCSeverity) +{ + /* NOTE: DTC is on UDS format according to DEM232 */ + Dem_ReturnGetSeverityOfDTCType ret = DEM_GET_SEVERITYOFDTC_WRONG_DTC; + boolean isDone = FALSE; + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETSEVERITYOFDTC_ID, DEM_E_UNINIT, DEM_GET_SEVERITYOFDTC_PENDING); + //VALIDATE_RV((NULL != DTCSeverity), DEM_GETSEVERITYOFDTC_ID, DEM_E_PARAM_POINTER, DEM_GET_SEVERITYOFDTC_PENDING); + + const Dem_DTCClassType *DTCPtr = configSet->DTCClass; + while( (DTCPtr->Arc_EOL==FALSE) && (isDone==FALSE) ) { + if( (DEM_NO_DTC != DTCPtr->DTCRef->UDSDTC) && (DTC == DTCPtr->DTCRef->UDSDTC) ) { + /* Dtc found */ + isDone = TRUE; + if( DTCIsAvailable(DTCPtr)==TRUE ) { + *DTCSeverity = DTCPtr->DTCSeverity; + if( DEM_SEVERITY_NO_SEVERITY == DTCPtr->DTCSeverity ) { + ret = DEM_GET_SEVERITYOFDTC_NOSEVERITY; + } else { + ret = DEM_GET_SEVERITYOFDTC_OK; + } + } + else { + /* @req 4.2.2/SWS_Dem_01100 */ + /* Ignore suppressed DTCs *//* @req DEM587 */ + ret = DEM_GET_SEVERITYOFDTC_WRONG_DTC; + } + } + DTCPtr++; + } + + return ret; +} + +#endif + +/* Function: Dem_DisableDTCRecordUpdate + * Description: Disables the event memory update of a specific DTC (only one at one time) + */ +Dem_ReturnDisableDTCRecordUpdateType Dem_DisableDTCRecordUpdate(uint32 DTC, Dem_DTCOriginType DTCOrigin) +{ + /* NOTE: DTC in in UDS format according to DEM233 */ + Dem_ReturnDisableDTCRecordUpdateType ret = DEM_DISABLE_DTCRECUP_WRONG_DTC; + + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_DISABLEDTCRECORDUPDATE_ID, DEM_E_UNINIT, DEM_DISABLE_DTCRECUP_PENDING); + + if(NO_DTC_DISABLED == DTCRecordDisabled.DTC) { + const Dem_EventParameterType *eventIdParamPtr = configSet->EventParameter; + while( (eventIdParamPtr->Arc_EOL==FALSE) && (DEM_DISABLE_DTCRECUP_OK != ret)) { + if( (NULL != eventIdParamPtr->DTCClassRef) && (eventHasDTCOnFormat(eventIdParamPtr, DEM_DTC_FORMAT_UDS)==TRUE) && + (eventIdParamPtr->DTCClassRef->DTCRef->UDSDTC == DTC) && (DTCIsAvailable(eventIdParamPtr->DTCClassRef)==TRUE)) { + /* Event references this DTC */ + ret = DEM_DISABLE_DTCRECUP_WRONG_DTCORIGIN; + if( eventIdParamPtr->EventClass->EventDestination == DTCOrigin ) { + /* Event destination match. Disable update for this DTC and the event destination */ + /* @req DEM270 */ + DTCRecordDisabled.DTC = DTC; + DTCRecordDisabled.Origin = DTCOrigin; + ret = DEM_DISABLE_DTCRECUP_OK; + } + } + eventIdParamPtr++; + } + } else if (DTCRecordDisabled.DTC != DTC) { + /* The previously disabled DTC has not been enabled */ + /* @req DEM648 *//* @req DEM518 */ + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_DISABLEDTCRECORDUPDATE_ID, DEM_E_WRONG_CONDITION); + ret = DEM_DISABLE_DTCRECUP_PENDING; + } else { + ret = DEM_DISABLE_DTCRECUP_OK; + } + + return ret; +} + +/* Function: Dem_EnableDTCRecordUpdate + * Description: Enables the event memory update of the DTC disabled by Dem_DisableDTCRecordUpdate() before. + */ +#if 0 +Std_ReturnType Dem_EnableDTCRecordUpdate(void) +{ + Std_ReturnType ret = E_NOT_OK; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_ENABLEDTCRECORDUPDATE_ID, DEM_E_UNINIT, E_NOT_OK); + + if(NO_DTC_DISABLED != DTCRecordDisabled.DTC) { + /* @req DEM271 */ + DTCRecordDisabled.DTC = NO_DTC_DISABLED; + ret = E_OK; + } else { + /* No DTC record update has been disabled */ + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_ENABLEDTCRECORDUPDATE_ID, DEM_E_SEQUENCE_ERROR); + } + + return ret; +} +#endif + +/** + * Gets the data of a freeze frame by event + * @param EventId + * @param RecordNumber + * @param ReportTotalRecord + * @param DataId + * @param DestBuffer + * @param BufSize + * @param CareAboutBufsize + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +static Std_ReturnType Dem_GetEventFreezeFrameData_Internal(Dem_EventIdType EventId, uint8 RecordNumber, boolean ReportTotalRecord, + uint16 DataId, uint8* DestBuffer, uint8* BufSize, boolean CareAboutBufsize) +{ + /* @req DEM478*/ + /* @req DEM479 */ + Std_ReturnType ret = E_NOT_OK; + const Dem_EventParameterType *eventIdParamPtr = NULL; + uint8 recordToReport = 0; + uint8 destBufferIndex = 0; + uint8 *ffRecordData; + EventStatusRecType * eventStatusRec = NULL; + Dem_FreezeFrameKindType ffKind = DEM_FREEZE_FRAME_NON_OBD; + if( DEM_INITIALIZED == demState ) { + lookupEventIdParameter(EventId, &eventIdParamPtr); + + lookupEventStatusRec(EventId, &eventStatusRec); + if( (NULL != eventIdParamPtr) && (NULL != eventStatusRec) && eventStatusRec->isAvailable) { + /* Event has freeze frames configured */ + if(getFFRecData(eventIdParamPtr, RecordNumber, &ffRecordData, &recordToReport, &ffKind)==TRUE) { + /* And the record we are looking for was found */ + const Dem_FreezeFrameClassType *freezeFrameClass = NULL; + const Dem_PidOrDidType * const *xidPtr; + if(DEM_FREEZE_FRAME_NON_OBD == ffKind ) { + freezeFrameClass = eventIdParamPtr->FreezeFrameClassRef; + xidPtr = freezeFrameClass->FFIdClassRef; + } else { + freezeFrameClass = configSet->GlobalOBDFreezeFrameClassRef; + xidPtr = freezeFrameClass->FFIdClassRef; + } + uint16 ffDataIndex = 0; + boolean done = FALSE; + while( ((*xidPtr)->Arc_EOL==FALSE) && (done==FALSE)) { + if(DEM_FREEZE_FRAME_NON_OBD == ffKind ) { + ffDataIndex += DEM_DID_IDENTIFIER_SIZE_OF_BYTES; + } else { + ffDataIndex += DEM_PID_IDENTIFIER_SIZE_OF_BYTES; + } + if( (ReportTotalRecord==TRUE) || + ((DEM_FREEZE_FRAME_NON_OBD == ffKind) && (DataId == (*xidPtr)->DidIdentifier)) || + ((DEM_FREEZE_FRAME_NON_OBD != ffKind) && (DataId == (*xidPtr)->PidIdentifier))) { + if(CareAboutBufsize==TRUE){ + if(((*xidPtr)->PidOrDidSize + destBufferIndex) > *BufSize){ + *BufSize = destBufferIndex; + return E_NOT_OK; /* buffer full, no info in DLT spec what to do for this case so we return operation failed */ + } + } + memcpy(&DestBuffer[destBufferIndex], &ffRecordData[ffDataIndex], (*xidPtr)->PidOrDidSize); + destBufferIndex += (*xidPtr)->PidOrDidSize; + done = (ReportTotalRecord==FALSE); + ret = E_OK; + } + ffDataIndex += (*xidPtr)->PidOrDidSize; + xidPtr++; + } + } + } + } else { + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEVENTFREEZEFRAMEDATA_ID, DEM_E_UNINIT); + } + + *BufSize = destBufferIndex; + return ret; +} + +/** + * Gets the data of a freeze frame by event + * @param EventId + * @param RecordNumber + * @param ReportTotalRecord + * @param DataId + * @param DestBuffer + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +Std_ReturnType Dem_GetEventFreezeFrameData(Dem_EventIdType EventId, uint8 RecordNumber, boolean ReportTotalRecord, uint16 DataId, uint8* DestBuffer) +{ + uint8 BufSize = 0x0; /* dummy size not used */ + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTFREEZEFRAMEDATA_ID, DEM_E_UNINIT, E_NOT_OK); + //VALIDATE_RV((NULL != DestBuffer), DEM_GETEVENTFREEZEFRAMEDATA_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + return Dem_GetEventFreezeFrameData_Internal(EventId,RecordNumber,ReportTotalRecord,DataId,DestBuffer, &BufSize, FALSE); +} + +#if (DEM_TRIGGER_DLT_REPORTS == STD_ON) +/** + * Gets the most recent data of a freeze frame by event for DLT + * @param EventId + * @param DestBuffer + * @param BufSize + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +Std_ReturnType Dem_DltGetMostRecentFreezeFrameRecordData(Dem_EventIdType EventId, uint8* DestBuffer, uint8* BufSize){ + /* @req DEM632 */ + /* @req DEM633 */ + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_DLTGETMOSTRECENTFREEZEFRAMERECORDDATA_ID, DEM_E_UNINIT, E_NOT_OK); + //VALIDATE_RV(((NULL != DestBuffer) && (NULL != BufSize)), DEM_DLTGETMOSTRECENTFREEZEFRAMERECORDDATA_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + return Dem_GetEventFreezeFrameData_Internal(EventId, MOST_RECENT_FF_RECORD, TRUE,0, DestBuffer, BufSize, TRUE); +} +#endif + + +/** + * Gets the data of an extended data record by event + * @param EventId + * @param RecordNumber + * @param DestBuffer + * @param BufSize + * @param CareAboutBufsize + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +#if 0 +static Std_ReturnType Dem_GetEventExtendedDataRecord_Internal(Dem_EventIdType EventId, uint8 RecordNumber, uint8* DestBuffer, uint8* BufSize, boolean CareAboutBufsize) +{ + /* @req DEM476 */ + /* @req DEM477 */ + Std_ReturnType ret = E_NOT_OK; + const Dem_EventParameterType *eventIdParamPtr = NULL; + Dem_ExtendedDataRecordClassType const *extendedDataRecordClass = NULL; + ExtDataRecType *extData; + uint16 posInExtData = 0; + uint16 extdataIndex = 0; + uint8 extendedDataNumber = RecordNumber; + boolean done = FALSE; + boolean readFailed = FALSE; + uint8 destBufferIndex = 0; + EventStatusRecType * eventStatusRec = NULL; + + if( DEM_INITIALIZED == demState ) { + if( IS_VALID_EXT_DATA_RECORD(RecordNumber) || (ALL_EXTENDED_DATA_RECORDS == RecordNumber) ) { + /* Record number ok */ + lookupEventIdParameter(EventId, &eventIdParamPtr); + lookupEventStatusRec(EventId, &eventStatusRec); + if( (NULL != eventIdParamPtr) && (NULL != eventIdParamPtr->ExtendedDataClassRef) && + (NULL != eventStatusRec) && eventStatusRec->isAvailable) { + /* Event ok and has extended data */ + ret = E_OK; + while( (done==FALSE) && (NULL != eventIdParamPtr->ExtendedDataClassRef->ExtendedDataRecordClassRef[extdataIndex])) { + readFailed = TRUE; + if( ALL_EXTENDED_DATA_RECORDS == RecordNumber) { + extendedDataNumber = eventIdParamPtr->ExtendedDataClassRef->ExtendedDataRecordClassRef[extdataIndex]->RecordNumber; + } else { + /* Should only read one specific record */ + done = TRUE; + } + if (lookupExtendedDataRecNumParam(extendedDataNumber, eventIdParamPtr, &extendedDataRecordClass, &posInExtData)==TRUE) { + if(CareAboutBufsize == TRUE){ + if((extendedDataRecordClass->DataSize + destBufferIndex) > *BufSize){ + *BufSize = destBufferIndex; + return E_NOT_OK; /* buffer full, no info in DLT spec what to do for this case so we return operation failed */ + } + } + if( extendedDataRecordClass->UpdateRule != DEM_UPDATE_RECORD_VOLATILE ) { + if (lookupExtendedDataMem(EventId, &extData, eventIdParamPtr->EventClass->EventDestination) ==TRUE ) { + // Yes all conditions met, copy the extended data record to destination buffer. + memcpy(&DestBuffer[destBufferIndex], &extData->data[posInExtData], extendedDataRecordClass->DataSize); /** @req DEM075 */ + destBufferIndex = (uint8)(destBufferIndex + extendedDataRecordClass->DataSize); + readFailed = FALSE; + } + } else { + if( NULL != extendedDataRecordClass->CallbackGetExtDataRecord ) { + if(E_OK == extendedDataRecordClass->CallbackGetExtDataRecord(&DestBuffer[destBufferIndex])) { + readFailed = FALSE; + } + destBufferIndex = (uint8)(destBufferIndex + extendedDataRecordClass->DataSize); + } else if (DEM_NO_ELEMENT != extendedDataRecordClass->InternalDataElement ) { + getInternalElement(eventIdParamPtr, extendedDataRecordClass->InternalDataElement, &DestBuffer[destBufferIndex], extendedDataRecordClass->DataSize ); + destBufferIndex = (uint8)(destBufferIndex +extendedDataRecordClass->DataSize); + readFailed = FALSE; + } else { + /* No callback and no internal element. + * IMPROVMENT: Det_error */ + } + } + } + if( readFailed ==TRUE) { + /* Something failed reading the data */ + done = TRUE; + ret = E_NOT_OK; + } + extdataIndex++; + } + } + } + } else { + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEVENTEXTENDEDDATARECORD_ID, DEM_E_UNINIT); + } + + *BufSize = destBufferIndex; + return ret; +} +#endif +/** + * Gets the data of an extended data record by event + * @param EventId + * @param RecordNumber + * @param DestBuffer + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +#if 0 +Std_ReturnType Dem_GetEventExtendedDataRecord(Dem_EventIdType EventId, uint8 RecordNumber, uint8* DestBuffer) +{ + uint8 Bufsize = 0; /* Dummy size not used */ + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTEXTENDEDDATARECORD_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV((NULL != DestBuffer), DEM_GETEVENTEXTENDEDDATARECORD_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + return Dem_GetEventExtendedDataRecord_Internal(EventId, RecordNumber, DestBuffer, &Bufsize, FALSE); +} +#endif +#if (DEM_TRIGGER_DLT_REPORTS == STD_ON) +/** + * Gets all the data of an extended data record by event for DLT + * @param EventId + * @param DestBuffer + * @param BufSize + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed + */ +Std_ReturnType Dem_DltGetAllExtendedDataRecords(Dem_EventIdType EventId, uint8* DestBuffer, uint8* BufSize){ + /* @req DEM634 */ + /* @req DEM635 */ + //VALIDATE_RV(DEM_INITIALIZED == demState, DEM_DLTGETALLEXTENDEDDATARECORDS_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV(((NULL != DestBuffer) && (NULL != BufSize)), DEM_DLTGETALLEXTENDEDDATARECORDS_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + return Dem_GetEventExtendedDataRecord_Internal(EventId, ALL_EXTENDED_DATA_RECORDS, DestBuffer, BufSize, TRUE); +} +#endif + +#if defined(DEM_ENABLE_PRESTORED_FF_RETURNING_NOT_OK) || defined(USE_RTE) +/** + * Captures the freeze frame data for a specific event. + * @param EventId + * @return E_OK: Freeze frame prestorage was successful, E_NOT_OK: Freeze frame prestorage failed + */ +/* !req DEM188 */ +Std_ReturnType Dem_PrestoreFreezeFrame(Dem_EventIdType EventId) +{ + /* IMPROVEMENT: Add support for pre-storing freeze frames */ + (void)EventId; + return E_NOT_OK; +} + +/** + * Clears a prestored freeze frame of a specific event. + * @param EventId + * @return E_OK: Clear prestored freeze frame was successful, E_NOT_OK: Clear prestored freeze frame failed + */ +/* !req DEM193 */ +Std_ReturnType Dem_ClearPrestoredFreezeFrame(Dem_EventIdType EventId) +{ + /* IMPROVEMENT: Add support for pre-storing freeze frames */ + (void)EventId; + return E_NOT_OK; +} +#endif + +/** + * Gets the event memory overflow indication status + * @param DTCOrigin + * @param OverflowIndication + * @return E_OK: Operation was successful, E_NOT_OK: Operation failed or is not supported + */ +/* @req DEM559 *//* @req DEM398 */ +Std_ReturnType Dem_GetEventMemoryOverflow(Dem_DTCOriginType DTCOrigin, boolean *OverflowIndication) +{ +// VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETEVENTMEMORYOVERFLOW_ID, DEM_E_UNINIT, E_NOT_OK) + // VALIDATE_RV(NULL != OverflowIndication, DEM_GETEVENTMEMORYOVERFLOW_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + return getOverflowIndication(DTCOrigin, OverflowIndication); +} + +#if (DEM_UNIT_TEST == STD_ON) +#if ( DEM_FF_DATA_IN_PRE_INIT ) +void getFFDataPreInit(FreezeFrameRecType **buf); +void getFFDataPreInit(FreezeFrameRecType **buf) +{ + *buf = &preInitFreezeFrameBuffer[0]; + return; +} +#endif +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) +uint32 getCurTimeStamp(void) +{ + return FF_TimeStamp; +} +#endif +void getEventStatusBufPtr(EventStatusRecType **buf); +void getEventStatusBufPtr(EventStatusRecType **buf) +{ + *buf = &eventStatusBuffer[0]; + return; +} +#endif /* DEM_UNIT_TEST */ + + + + + +/**************** + * OBD-specific * + ***************/ +/* + * Procedure: Dem_GetDTCOfOBDFreezeFrame + * Reentrant: No + */ + /* @req OBD_DEM_REQ_3 */ +Std_ReturnType Dem_GetDTCOfOBDFreezeFrame(uint8 FrameNumber, uint32* DTC ) +{ + /* @req DEM623 */ + const FreezeFrameRecType *freezeFrame = NULL; + const Dem_EventParameterType *eventParameter = NULL; + Std_ReturnType returnCode = E_NOT_OK; + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_GETDTCOFOBDFREEZEFRAME_ID, DEM_E_UNINIT, E_NOT_OK); + //VALIDATE_RV(NULL != DTC, DEM_GETDTCOFOBDFREEZEFRAME_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + //VALIDATE_RV(0 == FrameNumber, DEM_GETDTCOFOBDFREEZEFRAME_ID, DEM_E_PARAM_DATA, E_NOT_OK); + + /* find the corresponding FF in FF buffer */ + /* @req OBD_DEM_REQ_1 */ +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + for(uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++){ + if((priMemFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL) + && (DEM_FREEZE_FRAME_OBD == priMemFreezeFrameBuffer[i].kind)){ + freezeFrame = &priMemFreezeFrameBuffer[i]; + break; + } + } +#endif + /*if FF found,find the corresponding eventParameter*/ + if( freezeFrame != NULL ) { + lookupEventIdParameter(freezeFrame->eventId, &eventParameter); + if(eventParameter != NULL){ + /* if DTCClass configured,get DTC value */ + if((eventParameter->DTCClassRef != NULL) && (DTCIsAvailable(eventParameter->DTCClassRef)==TRUE) && (eventHasDTCOnFormat(eventParameter, DEM_DTC_FORMAT_OBD)==TRUE)){ + *DTC = TO_OBD_FORMAT(eventParameter->DTCClassRef->DTCRef->OBDDTC); + returnCode = E_OK; + } + else { + /* Event has no DTC or DTC is suppressed */ + /* @req 4.2.2/SWS_Dem_01101 *//* @req DEM587 */ + } + } + + } + + return returnCode; + +} + +/* + * Procedure: Dem_ReadDataOfOBDFreezeFrame + * Reentrant: No + */ + /* @req OBD_DEM_REQ_2 */ +/*lint -efunc(818,Dem_ReadDataOfOBDFreezeFrame) Pointers cannot be declared as pointing to const as API defined by AUTOSAR */ +Std_ReturnType Dem_ReadDataOfOBDFreezeFrame(uint8 PID, uint8 DataElementIndexOfPid, uint8* DestBuffer, uint8* BufSize) +{ + /* IMPROVEMENT: Validate parameters */ + /* @req DEM596 */ + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_READDATAOFOBDFREEZEFRAME_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV(NULL != DestBuffer, DEM_READDATAOFOBDFREEZEFRAME_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + // VALIDATE_RV(NULL != BufSize, DEM_READDATAOFOBDFREEZEFRAME_ID, DEM_E_PARAM_POINTER, E_NOT_OK); + Std_ReturnType returnCode = E_NOT_OK; + + /* IMPROVEMENT: DataElementIndexOfPid should be used to get the data of the Pid. But we only support 1 data element + * per Pid.. */ + (void)DataElementIndexOfPid; + +#if (DEM_MAX_NR_OF_PIDS_IN_FREEZEFRAME_DATA > 0) + const FreezeFrameRecType *freezeFrame = NULL; + const Dem_FreezeFrameClassType *freezeFrameClass; + boolean pidFound = FALSE; + uint16 offset = 0; + uint8 pidDataSize = 0; + SchM_Enter_Dem_EA_0(); + freezeFrameClass = configSet->GlobalOBDFreezeFrameClassRef; +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + /*find the corresponding FF in FF buffer*/ + for(uint16 i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++) { + /* @req OBD_DEM_REQ_1 */ + if((priMemFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL) + && (DEM_FREEZE_FRAME_OBD == priMemFreezeFrameBuffer[i].kind)) { + freezeFrame = &priMemFreezeFrameBuffer[i]; + break; + } + } +#endif + /*if FF class found,find the corresponding PID*/ + if(NULL != freezeFrame) { + if(freezeFrameClass->FFKind == DEM_FREEZE_FRAME_OBD) { + if(freezeFrameClass->FFIdClassRef != NULL){ + for(uint16 i = 0; (i < DEM_MAX_NR_OF_PIDS_IN_FREEZEFRAME_DATA) && ((freezeFrameClass->FFIdClassRef[i]->Arc_EOL) == FALSE); i++) { + offset += DEM_PID_IDENTIFIER_SIZE_OF_BYTES; + if(freezeFrameClass->FFIdClassRef[i]->PidIdentifier == PID){ + pidDataSize = freezeFrameClass->FFIdClassRef[i]->PidOrDidSize; + pidFound = TRUE; + break; + } else{ + offset += freezeFrameClass->FFIdClassRef[i]->PidOrDidSize; + } + } + } + } + } + + if( pidFound && (NULL != freezeFrame) && (offset >= DEM_PID_IDENTIFIER_SIZE_OF_BYTES) ) { + if(((*BufSize) >= pidDataSize) && (PID == (freezeFrame->data[offset - DEM_PID_IDENTIFIER_SIZE_OF_BYTES])) + && ((offset + pidDataSize) <= (freezeFrame->dataSize)) && ((offset + pidDataSize) <= DEM_MAX_SIZE_FF_DATA)) { + memcpy(DestBuffer, &freezeFrame->data[offset], pidDataSize); + *BufSize = pidDataSize; + returnCode = E_OK; + } + } + SchM_Exit_Dem_EA_0(); +#else + (void)PID; +#endif + + return returnCode; +} + +/* + * Procedure: storeOBDFreezeFrameDataMem + * Description: store OBD FreezeFrame data record in primary memory + */ +#ifdef DEM_USE_MEMORY_FUNCTIONS +#if ( DEM_FF_DATA_IN_PRE_INIT || DEM_FF_DATA_IN_PRI_MEM ) +static boolean storeOBDFreezeFrameDataMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame, + FreezeFrameRecType* freezeFrameBuffer, uint32 freezeFrameBufferSize, + Dem_DTCOriginType origin) +{ + boolean eventIdFound = FALSE; + boolean eventIdFreePositionFound = FALSE; + uint16 i; + boolean dataStored = FALSE; + (void)origin; + + /* Check if already stored */ + for (i = 0; (iEventClass->EventDestination, TRUE); + } + } +#else + setOverflowIndication(eventParam->EventClass->EventDestination, TRUE); + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_FF_DATA_MEM_ID, DEM_E_MEM_FF_DATA_BUFF_FULL); +#endif + } + } else { + /* OBD freeze frame was already stored. Check if we should replace it. + * We replace it if the new event has higher priority. */ + const Dem_EventParameterType *storedEventParam = NULL; + boolean replaceOBDFF = TRUE; + lookupEventIdParameter(freezeFrameBuffer[i-1].eventId, &storedEventParam); + if( NULL != storedEventParam ) { + if( storedEventParam->EventClass->EventPriority <= eventParam->EventClass->EventPriority ) { + /* Priority of the new event is lower or equal to the stored event. + * Should NOT replace the FF. */ + replaceOBDFF = FALSE; + } + } + if( replaceOBDFF ) { + memcpy(&freezeFrameBuffer[i-1], freezeFrame, sizeof(FreezeFrameRecType)); + dataStored = TRUE; + } + } + return dataStored; +} +#endif +#endif + +#if defined(USE_RTE) +Std_ReturnType Dem_SetEventDisabled(Dem_EventIdType EventId ) +{ + (void)EventId; + return E_NOT_OK; +} +#endif + +/** + * Set the suppression status of a specific DTC. + * @param DTC + * @param DTCFormat + * @param SuppressionStatus + * @return E_OK (Operation was successful), E_NOT_OK (operation failed or event entry for this DTC still exists) + */ +/* @req DEM589 */ +/* @req 4.2.2/SWS_Dem_01047 */ +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) +/* @req 4.2.2/SWS_Dem_00586 */ +Std_ReturnType Dem_SetDTCSuppression(uint32 DTC, Dem_DTCFormatType DTCFormat, boolean SuppressionStatus) +{ + /* Requirement tag intentionally incorrect. Handled in DEM.py */ + /* !req DEM588 Allowing suppression of DTC even if event memory entry exists (this requirement is removed in ASR 4.2.2) */ + Std_ReturnType ret = E_NOT_OK; +// VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETDTCSUPPRESSION_ID, DEM_E_UNINIT, E_NOT_OK); + // VALIDATE_RV(IS_VALID_DTC_FORMAT(DTCFormat), DEM_SETDTCSUPPRESSION_ID, DEM_E_PARAM_DATA, E_NOT_OK); + const Dem_DTCClassType *DTCClassPtr = configSet->DTCClass; + while( !DTCClassPtr->Arc_EOL ) { + if( ((DEM_DTC_FORMAT_UDS == DTCFormat) && (DTCClassPtr->DTCRef->UDSDTC == DTC)) || + ((DEM_DTC_FORMAT_OBD == DTCFormat) && (TO_OBD_FORMAT(DTCClassPtr->DTCRef->OBDDTC) == DTC))) { + DemDTCSuppressed[DTCClassPtr->DTCIndex].SuppressedByDTC = SuppressionStatus; + ret = E_OK; + break; + } + DTCClassPtr++; + } + return ret; +} +#endif + +#if 0//defined(DEM_USE_MEMORY_FUNCTIONS) +/** + * Check if an event is stored in freeze frame buffer + * @param eventId + * @param dtcOrigin + * @return TRUE: Event stored in FF buffer, FALSE: Event NOT stored in FF buffer + */ +static boolean isInFFBuffer(Dem_EventIdType eventId, Dem_DTCOriginType dtcOrigin) +{ + boolean ffFound = FALSE; + + FreezeFrameRecType* freezeFrameBuffer = NULL; + uint32 freezeFrameBufferSize = 0; + + switch (dtcOrigin) { + case DEM_DTC_ORIGIN_PRIMARY_MEMORY: +#if ((DEM_USE_PRIMARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_PRI_MEM) + freezeFrameBuffer = priMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_PRI_MEM; +#endif + break; + case DEM_DTC_ORIGIN_SECONDARY_MEMORY: +#if ((DEM_USE_SECONDARY_MEMORY_SUPPORT == STD_ON) && DEM_FF_DATA_IN_SEC_MEM) + freezeFrameBuffer = secMemFreezeFrameBuffer; + freezeFrameBufferSize = DEM_MAX_NUMBER_FF_DATA_SEC_MEM; +#endif + break; + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + } + + if (freezeFrameBuffer != NULL) { + + for (uint16 i = 0; (i < freezeFrameBufferSize) && (!ffFound); i++) { + ffFound = (freezeFrameBuffer[i].eventId == eventId); + } + } + return ffFound; +} +#endif + +#endif //W +/** + * Checks if event is stored in event memory + * @param EventId + * @return TRUE: Event stored in memory, FALSE: event NOT stored in memory + */ + +static boolean EventIsStoredInMemory(Dem_EventIdType EventId) +{ +#if defined(DEM_USE_MEMORY_FUNCTIONS) + // const Dem_EventParameterType *eventParam; + // ExtDataRecType *extData; + // boolean isStored = FALSE; + + // lookupEventIdParameter(EventId, &eventParam); + // if( (NULL != eventParam) && (DEM_DTC_ORIGIN_NOT_USED != eventParam->EventClass->EventDestination) ) { + // isStored = (isInEventMemory(eventParam)) || isInFFBuffer(EventId, eventParam->EventClass->EventDestination) || lookupExtendedDataMem(EventId, &extData, eventParam->EventClass->EventDestination); + //} + //return isStored; +#else + (void)EventId; + return FALSE; +#endif +return FALSE; +} + + +/** + * Set the available status of a specific Event. + * @param EventId: Identification of an event by assigned EventId. + * @param AvailableStatus: This parameter specifies whether the respective Event shall be available (TRUE) or not (FALSE). + * @return: E_OK: Operation was successful, E_NOT_OK: change of available status not accepted + */ +/* @req 4.2.2/SWS_Dem_01080 */ +#if 1 +Std_ReturnType Dem_SetEventAvailable(Dem_EventIdType EventId, boolean AvailableStatus) +{ +#if (DEM_SET_EVENT_AVAILABLE_PREINIT == STD_ON) + // VALIDATE_RV(DEM_UNINITIALIZED != demState, DEM_SETEVENTAVAILABLE_ID, DEM_E_UNINIT, E_NOT_OK); +#else + // VALIDATE_RV(DEM_INITIALIZED == demState, DEM_SETEVENTAVAILABLE_ID, DEM_E_UNINIT, E_NOT_OK); +#endif + // VALIDATE_RV(IS_VALID_EVENT_ID(EventId), DEM_SETEVENTAVAILABLE_ID, DEM_E_PARAM_DATA, E_NOT_OK); + + const Dem_EventParameterType *eventParam = NULL; + Dem_EventStatusExtendedType oldStatus; + EventStatusRecType *eventStatusRec = NULL; + Std_ReturnType ret = E_NOT_OK; + + if ( (demState == DEM_UNINITIALIZED) +#if (DEM_SET_EVENT_AVAILABLE_PREINIT == STD_OFF) + || (demState == DEM_PREINITIALIZED) +#endif + ) { + return E_NOT_OK; + } + + // SchM_Enter_Dem_EA_0(); + + lookupEventStatusRec(EventId, &eventStatusRec); + lookupEventIdParameter(EventId, &eventParam); + /* @req 4.2.2/SWS_Dem_01109 */ + if( (NULL != eventStatusRec) && (NULL != eventParam) && (*eventParam->EventClass->EventAvailableByCalibration == TRUE) && + (0u == (eventStatusRec->eventStatusExtended & DEM_TEST_FAILED)) && ((DEM_PREINITIALIZED == demState) || !EventIsStoredInMemory(EventId)) ) { + if( eventStatusRec->isAvailable != AvailableStatus ) { + /* Event availability changed */ + eventStatusRec->isAvailable = AvailableStatus; + oldStatus = eventStatusRec->eventStatusExtended; + if( !AvailableStatus ) { + /* @req 4.2.2/SWS_Dem_01110 */ + eventStatusRec->eventStatusExtended = 0x00; + } else { + /* @req 4.2.2/SWS_Dem_01111 */ + eventStatusRec->eventStatusExtended = 0x50; + } + + if( oldStatus != eventStatusRec->eventStatusExtended ) { + notifyEventStatusChange(eventParam, oldStatus, eventStatusRec->eventStatusExtended); + } +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) + /* Check if suppression of DTC is affected */ + boolean suppressed = TRUE; + EventStatusRecType *dtcEventStatusRec; + if( (NULL != eventParam->DTCClassRef) && (NULL != eventParam->DTCClassRef->Events) ) { + for( uint16 i = 0; (i < eventParam->DTCClassRef->NofEvents) && suppressed; i++ ) { + dtcEventStatusRec = NULL; + lookupEventStatusRec(eventParam->DTCClassRef->Events[i], &dtcEventStatusRec); + if( (NULL != dtcEventStatusRec) && dtcEventStatusRec->isAvailable ) { + /* Event is available -> DTC NOT suppressed */ + suppressed = FALSE; + } + } + if( 0 != eventParam->DTCClassRef->NofEvents ) { + DemDTCSuppressed[eventParam->DTCClassRef->DTCIndex].SuppressedByEvent = suppressed; + } + } +#endif + } + ret = E_OK; + } + //SchM_Exit_Dem_EA_0(); + return ret; +} +#endif + + diff --git a/firmware/src/DiagnosticR/Dem/Dem.h b/firmware/src/DiagnosticR/Dem/Dem.h new file mode 100644 index 0000000..0a25c51 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem.h @@ -0,0 +1,240 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + + + + + + + + +#ifndef DEM_H_ +#define DEM_H_ + +//#include "Modules.h" +/* @req DEM628 */ +#define DEM_MODULE_ID MODULE_ID_DEM +#define DEM_VENDOR_ID VENDOR_ID_ARCCORE + +#define DEM_AR_RELEASE_MAJOR_VERSION 4u +#define DEM_AR_RELEASE_MINOR_VERSION 0u +#define DEM_AR_RELEASE_REVISION_VERSION 3u + +#define DEM_SW_MAJOR_VERSION 5u +#define DEM_SW_MINOR_VERSION 14u +#define DEM_SW_PATCH_VERSION 0u +#define DEM_AR_MAJOR_VERSION DEM_AR_RELEASE_MAJOR_VERSION +#define DEM_AR_MINOR_VERSION DEM_AR_RELEASE_MINOR_VERSION +#define DEM_AR_PATCH_VERSION DEM_AR_RELEASE_REVISION_VERSION + +#include "Dem_Types.h" +#include "DiagnosticR/Dem/Dem_Cfg.h" +#include "DiagnosticR/Dem/Dem_Lcfg.h" +#include "DiagnosticR/Dem/Dem_IntErrId.h" /** @req DEM115 */ +#include "DiagnosticR/Dem/Dem_IntEvtId.h" +#include "DiagnosticR/rte/Rte_Dem_Type.h" +//#include "Dem_EnableCondId.h" +#include +/** @req DEM153 */ /** @req DEM154 */ /* Realized in Dem_IntErrId.h and Dem_IntEvtId.h */ +// #include "Rte_Dem.h" + + +#if (DEM_DEV_ERROR_DETECT == STD_ON) +// Error codes reported by this module defined by AUTOSAR /** @req DEM116 */ /** @req DEM173 */ +#define DEM_E_PARAM_CONFIG 0x10u +#define DEM_E_PARAM_POINTER 0x11u +#define DEM_E_PARAM_DATA 0x12u +#define DEM_E_PARAM_LENGTH 0x13u +#define DEM_E_UNINIT 0x20u +#define DEM_E_NODATAAVAILABLE 0x30u +#define DEM_E_WRONG_CONDITION 0x40u +// Other error codes reported by this module +#define DEM_E_CONFIG_PTR_INVALID 0x50u +#define DEM_E_EXT_DATA_TOO_BIG 0x52u +#define DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL 0x53u +#define DEM_E_MEM_EVENT_BUFF_FULL 0x54u +#define DEM_E_MEM_EXT_DATA_BUFF_FULL 0x55u +#define DEM_E_FF_TOO_BIG 0x56u +#define DEM_E_PRE_INIT_FF_DATA_BUFF_FULL 0x57u +#define DEM_E_MEM_FF_DATA_BUFF_FULL 0x58u +#define DEM_E_OBD_NOT_ALLOWED_IN_SEC_MEM 0x59u +#define DEM_E_MEMORY_CORRUPT 0x5Au + + + +#define DEM_E_SEQUENCE_ERROR 0xfdu +#define DEM_E_UNEXPECTED_EXECUTION 0xfeu +#define DEM_E_NOT_IMPLEMENTED_YET 0xffu + + +// Service ID in this module +#define DEM_PREINIT_ID 0x01u +#define DEM_INIT_ID 0x02u +#define DEM_SHUTDOWN_ID 0x03u +#define DEM_SETEVENTSTATUS_ID 0x04u +#define DEM_RESETEVENTSTATUS_ID 0x05u +#define DEM_SETOPERATIONCYCLESTATE_ID 0x08u +#define DEM_GETEVENTSTATUS_ID 0x0Au +#define DEM_GETEVENTFAILED_ID 0x0Bu +#define DEM_GETEVENTTESTED_ID 0x0Cu +#define DEM_GETDTCOFEVENT_ID 0x0Du +#define DEM_GETSEVERITYOFDTC_ID 0x0Eu +#define DEM_REPORTERRORSTATUS_ID 0x0Fu +#define DEM_SETDTCFILTER_ID 0x13u +#define DEM_GETSTATUSOFDTC_ID 0x15u +#define DEM_GETDTCSTATUSAVAILABILITYMASK_ID 0x16u +#define DEM_GETNUMBEROFFILTEREDDTC_ID 0x17u +#define DEM_GETNEXTFILTEREDDTC_ID 0x18u +#define DEM_DISABLEDTCRECORDUPDATE_ID 0x1Au +#define DEM_ENABLEDTCRECORDUPDATE_ID 0x1Bu +#define DEM_GETFREEZEFRAMEDATABYDTC_ID 0x1Du +#define DEM_GETSIZEOFFREEZEFRAMEBYDTC_ID 0x1Fu +#define DEM_GETEXTENDEDDATARECORDBYDTC_ID 0x20u +#define DEM_GETSIZEOFEXTENDEDDATARECORDBYDTC_ID 0x21u +#define DEM_CLEARDTC_ID 0x22u +#define DEM_DISABLEDTCSETTING_ID 0x24u +#define DEM_ENABLEDTCSETTING_ID 0x25u + +#define DEM_GETINDICATORSTATUS_ID 0x29u + +#define DEM_GETEVENTEXTENDEDDATARECORD_ID 0x30u +#define DEM_GETEVENTFREEZEFRAMEDATA_ID 0x31u + +#define DEM_GETEVENTMEMORYOVERFLOW_ID 0x32u +#define DEM_SETDTCSUPPRESSION_ID 0x33u +#define DEM_SETEVENTAVAILABLE_ID 0x37u /* ASR 4.2.2 API */ +#define DEM_GETNEXTFILTEREDRECORD_ID 0x3au + +#define DEM_GETTRANSLATIONTYPE_ID 0x3cu +#define DEM_SETENABLECONDITION_ID 0x39u +#define DEM_GETFAULTDETECTIONCOUNTER_ID 0x3Eu +#define DEM_SETFREEZEFRAMERECORDFILTER_ID 0x3Fu +#define DEM_DLTGETALLEXTENDEDDATARECORDS_ID 0x40u +#define DEM_DLTGETMOSTRECENTFREEZEFRAMERECORDDATA_ID 0x41u +#define DEM_READDATAOFOBDFREEZEFRAME_ID 0X52u +#define DEM_GETDTCOFOBDFREEZEFRAME_ID 0x53u +#define DEM_MAINFUNCTION_ID 0x55u + +#define DEM_UPDATE_EVENT_STATUS_ID 0x80u +#define DEM_MERGE_EVENT_STATUS_ID 0x81u +#define DEM_GET_EXTENDED_DATA_ID 0x82u +#define DEM_STORE_EXT_DATA_PRE_INIT_ID 0x83u +#define DEM_STORE_EVENT_MEM_ID 0x84u +#define DEM_STORE_EXT_DATA_MEM_ID 0x85u +#define DEM_PREDEBOUNCE_NONE_ID 0x86u +#define DEM_PREDEBOUNCE_COUNTER_BASED_ID 0x87u +#define DEM_GET_FREEZEFRAME_ID 0x88u +#define DEM_STORE_FF_DATA_PRE_INIT_ID 0x89u +#define DEM_STORE_FF_DATA_MEM_ID 0x90u + +#define DEM_DSP_DID_USE_PORT_IS_TRUE 0x91u +#define DEM_READ_DATA_LENGTH_FAILED 0x92u + +#define DEM_GLOBAL_ID 0xffu + +#endif + +#define DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT UINT32_MAX //when timestamp up to the max value,rearrangement starts. +#define DEM_MAX_TIMESTAMP_FOR_PRE_INIT (uint32)(UINT32_MAX/2) +/* + * Interface for upper layer modules + */ +#if ( DEM_VERSION_INFO_API == STD_ON ) /** @req DEM111 */ +#define Dem_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DEM) /** @req DEM177 */ /** @req DEM110 */ +#endif /* DEM_VERSION_INFO_API */ + +/* + * Interface ECU State Manager <-> DEM + */ +void Dem_PreInit( const Dem_ConfigType *ConfigPtr ); /** @req DEM179 */ +void Dem_Init( void ); /** @req DEM181 */ +void Dem_Shutdown( void ); /** @req DEM182 */ + + +/* + * Interface for basic software scheduler + */ +void Dem_MainFunction( void ); /** @req DEM266 */ + + +/* + * Interface BSW modules/SW-Components via RTE <-> DEM + */ +void Dem_ReportErrorStatus(Dem_EventIdType eventId ,Dem_EventStatusType eventStatus); /** @req DEM206 */ +#if !defined(USE_RTE) +Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, Dem_EventStatusType eventStatus); +Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId); +#endif +Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState); /** @req DEM194 */ +Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended); /** @req DEM195 */ +Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed); /** @req DEM196 */ +Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested); /** @req DEM197 */ +Std_ReturnType Dem_GetDTCOfEvent(Dem_EventIdType eventId, Dem_DTCFormatType dtcFormat, uint32* dtcOfEvent); /** @req DEM198 */ +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) +Std_ReturnType Dem_SetEnableCondition(uint8 EnableConditionID, boolean ConditionFulfilled); /** @req DEM201*/ +#endif +Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter); /** @req DEM203 */ +Std_ReturnType Dem_GetIndicatorStatus( uint8 IndicatorId, Dem_IndicatorStatusType* IndicatorStatus ); /* @req DEM205 */ +Std_ReturnType Dem_GetEventFreezeFrameData(Dem_EventIdType EventId, uint8 RecordNumber, boolean ReportTotalRecord, uint16 DataId, uint8* DestBuffer);/* @req DEM558 */ +Std_ReturnType Dem_GetEventExtendedDataRecord(Dem_EventIdType EventId, uint8 RecordNumber, uint8* DestBuffer);/* @req DEM557 */ +Std_ReturnType Dem_GetEventMemoryOverflow(Dem_DTCOriginType DTCOrigin, boolean *OverflowIndication); /* @req DEM559 */ + +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) +Std_ReturnType Dem_SetDTCSuppression(uint32 DTC, Dem_DTCFormatType DTCFormat, boolean SuppressionStatus);/* @req 4.2.2/SWS_Dem_01047 *//* @req DEM583 */ +#endif +Std_ReturnType Dem_SetEventAvailable(Dem_EventIdType EventId, boolean AvailableStatus);/* @req 4.2.2/SWS_Dem_01080 */ +/* + * Interface DCM <-> DEM + */ +/* Access DTCs and status information */ +Dem_ReturnSetFilterType Dem_SetDTCFilter(uint8 dtcStatusMask, Dem_DTCKindType dtcKind, Dem_DTCFormatType dtcFormat, Dem_DTCOriginType dtcOrigin, Dem_FilterWithSeverityType filterWithSeverity, Dem_DTCSeverityType dtcSeverityMask, Dem_FilterForFDCType filterForFaultDetectionCounter); /** @req DEM208 */ +Dem_ReturnSetFilterType Dem_SetFreezeFrameRecordFilter(Dem_DTCFormatType dtcFormat, uint16 *NumberOfFilteredRecords);/* @req DEM209 */ +Dem_ReturnGetStatusOfDTCType Dem_GetStatusOfDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, Dem_EventStatusExtendedType* status); /** @req DEM212 */ +Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask); /** @req DEM213 */ +Dem_ReturnGetNumberOfFilteredDTCType Dem_GetNumberOfFilteredDtc(uint16* numberOfFilteredDTC); /** @req DEM214 */ +Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredDTC(uint32* dtc, Dem_EventStatusExtendedType* dtcStatus); /** @req DEM215 */ +Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredRecord(uint32 *DTC, uint8 *RecordNumber); /* @req DEM224 */ +Dem_DTCTranslationFormatType Dem_GetTranslationType(void); /** @req DEM230 */ +Dem_ReturnGetSeverityOfDTCType Dem_GetSeverityOfDTC(uint32 DTC, Dem_DTCSeverityType* DTCSeverity);/** @req DEM232 */ + +/* Access extended data records and FreezeFrame data */ +Dem_ReturnDisableDTCRecordUpdateType Dem_DisableDTCRecordUpdate(uint32 DTC, Dem_DTCOriginType DTCOrigin);/* @req DEM233 */ +Std_ReturnType Dem_EnableDTCRecordUpdate(void);/* @req DEM234 */ +Dem_ReturnGetFreezeFrameDataByDTCType Dem_GetFreezeFrameDataByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin,uint8 recordNumber, uint8* destBuffer, uint16* bufSize);/** @req DEM236 */ +Dem_ReturnGetSizeOfFreezeFrameType Dem_GetSizeOfFreezeFrameByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 recordNumber, uint16* sizeOfFreezeFrame);/** @req DEM238 */ +Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint16 *bufSize); /** @req DEM239 */ +Dem_ReturnGetSizeOfExtendedDataRecordByDTCType Dem_GetSizeOfExtendedDataRecordByDTC(uint32 dtc, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint16 *sizeOfExtendedDataRecord); /** @req DEM240 */ + +/* DTC storage */ +#if !defined(USE_RTE) +Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCFormatType dtcFormat, Dem_DTCOriginType dtcOrigin); /** @req DEM241 */ +#endif +Dem_ReturnControlDTCStorageType Dem_DisableDTCSetting(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind); /** @req DEM242 */ +Dem_ReturnControlDTCStorageType Dem_EnableDTCSetting(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind); /** @req DEM243 */ + +/* + * OBD-specific Interfaces + */ +Std_ReturnType Dem_ReadDataOfOBDFreezeFrame(uint8 PID, uint8 DataElementIndexOfPid, uint8* DestBuffer, uint8* BufSize);/* @req DEM327 */ +Std_ReturnType Dem_GetDTCOfOBDFreezeFrame(uint8 FrameNumber, uint32* DTC );/* @req DEM624 */ + +/* + * Interface DLT <-> DEM + */ +#if (DEM_TRIGGER_DLT_REPORTS == STD_ON) +Std_ReturnType Dem_DltGetAllExtendedDataRecords(Dem_EventIdType EventId, uint8* DestBuffer, uint8* BufSize); /** @req DEM637 */ +Std_ReturnType Dem_DltGetMostRecentFreezeFrameRecordData(Dem_EventIdType EventId, uint8* DestBuffer, uint8* BufSize);/** @req DEM636 */ +#endif + +#endif /*DEM_H_*/ diff --git a/firmware/src/DiagnosticR/Dem/Dem.mod.mk b/firmware/src/DiagnosticR/Dem/Dem.mod.mk new file mode 100644 index 0000000..a62a632 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem.mod.mk @@ -0,0 +1,9 @@ +#Dem +obj-$(USE_DEM) += Dem.o +ifeq ($(filter Dem_Extension.o,$(obj-y)),) +obj-$(USE_DEM_EXTENSION) += Dem_Extension.o +endif +obj-$(USE_DEM) += Dem_Debounce.o +obj-$(USE_DEM) += Dem_LCfg.o +inc-$(USE_DEM) += $(ROOTDIR)/diagnostic/Dem +vpath-$(USE_DEM) += $(ROOTDIR)/diagnostic/Dem \ No newline at end of file diff --git a/firmware/src/DiagnosticR/Dem/Dem_Cfg.h b/firmware/src/DiagnosticR/Dem/Dem_Cfg.h new file mode 100644 index 0000000..1a41c3f --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Cfg.h @@ -0,0 +1,254 @@ + +/* + * Generator version: 5.14.0 + * AUTOSAR version: 4.0.3 + */ +#include "DiagnosticR/ProjectCfg.h" + +#if !(((DEM_SW_MAJOR_VERSION == 5) && (DEM_SW_MINOR_VERSION == 14)) ) +//#error Dem: Configuration file expected BSW module version to be 5.14.* +#endif + +#if !(((DEM_AR_RELEASE_MAJOR_VERSION == 4) && (DEM_AR_RELEASE_MINOR_VERSION == 0)) ) +//#error DEM: Configuration file expected AUTOSAR version to be 4.0.* +#endif + + + +#ifndef DEM_CFG_H_ +#define DEM_CFG_H_ + +#define DEM_VERSION_INFO_API STD_OFF +#define DEM_DEV_ERROR_DETECT STD_ON +#define DEM_TRIGGER_DLT_REPORTS STD_OFF +#define DEM_OBD_SUPPORT STD_OFF +#define DEM_PTO_SUPPORT STD_OFF +#define DEM_TYPE_OF_DTC_SUPPORTED DEM_DTC_TRANSLATION_ISO14229_1 +#define DEM_CLEAR_ALL_EVENTS STD_OFF +#define DEM_USE_NVM STD_ON +#define DEM_MAX_NUMBER_EVENT_ENTRY_MIR 0u +#define DEM_MAX_NUMBER_EVENT_ENTRY_PER 0u +#define DEM_MAX_NUMBER_EVENT_ENTRY_PRI 40u +#define DEM_MAX_NUMBER_EVENT_ENTRY_SEC 1u +#define DEM_MAX_NUMBER_EVENT_ENTRY MAX(DEM_MAX_NUMBER_EVENT_ENTRY_PRI, DEM_MAX_NUMBER_EVENT_ENTRY_SEC) + +#define DEM_USE_PRIMARY_MEMORY_SUPPORT STD_ON +#define DEM_USE_SECONDARY_MEMORY_SUPPORT STD_OFF + +#define DEM_MAX_NUMBER_PRESTORED_FF 0u /* Max nr of prestored FreezeFrames. 0=Not supported. */ +#define DEM_DTC_STATUS_AVAILABILITY_MASK 127 +#define DEM_TEST_FAILED_STORAGE STD_ON +#define DEM_NUM_ENABLECONDITIONS 0u +/* @req DEM444 */ +#define DEM_ENABLE_CONDITION_SUPPORT STD_OFF +/* @req DEM401 */ +#define DEM_EVENT_DISPLACEMENT_SUPPORT STD_OFF + +#define DEM_STORE_UDS_STATUS_BIT_SUBSET_FOR_ALL_EVENTS STD_OFF + +#define DEM_DTC_SUPPRESSION_SUPPORT STD_ON +#define DEM_NOF_DTCS 16u + +#define DEM_SET_EVENT_AVAILABLE_PREINIT STD_OFF + +/* Freeze frame capture *//* @req DEM461 */ +#define DEM_FREEZE_FRAME_CAPTURE_TESTFAILED +/* Extended data capture *//* @req DEM467 */ +#define DEM_EXTENDED_DATA_CAPTURE_TESTFAILED +/* + * Size limitations of the types derived from DemGeneral + */ +#define DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA 5u /* 0..253 according to Autosar */ +#define DEM_MAX_NR_OF_EVENT_DESTINATION 1u /* 0..4 according to Autosar */ + +#define DEM_MAX_NR_OF_DIDS_IN_FREEZEFRAME_DATA 5u /* Maximum number of dids referred by one freeze frame */ +#define DEM_MAX_NR_OF_PIDS_IN_FREEZEFRAME_DATA 0u + +/* + * Size limitations of storage area + */ +/* Maximum number of freeze frame record numbers one event may have */ +#define DEM_MAX_RECORD_NUMBERS_IN_FF_REC_NUM_CLASS 2 + +#define DEM_MAX_SIZE_FF_DATA 18u /* Max number of bytes in one freeze frame */ +#define DEM_MAX_SIZE_EXT_DATA 5u /* Max number of bytes in one extended data record */ +#define DEM_MAX_NUMBER_EVENT 22u /* Max number of events to keep status on */ + +#define DEM_MAX_NUMBER_FF_DATA_PRE_INIT 2u /* Max number of freeze frames to store before init */ + +#define DEM_MAX_NUMBER_EXT_DATA_PRE_INIT 16u /* Max number of extended data to store before init */ +/* Primary Memory */ +/* @req DEM162 */ +#define DEM_MAX_NUMBER_EVENT_PRI_MEM (DEM_MAX_NUMBER_EVENT_ENTRY_PRI) /* Max number of events status to store in primary memory */ +#define DEM_PRI_MEM_EVENT_BUFFER_SIZE 328u /* Size of priMemEventBuffer */ +#define DEM_MAX_NUMBER_FF_DATA_PRI_MEM 32u /* Maximum number of freeze frame records to store in primary memory */ +#define DEM_PRI_MEM_FREEZEFRAME_BUFFER_SIZE 768u /* Size of priMemFreezeFrameBuffer */ +#define DEM_MAX_NUMBER_EXT_DATA_PRI_MEM 40u /* Max number of extended data to store in primary memory */ +#define DEM_PRI_MEM_EXTDATA_BUFFER_SIZE 320u /* Size of priMemExtDataBuffer */ + + +/* Secondary memory */ +#define DEM_MAX_NUMBER_EVENT_SEC_MEM (DEM_MAX_NUMBER_EVENT_ENTRY_SEC) /* Max number of events status to store in secondary memory */ +#define DEM_SEC_MEM_EVENT_BUFFER_SIZE 8u /* Size of secMemEventBufferBuffer */ +#define DEM_MAX_NUMBER_FF_DATA_SEC_MEM 0u /* Maximum number of freeze frame records to store in secondary memory */ +#define DEM_SEC_MEM_FREEZEFRAME_BUFFER_SIZE 0u /* Size of secMemFreezeFrameBuffer */ +#define DEM_MAX_NUMBER_EXT_DATA_SEC_MEM 1u /* Max number of extended data to store in secondary memory */ +#define DEM_SEC_MEM_EXTDATA_BUFFER_SIZE 8u /* Size of secMemExtDataBuffer */ + + +#define DEM_FREEZEFRAME_DEFAULT_VALUE 0xFFu +#define DEM_DID_IDENTIFIER_SIZE_OF_BYTES 2u +#define DEM_FREEZEFRAME_RECORD_NUMBER_EOL 0xFFu + +#define DEM_HIGHEST_EXT_DATA_REC_NUM 5u +#define DEM_HIGHEST_FF_REC_NUM 2u + +/* Indicators */ +#define DEM_NOF_INDICATORS 0u +#define DEM_MIL_INIDICATOR_ID DEM_INVALID_INDICATOR + +#define DEM_NOF_EVENT_INDICATORS 0u +#define DEM_INVALID_INDICATOR_INDEX DEM_NOF_EVENT_INDICATORS + +#define DEM_MEM_INDICATOR_BUFFER_SIZE 0u + +/* NvM handles and blocks sizes*/ +#define DEM_EVENT_PRIMARY_NVM_BLOCK_SIZE 328 +//#define DEM_EVENT_PRIMARY_NVM_BLOCK_HANDLE NVM_DemPriEventBlock_HANDLE +#if (DEM_EVENT_PRIMARY_NVM_BLOCK_SIZE != DEM_PRI_MEM_EVENT_BUFFER_SIZE) +#error Dem: Configured NvM block (DemPriEventBlock) does not match size of priMemEventBuffer +#endif +#define DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_SIZE 768 +//#define DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_HANDLE NVM_DemPriFreezeFrameBlock_HANDLE +#if (DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_SIZE != DEM_PRI_MEM_FREEZEFRAME_BUFFER_SIZE) +#error Dem: Configured NvM block (DemPriFreezeFrameBlock) does not match size of priMemFreezeFrameBuffer +#endif +#define DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_SIZE 320 +#define DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_HANDLE NVM_DemPriExtendedDataBlock_HANDLE +#if (DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_SIZE != DEM_PRI_MEM_EXTDATA_BUFFER_SIZE) +#error Dem: Configured NvM block (DemPriExtendedDataBlock) does not match size of priMemExtDataBuffer +#endif + + +#ifndef DEM_EVENT_PRIMARY_NVM_BLOCK_SIZE +#define DEM_EVENT_PRIMARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_EVENT_SECONDARY_NVM_BLOCK_SIZE +#define DEM_EVENT_SECONDARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_SIZE +#define DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_SIZE +#define DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_SIZE +#define DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_SIZE +#define DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_SIZE 0u +#endif +#ifndef DEM_EVENT_PRIMARY_NVM_BLOCK_HANDLE +#define DEM_EVENT_PRIMARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_EVENT_SECONDARY_NVM_BLOCK_HANDLE +#define DEM_EVENT_SECONDARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_HANDLE +#define DEM_FREEZE_FRAME_PRIMARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_HANDLE +#define DEM_FREEZE_FRAME_SECONDARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_HANDLE +#define DEM_EXTENDED_DATA_PRIMARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_HANDLE +#define DEM_EXTENDED_DATA_SECONDARY_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_INDICATOR_NVM_BLOCK_HANDLE +#define DEM_INDICATOR_NVM_BLOCK_HANDLE 0u +#endif +#ifndef DEM_STATUSBIT_NVM_BLOCK_HANDLE +#define DEM_STATUSBIT_NVM_BLOCK_HANDLE 0u +#endif + +#define DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL +#define DEM_AGING_PROCESSING_DEM_INTERNAL +#define DEM_FAILURE_PROCESSING_DEM_INTERNAL +#define DEM_AGING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_CYCLE +#define DEM_HEALING_COUNTER_CLEAR_ON_FAIL_DURING_FAILURE_CYCLE + +#define DEM_NO_DTC 0xFFFFFFFFuL + +typedef struct { + uint32 UDSDTC; + uint32 OBDDTC; + boolean DTCUsed; +} Arc_Dem_DTC; + +typedef struct { + boolean JumpUp;/* @req DEM422 */ + boolean JumpDown;/* @req DEM424 */ + uint16 IncrementStepSize; + uint16 DecrementStepSize; + sint16 JumpDownValue; + sint16 JumpUpValue; + sint16 FailedThreshold;/* @req DEM416 */ + sint16 PassedThreshold;/* @req DEM417 */ +} Dem_PreDebounceCounterBasedType; + +#define DEM_GENERAL_EVENT_DATA_CB STD_OFF +#define DEM_GENERAL_EVENT_STATUS_CB STD_OFF + + +#define DEM_NOF_TIME_BASE_PREDEB 0 +#define DEM_TASK_TIME 10UL + +/* DTC indexes (for dem internal use) */ +//#define DEM_DTC_P123312_PButton2NotOK_INDEX 0u +//#define DEM_DTC_U010100_TCULost_INDEX 1u +#define DEM_DTC_C07300_BusOff_INDEX 0u +#define DEM_DTC_A06800_MorErr_INDEX 1u +#define DEM_DTC_A06700_PressErr_INDEX 2u +#define DEM_DTC_F00616_LowVoltage_INDEX 3u +#define DEM_DTC_F00617_HighVoltage_INDEX 4u +#define DEM_DTC_A06600_TouErr_INDEX 5u +//#define DEM_DTC_U014600_GWBCMLost_INDEX 8u +//#define DEM_DTC_P123311_PButton1NotOK_INDEX 9u +//#define DEM_DTC_P123313_PButton3NotOK_INDEX 10u +//#define DEM_DTC_P271F54_CalibrationFault_INDEX 11u +//#define DEM_DTC_P123411_LButton1NotOK_INDEX 12u +//#define DEM_DTC_P123412_LButton2NotOK_INDEX 13u +//#define DEM_DTC_P123511_LButton1Stucl_INDEX 14u +//#define DEM_DTC_P123512_LButton2Stuck_INDEX 15u + +/* FF indexes (for dem internal use) */ +#define DEM_FF_DemFreezeFrameClass_INDEX 0u + +/* DID indexes (for dem internal use) */ +#define DEM_DID_DID_ADCInformation_INDEX 0u +#define DEM_DID_DID_ActuatorPosInformation_INDEX 1u +#define DEM_DID_DID_BreakStatus_INDEX 2u +#define DEM_DID_DID_IgnitionStatus_INDEX 3u +#define DEM_DID_DID_Mlx_Die2_Val_INDEX 4u +#define DEM_DID_DID_ShiftPosInformation_INDEX 5u +#define DEM_DID_DID_TCUCurrentPosInformation_INDEX 6u +#define DEM_DID_DID_Mlx_Die1_Val_INDEX 7u +#define DEM_DID_DID_ShiftMechPosInformation_INDEX 8u +#define DEM_DID_DID_PbuttonStatus_INDEX 9u +#define DEM_DID_DID_OpDr_AutoP_Status_INDEX 10u +#define DEM_DID_DID_PowerSupply_INDEX 11u + +/* Ext data rec class indexes (for dem internal use) */ +#define DEM_EXT_DATA_REC_CLASS_FaultDetectionsNumber_Class_INDEX 0u +#define DEM_EXT_DATA_REC_CLASS_AgeingCounter_Class_INDEX 1u +#define DEM_EXT_DATA_REC_CLASS_FaultDetectionCounter_Class_INDEX 2u +#define DEM_EXT_DATA_REC_CLASS_UncompledTestCNT_class_INDEX 3u +#define DEM_EXT_DATA_REC_CLASS_DTC_OccurrenceCounter_Class_INDEX 4u + +/* Enable condition indexes (for dem internal use) */ + +/* DTC Groups */ + +#endif /*DEM_CFG_H_*/ diff --git a/firmware/src/DiagnosticR/Dem/Dem_Debounce.c b/firmware/src/DiagnosticR/Dem/Dem_Debounce.c new file mode 100644 index 0000000..e0b512b --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Debounce.c @@ -0,0 +1,451 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#include "Dem.h" +#include "Dem_Types.h" +#include "Dem_Lcfg.h" +#include "DiagnosticR/Dem/Dem_Internal.h" +#include "DiagnosticR/ProjectCfg.h" +#if defined(USE_DEM_EXTENSION) +#include "Dem_Extension.h" +#endif + +/* Local defines */ +#define DEM_UDS_TEST_FAILED_TRESHOLD (sint32)127 +#define DEM_UDS_TEST_PASSED_TRESHOLD (sint32)(-128) +#define DEM_UDS_FDC_RANGE (sint32)(DEM_UDS_TEST_FAILED_TRESHOLD - (DEM_UDS_TEST_PASSED_TRESHOLD)) + +/* Local variables */ +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +/* Buffer for time based debounce */ +static TimeBaseStatusType DemTimeBaseBuffer[DEM_NOF_TIME_BASE_PREDEB]; +#endif + +/* Local functions */ +/** + * Translates internal FDC to external FDC + * @param fdcInternal + * @param pdVars + * @return FDC + */ +static sint8 fdcInternalToUDSFdc(sint16 fdcInternal, const Dem_PreDebounceCounterBasedType* pdVars) +{ + /* Map the internal counter to the corresponding UDS fdc. I.e. map from [FailedThreshold, PassedThreshold] to [-128, 127]. */ + sint32 pdRange = (sint32)((sint32)pdVars->FailedThreshold - (sint32)pdVars->PassedThreshold); + sint32 temp = (DEM_UDS_FDC_RANGE*((sint32)((sint32)fdcInternal - (sint32)pdVars->PassedThreshold))) + (DEM_UDS_TEST_PASSED_TRESHOLD*pdRange); + return (sint8)(temp/pdRange); +} + +/* + * Procedure: preDebounceNone + * Description: Returns the result of the debouncing. + */ +static Dem_EventStatusType preDebounceNone(const Dem_EventStatusType reportedStatus) { + /* @req DEM437 */ + Dem_EventStatusType returnCode; + switch (reportedStatus) { + case DEM_EVENT_STATUS_FAILED: + case DEM_EVENT_STATUS_PASSED: + // Already debounced, do nothing. + break; + + default: + // NOTE: What to do with PREFAIL and PREPASSED on no debouncing? + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_NONE_ID, DEM_E_PARAM_DATA); + break; + } + + returnCode = reportedStatus; + return returnCode; +} + +/* + * Procedure: preDebounceCounterBased + * Description: Returns the result of the debouncing. + */ +static Dem_EventStatusType preDebounceCounterBased(Dem_EventStatusType reportedStatus, EventStatusRecType* statusRecord) { + Dem_EventStatusType returnCode; + const Dem_PreDebounceCounterBasedType* pdVars = statusRecord->eventParamRef->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceCounterBased; + + switch (reportedStatus) { + case DEM_EVENT_STATUS_PREFAILED: + if (statusRecord->fdcInternal < pdVars->FailedThreshold) { + if ((pdVars->JumpUp ==TRUE) && (statusRecord->fdcInternal < pdVars->JumpUpValue)) { + statusRecord->fdcInternal = pdVars->JumpUpValue;/* @req 4.2.2/SWS_DEM_00423 */ + } + if (((sint32)statusRecord->fdcInternal + (sint32)pdVars->IncrementStepSize) < pdVars->FailedThreshold) { + statusRecord->fdcInternal += pdVars->IncrementStepSize;/*lint !e734 OK since we check above that it will not overflow*/ /* @req DEM418 */ + } else { + statusRecord->fdcInternal = pdVars->FailedThreshold; + } + } + break; + + case DEM_EVENT_STATUS_PREPASSED: + if (statusRecord->fdcInternal > pdVars->PassedThreshold) { + if ((pdVars->JumpDown==TRUE) && (statusRecord->fdcInternal > pdVars->JumpDownValue)) { + statusRecord->fdcInternal = pdVars->JumpDownValue;/* @req 4.2.2/SWS_DEM_00425 */ + } + if (((sint32)statusRecord->fdcInternal - (sint32)pdVars->DecrementStepSize) > pdVars->PassedThreshold) { + statusRecord->fdcInternal -= pdVars->DecrementStepSize;/*lint !e734 OK since we check above that it will not overflow*/ /* @req DEM419 */ + } else { + statusRecord->fdcInternal = pdVars->PassedThreshold; + } + } + break; + + case DEM_EVENT_STATUS_FAILED: + statusRecord->fdcInternal = pdVars->FailedThreshold; /* @req DEM420 */ + break; + + case DEM_EVENT_STATUS_PASSED: + statusRecord->fdcInternal = pdVars->PassedThreshold; /* @req DEM421 */ + break; + + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_COUNTER_BASED_ID, DEM_E_PARAM_DATA); + break; + + } + +#if defined(USE_DEM_EXTENSION) + Dem_Extension_PostPreDebounceCounterBased(reportedStatus, statusRecord); +#endif + + if( statusRecord->fdcInternal >= pdVars->FailedThreshold ) { + returnCode = DEM_EVENT_STATUS_FAILED; + } else if( statusRecord->fdcInternal <= pdVars->PassedThreshold ) { + returnCode = DEM_EVENT_STATUS_PASSED; + } else { + returnCode = reportedStatus; + } + /* @req DEM415 */ + statusRecord->UDSFdc = fdcInternalToUDSFdc(statusRecord->fdcInternal, pdVars); + statusRecord->maxUDSFdc = MAX(statusRecord->maxUDSFdc, statusRecord->UDSFdc); + return returnCode; +} + +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +/** + * Calculates FDC based on timer + * @param debounceTimer + * @param pdVars + * @return FDC + */ +static sint8 getTimeBasedFDC(const TimeBaseStatusType *debounceTimer, const Dem_PreDebounceTimeBasedType *pdVars) +{ + /* @req DEM427 */ + sint8 FDC = 0; + sint64 temp; + if( TRUE == debounceTimer->started ) { + if( TRUE == debounceTimer->failureCounting ) { + /* 0 - pdVars->TimeFailedThreshold -> 0 - 127*/ + if( 0UL != pdVars->TimeFailedThreshold ) { + temp = ((sint64)debounceTimer->debounceTime * DEM_UDS_TEST_FAILED_TRESHOLD) / pdVars->TimeFailedThreshold; + temp = MIN(temp, DEM_UDS_TEST_FAILED_TRESHOLD); + FDC = (sint8)temp; + } else { + FDC = (sint8)DEM_UDS_TEST_FAILED_TRESHOLD; + } + + } else { + /* 0 - pdVars->TimePassedThreshold -> 0 - -128*/ + if(0UL != pdVars->TimePassedThreshold) { + temp = ((sint64)debounceTimer->debounceTime * DEM_UDS_TEST_PASSED_TRESHOLD) / pdVars->TimePassedThreshold; + temp = MAX(temp, DEM_UDS_TEST_PASSED_TRESHOLD); + FDC = (sint8)temp; + } else { + FDC = (sint8)DEM_UDS_TEST_PASSED_TRESHOLD; + } + } + } + return FDC; +} + +/** + * Handles starting time based debouncing + * @param reportedStatus + * @param eventParam + * @return + */ +static Dem_EventStatusType preDebounceTimeBased(Dem_EventStatusType reportedStatus, const Dem_EventParameterType *eventParam) +{ + Dem_EventStatusType ret = reportedStatus; + const Dem_PreDebounceTimeBasedType* pdVars = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased; + DemTimeBaseBuffer[pdVars->Index].EventId = eventParam->EventID; + switch (reportedStatus) { + case DEM_EVENT_STATUS_FAILED: + case DEM_EVENT_STATUS_PREFAILED: + /* @req DEM428 */ + /* @req DEM429 */ + if( (FALSE == DemTimeBaseBuffer[pdVars->Index].started) || (FALSE == DemTimeBaseBuffer[pdVars->Index].failureCounting) ) { + DemTimeBaseBuffer[pdVars->Index].started = TRUE; + DemTimeBaseBuffer[pdVars->Index].failureCounting = TRUE; + if( (DEM_EVENT_STATUS_FAILED == reportedStatus) || (0UL == pdVars->TimeFailedThreshold) ) { + /* @req DEM431 */ + DemTimeBaseBuffer[pdVars->Index].debounceTime = pdVars->TimeFailedThreshold; + DemTimeBaseBuffer[pdVars->Index].errorReported = TRUE; + DemTimeBaseBuffer[pdVars->Index].counterReset = FALSE; + ret = DEM_EVENT_STATUS_FAILED; + } else { + DemTimeBaseBuffer[pdVars->Index].debounceTime = 0; + DemTimeBaseBuffer[pdVars->Index].errorReported = FALSE; + DemTimeBaseBuffer[pdVars->Index].counterReset = TRUE; + } + } + break; + case DEM_EVENT_STATUS_PASSED: + case DEM_EVENT_STATUS_PREPASSED: + /* @req DEM432 */ + /* @req DEM433 */ + if( (FALSE == DemTimeBaseBuffer[pdVars->Index].started) || (TRUE == DemTimeBaseBuffer[pdVars->Index].failureCounting) ) { + DemTimeBaseBuffer[pdVars->Index].started = TRUE; + DemTimeBaseBuffer[pdVars->Index].failureCounting = FALSE; + if( (DEM_EVENT_STATUS_PASSED == reportedStatus) || (0UL == pdVars->TimePassedThreshold) ) { + /* @req DEM435 */ + DemTimeBaseBuffer[pdVars->Index].debounceTime = pdVars->TimePassedThreshold; + DemTimeBaseBuffer[pdVars->Index].errorReported = TRUE; + DemTimeBaseBuffer[pdVars->Index].counterReset = FALSE; + ret = DEM_EVENT_STATUS_PASSED; + } else { + DemTimeBaseBuffer[pdVars->Index].debounceTime = 0; + DemTimeBaseBuffer[pdVars->Index].errorReported = FALSE; + DemTimeBaseBuffer[pdVars->Index].counterReset = TRUE; + } + } + + break; + default: + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_COUNTER_BASED_ID, DEM_E_PARAM_DATA); + break; + + } + + return ret; +} +#endif + + +/* Exported functions */ + +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +/** + * Main function for time based predebounce + */ +void TimeBasedDebounceMainFunction(void) +{ + /* Handle time based predebounce */ + /* @req DEM426 */ + const Dem_EventParameterType *eventParam; + EventStatusRecType *eventStatusRec; + for( uint16 idx = 0; idx < DEM_NOF_TIME_BASE_PREDEB; idx++ ) { + eventParam = NULL; + eventStatusRec = NULL; + lookupEventIdParameter(DemTimeBaseBuffer[idx].EventId, &eventParam); /*lint !e934 eventParam only used in this function */ + lookupEventStatusRec(DemTimeBaseBuffer[idx].EventId, &eventStatusRec); /*lint !e934 eventStatusRec only used in this function */ + if( (NULL != eventParam) && (NULL != eventStatusRec) && + (NULL != eventParam->EventClass->PreDebounceAlgorithmClass) && + (DEM_PRE_DEBOUNCE_TIME_BASED == eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName)) { + const Dem_PreDebounceTimeBasedType* pdVars = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased; + + if( TRUE == operationCycleIsStarted(eventParam->EventClass->OperationCycleRef) ) { + if( TRUE == DemTimeBaseBuffer[idx].started ) { + if(FALSE == DemTimeBaseBuffer[idx].counterReset) { + if( TRUE == DemTimeBaseBuffer[idx].failureCounting ) { + if( DemTimeBaseBuffer[idx].debounceTime < pdVars->TimeFailedThreshold ) { + DemTimeBaseBuffer[idx].debounceTime += DEM_TASK_TIME; + } + /* @req DEM430 */ + if( DemTimeBaseBuffer[idx].debounceTime >= pdVars->TimeFailedThreshold ) { + /* FAILED! */ + if(E_OK == handleEvent(DemTimeBaseBuffer[idx].EventId, DEM_EVENT_STATUS_FAILED) ) { + DemTimeBaseBuffer[idx].errorReported = TRUE; + } + } + + + } else { + if( DemTimeBaseBuffer[idx].debounceTime < pdVars->TimePassedThreshold ) { + DemTimeBaseBuffer[idx].debounceTime += DEM_TASK_TIME; + } + /* @req DEM434 */ + if( DemTimeBaseBuffer[idx].debounceTime >= pdVars->TimePassedThreshold ) { + /* PASSED! */ + if( E_OK == handleEvent(DemTimeBaseBuffer[idx].EventId, DEM_EVENT_STATUS_PASSED) ) { + DemTimeBaseBuffer[idx].errorReported = TRUE; + } + } + } + } else { + DemTimeBaseBuffer[idx].counterReset = FALSE; + } + eventStatusRec->UDSFdc = getTimeBasedFDC(&DemTimeBaseBuffer[idx], pdVars); + eventStatusRec->maxUDSFdc = MAX(eventStatusRec->UDSFdc, eventStatusRec->maxUDSFdc); + } + } else { + /* Operation cycle is not started. + * Cancel timer. */ + DemTimeBaseBuffer[idx].started = FALSE; + DemTimeBaseBuffer[idx].errorReported = FALSE; + } + } + } +} +#endif + +/** + * Resets debounce counter of event + * @param eventStatusRec + */ +void resetDebounceCounter(EventStatusRecType *eventStatusRec) +{ + sint8 startFDC = getDefaultUDSFdc(eventStatusRec->eventId); + eventStatusRec->UDSFdc = startFDC;/* @req DEM344 */ + eventStatusRec->maxUDSFdc = startFDC; + eventStatusRec->fdcInternal = 0; +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) + const Dem_EventParameterType *eventParam = NULL; + lookupEventIdParameter(eventStatusRec->eventId, &eventParam); /*lint !e934 eventParam only used in this function */ + if( NULL != eventParam ) { + if( (NULL != eventParam->EventClass->PreDebounceAlgorithmClass) && + (DEM_PRE_DEBOUNCE_TIME_BASED == eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) ) { + DemTimeBaseBuffer[eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased->Index].started = FALSE; + DemTimeBaseBuffer[eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased->Index].errorReported = FALSE; + DemTimeBaseBuffer[eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased->Index].debounceTime = 0UL; + } + } +#endif +} + + + + +/* + * Procedure: getFaultDetectionCounter + * Description: Returns pre debounce counter of "eventId" in "counter" and return value E_OK if + * the counter was available else E_NOT_OK. + */ +Std_ReturnType getFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter) +{ + Std_ReturnType returnCode = E_NOT_OK; + const Dem_EventParameterType *eventParam; + EventStatusRecType *eventStatusRec = NULL; + lookupEventStatusRec(eventId, &eventStatusRec); /*lint !e934 eventStatusRec only used in this function */ + lookupEventIdParameter(eventId, &eventParam); /*lint !e934 eventParam only used in this function */ + if ((eventParam != NULL) && (NULL != eventStatusRec) && (TRUE == eventStatusRec->isAvailable)) { + if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) { + switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) + { + case DEM_NO_PRE_DEBOUNCE: + if (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal != NULL) { + if (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCntFnc != NULL) { + /* @req DEM204 None */ + /* @req DEM264 */ + /* @req DEM439 */ + returnCode = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCntFnc(counter); + } + } + break; + + case DEM_PRE_DEBOUNCE_COUNTER_BASED: + *counter = eventStatusRec->UDSFdc; /* @req DEM204 Counter */ + returnCode = E_OK; + break; + +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) + case DEM_PRE_DEBOUNCE_TIME_BASED: + /* Map timer to FDC */ + *counter = getTimeBasedFDC(&DemTimeBaseBuffer[eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased->Index], + eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceTimeBased); + returnCode = E_OK; + break; +#endif + + default: + //DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_PARAM_DATA); + break; + } + } + } + + return returnCode; +} + +/** + * Initializes time based debounce buffer + */ +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +void InitTimeBasedDebounce(void) +{ + for( uint16 idx = 0; idx < DEM_NOF_TIME_BASE_PREDEB; idx++ ) { + DemTimeBaseBuffer[idx].EventId = DEM_EVENT_ID_NULL; + DemTimeBaseBuffer[idx].started = FALSE; + } +} +#endif + +/** + * Gets the default UDS fdc + * @param eventId + * @return + */ +sint8 getDefaultUDSFdc(Dem_EventIdType eventId) +{ + sint8 udsFdc = 0; + const Dem_EventParameterType *eventParam = NULL; + lookupEventIdParameter(eventId, &eventParam); /*lint !e934 eventParam only used in this function */ + if( NULL != eventParam ) { + if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) { + switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) { + case DEM_PRE_DEBOUNCE_COUNTER_BASED: + udsFdc = fdcInternalToUDSFdc(0, eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceCounterBased); + break; + default: + break; + } + } + } + return udsFdc; +} + +/** + * Runs predebounce for event + * @param reportedEventStatus + * @param eventStatusRecPtr + * @param eventParam + * @return calculated eventStatus + */ +Dem_EventStatusType RunPredebounce(Dem_EventStatusType reportedEventStatus, EventStatusRecType *eventStatusRecPtr, const Dem_EventParameterType *eventParam) +{ + Dem_EventStatusType eventStatus = reportedEventStatus; + if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) { + switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) { + case DEM_NO_PRE_DEBOUNCE: + eventStatus = preDebounceNone(reportedEventStatus); + break; + case DEM_PRE_DEBOUNCE_COUNTER_BASED: + eventStatus = preDebounceCounterBased(reportedEventStatus, eventStatusRecPtr); + break; +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) + case DEM_PRE_DEBOUNCE_TIME_BASED: + eventStatus = preDebounceTimeBased(reportedEventStatus, eventParam); + break; +#endif + default: + // DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_NOT_IMPLEMENTED_YET); + break; + } + } + return eventStatus; +} diff --git a/firmware/src/DiagnosticR/Dem/Dem_Extension.c b/firmware/src/DiagnosticR/Dem/Dem_Extension.c new file mode 100644 index 0000000..7c98566 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Extension.c @@ -0,0 +1,142 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#include "Dem_Extension.h" +#include "Dem.h" +#include "Std_Types.h" + +void Dem_Extension_MainFunction(void) +{ + +} + +void Dem_Extension_ClearEvent(const Dem_EventParameterType *eventParam) +{ + (void)eventParam; +} + +void Dem_Extension_UpdateEventstatus(EventStatusRecType *eventStatusRecPtr, uint8 eventStatusExtendedBeforeUpdate, Dem_EventStatusType eventStatus) +{ + (void)eventStatusRecPtr; + (void)eventStatusExtendedBeforeUpdate; + (void)eventStatus; +} + + + +void Dem_Extension_OperationCycleStart(Dem_OperationCycleIdType operationCycleId, EventStatusRecType *eventStatusRecPtr) +{ + (void)operationCycleId; + (void)eventStatusRecPtr; +} + +void Dem_Extension_OperationCycleEnd(Dem_OperationCycleIdType operationCycleId, EventStatusRecType *eventStatusRecPtr) +{ + (void)operationCycleId; + (void)eventStatusRecPtr; +} + +void Dem_Extension_PreInit(const Dem_ConfigType *ConfigPtr) +{ + (void)ConfigPtr; +} + +void Dem_Extension_Init_PostEventMerge(Dem_DTCOriginType origin) +{ + +} + +void Dem_Extension_Init_Complete(void) +{ + +} + +void Dem_Extension_Shutdown(void) +{ + +} + +void Dem_Extension_GetExtendedDataInternalElement(Dem_EventIdType eventId, Dem_InternalDataElementType internalElement, uint8 *dataBuf, uint16 size) +{ + (void)eventId; + (void)internalElement; + (void)dataBuf; + (void)size; +} + +void Dem_Extension_PostPreDebounceCounterBased(Dem_EventStatusType reportedStatus, EventStatusRecType* statusRecord) +{ + (void)reportedStatus; + (void)statusRecord; +} + + +void Dem_Extension_HealedEvent(Dem_EventIdType eventId) +{ + (void)eventId; +} + +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) +void Dem_Extension_GetExtDataEventForDisplacement(const Dem_EventParameterType *eventParam, const ExtDataRecType *extDataBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + (void)eventParam; + (void)extDataBuffer; + (void)bufferSize; + (void)eventParam; +} + +void Dem_Extension_GetEventForDisplacement(const Dem_EventParameterType *eventParam, const EventRecType *eventRecordBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + (void)eventParam; + (void)eventRecordBuffer; + (void)bufferSize; + (void)eventParam; +} + +void Dem_Extension_GetFFEventForDisplacement(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *ffBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove) +{ + (void)eventParam; + (void)ffBuffer; + (void)bufferSize; + (void)eventParam; +} +#endif + +void Dem_Extension_EventDataDisplaced(Dem_EventIdType eventId) +{ + (void)eventId; +} + +void Dem_Extension_EventExtendedDataDisplaced(Dem_EventIdType eventId) +{ + (void)eventId; +} + +void Dem_Extension_EventFreezeFrameDataDisplaced(Dem_EventIdType eventId) +{ + (void)eventId; +} + +void Dem_Extension_PreMergeExtendedData(Dem_EventIdType eventId, boolean *UpdateAllData) +{ + (void)eventId; + (void)UpdateAllData; +} +void Dem_Extension_PreTransferPreInitFreezeFrames(Dem_EventIdType eventId, boolean *removeOldRecords, Dem_DTCOriginType origin) +{ + (void)eventId; + (void)removeOldRecords; + (void)origin; +} + diff --git a/firmware/src/DiagnosticR/Dem/Dem_Extension.h b/firmware/src/DiagnosticR/Dem/Dem_Extension.h new file mode 100644 index 0000000..af92c3f --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Extension.h @@ -0,0 +1,54 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef DEM_EXTENSION_H_ +#define DEM_EXTENSION_H_ + +#include "Dem.h" +#include "Dem_Internal.h" + +#define DEM_EXTENSION_UPDATE_EVENT_STATUS_ID 0xA0 +#define DEM_EXTENSION_INIT_ID 0xA1 +#define DEM_EXTENSION_PRE_INIT_ID 0xA2 +#define DEM_EXTENSION_EVENT_DATA_DISPLACED_ID 0xA3 + +/* Errors only used in the extension module */ +#define DEM_E_EXTENSION_PRE_INIT_BUFFER_FULL 0x60 +#define DEM_E_EXTENSION_EVENT_BUFF_FULL 0x61 + +void Dem_Extension_MainFunction(void); +void Dem_Extension_ClearEvent(const Dem_EventParameterType *eventParam); +void Dem_Extension_UpdateEventstatus(EventStatusRecType *eventStatusRecPtr, uint8 eventStatusExtendedBeforeUpdate, Dem_EventStatusType eventStatus); +void Dem_Extension_OperationCycleStart(Dem_OperationCycleIdType operationCycleId, EventStatusRecType *eventStatusRecPtr); +void Dem_Extension_OperationCycleEnd(Dem_OperationCycleIdType operationCycleId, EventStatusRecType *eventStatusRecPtr); +void Dem_Extension_PreInit(const Dem_ConfigType *ConfigPtr); +void Dem_Extension_Init_PostEventMerge(Dem_DTCOriginType origin); +void Dem_Extension_Init_Complete(void); +void Dem_Extension_Shutdown(void); +void Dem_Extension_GetExtendedDataInternalElement(Dem_EventIdType eventId, Dem_InternalDataElementType internalElement, uint8 *dataBuf, uint16 size); +void Dem_Extension_PostPreDebounceCounterBased(Dem_EventStatusType reportedStatus, EventStatusRecType* statusRecord); +void Dem_Extension_HealedEvent(Dem_EventIdType eventId); +#if defined(DEM_DISPLACEMENT_PROCESSING_DEM_EXTENSION) +void Dem_Extension_GetExtDataEventForDisplacement(const Dem_EventParameterType *eventParam, const ExtDataRecType *extDataBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove); +void Dem_Extension_GetEventForDisplacement(const Dem_EventParameterType *eventParam, const EventRecType *eventRecordBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove); /*lint !e9018 'eventRecordBuffer' with union based type 'EventRecType */ +void Dem_Extension_GetFFEventForDisplacement(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *ffBuffer, uint32 bufferSize, Dem_EventIdType *eventToRemove); +#endif + +void Dem_Extension_EventDataDisplaced(Dem_EventIdType eventId); +void Dem_Extension_EventExtendedDataDisplaced(Dem_EventIdType eventId); +void Dem_Extension_EventFreezeFrameDataDisplaced(Dem_EventIdType eventId); +void Dem_Extension_PreMergeExtendedData(Dem_EventIdType eventId, boolean *UpdateAllData); +void Dem_Extension_PreTransferPreInitFreezeFrames(Dem_EventIdType eventId, boolean *removeOldRecords, Dem_DTCOriginType origin); + +#endif /* DEM_EXTENSION_H_ */ diff --git a/firmware/src/DiagnosticR/Dem/Dem_IntErrId.h b/firmware/src/DiagnosticR/Dem/Dem_IntErrId.h new file mode 100644 index 0000000..50d5b82 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_IntErrId.h @@ -0,0 +1,83 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + + + + + + + + +//#warning "This default file may only be used as an example!" + +#ifndef DEM_INTERRID_H_ +#define DEM_INTERRID_H_ + +#endif /*DEM_INTERRID_H_*/ +/* + * Definition of event IDs used by BSW + * NB! Must be unique for each event! + */ + +enum { + // Event IDs from DEM module + DEM_EVENT_ID_NULL = 0, // Do not change this entry!!! + + // Event IDs from MCU + MCU_E_CLOCK_FAILURE, + + // Event IDs from CAN + CANTRCV_E_NO_TRCV_CONTROL, + CANTP_E_OPER_NOT_SUPPORTED, + CANTP_E_COMM, + CANNM_E_CANIF_TRANSMIT_ERROR, + CANNM_E_NETWORK_TIMEOUT, + CANIF_TRCV_E_TRANSCEIVER, + CANIF_E_INVALID_DLC, + CANIF_STOPPED, + CANIF_E_FULL_TX_BUFFER, + CAN_E_TIMEOUT, + + // Event IDs from EEPROM + EEP_E_COM_FAILURE, + + // Event IDs from flash + FLS_E_ERASE_FAILED, + FLS_E_WRITE_FAILED, + FLS_E_READ_FAILED, + FLS_E_COMPARE_FAILED, + FLS_E_UNEXPECTED_FLASH_ID, + + // Event IDs from LIN + LIN_E_TIMEOUT, + + // Event IDs from ECU + ECUM_E_RAM_CHECK_FAILED, + ECUM_E_ALL_RUN_REQUESTS_KILLED, + ECUM_E_CONFIGURATION_DATA_INCONSISTENT, + + // Event IDs from COM +// COMM_E_NET_START_IND_CHANNEL_, + + // Event IDs from PDUR + PDUR_E_PDU_INSTANCE_LOST, + PDUR_E_INIT_FAILED, + + // Event IDs from WDGM + WDGM_E_ALIVE_SUPERVISION, + WDGM_E_SET_MODE, + + // DEM last event id for BSW + DEM_EVENT_ID_LAST_FOR_BSW +}; diff --git a/firmware/src/DiagnosticR/Dem/Dem_IntEvtId.h b/firmware/src/DiagnosticR/Dem/Dem_IntEvtId.h new file mode 100644 index 0000000..cc5931c --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_IntEvtId.h @@ -0,0 +1,38 @@ + +/* + * Generator version: 5.14.0 + * AUTOSAR version: 4.0.3 + */ + +#if !(((DEM_SW_MAJOR_VERSION == 5) && (DEM_SW_MINOR_VERSION == 14)) ) +#error Dem: Configuration file expected BSW module version to be 5.14.* +#endif + +#if !(((DEM_AR_RELEASE_MAJOR_VERSION == 4) && (DEM_AR_RELEASE_MINOR_VERSION == 0)) ) +#error DEM: Configuration file expected AUTOSAR version to be 4.0.* +#endif + +#ifndef DEMINTEVTID_H_ +#define DEMINTEVTID_H_ + +#define DEM_EVENT_ID_SWC_START (Dem_EventIdType)7u +//#define DemConf_DemEventParameter_P123312_P_BUTTON2_NOT_OK (Dem_EventIdType)10u +//#define DemConf_DemEventParameter_P123311_P_BUTTON1_NOT_OK (Dem_EventIdType)11u +//#define DemConf_DemEventParameter_P123313_P_BUTTON3_NOT_OK (Dem_EventIdType)12u +//#define DemConf_DemEventParameter_U014600_GW_BCM_LOST (Dem_EventIdType)13u +//#define DemConf_DemEventParameter_U010100_TCU_LOST (Dem_EventIdType)16u +#define DemConf_DemEventParameter_C07300_BUS_OFF (Dem_EventIdType)0u +#define DemConf_DemEventParameter_A06800_MorErr (Dem_EventIdType)1u +#define DemConf_DemEventParameter_A06700_PressErr (Dem_EventIdType)2u +#define DemConf_DemEventParameter_F00616_LOW_VOLTAGE (Dem_EventIdType)3u +#define DemConf_DemEventParameter_F00617_HIGH_VOLTAGE (Dem_EventIdType)4u +#define DemConf_DemEventParameter_A06600_TouErr (Dem_EventIdType)5u +//#define DemConf_DemEventParameter_P271F54_Calibration_Fault (Dem_EventIdType)18u +//#define DemConf_DemEventParameter_P123411_L_BUTTON1_NOT_OK (Dem_EventIdType)19u +//#define DemConf_DemEventParameter_P123412_L_BUTTON2_NOT_OK (Dem_EventIdType)20u +//#define DemConf_DemEventParameter_P123511_L_BUTTON1_STUCK (Dem_EventIdType)21u +//#define DemConf_DemEventParameter_P123512_L_BUTTON2_STUCK (Dem_EventIdType)22u +#define DEM_EVENT_ID_LAST_FOR_SWC (Dem_EventIdType)6u +#define DEM_EVENT_ID_LAST_VALID_ID DEM_EVENT_ID_LAST_FOR_SWC + +#endif /*DEMINTEVTID_H_*/ diff --git a/firmware/src/DiagnosticR/Dem/Dem_Internal.h b/firmware/src/DiagnosticR/Dem/Dem_Internal.h new file mode 100644 index 0000000..50845cd --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Internal.h @@ -0,0 +1,133 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef DEM_INTERNAL_H_ +#define DEM_INTERNAL_H_ + +#if defined(DEM_FREEZE_FRAME_CAPTURE_EXTENSION) +#define DEM_EXT_STORE_FF_BIT (uint8)(1u<<0u) +#define DEM_EXT_CLEAR_BEFORE_STORE_FF_BIT (uint8)(1u<<1u) +#endif +#if defined(DEM_EXTENDED_DATA_CAPTURE_EXTENSION) +#define DEM_EXT_STORE_EXT_DATA_BIT (uint8)(1u<<2u) +#define DEM_EXT_CLEAR_BEFORE_STORE_EXT_DATA_BIT (uint8)(1u<<3u) +#endif + +#include "Dem.h" + +#if ( DEM_DEV_ERROR_DETECT == STD_ON ) +#if defined(USE_DET) +#include "Det.h" +#endif +/** @req DEM117 */ +//#define DET_REPORTERROR(_x,_y,_z,_q) (void)Det_ReportError(_x, _y, _z, _q) + +#else +#define DET_REPORTERROR(_x,_y,_z,_q) +#endif + +#if (DEM_NOF_TIME_BASE_PREDEB > 0) +#define DEM_USE_TIME_BASE_PREDEBOUNCE +#endif + +// For keeping track of the events status +/* NOTE: Do not change EventStatusRecType without also changing generation of measurement tags */ +typedef struct { + const Dem_EventParameterType *eventParamRef; + uint32 timeStamp; + Dem_EventIdType eventId; + uint16 occurrence; /** @req DEM011 */ + sint16 fdcInternal; /** @req DEM414 */ + sint8 UDSFdc; + sint8 maxUDSFdc; + uint8 failureCounter; + uint8 agingCounter; + Dem_EventStatusExtendedType eventStatusExtended; /** @req DEM006 */ + uint8 extensionDataStoreBitfield; + boolean failedDuringAgingCycle:1; /*lint !e46 *//*structure must remain the same, field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean passedDuringAgingCycle:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean failedDuringFailureCycle:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean passedDuringFailureCycle:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean errorStatusChanged:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean extensionDataChanged:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean indicatorDataChanged:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean isAvailable:1; /*lint !e46 *//*structure must remain the same,field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ +} EventStatusRecType; + +// Types for storing different event data on event memory +/* ****************************************************************************************************** + * WARNING: DO NOT CHANGE THESE STRUCTURES WITHOUT UPDATED THE DEM GENERATOR!! + * ******************************************************************************************************/ +typedef union { + struct { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + uint32 timeStamp; +#endif + Dem_EventIdType eventId; + uint16 occurrence; + Dem_EventStatusExtendedType eventStatusExtended; +#if defined(DEM_FAILURE_PROCESSING_DEM_INTERNAL) + uint8 failureCounter; +#endif +#if defined(DEM_AGING_PROCESSING_DEM_INTERNAL) + uint8 agingCounter;/* @req DEM492 */ +#endif + }EventData; + struct { + /* NOTE: This must be kept smaller than the event data */ + uint16 magic; + boolean overflow; + }AdminData; +} EventRecType; + +typedef struct { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + uint32 timeStamp; +#endif + Dem_EventIdType eventId; + uint8 data[DEM_MAX_SIZE_EXT_DATA]; +} ExtDataRecType; + +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +typedef struct { + uint32 debounceTime; + Dem_EventIdType EventId; + boolean started:1;/*lint !e46 *//*structure must remain the same, field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean failureCounting:1;/*lint !e46 *//*structure must remain the same, field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean errorReported:1;/*lint !e46 *//*structure must remain the same, field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ + boolean counterReset:1;/*lint !e46 *//*structure must remain the same, field type should be _Bool, unsigned int or signed int [MISRA 2004 6.4, 2012 6.1]*/ +}TimeBaseStatusType; +#endif + +void lookupEventStatusRec(Dem_EventIdType eventId, EventStatusRecType **const eventStatusRec); +boolean operationCycleIsStarted(Dem_OperationCycleIdType opCycle); + +#if (DEM_UNIT_TEST == STD_ON) +void demZeroPriMemBuffers(void); +void demZeroSecMemBuffers(void); +#endif +void lookupEventIdParameter(Dem_EventIdType eventId, const Dem_EventParameterType **const eventIdParam); +Std_ReturnType handleEvent(Dem_EventIdType eventId, Dem_EventStatusType eventStatus); + +/* Debouncing functions */ +void resetDebounceCounter(EventStatusRecType *eventStatusRec); +Std_ReturnType getFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter); +sint8 getDefaultUDSFdc(Dem_EventIdType eventId); +Dem_EventStatusType RunPredebounce(Dem_EventStatusType reportedEventStatus, EventStatusRecType *eventStatusRecPtr, const Dem_EventParameterType *eventParam); +#if defined(DEM_USE_TIME_BASE_PREDEBOUNCE) +void InitTimeBasedDebounce(void); +void TimeBasedDebounceMainFunction(void); +#endif + +#endif /* DEM_INTERNAL_H_ */ diff --git a/firmware/src/DiagnosticR/Dem/Dem_LCfg.c b/firmware/src/DiagnosticR/Dem/Dem_LCfg.c new file mode 100644 index 0000000..055ff11 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_LCfg.c @@ -0,0 +1,3276 @@ + +/* + * Generator version: 5.14.0 + * AUTOSAR version: 4.0.3 + */ + +#include "Dem.h" +#include "CalibrationData.h" +#if (DEM_USE_NVM == STD_ON) +//#include "NvM.h" +#endif + +#if defined(USE_RTE) +#include "Rte_Dem.h" +#endif + +//#include "CalibrationData.h" +/* Included header files containing callback declarations */ +//#include "Dem_Callbacks.h" + +// ######################################### INFO ######################################### +// The following data read callbacks should be declared in the included header files: + +// Std_ReturnType Get_Mlx_Die1_Val(uint8 *Data); +// Std_ReturnType Get_TCU_GearPos_Info(uint8 *Data); +// Std_ReturnType Get_Actuator_Pos_Info(uint8 *Data); +// Std_ReturnType Get_GSM_GearPos_Info(uint8 *Data); +// Std_ReturnType Get_Mlx_Die2_Val(uint8 *Data); +// Std_ReturnType Get_Internal_ADC_Info(uint8 *Data); +// Std_ReturnType Get_Battery_Status(uint8 *Data); +// Std_ReturnType Get_Break_Status(uint8 *Data); +// Std_ReturnType Get_Ignition_Status(uint8 *Data); +// Std_ReturnType Get_LMC_MechPos_Info(uint8 *Data); +// Std_ReturnType Get_ShieldOpDr_AutoP_Status(uint8 *Data); +// Std_ReturnType Get_Pbutton_Status(uint8 *Data); +// Std_ReturnType Get_PowerSupply(uint8 *Data); +// ########################################################################################## +// Rte functions + +#define DEM_PIDANDDID_LIST_EOL_INDEX 12u +#define DEM_FF_LIST_EOL_INDEX 1u + +#define DEM_PID_LIST_EOL_INDEX 0u +#define DEM_DID_LIST_EOL_INDEX 12u + +#if (DEM_MAX_NUMBER_EVENT_PRI_MEM < 16) && (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_OFF) +#warning Dem: The number of events with event destination primary memory is greater than the configured maximum \ +number of events which can be stored in primary memory (Dem Max Number Event Entry Primary)! \ +If changing Dem Max Number Event Entry Primary also make sure that the Fee block is big enough (if Fee used). +#endif + +#if (DEM_MAX_NUMBER_EVENT_SEC_MEM < 0) && (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_OFF) +#warning Dem: The number of events with event destination secondary memory is greater than the configured maximum \ +number of events which can be stored in seconday memory (Dem Max Number Event Entry Secondary)! \ +If changing Dem Max Number Event Entry Secondary also make sure that the Fee block is big enough (if Fee used). +#endif + +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123312_PButton2NotOK_DTC + * @desc calib param for DTC P123312_PButton2NotOK + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123312_PButton2NotOK_DTC) = { +#else +//Arc_Dem_DTC P123312_PButton2NotOK_DTC = { +#endif /* HOST_TEST */ +// .UDSDTC = 1192722, +// .OBDDTC = DEM_NO_DTC, +// .DTCUsed = TRUE, +//}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic U010100_TCULost_DTC + * @desc calib param for DTC U010100_TCULost + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +/* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, U010100_TCULost_DTC) = { +#else +Arc_Dem_DTC U010100_TCULost_DTC = { +#endif + .UDSDTC = 12648704, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic C07300_BusOff_DTC + * @desc calib param for DTC C07300_BusOff + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, C07300_BusOff_DTC) = { +#else +Arc_Dem_DTC C07300_BusOff_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 12612352, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06800_MorErr_DTC + * @desc calib param for DTC A06800_MorErr + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, A06800_MorErr_DTC) = { +#else +Arc_Dem_DTC A06800_MorErr_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 10512384, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06700_PressErr_DTC + * @desc calib param for DTC A06700_PressErr + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, A06700_PressErr_DTC) = { +#else +Arc_Dem_DTC A06700_PressErr_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 10512128, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic F00616_LowVoltage_DTC + * @desc calib param for DTC F00616_LowVoltage + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, F00616_LowVoltage_DTC) = { +#else +Arc_Dem_DTC F00616_LowVoltage_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 15730198, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic F00617_HighVoltage_DTC + * @desc calib param for DTC F00617_HighVoltage + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, F00617_HighVoltage_DTC) = { +#else +Arc_Dem_DTC F00617_HighVoltage_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 15730199, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06600_TouErr_DTC + * @desc calib param for DTC A06600_TouErr + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, A06600_TouErr_DTC) = { +#else +Arc_Dem_DTC A06600_TouErr_DTC = { +#endif /* HOST_TEST */ + .UDSDTC = 10511872, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic U014600_GWBCMLost_DTC + * @desc calib param for DTC U014600_GWBCMLost + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, U014600_GWBCMLost_DTC) = { +#else +Arc_Dem_DTC U014600_GWBCMLost_DTC = { +#endif + .UDSDTC = 12666368, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123311_PButton1NotOK_DTC + * @desc calib param for DTC P123311_PButton1NotOK + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ +/* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123311_PButton1NotOK_DTC) = { +#else +Arc_Dem_DTC P123311_PButton1NotOK_DTC = { +#endif + .UDSDTC = 1192721, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123313_PButton3NotOK_DTC + * @desc calib param for DTC P123313_PButton3NotOK + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123313_PButton3NotOK_DTC) = { +#else +Arc_Dem_DTC P123313_PButton3NotOK_DTC = { +#endif + .UDSDTC = 1192723, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P271F54_CalibrationFault_DTC + * @desc calib param for DTC P271F54_CalibrationFault + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P271F54_CalibrationFault_DTC) = { +#else +Arc_Dem_DTC P271F54_CalibrationFault_DTC = { +#endif + .UDSDTC = 2563924, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123411_LButton1NotOK_DTC + * @desc calib param for DTC P123411_LButton1NotOK + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123411_LButton1NotOK_DTC) = { +#else +Arc_Dem_DTC P123411_LButton1NotOK_DTC = { +#endif + .UDSDTC = 1192977, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123412_LButton2NotOK_DTC + * @desc calib param for DTC P123412_LButton2NotOK + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123412_LButton2NotOK_DTC) = { +#else +Arc_Dem_DTC P123412_LButton2NotOK_DTC = { +#endif + .UDSDTC = 1192978, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123511_LButton1Stucl_DTC + * @desc calib param for DTC P123511_LButton1Stucl + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123511_LButton1Stucl_DTC) = { +#else +Arc_Dem_DTC P123511_LButton1Stucl_DTC = { +#endif + .UDSDTC = 1193233, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123512_LButton2Stuck_DTC + * @desc calib param for DTC P123512_LButton2Stuck + * @struct_size 3 + * @field_name UDSDTC + * @min 1 + * @max 16777214 + * @type uint32 + * @field_name OBDDTC + * @min 1 + * @max 65535 + * @type uint32 + * @field_name DTCUsed + * @min 0 + * @max 1 + * @type uint8 + */ + /* +#if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const Arc_Dem_DTC, P123512_LButton2Stuck_DTC) = { +#else +Arc_Dem_DTC P123512_LButton2Stuck_DTC = { +#endif + .UDSDTC = 1193234, + .OBDDTC = DEM_NO_DTC, + .DTCUsed = TRUE, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/* +const Dem_EventIdType DTC_P123312_PButton2NotOK_Events[] = { + DemConf_DemEventParameter_P123312_P_BUTTON2_NOT_OK +}; + +const Dem_EventIdType DTC_U010100_TCULost_Events[] = { + DemConf_DemEventParameter_U010100_TCU_LOST +}; +*/ + +const Dem_EventIdType DTC_C07300_BusOff_Events[] = { + DemConf_DemEventParameter_C07300_BUS_OFF +}; + +const Dem_EventIdType DTC_A06800_MorErr_Events[] = { + DemConf_DemEventParameter_A06800_MorErr +}; + +const Dem_EventIdType DTC_A06700_PressErr_Events[] = { + DemConf_DemEventParameter_A06700_PressErr +}; + +const Dem_EventIdType DTC_F00616_LowVoltage_Events[] = { + DemConf_DemEventParameter_F00616_LOW_VOLTAGE +}; + +const Dem_EventIdType DTC_F00617_HighVoltage_Events[] = { + DemConf_DemEventParameter_F00617_HIGH_VOLTAGE +}; + +const Dem_EventIdType DTC_A06600_TouErr_Events[] = { + DemConf_DemEventParameter_A06600_TouErr +}; + +/* +const Dem_EventIdType DTC_U014600_GWBCMLost_Events[] = { + DemConf_DemEventParameter_U014600_GW_BCM_LOST +}; + +const Dem_EventIdType DTC_P123311_PButton1NotOK_Events[] = { + DemConf_DemEventParameter_P123311_P_BUTTON1_NOT_OK +}; + +const Dem_EventIdType DTC_P123313_PButton3NotOK_Events[] = { + DemConf_DemEventParameter_P123313_P_BUTTON3_NOT_OK +}; + +const Dem_EventIdType DTC_P271F54_CalibrationFault_Events[] = { + DemConf_DemEventParameter_P271F54_Calibration_Fault +}; + +const Dem_EventIdType DTC_P123411_LButton1NotOK_Events[] = { + DemConf_DemEventParameter_P123411_L_BUTTON1_NOT_OK +}; + +const Dem_EventIdType DTC_P123412_LButton2NotOK_Events[] = { + DemConf_DemEventParameter_P123412_L_BUTTON2_NOT_OK +}; + +const Dem_EventIdType DTC_P123511_LButton1Stucl_Events[] = { + DemConf_DemEventParameter_P123511_L_BUTTON1_STUCK +}; + +const Dem_EventIdType DTC_P123512_LButton2Stuck_Events[] = { + DemConf_DemEventParameter_P123512_L_BUTTON2_STUCK +}; +*/ + +const Dem_DTCClassType DtcClassList[] = { + /* + { //P123312_PButton2NotOK + .DTCRef = &P123312_PButton2NotOK_DTC, + .DTCIndex = 0u, + .Events = DTC_P123312_PButton2NotOK_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //U010100_TCULost + .DTCRef = &U010100_TCULost_DTC, + .DTCIndex = 1u, + .Events = DTC_U010100_TCULost_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + */ + { //C07300_BusOff + .DTCRef = &C07300_BusOff_DTC, + .DTCIndex = 2u, + .Events = DTC_C07300_BusOff_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //A06800_MorErr + .DTCRef = &A06800_MorErr_DTC, + .DTCIndex = 3u, + .Events = DTC_A06800_MorErr_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //A06700_PressErr + .DTCRef = &A06700_PressErr_DTC, + .DTCIndex = 4u, + .Events = DTC_A06700_PressErr_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //F00616_LowVoltage + .DTCRef = &F00616_LowVoltage_DTC, + .DTCIndex = 5u, + .Events = DTC_F00616_LowVoltage_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //F00617_HighVoltage + .DTCRef = &F00617_HighVoltage_DTC, + .DTCIndex = 6u, + .Events = DTC_F00617_HighVoltage_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //A06600_TouErr + .DTCRef = &A06600_TouErr_DTC, + .DTCIndex = 7u, + .Events = DTC_A06600_TouErr_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + /* + { //U014600_GWBCMLost + .DTCRef = &U014600_GWBCMLost_DTC, + .DTCIndex = 8u, + .Events = DTC_U014600_GWBCMLost_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123311_PButton1NotOK + .DTCRef = &P123311_PButton1NotOK_DTC, + .DTCIndex = 9u, + .Events = DTC_P123311_PButton1NotOK_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123313_PButton3NotOK + .DTCRef = &P123313_PButton3NotOK_DTC, + .DTCIndex = 10u, + .Events = DTC_P123313_PButton3NotOK_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P271F54_CalibrationFault + .DTCRef = &P271F54_CalibrationFault_DTC, + .DTCIndex = 11u, + .Events = DTC_P271F54_CalibrationFault_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123411_LButton1NotOK + .DTCRef = &P123411_LButton1NotOK_DTC, + .DTCIndex = 12u, + .Events = DTC_P123411_LButton1NotOK_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123412_LButton2NotOK + .DTCRef = &P123412_LButton2NotOK_DTC, + .DTCIndex = 13u, + .Events = DTC_P123412_LButton2NotOK_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123511_LButton1Stucl + .DTCRef = &P123511_LButton1Stucl_DTC, + .DTCIndex = 14u, + .Events = DTC_P123511_LButton1Stucl_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + { //P123512_LButton2Stuck + .DTCRef = &P123512_LButton2Stuck_DTC, + .DTCIndex = 15u, + .Events = DTC_P123512_LButton2Stuck_Events, + .NofEvents = 1u, + .DTCKind = DEM_DTC_KIND_ALL_DTCS, + .DTCSeverity = DEM_SEVERITY_CHECK_IMMEDIATELY, + .Arc_EOL = FALSE + }, + */ + { + .Arc_EOL = TRUE + } +}; + + + +const Dem_ExtendedDataRecordClassType ExtendedDataRecordClassList[] = { + { //FaultDetectionsNumber_Class + .RecordNumber = 4u, + .DataSize = 1u, + .UpdateRule = DEM_UPDATE_RECORD_YES, + .CallbackGetExtDataRecord = NULL, + .InternalDataElement = DEM_CONFIRMATIONCNTR, + }, + { //AgeingCounter_Class + .RecordNumber = 5u, + .DataSize = 1u, + .UpdateRule = DEM_UPDATE_RECORD_YES, + .CallbackGetExtDataRecord = NULL, + .InternalDataElement = DEM_AGINGCTR, + }, + { //FaultDetectionCounter_Class + .RecordNumber = 2u, + .DataSize = 1u, + .UpdateRule = DEM_UPDATE_RECORD_YES, + .CallbackGetExtDataRecord = NULL, + .InternalDataElement = DEM_FAULTDETCTR, + }, + { //UncompledTestCNT_class + .RecordNumber = 3u, + .DataSize = 1u, + .UpdateRule = DEM_UPDATE_RECORD_YES, + .CallbackGetExtDataRecord = NULL, + .InternalDataElement = DEM_OCCCTR, + }, + { //DTC_OccurrenceCounter_Class + .RecordNumber = 1u, + .DataSize = 1u, + .UpdateRule = DEM_UPDATE_RECORD_YES, + .CallbackGetExtDataRecord = NULL, + .InternalDataElement = DEM_OCCCTR, + }, +}; + + + +const Dem_ExtendedDataClassType DemExtendedDataClass = { + .ExtendedDataRecordClassRef = { + &ExtendedDataRecordClassList[DEM_EXT_DATA_REC_CLASS_AgeingCounter_Class_INDEX], + &ExtendedDataRecordClassList[DEM_EXT_DATA_REC_CLASS_FaultDetectionsNumber_Class_INDEX], + &ExtendedDataRecordClassList[DEM_EXT_DATA_REC_CLASS_FaultDetectionCounter_Class_INDEX], + &ExtendedDataRecordClassList[DEM_EXT_DATA_REC_CLASS_UncompledTestCNT_class_INDEX], + &ExtendedDataRecordClassList[DEM_EXT_DATA_REC_CLASS_DTC_OccurrenceCounter_Class_INDEX], + NULL, + } +}; + +/* Counter based predebounce */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_F00617_HIGH_VOLTAGE + * @desc calib param for predebounce counter for event F00617_HIGH_VOLTAGE (DTC: U3003A3_HighVoltage) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_F00617_HIGH_VOLTAGE) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_F00616_LOW_VOLTAGE + * @desc calib param for predebounce counter for event F00616_LOW_VOLTAGE (DTC: U3003A2_LowVoltage) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_F00616_LOW_VOLTAGE) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_A06600_TouErr + * @desc calib param for predebounce counter for event A06600_TouErr (DTC: P121061_Lever1Error) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_A06600_TouErr) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123312_P_BUTTON2_NOT_OK + * @desc calib param for predebounce counter for event P123312_P_BUTTON2_NOT_OK (DTC: P123312_PButton2NotOK) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123312_P_BUTTON2_NOT_OK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123311_P_BUTTON1_NOT_OK + * @desc calib param for predebounce counter for event P123311_P_BUTTON1_NOT_OK (DTC: P123311_PButton1NotOK) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123311_P_BUTTON1_NOT_OK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123313_P_BUTTON3_NOT_OK + * @desc calib param for predebounce counter for event P123313_P_BUTTON3_NOT_OK (DTC: P123313_PButton3NotOK) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123313_P_BUTTON3_NOT_OK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_U014600_GW_BCM_LOST + * @desc calib param for predebounce counter for event U014600_GW_BCM_LOST (DTC: U014600_GWBCMLost) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_U014600_GW_BCM_LOST) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_A06800_MorErr + * @desc calib param for predebounce counter for event A06800_MorErr (DTC: A06800_MorErr) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_A06800_MorErr) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_A06700_PressErr + * @desc calib param for predebounce counter for event A06700_PressErr (DTC: P121161_Lever2Error) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_A06700_PressErr) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_U010100_TCU_LOST + * @desc calib param for predebounce counter for event U010100_TCU_LOST (DTC: U010100_TCULost) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_U010100_TCU_LOST) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_C07300_BUS_OFF + * @desc calib param for predebounce counter for event C07300_BUS_OFF (DTC: U002888_BusOff) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_C07300_BUS_OFF) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P271F54_Calibration_Fault + * @desc calib param for predebounce counter for event P271F54_Calibration_Fault (DTC: P271F54_CalibrationFault) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P271F54_Calibration_Fault) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ + +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123411_L_BUTTON1_NOT_OK + * @desc calib param for predebounce counter for event P123411_L_BUTTON1_NOT_OK (DTC: P123411_LButton1NotOK) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123411_L_BUTTON1_NOT_OK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123412_L_BUTTON2_NOT_OK + * @desc calib param for predebounce counter for event P123412_L_BUTTON2_NOT_OK (DTC: P123412_LButton2NotOK) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123412_L_BUTTON2_NOT_OK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123511_L_BUTTON1_STUCK + * @desc calib param for predebounce counter for event P123511_L_BUTTON1_STUCK (DTC: P123511_LButton1Stucl) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123511_L_BUTTON1_STUCK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic DemPreDebounceCounterBased_P123512_L_BUTTON2_STUCK + * @desc calib param for predebounce counter for event P123512_L_BUTTON2_STUCK (DTC: P123512_LButton2Stuck) + * @struct_size 8 + * @field_name JumpUp + * @min 0 + * @max 1 + * @type uint8 + * @field_name JumpDown + * @min 0 + * @max 1 + * @type uint8 + * @field_name IncrementStepSize + * @min 0 + * @max 32767 + * @type uint16 + * @field_name DecrementStepSize + * @min 0 + * @max 32768 + * @type uint16 + * @field_name JumpDownValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name JumpUpValue + * @min -32768 + * @max 32767 + * @type sint16 + * @field_name FailedThreshold + * @min 0 + * @max 32767 + * @type sint16 + * @field_name PassedThreshold + * @min -32768 + * @max 0 + * @type sint16 + */ + /* +ARC_DECLARE_CALIB(const Dem_PreDebounceCounterBasedType, DemPreDebounceCounterBased_P123512_L_BUTTON2_STUCK) = { + .IncrementStepSize = 1, + .DecrementStepSize = 1, + .JumpDown = FALSE, + .JumpUp = FALSE, + .JumpDownValue = 0, + .JumpUpValue = 0, + .FailedThreshold = 127, + .PassedThreshold = -128, +}; +*/ +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/* Internal monitor */ + + +const Dem_PreDebounceAlgorithmClassType AlgoClass_F00617_HIGH_VOLTAGE = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_F00617_HIGH_VOLTAGE + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_F00616_LOW_VOLTAGE = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_F00616_LOW_VOLTAGE + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_A06600_TouErr = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_A06600_TouErr + } +}; +/* +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123312_P_BUTTON2_NOT_OK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123312_P_BUTTON2_NOT_OK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123311_P_BUTTON1_NOT_OK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123311_P_BUTTON1_NOT_OK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123313_P_BUTTON3_NOT_OK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123313_P_BUTTON3_NOT_OK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_U014600_GW_BCM_LOST = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_U014600_GW_BCM_LOST + } +}; +*/ +const Dem_PreDebounceAlgorithmClassType AlgoClass_A06800_MorErr = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_A06800_MorErr + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_A06700_PressErr = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_A06700_PressErr + } +}; +/* +const Dem_PreDebounceAlgorithmClassType AlgoClass_U010100_TCU_LOST = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_U010100_TCU_LOST + } +}; +*/ +const Dem_PreDebounceAlgorithmClassType AlgoClass_C07300_BUS_OFF = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_C07300_BUS_OFF + } +}; +/* +const Dem_PreDebounceAlgorithmClassType AlgoClass_P271F54_Calibration_Fault = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P271F54_Calibration_Fault + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123411_L_BUTTON1_NOT_OK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123411_L_BUTTON1_NOT_OK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123412_L_BUTTON2_NOT_OK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123412_L_BUTTON2_NOT_OK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123511_L_BUTTON1_STUCK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123511_L_BUTTON1_STUCK + } +}; +const Dem_PreDebounceAlgorithmClassType AlgoClass_P123512_L_BUTTON2_STUCK = { + .PreDebounceName = DEM_PRE_DEBOUNCE_COUNTER_BASED, + .PreDebounceAlgorithm = { + .PreDebounceCounterBased = &DemPreDebounceCounterBased_P123512_L_BUTTON2_STUCK + } +}; +*/ + +const Dem_PidOrDidType DemDidList[] = { + /* + { + .PidOrDidSize = 18, + .DidIdentifier = 4099u, + .DidReadFnc = Get_Internal_ADC_Info, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 8451u, + .DidReadFnc = Get_Actuator_Pos_Info, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 1281u, + .DidReadFnc = Get_Break_Status, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 4610u, + .DidReadFnc = Get_Ignition_Status, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 2, + .DidIdentifier = 45062u, + .DidReadFnc = Get_Mlx_Die2_Val, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 8448u, + .DidReadFnc = Get_GSM_GearPos_Info, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 8450u, + .DidReadFnc = Get_TCU_GearPos_Info, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 2, + .DidIdentifier = 45061u, + .DidReadFnc = Get_Mlx_Die1_Val, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 45059u, + .DidReadFnc = Get_LMC_MechPos_Info, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 45060u, + .DidReadFnc = Get_Pbutton_Status, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 1, + .DidIdentifier = 1536u, + .DidReadFnc = Get_ShieldOpDr_AutoP_Status, + .Arc_EOL = FALSE + }, + { + .PidOrDidSize = 2, + .DidIdentifier = 45057u, + .DidReadFnc = Get_PowerSupply, + .Arc_EOL = FALSE + }, + { + .Arc_EOL = TRUE + } + */ +}; + +const Dem_PidOrDidType DemPidList[] = { + { + .Arc_EOL = TRUE + } +}; + +const Dem_PidOrDidType * const DemFreezeFrameClass_didRefList[] = { + &DemDidList[DEM_DID_DID_PowerSupply_INDEX], + &DemDidList[DEM_DID_DID_ShiftMechPosInformation_INDEX], + &DemDidList[DEM_DID_DID_PbuttonStatus_INDEX], + &DemDidList[DEM_DID_DID_Mlx_Die1_Val_INDEX], + &DemDidList[DEM_DID_DID_Mlx_Die2_Val_INDEX], + &DemDidList[DEM_DID_LIST_EOL_INDEX] +}; + +const Dem_PidOrDidType * const OBDFreezeFrame_pidRefList[] = { + &DemPidList[DEM_PID_LIST_EOL_INDEX] +}; + + +const Dem_FreezeFrameClassType FreezeFrameClassList[] = { + { //DemFreezeFrameClass + .FFKind = DEM_FREEZE_FRAME_NON_OBD, + .FFIdClassRef = DemFreezeFrameClass_didRefList + }, +}; + + + +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * TODO: This is actually a structure but it only contains an array + * @a2l_characteristic DemFreezeFrameRecNumClass_FreezeFrameRecNumClass + * @desc freeze frame record numbers for record number class DemFreezeFrameRecNumClass (DTC: [F00617_HighVoltage, F00616_LowVoltage, A06600_TouErr, P123312_PButton2NotOK, P123311_PButton1NotOK, P123313_PButton3NotOK, U014600_GWBCMLost, A06800_MorErr, A06700_PressErr, U010100_TCULost, C07300_BusOff, P271F54_CalibrationFault, P123411_LButton1NotOK, P123412_LButton2NotOK, P123511_LButton1Stucl, P123512_LButton2Stuck] ) + * @scaling 1 + * @elements 2 + * @min 1 + * @max 255 + * @type uint8 + */ + /* @req DEM583 */ +ARC_DECLARE_CALIB(const Dem_FreezeFrameRecNumClass, DemFreezeFrameRecNumClass_FreezeFrameRecNumClass) = { + .FreezeFrameRecordNumber = { + 0x1u, + 0x2u, + DEM_FREEZEFRAME_RECORD_NUMBER_EOL + } +}; +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Arc_FailureCycleCounterThreshold NoFailure_FailureCycleCounter = { + .Threshold = 0u, +}; + +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic F00617_HIGH_VOLTAGE_FailureCycleCounter + * @desc failure cycle threshold for event F00617_HIGH_VOLTAGE (DTC: F00617_HighVoltage) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, F00617_HIGH_VOLTAGE_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic F00617_HIGH_VOLTAGE_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, F00617_HIGH_VOLTAGE_EventAvailable) = TRUE; +#else +boolean F00617_HIGH_VOLTAGE_EventAvailable = TRUE; /*lint -esym(843,F00617_HIGH_VOLTAGE_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType F00617_HIGH_VOLTAGE_DemEventClass = { + .EventAvailableByCalibration = &F00617_HIGH_VOLTAGE_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_F00617_HIGH_VOLTAGE, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &F00617_HIGH_VOLTAGE_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic F00616_LOW_VOLTAGE_FailureCycleCounter + * @desc failure cycle threshold for event F00616_LOW_VOLTAGE (DTC: U3003A2_LowVoltage) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, F00616_LOW_VOLTAGE_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic F00616_LOW_VOLTAGE_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, F00616_LOW_VOLTAGE_EventAvailable) = TRUE; +#else +boolean F00616_LOW_VOLTAGE_EventAvailable = TRUE; /*lint -esym(843,F00616_LOW_VOLTAGE_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType F00616_LOW_VOLTAGE_DemEventClass = { + .EventAvailableByCalibration = &F00616_LOW_VOLTAGE_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_F00616_LOW_VOLTAGE, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &F00616_LOW_VOLTAGE_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06600_TouErr_FailureCycleCounter + * @desc failure cycle threshold for event A06600_TouErr (DTC: A06600_TouErr) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, A06600_TouErr_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic A06600_TouErr_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, A06600_TouErr_EventAvailable) = TRUE; +#else +boolean A06600_TouErr_EventAvailable = TRUE; /*lint -esym(843,A06600_TouErr_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType A06600_TouErr_DemEventClass = { + .EventAvailableByCalibration = &A06600_TouErr_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_A06600_TouErr, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &A06600_TouErr_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter0_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter0_EventAvailable) = TRUE; +#else +boolean DemEventParameter0_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter0_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter0_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter0_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter1_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter1_EventAvailable) = TRUE; +#else +boolean DemEventParameter1_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter1_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter1_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter1_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter2_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter2_EventAvailable) = TRUE; +#else +boolean DemEventParameter2_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter2_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter2_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter2_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter3_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter3_EventAvailable) = TRUE; +#else +boolean DemEventParameter3_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter3_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter3_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter3_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter4_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter4_EventAvailable) = TRUE; +#else +boolean DemEventParameter4_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter4_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter4_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter4_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +/** + * @a2l_characteristic DemEventParameter5_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, DemEventParameter5_EventAvailable) = TRUE; +#else +boolean DemEventParameter5_EventAvailable = TRUE; /*lint -esym(843,DemEventParameter5_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType DemEventParameter5_DemEventClass = { + .EventAvailableByCalibration = &DemEventParameter5_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_NOT_USED, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = NULL, + .AgingAllowed = FALSE, + .AgingCycleCounterThreshold = 0u, + .AgingCycleRef = DEM_ACTIVE, /* Not used */ + .FailureCycleRef= DEM_OPERATION_CYCLE_ID_ENDMARK, + .FailureCycleCounterThresholdRef = &NoFailure_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123312_P_BUTTON2_NOT_OK_FailureCycleCounter + * @desc failure cycle threshold for event P123312_P_BUTTON2_NOT_OK (DTC: P123312_PButton2NotOK) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ + /* +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123312_P_BUTTON2_NOT_OK_FailureCycleCounter) = { + .Threshold = 1u, +}; +*/ +/** + * @a2l_characteristic P123312_P_BUTTON2_NOT_OK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123312_P_BUTTON2_NOT_OK_EventAvailable) = TRUE; +#else +//boolean P123312_P_BUTTON2_NOT_OK_EventAvailable = TRUE; /*lint -esym(843,P123312_P_BUTTON2_NOT_OK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123312_P_BUTTON2_NOT_OK_DemEventClass = { + .EventAvailableByCalibration = &P123312_P_BUTTON2_NOT_OK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123312_P_BUTTON2_NOT_OK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P123312_P_BUTTON2_NOT_OK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123311_P_BUTTON1_NOT_OK_FailureCycleCounter + * @desc failure cycle threshold for event P123311_P_BUTTON1_NOT_OK (DTC: P123311_PButton1NotOK) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123311_P_BUTTON1_NOT_OK_FailureCycleCounter) = { + //.Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123311_P_BUTTON1_NOT_OK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123311_P_BUTTON1_NOT_OK_EventAvailable) = TRUE; +#else +//boolean P123311_P_BUTTON1_NOT_OK_EventAvailable = TRUE; /*lint -esym(843,P123311_P_BUTTON1_NOT_OK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123311_P_BUTTON1_NOT_OK_DemEventClass = { + .EventAvailableByCalibration = &P123311_P_BUTTON1_NOT_OK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123311_P_BUTTON1_NOT_OK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P123311_P_BUTTON1_NOT_OK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123313_P_BUTTON3_NOT_OK_FailureCycleCounter + * @desc failure cycle threshold for event P123313_P_BUTTON3_NOT_OK (DTC: P123313_PButton3NotOK) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123313_P_BUTTON3_NOT_OK_FailureCycleCounter) = { + //.Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123313_P_BUTTON3_NOT_OK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123313_P_BUTTON3_NOT_OK_EventAvailable) = TRUE; +#else +//boolean P123313_P_BUTTON3_NOT_OK_EventAvailable = TRUE; /*lint -esym(843,P123313_P_BUTTON3_NOT_OK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123313_P_BUTTON3_NOT_OK_DemEventClass = { + .EventAvailableByCalibration = &P123313_P_BUTTON3_NOT_OK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123313_P_BUTTON3_NOT_OK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P123313_P_BUTTON3_NOT_OK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic U014600_GW_BCM_LOST_FailureCycleCounter + * @desc failure cycle threshold for event U014600_GW_BCM_LOST (DTC: U014600_GWBCMLost) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, U014600_GW_BCM_LOST_FailureCycleCounter) = { +// .Threshold = 1u, +//}; + +/** + * @a2l_characteristic U014600_GW_BCM_LOST_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, U014600_GW_BCM_LOST_EventAvailable) = TRUE; +#else +//boolean U014600_GW_BCM_LOST_EventAvailable = TRUE; /*lint -esym(843,U014600_GW_BCM_LOST_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType U014600_GW_BCM_LOST_DemEventClass = { + .EventAvailableByCalibration = &U014600_GW_BCM_LOST_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_U014600_GW_BCM_LOST, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &U014600_GW_BCM_LOST_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06800_MorErr_FailureCycleCounter + * @desc failure cycle threshold for event A06800_MorErr (DTC: P121261_LeverAllError) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, A06800_MorErr_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic A06800_MorErr_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, A06800_MorErr_EventAvailable) = TRUE; +#else +boolean A06800_MorErr_EventAvailable = TRUE; /*lint -esym(843,A06800_MorErr_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType A06800_MorErr_DemEventClass = { + .EventAvailableByCalibration = &A06800_MorErr_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_A06800_MorErr, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &A06800_MorErr_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; + +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic A06700_PressErr_FailureCycleCounter + * @desc failure cycle threshold for event A06700_PressErr (DTC: A06700_PressErr) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, A06700_PressErr_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic A06700_PressErr_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, A06700_PressErr_EventAvailable) = TRUE; +#else +boolean A06700_PressErr_EventAvailable = TRUE; /*lint -esym(843,P121161_LEVER2_ERROR_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType A06700_PressErr_DemEventClass = { + .EventAvailableByCalibration = &A06700_PressErr_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_A06700_PressErr, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &A06700_PressErr_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic U010100_TCU_LOST_FailureCycleCounter + * @desc failure cycle threshold for event U010100_TCU_LOST (DTC: U010100_TCULost) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, U010100_TCU_LOST_FailureCycleCounter) = { +// .Threshold = 1u, +//}; + +/** + * @a2l_characteristic U010100_TCU_LOST_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, U010100_TCU_LOST_EventAvailable) = TRUE; +#else +//boolean U010100_TCU_LOST_EventAvailable = TRUE; /*lint -esym(843,U010100_TCU_LOST_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType U010100_TCU_LOST_DemEventClass = { + .EventAvailableByCalibration = &U010100_TCU_LOST_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_U010100_TCU_LOST, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &U010100_TCU_LOST_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic C07300_BUS_OFF_FailureCycleCounter + * @desc failure cycle threshold for event C07300_BUS_OFF (DTC: U002888_BusOff) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, C07300_BUS_OFF_FailureCycleCounter) = { + .Threshold = 1u, +}; + +/** + * @a2l_characteristic C07300_BUS_OFF_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +ARC_DECLARE_CALIB(const boolean, C07300_BUS_OFF_EventAvailable) = TRUE; +#else +boolean C07300_BUS_OFF_EventAvailable = TRUE; /*lint -esym(843,C07300_BUS_OFF_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ + +const Dem_EventClassType C07300_BUS_OFF_DemEventClass = { + .EventAvailableByCalibration = &C07300_BUS_OFF_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, /* Value is not configurable */ + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_C07300_BUS_OFF, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &C07300_BUS_OFF_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P271F54_Calibration_Fault_FailureCycleCounter + * @desc failure cycle threshold for event P271F54_Calibration_Fault (DTC: P271F54_CalibrationFault) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P271F54_Calibration_Fault_FailureCycleCounter) = { + //.Threshold = 1u, +//}; + +/** + * @a2l_characteristic P271F54_Calibration_Fault_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P271F54_Calibration_Fault_EventAvailable) = TRUE; +#else +//boolean P271F54_Calibration_Fault_EventAvailable = TRUE; /*lint -esym(843,P271F54_Calibration_Fault_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P271F54_Calibration_Fault_DemEventClass = { + .EventAvailableByCalibration = &P271F54_Calibration_Fault_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P271F54_Calibration_Fault, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P271F54_Calibration_Fault_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123411_L_BUTTON1_NOT_OK_FailureCycleCounter + * @desc failure cycle threshold for event P123411_L_BUTTON1_NOT_OK (DTC: P123411_LButton1NotOK) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123411_L_BUTTON1_NOT_OK_FailureCycleCounter) = { +// .Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123411_L_BUTTON1_NOT_OK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123411_L_BUTTON1_NOT_OK_EventAvailable) = TRUE; +#else +//boolean P123411_L_BUTTON1_NOT_OK_EventAvailable = TRUE; /*lint -esym(843,P123411_L_BUTTON1_NOT_OK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123411_L_BUTTON1_NOT_OK_DemEventClass = { + .EventAvailableByCalibration = &P123411_L_BUTTON1_NOT_OK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123411_L_BUTTON1_NOT_OK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P123411_L_BUTTON1_NOT_OK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123412_L_BUTTON2_NOT_OK_FailureCycleCounter + * @desc failure cycle threshold for event P123412_L_BUTTON2_NOT_OK (DTC: P123412_LButton2NotOK) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123412_L_BUTTON2_NOT_OK_FailureCycleCounter) = { + //.Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123412_L_BUTTON2_NOT_OK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123412_L_BUTTON2_NOT_OK_EventAvailable) = TRUE; +#else +//boolean P123412_L_BUTTON2_NOT_OK_EventAvailable = TRUE; /*lint -esym(843,P123412_L_BUTTON2_NOT_OK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123412_L_BUTTON2_NOT_OK_DemEventClass = { + //.EventAvailableByCalibration = &P123412_L_BUTTON2_NOT_OK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123412_L_BUTTON2_NOT_OK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + //.FailureCycleCounterThresholdRef = &P123412_L_BUTTON2_NOT_OK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123511_L_BUTTON1_STUCK_FailureCycleCounter + * @desc failure cycle threshold for event P123511_L_BUTTON1_STUCK (DTC: P123511_LButton1Stucl) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123511_L_BUTTON1_STUCK_FailureCycleCounter) = { +// .Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123511_L_BUTTON1_STUCK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123511_L_BUTTON1_STUCK_EventAvailable) = TRUE; +#else +//boolean P123511_L_BUTTON1_STUCK_EventAvailable = TRUE; /*lint -esym(843,P123511_L_BUTTON1_STUCK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123511_L_BUTTON1_STUCK_DemEventClass = { + .EventAvailableByCalibration = &P123511_L_BUTTON1_STUCK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123511_L_BUTTON1_STUCK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + //.FailureCycleCounterThresholdRef = &P123511_L_BUTTON1_STUCK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ +#define Dem_START_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/** + * @a2l_characteristic P123512_L_BUTTON2_STUCK_FailureCycleCounter + * @desc failure cycle threshold for event P123512_L_BUTTON2_STUCK (DTC: P123512_LButton2Stuck) + * @scaling 1 + * @struct_size 1 + * @field_name DemEventFailureCycleCounterThreshold + * @min 0 + * @max 255 + * @type uint8 + */ +//ARC_DECLARE_CALIB(const Arc_FailureCycleCounterThreshold, P123512_L_BUTTON2_STUCK_FailureCycleCounter) = { + //.Threshold = 1u, +//}; + +/** + * @a2l_characteristic P123512_L_BUTTON2_STUCK_EventAvailable + * @desc Determines if event is available or not + * @scaling 1 + * @min 0 + * @max 1 + * @type uint8 + */ + #if !defined(HOST_TEST) +//ARC_DECLARE_CALIB(const boolean, P123512_L_BUTTON2_STUCK_EventAvailable) = TRUE; +#else +//boolean P123512_L_BUTTON2_STUCK_EventAvailable = TRUE; /*lint -esym(843,P123512_L_BUTTON2_STUCK_EventAvailable) not declared as const for HOST_TEST only */ +#endif +#define Dem_STOP_SEC_CALIB_UNSPECIFIED +//#include "Dem_MemMap.h" /*lint !e9019 suppressed due to Dem_MemMap.h include is required */ +/* +const Dem_EventClassType P123512_L_BUTTON2_STUCK_DemEventClass = { + .EventAvailableByCalibration = &P123512_L_BUTTON2_STUCK_EventAvailable, + .ConsiderPtoStatus = FALSE, + .EventDestination = DEM_DTC_ORIGIN_PRIMARY_MEMORY, + .IndicatorAttribute = NULL, + .EventPriority = 1u, + .FFPrestorageSupported = FALSE, + .OperationCycleRef = DEM_ACTIVE, + .PreDebounceAlgorithmClass = &AlgoClass_P123512_L_BUTTON2_STUCK, + .AgingAllowed = TRUE, + .AgingCycleCounterThreshold = 40u, + .AgingCycleRef = DEM_ACTIVE, + .FailureCycleRef = DEM_ACTIVE, + .FailureCycleCounterThresholdRef = &P123512_L_BUTTON2_STUCK_FailureCycleCounter, + .EnableConditionGroupRef = NULL +}; +*/ + +const Dem_EventParameterType EventParameterList[] = { + { + //.EventID = DemConf_DemEventParameter_DemEventParameter0, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter0_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + //.EventID = DemConf_DemEventParameter_DemEventParameter1, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter1_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + //.EventID = DemConf_DemEventParameter_DemEventParameter2, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter2_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + //.EventID = DemConf_DemEventParameter_DemEventParameter3, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter3_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + //.EventID = DemConf_DemEventParameter_DemEventParameter4, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter4_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + //.EventID = DemConf_DemEventParameter_DemEventParameter5, + .EventKind = DEM_EVENT_KIND_BSW, + .EventClass = &DemEventParameter5_DemEventClass, + .ExtendedDataClassRef = NULL, + .FreezeFrameClassRef = NULL, + .MaxNumberFreezeFrameRecords = 0u, + .FreezeFrameRecNumClassRef = NULL, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = NULL, + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_F00617_HIGH_VOLTAGE, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &F00617_HIGH_VOLTAGE_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_F00617_HighVoltage_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_F00616_LOW_VOLTAGE, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &F00616_LOW_VOLTAGE_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_F00616_LowVoltage_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_A06600_TouErr, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &A06600_TouErr_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_A06600_TouErr_INDEX], + .Arc_EOL = FALSE + }, + /* + { + .EventID = DemConf_DemEventParameter_P123312_P_BUTTON2_NOT_OK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123312_P_BUTTON2_NOT_OK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123312_PButton2NotOK_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_P123311_P_BUTTON1_NOT_OK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123311_P_BUTTON1_NOT_OK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123311_PButton1NotOK_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_P123313_P_BUTTON3_NOT_OK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123313_P_BUTTON3_NOT_OK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123313_PButton3NotOK_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_U014600_GW_BCM_LOST, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &U014600_GW_BCM_LOST_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_U014600_GWBCMLost_INDEX], + .Arc_EOL = FALSE + }, + */ + + { + .EventID = DemConf_DemEventParameter_A06800_MorErr, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &A06800_MorErr_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_A06800_MorErr_INDEX], + .Arc_EOL = FALSE + }, + + { + .EventID = DemConf_DemEventParameter_A06700_PressErr, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &A06700_PressErr_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_A06700_PressErr_INDEX], + .Arc_EOL = FALSE + }, + /* + { + .EventID = DemConf_DemEventParameter_U010100_TCU_LOST, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &U010100_TCU_LOST_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_U010100_TCULost_INDEX], + .Arc_EOL = FALSE + }, + */ + { + .EventID = DemConf_DemEventParameter_C07300_BUS_OFF, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &C07300_BUS_OFF_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_C07300_BusOff_INDEX], + .Arc_EOL = FALSE + }, + /* + { + .EventID = DemConf_DemEventParameter_P271F54_Calibration_Fault, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P271F54_Calibration_Fault_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P271F54_CalibrationFault_INDEX], + .Arc_EOL = FALSE + }, + + { + .EventID = DemConf_DemEventParameter_P123411_L_BUTTON1_NOT_OK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123411_L_BUTTON1_NOT_OK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123411_LButton1NotOK_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_P123412_L_BUTTON2_NOT_OK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123412_L_BUTTON2_NOT_OK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123412_LButton2NotOK_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_P123511_L_BUTTON1_STUCK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123511_L_BUTTON1_STUCK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123511_LButton1Stucl_INDEX], + .Arc_EOL = FALSE + }, + { + .EventID = DemConf_DemEventParameter_P123512_L_BUTTON2_STUCK, + .EventKind = DEM_EVENT_KIND_SWC, + .EventClass = &P123512_L_BUTTON2_STUCK_DemEventClass, + .ExtendedDataClassRef = &DemExtendedDataClass, + .MaxNumberFreezeFrameRecords = 2, + .FreezeFrameClassRef = &FreezeFrameClassList[DEM_FF_DemFreezeFrameClass_INDEX], + //.FreezeFrameRecNumClassRef = &DemFreezeFrameRecNumClass_FreezeFrameRecNumClass, + .CallbackInitMforE = NULL, + .CallbackEventStatusChanged = NULL, + .CallbackClearEventAllowed = NULL, + .CallbackEventDataChanged = NULL, + .DTCClassRef = &DtcClassList[DEM_DTC_P123512_LButton2Stuck_INDEX], + .Arc_EOL = FALSE + }, + */ + { + .Arc_EOL = TRUE + } +}; + + +const Dem_GroupOfDtcType DemDtcGroups[] = { + { + .DemGroupDTCs = 0x0UL, + .Arc_EOL = FALSE + }, + { + .DemGroupDTCs = 0xFFFFFFUL, + .Arc_EOL = TRUE + } +}; + +const Dem_ConfigSetType DEM_ConfigSet = { + .EventParameter = EventParameterList, + .DTCClass = DtcClassList, + .GlobalOBDFreezeFrameClassRef = NULL, + .Indicators = NULL, +#if (DEM_ENABLE_CONDITION_SUPPORT == STD_ON) + .EnableCondition = DemEnableConditionList, +#endif + .GroupOfDtc = DemDtcGroups +}; + + +const Dem_ConfigType DEM_Config = { + .ConfigSet = &DEM_ConfigSet, +}; + diff --git a/firmware/src/DiagnosticR/Dem/Dem_Lcfg.h b/firmware/src/DiagnosticR/Dem/Dem_Lcfg.h new file mode 100644 index 0000000..11b3f60 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Lcfg.h @@ -0,0 +1,313 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef DEM_LCFG_H_ +#define DEM_LCFG_H_ +#include "Dem_Types.h" +#include "DiagnosticR/rte/Rte_Dem_Type.h" +#include "DiagnosticR/Dem/Dem_Cfg.h" +#if defined(USE_DCM) +#include "Dcm_Types.h" /** @req DEM176.Dcm */ +#endif + +/* + * Callback function prototypes + */ + +// ClearEventAllowed +typedef Std_ReturnType (*Dem_CallbackClearEventAllowedFncType)(boolean *Allowed); /* @req DEM563 */ + +// EventDataChanged +typedef Std_ReturnType (*Dem_CallbackEventDataChangedFncTypeWithId)(Dem_EventIdType EventId);/* @req DEM562 */ +typedef Std_ReturnType (*Dem_CallbackEventDataChangedFncTypeWithoutId)(void); + + +typedef union { + Dem_CallbackEventDataChangedFncTypeWithId eventDataChangedWithId; + Dem_CallbackEventDataChangedFncTypeWithoutId eventDataChangedWithoutId; +}Dem_CallbackEventDataChangedFncType; + +typedef struct { + boolean UsePort; + Dem_CallbackEventDataChangedFncType CallbackEventDataChangedFnc; +}Dem_CallbackEventDataChangedType; + +// InitMonitorForEvent +typedef Std_ReturnType (*Dem_CallbackInitMonitorForEventFncType)(Dem_InitMonitorReasonType InitMonitorReason); /** @req DEM256 *//** @req DEM376 *//** @req DEM003 */ + +// InitMonitorForFunction +typedef Std_ReturnType (*Dem_CallbackInitMonitorForFunctionFncType)(void); /** !req DEM258 */ + +// EventStatusChanged +typedef Std_ReturnType (*Dem_CallbackEventStatusChangedFncTypeWithId)(Dem_EventIdType EventId, Dem_EventStatusExtendedType EventStatusOld, Dem_EventStatusExtendedType EventStatusNew); /** @req DEM259 */ +typedef Std_ReturnType (*Dem_CallbackEventStatusChangedFncTypeWithoutId)(Dem_EventStatusExtendedType EventStatusOld, Dem_EventStatusExtendedType EventStatusNew); /** @req DEM259 */ + +typedef union { + Dem_CallbackEventStatusChangedFncTypeWithId eventStatusChangedWithId; + Dem_CallbackEventStatusChangedFncTypeWithoutId eventStatusChangedWithoutId; +}Dem_CallbackEventStatusChangedFncType; + +// DTCStatusChanged +typedef Std_ReturnType (*Dem_CallbackDTCStatusChangedFncType)(uint8 DTCStatusOld, uint8 DTCStatusNew); /** !req DEM260 */ + +// DIDServices /** @req DEM261 *//* */ +typedef Std_ReturnType (*Dem_CallbackReadDataFncType)(uint8 *Data);/* @req DEM564 */ + +// GetFaultDetectionCounter +typedef Std_ReturnType (*Dem_CallbackGetFaultDetectionCounterFncType)(sint8 *EventIdFaultDetectionCounter); /** @req DEM263 */ + +typedef uint8 Dem_InternalDataElementType; +#define DEM_NO_ELEMENT 0u +#define DEM_OCCCTR 1u +#define DEM_FAULTDETCTR 2u +#define DEM_MAXFAULTDETCTR 3u +#define DEM_CONFIRMATIONCNTR 4u +#define DEM_AGINGCTR 5u +#define DEM_OVFLIND 6u + +typedef enum { + DEM_UPDATE_RECORD_NO, + DEM_UPDATE_RECORD_YES, + DEM_UPDATE_RECORD_VOLATILE, +} Dem_UpdateRuleType; +/* + * DemGeneral types + */ + +// 10.2.25 DemEnableCondition +typedef struct { + boolean EnableConditionStatus; // + uint8 EnableConditionID; // Optional +} Dem_EnableConditionType; + +typedef struct { + uint8 nofEnableConditions; + const Dem_EnableConditionType * const *EnableCondition; +}Dem_EnableConditionGroupType; + +// 10.2.30 DemExtendedDataRecordClass +typedef struct { + uint8 RecordNumber; // (1) + uint16 DataSize; // (1) + Dem_UpdateRuleType UpdateRule; /* @req DEM466 */ + Dem_CallbackReadDataFncType CallbackGetExtDataRecord; // (1) + Dem_InternalDataElementType InternalDataElement; /* @req DEM469 */ +} Dem_ExtendedDataRecordClassType; + +// 10.2.13 DemExtendedDataClass +typedef struct { + const Dem_ExtendedDataRecordClassType *const ExtendedDataRecordClassRef[DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA+1]; // (1..253) +} Dem_ExtendedDataClassType; + +// 10.2.8 DemPidOrDid +typedef struct { + const uint16 DidIdentifier; // (0..1) + Dem_CallbackReadDataFncType DidReadFnc; // (0..1) + const uint8 PidIdentifier; // (0..1) + uint8 PidOrDidSize; // (1) + boolean PidOrDidUsePort; // (1) Not used in current implementation + Dem_CallbackReadDataFncType PidReadFnc; // (0..1) + boolean Arc_EOL; +} Dem_PidOrDidType; + +// 10.2.18 DemFreezeFrameClass +typedef struct { + Dem_FreezeFrameKindType FFKind; // (1) + const Dem_PidOrDidType * const * FFIdClassRef; // (1..255)/** @req DEM039 *//** @req DEM040 */ +} Dem_FreezeFrameClassType; + +/* + * DemConfigSetType types + */ + +// 10.2.6 DemCallbackDTCStatusChanged +typedef struct { + Dem_CallbackDTCStatusChangedFncType CallbackDTCStatusChangedFnc; // (0..1) +} Dem_CallbackDTCStatusChangedType; + +// 10.2.26 DemCallbackInitMForF +typedef struct { + Dem_CallbackInitMonitorForFunctionFncType CallbackInitMForF; // (0..1) +} Dem_CallbackInitMForFType; + +// 10.2.17 DemDTCClass +typedef struct { +#if defined(HOST_TEST) + Arc_Dem_DTC *DTCRef; // (1) +#else + const Arc_Dem_DTC *DTCRef; // (1) +#endif +#if (DEM_DTC_SUPPRESSION_SUPPORT == STD_ON) + uint16 DTCIndex; // Index of the DTC + const Dem_EventIdType *Events; // List of events referencing DTC + uint16 NofEvents; // Number of events referencing DTC +#endif + Dem_DTCKindType DTCKind; // (1) +// const Dem_CallbackDTCStatusChangedType *CallbackDTCStatusChanged; // (0..*) +// const Dem_CallbackInitMForFType *CallbackInitMForF; // (0..*) + Dem_DTCSeverityType DTCSeverity; // (0..1) Optional /* @req DEM033 */ + boolean Arc_EOL; +} Dem_DTCClassType; + +// 10.2.5 DemCallbackEventStatusChanged +typedef struct { + Dem_CallbackEventStatusChangedFncType CallbackEventStatusChangedFnc; // (0..1) + boolean UsePort; + boolean Arc_EOL; +} Dem_CallbackEventStatusChangedType; + + +typedef enum { + DEM_FAILURE_CYCLE_EVENT = 0, + DEM_FAILURE_CYCLE_INDICATOR +}DemIndicatorFailureSourceType; + +typedef struct { + uint16 IndicatorBufferIndex; + uint8 IndicatorId; + Dem_IndicatorStatusType IndicatorBehaviour;/* @req DEM511 */ + uint8 IndicatorFailureCycleThreshold;/* @req DEM500 */ + Dem_OperationCycleStateType IndicatorFailureCycle;/* @req DEM504 */ + uint8 IndicatorHealingCycleThreshold; + Dem_OperationCycleStateType IndicatorHealingCycle; + DemIndicatorFailureSourceType IndicatorFailureCycleSource; + boolean Arc_EOL; +} Dem_IndicatorAttributeType; + +// 10.2.23 DemPreDebounceMonitorInternal +typedef struct { + Dem_CallbackGetFaultDetectionCounterFncType CallbackGetFDCntFnc; // (1) +} Dem_PreDebounceMonitorInternalType; + +// 10.2.22 DemPreDebounceFrequencyBased +typedef uint8 Dem_PreDebounceFrequencyBasedType; + +// 10.2.24 DemPreDebounceTimeBased +typedef struct{ + uint32 TimeFailedThreshold; + uint32 TimePassedThreshold; + uint16 Index; +}Dem_PreDebounceTimeBasedType; + +// 10.2.20 +typedef struct { + Dem_PreDebounceNameType PreDebounceName; // (1) + union { + const Dem_PreDebounceMonitorInternalType *PreDebounceMonitorInternal; // (0..1) + const Dem_PreDebounceCounterBasedType *PreDebounceCounterBased; // (0..1) + const Dem_PreDebounceFrequencyBasedType *PreDebounceFrequencyBased; // (0..1) + const Dem_PreDebounceTimeBasedType *PreDebounceTimeBased; // (0..1) + } PreDebounceAlgorithm; +} Dem_PreDebounceAlgorithmClassType; + +typedef struct { + uint8 Threshold; +} Arc_FailureCycleCounterThreshold; + +// 10.2.14 DemEventClass +typedef struct { + const Arc_FailureCycleCounterThreshold *FailureCycleCounterThresholdRef; // (1) /* @req DEM529 */ + const Dem_EnableConditionGroupType *EnableConditionGroupRef; // (0..*) Optional /* @req DEM446 */ + const Dem_PreDebounceAlgorithmClassType *PreDebounceAlgorithmClass; // (0..255) (Only 0..1 supported) /* @req DEM413 */ + const Dem_IndicatorAttributeType *IndicatorAttribute; // (0..255) + const boolean *EventAvailableByCalibration; + boolean ConsiderPtoStatus; // (1) + Dem_DTCOriginType EventDestination; // (1 Arccore specific) + uint8 EventPriority; // (1) /* @req DEM382 */ + boolean FFPrestorageSupported; // (1) + boolean AgingAllowed; // (1) + Dem_OperationCycleIdType OperationCycleRef; // (1) + Dem_OperationCycleIdType AgingCycleRef; // (1) /* @req DEM494 */ + Dem_OperationCycleIdType FailureCycleRef; // (1) /* @req DEM528 */ + uint8 AgingCycleCounterThreshold; // (0..1) Optional /* @req DEM493 */ +// Dem_OEMSPecific +} Dem_EventClassType; + +typedef struct +{ + uint8 FreezeFrameRecordNumber[DEM_MAX_RECORD_NUMBERS_IN_FF_REC_NUM_CLASS + 1]; +}Dem_FreezeFrameRecNumClass; + +// 10.2.12 DemEventParameter +typedef struct { + uint16 EventID; // (1) + Dem_EventKindType EventKind; // (1) + uint8 MaxNumberFreezeFrameRecords; // (1) /* @req DEM337 *//* @req DEM582 */ + const Dem_EventClassType *EventClass; // (1) + const Dem_ExtendedDataClassType *ExtendedDataClassRef; // (0..1) /* @req DEM460 */ + const Dem_FreezeFrameClassType *FreezeFrameClassRef; // (0..1) /* @req DEM460 */ + const Dem_CallbackInitMonitorForEventFncType CallbackInitMforE; // (0..1) + const Dem_CallbackEventStatusChangedType *CallbackEventStatusChanged; // (0..) + const Dem_CallbackClearEventAllowedFncType CallbackClearEventAllowed; // (0..1) + const Dem_CallbackEventDataChangedType *CallbackEventDataChanged; // (0..1) + const Dem_DTCClassType *DTCClassRef; // (0..1) + const Dem_FreezeFrameRecNumClass *FreezeFrameRecNumClassRef; // (1) + boolean Arc_EOL; +} Dem_EventParameterType; + + +typedef struct { + uint8 EventListSize; + const Dem_EventIdType *EventList; +}Dem_IndicatorType; + +// 10.2.19 DemGroupOfDTC +typedef struct { + uint32 DemGroupDTCs; + boolean Arc_EOL; +}Dem_GroupOfDtcType; + +// 10.2.9 DemConfigSet +typedef struct { + const Dem_EventParameterType *EventParameter; // (0..65535) + const Dem_DTCClassType *DTCClass; // (1..16777214) + const Dem_GroupOfDtcType *GroupOfDtc; + const Dem_EnableConditionType *EnableCondition; + const Dem_FreezeFrameClassType *GlobalOBDFreezeFrameClassRef;/* @req DEM291 */ + const Dem_IndicatorType *Indicators; +} Dem_ConfigSetType; + +// 10.2.2 Dem +typedef struct { + const Dem_ConfigSetType *ConfigSet; // (1) +} Dem_ConfigType; + +/* ****************************************************************************************************** + * WARNING: DO NOT CHANGE THESE STRUCTURES WITHOUT UPDATED THE DEM GENERATOR!! + * ******************************************************************************************************/ +typedef struct { +#if (DEM_EVENT_DISPLACEMENT_SUPPORT == STD_ON) && defined(DEM_DISPLACEMENT_PROCESSING_DEM_INTERNAL) + uint32 timeStamp; +#endif + uint16 dataSize; + Dem_EventIdType eventId; + Dem_FreezeFrameKindType kind; + uint8 recordNumber; + uint8 data[DEM_MAX_SIZE_FF_DATA]; +} FreezeFrameRecType; + +// Types for storing different event aging counter +typedef struct { + Dem_EventIdType eventId; + uint8 agingCounter;/** @req Dem019 */ +} HealingRecType; +/* ****************************************************************************************************** + * + * ******************************************************************************************************/ +/* + * Make the DEM_Config visible for others. + */ +extern const Dem_ConfigType DEM_Config; + +#endif /*DEM_LCFG_H_*/ diff --git a/firmware/src/DiagnosticR/Dem/Dem_Types.h b/firmware/src/DiagnosticR/Dem/Dem_Types.h new file mode 100644 index 0000000..298d542 --- /dev/null +++ b/firmware/src/DiagnosticR/Dem/Dem_Types.h @@ -0,0 +1,419 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + + +#ifndef DEM_TYPES_H_ +#define DEM_TYPES_H_ +#include "Std_Types.h" /** @req DEM176.Std */ +//#include "Rte_Dem_Type.h" + +/** Enum literals for Dem_DTCFormatType */ +#ifndef DEM_DTC_FORMAT_OBD +#define DEM_DTC_FORMAT_OBD 0U +#endif /* DEM_DTC_FORMAT_OBD */ + +#ifndef DEM_DTC_FORMAT_UDS +#define DEM_DTC_FORMAT_UDS 1U +#endif /* DEM_DTC_FORMAT_UDS */ + +/** Enum literals for Dem_DTCOriginType */ +#ifndef DEM_DTC_ORIGIN_NOT_USED +#define DEM_DTC_ORIGIN_NOT_USED 0U +#endif /* DEM_DTC_ORIGIN_NOT_USED */ + +#ifndef DEM_DTC_ORIGIN_PRIMARY_MEMORY +#define DEM_DTC_ORIGIN_PRIMARY_MEMORY 1U +#endif /* DEM_DTC_ORIGIN_PRIMARY_MEMORY */ + +#ifndef DEM_DTC_ORIGIN_MIRROR_MEMORY +#define DEM_DTC_ORIGIN_MIRROR_MEMORY 2U +#endif /* DEM_DTC_ORIGIN_MIRROR_MEMORY */ + +#ifndef DEM_DTC_ORIGIN_PERMANENT_MEMORY +#define DEM_DTC_ORIGIN_PERMANENT_MEMORY 3U +#endif /* DEM_DTC_ORIGIN_PERMANENT_MEMORY */ + +#ifndef DEM_DTC_ORIGIN_SECONDARY_MEMORY +#define DEM_DTC_ORIGIN_SECONDARY_MEMORY 4U +#endif /* DEM_DTC_ORIGIN_SECONDARY_MEMORY */ + +/** Enum literals for Dem_EventStatusExtendedType */ +#ifndef DEM_TEST_FAILED +#define DEM_TEST_FAILED 1U +#endif /* DEM_TEST_FAILED */ + +#ifndef DEM_TEST_FAILED_THIS_OPERATION_CYCLE +#define DEM_TEST_FAILED_THIS_OPERATION_CYCLE 2U +#endif /* DEM_TEST_FAILED_THIS_OPERATION_CYCLE */ + +#ifndef DEM_PENDING_DTC +#define DEM_PENDING_DTC 4U +#endif /* DEM_PENDING_DTC */ + +#ifndef DEM_CONFIRMED_DTC +#define DEM_CONFIRMED_DTC 8U +#endif /* DEM_CONFIRMED_DTC */ + +#ifndef DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR +#define DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR 16U +#endif /* DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR */ + +#ifndef DEM_TEST_FAILED_SINCE_LAST_CLEAR +#define DEM_TEST_FAILED_SINCE_LAST_CLEAR 32U +#endif /* DEM_TEST_FAILED_SINCE_LAST_CLEAR */ + +#ifndef DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE +#define DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE 64U +#endif /* DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE */ + +#ifndef DEM_WARNING_INDICATOR_REQUESTED +#define DEM_WARNING_INDICATOR_REQUESTED 128U +#endif /* DEM_WARNING_INDICATOR_REQUESTED */ + +/** Enum literals for Dem_EventStatusType */ +#ifndef DEM_EVENT_STATUS_PASSED +#define DEM_EVENT_STATUS_PASSED 0U +#endif /* DEM_EVENT_STATUS_PASSED */ + +#ifndef DEM_EVENT_STATUS_FAILED +#define DEM_EVENT_STATUS_FAILED 1U +#endif /* DEM_EVENT_STATUS_FAILED */ + +#ifndef DEM_EVENT_STATUS_PREPASSED +#define DEM_EVENT_STATUS_PREPASSED 2U +#endif /* DEM_EVENT_STATUS_PREPASSED */ + +#ifndef DEM_EVENT_STATUS_PREFAILED +#define DEM_EVENT_STATUS_PREFAILED 3U +#endif /* DEM_EVENT_STATUS_PREFAILED */ + +/** Enum literals for Dem_OperationCycleStateType */ +#ifndef DEM_CYCLE_STATE_START +#define DEM_CYCLE_STATE_START 0U +#endif /* DEM_CYCLE_STATE_START */ + +#ifndef DEM_CYCLE_STATE_END +#define DEM_CYCLE_STATE_END 1U +#endif /* DEM_CYCLE_STATE_END */ + +/** Enum literals for Dem_ReturnClearDTCType */ +#ifndef DEM_CLEAR_OK +#define DEM_CLEAR_OK 0U +#endif /* DEM_CLEAR_OK */ + +#ifndef DEM_CLEAR_WRONG_DTC +#define DEM_CLEAR_WRONG_DTC 1U +#endif /* DEM_CLEAR_WRONG_DTC */ + +#ifndef DEM_CLEAR_WRONG_DTCORIGIN +#define DEM_CLEAR_WRONG_DTCORIGIN 2U +#endif /* DEM_CLEAR_WRONG_DTCORIGIN */ + +#ifndef DEM_CLEAR_WRONG_DTCKIND +#define DEM_CLEAR_WRONG_DTCKIND 3U +#endif /* DEM_CLEAR_WRONG_DTCKIND */ + +#ifndef DEM_CLEAR_FAILED +#define DEM_CLEAR_FAILED 4U +#endif /* DEM_CLEAR_FAILED */ + +#ifndef DEM_DTC_PENDING +#define DEM_DTC_PENDING 5U +#endif /* DEM_DTC_PENDING */ + +#define DEM_EVENT_DESTINATION_END_OF_LIST 0 + +/* + * DTC storage types + */ +typedef uint8 Dem_DTCTranslationFormatType; +#define DEM_DTC_TRANSLATION_ISO15031_6 0x00 +#define DEM_DTC_TRANSLATION_ISO14229_1 0x01 +#define DEM_DTC_TRANSLATION_SAEJ1939_73 0x02 +#define DEM_DTC_TRANSLATION_ISO11992_4 0x03 + +/* + * Dem_DTCGroupType + */ +typedef uint32 Dem_DTCGroupType; +#define DEM_DTC_GROUP_EMISSION_REL_DTCS (Dem_DTCGroupType)0x0 +#define DEM_DTC_GROUP_ALL_DTCS (Dem_DTCGroupType)0xffffff + +/* + * Dem status type + */ +#define DEM_DTC_STATUS_MASK_ALL (uint8)0x00 + + +/* + * Dem_FreezeFrameKindType + */ +typedef uint8 Dem_FreezeFrameKindType; // NOTE: Check type and values +#define DEM_FREEZE_FRAME_NON_OBD (Dem_FreezeFrameKindType)0x01 +#define DEM_FREEZE_FRAME_OBD (Dem_FreezeFrameKindType)0x02 + +/* + * Dem_EventKindType + */ +typedef uint8 Dem_EventKindType; // NOTE: Check type and values +#define DEM_EVENT_KIND_BSW (Dem_EventKindType)0x01 +#define DEM_EVENT_KIND_SWC (Dem_EventKindType)0x02 + +/* + * Dem_PreDebounceNameType + */ +typedef uint8 Dem_PreDebounceNameType; +enum { + DEM_NO_PRE_DEBOUNCE, + DEM_PRE_DEBOUNCE_COUNTER_BASED, + DEM_PRE_DEBOUNCE_TIME_BASED +}; + +/* + * Dem_FilterWithSeverityType + */ +typedef uint8 Dem_FilterWithSeverityType; +#define DEM_FILTER_WITH_SEVERITY_YES (Dem_FilterWithSeverityType)0x00 +#define DEM_FILTER_WITH_SEVERITY_NO (Dem_FilterWithSeverityType)0x01 + +/* + * Dem_FilterForFDCType + */ +typedef uint8 Dem_FilterForFDCType; +#define DEM_FILTER_FOR_FDC_YES (Dem_FilterForFDCType)0x00 +#define DEM_FILTER_FOR_FDC_NO (Dem_FilterForFDCType)0x01 + +/* + * Dem_DTCSeverityType + */ +typedef uint8 Dem_DTCSeverityType; +#define DEM_SEVERITY_NO_SEVERITY 0x00u /* No severity information available */ +#define DEM_SEVERITY_MAINTENANCE_ONLY 0x20u +#define DEM_SEVERITY_CHECK_AT_NEXT_HALT 0x40u +#define DEM_SEVERITY_CHECK_IMMEDIATELY 0x80u + +/* + * Dem_ReturnSetDTCFilterType + */ +typedef uint8 Dem_ReturnSetFilterType; +#define DEM_FILTER_ACCEPTED (Dem_ReturnSetFilterType)0x00 +#define DEM_WRONG_FILTER (Dem_ReturnSetFilterType)0x01 + +/* + * Dem_ReturnGetStatusOfDTCType + */ +typedef uint8 Dem_ReturnGetStatusOfDTCType; +#define DEM_STATUS_OK (Dem_ReturnGetStatusOfDTCType)0x00 +#define DEM_STATUS_WRONG_DTC (Dem_ReturnGetStatusOfDTCType)0x01 +#define DEM_STATUS_WRONG_DTCORIGIN (Dem_ReturnGetStatusOfDTCType)0x02 +#define DEM_STATUS_FAILED (Dem_ReturnGetStatusOfDTCType)0x04 +#define DEM_STATUS_WRONG_DTCKIND (Dem_ReturnGetStatusOfDTCType)0x03 + +/* + * Dem_ReturnGetNextFilteredDTCType + */ +typedef uint8 Dem_ReturnGetNextFilteredDTCType; +#define DEM_FILTERED_OK (Dem_ReturnGetNextFilteredDTCType)0x00 +#define DEM_FILTERED_NO_MATCHING_DTC (Dem_ReturnGetNextFilteredDTCType)0x01 +#define DEM_FILTERED_WRONG_DTCKIND (Dem_ReturnGetNextFilteredDTCType)0x02 +#define DEM_FILTERED_PENDING (Dem_ReturnGetNextFilteredDTCType)0x03 + +/* + * Dem_ReturnGetNumberOfFilteredDTCType + */ +typedef uint8 Dem_ReturnGetNumberOfFilteredDTCType; +#define DEM_NUMBER_OK (Dem_ReturnGetNumberOfFilteredDTCType)0x00 +#define DEM_NUMBER_FAILED (Dem_ReturnGetNumberOfFilteredDTCType)0x01 +#define DEM_NUMBER_PENDING (Dem_ReturnGetNumberOfFilteredDTCType)0x02 + +/* + * Dem_ReturnControlDTCStorageType + */ +typedef uint8 Dem_ReturnControlDTCStorageType; +#define DEM_CONTROL_DTC_STORAGE_OK (Dem_ReturnControlDTCStorageType)0x00 +#define DEM_CONTROL_DTC_STORAGE_N_OK (Dem_ReturnControlDTCStorageType)0x01 +#define DEM_CONTROL_DTC_WRONG_DTCGROUP (Dem_ReturnControlDTCStorageType)0x02 + +/* + * Dem_ReturnControlEventUpdateType + */ +typedef uint8 Dem_ReturnControlEventUpdateType; +#define DEM_CONTROL_EVENT_UPDATE_OK (Dem_ReturnControlEventUpdateType)0x00 +#define DEM_CONTROL_EVENT_N_OK (Dem_ReturnControlEventUpdateType)0x01 +#define DEM_CONTROL_EVENT_WRONG_DTCGROUP (Dem_ReturnControlEventUpdateType)0x02 + +/* + * Dem_ReturnGetExtendedDataRecordByDTCType + */ +typedef uint8 Dem_ReturnGetExtendedDataRecordByDTCType; +#define DEM_RECORD_OK (Dem_ReturnGetExtendedDataRecordByDTCType)0x00 +#define DEM_RECORD_WRONG_DTC (Dem_ReturnGetExtendedDataRecordByDTCType)0x01 +#define DEM_RECORD_WRONG_DTCORIGIN (Dem_ReturnGetExtendedDataRecordByDTCType)0x02 +#define DEM_RECORD_DTCKIND (Dem_ReturnGetExtendedDataRecordByDTCType)0x03 +#define DEM_RECORD_NUMBER (Dem_ReturnGetExtendedDataRecordByDTCType)0x04 +#define DEM_RECORD_BUFFERSIZE (Dem_ReturnGetExtendedDataRecordByDTCType)0x05 +#define DEM_RECORD_PENDING (Dem_ReturnGetExtendedDataRecordByDTCType)0x06 + +/* + * Dem_ReturnGetDTCByOccurenceTimeType + */ +typedef uint8 Dem_ReturnGetDTCByOccurenceTimeType; +#define DEM_OCCURR_OK (Dem_ReturnGetDTCByOccurenceTimeType)0x00 +#define DEM_OCCURR_WRONG_DTCKIND (Dem_ReturnGetDTCByOccurenceTimeType)0x01 +#define DEM_OCCURR_FAILED (Dem_ReturnGetDTCByOccurenceTimeType)0x02 + +/* + * Dem_ReturnGetFreezeFrameDataByDTCType + */ +typedef uint8 Dem_ReturnGetFreezeFrameDataByDTCType; +#define DEM_GET_FFDATABYDTC_OK (Dem_ReturnGetFreezeFrameDataByDTCType)0x00 +#define DEM_GET_FFDATABYDTC_WRONG_DTC (Dem_ReturnGetFreezeFrameDataByDTCType)0x01 +#define DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN (Dem_ReturnGetFreezeFrameDataByDTCType)0x02 +#define DEM_GET_FFDATABYDTC_WRONG_DTCKIND (Dem_ReturnGetFreezeFrameDataByDTCType)0x03 +#define DEM_GET_FFDATABYDTC_RECORDNUMBER (Dem_ReturnGetFreezeFrameDataByDTCType)0x04 +#define DEM_GET_FFDATABYDTC_WRONG_DATAID (Dem_ReturnGetFreezeFrameDataByDTCType)0x05 +#define DEM_GET_FFDATABYDTC_BUFFERSIZE (Dem_ReturnGetFreezeFrameDataByDTCType)0x06 +#define DEM_GET_ID_PENDING (Dem_ReturnGetFreezeFrameDataByDTCType)0x07 + +/* + * Dem_ReturnGetSizeOfExtendedDataRecordByDTCType + */ +typedef uint8 Dem_ReturnGetSizeOfExtendedDataRecordByDTCType; +#define DEM_GET_SIZEOFEDRBYDTC_OK (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x00 +#define DEM_GET_SIZEOFEDRBYDTC_W_DTC (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x01 +#define DEM_GET_SIZEOFEDRBYDTC_W_DTCOR (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x02 +#define DEM_GET_SIZEOFEDRBYDTC_W_DTCKI (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x03 +#define DEM_GET_SIZEOFEDRBYDTC_W_RNUM (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x04 +#define DEM_GET_SIZEOFEDRBYDTC_PENDING (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x05 + +/* + * Dem_ReturnGetSizeOfFreezeFrameType + */ +typedef uint8 Dem_ReturnGetSizeOfFreezeFrameType; +#define DEM_GET_SIZEOFFF_OK (Dem_ReturnGetSizeOfFreezeFrameType)0x00 +#define DEM_GET_SIZEOFFF_WRONG_DTC (Dem_ReturnGetSizeOfFreezeFrameType)0x01 +#define DEM_GET_SIZEOFFF_WRONG_DTCOR (Dem_ReturnGetSizeOfFreezeFrameType)0x02 +#define DEM_GET_SIZEOFFF_WRONG_DTCKIND (Dem_ReturnGetSizeOfFreezeFrameType)0x03 +#define DEM_GET_SIZEOFFF_WRONG_RNUM (Dem_ReturnGetSizeOfFreezeFrameType)0x04 +#define DEM_GET_SIZEOFFF_PENDING (Dem_ReturnGetSizeOfFreezeFrameType)0x05 + +/******************************************************* + * Definitions where the type is declared in Rte_Dem.h * + *******************************************************/ +/* + * DemDTCKindType definitions + */ +typedef uint8 Dem_DTCKindType; + +#ifndef DEM_DTC_KIND_ALL_DTCS +#define DEM_DTC_KIND_ALL_DTCS (Dem_DTCKindType)0x01 +#endif /* DEM_DTC_KIND_ALL_DTCS */ + +#ifndef DEM_DTC_KIND_EMISSION_REL_DTCS +#define DEM_DTC_KIND_EMISSION_REL_DTCS (Dem_DTCKindType)0x02 +#endif /* DEM_DTC_KIND_EMISSION_REL_DTCS */ + +/* + * Dem_InitMonitorKindType definitions + */ +#ifndef DEM_INIT_MONITOR_CLEAR +#define DEM_INIT_MONITOR_CLEAR (Dem_InitMonitorReasonType)1 +#endif /* DEM_INIT_MONITOR_CLEAR */ + +#ifndef DEM_INIT_MONITOR_RESTART +#define DEM_INIT_MONITOR_RESTART (Dem_InitMonitorReasonType)2 +#endif /* DEM_INIT_MONITOR_RESTART */ + + +/* + * Dem_IndicatorStatusType definitions + */ +#ifndef DEM_INDICATOR_OFF +#define DEM_INDICATOR_OFF 0U +#endif /* DEM_INDICATOR_OFF */ +#ifndef DEM_INDICATOR_CONTINUOUS +#define DEM_INDICATOR_CONTINUOUS 1U +#endif /* DEM_INDICATOR_CONTINUOUS */ +#ifndef DEM_INDICATOR_BLINKING +#define DEM_INDICATOR_BLINKING 2U +#endif /* DEM_INDICATOR_BLINKING */ +#ifndef DEM_INDICATOR_BLINK_CONT +#define DEM_INDICATOR_BLINK_CONT 3U +#endif /* DEM_INDICATOR_BLINK_CONT */ + + +/* + * DemOperationCycleType definitions + */ +enum { + DEM_ACTIVE, // Started by DEM on Dem_PreInit and stopped on Dem_Shutdown + + DEM_POWER, // Power ON/OFF Cycle + DEM_IGNITION, // Ignition ON/OF Cycle + DEM_WARMUP, // OBD Warm up Cycle + DEM_OBD_DCY, // OBD Driving Cycle + + DEM_OPERATION_CYCLE_ID_ENDMARK +};/** @req DEM480 */ + +/* + * Dem_ReturnGetSeverityOfDTCType + */ +typedef uint8 Dem_ReturnGetSeverityOfDTCType; +#define DEM_GET_SEVERITYOFDTC_OK (Dem_ReturnGetSeverityOfDTCType)0x00 +#define DEM_GET_SEVERITYOFDTC_WRONG_DTC (Dem_ReturnGetSeverityOfDTCType)0x01 +#define DEM_GET_SEVERITYOFDTC_NOSEVERITY (Dem_ReturnGetSeverityOfDTCType)0x02 +#define DEM_GET_SEVERITYOFDTC_PENDING (Dem_ReturnGetSeverityOfDTCType)0x03 + +/* + * Dem_ReturnDisableDTCRecordUpdateType + */ +typedef uint8 Dem_ReturnDisableDTCRecordUpdateType; +#define DEM_DISABLE_DTCRECUP_OK (Dem_ReturnDisableDTCRecordUpdateType)0x00 +#define DEM_DISABLE_DTCRECUP_WRONG_DTC (Dem_ReturnDisableDTCRecordUpdateType)0x01 +#define DEM_DISABLE_DTCRECUP_WRONG_DTCORIGIN (Dem_ReturnDisableDTCRecordUpdateType)0x02 +#define DEM_DISABLE_DTCRECUP_PENDING (Dem_ReturnDisableDTCRecordUpdateType)0x03 + +/* + * Dem_ReturnGetSizeOfFreezeFrameByDTCType + */ +typedef uint8 Dem_ReturnGetSizeOfFreezeFrameByDTCType; +//conflict in type check +//#define DEM_GET_SIZEOFFF_OK (Dem_ReturnGetSizeOfFreezeFrameByDTCType)0x00 +//#define DEM_GET_SIZEOFFF_WRONG_DTC (Dem_ReturnGetSizeOfFreezeFrameByDTCType)0x01 +//#define DEM_GET_SIZEOFFF_WRONG_DTCOR (Dem_ReturnGetSizeOfFreezeFrameByDTCType)0x02 +//#define DEM_GET_SIZEOFFF_WRONG_RNUM (Dem_ReturnGetSizeOfFreezeFrameByDTCType)0x03 +//#define DEM_GET_SIZEOFFF_PENDING (Dem_ReturnGetSizeOfFreezeFrameByDTCType)0x04 + +/* + * Dem_ReturnGetFreezeFrameDataByDTCType + */ +//typedef uint8 Dem_ReturnGetFreezeFrameDataByDTCType; +//#define DEM_GET_FFDATABYDTC_OK (Dem_ReturnGetFreezeFrameDataByDTCType)0x00 +//#define DEM_GET_FFDATABYDTC_WRONG_DTC (Dem_ReturnGetFreezeFrameDataByDTCType)0x01 +//#define DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN (Dem_ReturnGetFreezeFrameDataByDTCType)0x02 +//#define DEM_GET_FFDATABYDTC_WRONG_RECORDNUMBER (Dem_ReturnGetFreezeFrameDataByDTCType)0x03 +//#define DEM_GET_FFDATABYDTC_WRONG_BUFFERSIZE (Dem_ReturnGetFreezeFrameDataByDTCType)0x04 +#define DEM_GET_FFDATABYDTC_PENDING (Dem_ReturnGetFreezeFrameDataByDTCType)0x05 + +#define DEM_RECORD_WRONG_NUMBER (Dem_ReturnGetExtendedDataRecordByDTCType)0x03 + + + + + + + + +#endif /*DEM_TYPES_H_*/ diff --git a/firmware/src/DiagnosticR/FicOsek/FicOsekCom.h b/firmware/src/DiagnosticR/FicOsek/FicOsekCom.h new file mode 100644 index 0000000..46881cf --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicOsekCom.h @@ -0,0 +1,451 @@ +#ifndef __FICOSEKCOM_H +#define __FICOSEKCOM_H + +/*-------------------------------- Includes ------------------------------*/ +#include "Std_Types.h" +#include "DiagnosticR/Comp_HAL_Autosar_Wrappers/FicosarCAN.h" +#include "OsekCom/OsekCom.h" +/*-------------------------------- Defines -------------------------------*/ + + +/*----------------------------- Data Types -------------------------------*/ +typedef UI_8 t_sig_diagnosticreqprndl[8]; +typedef UI_8 t_sig_diagnosticfuncaddrreq[8]; + + + +#ifndef _FICOSEKCOM_H +#define _FICOSEKCOM_H + +/* Type definition of the symbolic names for signals */ +typedef UI_16 t_symbolic_name; +typedef UI_16 t_symbolic_frm_name; + +/* Return type of the calls OSEK COM */ +typedef UI_8 t_status_type; + +/* Structure of data type passed by reference in */ +/* the calls of OSEK COM */ +typedef void *t_application_data_ref; +typedef void *t_length_ref; + +/* Flag types of OSEK COM */ +//typedef enum { + //COM_FALSE = 0x00, /* Flag down */ + // COM_TRUE = 0x01 /* Flag up */ +//} t_flag_value; + +/* Stop mode of OSEK COM */ +//typedef enum { + // COM_SHUTDOWN_IMMEDIATE = 0 /* Apagat immediat */ +//} t_com_shutdown_mode_type; + +/* Initialize mode of OSEK COM */ +//typedef enum { + // COM_NORMAL_MODE = 0 /* No es processen trames de COM de Debug */ +//} t_com_application_mode_type; + +#endif + + + +/*--------------------------- Global Variables ---------------------------*/ + +/*----------- Prototypes of Callback Function Provided by User ----------*/ + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Notification Callbacks provided by user for class 1 (RxNotif), 3 (RxErrorNotif) +| 2 (TxNotif) and 4 (TxErrorNotif) +| --------------------------------------------------------------------------- +| Parameters description: +/ ------------------------------------------------- -------------------------- */ +#define COMCallback(CallbackRoutineName) void CallbackRoutineName(void) + +//COMCallback(VCU_RX_Timeout_Callback); +//COMCallback(CGW_BCM_Status1_Timeout_Callback); +COMCallback(SHIFT_Tx_Callback); +COMCallback(SHIFT_Tx_Error_Callback); + + +/* --------------------------- Routine Prototypes --------------------------- */ + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reception of a new frame notification callback +| * This callback must be launched by the lower COM driver upon the reception +| of a new frame. +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the received frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComRxNotifCallbackPRNDL(t_com_buf_hdl bhdl); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Available transmission buffer notification callback +| * This callback must be launched by the lower COM driver upon a transmission +| buffer will become available after requesting one to perform a transmission. +|--------------------------------------------------------------------------- +| Parameters description: +| return: TRUE in case that after current transmission lower COM driver should +| call again this callback to transmit a new frame. +| FALSE otherwise. +/---------------------------------------------------------------------------*/ +BOOL OsekComTxReqCallbackPRNDL(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Frame transmission confirmation notifying callback +| * This callback must be launched by the lower COM driver upon the completion +| of a frame transmission for which transmission confirmation has been requested +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the transmitted frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComTxNotifCallbackPRNDL(t_com_buf_hdl bhdl); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to initialize OsekCom stack +| +| ------------------------------------------------- -------------------------- +| Parameters description: +| app_mode: OsekCom initialization mode (See t_com_application_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +//t_status_type StartCom(t_com_application_mode_type app_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to inquiry in which mode OsekCom has been initialized. +| * If this service is called before initializing the communications stack +| a random mode will be returned. +| --------------------------------------------------------------------------- +| Parameters description: +| return: OsekCom initialization mode(See t_com_application_mode_type) +/ --------------------------------------------------------------------------- */ +//t_com_application_mode_type GetComApplicationMode(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to close the OsekCom stack. +| * This service stops the transmission of periodic frames. +| * After calling this service communications could be re-established +| calling again service StartCom. +| * This service does not change the state of any lower COM driver. +| --------------------------------------------------------------------------- +| Parameters description: +| shtdwn_mode: OsekCom stop mode (See t_com_shutdown_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/ --------------------------------------------------------------------------- */ +//t_status_type StopCom(t_com_shutdown_mode_type shtdwn_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to start the transmission of periodic or mixed frames. +| * If this service is re-executed then transmission timers will be re-started. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StartPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to stop the transmission of periodic or mixed frames. +| * To re-start the transmission of periodic or mixed frames service +| StartPeriodic must be called. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StopPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates the application variable referenced by >data_ref< with +| the data stored in the internal stack for the object identified by >message<. +| * This service will reset the class 1 (RxNotif) and 3 (RxErrorNotif) flags +| associated to >message< +| * If >message< is an enqueued signal the service will return the data +| stored in the internal stack (initial value / last received value / last value +| set with InitMessage) +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not supported) +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be retrieved. +| data_ref: Pointer to a variable where to store the requested signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent, dynamic length or zero-length +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the queue of the signal identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type ReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates the application variable referenced by >data_ref< with +| the data stored in the internal stack for the object identified by >message<. +| * The length of the received signal data will be placed in the variable +| referenced by >length_ref<. +| * This service will reset the class 1 (RxNotif) and 3 (RxErrorNotif) flags +| associated to >message< +| * This service could be used with enqueued messages only. This service is +| provided for external communication only. +| * The service will return the data stored in the internal stack +| (initial value / last received value / last value set with InitMessage) +| * The user is responsible of granting that the parameters >data_ref< +| and >lenght_ref< point to variables correctly allocated and compatible in +| size with the received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| t_length_ref length_ref; +| (void)ReceiveDynamicMessage(SIG_VEHICLE_SPEED,&vehicle_speed,&length_ref); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be retrieved. +| data_ref: Pointer to a variable where to store the requested signal. +| lenght_ref: Pointer to a variable where to store the retrieved signal size. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to a message that is sent, a queued message, a static-length +| message or a zero-length message. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type ReceiveDynamicMessage(t_symbolic_name message, + t_application_data_ref data_ref, + t_length_ref length_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< parameter. +| * This service will reset the class 2 (TxNotif) and 4 (TxErrorNotif) flags +| associated to >message< +| * If >message< has the Triggered Transfer Property, the update will be +| followed by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode. +| In this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| triggered by the usage of this service. +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| transmitted signal type. +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| (void)SendMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be transmitted. +| data_ref: Pointer to a variable containing the data to be transmitted. +| return: +| E_OK in case of no errors +| E_COM_ID is case the parameter >message< is out of range or if it refers +| to a message that is received or to a dynamic-length or +| zero-length message. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +#define OSEK_SENDMESSAGE +t_status_type SendMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by variables +| referenced by >data_ref< and >lenght_ref< +| * This service will reset the class 2 (TxNotif) and 4 (TxErrorNotif) flags +| associated to >message< +| * If >message< has the Triggered Transfer Property, the update is followed +| by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode. +| In this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| caused by the usage of this service. +| * This service can be used with enqueued messages only. This service is +| provided for external communication only. +| * The user is responsible of granting that the parameters >data_ref< +| and >lenght_ref< points to variables correctly allocated and +| compatible in size with the transmitted signal type. +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| t_length_ref length_ref = 1; +| (void)SendDynamicMessage(SIG_VEHICLE_SPEED, &vehicle_speed, &length_ref); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be transmitted. +| data_ref: Pointer to a variable containing the data to be transmitted. +| lenght_ref: Pointer to a variable containing the size of the signal +| to be transmitted. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to a received signal, a static-length signal or a zero-length signal. +| E_COM_LENGTH in case the value to which >length_ref< points is not within +| the range 0 to the maximum length defined for >message<. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +#define OSEK_SENDDYNAMICMESSAGE +t_status_type SendDynamicMessage(t_symbolic_name message, + t_application_data_ref data_ref, + t_length_ref length_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< +| * This service will not reset any class flags associated to >message< +| * This service will not initiate any transmission. +| * The user is responsible of granting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| data_ref: Pointer to a variable containing the data. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type InitMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if has not been detected any communication activity since +| last clear +| COM_TRUE if has been detected communication activity since last clear +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagComTrafficPRNDL(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void ResetFlagComTrafficPRNDL(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to retrieve the state of class 1 (RxNotif), +| class 3 (Rx_ErrorNotif), class 2 (TxNotif) and class 4 (Tx_ErrorNotif) flags +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagRxSig(t_symbolic_name message); +t_flag_value ReadFlagTxSig(t_symbolic_name message); +t_flag_value ReadFlagTxSigDiagnosticRespPRNDL(void); +t_flag_value ReadFlagTxErrorSig(t_symbolic_name message); +t_flag_value ReadFlagTxErrorSigDiagnosticRespPRNDL(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to enable tx message flag +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void EnableTxFrm_diag_physresp_prndl(void); +void DisableTxFrm_diag_physresp_prndl(void); +void EnableTxFrm_shiftselectposition(void); +void DisableTxFrm_shiftselectposition(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the notify class 1 (RxNotif) class 3 (RxErrorNotif) +| class 2 (TxNotif) and class 4 (TxErrorNotif) +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +/---------------------------------------------------------------------------*/ +void ResetFlagRxSig(t_symbolic_name message); +//void ResetFlagRxSigDiagnosticReqSWTR(void); +void ResetFlagRxSigDiagnosticFuncAddrReq(void); +void ResetFlagTxSig(t_symbolic_name message); +void ResetFlagTxErrorSig(t_symbolic_name message); +void ResetFlagTxErrorSigDiagnosticRespSWTR(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Main runnable of the OsekCom stack intended to be called periodically by +| the system scheduler with a period equal to FICOSEK_COM_TASK_TICKS +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void OsekComTask(void); + +#endif + diff --git a/firmware/src/DiagnosticR/FicOsek/FicOsekComSSU.h b/firmware/src/DiagnosticR/FicOsek/FicOsekComSSU.h new file mode 100644 index 0000000..a358ab1 --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicOsekComSSU.h @@ -0,0 +1,597 @@ + +#ifndef _Internal_FICOSEKCOM_H +#define _Internal_FICOSEKCOM_H + +/*-------------------------------- includes ------------------------------*/ +#include "Global.h" +#include "SpiFrameWrapper.h" + +/*-------------------------------- defines -------------------------------*/ +/* Return type of the calls OSEK COM */ +#ifndef STD_TYPES_H + #define E_OK ((UI_8)0x00) /* Service call has succeeded */ +#endif +#define E_COM_ID ((UI_8)0x01) /* Given message or mode identifier */ + /* is out of range or invalid */ +#define E_COM_LENGTH ((UI_8)0x02) /* Given data length is out of range */ +#define E_COM_LIMIT ((UI_8)0x03) /* Overflow of message queue */ +#define E_COM_NOMSG ((UI_8)0x04) /* Message queue is empty */ +#define E_COM_SYS_NOINIT ((UI_8)0x05) /* User defined E_COM_SYS_?? */ + +/* Node id */ +#define NODE_ID_MASK ((UI_16) 0xF000) /* Mask to get nodes id */ +#define NODE_ID_MMC (((UI_16) 0x1000) & NODE_ID_MASK) /* Symbolic name of the node MMC */ + +/* Symbolic names for Tx signals with static length */ +/* First tx signal */ +#define INTERNALFIRST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_MMC_ACTU_UDS_MODE) +#define SIG_MMC_ACTU_UDS_MODE (((UI_16) 1) | NODE_ID_MMC) /* Symbolic name of the signal MMC_ACTU_uds_mode */ +#define SIG_MMC_APPLICATION_MODE (((UI_16) 2) | NODE_ID_MMC) /* Symbolic name of the signal MMC_application_mode */ +#define SIG_MMC_CLOCK_ATCU_A112 (((UI_16) 3) | NODE_ID_MMC) /* Symbolic name of the signal MMC_Clock_ATCU_A112 */ +#define SIG_MMC_CRC_ATCU_A112 (((UI_16) 4) | NODE_ID_MMC) /* Symbolic name of the signal MMC_CRC_ATCU_A112 */ +#define SIG_MMC_D_LOCK_UDS_OFFSET (((UI_16) 5) | NODE_ID_MMC) /* Symbolic name of the signal MMC_d_lock_uds_offset */ +#define SIG_MMC_D_N_UDS_OFFSET (((UI_16) 6) | NODE_ID_MMC) /* Symbolic name of the signal MMC_d_n_uds_offset */ +#define SIG_MMC_D_OUT_UDS_OFFSET (((UI_16) 7) | NODE_ID_MMC) /* Symbolic name of the signal MMC_d_out_uds_offset */ +#define SIG_MMC_D_UDS_DIE1_SETPOINT (((UI_16) 8) | NODE_ID_MMC) /* Symbolic name of the signal MMC_d_uds_die1_setpoint */ +#define SIG_MMC_D_UDS_DIE2_SETPOINT (((UI_16) 9) | NODE_ID_MMC) /* Symbolic name of the signal MMC_d_uds_die2_setpoint */ +#define SIG_MMC_GEARLEVERPOSITIONEXTENDED_V2 (((UI_16) 10) | NODE_ID_MMC) /* Symbolic name of the signal MMC_GearLeverPositionExtended_v2 */ +#define SIG_MMC_IGNITIONSUPPLYCONFIRMATION (((UI_16) 11) | NODE_ID_MMC) /* Symbolic name of the signal MMC_IgnitionSupplyConfirmation */ +#define SIG_MMC_MELEXIS_VIRTUAL_DIE1 (((UI_16) 12) | NODE_ID_MMC) /* Symbolic name of the signal MMC_melexis_virtual_die1 */ +#define SIG_MMC_MELEXIS_VIRTUAL_DIE2 (((UI_16) 13) | NODE_ID_MMC) /* Symbolic name of the signal MMC_melexis_virtual_die2 */ +#define SIG_MMC_MLX_POSITION (((UI_16) 14) | NODE_ID_MMC) /* Symbolic name of the signal MMC_mlx_position */ +#define SIG_MMC_N_D_UDS_OFFSET (((UI_16) 15) | NODE_ID_MMC) /* Symbolic name of the signal MMC_n_d_uds_offset */ +#define SIG_MMC_N_R_UDS_OFFSET (((UI_16) 16) | NODE_ID_MMC) /* Symbolic name of the signal MMC_n_r_uds_offset */ +#define SIG_MMC_N_UDS_DIE1_SETPOINT (((UI_16) 17) | NODE_ID_MMC) /* Symbolic name of the signal MMC_n_uds_die1_setpoint */ +#define SIG_MMC_N_UDS_DIE2_SETPOINT (((UI_16) 18) | NODE_ID_MMC) /* Symbolic name of the signal MMC_n_uds_die2_setpoint */ +#define SIG_MMC_P_LOCK_UDS_OFFSET (((UI_16) 19) | NODE_ID_MMC) /* Symbolic name of the signal MMC_p_lock_uds_offset */ +#define SIG_MMC_P_OUT_UDS_OFFSET (((UI_16) 20) | NODE_ID_MMC) /* Symbolic name of the signal MMC_p_out_uds_offset */ +#define SIG_MMC_P_R_UDS_OFFSET (((UI_16) 21) | NODE_ID_MMC) /* Symbolic name of the signal MMC_p_r_uds_offset */ +#define SIG_MMC_P_UDS_DIE1_SETPOINT (((UI_16) 22) | NODE_ID_MMC) /* Symbolic name of the signal MMC_p_uds_die1_setpoint */ +#define SIG_MMC_P_UDS_DIE2_SETPOINT (((UI_16) 23) | NODE_ID_MMC) /* Symbolic name of the signal MMC_p_uds_die2_setpoint */ +#define SIG_MMC_RELAY_SELFCHECK_REQUEST (((UI_16) 24) | NODE_ID_MMC) /* Symbolic name of the signal MMC_relay_selfcheck_request */ +#define SIG_MMC_R_N_UDS_OFFSET (((UI_16) 25) | NODE_ID_MMC) /* Symbolic name of the signal MMC_r_n_uds_offset */ +#define SIG_MMC_R_P_UDS_OFFSET (((UI_16) 26) | NODE_ID_MMC) /* Symbolic name of the signal MMC_r_p_uds_offset */ +#define SIG_MMC_R_UDS_DIE1_SETPOINT (((UI_16) 27) | NODE_ID_MMC) /* Symbolic name of the signal MMC_r_uds_die1_setpoint */ +#define SIG_MMC_R_UDS_DIE2_SETPOINT (((UI_16) 28) | NODE_ID_MMC) /* Symbolic name of the signal MMC_r_uds_die2_setpoint */ +#define SIG_MMC_SCU_GEARBOXPOSITIONTARGET (((UI_16) 29) | NODE_ID_MMC) /* Symbolic name of the signal MMC_SCU_GearboxPositionTarget */ +#define SIG_MMC_UDS_SETPOINTS_CRC (((UI_16) 30) | NODE_ID_MMC) /* Symbolic name of the signal MMC_uds_setpoints_crc */ +#define SIG_MMC_UDS_SETPOINTS_RC (((UI_16) 31) | NODE_ID_MMC) /* Symbolic name of the signal MMC_uds_setpoints_rc */ +/* Last tx signal */ +#define INTERNALLAST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_MMC_UDS_SETPOINTS_RC) + + +/* Symbolic names for Rx signals */ +#define SIG_SMC_BMAR_SNS (((UI_16) 32) | NODE_ID_MMC) /* Symbolic name of the signal SMC_bmar_sns */ +#define SIG_SMC_CALIBRATION_NOP (((UI_16) 33) | NODE_ID_MMC) /* Symbolic name of the signal SMC_calibration_NOP */ +#define SIG_SMC_FW_VERSION (((UI_16) 34) | NODE_ID_MMC) /* Symbolic name of the signal SMC_fw_version */ +#define SIG_SMC_MELEXIS_DIAGNOSTICS (((UI_16) 35) | NODE_ID_MMC) /* Symbolic name of the signal SMC_melexis_diagnostics */ +#define SIG_SMC_MLX_COOK_DIE1 (((UI_16) 36) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_cook_die1 */ +#define SIG_SMC_MLX_COOK_DIE2 (((UI_16) 37) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_cook_die2 */ +#define SIG_SMC_MLX_CURRENT_POSITION (((UI_16) 38) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_current_position */ +#define SIG_SMC_MLX_RAW_DIE1 (((UI_16) 39) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_raw_die1 */ +#define SIG_SMC_MLX_RAW_DIE2 (((UI_16) 40) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_raw_die2 */ +#define SIG_SMC_MLX_TEMPERATURE_DIE1 (((UI_16) 41) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_temperature_die1 */ +#define SIG_SMC_MLX_TEMPERATURE_DIE2 (((UI_16) 42) | NODE_ID_MMC) /* Symbolic name of the signal SMC_MLX_temperature_die2 */ +#define SIG_SMC_MODE_CONTOLER (((UI_16) 43) | NODE_ID_MMC) /* Symbolic name of the signal SMC_mode_contoler */ +#define SIG_SMC_RELAY_STATUS (((UI_16) 44) | NODE_ID_MMC) /* Symbolic name of the signal SMC_relay_status */ +#define SIG_SMC_VBAT_MOTOR_SUP_SNS (((UI_16) 45) | NODE_ID_MMC) /* Symbolic name of the signal SMC_vbat_motor_sup_sns */ + +/* Symbolic names for Dummy signal */ +#define INTERNALSIGDUMMY ((UI_16)0x0FFF) /* Symbolic name of the signal SIGDUMMY */ + + +/*----------------------------- data types -------------------------------*/ +/* Type definition of internal signals */ +typedef SI_16 t_sig_mmc_p_uds_die1_setpoint; +typedef SI_16 t_sig_mmc_r_uds_die1_setpoint; +typedef SI_16 t_sig_mmc_n_uds_die1_setpoint; +typedef SI_16 t_sig_mmc_d_uds_die1_setpoint; +typedef SI_16 t_sig_mmc_p_uds_die2_setpoint; +typedef SI_16 t_sig_mmc_r_uds_die2_setpoint; +typedef SI_16 t_sig_mmc_n_uds_die2_setpoint; +typedef SI_16 t_sig_mmc_d_uds_die2_setpoint; +typedef UI_8 t_sig_mmc_p_lock_uds_offset; +typedef UI_8 t_sig_mmc_p_r_uds_offset; +typedef UI_8 t_sig_mmc_r_p_uds_offset; +typedef UI_8 t_sig_mmc_r_n_uds_offset; +typedef UI_8 t_sig_mmc_n_r_uds_offset; +typedef UI_8 t_sig_mmc_n_d_uds_offset; +typedef UI_8 t_sig_mmc_d_n_uds_offset; +typedef UI_8 t_sig_mmc_d_lock_uds_offset; +typedef SI_16 t_sig_mmc_uds_setpoints_rc; +typedef SI_8 t_sig_mmc_uds_setpoints_crc; +typedef UI_8 t_sig_mmc_p_out_uds_offset; +typedef UI_8 t_sig_mmc_d_out_uds_offset; +typedef UI_8 t_sig_mmc_scu_gearboxpositiontarget; +typedef UI_8 t_sig_mmc_gearleverpositionextended_v2; +typedef UI_8 t_sig_mmc_clock_atcu_a112; +typedef UI_8 t_sig_mmc_crc_atcu_a112; +typedef UI_8 t_sig_mmc_ignitionsupplyconfirmation; +typedef UI_8 t_sig_mmc_actu_uds_mode; +typedef UI_8 t_sig_mmc_mlx_position; +typedef SI_16 t_sig_mmc_melexis_virtual_die1; +typedef SI_16 t_sig_mmc_melexis_virtual_die2; +typedef UI_8 t_sig_mmc_relay_selfcheck_request; +typedef UI_8 t_sig_mmc_application_mode; +typedef SI_16 t_sig_smc_mlx_cook_die1; +typedef SI_16 t_sig_smc_mlx_cook_die2; +typedef UI_8 t_sig_smc_mode_contoler; +typedef SI_8 t_sig_smc_mlx_current_position; +typedef UI_16 t_sig_smc_vbat_motor_sup_sns; +typedef UI_16 t_sig_smc_bmar_sns; +typedef SI_16 t_sig_smc_mlx_raw_die1; +typedef SI_16 t_sig_smc_mlx_raw_die2; +typedef UI_8 t_sig_smc_mlx_temperature_die1; +typedef UI_8 t_sig_smc_mlx_temperature_die2; +typedef UI_8 t_sig_smc_fw_version; +typedef UI_8 t_sig_smc_melexis_diagnostics; +typedef UI_8 t_sig_smc_relay_status; +typedef UI_8 t_sig_smc_calibration_nop[8]; + + +#ifndef _FICOSEKCOM_H +#define _FICOSEKCOM_H + +/* Type definition of the symbolic names for signals */ +typedef UI_16 t_symbolic_name; +typedef UI_16 t_symbolic_frm_name; + +/* Return type of the calls OSEK COM */ +typedef UI_8 t_status_type; + +/* Structure of data type passed by reference in */ +/* the calls of OSEK COM */ +typedef void *t_application_data_ref; +typedef void *t_length_ref; + +/* Flag types of OSEK COM */ +typedef enum { + COM_FALSE = 0x00, /* Flag down */ + COM_TRUE = 0x01 /* Flag up */ +} t_flag_value; + +/* Stop mode of OSEK COM */ +typedef enum { + COM_SHUTDOWN_IMMEDIATE = 0 /* Apagat immediat */ +} t_com_shutdown_mode_type; + +/* Initialize mode of OSEK COM */ +typedef enum { + COM_NORMAL_MODE = 0 /* No es processen trames de COM de Debug */ +} t_com_application_mode_type; + +#endif + +/*--------------------------- global variables ---------------------------*/ + + +/*------------------------- prototips de funcions ------------------------*/ + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reception callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InternalOsekComRxNotifCallbackMMC(t_com_buf_hdl bhdl); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Transmission callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL InternalOsekComTxReqCallbackMMC(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Notifying transmission callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InternalOsekComTxNotifCallbackMMC(t_com_buf_hdl bhdl); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service of OSEK COM in the selected mode +| +| ------------------------------------------------- -------------------------- +| Explanation of arguments: +| App_mode: activation model of communications. +| Result: if all goes well E_OK +| Another code (see t_status_type) if an error occurs. +|--------------------------------------------------------------------------- +| Temporitzacio: +| Tmax: ?? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type InternalStartCom(t_com_application_mode_type app_mode); + +/***************************************************************************** +| Portability: Generic +| ---------------------------------------------------------------------------- +| Contract transactions: +| * Service inquiry mode in which communications are initialized +| COM. +| * If this service is called before initializing the communications +| Random mode will be returned. +| --------------------------------------------------------------------------- +| Explanation of arguments: +| Result: how they have been enabled communications +| (See t_com_application_mode_type) +| --------------------------------------------------------------------------- +| Timing: +| Tmax: 15 cpu cycles | O (n): CTE +/ --------------------------------------------------------------------------- */ +t_com_application_mode_type InternalGetComApplicationMode(void); + +/***************************************************************************** +| Portability: Generic +| ---------------------------------------------------------------------------- +| Contract transactions: +| * Service stopped the activity of OSEK COM communications. +| * This service stops the transmission of messages periodically. +| * After calling this service communications can be reestablished +| Calling service StartCom. (At no time this service modifies the state +| COM driver). +| --------------------------------------------------------------------------- +| Explanation of arguments: +| App_mode: Stop mode communications. +| Result: if all goes well E_OK +| Another code (see t_status_type) if an error occurs. +| --------------------------------------------------------------------------- +| Timing: +| Tmax:? cpu cycles | O (n): CTE +/ --------------------------------------------------------------------------- */ +t_status_type InternalStopCom(t_com_shutdown_mode_type shtdwn_mode); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service transmission of periodic or mix frames. +| * If the transmission of periodic or mix frames is initialized, this service +| reboot the communication. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| E_OK in case of no errors +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type InternalStartPeriodic(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Stop service transmission of periodic or mix frames. +| * If the transmission of periodic or mix frames is stopped, you can restart +| it calling the StartPeriodic service. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| E_OK in case of no errors +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type InternalStopPeriodic(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * This service updates the application signal referenced by >data_ref< with +| the data in the internal object identified by >message<. +| * This service will reset the class 1 and 3 flags associated to >message< +| * If >message< is an unqueued signal the service will return the last value +| received. +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not suported) +| * The software engineer is resposible of granting that the parameter >data_ref< +| points to an address correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the received signal. +| data_ref: Pointer to the application area where to store the received signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent or to a dynamiclength or zero-length signal +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the signal queue identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU resources data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type InternalReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * This service updates the internal signal object identified by >message< +| with the application signal referenced by the >data_ref< parameter. +| * This service will reset the class 2 and 4 flags associated to >message< +| * If >message< has the Triggered Transfer Property, the update is followed +| by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode; +| in this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| caused by the update. +| * The software engineer is resposible of granting that the parameter >data_ref< +| points to an address correctly allocated and compatible in size with the +| transmited signal type +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| (void)SendMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the transmited signal. +| data_ref: Pointer to the application signal where is the value to be transmited. +| return: +| E_OK in case of no errors +| E_COM_ID is case the parameter >message< is out of range or if it refers +| to a message that is received or to a dynamic-length or +| zero-length message. +| other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#define OSEK_INTERNALSENDMESSAGE +t_status_type InternalSendMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service message with a different value than configuration. +| * The software engineer is responsible of garanting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the received signal. +| data_ref: Pointer to the application area where to store the received signal. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type InternalInitMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_flag_value InternalReadFlagComTrafficMMC(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InternalResetFlagComTrafficMMC(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Consult service for the notify Rx Rx_Error Tx Tx_Error +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal flag. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_flag_value InternalReadFlagRxSig(t_symbolic_name message); +t_flag_value InternalReadFlagRxSigSMC_MLX_cook_die1(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_cook_die2(void); +t_flag_value InternalReadFlagRxSigSMC_mode_contoler(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_current_position(void); +t_flag_value InternalReadFlagRxSigSMC_vbat_motor_sup_sns(void); +t_flag_value InternalReadFlagRxSigSMC_bmar_sns(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_raw_die1(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_raw_die2(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_temperature_die1(void); +t_flag_value InternalReadFlagRxSigSMC_MLX_temperature_die2(void); +t_flag_value InternalReadFlagRxSigSMC_fw_version(void); +t_flag_value InternalReadFlagRxSigSMC_melexis_diagnostics(void); +t_flag_value InternalReadFlagRxSigSMC_relay_status(void); +t_flag_value InternalReadFlagRxSigSMC_calibration_NOP(void); +t_flag_value InternalReadFlagRxErrorSig(t_symbolic_name message); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_cook_die1(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_cook_die2(void); +t_flag_value InternalReadFlagRxErrorSigSMC_mode_contoler(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_current_position(void); +t_flag_value InternalReadFlagRxErrorSigSMC_vbat_motor_sup_sns(void); +t_flag_value InternalReadFlagRxErrorSigSMC_bmar_sns(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_raw_die1(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_raw_die2(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_temperature_die1(void); +t_flag_value InternalReadFlagRxErrorSigSMC_MLX_temperature_die2(void); +t_flag_value InternalReadFlagRxErrorSigSMC_fw_version(void); +t_flag_value InternalReadFlagRxErrorSigSMC_melexis_diagnostics(void); +t_flag_value InternalReadFlagRxErrorSigSMC_relay_status(void); +t_flag_value InternalReadFlagRxErrorSigSMC_calibration_NOP(void); +t_flag_value InternalReadFlagTxSig(t_symbolic_name message); +t_flag_value InternalReadFlagTxSigMMC_p_uds_die1_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_r_uds_die1_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_n_uds_die1_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_d_uds_die1_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_p_uds_die2_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_r_uds_die2_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_n_uds_die2_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_d_uds_die2_setpoint(void); +t_flag_value InternalReadFlagTxSigMMC_p_lock_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_p_r_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_r_p_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_r_n_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_n_r_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_n_d_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_d_n_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_d_lock_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_uds_setpoints_rc(void); +t_flag_value InternalReadFlagTxSigMMC_uds_setpoints_crc(void); +t_flag_value InternalReadFlagTxSigMMC_p_out_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_d_out_uds_offset(void); +t_flag_value InternalReadFlagTxSigMMC_SCU_GearboxPositionTarget(void); +t_flag_value InternalReadFlagTxSigMMC_GearLeverPositionExtended_v2(void); +t_flag_value InternalReadFlagTxSigMMC_Clock_ATCU_A112(void); +t_flag_value InternalReadFlagTxSigMMC_CRC_ATCU_A112(void); +t_flag_value InternalReadFlagTxSigMMC_IgnitionSupplyConfirmation(void); +t_flag_value InternalReadFlagTxSigMMC_ACTU_uds_mode(void); +t_flag_value InternalReadFlagTxSigMMC_mlx_position(void); +t_flag_value InternalReadFlagTxSigMMC_melexis_virtual_die1(void); +t_flag_value InternalReadFlagTxSigMMC_melexis_virtual_die2(void); +t_flag_value InternalReadFlagTxSigMMC_relay_selfcheck_request(void); +t_flag_value InternalReadFlagTxSigMMC_application_mode(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reset service for the notify Rx Rx_Error Tx Tx_Error +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal flag. +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InternalResetFlagRxSig(t_symbolic_name message); +void InternalResetFlagRxSigSMC_MLX_cook_die1(void); +void InternalResetFlagRxSigSMC_MLX_cook_die2(void); +void InternalResetFlagRxSigSMC_mode_contoler(void); +void InternalResetFlagRxSigSMC_MLX_current_position(void); +void InternalResetFlagRxSigSMC_vbat_motor_sup_sns(void); +void InternalResetFlagRxSigSMC_bmar_sns(void); +void InternalResetFlagRxSigSMC_MLX_raw_die1(void); +void InternalResetFlagRxSigSMC_MLX_raw_die2(void); +void InternalResetFlagRxSigSMC_MLX_temperature_die1(void); +void InternalResetFlagRxSigSMC_MLX_temperature_die2(void); +void InternalResetFlagRxSigSMC_fw_version(void); +void InternalResetFlagRxSigSMC_melexis_diagnostics(void); +void InternalResetFlagRxSigSMC_relay_status(void); +void InternalResetFlagRxSigSMC_calibration_NOP(void); +void InternalResetFlagRxErrorSig(t_symbolic_name message); +void InternalResetFlagRxErrorSigSMC_MLX_cook_die1(void); +void InternalResetFlagRxErrorSigSMC_MLX_cook_die2(void); +void InternalResetFlagRxErrorSigSMC_mode_contoler(void); +void InternalResetFlagRxErrorSigSMC_MLX_current_position(void); +void InternalResetFlagRxErrorSigSMC_vbat_motor_sup_sns(void); +void InternalResetFlagRxErrorSigSMC_bmar_sns(void); +void InternalResetFlagRxErrorSigSMC_MLX_raw_die1(void); +void InternalResetFlagRxErrorSigSMC_MLX_raw_die2(void); +void InternalResetFlagRxErrorSigSMC_MLX_temperature_die1(void); +void InternalResetFlagRxErrorSigSMC_MLX_temperature_die2(void); +void InternalResetFlagRxErrorSigSMC_fw_version(void); +void InternalResetFlagRxErrorSigSMC_melexis_diagnostics(void); +void InternalResetFlagRxErrorSigSMC_relay_status(void); +void InternalResetFlagRxErrorSigSMC_calibration_NOP(void); +void InternalResetFlagTxSig(t_symbolic_name message); +void InternalResetFlagTxSigMMC_p_uds_die1_setpoint(void); +void InternalResetFlagTxSigMMC_r_uds_die1_setpoint(void); +void InternalResetFlagTxSigMMC_n_uds_die1_setpoint(void); +void InternalResetFlagTxSigMMC_d_uds_die1_setpoint(void); +void InternalResetFlagTxSigMMC_p_uds_die2_setpoint(void); +void InternalResetFlagTxSigMMC_r_uds_die2_setpoint(void); +void InternalResetFlagTxSigMMC_n_uds_die2_setpoint(void); +void InternalResetFlagTxSigMMC_d_uds_die2_setpoint(void); +void InternalResetFlagTxSigMMC_p_lock_uds_offset(void); +void InternalResetFlagTxSigMMC_p_r_uds_offset(void); +void InternalResetFlagTxSigMMC_r_p_uds_offset(void); +void InternalResetFlagTxSigMMC_r_n_uds_offset(void); +void InternalResetFlagTxSigMMC_n_r_uds_offset(void); +void InternalResetFlagTxSigMMC_n_d_uds_offset(void); +void InternalResetFlagTxSigMMC_d_n_uds_offset(void); +void InternalResetFlagTxSigMMC_d_lock_uds_offset(void); +void InternalResetFlagTxSigMMC_uds_setpoints_rc(void); +void InternalResetFlagTxSigMMC_uds_setpoints_crc(void); +void InternalResetFlagTxSigMMC_p_out_uds_offset(void); +void InternalResetFlagTxSigMMC_d_out_uds_offset(void); +void InternalResetFlagTxSigMMC_SCU_GearboxPositionTarget(void); +void InternalResetFlagTxSigMMC_GearLeverPositionExtended_v2(void); +void InternalResetFlagTxSigMMC_Clock_ATCU_A112(void); +void InternalResetFlagTxSigMMC_CRC_ATCU_A112(void); +void InternalResetFlagTxSigMMC_IgnitionSupplyConfirmation(void); +void InternalResetFlagTxSigMMC_ACTU_uds_mode(void); +void InternalResetFlagTxSigMMC_mlx_position(void); +void InternalResetFlagTxSigMMC_melexis_virtual_die1(void); +void InternalResetFlagTxSigMMC_melexis_virtual_die2(void); +void InternalResetFlagTxSigMMC_relay_selfcheck_request(void); +void InternalResetFlagTxSigMMC_application_mode(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Main task of OSEK/COM that must be called periodically in +| the main loop of the program. +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void InternalOsekComTask(void); + +#endif + diff --git a/firmware/src/DiagnosticR/FicOsek/FicOsekComSent.h b/firmware/src/DiagnosticR/FicOsek/FicOsekComSent.h new file mode 100644 index 0000000..500cb11 --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicOsekComSent.h @@ -0,0 +1,316 @@ + +#ifndef _Sent_FICOSEKCOM_H +#define _Sent_FICOSEKCOM_H + +/*-------------------------------- Includes ------------------------------*/ +#include "Global.h" +#include "SentDriver.h" + +/*-------------------------------- Defines -------------------------------*/ + +/* Theoretical time between two consecutive executions of FicOsekCom task */ +#define SENTFICOSEK_COM_TASK_TICKS ((t_timer_time)2) + +/* Return type of the calls OSEK COM */ +#ifndef STD_TYPES_H + #define E_OK ((UI_8)0x00) /* Service call has succeeded */ +#endif +#define E_COM_ID ((UI_8)0x01) /* Given message or mode identifier */ + /* is out of range or invalid */ +#define E_COM_LENGTH ((UI_8)0x02) /* Given data length is out of range */ +#define E_COM_LIMIT ((UI_8)0x03) /* Overflow of message queue */ +#define E_COM_NOMSG ((UI_8)0x04) /* Message queue is empty */ +#define E_COM_SYS_NOINIT ((UI_8)0x05) /* User defined E_COM_SYS_?? */ + +/* Node id */ +#define NODE_ID_MASK ((UI_16) 0xF000U) /* Mask to get nodes id */ +#define NODE_ID_DEFC_SENT (((UI_16) 0x1000U) & NODE_ID_MASK) /* Symbolic name of the node DEFC_SENT */ + +/* Symbolic names for Rx signals */ +#define SIG_MLX_DIE1_ANGLE (((UI_16) 1) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE1_ANGLE */ +#define SIG_MLX_DIE1_RC (((UI_16) 2) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE1_RC */ +#define SIG_MLX_DIE1_ST (((UI_16) 3) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE1_ST */ +#define SIG_MLX_DIE2_ANGLE (((UI_16) 4) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE2_ANGLE */ +#define SIG_MLX_DIE2_RC (((UI_16) 5) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE2_RC */ +#define SIG_MLX_DIE2_ST (((UI_16) 6) | NODE_ID_DEFC_SENT) /* Symbolic name of the signal MLX_DIE2_ST */ +/* Last Rx signal */ +#define SENTLAST_RX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_MLX_DIE2_ST) + +/* Last OsekCom signal */ +#define SENTLAST_OSEK_COM_SIGNAL_SYMBOLIC_NAME ((UI_16) 6) + +/* Symbolic names for Dummy signal */ +#define SENTSIGDUMMY ((UI_16)0x0FFF) /* Symbolic name of the signal SIGDUMMY */ + + +/*----------------------------- Data Types -------------------------------*/ +/* Type definition of internal signals */ +typedef UI_16 t_sig_mlx_die1_angle; +typedef UI_8 t_sig_mlx_die1_st; +typedef UI_8 t_sig_mlx_die1_rc; +typedef UI_16 t_sig_mlx_die2_angle; +typedef UI_8 t_sig_mlx_die2_rc; +typedef UI_8 t_sig_mlx_die2_st; + + +#ifndef _FICOSEKCOM_H +#define _FICOSEKCOM_H + +/* Type definition of the symbolic names for signals */ +typedef UI_16 t_symbolic_name; +typedef UI_16 t_symbolic_frm_name; + +/* Return type of the calls OSEK COM */ +typedef UI_8 t_status_type; + +/* Structure of data type passed by reference in */ +/* the calls of OSEK COM */ +typedef void *t_application_data_ref; +typedef void *t_length_ref; + +/* Flag types of OSEK COM */ +typedef enum { + COM_FALSE = 0x00, /* Flag down */ + COM_TRUE = 0x01 /* Flag up */ +} t_flag_value; + +/* Stop mode of OSEK COM */ +typedef enum { + COM_SHUTDOWN_IMMEDIATE = 0 /* Apagat immediat */ +} t_com_shutdown_mode_type; + +/* Initialize mode of OSEK COM */ +typedef enum { + COM_NORMAL_MODE = 0 /* No es processen trames de COM de Debug */ +} t_com_application_mode_type; + +#endif + + + +/*--------------------------- Global Variables ---------------------------*/ + + +/* --------------------------- Routine Prototypes --------------------------- */ + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reception of a new frame notification callback +| * This callback must be launched by the lower COM driver upon the reception +| of a new frame. +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the received frame is stored. +/---------------------------------------------------------------------------*/ +void SentOsekComRxNotifCallbackDEFC_SENT(t_com_buf_hdl bhdl); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to initialize OsekCom stack +| +| ------------------------------------------------- -------------------------- +| Parameters description: +| app_mode: OsekCom initialization mode (See t_com_application_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SentStartCom(t_com_application_mode_type app_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to inquiry in which mode OsekCom has been initialized. +| * If this service is called before initializing the communications stack +| a random mode will be returned. +| --------------------------------------------------------------------------- +| Parameters description: +| return: OsekCom initialization mode(See t_com_application_mode_type) +/ --------------------------------------------------------------------------- */ +t_com_application_mode_type SentGetComApplicationMode(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to close the OsekCom stack. +| * This service stops the transmission of periodic frames. +| * After calling this service communications could be re-established +| calling again service StartCom. +| * This service does not change the state of any lower COM driver. +| --------------------------------------------------------------------------- +| Parameters description: +| shtdwn_mode: OsekCom stop mode (See t_com_shutdown_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/ --------------------------------------------------------------------------- */ +t_status_type SentStopCom(t_com_shutdown_mode_type shtdwn_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to start the transmission of periodic or mixed frames. +| * If this service is re-executed then transmission timers will be re-started. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SentStartPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to stop the transmission of periodic or mixed frames. +| * To re-start the transmission of periodic or mixed frames service +| StartPeriodic must be called. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SentStopPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates the application variable referenced by >data_ref< with +| the data stored in the internal stack for the object identified by >message<. +| * This service will reset the class 1 (RxNotif) and 3 (RxErrorNotif) flags +| associated to >message< +| * If >message< is an enqueued signal the service will return the data +| stored in the internal stack (initial value / last received value / last value +| set with InitMessage) +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not supported) +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be retrieved. +| data_ref: Pointer to a variable where to store the requested signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent, dynamic length or zero-length +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the queue of the signal identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SentReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< +| * This service will not reset any class flags associated to >message< +| * This service will not initiate any transmission. +| * The user is responsible of granting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| data_ref: Pointer to a variable containing the data. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SentInitMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if has not been detected any communication activity since +| last clear +| COM_TRUE if has been detected communication activity since last clear +/---------------------------------------------------------------------------*/ +t_flag_value SentReadFlagComTrafficDEFC_SENT(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void SentResetFlagComTrafficDEFC_SENT(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to retrieve the state of class 1 (RxNotif), +| class 3 (Rx_ErrorNotif), class 2 (TxNotif) and class 4 (Tx_ErrorNotif) flags +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +/---------------------------------------------------------------------------*/ +t_flag_value SentReadFlagRxSig(t_symbolic_name message); +t_flag_value SentReadFlagRxSigMLX_DIE1_ANGLE(void); +t_flag_value SentReadFlagRxSigMLX_DIE2_ANGLE(void); +t_flag_value SentReadFlagRxErrorSig(t_symbolic_name message); +t_flag_value SentReadFlagRxErrorSigMLX_DIE1_ANGLE(void); +t_flag_value SentReadFlagRxErrorSigMLX_DIE2_ANGLE(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the notify class 1 (RxNotif) class 3 (RxErrorNotif) +| class 2 (TxNotif) and class 4 (TxErrorNotif) +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +/---------------------------------------------------------------------------*/ +void SentResetFlagRxSig(t_symbolic_name message); +void SentResetFlagRxSigMLX_DIE1_ANGLE(void); +void SentResetFlagRxSigMLX_DIE2_ANGLE(void); +void SentResetFlagRxErrorSig(t_symbolic_name message); +void SentResetFlagRxErrorSigMLX_DIE1_ANGLE(void); +void SentResetFlagRxErrorSigMLX_DIE2_ANGLE(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Main runnable of the OsekCom stack intended to be called periodically by +| the system scheduler with a period equal to SENTFICOSEK_COM_TASK_TICKS +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void SentOsekComTask(void); + +#endif + diff --git a/firmware/src/DiagnosticR/FicOsek/FicOsekComSpi.h b/firmware/src/DiagnosticR/FicOsek/FicOsekComSpi.h new file mode 100644 index 0000000..c41f256 --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicOsekComSpi.h @@ -0,0 +1,550 @@ + +#ifndef _Spi_FICOSEKCOM_H +#define _Spi_FICOSEKCOM_H + +/*-------------------------------- includes ------------------------------*/ +#include "Global.h" +#include "SpiFrameWrapper.h" + +/*-------------------------------- defines -------------------------------*/ +/* Return type of the calls OSEK COM */ +#ifndef STD_TYPES_H + #define E_OK ((UI_8)0x00) /* Service call has succeeded */ +#endif +#define E_COM_ID ((UI_8)0x01) /* Given message or mode identifier */ + /* is out of range or invalid */ +#define E_COM_LENGTH ((UI_8)0x02) /* Given data length is out of range */ +#define E_COM_LIMIT ((UI_8)0x03) /* Overflow of message queue */ +#define E_COM_NOMSG ((UI_8)0x04) /* Message queue is empty */ +#define E_COM_SYS_NOINIT ((UI_8)0x05) /* User defined E_COM_SYS_?? */ + + +/* Valors admisibles pel senyal sig_DIE1_M0_DIAG */ +#define SIG_DIE1_M0_DIAG_F_DIAG_SEQUENCE_NOT_FINISHED ((t_sig_die1_m0_diag) 0) +#define SIG_DIE1_M0_DIAG_DIAG_FAIL ((t_sig_die1_m0_diag) 1) +#define SIG_DIE1_M0_DIAG_DIAGC_PASS_(PREVIOUS_CYCLE) ((t_sig_die1_m0_diag) 2) +#define SIG_DIE1_M0_DIAG_DIAG_PASS_NEW_CYCLE_COMPLETED ((t_sig_die1_m0_diag) 3) + +/* Valors admisibles pel senyal sig_DIE1_M1_DIAG */ +#define SIG_DIE1_M1_DIAG_F_DIAG_SEQUENCE_NOT_FINISHED ((t_sig_die1_m1_diag) 0) +#define SIG_DIE1_M1_DIAG_DIAG_FAIL ((t_sig_die1_m1_diag) 1) +#define SIG_DIE1_M1_DIAG_DIAGC_PASS_(PREVIOUS_CYCLE) ((t_sig_die1_m1_diag) 2) +#define SIG_DIE1_M1_DIAG_DIAG_PASS_NEW_CYCLE_COMPLETED ((t_sig_die1_m1_diag) 3) + +/* Valors admisibles pel senyal sig_DIE2_M0_DIAG */ +#define SIG_DIE2_M0_DIAG_F_DIAG_SEQUENCE_NOT_FINISHED ((t_sig_die2_m0_diag) 0) +#define SIG_DIE2_M0_DIAG_DIAG_FAIL ((t_sig_die2_m0_diag) 1) +#define SIG_DIE2_M0_DIAG_DIAGC_PASS_(PREVIOUS_CYCLE) ((t_sig_die2_m0_diag) 2) +#define SIG_DIE2_M0_DIAG_DIAG_PASS_NEW_CYCLE_COMPLETED ((t_sig_die2_m0_diag) 3) + +/* Valors admisibles pel senyal sig_DIE2_M1_DIAG */ +#define SIG_DIE2_M1_DIAG_F_DIAG_SEQUENCE_NOT_FINISHED ((t_sig_die2_m1_diag) 0) +#define SIG_DIE2_M1_DIAG_DIAG_FAIL ((t_sig_die2_m1_diag) 1) +#define SIG_DIE2_M1_DIAG_DIAGC_PASS_(PREVIOUS_CYCLE) ((t_sig_die2_m1_diag) 2) +#define SIG_DIE2_M1_DIAG_DIAG_PASS_NEW_CYCLE_COMPLETED ((t_sig_die2_m1_diag) 3) +/* Node id */ +#define NODE_ID_MASK ((UI_16) 0xF000) /* Mask to get nodes id */ +#define NODE_ID_ECU_LITE (((UI_16) 0x1000) & NODE_ID_MASK) /* Symbolic name of the node ECU_Lite */ + +/* Symbolic names for Tx signals with static length */ +/* First tx signal */ +#define SPIFIRST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_MASTER_M0_RST_DIE1) +#define SIG_MASTER_M0_RST_DIE1 (((UI_16) 1) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M0_RST_DIE1 */ +#define SIG_MASTER_M0_RST_DIE2 (((UI_16) 2) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M0_RST_DIE2 */ +#define SIG_MASTER_M0_TIMEOUT_VALUE_DIE1 (((UI_16) 3) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M0_TIMEOUT_VALUE_DIE1 */ +#define SIG_MASTER_M0_TIMEOUT_VALUE_DIE2 (((UI_16) 4) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M0_TIMEOUT_VALUE_DIE2 */ +#define SIG_MASTER_M3_ADD0_DIE1 (((UI_16) 5) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M3_ADD0_DIE1 */ +#define SIG_MASTER_M3_ADD0_DIE2 (((UI_16) 6) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M3_ADD0_DIE2 */ +#define SIG_MASTER_M3_ADD1_DIE1 (((UI_16) 7) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M3_ADD1_DIE1 */ +#define SIG_MASTER_M3_ADD1_DIE2 (((UI_16) 8) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M3_ADD1_DIE2 */ +#define SIG_MASTER_M7_KEY_DIE1 (((UI_16) 9) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M7_KEY_DIE1 */ +#define SIG_MASTER_M7_KEY_DIE2 (((UI_16) 10) | NODE_ID_ECU_LITE) /* Symbolic name of the signal MASTER_M7_KEY_DIE2 */ +/* Last tx signal */ +#define SPILAST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_MASTER_M7_KEY_DIE2) + + +/* Symbolic names for Rx signals */ +#define SIG_DIE1_M0_ALPHA (((UI_16) 11) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M0_ALPHA */ +#define SIG_DIE1_M0_DIAG (((UI_16) 12) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M0_DIAG */ +#define SIG_DIE1_M0_VG (((UI_16) 13) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M0_VG */ +#define SIG_DIE1_M1_ALPHA (((UI_16) 14) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M1_ALPHA */ +#define SIG_DIE1_M1_BETA (((UI_16) 15) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M1_BETA */ +#define SIG_DIE1_M1_DIAG (((UI_16) 16) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M1_DIAG */ +#define SIG_DIE1_M1_VG (((UI_16) 17) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M1_VG */ +#define SIG_DIE1_M4_DATA_AT_ADD0 (((UI_16) 18) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M4_DATA_AT_ADD0 */ +#define SIG_DIE1_M4_DATA_AT_ADD1 (((UI_16) 19) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M4_DATA_AT_ADD1 */ +#define SIG_DIE1_M8_INVERTED_KEY_ECHO (((UI_16) 20) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M8_INVERTED_KEY_ECHO */ +#define SIG_DIE1_M8_KEY_ECHO (((UI_16) 21) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE1_M8_KEY_ECHO */ +#define SIG_DIE2_M0_ALPHA (((UI_16) 22) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M0_ALPHA */ +#define SIG_DIE2_M0_DIAG (((UI_16) 23) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M0_DIAG */ +#define SIG_DIE2_M0_VG (((UI_16) 24) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M0_VG */ +#define SIG_DIE2_M1_ALPHA (((UI_16) 25) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M1_ALPHA */ +#define SIG_DIE2_M1_BETA (((UI_16) 26) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M1_BETA */ +#define SIG_DIE2_M1_DIAG (((UI_16) 27) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M1_DIAG */ +#define SIG_DIE2_M1_VG (((UI_16) 28) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M1_VG */ +#define SIG_DIE2_M4_DATA_AT_ADD0 (((UI_16) 29) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M4_DATA_AT_ADD0 */ +#define SIG_DIE2_M4_DATA_AT_ADD1 (((UI_16) 30) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M4_DATA_AT_ADD1 */ +#define SIG_DIE2_M8_INVERTED_KEY_ECHO (((UI_16) 31) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M8_INVERTED_KEY_ECHO */ +#define SIG_DIE2_M8_KEY_ECHO (((UI_16) 32) | NODE_ID_ECU_LITE) /* Symbolic name of the signal DIE2_M8_KEY_ECHO */ +/* Last Rx signal */ +#define SPILAST_RX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_DIE2_M8_KEY_ECHO) + + +/* Symbolic names for Dummy signal */ +#define SPISIGDUMMY ((UI_16)0x0FFF) /* Symbolic name of the signal SIGDUMMY */ + + +/*----------------------------- data types -------------------------------*/ +/* Type definition of internal signals */ +typedef UI_16 t_sig_die1_m0_alpha; +typedef UI_8 t_sig_die1_m0_vg; +typedef UI_8 t_sig_die1_m0_diag; +typedef UI_16 t_sig_die1_m1_alpha; +typedef UI_16 t_sig_die1_m1_beta; +typedef UI_8 t_sig_die1_m1_diag; +typedef UI_8 t_sig_die1_m1_vg; +typedef UI_16 t_sig_die1_m4_data_at_add0; +typedef UI_16 t_sig_die1_m4_data_at_add1; +typedef UI_16 t_sig_die1_m8_key_echo; +typedef UI_16 t_sig_die1_m8_inverted_key_echo; +typedef UI_16 t_sig_die2_m0_alpha; +typedef UI_8 t_sig_die2_m0_diag; +typedef UI_8 t_sig_die2_m0_vg; +typedef UI_16 t_sig_die2_m1_alpha; +typedef UI_16 t_sig_die2_m1_beta; +typedef UI_8 t_sig_die2_m1_diag; +typedef UI_8 t_sig_die2_m1_vg; +typedef UI_16 t_sig_die2_m4_data_at_add0; +typedef UI_16 t_sig_die2_m4_data_at_add1; +typedef UI_16 t_sig_die2_m8_key_echo; +typedef UI_16 t_sig_die2_m8_inverted_key_echo; +typedef UI_8 t_sig_master_m0_rst_die1; +typedef UI_16 t_sig_master_m0_timeout_value_die1; +typedef UI_16 t_sig_master_m7_key_die1; +typedef UI_16 t_sig_master_m3_add0_die1; +typedef UI_16 t_sig_master_m3_add1_die1; +typedef UI_8 t_sig_master_m0_rst_die2; +typedef UI_16 t_sig_master_m0_timeout_value_die2; +typedef UI_16 t_sig_master_m3_add0_die2; +typedef UI_16 t_sig_master_m3_add1_die2; +typedef UI_16 t_sig_master_m7_key_die2; + + +#ifndef _FICOSEKCOM_H +#define _FICOSEKCOM_H + +/* Type definition of the symbolic names for signals */ +typedef UI_16 t_symbolic_name; +typedef UI_16 t_symbolic_frm_name; + +/* Return type of the calls OSEK COM */ +typedef UI_8 t_status_type; + +/* Structure of data type passed by reference in */ +/* the calls of OSEK COM */ +typedef void *t_application_data_ref; +typedef void *t_length_ref; + +/* Flag types of OSEK COM */ +typedef enum { + COM_FALSE = 0x00, /* Flag down */ + COM_TRUE = 0x01 /* Flag up */ +} t_flag_value; + +/* Stop mode of OSEK COM */ +typedef enum { + COM_SHUTDOWN_IMMEDIATE = 0 /* Apagat immediat */ +} t_com_shutdown_mode_type; + +/* Initialize mode of OSEK COM */ +typedef enum { + COM_NORMAL_MODE = 0 /* No es processen trames de COM de Debug */ +} t_com_application_mode_type; + +#endif + +/*--------------------------- global variables ---------------------------*/ + + +/*------------------------- prototips de funcions ------------------------*/ + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reception callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void SpiOsekComRxNotifCallbackECU_Lite(t_com_buf_hdl bhdl); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Transmission callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +BOOL SpiOsekComTxReqCallbackECU_Lite(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Notifying transmission callback Routine of COM frames +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void SpiOsekComTxNotifCallbackECU_Lite(t_com_buf_hdl bhdl); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service of OSEK COM in the selected mode +| +| ------------------------------------------------- -------------------------- +| Explanation of arguments: +| App_mode: activation model of communications. +| Result: if all goes well E_OK +| Another code (see t_status_type) if an error occurs. +|--------------------------------------------------------------------------- +| Temporitzacio: +| Tmax: ?? cicles cpu | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type SpiStartCom(t_com_application_mode_type app_mode); + +/***************************************************************************** +| Portability: Generic +| ---------------------------------------------------------------------------- +| Contract transactions: +| * Service inquiry mode in which communications are initialized +| COM. +| * If this service is called before initializing the communications +| Random mode will be returned. +| --------------------------------------------------------------------------- +| Explanation of arguments: +| Result: how they have been enabled communications +| (See t_com_application_mode_type) +| --------------------------------------------------------------------------- +| Timing: +| Tmax: 15 cpu cycles | O (n): CTE +/ --------------------------------------------------------------------------- */ +t_com_application_mode_type SpiGetComApplicationMode(void); + +/***************************************************************************** +| Portability: Generic +| ---------------------------------------------------------------------------- +| Contract transactions: +| * Service stopped the activity of OSEK COM communications. +| * This service stops the transmission of messages periodically. +| * After calling this service communications can be reestablished +| Calling service StartCom. (At no time this service modifies the state +| COM driver). +| --------------------------------------------------------------------------- +| Explanation of arguments: +| App_mode: Stop mode communications. +| Result: if all goes well E_OK +| Another code (see t_status_type) if an error occurs. +| --------------------------------------------------------------------------- +| Timing: +| Tmax:? cpu cycles | O (n): CTE +/ --------------------------------------------------------------------------- */ +t_status_type SpiStopCom(t_com_shutdown_mode_type shtdwn_mode); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service transmission of periodic or mix frames. +| * If the transmission of periodic or mix frames is initialized, this service +| reboot the communication. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| E_OK in case of no errors +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type SpiStartPeriodic(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Stop service transmission of periodic or mix frames. +| * If the transmission of periodic or mix frames is stopped, you can restart +| it calling the StartPeriodic service. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| E_OK in case of no errors +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type SpiStopPeriodic(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * This service updates the application signal referenced by >data_ref< with +| the data in the internal object identified by >message<. +| * This service will reset the class 1 and 3 flags associated to >message< +| * If >message< is an unqueued signal the service will return the last value +| received. +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not suported) +| * The software engineer is resposible of granting that the parameter >data_ref< +| points to an address correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the received signal. +| data_ref: Pointer to the application area where to store the received signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent or to a dynamiclength or zero-length signal +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the signal queue identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU resources data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type SpiReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * This service updates the internal signal object identified by >message< +| with the application signal referenced by the >data_ref< parameter. +| * This service will reset the class 2 and 4 flags associated to >message< +| * If >message< has the Triggered Transfer Property, the update is followed +| by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode; +| in this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| caused by the update. +| * The software engineer is resposible of granting that the parameter >data_ref< +| points to an address correctly allocated and compatible in size with the +| transmited signal type +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| (void)SendMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the transmited signal. +| data_ref: Pointer to the application signal where is the value to be transmited. +| return: +| E_OK in case of no errors +| E_COM_ID is case the parameter >message< is out of range or if it refers +| to a message that is received or to a dynamic-length or +| zero-length message. +| other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +#define OSEK_SPISENDMESSAGE +t_status_type SpiSendMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Initialize service message with a different value than configuration. +| * The software engineer is responsible of garanting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the received signal. +| data_ref: Pointer to the application area where to store the received signal. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_status_type SpiInitMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_flag_value SpiReadFlagComTrafficECU_Lite(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void SpiResetFlagComTrafficECU_Lite(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Consult service for the notify Rx Rx_Error Tx Tx_Error +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal flag. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +t_flag_value SpiReadFlagRxSig(t_symbolic_name message); +t_flag_value SpiReadFlagRxSigDIE1_M0_ALPHA(void); +t_flag_value SpiReadFlagRxSigDIE1_M0_VG(void); +t_flag_value SpiReadFlagRxSigDIE1_M0_DIAG(void); +t_flag_value SpiReadFlagRxSigDIE1_M1_ALPHA(void); +t_flag_value SpiReadFlagRxSigDIE1_M1_BETA(void); +t_flag_value SpiReadFlagRxSigDIE1_M1_DIAG(void); +t_flag_value SpiReadFlagRxSigDIE1_M1_VG(void); +t_flag_value SpiReadFlagRxSigDIE1_M4_DATA_AT_ADD0(void); +t_flag_value SpiReadFlagRxSigDIE1_M4_DATA_AT_ADD1(void); +t_flag_value SpiReadFlagRxSigDIE1_M8_KEY_ECHO(void); +t_flag_value SpiReadFlagRxSigDIE1_M8_INVERTED_KEY_ECHO(void); +t_flag_value SpiReadFlagRxSigDIE2_M0_ALPHA(void); +t_flag_value SpiReadFlagRxSigDIE2_M0_DIAG(void); +t_flag_value SpiReadFlagRxSigDIE2_M0_VG(void); +t_flag_value SpiReadFlagRxSigDIE2_M1_ALPHA(void); +t_flag_value SpiReadFlagRxSigDIE2_M1_BETA(void); +t_flag_value SpiReadFlagRxSigDIE2_M1_DIAG(void); +t_flag_value SpiReadFlagRxSigDIE2_M1_VG(void); +t_flag_value SpiReadFlagRxSigDIE2_M4_DATA_AT_ADD0(void); +t_flag_value SpiReadFlagRxSigDIE2_M4_DATA_AT_ADD1(void); +t_flag_value SpiReadFlagRxSigDIE2_M8_KEY_ECHO(void); +t_flag_value SpiReadFlagRxSigDIE2_M8_INVERTED_KEY_ECHO(void); +t_flag_value SpiReadFlagRxErrorSig(t_symbolic_name message); +t_flag_value SpiReadFlagRxErrorSigDIE1_M0_ALPHA(void); +t_flag_value SpiReadFlagRxErrorSigDIE1_M4_DATA_AT_ADD0(void); +t_flag_value SpiReadFlagRxErrorSigDIE2_M0_ALPHA(void); +t_flag_value SpiReadFlagTxSig(t_symbolic_name message); +t_flag_value SpiReadFlagTxSigMASTER_M0_RST_DIE1(void); +t_flag_value SpiReadFlagTxSigMASTER_M0_TIMEOUT_VALUE_DIE1(void); +t_flag_value SpiReadFlagTxSigMASTER_M7_KEY_DIE1(void); +t_flag_value SpiReadFlagTxSigMASTER_M3_ADD0_DIE1(void); +t_flag_value SpiReadFlagTxSigMASTER_M3_ADD1_DIE1(void); +t_flag_value SpiReadFlagTxSigMASTER_M0_RST_DIE2(void); +t_flag_value SpiReadFlagTxSigMASTER_M0_TIMEOUT_VALUE_DIE2(void); +t_flag_value SpiReadFlagTxSigMASTER_M3_ADD0_DIE2(void); +t_flag_value SpiReadFlagTxSigMASTER_M3_ADD1_DIE2(void); +t_flag_value SpiReadFlagTxSigMASTER_M7_KEY_DIE2(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Reset service for the notify Rx Rx_Error Tx Tx_Error +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal flag. +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void SpiResetFlagRxSig(t_symbolic_name message); +void SpiResetFlagRxSigDIE1_M0_ALPHA(void); +void SpiResetFlagRxSigDIE1_M0_VG(void); +void SpiResetFlagRxSigDIE1_M0_DIAG(void); +void SpiResetFlagRxSigDIE1_M1_ALPHA(void); +void SpiResetFlagRxSigDIE1_M1_BETA(void); +void SpiResetFlagRxSigDIE1_M1_DIAG(void); +void SpiResetFlagRxSigDIE1_M1_VG(void); +void SpiResetFlagRxSigDIE1_M4_DATA_AT_ADD0(void); +void SpiResetFlagRxSigDIE1_M4_DATA_AT_ADD1(void); +void SpiResetFlagRxSigDIE1_M8_KEY_ECHO(void); +void SpiResetFlagRxSigDIE1_M8_INVERTED_KEY_ECHO(void); +void SpiResetFlagRxSigDIE2_M0_ALPHA(void); +void SpiResetFlagRxSigDIE2_M0_DIAG(void); +void SpiResetFlagRxSigDIE2_M0_VG(void); +void SpiResetFlagRxSigDIE2_M1_ALPHA(void); +void SpiResetFlagRxSigDIE2_M1_BETA(void); +void SpiResetFlagRxSigDIE2_M1_DIAG(void); +void SpiResetFlagRxSigDIE2_M1_VG(void); +void SpiResetFlagRxSigDIE2_M4_DATA_AT_ADD0(void); +void SpiResetFlagRxSigDIE2_M4_DATA_AT_ADD1(void); +void SpiResetFlagRxSigDIE2_M8_KEY_ECHO(void); +void SpiResetFlagRxSigDIE2_M8_INVERTED_KEY_ECHO(void); +void SpiResetFlagRxErrorSig(t_symbolic_name message); +void SpiResetFlagRxErrorSigDIE1_M0_ALPHA(void); +void SpiResetFlagRxErrorSigDIE1_M4_DATA_AT_ADD0(void); +void SpiResetFlagRxErrorSigDIE2_M0_ALPHA(void); +void SpiResetFlagTxSig(t_symbolic_name message); +void SpiResetFlagTxSigMASTER_M0_RST_DIE1(void); +void SpiResetFlagTxSigMASTER_M0_TIMEOUT_VALUE_DIE1(void); +void SpiResetFlagTxSigMASTER_M7_KEY_DIE1(void); +void SpiResetFlagTxSigMASTER_M3_ADD0_DIE1(void); +void SpiResetFlagTxSigMASTER_M3_ADD1_DIE1(void); +void SpiResetFlagTxSigMASTER_M0_RST_DIE2(void); +void SpiResetFlagTxSigMASTER_M0_TIMEOUT_VALUE_DIE2(void); +void SpiResetFlagTxSigMASTER_M3_ADD0_DIE2(void); +void SpiResetFlagTxSigMASTER_M3_ADD1_DIE2(void); +void SpiResetFlagTxSigMASTER_M7_KEY_DIE2(void); + +/***************************************************************************** +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine specification: +| * Main task of OSEK/COM that must be called periodically in +| the main loop of the program. +|--------------------------------------------------------------------------- +| Parameters description: +|--------------------------------------------------------------------------- +| CPU requirements data: +| Tmax: ?? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +void SpiOsekComTask(void); + +#endif + diff --git a/firmware/src/DiagnosticR/FicOsek/FicOsekOS.h b/firmware/src/DiagnosticR/FicOsek/FicOsekOS.h new file mode 100644 index 0000000..e83d42d --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicOsekOS.h @@ -0,0 +1,15 @@ +#ifndef _FICOSEKOS_H +#define _FICOSEKOS_H + +/*----------------------------- includes ---------------------------------*/ +#include "Global.h" + +/*-------------------------- tipus de dades ------------------------------*/ + +/*----------------------------- defines ----------------------------------*/ +#define ResumeAllInterrupts ENABLE_INTERRUPT +#define SuspendAllInterrupts DISABLE_INTERRUPT +#define InitFicOsekInterrupts() + +/*---------------------- variables externes -----------------------------*/ +#endif diff --git a/firmware/src/DiagnosticR/FicOsek/FicoComCrc.h b/firmware/src/DiagnosticR/FicOsek/FicoComCrc.h new file mode 100644 index 0000000..e541432 --- /dev/null +++ b/firmware/src/DiagnosticR/FicOsek/FicoComCrc.h @@ -0,0 +1,55 @@ +/************** FICOSA COMMAND AND CONTROL SYSTEMS DIVISION **************** +| File: | Crc.h +| Init Date: | +| Rev. Date.: | +|-----------------|------------------------------------------------------------ +| Language: | MISRA C +| Spec. Document: | +|-----------------|------------------------------------------------------------ +| Project: | ARCGEN BSW +| Reference: | +| Version: | - +|------------------------------------------------------------------------------ +| Date - Cod. - Description +| +| 17/07/14 ATo Document Creation +|------------------------------------------------------------------------------ +| DESCRIPTION: +| CRC Service following Autosar 3.2 defined in: +| http://www.autosar.org/fileadmin/files/releases/3-2/software-architecture/system-services/standard/AUTOSAR_SWS_CRC_Routines.pdf +************************** FI DE LA CAPCALERA *****************************/ +#ifndef _FICOCOMCRC_H +#define _FICOCOMCRC_H + +/* -------------------------------- Includes -------------------------------- */ +#include "Std_Types.h" +#include "Global.h" + +/* -------------------------------- Defines --------------------------------- */ + +/* ------------------------------- Data Types ------------------------------- */ + +/* ---------------------------- Global Variables ---------------------------- */ + +/* ------------------------------- Prototypes ------------------------------ */ +/***************************************************************************** +| Portability: Generic +|---------------------------------------------------------------------------- +| Operations: This service makes a CRC for Melexis SPI. +|--------------------------------------------------------------------------- +| Arguments: +| Message: Pointer to start address of data block to be calculated. + +|--------------------------------------------------------------------------- +| Return: 32 bit result of CRC calculation. +|--------------------------------------------------------------------------- +| Timing: +| Tmax: ? cpu cycles | O(n): CTE +/---------------------------------------------------------------------------*/ +UI_8 cba_256_calc_crc(UI_8 *message); + +/*** Routines for SSU ***/ +UI_16 CalcByteCrc(UI_16 crc, UI_8 new_byte); +UI_16 CalcCompleteCrc(UI_8 * buffer, UI_16 len); + +#endif /* _FICOCOMCRC_H */ diff --git a/firmware/src/DiagnosticR/ProjectCfg.h b/firmware/src/DiagnosticR/ProjectCfg.h new file mode 100644 index 0000000..04799ec --- /dev/null +++ b/firmware/src/DiagnosticR/ProjectCfg.h @@ -0,0 +1,136 @@ + +#ifndef PROJECT_CFG_H +#define PROJECT_CFG_H + +/* -------------------------------- Includes -------------------------------- */ + +/* -------------------------------- Defines --------------------------------- */ +#define MAX_SECURITY_ATTEMPTS 3 +//#define SW_VERSION ((UI_16)0x0101) +///*#define HW_VERSION ((UI_8)0x01)*/ + +/* Return the absolut value of the given parameter */ +#define ABS(x) (((x)>=0)?(x):(-(x))) + +/* Return the minimum parameter from the two parameters given */ +#define MIN(x,y) (((x)>=(y))?(y):(x)) + +/* Return the maximum parameter from the two parameters given */ +#define MAX(x,y) (((x)>=(y))?(x):(y)) + +/******* PWM *******/ +//#define UC_PWM PwmConf_PwmChannel_PwmChannel1//PwmConf_PwmChannel_UC_PWM + +//#define PWM_DUTY_0 ((UI_16)0x0000) +//#define PWM_DUTY_25 ((UI_16)0x2000) +//#define PWM_DUTY_50 ((UI_16)0x4000) +//#define PWM_DUTY_75 ((UI_16)0x6000) +//#define PWM_DUTY_100 ((UI_16)0x8000) +//#define PERCENT_0 ((UI_8)0) +//#define PERCENT_100 ((UI_8)1000) +//#define PWM_DUTY_X(X) ((UI_16)(((UI_32)(X*PWM_DUTY_100))/PERCENT_100)) +//#define PWM_X_DUTY(X) ((UI_8)((UI_32)((X*PERCENT_100))/PWM_DUTY_100)) + +/******* DIO *******/ +/* Defined at Dio_Cfg.h, DIO Channel Configuration Handles */ + +/******* ADC *******/ +/* Defined at Adc_Cfg.h, ADC Group Handles */ + +/******* ATX GA *******/ + +/* GAC ECU Identifier */ +#define GAC_ECU_SW_VERSION_NUMBER {'0','B','0','0','0','9'} +#define GAC_ECU_APP_VERSION_NUMBER {'1','2','8'} +#define GAC_ECU_CALIBRATION_VERSION {'3','0','2','0','0','1','3','A','M','V','0','3','C','.','0','0','0'} +#define GAC_ECU_REPAIR_SHOP_CODE {0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x30,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f} + + +#define GAC_ECUINSTALL_DATE_DEFAULT_VAL {0,0,0,0} +#define GAC_APP_SW_FINGER_INFO {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} +#define GAC_DCID_VALUE {0x0D,0x00,0x00} +#define GAC_DIAG_PARAM_TABLE {0x0,0x0,0x0,0x0} +#define GAC_VIN_DEFAULT_VALUE {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x30,0x30,0x30,0x30,0x30,0x30,0x30} +#define GAC_CLIBRATION_DATE_DEFAULT_VALUE {0x05,0x31,0x20,0x21} +#define GAC_APP_DATAID_DEFAULT_VALUE {0x00,0x00,0x00} +#define GAC_MANUF_ECUHWNUM_DEFAULT_VALUE {'A','K','C','G','-','0','0','3','-','A','A'} +#define GAC_ECU_SN_DEFAULT_VALUE {0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20} +#define GAC_APP_SW_LOGICAL_ID {} +#define GAC_BOOT_ID_DEFAULT_VALUE {'4','5','0'} +#define GAC_ECUSW_VERSION_DEFAULT_VALUE {'S','W','0','3','0','2',' ',' ',' ',0x20,0x20,0x20,0x20,0x20,0x20,0x20} +#define GAC_APP_SUPPLIER_ID {0x46,0x49,0x43,0x4F,0x53,0x41,0x20,0x49,0x4E,0x54,0x45,0x52,0x4e}; + + +/* ------------------------------- Data Types ------------------------------- */ +//typedef signed char int8_t; +//typedef unsigned char uint8_t; +typedef volatile signed char vint8_t; +typedef volatile unsigned char vuint8_t; + +//typedef signed short int16_t; +//typedef unsigned short uint16_t; +typedef volatile signed short vint16_t; +typedef volatile unsigned short vuint16_t; + +//typedef signed int int32_t; +//typedef unsigned int uint32_t; +typedef volatile signed int vint32_t; +typedef volatile unsigned int vuint32_t; + +typedef enum { + SYS_STARTUP = 0, + SYS_FAILSAFE = 1, + SYS_RUN = 2, + SYS_SHUTDOWN = 3, + SYS_SLEEP = 4, + SYS_MCAL = 5, +}e_Sys_Status; + + +#define ISO15765_2_REPROGONCAN_HANDLER ((UI_8)0) + +#define DEBUG_ENABLE + +/* ---------------------------- Global Variables ---------------------------- */ +//extern Mcu_ResetType last_reset_cause; +//extern t_error cycle_violation; +/* --------------------------- Routine prototypes --------------------------- */ + +/* -------------------------------- Routines -------------------------------- */ +//void OS_getFreezeRecordReset(UI_8 *pFreezeRecord); +//void OS_getFreezeRecordScheduler(UI_8 *pFreezeRecord); +/* IDs for Safety events. Must be consecutive numbers from 0 to NUM_SAFETY_EVENTS-1 */ +#define SAFETY_EVENT_CAN_SPEED_LOST ((uint16)0) +#define SAFETY_EVENT_CAN_BRAKE_LOST ((uint16)1) +#define SAFETY_EVENT_ACT_SENSOR_1_NOK ((uint16)2) +#define SAFETY_EVENT_ACT_SENSOR_2_NOK ((uint16)3) +#define SAFETY_EVENT_ACT_SENSOR_ALL_NOK ((uint16)4) +#define SAFETY_EVENT_ACT_CAL_NVM_KO ((uint16)5) +#define SAFETY_EVENT_ACT_SENSOR_1_NO_PLAUSIBLE ((uint16)6) +#define SAFETY_EVENT_ACT_SENSOR_2_NO_PLAUSIBLE ((uint16)7) +#define SAFETY_EVENT_ACT_POSITION_COMB_NO_PLAUSIBLE ((uint16)8) +#define SAFETY_EVENT_ACT_POSITION_INVALID ((uint16)9) +#define SAFETY_EVENT_ROT_SENSOR_1_NOK ((uint16)10) +#define SAFETY_EVENT_ROT_SENSOR_2_NOK ((uint16)11) +#define SAFETY_EVENT_ROT_SENSOR_ALL_NOK ((uint16)12) +#define SAFETY_EVENT_ROT_CAL_NVM_KO ((uint16)13) +#define SAFETY_EVENT_ROT_SENSOR_1_NO_PLAUSIBLE ((uint16)14) +#define SAFETY_EVENT_ROT_SENSOR_2_NO_PLAUSIBLE ((uint16)15) +#define SAFETY_EVENT_ROT_POSITION_COMB_NO_PLAUSIBLE ((uint16)16) +#define SAFETY_EVENT_PBUTTON_1_NOK ((uint16)17) +#define SAFETY_EVENT_PBUTTON_2_NOK ((uint16)18) +#define SAFETY_EVENT_PBUTTON_ALL_NOK ((uint16)19) +#define SAFETY_EVENT_SSU_SFTY_WARNING ((uint16)20) +#define SAFETY_EVENT_SSU_NOK ((uint16)21) +#define SAFETY_EVENT_INT_RAM_NOK ((uint16)22) +#define SAFETY_EVENT_INT_ROM_NOK ((uint16)23) +#define SAFETY_EVENT_INT_ADC_NOK ((uint16)24) +#define SAFETY_EVENT_INT_STACK_NOK ((uint16)25) +#define SAFETY_EVENT_INT_2E2_NOK ((uint16)26) +#define SAFETY_EVENT_INT_CPU_NOK ((uint16)27) +#define SAFETY_EVENT_CAN_SPEED_INVALID ((uint16)28) +#define SAFETY_EVENT_CAN_BRAKE_INVALID ((uint16)29) +#define SAFETY_EVENT_EPB_STS_LOST ((uint16)30) +#define SAFETY_EVENT_EPB_STS_INVALID ((uint16)31) + +#endif /* PROJECT_CFG_H */ diff --git a/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c b/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c new file mode 100644 index 0000000..e5eb406 --- /dev/null +++ b/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.c @@ -0,0 +1,165 @@ +#include "SysDiagDetect.h" +#include "FunctionState.h" +#include "OsekCom/OsekCom.h" +#include "RTE.h" +#include "forcedetect.h" +#include "forceSnsr.h" + +static uint8 Bat_Rng = 0; +static void Battery_Volt_Diag_Task(void) +{ + if (Fuction_State != Function_State_A) + { + Bat_Rng = Bat_Out_Range; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS, &Bat_Rng); + } + else + { + Bat_Rng = Bat_In_Range; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS, &Bat_Rng); + } +} + +uint8 Force_Sens_Err = 0; +static void Force_Sensor_Diag_Task(void) +{ + uint16 Diag_Press_baseline; + sint16 Diag_Convert_baseline; + uint16 CurrentDiag_Press_signal; + static uint16 LastDiag_Press_signal = 0; + static uint16 Press_NoChange_Count = 0; + + // basline + - convert + Diag_Press_baseline = Get_forcedetect_basline_value(); + if ((Diag_Press_baseline >> 11) == 1) + { + Diag_Convert_baseline = Diag_Press_baseline - 4096; + } + else + { + Diag_Convert_baseline = Diag_Press_baseline; + } + + CurrentDiag_Press_signal = Get_forcedetect_force_value(); + + // Force sensor Diag start + if (forcesnsr_i2c_process_state_u8 == 1) + { + Force_Sens_Err = 1; + } + else + { + Force_Sens_Err = 0; + if (CurrentDiag_Press_signal == LastDiag_Press_signal) + { + Press_NoChange_Count++; + if (Press_NoChange_Count >= 800) // 4 seconds + { + Force_Sens_Err = 1; + Press_NoChange_Count = 800; + } + } + else + { + Press_NoChange_Count = 0; + } + + if (Diag_Convert_baseline < -2040 || Diag_Convert_baseline > 1000) + { + Force_Sens_Err = 1; + } + } + + // Force_Sens_Err = 1; //just for test,to set sensor error + LastDiag_Press_signal = CurrentDiag_Press_signal; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS, &Force_Sens_Err); +} + +// Touch_Sensor_Sts00; +static uint8 Touch_Sensor_Fault = 0; +static void Touch_Sensor_Diag_Task(void) +{ + static uint16_t fault_count = 0, fault_count2 = 0; + uint16 CurrentDiag_Press_signal; + if (Touch_Sensor_Sts00 < 80 && Touch_Sensor_Sts01 < 80 && Touch_Sensor_Sts02 < 80 && Touch_Sensor_Sts03 < 80 && Touch_Sensor_Sts04 < 80 && + Touch_Sensor_Sts05 < 80 && Touch_Sensor_Sts06 < 80 && Touch_Sensor_Sts07 < 80 && Touch_Sensor_Sts08 < 80 && Touch_Sensor_Sts09 < 80 && + Touch_Sensor_Sts10 < 80 && Touch_Sensor_Sts11 < 80 && Touch_Sensor_Sts12 < 80 && Touch_Sensor_Sts13 < 80 && Touch_Sensor_Sts14 < 80) + { + Touch_Sensor_Fault = Touch_NoFault; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS, &Touch_Sensor_Fault); + fault_count = 0; + } + else + { + Touch_Sensor_Fault = Touch_Out_Range; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS, &Touch_Sensor_Fault); + fault_count++; + if (fault_count > 200) + { + fault_count = 0; + //touch_init(); + } + } + + CurrentDiag_Press_signal = Get_forcedetect_force_value(); + if (CurrentDiag_Press_signal < 50) + { + if (Touch_Sensor_Sts00 > 10 || Touch_Sensor_Sts01 > 10 || Touch_Sensor_Sts02 > 10 || Touch_Sensor_Sts03 > 10 || Touch_Sensor_Sts04 > 10 + || Touch_Sensor_Sts05 > 20 || Touch_Sensor_Sts06 > 20 || Touch_Sensor_Sts07 > 20 || Touch_Sensor_Sts08 > 20 || Touch_Sensor_Sts09 > 20 + || Touch_Sensor_Sts10 > 20 || Touch_Sensor_Sts11 > 20 || Touch_Sensor_Sts12 > 20|| Touch_Sensor_Sts13 > 20 || Touch_Sensor_Sts14 > 20) + { + fault_count2++; + if (fault_count2 > 200) + { + fault_count2 = 0; + //touch_init(); + } + } + else + { + fault_count2 = 0; + } + } + else + { + fault_count2 = 0; + } +} + +static uint8 Vibra_Fault = 0; +static void Vibration_Diag_Task(void) +{ + // AD_data=voltage * 4096/3.3V normal:0-0.01(15) short: 0.15(185)-0.36(448) 0.6(742)-0.7(870) 0.95(1177)-1.05(1305) 1.27(1575)-1.39(1727) open:1.55(1921) - 1.72(2136) + + Vibra_Fault = Vibration_Normal; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS, &Vibra_Fault); + + /* + if(LD_AD_Val>=0 && LD_AD_Val<=15) //normal + { + Vibra_Fault = Vibration_Normal; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS, &Vibra_Fault); + } + else if((LD_AD_Val>=185 && LD_AD_Val<=448)||(LD_AD_Val>=742 && LD_AD_Val<=870)||(LD_AD_Val>=1177 && LD_AD_Val<=1305)||(LD_AD_Val>=1575 && LD_AD_Val<=1727)) + { + Vibra_Fault = Vibration_Short; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS, &Vibra_Fault); + } + else if(LD_AD_Val>=1921 && LD_AD_Val<=2136) + { + Vibra_Fault = Vibration_open; + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS, &Vibra_Fault); + } + */ +} + +void Sys_Diag_Detcet_Task(void) +{ + Battery_Volt_Diag_Task(); + if (Bat_Rng == Bat_In_Range) + { + Force_Sensor_Diag_Task(); + Touch_Sensor_Diag_Task(); + Vibration_Diag_Task(); + } +} diff --git a/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.h b/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.h new file mode 100644 index 0000000..3a6bbde --- /dev/null +++ b/firmware/src/DiagnosticR/Sys_Diag_Detect/SysDiagDetect.h @@ -0,0 +1,26 @@ +#ifndef __SysDiagDetect_H__ +#define __SysDiagDetect_H__ + +#include "Std_Types.h" + +#define Bat_In_Range 0 +#define Bat_Out_Range 1 + +#define Touch_NoFault 0 +#define Touch_Out_Range 1 + +#define Vibration_Normal 0 +#define Vibration_Short 1 +#define Vibration_open 2 + +extern uint8 Force_Sens_Err; +//extern uint8 Fuction_State ; +//extern uint8 Control_SDZ ; + + +extern void Sys_Diag_Detcet_Task(void); + + + + +#endif \ No newline at end of file diff --git a/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c b/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c new file mode 100644 index 0000000..cec7114 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.c @@ -0,0 +1,138 @@ +/************ Copyright 2004-2009 FICOSA CORPORATIVE ELECTRONICS ************ +| Language: | MISRA C +| Controller: | dsPIC33 +| Requirements: +|-------------|------------------------------------------------------------ +| Project: | 082_TCU01_F1_TCU_EMU_RSA +|------------------------------------------------------------------------------ +| HISTORY OF MODIFICATIONS +| Date - Coder - Description +| 07/02/10 AC Creation of the file. +|------------------------------------------------------------------------------ +| FILE DESCRIPTION: +| Configuration source file of the transport protocol (ISO15765_2) layer. +| This source file must contain the transport protocol callback routine +| TPDynamicParametersInitCallback to initialize the dynamic configuration +| parameters for each TP instance defined in TP_CFG.h. +******************************************************************************/ + +/* -------------------------------- Includes -------------------------------- */ +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +#include "DiagnosticR/ProjectCfg.h" +#include "TP_CFG.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" +#include "DiagnosticR/UDS\Iso15765_layer3/Iso15765_3_CFG.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" + +/* -------------------------------- Defines --------------------------------- */ + +/* Size of the buffer that must store the largest frame for the */ +/* MPDT TX and RX instances */ +/* The size of the buffer must be declared using the macro */ +/* SIZE_ALLOC_BUFFER to assure that no overflows will happen during */ +/* transmission or reception of frames larger than single frames */ +#define TP_MPDT_TX_LEN (SIZE_ALLOC_BUFFER(30)) +#define TP_MPDT_RX_LEN (SIZE_ALLOC_BUFFER(30)) + +/* For diagnostics TP instance I have the length of the buffers already */ +/* defined in the Iso15765_3 layer */ + +/* ------------------------------- Data Types ------------------------------- */ + +/* ---------------------------- Global Variables ---------------------------- */ + +/* Definition of the buffer to allocate functional frames. As functional */ +/* frames are not needed in any of my TP instances I declare it as a dummy */ +/* buffer. The size of the functional buffer must be always of 7 bytes */ +/* because this is the maximum length that could be send in a SF */ +//static UI_8 diag_rx_fun_dummy_buf[7] = { 0,0,0,0,0,0,0 }; + +/* Definition of the transmission and reception TP buffers for MPDT */ +//static UI_8 tp_mpdt_tx_buf[TP_MPDT_TX_LEN]; +//static UI_8 tp_mpdt_rx_buf[TP_MPDT_RX_LEN]; + +/* For diagnostics TP instance I have the buffers already defined in the */ +/* Iso15765_3 layer */ + +/* --------------------------- Routine prototypes --------------------------- */ + +/* -------------------------------- Routines -------------------------------- */ + +/***************************************************************************** +| Portability: General +|---------------------------------------------------------------------------- +| Routine description: +| * It is responsability of the user to declare this routine. +| * This routine is a callback routine that will be called each time that the +| InicialitzaTPTask is executed. This InicialitzaTPTask must be called at +| the initializations in main and must be called once for each instance +| defined in the TP_CFG.h. +| * Routine to initializate dynamically the parameters of each defined +| transport protocol instance. The way to configure each transport protocol +| instance is using the structure t_tp_init which must be given as a pointer +| to TPInitData routine. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void TPDynamicParametersInitCallback(UI_8 tp_hdl) +{ + /* Declare the initialization ISO15765_2 structure as a local variable */ + /* in order to not use space in the stack */ + t_tp_init tp_init = {0}; /* MISRA wants all variables to be initialized. */ + + /* Switch for each instance of ISO15765_2 declared (TP_NUM_INSTANCES) */ + switch(tp_hdl) { + /* Initialize the user configuration parameters of the transport protocol instance used for diagnostics */ + case ISO15765_2_REPROGONCAN_HANDLER: + /* Maximum size allowed for the diagnostics RX buffer. */ + /* The buffer must be reserved having into account the MACRO "SIZE_ALLOC_BUFFER" to avoid overflows */ + tp_init.max_frm_size = (UI_16)(MAX(TP_DIAG_RX_LEN,TP_DIAG_TX_LEN)); + /* Flag to configure fixed or variable length in the CAN frames TX */ + /* Diagnostics frm_size_fixed = TRUE: Defined in the renault document 36-02-031--A_Gb.pdf, page 9, chapter 6 */ + tp_init.frm_size_fixed = TRUE; + /* Flag to configure if TP RX frames are sensitive to have a fixed length. TRUE indicates that we will ignore TP RX frames */ + /* that have less than 8 bytes */ + tp_init.rx_padding_sensitive = TRUE; + /* Special value 0x50 is requiered in the padding value for diagnostics TX (only cares if frame size is configured as fixed) */ + /* Defined in the renault document CRS_TCU_NT65612_2009_80_v1.1DRAFT.pdf page 6 */ + tp_init.tx_padding_value = 0xAA; + /* Maximum timeout in ms between Consecutive frames before aborting the reception due to time out */ + /* Diagnostics CR timer: Defined in the renault document 36-02-031--A_Gb.pdf, pages 7 and 17 */ + tp_init.cr_timer = (UI_16)150; + /* Time in ms between the first frame and the firs flow control or between the last consecutive frame of a block */ + /* and the flow control before aborting the transmission due to timeout */ + /* Diagnostics BS timer: Defined in the renault document 36-02-031--A_Gb.pdf, pages 7 and 17 */ + tp_init.bs_timer = (UI_16)150; + /* Time in ms between consecutive frames of the transmitter to allow ourself to process the received frames */ + /* without losing anyone. If the block size if different from 1, this time must be minimum the cycle frequency, */ + /* otherwise if this is 1 the stmin could be 0 */ + /* For diagnostics this requirement is defined in the renault document 36-02-031--A_Gb.pdf, page 7 as 0 */ + tp_init.stmin_timer = (UI_16)20; + /* Number of consecutive frames that the diagnostics TP will send without waiting for a flow control before continuing. */ + /* If the block size is set to 0 means that only one flow control is needed after receiving the first */ + tp_init.block_size = (UI_8)0; + /* Number of FC w can handle before rising directly an error during the transmission when a FC wait is received */ + tp_init.max_fc_wait = (UI_8) 0; + /* Initialize the buffer pointer where the diagnostics TX positive response physical information is set */ + tp_init.tx_phy_buffer = diag_tx_buf; + /* Initialize the buffer pointer where the diagnostics RX physical request information is set */ + tp_init.rx_phy_buffer = diag_phy_rx_buf; + /* Initialize the buffer pointer where the diagnostics RX functional request information is set */ + tp_init.rx_fun_buffer = diag_fun_rx_buf; + /* Set the OSEKCOM diagnostics signal to get the RX physical frame */ + tp_init.sig_np_rx_phy = SIG_DIAGNOSTICREQSWTR; //SIG_DIAGNOSTICREQPRNDL + /* Set the OSEKCOM signal to request the transmission of the diagnostics TX physical frame */ + tp_init.sig_np_tx_phy = SIG_DIAGNOSTICRESPSWTR; //SIG_DIAGNOSTICRESPSWTR + /* Initialize the diagnostics RX functional notification routine to NULL because we must not receive functional frames */ + //tp_init.np_get_rx_fun_notif = NULL; + /* Initialize the signal of the diagnostics RX functional frame to DUMMY signal becuase we must not receive functional frames */ + tp_init.sig_np_rx_fun = SIG_DIAGNOSTICFUNCADDRREQ; + /* Call the ISO15765_2 configuration routine to initialize the diagnostics instance with the configured parameters */ + TPInitData(tp_hdl, &tp_init); + break; + + default: + break; + } +} diff --git a/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h b/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h new file mode 100644 index 0000000..6e132ad --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/Iso15765_layer2/TP_CFG.h @@ -0,0 +1,74 @@ +/*************** COPYRIGHT (c) 2012 IDNEO INTERNATIONAL ****************** +| Language: | MISRA C +| Controller: | dsPIC33 +| Requirements: | +|-----------------|----------------------------------------------------------- +| Project: | 082_TCU01_F1_TCU_EMU_RSA +|------------------------------------------------------------------------------ +| Date - Cod. - Rev. - App. - Description +| 07/02/10 AC Creation of the file. +|------------------------------------------------------------------------------ +| FILE DESCRIPTION: Configuration header file of the transport protocol +| (ISO15765_2) layer. This header must define if the transport +| protocol used is FULL or LITE which implies if frames till +| 4096 bytes can be send or only single frames till 7 bytes can +| be send. This header must configure the number of transport +| protocol instances that the application need.This header must +| also contain the declaration of the callback routine to +| initialize the transport protocol dynamic configuration +| parameters which must be called TPDynamicParametersInitCallback +******************************************************************************/ +#ifndef __TP_CFG_H +#define __TP_CFG_H + +/*---------------------------- includes ----------------------------------*/ +//#include "FicosarCfg.h" + +/*----------------------------- defines ----------------------------------*/ + +/* Select the mode of ISO15765_2 used. This will apply for all the */ +/* transport protocol instances defined */ +/* TP_MODE_LITE -> Only single frames can be sent and received */ +/* TP_MODE_FULL -> Frames till 4096 bytes can be sent and received */ +#define TP_MODE_FULL + +/* Number of Transport Protocol instances that will be defined. One */ +/* instance must be defined for example for each of the following upper */ +/* layters: */ +/* - Diagnostics client */ +/* - Diagnostics server */ +/* - MPDT */ +#define TP_NUM_INSTANCES ((UI_8)1) + +/*************************** ISO15765_2 HANDLERS USAGE BEGIN****************************/ +#define ISO15765_2_REPROGONCAN_HANDLER ((UI_8)0) +/*************************** ISO15765_2 HANDLERS USAGE END ****************************/ +/* Ticks between task periodic calls */ +#define TP_TASK_TICKS ((t_timer_time)2) + +/* Minimum length of a flow control frame to be accepted */ +#define CAN_FRM_FC_SIZE ((UI_8)8) + +/*------------------------- prototips de funcions ------------------------*/ + +/***************************************************************************** +| Portability: General +|---------------------------------------------------------------------------- +| Routine description: +| * It is responsability of the user to declare this routine. +| * This routine is a callback routine that will be called each time that the +| InicialitzaTPTask is executed. This InicialitzaTPTask must be called at +| the initializations in main and must be called once for each instance +| defined in the TP_CFG.h. +| * Routine to initializate dynamically the parameters of each defined +| transport protocol instance. The way to configure each transport protocol +| instance is using the structure t_tp_init which must be given as a pointer +| to TPInitData routine. +|--------------------------------------------------------------------------- +| Parameters description: +| UI_8 tp_hdl : ... +| result none : ... +/---------------------------------------------------------------------------*/ +void TPDynamicParametersInitCallback(UI_8 tp_hdl); + +#endif diff --git a/firmware/src/DiagnosticR/UDS/Iso15765_layer3/ISO15765_3_CFG.h b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/ISO15765_3_CFG.h new file mode 100644 index 0000000..84ed315 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/ISO15765_3_CFG.h @@ -0,0 +1,503 @@ +#ifndef _ISO15765_3_CFG_H_ +#define _ISO15765_3_CFG_H_ + +// TODO XXX FIXME: this should probably go to ISO15765_3.H +//#include "Timer.h" +//#include "ProjectCfg.h" +#include "DiagnosticR/UDS/UDS_CoreServices_CB.h" +/* ISO15765_3 VARIANTS */ +/* Pure UDS Standard */ +#define ISO15765_3_UDS (0x00) +/* RSA Variant*/ +#define ISO15765_3_RSA (0x01) +/* Fiat customizations */ +#define ISO15765_3_FIAT (0x02) +#define ISO15765_3_GAC (0x03) +#define ISO15765_3_VARIANT (ISO15765_3_UDS) + +/* ISO15765_3 MODE */ +#define ISO15765_3_APP (0x00) +#define ISO15765_3_BL (0x01) +#define ISO_3_MODE (ISO15765_3_APP) + + + +/* FICOSA_SYSTEM_SUPPLIER_SESSION */ +/* 0x60 - 0x7E systemSupplierSpecific: this range of values is reserved for system-supplier-specific use.*/ +/* ISO 14229-1:2006(E) pag 39 */ +#define UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID ((UI_8)0x60) + +/* Size of the buffer that must store the largest frame for the */ +/* diagnostic server instance (ISO15765_3) */ +/* The size of the buffer must be declared using the macro */ +/* SIZE_ALLOC_BUFFER to assure that no overflows will happen during */ +/* transmission or reception of frames larger than single frames */ +/* Defined Candela A68_GSM_Ficosa.75.cdd -> ECU Information -> Supported Interfaces -> Diagnose CAN */ +#define TP_DIAG_FUN_RX_BUFFER ((UI_16)(8)) +#define TP_DIAG_RX_BUFFER ((UI_16)(4096)) +#define TP_DIAG_TX_BUFFER ((UI_16)(4096)) +#define TP_DIAG_FUN_RX_LEN (SIZE_ALLOC_BUFFER(TP_DIAG_FUN_RX_BUFFER)) +#define TP_DIAG_RX_LEN (SIZE_ALLOC_BUFFER(TP_DIAG_RX_BUFFER)) +#define TP_DIAG_TX_LEN (SIZE_ALLOC_BUFFER(TP_DIAG_TX_BUFFER)) + +/* + * ISO15765_3_MIN_ADDRESS_LENGTH_MULTIDEVICE: + * Addresses with less bytes will be considered directed to DEVICE_0. + */ +#define ISO15765_3_MIN_ADDRESS_LENGTH_MULTIDEVICE ((UI_8)4) + +/* Used ISO15765_2 stack in order to send and receive */ +/* the diagnostics */ +#define DIAG_ISO15765_2_HDL (ISO15765_2_REPROGONCAN_HANDLER) + +/*****************************************************************************/ +/* TIMING */ +/*****************************************************************************/ +/* Max time allowed to answer a request. In milliseconds */ +#define P2_MAX ((UI_16)50) +/* Max time between a UDS_ERR_RESPONSE_PENDING and the next answer. In ms */ +#define P2_EXT_MAX ((UI_16)200) +/* Max counter between a UDS_ERR_RESPONSE_PENDING and the next answer. */ +#define P2_EXT_MAX_COUNTER ((UI_16)150) +/* Session Expiration Timeout. In ms */ +#define S3_MAX ((UI_16)5000) + +/*****************************************************************************/ +/* DATA TYPES */ +/*****************************************************************************/ +/* Specify the Download Addresses size: */ +/* Possible values: ISO3_16BIT_ADDRESS, ISO3_32BIT_ADDRESS */ +#define DOWNLOAD_ADDRESS_SIZE (ISO3_32BIT_ADDRESS) + +/*****************************************************************************/ +/* UDS SERVICES */ +/*****************************************************************************/ +/* SECURITY ACCESS ENABLED/DISABLED */ +#define SERVICE_DISABLED (0x00) +#define SERVICE_ENABLED (0x01) + +#define LIN_ASSIGN_FRAME_IDENTIFIER_STATUS (SERVICE_DISABLED) +#define LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ +#define LIN_READ_BY_IDENTIFIER_STATUS (SERVICE_DISABLED) +#define LIN_ASSIGN_NAD_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ +#define LIN_CONDITIONAL_CHANGE_NAD_STATUS (SERVICE_DISABLED) /*NOT IMPLEMENTED YET */ + +#define UDS_SERVICE_SESSION_CONTROL_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_ECU_RESET_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_SECURITY_ACCESS_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_TESTER_PRESENT_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_CONTROL_DTC_SETTING_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS_STATUS (SERVICE_DISABLED)//NOT IMPLEMENTED YET +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_STATUS (SERVICE_DISABLED)//NOT IMPLEMENTED YET +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_READ_DTC_INFORMATION_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_IO_CTRL_BY_ID_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_ROUTINE_CONTROL_STATUS (SERVICE_ENABLED) +#define UDS_SERVICE_REQUEST_DOWNLOAD_STATUS (SERVICE_DISABLED) +#define UDS_SERVICE_TRANSFER_DATA_STATUS (SERVICE_DISABLED) +#define UDS_SERVICE_REQUEST_TRANSFER_EXIT_STATUS (SERVICE_DISABLED) +#define UDS_SERVICE_COMMUNICATION_CONTROL_STATUS (SERVICE_ENABLED) + +#if (LIN_ASSIGN_FRAME_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * ASSIGN FRAME IDENTIFIER (0xB7) + ***************************************************************************** + * This service IS ONLY VALID in LIN version 2.0 + * CALLBACKS: + * LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK(UI_8 supplierID_LSB, UI_8 supplierID_MSB, UI_8 messageID_LSB, UI_8 messageID_MSB, UI_8 new_pid): + * 'supplierID' defines the product vendor identifier. + * 'messageID' defines the message identifier as in section in Lin Description File. + * 'new_pid' defines the new pid to identify the frame with the selected messageID. + * A response shall be sent if the assignation is successful. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_FRAME_IDENTIFIER_CALLBACK (LinAssignFrameId) +#endif + +#if (LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * ASSIGN FRAME IDENTIFIER RANGE (0xB7) + ***************************************************************************** + * This service IS MANDATORY in all three LIN diagnostics classes + * (See 4.2.5.5 on LIN Spec 2.2) + * CALLBACKS: + * LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK(UI_8 index, const UI_8* new_pid_list): + * 'index' defines the protected identifier (pid) start from the pid list available. + * 'new_pid_lis' defines a buffer where are specified the four new pids for change + * counting from index. + * - 0x00: Disable service. + * - 0xFF: Do not change PID. + * - 0xXX: Change pid. + * The system shall only response if NAD matched. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_FRAME_IDENTIFIER_RANGE (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_FRAME_IDENTIFIER_RANGE_CALLBACK (LinAssignFrameIdRange) +#endif + + +#if (LIN_READ_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ BY IDENTIFIER (0xB2) + ***************************************************************************** + * This service IS MANDATORY in all three LIN diagnostics classes for ID = 0x00 + * The rest of identifier are optional. + * (See 4.2.6.1 on LIN Spec 2.2) + * CALLBACKS: + * LIN_READ_BY_IDENTIFIER_CALLBACK(UI_8 id): + * 'id' defines the identifier requested. + * - 0x00: LIN Product identification: SupplierID, FunctionID & Variant. + * - 0x01: Serial Number. + * - 0x32-0x63: User defined. + * - The rest of identifiers are reserved. + * The system shall accordingly to each request. (See 4.2.6.1 on LIN Spec 2.2) + ****************************************************************************/ +#define LIN_SERVICE_READ_BY_IDENTIFIER (UDS_DEFAULT_SESSION_MASK) +#define LIN_READ_BY_IDENTIFIER_CALLBACK (LinReadByID) +#endif + + +#if (LIN_ASSIGN_NAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * LIN ASSIGN NAD (0xB0) + ***************************************************************************** + * This service CAN be enabled/disabled + * (See 4.2.5.1 on LIN Spec 2.2) + * CALLBACKS: + * LIN_ASSIGN_NAD_CALLBACK(UI_16 supplierId, UI_16 functionId, UI_8 new_nad): + * - 'supplierId' and 'functionId' must be the same as defined in the system, + * otherwise the NAD won't be assigned. + * - 'new_nad' is the new NAD to be assigned + * The system shall response with the initial NAD to confirm the change. + ****************************************************************************/ +#define LIN_SERVICE_ASSIGN_NAD (UDS_DEFAULT_SESSION_MASK) +#define LIN_ASSIGN_NAD_CALLBACK (LinAssignNAD) +#endif + + +#if (LIN_CONDITIONAL_CHANGE_NAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * LIN CONDITIONAL CHANGE NAD (0xB3) + ***************************************************************************** + * This service CAN be enabled/disabled + * (See 4.2.5.2 on LIN Spec 2.2) + * CALLBACKS: + * LIN_CONDITIONAL_CHANGE_NAD_CALLBACK(UI_8 id, UI_8 byte, UI_8 mask, UI_8 invert, UI_8 new_nad): + * 1. 'id' Get the identifier specified by the function LinReadByID. + * 2. Extract the data byte selected by Byte (Byte = 1 corresponds to the first byte, D1). + * 3. Do a bitwise XOR with Invert. + * 4. Do a bitwise AND with Mask. + * 5. If the final result is zero then change the NAD to New NAD. + * The system shall response with the new NAD to confirm the change. + ****************************************************************************/ +#define LIN_SERVICE_CONDITIONAL_CHANGE_NAD (UDS_DEFAULT_SESSION_MASK) +#define LIN_CONDITIONAL_CHANGE_NAD_CALLBACK (LinConditionalChangeNAD) +#endif + + +#if (UDS_SERVICE_SESSION_CONTROL_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * DIAGNOSTICS SESSION CONTROL (0x10) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * .- UDS_INI_SESSION_CALLBACK: The user MAY implement this callback. + * Called when layer 3 changes session + * DEFINES: + * .- UDS_USER_DEFINED_SESSION. Valid User Defined Session ID + ****************************************************************************/ +#define UDS_SERVICE_SESSION_CONTROL (UDS_ALL_SESSION_MASK) +//TODO: Check allowed session +//#define UDS_USER_DEFINED_SESSION (UDS_DEFAULT_SESSION) +#define UDS_USER_DEFINED_SESSION (UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID) + +#define UDS_INI_SESSION_CALLBACK (UdsIniSession) + +#endif + +#if (UDS_SERVICE_ECU_RESET_STATUS == SERVICE_ENABLED) +/**************************************************************************** + * ECU RESET (0x11) + **************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * BOOL CHECK_RESET_POSSIBLE(UI_8 reset_type): + * Asks the user if this reset type is allowed at this point in time. + * Return TRUE if yes + * void EXECUTE_RESET(UI_8 reset_type): + * Execute the reset type requested + ****************************************************************************/ +#define UDS_SERVICE_ECU_RESET (UDS_DEFAULT_SESSION_MASK | UDS_EXT_DIAG_SESSION_MASK | UDS_PROGRAMMING_SESSION_MASK | UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define CHECK_RESET_POSSIBLE (UdsCheckResetIsPossible) +#define EXECUTE_RESET (UdsExecuteResetNow) + +#endif + +#if (UDS_SERVICE_SECURITY_ACCESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * SECURITY ACCESS(0x27) + **************************************************************************** + * This service can be enabled/disabled + * CALLBACKS: + * void UDS_SECURITY_REQUEST_SEED_CALLBACK(UI_8* p_local_seed): + * Generate a Random Seed and place it in p_local_seed (4 bytes) + * BOOL UDS_SECURITY_CHECK_KEY_CALLBACK(UI_8* p_local_seed, UI_8* p_tool_key): + * Check the key returned by the tool. Return TRUE is ok + * DEFINES + * UDS_SERVICE_SECURITY_ACCESS: set the session which accepts this service. + * SECURITY_INIT_DELAY: Set to SECURITY_DELAY, to introduce 10 secs + * delay after Reset, before accepting security resets. Set to + * SECURITY_NO_DELAY if no delay is wanted. + * MAX_SECURITY_ATTEMPTS: Number of failed attempts before starting the penalty + * SECURITY_PENALTY_TIME: Time to wait before next attempt. + * SECURITY_SEED_SIZE: Number of bytes of the security seed (max = 4) + * SECURITY_KEY_SIZE: Number of bytes of the security seed (max = 4) + * UDS_SECURITY_COUNTER_NVM_CALLBACK: Callback to store a new value of the counter in NVM. + * - Signature: void UDS_SECURITY_COUNTER_NVM_CALLBACK(UI_8 *value) + * - (legacy) If not defined, then value will not be stored in NVM. + * UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK: Callback to retrieve the value of the counter from NVM, tipically + * at the beginning of the execution. + * - Signature: UI_8 UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK(void) + * - (legacy) If not defined, then value will be loaded as zero (check startup strategy for penalty delay + * using SECURITY_INIT_DELAY). + ****************************************************************************/ +//#define UDS_SERVICE_SECURITY_ACCESS (UDS_EXT_DIAG_SESSION_MASK | UDS_PROGRAMMING_SESSION_MASK | UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +////#define UDS_SECURITY_REQUEST_SEED_CALLBACK (UdsSecurityGetSeed) +//#define UDS_SECURITY_CHECK_KEY_CALLBACK (UdsSecurityCheckKey) +#define SECURITY_INIT_DELAY (SECURITY_DELAY) +//#define MAX_SECURITY_ATTEMPTS ((UI_8) 3) +#define SECURITY_PENALTY_TIME ((UI_16) 20000) +#define SECURITY_SEED_SIZE ((UI_8) 16) +#define SECURITY_KEY_SIZE ((UI_8) 16) +#define UDS_SECURITY_COUNTER_NVM_CALLBACK (UdsSecurityNvmCallback) +#define UDS_SECURITY_COUNTER_NVM_LOAD_CALLBACK (UdsSecurityLoadNvmCallback) + +#endif + +#if (UDS_SERVICE_TESTER_PRESENT_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TESTER PRESENT (0x3E) + ***************************************************************************** + * This service CAN be enabled/disabled + * No User CALLBACK Needed + ****************************************************************************/ +#define UDS_SERVICE_TESTER_PRESENT (UDS_ALL_SESSION_MASK) + +#endif + + +#if (UDS_SERVICE_READ_DATA_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ DATA BY ID(0x22) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK(UI_8 id_high, + * UI_8 id_low): Pass the ID to the user to + * process the request. The user is responsible for checking the security + * status for each parameter, and to send the appropiate response. + *****************************************************************************/ +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_READ_DATA_BY_IDENTIFIER_CALLBACK (UdsReadDataByIdentifier) + +#endif + +#if (UDS_SERVICE_READ_MEMORY_BY_ADDRESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ MEMORY BY ADDRESS(0x23) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK(UI_8 mem_size_len, + * UI_8 mem_addr_len, UI_8* mem_addr, UI_8* mem_size): The user must + * retrieve the requested memory address buffer and return it to the host + *****************************************************************************/ +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS (UDS_DEFAULT_SESSION_MASK | UDS_PROGRAMMING_SESSION_MASK | UDS_EXT_DIAG_SESSION_MASK) +#define UDS_SERVICE_READ_MEMORY_BY_ADDRESS_CALLBACK (UdsReadMemoryByAddress) + +#endif + + +#if (UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * WRITE DATA BY IDENTIFIER(0x2E) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UI_16 id, + * UI_8* p_buf, UI_16 size): This callback is + * responsible for starting the writting process to get the data written + * in the apporpiate memory position / device and to + * return the command that must be sent back to the tool + * id: The id to modify + * p_buf: Id data as sent by the diagnostics tool + * size: Amount of ID data bytes received + *****************************************************************************/ +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UdsWriteDataByIdentifier) + +#endif + +#if (UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * WRITE MEMORY BY ADDRES(0x3D) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_WRITE_DATA_BY_IDENTIFIER_CALLBACK (UI_8 id_high, + * UI_8 id_low, UI_8* p_buf, UI_16 size): + * This callback is used by the user to write the data identified with id + * in the appropiate mamory / device. The data sent by the host is passed + * in p_buf/size + *****************************************************************************/ +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS (UDS_DEFAULT_SESSION_MASK | UDS_PROGRAMMING_SESSION_MASK | UDS_EXT_DIAG_SESSION_MASK) +#define UDS_SERVICE_WRITE_MEMORY_BY_ADDRESS_CALLBACK (UdsWriteMemoryByAddr) + +#endif + + +#if (UDS_SERVICE_CONTROL_DTC_SETTING_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * CONTROL DTC SETTING (0x85) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK(UI_8 dtc_setting_mode, + * UI_8* buf_data_rx, I_16 size): + * size: size of the dtc option record received + * buf_data_rx: pointer to the dtc option record received + * This callback is responsible for sending the appropiate response + ****************************************************************************/ +//#define UDS_SERVICE_CONTROL_DTC_SETTING (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_CONTROL_DTC_SETTING_CALLBACK (UdsControlDtcSetting) + +#endif + + +#if (UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * CLEAR DTC INFORMATION(0x14) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * void UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK(UI_8* p_dtc_group) + * Clear all DTC codes identified by the p_dtc_group reference + *****************************************************************************/ +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_CLEAR_DIAGNOSTIC_INFORMATION_CALLBACK (UdsClearDtc) + +#endif + + +#if (UDS_SERVICE_READ_DTC_INFORMATION_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * READ DTC INFORMATION(0x19) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK (UI_16 id, + * UI_8* p_buf, UI_16 size): + * Retrieve and send the Diagnostics Info identified by id. + *****************************************************************************/ +#define UDS_SERVICE_READ_DTC_INFORMATION (UDS_ALL_SESSION_MASK) +#define UDS_SERVICE_READ_DTC_INFORMATION_CALLBACK (UdsReadDtc) + +#endif + + +#if (UDS_SERVICE_IO_CTRL_BY_ID_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * I/O CONTROL BY ID(0x2F) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_INPUT_OUTPUT_CONTROL_BY_ID(UI_8 *data_buffer, UI_8 size) +*****************************************************************************/ +#define UDS_SERVICE_IO_CTRL_BY_ID (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_IO_CTRL_BY_ID_CALLBACK (UdsInputOutputControlByIdentifier) + +#endif + + +#if (UDS_SERVICE_ROUTINE_CONTROL_STATUS == SERVICE_ENABLED) +/**************************************************************************** + * ROUTINE CONTROL(0x31) + **************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * UI_8 UDS_SERVICE_ROUTINE_CONTROL_START_CALLBACK(UI_8 id_high, UI_8 id_low, + * UI_16 size, UI_8 *data_buffer); + * Host wants to start a control routine. + * User is responsible for returning the appropiate response code. + ****************************************************************************/ +#define UDS_SERVICE_ROUTINE_CONTROL (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_SERVICE_ROUTINE_CONTROL_CALLBACK (UdsControlRoutine) + +#endif + + +#if (UDS_SERVICE_REQUEST_DOWNLOAD_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * REQUEST DOWNLOAD(0x34) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACK: + * UI_8 DEVICE_0_REQUEST_DOWNLOAD_CALLBACK(t_addr base_addr, t_addr last_addr) + * The host wnats to start a download from address dl_base with a size + * of dl_size in bytes. Calculate if this is possible. And give an answer + * Define one callback for each device in the system that may receive + * data through a downlonad. + ****************************************************************************/ +#define UDS_SERVICE_REQUEST_DOWNLOAD (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_REQUEST_DOWNLOAD_CALLBACK (UdsPlm2BLRequestDownload)*/ + +#endif + + +#if (UDS_SERVICE_TRANSFER_DATA_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TRANSFER DATA(0x36) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS + * UI_8 DEVICE_0_TRANSFER_DATA_CALLBACK(UI_8* pData, UI_16 size) + * A data block is sent by the host, program it in the right memory. + * The right destination address is responsability of the user callback + * Define one callback per each device that can receive the data + ****************************************************************************/ +#define UDS_SERVICE_TRANSFER_DATA (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_TRANSFER_DATA_CALLBACK (UdsPlm2BLTransferData)*/ + +#endif + + +#if (UDS_SERVICE_REQUEST_TRANSFER_EXIT_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * TRANSFER EXIT(0x37) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACK: + * UI_8 DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK(UI_8* pData, UI_16 size) + * The host informs us that the download process is finished + ****************************************************************************/ +#define UDS_SERVICE_REQUEST_TRANSFER_EXIT (UDS_PROGRAMMING_SESSION_MASK) +/*#define DEVICE_0_REQUEST_TRANSFER_EXIT_CALLBACK (UdsPlm2BLTransferExit)*/ + +#endif + +#if (UDS_SERVICE_COMMUNICATION_CONTROL_STATUS == SERVICE_ENABLED) +/***************************************************************************** + * COMMUNICATION CONTROL (0x28) + ***************************************************************************** + * This service CAN be enabled/disabled + * CALLBACKS: + * .- UDS_COMMUNICATION_CONTROL_CALLBACK: The user MAY implement this callback. + * DEFINES: + * .- UDS_COMMUNICATION_CONTROL. Session in which the service will be supported + ****************************************************************************/ +#define UDS_SERVICE_COMMUNICATION_CONTROL (UDS_EXT_DIAG_SESSION_MASK|UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_MASK) +#define UDS_COMMUNICATION_CONTROL_CALLBACK (UdsCommunicationControl) + +#endif +#endif diff --git a/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c new file mode 100644 index 0000000..f0f05c1 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.c @@ -0,0 +1,25 @@ + +/* ------------------------------ Includes --------------------------------- */ +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "UdsServerCallbacks_H61L.h" +#include "DiagnosticR/ProjectCfg.h" +//#include "FicoHwAbsADC.h" +//#include "ficoNVM_wrapper_dcm.h" +//#include "Dem.h" +//#include "QMGateway.h" + +/* --------------------------- Type Definitions ---------------------------- */ + +/* ------------------------------- Defines --------------------------------- */ +#define DTC_NUM_SUBFUNC ((uint8)0x16) +#define VALUE_IS_NOT_USED ((uint8)0x00) +#define BYTES_TO_DTC(hb, mb, lb) (((uint32)(hb) << 16) | ((uint32)(mb) << 8) | (uint32)(lb)) +#define DTC_HIGH_BYTE(dtc) (((uint32)(dtc) >> 16) & 0xFFu) +#define DTC_MID_BYTE(dtc) (((uint32)(dtc) >> 8) & 0xFFu) +#define DTC_LOW_BYTE(dtc) ((uint32)(dtc) & 0xFFu) + + + + + diff --git a/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.h b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.h new file mode 100644 index 0000000..5c0aac6 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/Iso15765_layer3/_h61/UdsServerCallbacks_H61L.h @@ -0,0 +1,86 @@ +#ifndef __UDSSERVERCALLBACKS_GM_H +#define __UDSSERVERCALLBACKS_GM_H + +/* ------------------------------ Includes --------------------------------- */ +#include "Global.h" +#include "Iso15765_3_CFG.h" + +/* --------------------------- Type Definitions ---------------------------- */ + +/* ------------------------------- Defines --------------------------------- */ +#define START_DOWNLOAD_VALUE (0xABC1) /* Memory value to indicate to the bootloader that a reprogramming session is requested */ + +/************************* DATA IDENTIFIERS ***********************************/ + +/*** SUPPORTED DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES ***/ +#define DID_DIO_HALL_SENSOR_VALUES ((uint16)0xB000) +#define DID_DIO_ST ((uint16)0xB001) +#define DID_DIO_HOLD ((uint16)0xB002) +#define DID_DIO_SNS_ENA ((uint16)0xB003) +#define DID_DIO_HALL_ENA_1 ((uint16)0xB004) +#define DID_DIO_HALL_SNS_2 ((uint16)0xB005) +#define DID_DIO_STR_RLY_CTRL ((uint16)0xB006) +#define DID_DIO_REV_LMP_CTRL ((uint16)0xB007) +#define DID_DIO_RESET_TO_SUPERVISOR ((uint16)0xB008) +#define DID_ADC_IGN_SNS ((uint16)0xB100) +#define DID_ADC_BAT_12V_SNS ((uint16)0xB101) +#define DID_ADC_PWR_OR_SNS ((uint16)0xB102) +#define DID_ADC_2V5REFA ((uint16)0xB103) +#define DID_ADC_VCC_B_SNS ((uint16)0xB104) +#define DID_ADC_VCC_C_SNS ((uint16)0xB105) +#define DID_ADC_VCC_HALL_A_SNS ((uint16)0xB106) +#define DID_ADC_VCC_HALL_B_SNS ((uint16)0xB107) +#define DID_ADC_HW_VERSION ((uint16)0xB108) +#define DID_ADC_REV_LMP_SNS ((uint16)0xB109) +#define DID_ADC_STR_RLY_SNS ((uint16)0xB110) +#define DID_COLUMN_SHIFTER_DETECTION ((uint16)0xB020) + + +/* Routine Control */ +#define DID_Periodic_ID ((uint16)0xF005)/* Same than NEVs */ +#define DID_UDS_Resp_ID ((uint16)0xF006)/* Same than NEVs */ +#define DID_UDS_Req_ID ((uint16)0xF007)/* Same than NEVs */ + +/* IO Control */ +#define DID_HS_Control ((uint16)0xF100) +#define DID_SR_Control ((uint16)0xF101) +#define DID_RLR_Control ((uint16)0xF102) + +/* Logistic data */ +#define DID_FICOSA_HW_ID ((UI_16)0xF192) +#define DID_FICOSA_SW_ID ((UI_16)0xF194) + +#define DID_PP_DIO_HALL_SENSOR_VALUES ((uint16)0xFD00) +#define DID_PP_DIO_ST ((uint16)0xFD01) +#define DID_PP_DIO_HOLD ((uint16)0xFD02) +#define DID_PP_DIO_SNS_ENA ((uint16)0xFD03) +#define DID_PP_DIO_HALL_ENA_1 ((uint16)0xFD04) +#define DID_PP_DIO_HALL_SNS_2 ((uint16)0xFD05) +#define DID_PP_DIO_STR_RLY_CTRL ((uint16)0xFD06) +#define DID_PP_DIO_REV_LMP_CTRL ((uint16)0xFD07) +#define DID_PP_DIO_RESET_TO_SUPERVISOR ((uint16)0xFD08) +#define DID_PP_ADC_IGN_SNS ((uint16)0xFD20) +#define DID_PP_ADC_BAT_12V_SNS ((uint16)0xFD21) +#define DID_PP_ADC_PWR_OR_SNS ((uint16)0xFD22) +#define DID_PP_ADC_2V5REFA ((uint16)0xFD23) +#define DID_PP_ADC_VCC_B_SNS ((uint16)0xFD24) +#define DID_PP_ADC_VCC_C_SNS ((uint16)0xFD25) +#define DID_PP_ADC_VCC_HALL_A_SNS ((uint16)0xFD26) +#define DID_PP_ADC_VCC_HALL_B_SNS ((uint16)0xFD27) +#define DID_PP_ADC_HW_VERSION ((uint16)0xFD28) +#define DID_PP_ADC_REV_LMP_SNS ((uint16)0xFD29) +#define DID_PP_ADC_STR_RLY_SNS ((uint16)0xFD30) +#define DID_PP_PRODUCTION_DATA ((uint16)0xFE00) +#define DID_PP_UDS_SESSION_CHECK ((uint16)0xFE01) +#define DID_PP_START_UP_HS_CHECK ((uint16)0xFE02) +/* Logistic data */ +#define DID_PP_FICOSA_HW_ID ((UI_16)0xFE92) +#define DID_PP_FICOSA_SW_ID ((UI_16)0xFE94) + +/* Definitions needed for the Read/WriteMemoryByAddress UDS services */ +#define FIXED_ADDR_LEN ((UI_8)4) +#define MAX_ADDR_SIZE ((UI_8)4) +#define MAX_SIZE_LEN ((UI_8)0xFF) +#define DIAG_TX_RX_BUF_LEN ((UI_8)0xFF) +#define MAX_DATA_SIZE ((UI_8)4) +#endif diff --git a/firmware/src/DiagnosticR/UDS/ModelsInterfaces/CommonMacros.h b/firmware/src/DiagnosticR/UDS/ModelsInterfaces/CommonMacros.h new file mode 100644 index 0000000..baeb26c --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/ModelsInterfaces/CommonMacros.h @@ -0,0 +1,136 @@ +/** + * Copyright (c) 2018 + * + * @file + * Common Macros and Constants Non Platform Related + */ + +#ifndef COMMON_H_ +#define COMMON_H_ + +/* --------------------------------------------------------------------------- + * Includes + */ +//#include +#include +#include + + +#define CLI + +/* --------------------------------------------------------------------------- + * Printing + */ + +#define PRINTF(...) printf(__VA_ARGS__) +#define TRACE_PRINT(...) printf(__VA_ARGS__) + +/* --------------------------------------------------------------------------- + * Exported Constants + */ + +#define PROMPT "\n# " +#define SUCCESS 0 +#define ERROR 1 +//#define TRUE 1 +//#define FALSE 0 + +/* --------------------------------------------------------------------------- + * Exported Macros + */ + +/* --------------------------------------------------------------------------- + * Variadic macro argument helpers + */ + +/** + * Expand first argument in variadic list. + */ +#define FIRST(...) FIRST_HELPER(__VA_ARGS__, throwaway) +#define FIRST_HELPER(first, ...) first + +/** + * Expand to "," and subsequent arguments in variadic list if any, else empty. + * + * Arbitrary limit of 9 arguments. + */ +#define REST(...) REST_HELPER(NUM(__VA_ARGS__), __VA_ARGS__) +#define REST_HELPER(qty, ...) REST_HELPER2(qty, __VA_ARGS__) +#define REST_HELPER2(qty, ...) REST_HELPER_##qty(__VA_ARGS__) +#define REST_HELPER_ONE(first) +#define REST_HELPER_TWOORMORE(first, ...) , __VA_ARGS__ +#define NUM(...) SELECT_10TH(__VA_ARGS__, TWOORMORE, TWOORMORE, TWOORMORE, TWOORMORE,\ + TWOORMORE, TWOORMORE, TWOORMORE, TWOORMORE, ONE, throwaway) +#define SELECT_10TH(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, ...) a10 + +/** + * Stringify a token + * + * #define foo 4 + * STR(foo) -> "foo" + */ +#define STR(s) #s + +/** + * Expand, then stringify a token + * + * #define foo 4 + * XSTR(foo) -> "4" + */ +#define XSTR(s) STR(s) + + +#define COUNTOF(a) (sizeof(a)/sizeof(*(a))) +#define NOOF(a) (sizeof(a)/sizeof(a[0])) +#define UNUSED(x) (void)x + +/** 1st dimension of fixed-size array */ +#define ARRAY_DIM(a) (sizeof(a) / sizeof((a)[0])) + +/** Pointer to 1st element of fixed-size array - used to start iterations */ +#define ARRAY_START(a) (&(a)[0]) + +/** Pointer to last element + 1 of fixed-size array - used to terminate iterations */ +#define ARRAY_STOP(a) (ARRAY_START(a) + ARRAY_DIM(a)) + +#define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(!!(COND))*2-1] +// token pasting madness: +#define COMPILE_TIME_ASSERT3(X,L) STATIC_ASSERT(X,static_assertion_at_line_##L) +#define COMPILE_TIME_ASSERT2(X,L) COMPILE_TIME_ASSERT3(X,L) +#define COMPILE_TIME_ASSERT(X) COMPILE_TIME_ASSERT2(X,__LINE__) + +#define LINK_SECTION(name) __attribute__((section(#name))) + +/** + * Tag a static variable to force compiler not to optimise it away. + * + * E.g. a variable in shared ram that is only read. + * + * Prefer to "volatile" for this purpose (only) as volatile changes the type. + */ +#define COMPILER_KEEP __attribute__((__used__)) + +/** + * Tag XCP diagnostic variable (read only). + */ +#define XCP_DIAGNOSTIC LINK_SECTION(.xcp.diag) + +/** + * Tag XCP calibration variable (read/write). + */ +#define XCP_CALIBRATION LINK_SECTION(.xcp.cal) + + +/* --------------------------------------------------------------------------- + * Exported Types + */ + +/* --------------------------------------------------------------------------- + * Exported Variables + */ + +/* --------------------------------------------------------------------------- + * Exported Functions + */ + +#endif /* COMMON_H_ */ diff --git a/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.c b/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.c new file mode 100644 index 0000000..65cf88c --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.c @@ -0,0 +1,1223 @@ + +/* ------------------------------ Includes --------------------------------- */ +//#include "CommonMacros.h" +#include "UDS_CoreServices_CB.h" + +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "DiagnosticR/Dem/Dem_Types.h" +#include "DiagnosticR/rte/Rte_Dem_Type.h" +#include "DiagnosticR/Dem/Dem.h" + +//#include "Mcu.h" +//#include "Dio.h" +//#include "Nvm.h" +//#include "Dem.h" +//#include "revision.h" +#include "UDS_Services_Common.h" +//#include "WdgM_API.h" +//#include "BswM_API.h" +#include +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h" +//#include "Uja1169fdWdgUpdate_functions.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" +#include "OsekCom/OsekCom.h" +//#include "App_Boot.h" +//#include "ficoNVM.h" +//#include "AppMode_If.h" +//#include "QMGateway.h" +//#include "SecurityAlgorithm.h" +/* --------------------------- Type Definitions ---------------------------- */ + +/* ------------------------------- Defines --------------------------------- */ +#define DTC_NUM_SUBFUNC ((uint8)0x16) +#define VALUE_IS_NOT_USED ((uint8)0x00) +#define BYTES_TO_DTC(hb, mb, lb) (((uint32)(hb) << 16) | ((uint32)(mb) << 8) | (uint32)(lb)) +#define DTC_HIGH_BYTE(dtc) (((uint32)(dtc) >> 16) & 0xFFu) +#define DTC_MID_BYTE(dtc) (((uint32)(dtc) >> 8) & 0xFFu) +#define DTC_LOW_BYTE(dtc) ((uint32)(dtc) & 0xFFu) + +#define DATA_SIZE_ZERO ((UI_8)0) +#define DATA_SIZE_ONE ((UI_8)1) +#define DATA_SIZE_TWO ((UI_8)2) +#define DATA_SIZE_THREE ((UI_8)3) +#define DATA_SIZE_FOUR ((UI_8)4) +#define DATA_SIZE_PP ((UI_8)100) +#define DATA_SIZE_ECU_SER_NO ECU_SERIAL_NUMBER_SIZE + +#define DATA_DEFAULT_SNAPSHOT_REC_NO ((UI_8)0x01) +#define DATA_DEFAULT_SNAPSHOT_REC_NO2 ((UI_8)0x02) + +/*--------------------------- Global variables ---------------------------- */ + +/* Current session of the diagnostics server layer */ +static UI_8 current_session = UDS_DEFAULT_SESSION; + +/* Global variable to request a reset to the whole DEFC system */ +BOOL do_ecu_reset = FALSE; + +/* Bootloader variable that tells if bootloader must respond or not to the session +change when coming from application (supress positive response) */ +UI_16 start_download_response; +static UI_16 *start_download = (UI_16 *)0x20000000; +volatile boolean suppress_positive_bit; +UI_8 manufactory_mode = 0xFF; +#if 0 +#pragma ghs section bss=".fbl_shared" + +volatile uint8 mcu_reset_type; + +volatile uint8 suppress_positive_bit_valid_info; +uint8 security_faa_flag = 0; +static uint8 reset_flag = 0; + +#pragma ghs section +#endif +BOOL clear_dtc_flag = FALSE; +/* ------------------------- Function --------------------------- */ + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the DEFCUdsTesterPresent diagnostic service and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Arguments: + | - tp_type: tester present type requested + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsTesterPresent(UI_8 tp_type) { + UI_8 response_mode; + + /* Only accepts if tester present type is 0x01 */ + if (tp_type == 0x01) { + response_mode = ISO15765_3_POSITIVE_RESPONSE; + } else { + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + /* We send the answer with the adequate measure */ + Iso15765_3SendResponse(response_mode); +} + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands all the ReadDataByIdentifier diagnostics and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Arguments: + | - id_h: higher byte of the identifier requested + | - id_h: lower byte of the identifier requested + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +UI_8 UdsReadDataByIdentifier(UI_8 id_h, UI_8 id_l) +{ + return (UI_8)UDS_ReadDiD_CB(id_h, id_l); +} + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands all the WriteDataByIdentifier diagnostics and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Arguments: + | - id_h: higher byte of the identifier requested + | - id_h: lower byte of the identifier requested + | - data_buffer: data pointer of the received parameters for the write + | - size: length of the parameters received for the write + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsWriteDataByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 *buf_data_rx, UI_16 size) +{ + (void)UDS_WriteDiD_CB(id_h, id_l, buf_data_rx, size); +} +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the InputOutputControlByLocalId diagnostic + | service and is responsible for giving the final answer to ISO_3 layer + |--------------------------------------------------------------------------- + | Arguments: + | - id: identifier of the requested input output control + | - size: length of the data received to control + | - data: data pointer to the received control data + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +#if 0 +void UdsInputOutputControlByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 io_ctrl_type, UI_8* buf_data_rx, UI_16 size) +{ + (void)UDS_IOControl_CB(id_h, id_l, io_ctrl_type, buf_data_rx, size); +} +#endif +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands all the WriteDataByIdentifier diagnostics and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Arguments: + | - sub_function: sub function + | - data_buffer: data pointer of the received parameters for the write + | - size: length of the parameters received for the write + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +#if 0 +void UdsControlDtcSetting(UI_8 sub_function, UI_8 *buf_data_rx, UI_16 size) +{ + (void)UDS_DTCSetting_CB(sub_function,buf_data_rx, size); +} +#endif +/***************************************************************************** + | Portability: + |---------------------------------------------------------------------------- + | Description: + | * Called when layer 3 changes session + |--------------------------------------------------------------------------- + | Arguments: + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +//#include "WdgM_API.h" +//#include "WdgM_Types.h" +//extern uint8 application_active; +void UdsIniSession(void) +{ + /* Save the current session */ + current_session = Iso15765_3QueryActiveSession(); + + switch(current_session){ + + case UDS_DEFAULT_SESSION: + /* Nothing to be done for now in the GM project */ + // SET_FLAG_DTC_SETTING(); + + // EnableTxFrm_shiftselectposition(); +// EnableTxFrm_gsm_nm(); + + /* Enable Rx */ + // CAN_RX_CONFIG_ENABLE(); + + /* disable UDS IO control */ + //uds_control_led = FALSE; + //uds_control_led_lmc = FALSE; + //uds_control_led_conbyte = 0; + break; + case UDS_EXT_DIAG_SESSION: + /* Nothing to be done */ + break; + case UDS_PROGRAMMING_SESSION: + /* Bootloader enters Programming session after reset */ + + start_download[0] = START_DOWNLOAD_VALUE; + + DCACHE_CLEAN_BY_ADDR(start_download, 2); + if(iso15765_3_supress_pos_resp == TRUE){ + start_download_response = START_DOWNLOAD_VALUE; + }else{ + start_download_response = ((UI_8)0); + } + + Iso15765_3SendResponse(UDS_ERR_RESPONSE_PENDING); + suppress_positive_bit = 1; + + /* TODO: move reset after response in main loop */ + __NVIC_SystemReset(); + break; + case UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID: + /* Nothing to be done */ + break; + + default: + break; + } + +} + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * UdServices diagnostic initialitzation task. This routine should only + | be called one time at the microcontroller initialization + |--------------------------------------------------------------------------- + | Arguments: + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsServerCallbacksInit(void) { + +} + +/***************************************************************************** + | Portability: + |---------------------------------------------------------------------------- + | Description: + | * UdServices diagnostic task executed in every main cycle + |--------------------------------------------------------------------------- + | Arguments: + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsServerCallbacksTask(void) { + +} + +/***************************************************************************** + | Portability: Generic + |---------------------------------------------------------------------------- + | Routine description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | void : ... + | result none : ... + /---------------------------------------------------------------------------*/ +#if 1 +void UdsExecuteResetNow(UI_8 reset_type) +{ + //reset_flag = reset_type; + if (reset_type == UDS_HARD_RESET) { + //RequestReleaseRun(SHUTDOWN_HARD_RESET); + while(1) + { + } + + } else if (reset_type == UDS_KEY_ON_OFF_RESET) { + Dem_SetOperationCycleState(DEM_IGNITION,DEM_CYCLE_STATE_END); + //RequestReleaseRun(SHUTDOWN_HARD_RESET); + + } + else if(reset_type == UDS_SOFT_RESET) + { + do_ecu_reset = TRUE; + NVIC_SystemReset(); + //RequestReleaseRun(SHUTDOWN_SOFT_RESET); + + } + else { + /* Do nothing */ + } +} + +boolean doReset(void) +{ + return do_ecu_reset; +} + +BOOL CHECK_RESET_TYPE(UI_8 reset_type){ + BOOL result = FALSE; + /* check supported reset sub function. Only hard reset is supported as per the requirements */ + if ((reset_type == UDS_HARD_RESET)||(reset_type == UDS_KEY_ON_OFF_RESET)) { + result = TRUE; + }else if(reset_type == UDS_SOFT_RESET) + { + result = TRUE; + } + else { + result = FALSE; + } + return result; +} + + +/***************************************************************************** + | Portability: Generic + |---------------------------------------------------------------------------- + | Routine description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | void : ... + | result none : ... + /---------------------------------------------------------------------------*/ +BOOL UdsCheckResetIsPossible(UI_8 reset_type) +{ + BOOL result; + /* Temporary all sessions allowed to reset */ + if (current_session) { + result = TRUE; + } + else { + result = FALSE; + } + return result; +} +#endif +/***************************************************************************** + | Portability: + |---------------------------------------------------------------------------- + | Description: + | * Callback for the routine control service callback. + |--------------------------------------------------------------------------- + | Arguments: + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +#if 1 +void UdsControlRoutine(UI_8 routine_ctrl_type, UI_8 id_high, UI_8 id_low, UI_8 *routine_entry_option, UI_16 size) +{ + (void)UDS_RoutineControl_CB(routine_ctrl_type, id_high, id_low, routine_entry_option, size); +} +#endif +/***************************************************************************** + | Portability: + |---------------------------------------------------------------------------- + | Description: + | * Callback for the read DTC callback. + |--------------------------------------------------------------------------- + | Arguments: + |--------------------------------------------------------------------------- + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +#if 1 +void UdsReadDtc(UI_8 id, UI_8 *data, UI_16 size) { + tp_uds_read_dtc_information_resp resp; + Dem_ReturnSetFilterType setDtcFilterResult = DEM_FILTER_ACCEPTED; + Dem_ReturnGetStatusOfDTCType GetStatusOfDtc = DEM_STATUS_OK; + Dem_EventStatusExtendedType dtcStatus = DEM_EVENT_STATUS_PASSED; + Dem_ReturnGetNextFilteredDTCType getNextFilteredDtcResult = DEM_FILTERED_OK; + Dem_ReturnGetNumberOfFilteredDTCType getNumerResult; + uint16 numberOfFilteredDtc = 0; + Std_ReturnType result = E_OK; + uint32 DtcNumber = 0; + uint32 dtc = 0x000000; + uint16 nrOfDtcs = 0; + uint16 requested_status_mask = 0x00; + uint8 dtcStatusMask = 0xFF; /* polyspace MISRA-C:10.1 [Justified:Low] "0xFF perfectly fits an object 8 bits wide." */ + uint8 RecordNumber = 0; + uint8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + /* Snapshot data */ + uint8 record = 1; + uint16 nofBytesCopied = 0; + uint16 bufSizeLeft = 0; + uint8 snapshot_data[128] = {0}; + uint8 snapshot_data_tores[2][20] = {0}; + uint8 index = 0; + /* Extended date */ + uint8 startRecNum; + uint8 endRecNum; +// uint8 extended_data[10] = {0}; + + /* prepares response estructure */ + resp = ISO15765_3_GET_RESP_DATA(tp_uds_read_dtc_information_resp); + switch (id) { + /* 0x01 Subservice from Read DTC */ + case REPORT_NUMBER_OF_DTC_BY_STATUS_MASK: + { + if(DATA_SIZE_ONE==size){ + /* filter the DTC for the corresponding status mask requested */ + requested_status_mask = *data; + setDtcFilterResult = Dem_SetDTCFilter(requested_status_mask, DEM_DTC_KIND_ALL_DTCS, DEM_DTC_FORMAT_UDS, DEM_DTC_ORIGIN_PRIMARY_MEMORY, DEM_FILTER_WITH_SEVERITY_NO, VALUE_IS_NOT_USED, DEM_FILTER_FOR_FDC_NO); /* polyspace MISRA-C:10.1 [Justified:Low] "I can't see the object of type UI_16." */ + if (setDtcFilterResult == DEM_FILTER_ACCEPTED) { + + /* Fill the anwer with all the DTC founded */ + getNumerResult = Dem_GetNumberOfFilteredDtc(&numberOfFilteredDtc); + if (getNumerResult == DEM_NUMBER_OK) { + /* Create positive response (ISO 14229-1 table 251) */ + resp->subservice = 0x01; + resp->buffer_dades[0] = requested_status_mask;/*data;*/ /* DTCStatusAvailabilityMask */ /* polyspace MISRA-C:10.1 [Justified:Low] "To be analyzed by the software component owner." */ + resp->buffer_dades[1] = 0x01; /* DTC format ISO 14229-1 */ + resp->buffer_dades[2] = (numberOfFilteredDtc >> 8); /* DTCCountHighByte */ /* polyspace MISRA-C:10.1 [Justified:Low] "No problem here because we are discarding half the bits, so only 8 are left." */ + resp->buffer_dades[3] = (numberOfFilteredDtc & 0xFFu); /* DTCCountLowByte */ /* polyspace MISRA-C:10.1 [Justified:Low] "0xFF perfectly fits an object 8 bits wide." */ + Iso15765_3IncrementResponseSize(5); + } + else { + /* NOTE: What to do? */ + response_mode = UDS_ERR_GENERAL_REJECT; + } + } + else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + }else{ + response_mode = UDS_ERR_INVALID_FORMAT; + } + } + break; + /* 0x02 Subservice from Read DTC */ + case REPORT_DTC_BY_STATUS_MASK: + { + if(DATA_SIZE_ONE==size){ + /* filter the DTC for the corresponding status mask requested */ + requested_status_mask = *data; + setDtcFilterResult = Dem_SetDTCFilter(requested_status_mask, DEM_DTC_KIND_ALL_DTCS, DEM_DTC_FORMAT_UDS, DEM_DTC_ORIGIN_PRIMARY_MEMORY, DEM_FILTER_WITH_SEVERITY_NO, VALUE_IS_NOT_USED, DEM_FILTER_FOR_FDC_NO); /* polyspace MISRA-C:10.1 [Justified:Low] "I can't see the object of type UI_16." */ + if (setDtcFilterResult == DEM_FILTER_ACCEPTED) { + result = Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask); + if (result != E_OK) { + dtcStatusMask = 0; + } + + /* Get the number of DTCs to set a limit in the while */ + getNumerResult = Dem_GetNumberOfFilteredDtc(&numberOfFilteredDtc); + + if (dtcStatusMask != 0x00) { /** @req DCM008 */ + getNextFilteredDtcResult = Dem_GetNextFilteredDTC(&dtc, &dtcStatus); + /* Fill the answer with all the DTC founded */ + while ((getNextFilteredDtcResult == DEM_FILTERED_OK) && ((numberOfFilteredDtc) >= (nrOfDtcs-1))) { + if (nrOfDtcs < 1024) /* see AXOECUGBA-1104 */ + { + resp->buffer_dades[(nrOfDtcs*4)+1] = DTC_HIGH_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+2] = DTC_MID_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+3] = DTC_LOW_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+4] = dtcStatus; + } /* else: we would be accessing outside resp->buffer_dades */ + nrOfDtcs++; + + getNextFilteredDtcResult = Dem_GetNextFilteredDTC(&dtc, &dtcStatus); + } + + if (getNextFilteredDtcResult != DEM_FILTERED_NO_MATCHING_DTC) { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + } + resp->subservice = 0x02; + resp->buffer_dades[0] = 0xFF;/*(uint8) nrOfDtcs; */ /* polyspace MISRA-C:10.1 [Justified:Low] "It is expected that nrOfDtcs will have a small enough value." */ + Iso15765_3IncrementResponseSize((nrOfDtcs*4)+2); + } + else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + }else{ + response_mode = UDS_ERR_INVALID_FORMAT; + } + } + break; + /* 0x04 Subservice from Read DTC */ + case REPORT_DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER: + { + /* Now let's assume DTC has 3 bytes. */ + DtcNumber = (((uint32)data[0])<<16) + (((uint32)data[1])<<8) + ((uint32)data[2]); /* polyspace MISRA-C:17.4 [Justified:Low] "The only potential problem here would be accessing outside the memory buffer pointed by the pointer; we trust Polyspace to check whether this happens." */ + GetStatusOfDtc = Dem_GetStatusOfDTC(DtcNumber, DEM_DTC_ORIGIN_PRIMARY_MEMORY, &dtcStatus); /** @req DCM383 */ + + if(GetStatusOfDtc != DEM_STATUS_OK){ + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + }else if(DATA_SIZE_FOUR != size){ + response_mode = UDS_ERR_INVALID_FORMAT; + }else{ + + resp->buffer_dades[0] = DTC_HIGH_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[1] = DTC_MID_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[2] = DTC_LOW_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[3] = dtcStatus; + resp->subservice = 0x04; + Iso15765_3IncrementResponseSize(5); + + /*** start DTC snapshot read ***/ + RecordNumber = data[3]; /* polyspace MISRA-C:17.4 [Justified:Low] "The only potential problem here would be accessing outside the memory buffer pointed by the pointer; we trust Polyspace to check whether this happens." */ + /* !req DCM372 *//* !req DCM702 */ + if(( (0xFF == RecordNumber) || (RecordNumber == 0x01) || (RecordNumber == 0x02))) /* polyspace MISRA-C:10.1 [Justified:Low] "0xFF is an 8-bit integer value." */ + { + /* Request for all freeze frames */ + Dem_ReturnGetFreezeFrameDataByDTCType ret = DEM_GET_FFDATABYDTC_OK; + /* Check the maxim 10 records availables */ + for (record = 0; record <= 2; record++) + { + bufSizeLeft = 512; /* PATCH RSBWGB-1386: make sure condition bufSize >= FFDataSize */ + ret = Dem_GetFreezeFrameDataByDTC(DtcNumber, DEM_DTC_ORIGIN_PRIMARY_MEMORY, + /* record, (uint8*)(resp->buffer_dades[4]), &bufSizeLeft); */ + record, snapshot_data, &bufSizeLeft); + + if( ret == DEM_GET_FFDATABYDTC_OK) + { + nofBytesCopied += bufSizeLeft;/* !req DCM441 */ + if(record == 1) + { for(index = 0; index <= 19; index++) + snapshot_data_tores[0][index] = snapshot_data[index]; + } + else if(record == 2) + { + for(index = 0; index <= 19; index++) + snapshot_data_tores[1][index] = snapshot_data[index]; + } + } + else + { + } + bufSizeLeft = 0; + + } + + //while( (bufSizeLeft < nofBytesCopied) && (bufSizeLeft < 128)) /* see AXOECUGBA-1104 -- 128 is the size (in cells) of snapshot_data */ + //{ + // resp->buffer_dades[bufSizeLeft+4] = snapshot_data[bufSizeLeft]; + // bufSizeLeft++; + // } + //<< + if(RecordNumber == 0x02) + { + resp->buffer_dades[4] = 0x02; + for(index = 0; index <= 18; index++ ) + { + resp->buffer_dades[index + 5] = snapshot_data_tores[1][index + 1]; + } + Iso15765_3IncrementResponseSize(20); + } + + else if(RecordNumber == 0xFF) + { + resp->buffer_dades[4] = DATA_DEFAULT_SNAPSHOT_REC_NO; + for(index = 0; index <= 18; index++) + { + resp->buffer_dades[index + 5] = snapshot_data_tores[0][index + 1]; + } + + for(index = 0; index <= 19; index++) + { + resp->buffer_dades[index + 24] = snapshot_data_tores[1][index]; + } + + resp->buffer_dades[24] = 0x02; + resp->buffer_dades[25] = 0x05; + resp->buffer_dades[26] = 0xB0; + resp->buffer_dades[27] = 0x01; + resp->buffer_dades[30] = 0xB0; + resp->buffer_dades[31] = 0x03; + resp->buffer_dades[33] = 0xB0; + resp->buffer_dades[34] = 0x04; + resp->buffer_dades[36] = 0xB0; + resp->buffer_dades[37] = 0x05; + resp->buffer_dades[40] = 0xB0; + resp->buffer_dades[41] = 0x06; + Iso15765_3IncrementResponseSize(40); + } + else + { + resp->buffer_dades[4] = DATA_DEFAULT_SNAPSHOT_REC_NO; + for(index = 0; index <= 18; index++) + { + resp->buffer_dades[index + 5] = snapshot_data_tores[0][index + 1]; + } + Iso15765_3IncrementResponseSize(20); + } + resp->buffer_dades[5] = 0x05; + resp->buffer_dades[6] = 0xB0; + resp->buffer_dades[7] = 0x01; + resp->buffer_dades[10] = 0xB0; + resp->buffer_dades[11] = 0x03; + resp->buffer_dades[13] = 0xB0; + resp->buffer_dades[14] = 0x04; + resp->buffer_dades[16] = 0xB0; + resp->buffer_dades[17] = 0x05; + resp->buffer_dades[20] = 0xB0; + resp->buffer_dades[21] = 0x06; + //>> + //Iso15765_3IncrementResponseSize(nofBytesCopied); + if(nofBytesCopied == 0) + { + //Iso15765_3IncrementResponseSize(20); + } + }/*** finish DTC snapshot read ***/ + else + { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + + } + } + break; + + /* 0x06 Subservice from Read DTC */ + case REPORT_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER: + { + if (DATA_SIZE_FOUR == size){ + uint8 recNum; + /* Now let's assume DTC has 3 bytes. */ + DtcNumber = (((uint32)data[0])<<16) + (((uint32)data[1])<<8) + ((uint32)data[2]); /* polyspace MISRA-C:17.4 [Justified:Low] "The only potential problem here would be accessing outside the memory buffer pointed by the pointer; we trust Polyspace to check whether this happens." */ + GetStatusOfDtc = Dem_GetStatusOfDTC(DtcNumber, DEM_DTC_ORIGIN_PRIMARY_MEMORY, &dtcStatus); /** @req DCM383 */ + + if(GetStatusOfDtc != DEM_STATUS_OK){ + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + }else{ + resp->buffer_dades[0] = DTC_HIGH_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[1] = DTC_MID_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[2] = DTC_LOW_BYTE(DtcNumber); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[3] = dtcStatus; + resp->subservice = 0x06; + // Iso15765_3IncrementResponseSize(5); + + + /*** start extended data read ***/ + RecordNumber = data[3];//Consider more about the 0xFF; + + if(RecordNumber == 0xFF || RecordNumber == 0x01 || RecordNumber == 0x02 || RecordNumber == 0x03 || + RecordNumber == 0x05 || RecordNumber == 0x04) + { + + startRecNum = 1; + endRecNum = 5; + #if 0 + /* because of the definition of DPT in GAC, and Autosar can not fullfill the requirement */ + + switch (RecordNumber){ + case 0xFF: // Report all Extended Data Records for a particular DTC + startRecNum = 0x00; + endRecNum = 0xEF; + break; + + case 0xFE: // Report all OBD Extended Data Records for a particular DTC + startRecNum = 0x90; + endRecNum = 0xEF; + break; + + default: // Report one specific Extended Data Records for a particular DTC + startRecNum = data[3]; + endRecNum = startRecNum; + break; + } + #endif + + + uint8 txIndex = 4; + uint16 recLength = 0; + Dem_ReturnGetExtendedDataRecordByDTCType getExtendedDataRecordByDtcResult; + //boolean foundValidRecordNumber = FALSE; + UI_8 extended_data[20] = {0,0,0,0,1,0,2,0,3,0,4,0,5,0}; + + for (recNum = startRecNum; recNum <= endRecNum; recNum++) { + recLength = 512 - (txIndex + 1); // Calculate what's left in buffer + getExtendedDataRecordByDtcResult = Dem_GetExtendedDataRecordByDTC(DtcNumber, DEM_DTC_ORIGIN_PRIMARY_MEMORY, recNum, &extended_data[txIndex+1], &recLength); + if (getExtendedDataRecordByDtcResult == DEM_RECORD_OK) { + //foundValidRecordNumber = TRUE; + if (recLength > 0) { + extended_data[txIndex++] = recNum; + /* Instead of calling Dem_GetSizeOfExtendedDataRecordByDTC() the result from Dem_GetExtendedDataRecordByDTC() is used */ + /* !req DCM478 */ + txIndex += recLength; + } + } + // if (!foundValidRecordNumber) { + // + // response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + // } + } + + switch (RecordNumber) + { + case 0xFF: + resp->buffer_dades[4] = extended_data[4]; + resp->buffer_dades[5] = extended_data[5]; + resp->buffer_dades[6] = extended_data[6]; + resp->buffer_dades[7] = extended_data[7]; + resp->buffer_dades[8] = extended_data[8]; + resp->buffer_dades[9] = 0;//extended_data[9]; + resp->buffer_dades[10] = extended_data[10]; + resp->buffer_dades[11] = extended_data[11]; + resp->buffer_dades[12] = extended_data[12]; + resp->buffer_dades[13] = extended_data[13]; + Iso15765_3IncrementResponseSize(15); //14,11 + break; + case 0x01: + resp->buffer_dades[4] = extended_data[4]; + resp->buffer_dades[5] = extended_data[5]; + Iso15765_3IncrementResponseSize(7); + break; + case 0x02: + resp->buffer_dades[4] = extended_data[6]; + resp->buffer_dades[5] = extended_data[7]; + Iso15765_3IncrementResponseSize(7); + break; + case 0x03: + resp->buffer_dades[4] = extended_data[8]; + resp->buffer_dades[5] = 0;//extended_data[9]; + Iso15765_3IncrementResponseSize(7); + break; + case 0x04: + resp->buffer_dades[4] = extended_data[10]; + resp->buffer_dades[5] = extended_data[11]; + Iso15765_3IncrementResponseSize(7); + break; + case 0x05: + resp->buffer_dades[4] = extended_data[12]; + resp->buffer_dades[5] = extended_data[13]; + Iso15765_3IncrementResponseSize(7); + break; + default: + resp->buffer_dades[4] = extended_data[4]; + resp->buffer_dades[5] = extended_data[5]; + Iso15765_3IncrementResponseSize(7); + break; + } + + } + else{ + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + } + } + else{ + response_mode = UDS_ERR_INVALID_FORMAT; + } + } + break; + + + /* 0x0A Subservice from Read DTC */ + case REPORT_SUPPORTED_DTC: + { + if(DATA_SIZE_ZERO==size){ + /* filter the DTC for the DEM_DTC_STATUS_MASK_ALL status mask */ + setDtcFilterResult = Dem_SetDTCFilter(DEM_DTC_STATUS_MASK_ALL, DEM_DTC_KIND_ALL_DTCS, DEM_DTC_FORMAT_UDS, DEM_DTC_ORIGIN_PRIMARY_MEMORY, DEM_FILTER_WITH_SEVERITY_NO, VALUE_IS_NOT_USED, DEM_FILTER_FOR_FDC_NO); + if (setDtcFilterResult == DEM_FILTER_ACCEPTED) { + result = Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask); + if (result != E_OK) { + dtcStatusMask = 0; + } + + /* Get the number of DTCs to set a limit in the while */ + getNumerResult = Dem_GetNumberOfFilteredDtc(&numberOfFilteredDtc); + if (dtcStatusMask != 0x00) { /** @req DCM008 */ + getNextFilteredDtcResult = Dem_GetNextFilteredDTC(&dtc, &dtcStatus); + /* Fill the answer with all the DTC founded */ + while ((getNextFilteredDtcResult == DEM_FILTERED_OK) && ((numberOfFilteredDtc) >= (nrOfDtcs-1))) { + if (nrOfDtcs < 1024) /* see AXOECUGBA-1104 */ + { + resp->buffer_dades[(nrOfDtcs*4)+1] = DTC_HIGH_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+2] = DTC_MID_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+3] = DTC_LOW_BYTE(dtc); /* polyspace MISRA-C:10.1 [Justified:Low] "This macro only yields 8 bits." */ + resp->buffer_dades[(nrOfDtcs*4)+4] = dtcStatus; + } /* else: we would be accessing outside resp->buffer_dades */ + nrOfDtcs++; + + getNextFilteredDtcResult = Dem_GetNextFilteredDTC(&dtc, &dtcStatus); + } + + if (getNextFilteredDtcResult != DEM_FILTERED_NO_MATCHING_DTC) { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + } + resp->subservice = 0x0A; + resp->buffer_dades[0] = 0xFF/*nrOfDtcs*/; /* polyspace MISRA-C:10.1 [Justified:Low] "It is expected that nrOfDtcs will have a small enough value." */ + Iso15765_3IncrementResponseSize((nrOfDtcs*4)+2); + } + else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + }else{ + response_mode = UDS_ERR_INVALID_FORMAT; + } + break; + } + /* Not supported subfunction */ + default: + { + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + break; + } + + } /* UDS service switch case end */ + + + /* Initates response sending with approppriate size */ + Iso15765_3SendResponse(response_mode); +} +#endif +/* for hardware reset to store DTC data */ +/* +void write_nvm_all_callback(uint8 ServiceId, NvM_RequestResultType JobResult) +{ + if ((reset_flag == UDS_HARD_RESET)||(reset_flag == UDS_KEY_ON_OFF_RESET)){ + DisableWdgTrigger(); + reset_flag = 0; + } + if (clear_dtc_flag == TRUE){ + clear_dtc_flag = FALSE; + Iso15765_3SendResponse(ISO15765_3_POSITIVE_RESPONSE); + } +} +*/ +void UdsClearDtc(UI_8 groupOfDTCHighByte, UI_8 groupOfDTCMiddleByte, UI_8 groupOfDTCLowByte){ + Dem_ReturnClearDTCType result; + //tp_uds_control_routine resp; + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + // memset(&Gateway_DEM_Data,0,sizeof(Gateway_DEM_Type)); + + // resp = ISO15765_3_GET_RESP_DATA(tp_uds_control_routine); + result = Dem_ClearDTC(BYTES_TO_DTC(groupOfDTCHighByte, groupOfDTCMiddleByte, groupOfDTCLowByte), + DEM_DTC_FORMAT_UDS, DEM_DTC_ORIGIN_PRIMARY_MEMORY); /** @req DCM005 */ + + switch (result) { + case DEM_CLEAR_OK: + /* Create positive response *//* @req DCM705 */ + //NvM_WriteAll(); + clear_dtc_flag = TRUE; + response_mode = UDS_ERR_RESPONSE_PENDING; + break; + case DEM_CLEAR_FAILED: + response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; /* @req DCM707 */ + break; + case DEM_CLEAR_WRONG_DTC: + default: + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; /* @req DCM708 *//* !req DCM706 */ + break; + } + Iso15765_3SendResponse(response_mode); +} + +#if 0 +static const UI_8 seed_gen_tbl[16] = { + 0xA9, 0x85, 0xD6, 0xD3, 0x54, 0x1D, 0xAC, 0x25, + 0x5D, 0x43, 0x18, 0x1E, 0x51, 0xFC, 0xCA, 0x63 +}; + +UI_8 UdsSecurityGetSeed(UI_8 seed_type, UI_8 * seed) +{ + UI_8 i = 0; + UI_8 seed_rand = 0; + static UI_8 dummy[SECURITY_SEED_SIZE] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + UI_8 response = ISO15765_3_POSITIVE_RESPONSE; + + if (0x03 == seed_type) { + tp_uds_security_access_seed_resp resp; + if(UdsSecurityTaskQueryIfConsecutiveRequestSeed() == FALSE) + { + seed_rand = UdsSecurityTaskSeedGeneric(); + for(i = 0;i < sizeof(dummy);i++) + { + dummy[i] = seed_gen_tbl[i] ^ seed_rand; + } + } + memcpy(seed, dummy, sizeof(dummy)); + resp = ISO15765_3_GET_RESP_DATA(tp_uds_security_access_seed_resp); + resp->access_mode = 0x03; + Iso15765_3IncrementResponseSize(1); + for(i = 0;i < sizeof(dummy);i++) + { + resp->seed[i] = seed[i]; + Iso15765_3IncrementResponseSize(1); + } + + } else { + response = UDS_ERR_SUBFUNCTION_NOT_SUPORTED_IN_ACTIVE_SESSION; + } + + return (response); +} + +void UdsSecurityNvmCallback(UI_8 *counter) +{ + if(*counter < MAX_SECURITY_ATTEMPTS) + { + security_faa_flag = 0; + }else{ + security_faa_flag = 1; + } +} + +static void manufactoryModeInit(void) +{ +// manufactory_mode = GetNvmManufactoryMode(); +// +// if(manufactory_mode >= 0x10) +// { +// UdsSecurityTaskForceLockState(UDS_ECU_UNLOCKED_LEVEL1); +// }else{ +// UdsSecurityTaskForceLockState(UDS_ECU_LOCKED); +// } +} + +UI_8 UdsSecurityLoadNvmCallback(void) +{ + UI_8 counter = 0; + + manufactoryModeInit(); + + security_faa_flag = GetNvmFaa(); + + if(security_faa_flag == 1) + { + counter = MAX_SECURITY_ATTEMPTS; + } + + return counter; +} + +BOOL UdsSecurityCheckKey(UI_8 key_type, UI_8 * seed, UI_8 * key, UI_8 * response_mode) +{ + BOOL ret = FALSE; + UI_8 cal_key[SECURITY_KEY_SIZE] = {0}; + UI_8 i; + + /* calculate the key */ + AES_cbc_encrypt_process(seed, cal_key, SECURITY_KEY_SIZE, TRUE); + /* Compare received key */ + for (i = 0; i < SECURITY_KEY_SIZE; i++) + { + if (key[i] != cal_key[i]){ + break; + } + } + + if (key_type== 0x04){ + if (i == SECURITY_KEY_SIZE){ + tp_uds_security_access_key_resp resp; + resp = ISO15765_3_GET_RESP_DATA(tp_uds_security_access_key_resp); + resp->access_mode = 0x04; + Iso15765_3IncrementResponseSize(1); + *response_mode = ISO15765_3_POSITIVE_RESPONSE; + ret = TRUE; + }else{ + *response_mode = UDS_ERR_INVALID_KEY; + } + + }else{ + *response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + + return ret; +} + +void UdsReadMemoryByAddress(UI_8 mem_size_len, UI_8 mem_addr_len, UI_8 *mem_addr, UI_8 *mem_size) +{ + UI_32 memoryAddress = 0; + UI_32 length = 0; + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + if ((mem_size_len == (UI_8)2) && (mem_addr_len == (UI_8)4)) { + /* Parse address */ + for (UI_8 i = 0; i < mem_addr_len; i++){ + memoryAddress <<= 8; + memoryAddress += (UI_32)mem_addr[i]; + } + /* Parse size */ + for (UI_8 i = 0; i < mem_size_len; i++){ + length <<= 8; + length += (UI_32)mem_size[i]; + } + /* Need to implement the process + * Check address and data length + * Read memory data */ + response_mode = UDS_ERR_WRONG_BLOCK_SEQUENCE; + } else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + Iso15765_3SendResponse(response_mode); +} + +void UdsWriteMemoryByAddr(UI_8 addr_data_size, UI_8 *data_buffer, UI_16 size) +{ + UI_32 memoryAddress = 0; + UI_32 length = 0; + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + UI_8 mem_addr_len = addr_data_size & (UI_8) 0x0F; + UI_8 mem_size_len = addr_data_size >> (UI_8) 0x04; + UI_8 * data; + UI_16 data_size = 0; + + if ((mem_size_len == (UI_8)2) && (mem_addr_len == (UI_8)4)) { + /* Parse address */ + for (UI_8 i = 0; i < mem_addr_len; i++){ + memoryAddress <<= 8; + memoryAddress += (UI_32)data_buffer[i]; + } + /* Parse size */ + for (UI_8 i = mem_addr_len; i < (mem_size_len + mem_addr_len); i++){ + length <<= 8; + length += (UI_32)data_buffer[i]; + } + data = &data_buffer[mem_size_len + mem_addr_len]; + data_size = size - (mem_size_len + mem_addr_len); + /* Need to implement the process + * Check address and data length + * Write memory data */ + response_mode = UDS_ERR_WRONG_BLOCK_SEQUENCE; + } else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + Iso15765_3SendResponse(response_mode); + +} +static UI_8 EnableCommunicationControl(UI_8 comtype) +{ + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + switch(comtype) + { + case 1:/* enable the normal communication TX*/ + EnableTxFrm_shiftselectposition(); // EnableTxFrm_gsm_1(); + + /* Enable Rx */ + CAN_RX_CONFIG_ENABLE(); + break; + case 2:/* enable the network communication TX */ +// EnableTxFrm_gsm_nm(); + + /* Enable Rx */ + CAN_RX_CONFIG_ENABLE(); + break; + case 3:/* enable all communication TX */ + EnableTxFrm_shiftselectposition();//EnableTxFrm_gsm_1(); +// EnableTxFrm_gsm_nm(); + + /* Enable Rx */ + CAN_RX_CONFIG_ENABLE(); + break; + default: + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + break; + } + + return response_mode; +} + +static UI_8 DisableCommunicationControl(UI_8 comtype) +{ + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + switch(comtype) + { + case 1:/* disable normal communication TX*/ + DisableTxFrm_shiftselectposition();//DisableTxFrm_gsm_1(); + + /* Disable RX */ + CAN_RX_CONFIG_DISABLE(); + break; + case 2:/* disable network communication TX*/ +// DisableTxFrm_gsm_nm(); + + /* Disable RX */ + CAN_RX_CONFIG_DISABLE(); + break; + case 3:/* disable normal and network communication TX */ + DisableTxFrm_shiftselectposition(); // DisableTxFrm_gsm_1(); +// DisableTxFrm_gsm_nm(); + + /* Disable RX */ + CAN_RX_CONFIG_DISABLE(); + break; + default: + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + break; + } + + return response_mode; +} + +//<< +static UI_8 EnaRxDisTxCommunicationControl(UI_8 comtype) +{ + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + + switch(comtype) + { + case 1:/* disable normal communication TX*/ + DisableTxFrm_shiftselectposition();//DisableTxFrm_gsm_1(); + + /* Enable RX */ + CAN_RX_CONFIG_ENABLE(); + break; + case 2:/* disable network communication TX*/ +// DisableTxFrm_gsm_nm(); + + /* Enable RX */ + CAN_RX_CONFIG_ENABLE(); + break; + case 3:/* disable normal and network communication TX */ + DisableTxFrm_shiftselectposition(); // DisableTxFrm_gsm_1(); +// DisableTxFrm_gsm_nm(); + + /* Enable RX */ + CAN_RX_CONFIG_ENABLE(); + break; + default: + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + break; + } + + return response_mode; +} +//>> + +void UdsCommunicationControl(UI_8 subfunction, UI_8 comtype) +{ + UI_8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + tp_uds_communication_control_resp resp; + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_communication_control_resp); + resp->ctrl_type = subfunction; + Iso15765_3IncrementResponseSize(1); + + switch(subfunction) + { + case 0: + response_mode = EnableCommunicationControl(comtype); + break; + case 1: + response_mode = EnaRxDisTxCommunicationControl(comtype); + break; + case 3: + response_mode = DisableCommunicationControl(comtype); + break; + default: + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + break; + } + Iso15765_3SendResponse(response_mode); +} +#endif + +/* Cyclic task. It forwards the signals from Safety partition (SafetyGateway) to QM partition */ +void QMGatewayDEMTask(void){ + static uint8 testing = 0; + //Dem_ReportErrorStatus(DemConf_DemEventParameter_F00617_HIGH_VOLTAGE,Gateway_DEM_Data.event_status_DEM_BAT_HIGH); + //Dem_ReportErrorStatus(DemConf_DemEventParameter_F00616_LOW_VOLTAGE,Gateway_DEM_Data.event_status_DEM_BAT_LOW); + + //Dem_ReportErrorStatus(DemConf_DemEventParameter_C07300_BUS_OFF,Gateway_DEM_Data.event_status_DEM_BUS_OFF); + + //Dem_ReportErrorStatus(DemConf_DemEventParameter_A06600_TouErr,Gateway_DEM_Data.event_status_DEM_Melexis_DIE1_Fault); + //Dem_ReportErrorStatus(DemConf_DemEventParameter_A06700_PressErr,Gateway_DEM_Data.event_status_DEM_Melexis_DIE2_Fault); + //Dem_ReportErrorStatus(DemConf_DemEventParameter_A06800_MorErr,Gateway_DEM_Data.event_status_DEM_Melexis_Heavy_Fault); + //Dem_ReportErrorStatus(DemConf_DemEventParameter_F00617_HIGH_VOLTAGE,FALSE); + if(testing == 0) + { + Dem_ReportErrorStatus(DemConf_DemEventParameter_F00616_LOW_VOLTAGE,TRUE); + Dem_ReportErrorStatus(DemConf_DemEventParameter_F00617_HIGH_VOLTAGE,TRUE); + testing = 1; + } +} + + + diff --git a/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.h b/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.h new file mode 100644 index 0000000..8afe2ab --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_CoreServices_CB.h @@ -0,0 +1,585 @@ + +#ifndef __UDSSERVERCALLBACKS_GM_H +#define __UDSSERVERCALLBACKS_GM_H + +/* ------------------------------ Includes --------------------------------- */ +//#include "Global.h" +//#include "ISO15765_3_CFG.h" + +//<> +/* --------------------------- Type Definitions ---------------------------- */ + +/* ------------------------------- Defines --------------------------------- */ +#define START_DOWNLOAD_VALUE (0xABC1) /* Memory value to indicate to the bootloader that a reprogramming session is requested */ + +/************************* DATA IDENTIFIERS ***********************************/ + +/*** SUPPORTED DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES ***/ + +/* FICOSA DIDs */ +/* DIAGNOSTICS ACTIVE */ + +#define DID_DIAGNOSTICS_ACTIVE ((UI_16)0x08) //ACT: 0x7CA, 0x03, 0x2F, 0x08, 0x01, 0x50, 0x50, 0x50, 0x50 + //FREE: 0x7CA, 0x03, 0x2F, 0x08, 0xFF, 0x50, 0x50, 0x50, 0x50 +/* CAN IDS MANAGEMENT */ +#define DID_CAN_IDS_MANAGEMENT_SEED ((UI_16)0x001) // 0x7CA, 0x04, 0x2E, 0x00, 0x01, 0xSD, 0x50, 0x50, 0x50 + +/* SYSTEM SHUTDOWN NOTIF */ +#define DID_SYSTEM_SHUTDOWN_NOTIF ((UI_16)0x002) // 0x7CA, 0x04, 0x2E, 0x00, 0x02, 0xSS, 0x50, 0x50, 0x50 + +/* LENGTH OF DATA IDENTIFIERS FOR READDATABYID AND WRITEDATABYID SERVICES */ + +/*** SUPPORTED LOCAL IDENTIFIERS FOR INPUTOUTPUTCONTROLBYLOCALID SERVICE ***/ + +/* FICOSA DIDs */ + +/* MOTOR DRIVING DRIVING AND MONITORING */ + +#define DID_MOTOR_DRIVING ((UI_16)0x01) + +#define IO_CTL_LED_STATUS ((UI_16)0xFA00) + +#define IO_CTL_ACT_MOV_SUB_RETURN_CONTOL ((UI_8)0x00) +#define IO_CTL_ACT_MOV_SUB_RESET ((UI_8)0x01) +#define IO_CTL_ACT_MOV_SUB_FREEZE ((UI_8)0x02) +#define IO_CTL_ACT_MOV_SUB_CONTROL ((UI_8)0x03) + +/*** SUPPORTED LOCAL IDENTIFIERS FOR ROUTINE CONTROL SERVICE ***/ + +/* FICOSA DIDs */ +#define ROUTINE_CTL_N_CAL_DEMO ((UI_16)0xF1C1) +#define ROUTINE_CTL_CALIBRATION_MODE ((UI_16)0xF1C0) +#define ROUTINE_CTL_UNCALIBRATION_MODE ((UI_16)0x1800) +#define ROUTINE_CTL_PROGRAM_PRECONDITION ((UI_16)0x0203) + +#define ROUTINE_CTL_CALI_IDLE_START ((UI_16)0x0100) +#define ROUTINE_CTL_CALI_F1_START ((UI_16)0x0101) +#define ROUTINE_CTL_CALI_F2_START ((UI_16)0x0102) +#define ROUTINE_CTL_CALI_B1_START ((UI_16)0x0103) +#define ROUTINE_CTL_CALI_B2_START ((UI_16)0x0104) + +/* Definitions needed for the Read/WriteMemoryByAddress UDS services */ +#define FIXED_ADDR_LEN ((UI_8)4) +#define MAX_ADDR_SIZE ((UI_8)4) +#define MAX_SIZE_LEN ((UI_8)0xFF) +#define DIAG_TX_RX_BUF_LEN ((UI_8)0xFF) +#define MAX_DATA_SIZE ((UI_8)4) + +/** New DID's **/ +/* Logistic data */ +#define DID_FICOSA_HW_ID ((UI_16)0xF192) +#define DID_FICOSA_SW_ID ((UI_16)0xF194) +#define DID_CD_SYSID_DIAGNOSTIC_SPEC ((UI_16)0xF10D) +#define DID_CD_SYSID_ECU_HW_VER_NUMBER ((UI_16)0xF193) +#define DID_CD_SYSID_ECU_SW_VER_NUMBER ((UI_16)0xF195) +#define DID_CD_SYSID_BOOT_ID ((UI_16)0xF180) +#define DID_CD_SYSID_APP_SW_ID ((UI_16)0xF181) +#define DID_CD_SYSID_APP_SW_FINGERPRINT ((UI_16)0xF184) +#define DID_CD_SYSID_ACTIVE_DIAG_SESSION ((UI_16)0xF186) +#define DID_CD_SYSID_SPARE_PART_NUMBER ((UI_16)0xF187) +#define DID_CD_SYSID_ECU_SW_VERSION ((UI_16)0xF189) +#define DID_CD_SYSID_SYSTEMSUPPLIER_ID ((UI_16)0xF18A) +#define DID_CD_SYSID_KIT_ASSEMLY_PART_NUMBER ((UI_16)0xF18E) +#define DID_CD_SYSID_REPAIR_SHOP_CODE ((UI_16)0xF198) +#define DID_CD_SYSID_UDS_PROTOCOL_VERSION ((UI_16)0xF100) +#define DID_CD_SYSID_REPROGRAMING_DATE ((UI_16)0xF199) +#define DID_CD_SYSID_BOOT_VERSION ((UI_16)0xF101) +#define DID_CD_SYSID_DIAGNOSTIC_TABLE_VERSION ((UI_16)0xF10B) +#define DID_CD_SYSID_ECU_NAME ((UI_16)0xF197) +#define DID_CD_SYSID_CALIBRATION_SW_VERSION ((UI_16)0xF1B2) +#define DID_CD_SYSID_SHARED_KEY ((UI_16)0xF16A) + + +#define DID_CD_SYSID_INDEXSRVDATA ((UI_16)0xF011) +#define DID_CD_SYSID_OPERATIONALREF ((UI_16)0xF012) + +#define DID_CD_SYSID_ECU_MANUFAC_DATE ((UI_16)0xF18B) +#define DID_CD_SYSID_ECUSNDATAID ((UI_16)0xF18C) +#define DID_CD_SYSID_VIN ((UI_16)0xF190) +#define DID_CD_SYSID_CALIBRATION_DATA ((UI_16)0xF19B) +#define DID_CD_SYSID_BOOT_VERSION ((UI_16)0xF101) +#define DID_CD_SYSID_MANUF_ECUHWNUM ((UI_16)0xF191) +#define DID_CD_SYSID_ECU_INSTALL_DATE ((UI_16)0xF19D) +#define DID_CD_SYSID_VEH_POWERMODE ((UI_16)0xFD08) + +#define DID_FUN1 ((UI_16)0x9020) +#define DID_FUN2 ((UI_16)0x9021) +#define DID_FUN3 ((UI_16)0x9022) +#define DID_UP ((UI_16)0x9023) +#define DID_DOWN ((UI_16)0x9024) +#define DID_LEFT ((UI_16)0x9025) +#define DID_RIGHT ((UI_16)0x9026) +#define DID_OK ((UI_16)0x9027) +#define DID_Trigger_Vibration ((UI_16)0x9001) +#define DID_DAC_Ref_Voltage ((UI_16)0x9002) +#define DID_Vibration_Gain ((UI_16)0x9003) +#define DID_DAC_Timer_Period ((UI_16)0x9004) +#define DID_Measure_Frame_Switch ((UI_16)0xA001) + + +/** Dynamic **/ + +#define DID_READ_MELEXIS_SPI_DATA ((UI_16)0xFD00) +#define DID_READ_BATTERY_ADC ((UI_16)0x1000) +#define DID_READ_INTERNAL_ADC ((UI_16)0xFD01) +#define DID_READ_PADDLE_ADC ((UI_16)0x1001) +#define DID_READ_PARK_SWITCH_ADC ((UI_16)0x1002) +#define DID_READ_ECO_SWITCH_ADC ((UI_16)0x1004) +#define DID_READ_SHIFT_POSITION ((UI_16)0x2100) +#define DID_READ_ACTUATOR_POSITION ((UI_16)0x2103) +#define DID_READ_ILLUMINATION_DUTY ((UI_16)0x2002) +#define DID_READ_TCU_POSITION ((UI_16)0x2102) +#define DID_READ_BCS_SPEED ((UI_16)0x0500) +#define DID_READ_BRAKE_STATE ((UI_16)0x0501) +#define DID_READ_BCM_KEY_STS ((UI_16)0x1202) +#define DID_READ_SHIFT_DISABLE_CONDITION ((UI_16)0x1204) +#define DID_READ_REPROGRAMMING_COUNTER ((UI_16)0x0200) +#define DID_READ_REPROGRAMMING_ATTEMPT_COUNTER ((UI_16)0x0201) +#define DID_READ_SHIFT_LEVER_POS ((UI_16)0x2104) + +#define DID_READ_POW_SUP_VOLTAGE ((UI_16)0xB001) +#define DID_READ_SYS_MEC_POSITION ((UI_16)0xB003) +#define DID_READ_P_BUT_STATUS ((UI_16)0xB004) +#define DID_READ_MLX_DIE1_VAL ((UI_16)0xB005) +#define DID_READ_MLX_DIE2_VAL ((UI_16)0xB006) + + +#define DID_READ_DTC_OCCURENCE_CNT ((UI_16)0xB101) +#define DID_READ_FAULT_DET_CNT ((UI_16)0xB102) +#define DID_READ_UNCOMPLETE_TES_CNT ((UI_16)0xB103) +#define DID_READ_FAULT_OCCUENCE_CNT ((UI_16)0xB104) +#define DID_READ_DTC_AGEING_CNT ((UI_16)0xB105) +#define DID_READ_ALLDTC_EXT_REC ((UI_16)0xB106) + +/** FICOSA **/ +#define DID_FICOSA_CALI_STABLE_POSTION ((UI_16)0xFD02) +#define DID_FICOSA_CALI_F2_POSTION ((UI_16)0xFD06) +#define DID_FICOSA_CALI_B2_POSTION ((UI_16)0xFD05) +#define DID_FICOSA_CALI_F1_POSTION ((UI_16)0xFD03) +#define DID_FICOSA_CALI_B1_POSTION ((UI_16)0xFD04) +#define DID_SHIFT_PADDLE_CONFKGURE ((UI_16)0xFD10) +#define DID_FICOSA_SHIELD_ATP ((UI_16)0x0600) + +#define DID_FICOSA_DRIVE_MODE_CONFIGURE ((UI_16)0x0102) + +#define DID_FICOSA_SHIFT_FAILURE_REASON ((UI_16)0x1204) +#define DID_FICOSA_SHIFT_RESET_REASON ((UI_16)0x1205) +#define DID_FICOSA_MLX_OPERATION_MODE ((UI_16)0xFD07) +/* GAC */ +#define DID_GAC_MANUFACTORY_MODE ((UI_16)0x0110) +#define DID_GAC_DTC_SETTING_CONTROL_STATE ((UI_16)0x0120) +#define DID_GAC_TRANSPORTATION_MODE ((UI_16)0x0140) + +#define IO_CTL_LED_STATUS_MS_MASK ((UI_16)0x08) +#define IO_CTL_LED_STATUS_D_MASK ((UI_16)0x10) +#define IO_CTL_LED_STATUS_N_MASK ((UI_16)0x20) +#define IO_CTL_LED_STATUS_R_MASK ((UI_16)0x40) +#define IO_CTL_LED_STATUS_P_MASK ((UI_16)0x80) + +#define IO_STS_LED_STATUS_D_MASK ((UI_16)0x10) +#define IO_STS_LED_STATUS_N_MASK ((UI_16)0x20) +#define IO_STS_LED_STATUS_R_MASK ((UI_16)0x40) +#define IO_STS_LED_STATUS_P_MASK ((UI_16)0x80) + +/*Applicaiton*/ +#define DID_TOUCH_SEN1_BASE_LINE ((UI_16)0x7000) +#define DID_TOUCH_SEN2_BASE_LINE ((UI_16)0x7001) +#define DID_TOUCH_SEN3_BASE_LINE ((UI_16)0x7002) +#define DID_TOUCH_SEN4_BASE_LINE ((UI_16)0x7003) +#define DID_TOUCH_SEN5_BASE_LINE ((UI_16)0x7004) +#define DID_TOUCH_SEN6_BASE_LINE ((UI_16)0x7005) +#define DID_TOUCH_SEN7_BASE_LINE ((UI_16)0x7006) +#define DID_TOUCH_SEN8_BASE_LINE ((UI_16)0x7007) +#define DID_TOUCH_SEN9_BASE_LINE ((UI_16)0x7008) +#define DID_TOUCH_SEN10_BASE_LINE ((UI_16)0x7009) +#define DID_TOUCH_SEN11_BASE_LINE ((UI_16)0x700A) +#define DID_TOUCH_SEN12_BASE_LINE ((UI_16)0x700B) +#define DID_TOUCH_SEN13_BASE_LINE ((UI_16)0x700C) +#define DID_TOUCH_SEN14_BASE_LINE ((UI_16)0x700D) +#define DID_TOUCH_SEN15_BASE_LINE ((UI_16)0x700E) + +#define DID_TOUCH_SEN1_SIGNAL ((UI_16)0x7010) +#define DID_TOUCH_SEN2_SIGNAL ((UI_16)0x7011) +#define DID_TOUCH_SEN3_SIGNAL ((UI_16)0x7012) +#define DID_TOUCH_SEN4_SIGNAL ((UI_16)0x7013) +#define DID_TOUCH_SEN5_SIGNAL ((UI_16)0x7014) +#define DID_TOUCH_SEN6_SIGNAL ((UI_16)0x7015) +#define DID_TOUCH_SEN7_SIGNAL ((UI_16)0x7016) +#define DID_TOUCH_SEN8_SIGNAL ((UI_16)0x7017) +#define DID_TOUCH_SEN9_SIGNAL ((UI_16)0x7018) +#define DID_TOUCH_SEN10_SIGNAL ((UI_16)0x7019) +#define DID_TOUCH_SEN11_SIGNAL ((UI_16)0x701A) +#define DID_TOUCH_SEN12_SIGNAL ((UI_16)0x701B) +#define DID_TOUCH_SEN13_SIGNAL ((UI_16)0x701C) +#define DID_TOUCH_SEN14_SIGNAL ((UI_16)0x701D) +#define DID_TOUCH_SEN15_SIGNAL ((UI_16)0x701E) + +#define DID_PRESEE_SEN_BASELINE ((UI_16)0x7020) +#define DID_PRESEE_SEN_SIGNAL ((UI_16)0x7021) +#define DID_PRESEE_SEN_PRE_VAL ((UI_16)0x7022) + +/*--------------------------- Global variables ---------------------------- */ +//#pragma push + +//#pragma section data_type ".sect_shr_var_ram" ".sect_shr_var_ram" + +/* Variable to enable directly a download session after a SW reset. This variable */ +/* will be set by the application before reset only in the case that a reprog */ +/* session is requested. */ +/* This variable is declared here in main to make it clear for everybody that it */ +/* is shared between bootloader and application. */ +//extern UI_16 start_download; +// +///* Bootloader variable that tells if bootloader must respond or not to the session +//change when coming from application (supress positive response) */ +//extern UI_16 start_download_response; +// +///* Variable shared between bootloader and application in which application says to */ +///* bootloader to perform a memory selfcheck because it has detected some problems */ +///* This variable is declared here in main to make it clear for everybody that it */ +///* is shared between bootloader and application */ +//extern UI_16 check_app; +// +///* Bootloader variable that tells if bootloader must give control to the app */ +//extern UI_16 bootloader_active; +// +////#pragma pop + +extern uint8 security_faa_flag; +extern UI_8 manufactory_mode; +extern BOOL uds_control_led; +extern BOOL uds_control_led_lmc; +extern uint8 uds_control_led_conbyte; +extern BOOL uds_control_led_p; +extern BOOL uds_control_led_r; +extern BOOL uds_control_led_n; +extern BOOL uds_control_led_d; +//extern BOOL dtc_setting; +/* ------------------------- Function prototypes --------------------------- */ + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the TcuUdsTesterPresent diagnostic service and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 tp_type : tester present type requested + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsTesterPresent(UI_8 tp_type); + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands all the ReadDataByIdentifier diagnostics and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 id_h : higher byte of the identifier requested + | UI_8 id_l : lower byte of the identifier requested + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +UI_8 UdsReadDataByIdentifier(UI_8 id_h, UI_8 id_l); + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands all the WriteDataByIdentifier diagnostics and is + | responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 id_h : higher byte of the identifier requested + | UI_8 id_l : lower byte of the identifier requested + | UI_8 *data_buffer: data pointer of the received parameters for the write + | UI_16 size: length of the parameters received for the write + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsWriteDataByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 *buf_data_rx, UI_16 size); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the TcuUdsReadMemoryByAddress diagnostic service + | and is responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 mem_size_len: length of the requested size in bytes + | UI_8 mem_addr_len: length of the requested address in bytes + | UI_8 *mem_addr: data pointer to the requested initial memory address to be read + | UI_8 *mem_size: data pointer to the requested memory size to be read + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsReadMemoryByAddress(UI_8 mem_size_len, UI_8 mem_addr_len, + UI_8 *mem_addr, UI_8 *mem_size); + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the TcuUdsWriteMemoryByAddress diagnostic service + | and is responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 addr_data_size: The first four bits cointains the data size length in + | bytes and the last four bits contains the address size + | length in bytes + | UI_8 *data_buffer: Data pointer where to find the requested initial write + | address, the requested write length and the values to write + | in memory + | UI_16 size: ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsWriteMemoryByAddr(UI_8 addr_data_size, UI_8 *data_buffer, UI_16 size); + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the InputOutputControlByLocalId diagnostic + | service and is responsible for giving the final answer to ISO_3 layer + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 *data_buffer: data pointer to the received control data + | UI_8 size: length of the data received to control + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsInputOutputControlByIdentifier(UI_8 id_h, UI_8 id_l, UI_8 io_ctrl_type, UI_8* buf_data_rx, UI_16 size); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * Routine that commands the TcuUdsDiagnosticSessionControl diagnostic + | service and is responsible for giving the final answer to ISO_3 layer. + |--------------------------------------------------------------------------- + | Arguments: + | - session: requested new session + |--------------------------------------------------------------------------- + | Parameters description: + | UI_8 session: requested new session + | result none : .. + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsDiagnosticSessionControl(UI_8 session); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * UdServices diagnostic initialitzation task. This routine should only + | be called one time at the microcontroller initialization + |--------------------------------------------------------------------------- + | Parameters description: + | void: ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsServerCallbacksInit(void); + + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * UdServices diagnostic task executed in every main cycle + |--------------------------------------------------------------------------- + | Parameters description: + | void: ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsServerCallbacksTask(void); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsIniSession(void); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +BOOL UdsCheckResetIsPossible(UI_8 reset_type); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsExecuteResetNow(UI_8 reset_type); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +UI_8 UdsControlRoutineCallback(UI_8 id_high, UI_8 id_low, UI_8* routine_entry_option, UI_16 size); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +//UI_8 UdsSecurityGetSeed(UI_8 seed_type, UI_8 * seed); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +//BOOL UdsSecurityCheckKey(UI_8 key_type, UI_8 * seed, UI_8 * key, UI_8 * response_mode); +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsCommunicationControl(UI_8 subfunction, UI_8 comtype); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +void UdsSecurityNvmCallback(UI_8 *counter); + +/***************************************************************************** + | Portability: DEFC Project + |---------------------------------------------------------------------------- + | Description: + | * + |--------------------------------------------------------------------------- + | Parameters description: + | param : ... + | result none : ... + | Timing: + | Tmax Int Dis: ? cicles cpu | O(n): CTE + | Tmax Int En : ? cicles cpu | O(n): CTE + | Tmax Total : ? cicles cpu | O(n): CTE + /---------------------------------------------------------------------------*/ +UI_8 UdsSecurityLoadNvmCallback(void); + +#define STORAGE_FAA_CALLBACK (StorageFaaFlag) +void StorageFaaFlag(void); +void QMGatewayDEMTask(void); + +#endif diff --git a/firmware/src/DiagnosticR/UDS/UDS_DIDNvm.c b/firmware/src/DiagnosticR/UDS/UDS_DIDNvm.c new file mode 100644 index 0000000..e3baee2 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_DIDNvm.c @@ -0,0 +1,869 @@ + +/* ---------------------------------------------------------------------------- + * Implements + */ +#include "UDS_Services_Common.h" + +/* ---------------------------------------------------------------------------- + * Uses + */ +#include "ModelsInterfaces/CommonMacros.h" +//#include "Platform_Types.h" +#include "DiagnosticR/ProjectCfg.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "UDS_Services_Common.h" +#include "UDS_CoreServices_CB.h" +//#include "ficoNVM.h" +//#include "GearShiftStrategy_If.h" +//#include "DriveModeSwitch_If.h" +//#include "PaddleStatus_If.h" +#include "smartee.h" +/* ---------------------------------------------------------------------------- + * Private defines + */ + +#define DLC_DID_ECU_SN 24U +#define DLC_DID_CD_VIN 17U +#define DLC_DID_CD_MANFAC_SN 16U +#define DLC_DID_CD_APP_DATAID 3U +#define DLC_DID_CD_MANUF_ECUHWNUM 11U +#define DLC_DID_DTC_SETTING 12U +#define DLC_DID_MTOC 17U +#define DLC_DID_SHEILD_AUTOPARK 1U +#define DLC_DID_TRANSPORTATION_MODE 1U +#define DLC_DID_REPROGRAMMING_COUNTER 2U +#define DLC_DID_REPROGRAMMING_DATE 4U +#define DLC_DID_APPSW_FINGER_PRINT 26U +#define DLC_DID_ECUMANUFACTURE_DATE 6U +#define DLC_DID_ECUINSTALLATION_DATE 6U +#define DLC_DID_DCID 3U + +#define DLC_GAC_DIAG_SPEC_VERSION 3U +#define DLC_GAC_HW_VERSION 16U +#define DLC_GAC_ECU_SW_VERSION 16U +#define DLC_GAC_SPARE_NUMBER 14U +#define DLC_SYSTEM_SUPPLIER_ID 6U +#define DLC_GAC_KIT_PART_NUMBER 14U +#define DLC_SYSTEM_NAME 20U +#define DLC_UDS_PROTOL_VERSION 2U +#define DLC_BOOT_SW_VERSION 6U +#define DLC_REPAIR_SHOP_CODE 16U +#define DLC_BOOT_SW_ID 3U + + +/* ---------------------------------------------------------------------------- + * Private types + */ +typedef struct{ + UI_8 gac_diagnostic_version[DLC_GAC_DIAG_SPEC_VERSION]; + UI_8 gac_hardware_version[DLC_GAC_HW_VERSION]; + UI_8 gac_spare_number[DLC_GAC_SPARE_NUMBER]; + UI_8 system_supplier_id[DLC_SYSTEM_SUPPLIER_ID]; + UI_8 gac_kit_assembly_part_number[DLC_GAC_KIT_PART_NUMBER]; + UI_8 system_name[DLC_SYSTEM_NAME]; + UI_8 uds_protol_version[DLC_UDS_PROTOL_VERSION]; + UI_8 boot_version[DLC_BOOT_SW_VERSION]; +}t_logical_did; + +/* ---------------------------------------------------------------------------- + * Private macros + */ + +/* ---------------------------------------------------------------------------- + * Forward declarations + */ + +/* ---------------------------------------------------------------------------- + * Private variables + */ +const UI_8 NVM_DID_CD_VIN[DLC_DID_CD_VIN] = GAC_VIN_DEFAULT_VALUE; +const UI_8 NVM_Reprogramming_Date_App[DLC_DID_REPROGRAMMING_DATE] = {0x20,0x24,0x06,0x24}; +const UI_8 NVM_DID_CD_SUPPLIER_ID[DLC_SYSTEM_SUPPLIER_ID] = {'2','4','0','6','2','4'}; +const UI_8 NVM_Repair_Shop_Code[DLC_REPAIR_SHOP_CODE] = GAC_ECU_REPAIR_SHOP_CODE; +const UI_8 NVM_DID_CD_HW_VERSION[DLC_GAC_HW_VERSION] = {'H','W','0','5',0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20}; +static uint8 RAM_DID_CD_VIN[DLC_DID_CD_VIN]; +static uint8 RAM_DID_CD_REPROGRAMMING_DATE[DLC_DID_REPROGRAMMING_DATE]; +static uint8 RAM_DID_CD_SUPPLIER_ID[DLC_SYSTEM_SUPPLIER_ID]; +static uint8 RAM_DID_REPAIR_SHOP_CODE[DLC_REPAIR_SHOP_CODE]; +static uint8 RAM_DID_CD_HW_VERSION[DLC_GAC_HW_VERSION]; + #if 0 +#pragma ghs startdata +#pragma ghs section rodata=".nvm_sn" +const UI_8 NVM_DID_CD_ECU_SN[DLC_DID_ECU_SN] = GAC_ECU_SN_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_sheild_auto_park" +const UI_8 NVM_DID_CD_SHEILD_AutoPark[DLC_DID_SHEILD_AUTOPARK] = {0x0}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_vin" +const UI_8 NVM_DID_CD_VIN[DLC_DID_CD_VIN] = GAC_VIN_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_manfac_sn" +const UI_8 NVM_DID_CD_MANFAC_SN[DLC_DID_CD_MANFAC_SN] = GAC_MANFAC_SN_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +//<0610 +#pragma ghs startdata +#pragma ghs section rodata=".nvm_boot_id" +const UI_8 NVM_DID_CD_BOOT_ID[DLC_BOOT_SW_ID] = GAC_BOOT_ID_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_ecusw_version" +const UI_8 NVM_DID_CD_ECUSW_VERSION[DLC_GAC_ECU_SW_VERSION] = GAC_ECUSW_VERSION_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + + + +//0610> + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_app_dataid" +const UI_8 NVM_DID_CD_APP_DATAID[DLC_DID_CD_APP_DATAID] = GAC_APP_DATAID_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_vehiclemanuf_ecuhwnum_sn" +const UI_8 NVM_DID_CD_MANUF_ECUHWNUM[DLC_DID_CD_MANUF_ECUHWNUM] = GAC_MANUF_ECUHWNUM_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_dtc_setting" +const UI_8 NVM_DID_CD_DTC_SETTING[DLC_DID_DTC_SETTING] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_transportation_mode" +const UI_8 NVM_DID_CD_TRANSPORTATION_MODEG[DLC_DID_TRANSPORTATION_MODE]= {0x0}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_mtoc" +const UI_8 NVM_DID_CD_MTOC[DLC_DID_MTOC]= GAC_MTOC_DEFAULT_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_faa_flag" +const UI_8 NVM_Faa_Flag = 0x0; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_reprogramming_counter" +const UI_8 NVM_Reprogramming_Counter[DLC_DID_REPROGRAMMING_COUNTER] = {0x0}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_reprogramming_attempt_counter" +const UI_8 NVM_Reprogramming_Attempt_Counter[DLC_DID_REPROGRAMMING_COUNTER] = {0x0}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_reprogramming_date" +const UI_8 NVM_Reprogramming_Date[DLC_DID_REPROGRAMMING_DATE] = {3,1,0,5,2,1}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_reprogramming_date_app" +const UI_8 NVM_Reprogramming_Date_App[DLC_DID_REPROGRAMMING_DATE] = {3,1,0,5,2,1}; +#pragma ghs section data=default +#pragma ghs enddata + + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_ecumanufacture_date" +const UI_8 NVM_Ecumanufacture_Date[DLC_DID_ECUMANUFACTURE_DATE] = {3,1,0,5,2,1}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_ecuinstallation_date" +const UI_8 NVM_Ecuinstallation_Date[DLC_DID_ECUINSTALLATION_DATE] = {3,1,0,5,2,1}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_bootsw_version" +const UI_8 NVM_DID_CD_BOOTSW_VERSION[DLC_BOOT_SW_VERSION] = {'0','A','0','0','0','1'}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_hw_version" +const UI_8 NVM_DID_CD_HW_VERSION[DLC_GAC_HW_VERSION] = {0x41,0x30,0x30,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20}; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_supplier_id" +const UI_8 NVM_DID_CD_SUPPLIER_ID[DLC_SYSTEM_SUPPLIER_ID] = GAC_APP_SUPPLIER_ID; +#pragma ghs section data=default +#pragma ghs enddata + + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_app_finger_print" +const UI_8 NVM_App_SW_Finger_Print[DLC_DID_APPSW_FINGER_PRINT] = GAC_APP_SW_FINGER_INFO; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_app_finger_print_app" +const UI_8 NVM_App_SW_Finger_Print_App[DLC_DID_APPSW_FINGER_PRINT] = GAC_APP_SW_FINGER_INFO; +#pragma ghs section data=default +#pragma ghs enddata + + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_manufactory_mode" +const UI_8 NVM_Manufactory_Mode = 0xFF; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_logical_did" +const t_logical_did nvm_logical_id; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_dcid" +const uint8 nvm_dcid[DLC_DID_DCID] = GAC_DCID_VALUE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_drive_mode" +const UI_8 NVM_Drive_Mode = 0x0; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_paddle_active" +const UI_8 NVM_Paddle_Configure = 0xAA; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_drive_mode_storage" +const UI_8 NVM_Drive_Storage = 0x39; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_repair_shop_code" +const UI_8 NVM_Repair_Shop_Code[DLC_REPAIR_SHOP_CODE] = GAC_ECU_REPAIR_SHOP_CODE; +#pragma ghs section data=default +#pragma ghs enddata + +#pragma ghs startdata +#pragma ghs section rodata=".nvm_last_position" +const UI_8 NVM_Last_Pos_Req = 1; +#pragma ghs section data=default +#pragma ghs enddata + +static uint8 RAM_DID_ECU_SN[DLC_DID_ECU_SN]; +static uint8 RAM_DID_CD_VIN[DLC_DID_CD_VIN]; +static uint8 RAM_DID_CD_MANFAC_SN[DLC_DID_CD_MANFAC_SN]; +static uint8 RAM_DID_CD_APP_DATAID[DLC_DID_CD_APP_DATAID]; +static uint8 RAM_DID_CD_MANUF_ECUHWNUM[DLC_DID_CD_MANUF_ECUHWNUM]; +static uint8 RAM_DID_CD_DTC_SETTING[DLC_DID_DTC_SETTING]; +static uint8 RAM_DID_CD_TRANSPORTATION_MODEG[DLC_DID_TRANSPORTATION_MODE]; +static uint8 RAM_DID_CD_MTOC[DLC_DID_MTOC]; +static uint8 RAM_DID_CD_REPROGRAMMING_COUNTER[DLC_DID_REPROGRAMMING_COUNTER]; +static uint8 RAM_DID_CD_REPROGRAMMING_ATTEMPT_COUNTER[DLC_DID_REPROGRAMMING_COUNTER]; + +static uint8 RAM_DID_CD_ECUMANUFACTURE_DATE[DLC_DID_ECUMANUFACTURE_DATE]; +static uint8 RAM_DID_CD_ECUINSTALLATION_DATE[DLC_DID_ECUINSTALLATION_DATE]; +//<0610 +static uint8 RAM_DID_CD_BOOT_ID[DLC_BOOT_SW_ID]; +static uint8 RAM_DID_CD_ECUSW_VERSION[DLC_GAC_ECU_SW_VERSION]; +static uint8 RAM_DID_CD_BOOTSW_VERSION[DLC_BOOT_SW_VERSION]; + + + +//0610> +static uint8 RAM_DID_CD_APPSW_FINGER_PRINT[DLC_DID_APPSW_FINGER_PRINT]; +static uint8 RAM_DRIVE_MODE; +static uint8 RAM_PADDLE_CONFIGURE; +static uint8 RAM_EOL_CONFIGURE; + +static t_logical_did RAM_LOGICAL_DID; +static uint8 RAM_DCID[DLC_DID_DCID]; + +static uint8 RAM_LAST_POSITION = 0; +static uint8 RAM_ATP = 0; +static uint8 RAM_FAA_FLAG = 0; +static uint8 RAM_Manufactory_Mode = 0; +#endif +/* ---------------------------------------------------------------------------- + * Public variables + */ + +/* ---------------------------------------------------------------------------- + * Public functions + */ +void UDS_DID_initNVM(void) +{ + + memcpy(RAM_DID_CD_VIN, NVM_DID_CD_VIN, DLC_DID_CD_VIN); + memcpy(RAM_DID_CD_REPROGRAMMING_DATE, NVM_Reprogramming_Date_App,DLC_DID_REPROGRAMMING_DATE); + memcpy(RAM_DID_CD_SUPPLIER_ID, NVM_DID_CD_SUPPLIER_ID,DLC_SYSTEM_SUPPLIER_ID); + memcpy(RAM_DID_REPAIR_SHOP_CODE,NVM_Repair_Shop_Code,sizeof(NVM_Repair_Shop_Code)); + memcpy(RAM_DID_CD_HW_VERSION, NVM_DID_CD_HW_VERSION,DLC_GAC_HW_VERSION); +} +//static void onWriteFinished(BOOL ret) +//{ + /* Do Nothing */ +//} +t_UDS_ERR Get_DID_ECU_SN(uint8 *data) +{ + //memcpy(data, RAM_DID_ECU_SN, sizeof(RAM_DID_ECU_SN)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_ECU_SN(uint8 *data) +{ + //memcpy(RAM_DID_ECU_SN, data, sizeof(RAM_DID_ECU_SN)); + //ficoNVM_Write_Serial_Number(RAM_DID_ECU_SN, onWriteFinished); + + return TRUE; +} + +t_UDS_ERR Get_DID_CD_SYSID_VIN(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_VIN, sizeof(RAM_DID_CD_VIN)); + SmartEE_Read(0x500, data, 17); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_CD_VIN(uint8 *data) +{ + //memcpy(RAM_DID_CD_VIN, data, sizeof(RAM_DID_CD_VIN)); + //ficoNVM_Write_VIN(RAM_DID_CD_VIN, onWriteFinished); + SmartEE_Write(0x500, data, 17); + return TRUE; +} + +t_UDS_ERR Get_DID_TouchSen1_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][0],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen2_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][1],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen3_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][2],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen4_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][3],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen5_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][4],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen6_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][5],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen7_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][6],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen8_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][7],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen9_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][8],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen10_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][9],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen11_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][10],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen12_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][11],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen13_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][12],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen14_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][13],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen15_BaseLine(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[0][14],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen1_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][0],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen2_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][1],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen3_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][2],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen4_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][3],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen5_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][4],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen6_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][5],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen7_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][6],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen8_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][7],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen9_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][8],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen10_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][9],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen11_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][10],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen12_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][11],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen13_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][12],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen14_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][13],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_TouchSen15_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[1][14],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_PressSen_Baseline(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[2][0],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_PressSen_Signal(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[2][1],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Pre_Value(uint8 *data) +{ + memcpy(data,&g16_DiagTouchPressSenRes[2][2],2); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Reprogramming_Date(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_REPROGRAMMING_DATE, sizeof(RAM_DID_CD_REPROGRAMMING_DATE)); + SmartEE_Read(0x517, data, 4); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_Reprogramming_Date(uint8 *data) +{ + + //memcpy(RAM_DID_CD_REPROGRAMMING_DATE, data, sizeof(RAM_DID_CD_REPROGRAMMING_DATE)); + //ficoNVM_Write_REPROGRAME_DATE(RAM_DID_CD_REPROGRAMMING_DATE, onWriteFinished); + SmartEE_Write(0x517, data, 4); + return TRUE; +} + + +t_UDS_ERR Set_DID_CD_APP_SW_FINGERPRINT(uint8 *data) +{ + //memcpy(RAM_DID_CD_APPSW_FINGER_PRINT, data, sizeof(RAM_DID_CD_APPSW_FINGER_PRINT)); + //ficoNVM_Write_App_FigrPriApp(RAM_DID_CD_APPSW_FINGER_PRINT, onWriteFinished); + + return TRUE; +} + +t_UDS_ERR Get_DID_CD_SYSID_MANFAC_SN(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_MANFAC_SN, sizeof(RAM_DID_CD_MANFAC_SN)); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_CD_MANFAC_SN(uint8 *data) +{ + //memcpy(RAM_DID_CD_MANFAC_SN, data, sizeof(RAM_DID_CD_MANFAC_SN)); + //ficoNVM_Write_MANFAC_SN(RAM_DID_CD_MANFAC_SN, onWriteFinished); + + return TRUE; +} + +t_UDS_ERR Get_DID_CD_SYSID_APP_DATAID(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_APP_DATAID, sizeof(RAM_DID_CD_APP_DATAID)); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_CD_APP_DATAID(uint8 *data) +{ + //memcpy(RAM_DID_CD_APP_DATAID, data, sizeof(RAM_DID_CD_APP_DATAID)); + //ficoNVM_Write_APP_DATAID(RAM_DID_CD_APP_DATAID, onWriteFinished); + + return TRUE; +} + +t_UDS_ERR Get_DID_CD_SYSID_MANUF_ECUHWNUM(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_MANUF_ECUHWNUM, sizeof(RAM_DID_CD_MANUF_ECUHWNUM)); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_CD_MANUF_ECUHWNUM(uint8 *data) +{ + //memcpy(RAM_DID_CD_MANUF_ECUHWNUM, data, sizeof(RAM_DID_CD_MANUF_ECUHWNUM)); + //ficoNVM_Write_MANUF_ECUHWNUM(RAM_DID_CD_MANUF_ECUHWNUM, onWriteFinished); + + return TRUE; +} + +t_UDS_ERR Get_DID_Dtc_Setting(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_DTC_SETTING, sizeof(RAM_DID_CD_DTC_SETTING)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Set_DID_Dtc_Setting(uint8 *data) +{ + //memcpy(RAM_DID_CD_DTC_SETTING, data, sizeof(RAM_DID_CD_DTC_SETTING)); + //ficoNVM_Write_Dtc_Setting_Flag(RAM_DID_CD_DTC_SETTING, onWriteFinished); + + return TRUE; +} + + +t_UDS_ERR Set_DID_Shield_Atp(uint8 *data) +{ + if(data[0] <= 1) + { +// shield_atp = data[0]; +// ficoNVM_Write_Shield_ATP_Flag(&shield_atp, onWriteFinished); + }else{ + return FALSE; + } + return TRUE; +} + +t_UDS_ERR Set_DID_Repair_Shop_Code(uint8 *data) +{ + //memcpy(RAM_DID_REPAIR_SHOP_CODE,data,sizeof(RAM_DID_REPAIR_SHOP_CODE)); + //ficoNVM_Write_Repair_Shop_Code_Flag(RAM_DID_REPAIR_SHOP_CODE, onWriteFinished); + SmartEE_Write(0x51B, data, 16); + return TRUE; +} + +t_UDS_ERR Get_DID_Reprogramming_Counter(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_REPROGRAMMING_COUNTER, sizeof(RAM_DID_CD_REPROGRAMMING_COUNTER)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Reprogramming_Attempt_Counter(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_REPROGRAMMING_ATTEMPT_COUNTER, sizeof(RAM_DID_CD_REPROGRAMMING_ATTEMPT_COUNTER)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_EcuManufacture_Date(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_ECUMANUFACTURE_DATE, sizeof(RAM_DID_CD_ECUMANUFACTURE_DATE)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_EcuInstallation_Date(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_ECUINSTALLATION_DATE, sizeof(RAM_DID_CD_ECUINSTALLATION_DATE)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_App_Sw_Finger_Print(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_APPSW_FINGER_PRINT, sizeof(RAM_DID_CD_APPSW_FINGER_PRINT)); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Gac_Hw_Version(uint8 *data) +{ + memcpy(data, RAM_DID_CD_HW_VERSION,DLC_GAC_HW_VERSION); + + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Gac_Ecusw_Version(uint8 *data) +{ + UI_8 sw_num[DLC_GAC_ECU_SW_VERSION] = GAC_ECUSW_VERSION_DEFAULT_VALUE; + memcpy(data,sw_num,DLC_GAC_ECU_SW_VERSION); + return ISO15765_3_POSITIVE_RESPONSE; +} + + +t_UDS_ERR Get_DID_Gac_Spare_Number(uint8 *data) +{ + data[0] = 'A'; + data[1] = 'B'; + data[2] = 'C'; + data[3] = 'D'; + data[4] = 'E'; + data[5] = 'F'; + data[6] = '0'; + data[7] = '1'; + data[8] = '2'; + data[9] = '3'; + data[10] = '4'; + data[11] = '5'; + data[12] = '6'; + data[13] = '7'; + data[14] = '8'; + data[15] = '9'; + data[16] = 'A'; + data[17] = 'B'; + data[18] = 'C'; + data[19] = 'D'; + data[20] = 'E'; +// memcpy(data, RAM_LOGICAL_DID.gac_spare_number,DLC_GAC_SPARE_NUMBER); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_System_Supplier_Id(uint8 *data) +{ + memcpy(data, RAM_DID_CD_SUPPLIER_ID,DLC_SYSTEM_SUPPLIER_ID); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Gac_Kit_Part_Number(uint8 *data) +{ + data[0] = 'A'; + data[1] = 'K'; + data[2] = 'C'; + data[3] = 'G'; + data[4] = '-'; + data[5] = '0'; + data[6] = '0'; + data[7] = '7'; + data[8] = 'X'; + data[9] = '-'; + data[10] = 'A'; + data[11] = '1'; + data[12] = ' '; + data[13] = ' '; + // memcpy(data, RAM_LOGICAL_DID.gac_kit_assembly_part_number,DLC_GAC_KIT_PART_NUMBER); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_System_Name(uint8 *data) +{ + //memcpy(data, RAM_LOGICAL_DID.system_name,DLC_SYSTEM_NAME); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Uds_Protol_Version(uint8 *data) +{ + //memcpy(data, RAM_LOGICAL_DID.uds_protol_version,DLC_UDS_PROTOL_VERSION); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Boot_Version(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_BOOTSW_VERSION,DLC_BOOT_SW_VERSION); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_Boot_ID(uint8 *data) +{ + //memcpy(data, RAM_DID_CD_BOOT_ID,sizeof(RAM_DID_CD_BOOT_ID)); + return ISO15765_3_POSITIVE_RESPONSE; +} + + +t_UDS_ERR Get_DID_DCID(uint8 *data) +{ + //memcpy(data, RAM_DCID,DLC_DID_DCID); + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_Shield_Atp(uint8 *data) +{ +// data[0] = shield_atp; + return ISO15765_3_POSITIVE_RESPONSE; +} + +t_UDS_ERR Get_DID_GAC_Repair_Shop_Id(uint8 *data) +{ + //memcpy(data, RAM_DID_REPAIR_SHOP_CODE,DLC_REPAIR_SHOP_CODE); + SmartEE_Read(0x51B, data, 16); + return ISO15765_3_POSITIVE_RESPONSE; +} + + +//t_UDS_ERR Set_DID_CD_Drive_Mode_Configure(uint8 *data) +//{ +// EOL_config = *((st_eol_config *)data); +// paddle_active = EOL_config.paddle_config; +// +// ficoNVM_Write_Drive_Mode_Configure((uint8*)(&EOL_config), onFinishedDriveConfig); +// +// return TRUE; +//} + +//uint8 GetLastPosition(void) +//{ + //return RAM_LAST_POSITION; +//} + +//uint8* GetNvmDtcSetting(void) +//{ + //return RAM_DID_CD_DTC_SETTING; +//} + +/* ---------------------------------------------------------------------------- + * Private functions + */ + diff --git a/firmware/src/DiagnosticR/UDS/UDS_DiDRead_CB.c b/firmware/src/DiagnosticR/UDS/UDS_DiDRead_CB.c new file mode 100644 index 0000000..54a1532 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_DiDRead_CB.c @@ -0,0 +1,204 @@ + +/* ---------------------------------------------------------------------------- + * Implements + */ +#include "UDS_Services_Common.h" + +/* ---------------------------------------------------------------------------- + * Uses + */ +//#include "CommonMacros.h" +//#include "Platform_Types.h" +//#include "ProjectCfg.h" +//#include "Global.h" + + +#include "UDS_CoreServices_CB.h" +#include "DiagnosticR/UDS/UDS_Services_Common.h" +#include +#include "TouchPanel.h" +//#include "TouchPanel_Cfg.h" +#include "Std_Types.h" +#include "device.h" +#include "touch/touch.h" +#include "math.h" +#include "stdlib.h" +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "OsekCom/OsekCom.h" +#include "Speaker/Speaker.h" +#include "P417_SWTR_App_ert_rtw/P417_SWTR_App.h" +#include "TouchPanel/TouchPanel.h" +#include "forceSnsr/forcedetect.h" +#include "TLE9263/TLE926x_Main.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "ModelsInterfaces/CommonMacros.h" +#include "calib_public.h" +#include "smartee.h" +extern UI_8 frm_diag_physresp_swtr[8]; + +t_UDS_ERR Get_DID_Fun1(uint8 *data) +{ + data[0] = Calib_GetData(data0)>>8; + data[1] = Calib_GetData(data0); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_Fun2(uint8 *data) +{ + data[0] = Calib_GetData(data1)>>8; + data[1] = Calib_GetData(data1); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_Fun3(uint8 *data) +{ + data[0] = Calib_GetData(data2)>>8; + data[1] = Calib_GetData(data2); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_UP(uint8 *data) +{ + data[0] = Calib_GetData(data3)>>8; + data[1] = Calib_GetData(data3); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_DOWN(uint8 *data) +{ + data[0] = Calib_GetData(data4)>>8; + data[1] = Calib_GetData(data4); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_LEFT(uint8 *data) +{ + data[0] = Calib_GetData(data5)>>8; + data[1] = Calib_GetData(data5); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_RIGHT(uint8 *data) +{ + data[0] = Calib_GetData(data6)>>8; + data[1] = Calib_GetData(data6); + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_OK(uint8 *data) +{ + data[0] = Calib_GetData(data7)>>8; + data[1] = Calib_GetData(data7); + return ISO15765_3_POSITIVE_RESPONSE; +} + +extern uint8 UDS_DAC_Ref_Voltage; +t_UDS_ERR Get_DID_DAC_Ref_Voltage(uint8 *data) +{ + *data = UDS_DAC_Ref_Voltage; + return ISO15765_3_POSITIVE_RESPONSE; +} + +extern uint8 UDS_Vibration_Gain; +t_UDS_ERR Get_DID_Vibration_Gain(uint8 *data) +{ + *data = UDS_Vibration_Gain; + return ISO15765_3_POSITIVE_RESPONSE; +} +t_UDS_ERR Get_DID_Measure_Frame_Switch(uint8 *data) +{ + // uint8_t temp=0; + + SmartEE_Read(0x783, data, 1); + //*data=*temp; + return ISO15765_3_POSITIVE_RESPONSE; +} + +/* ---------------------------------------------------------------------------- + * Private macros + */ +/********************* MACRO for support DID read *****************************/ +#define SUPPORT_ID_FOR_22_SERVICE ((uint8)0xDF) +#define SUPPORT_ID_FOR_2E_SERVICE ((uint8)0xEC) +#define SUPPORT_ID_FOR_2F_SERVICE ((uint8)0xED) +#define SUPPORT_ID_FOR_31_SERVICE ((uint8)0xEE) + +#define BAT_MODE_A ((uint8)0) +#define BAT_MODE_B ((uint8)1) +#define BAT_MODE_C ((uint8)2) + +/* ---------------------------------------------------------------------------- + * Forward declarations + */ + UI_16 g16_DiagTouchPressSenRes[3][15] = {0}; + +static t_UDS_ERR Get_DID_GAC_Active_Diagnostic_session(uint8 *data); + +t_UDSReadDidSubCommands uds_did_read_commands[] = +{ + /** ECU Identification ***********************************************************************************/ + { DID_CD_SYSID_ACTIVE_DIAG_SESSION, 1, UDS_DEFAULT_SESSION, Get_DID_GAC_Active_Diagnostic_session }, + { DID_CD_SYSID_VIN, 17, UDS_DEFAULT_SESSION, Get_DID_CD_SYSID_VIN }, + { DID_CD_SYSID_REPROGRAMING_DATE , 4, UDS_DEFAULT_SESSION, Get_DID_Reprogramming_Date }, + { DID_CD_SYSID_SYSTEMSUPPLIER_ID, 6 , UDS_DEFAULT_SESSION, Get_DID_System_Supplier_Id }, + { DID_CD_SYSID_SPARE_PART_NUMBER, 21, UDS_DEFAULT_SESSION, Get_DID_Gac_Spare_Number }, + { DID_CD_SYSID_REPAIR_SHOP_CODE, 16, UDS_DEFAULT_SESSION, Get_DID_GAC_Repair_Shop_Id }, + { DID_CD_SYSID_ECU_HW_VER_NUMBER, 16, UDS_DEFAULT_SESSION, Get_DID_Gac_Hw_Version }, + { DID_CD_SYSID_ECU_SW_VER_NUMBER , 16, UDS_DEFAULT_SESSION, Get_DID_Gac_Ecusw_Version }, + /*Application*/ + { DID_TOUCH_SEN1_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen1_BaseLine }, + { DID_TOUCH_SEN2_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen2_BaseLine }, + { DID_TOUCH_SEN3_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen3_BaseLine }, + { DID_TOUCH_SEN4_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen4_BaseLine }, + { DID_TOUCH_SEN5_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen5_BaseLine }, + { DID_TOUCH_SEN6_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen6_BaseLine }, + { DID_TOUCH_SEN7_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen7_BaseLine }, + { DID_TOUCH_SEN8_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen8_BaseLine }, + { DID_TOUCH_SEN9_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen9_BaseLine }, + { DID_TOUCH_SEN10_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen10_BaseLine }, + { DID_TOUCH_SEN11_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen11_BaseLine }, + { DID_TOUCH_SEN12_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen12_BaseLine }, + { DID_TOUCH_SEN13_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen13_BaseLine }, + { DID_TOUCH_SEN14_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen14_BaseLine }, + { DID_TOUCH_SEN15_BASE_LINE , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen15_BaseLine }, + + { DID_TOUCH_SEN1_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen1_Signal }, + { DID_TOUCH_SEN2_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen2_Signal }, + { DID_TOUCH_SEN3_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen3_Signal }, + { DID_TOUCH_SEN4_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen4_Signal }, + { DID_TOUCH_SEN5_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen5_Signal }, + { DID_TOUCH_SEN6_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen6_Signal }, + { DID_TOUCH_SEN7_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen7_Signal }, + { DID_TOUCH_SEN8_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen8_Signal }, + { DID_TOUCH_SEN9_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen9_Signal }, + { DID_TOUCH_SEN10_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen10_Signal }, + { DID_TOUCH_SEN11_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen11_Signal }, + { DID_TOUCH_SEN12_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen12_Signal }, + { DID_TOUCH_SEN13_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen13_Signal }, + { DID_TOUCH_SEN14_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen14_Signal }, + { DID_TOUCH_SEN15_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_TouchSen15_Signal }, + + { DID_PRESEE_SEN_BASELINE , 2, UDS_DEFAULT_SESSION, Get_DID_PressSen_Baseline }, + { DID_PRESEE_SEN_SIGNAL , 2, UDS_DEFAULT_SESSION, Get_DID_PressSen_Signal }, + { DID_PRESEE_SEN_PRE_VAL , 2, UDS_DEFAULT_SESSION, Get_DID_Pre_Value }, + + {DID_FUN1, 2, UDS_DEFAULT_SESSION, Get_DID_Fun1}, + {DID_FUN2, 2, UDS_DEFAULT_SESSION, Get_DID_Fun2}, + {DID_FUN3, 2, UDS_DEFAULT_SESSION, Get_DID_Fun3}, + {DID_UP, 2, UDS_DEFAULT_SESSION, Get_DID_UP}, + {DID_DOWN, 2, UDS_DEFAULT_SESSION, Get_DID_DOWN}, + {DID_LEFT, 2, UDS_DEFAULT_SESSION, Get_DID_LEFT}, + {DID_RIGHT, 2, UDS_DEFAULT_SESSION, Get_DID_RIGHT}, + {DID_OK, 2, UDS_DEFAULT_SESSION, Get_DID_OK}, + {DID_DAC_Ref_Voltage, 1, UDS_DEFAULT_SESSION, Get_DID_DAC_Ref_Voltage}, + {DID_Vibration_Gain, 1, UDS_DEFAULT_SESSION, Get_DID_Vibration_Gain}, + {DID_Measure_Frame_Switch, 1, UDS_DEFAULT_SESSION, Get_DID_Measure_Frame_Switch}, +}; + + +static t_UDS_ERR Get_DID_GAC_Active_Diagnostic_session(uint8 *data) +{ + data[0] = Iso15765_3QueryActiveSession(); + return ISO15765_3_POSITIVE_RESPONSE; +} + +uint8 GetReadDidServiceNumber(void) +{ + return NOOF(uds_did_read_commands); +} diff --git a/firmware/src/DiagnosticR/UDS/UDS_DiDWrite_CB.c b/firmware/src/DiagnosticR/UDS/UDS_DiDWrite_CB.c new file mode 100644 index 0000000..db449aa --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_DiDWrite_CB.c @@ -0,0 +1,323 @@ +/* ---------------------------------------------------------------------------- + * Implements + */ +//#include "UDS_Services_Common.h" + +/* ---------------------------------------------------------------------------- + * Uses + */ +#include "ModelsInterfaces/CommonMacros.h" +#include "DiagnosticR/ProjectCfg.h" +#include "Std_Types.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "UDS_CoreServices_CB.h" +//#include "SafetyHwAbsDIO.h" +//#include "PaddleStatus_If.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3_Task.h" +#include "DiagnosticR/UDS/UDS_Services_Common.h" +#include "calib_public.h" +#include "smartee.h" +#include "Speaker.h" +/* ---------------------------------------------------------------------------- + * Private defines + */ +#define NO_MESSAGE 0xFFFF + +/* ---------------------------------------------------------------------------- + * Private types + */ +//typedef struct { +// uint16 did; +// uint8 size; +// t_UDS_Session allowed_session; +// // t_UDS_ERR (*Setter)(const uint8 * buf_data_rx); +// t_UDS_ERR (*Setter)(uint8 * buf_data_rx); +// +//} t_UDSWriteDiDSubCommandsReference; + +/* ---------------------------------------------------------------------------- + * Private macros + */ +uint8* p_dtc_setting = NULL; +/* ---------------------------------------------------------------------------- + * Forward declarations + */ +//static boolean isSessionAllowed(t_UDS_Session did_session); + +//static t_UDS_ERR Set_DID_GAC_Manufactory_Mode(uint8 *data); + +t_UDS_ERR CalibFun1(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data0, value); + + return TRUE; +} +t_UDS_ERR CalibFun2(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data1, value); + return TRUE; +} +t_UDS_ERR CalibFun3(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data2, value); + return TRUE; +} +t_UDS_ERR CalibUp(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data3, value); + return TRUE; +} +t_UDS_ERR CalibDown(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data4, value); + return TRUE; +} +t_UDS_ERR CalibLeft(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data5, value); + return TRUE; +} +t_UDS_ERR CalibRight(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data6, value); + return TRUE; +} +t_UDS_ERR CalibOk(uint8 *data) +{ + uint16 value = data[0]<<8 | data[1]; + Calib_Trigger(data7, value); + return TRUE; +} + +extern uint8 UDS_Vibration_Gain; +t_UDS_ERR Trigger_Vibration(uint8 *data) +{ + speeker_Tig_Once(49, UDS_Vibration_Gain); + return TRUE; +} +extern uint8 UDS_DAC_Ref_Voltage; +t_UDS_ERR DAC_Ref_Voltage(uint8 *data) +{ + t_UDS_ERR rtn = FALSE; + + if(*data < 8) + { + UDS_DAC_Ref_Voltage = *data; + SmartEE_Write(0x781, data, 1); + SUPC_REGS->SUPC_VREF = SUPC_VREF_SEL(UDS_DAC_Ref_Voltage); + rtn = TRUE; + } + return rtn; +} + +t_UDS_ERR Vibration_Gain(uint8 *data) +{ + t_UDS_ERR rtn = FALSE; + if(*data < 4) + { + UDS_Vibration_Gain = *data; + SmartEE_Write(0x780, data, 1); + rtn = TRUE; + } + return rtn; +} +extern uint8 UDS_DAC_Timer_Period; +t_UDS_ERR DAC_Timer_Period(uint8 *data) +{ + t_UDS_ERR rtn = FALSE; + if(*data <= 255 && *data >= 40) + { + UDS_DAC_Timer_Period = *data; + TC0_REGS->COUNT16.TC_CC[0U] = UDS_DAC_Timer_Period; + SmartEE_Write(0x782, data, 1); + rtn = TRUE; + } + return rtn; +} + +t_UDS_ERR Measure_Frame_Switch(uint8 *data) +{ + t_UDS_ERR rtn = FALSE; + if(*data == 1 || *data == 0) + { + + SmartEE_Write(0x783, data, 1); + rtn = TRUE; + } + return rtn; + +} + + +/* ---------------------------------------------------------------------------- + * Private variables + */ +t_UDSWriteDiDSubCommandsReference uds_did_write_commands_by_reference[] = +{ + { DID_CD_SYSID_VIN, 17, UDS_EXT_DIAG_SESSION, 1,Set_DID_CD_VIN }, + { DID_CD_SYSID_REPROGRAMING_DATE, 4, UDS_EXT_DIAG_SESSION, 1,Set_DID_Reprogramming_Date }, + { DID_CD_SYSID_REPAIR_SHOP_CODE, 16, UDS_EXT_DIAG_SESSION, 1,Set_DID_Repair_Shop_Code }, + {DID_FUN1, 2, UDS_EXT_DIAG_SESSION, 1, CalibFun1}, + {DID_FUN2, 2, UDS_EXT_DIAG_SESSION, 1, CalibFun2}, + {DID_FUN3, 2, UDS_EXT_DIAG_SESSION, 1, CalibFun3}, + {DID_UP, 2, UDS_EXT_DIAG_SESSION, 1, CalibUp}, + {DID_DOWN, 2, UDS_EXT_DIAG_SESSION, 1, CalibDown}, + {DID_LEFT, 2, UDS_EXT_DIAG_SESSION, 1, CalibLeft}, + {DID_RIGHT, 2, UDS_EXT_DIAG_SESSION, 1, CalibRight}, + {DID_OK, 2, UDS_EXT_DIAG_SESSION, 1, CalibOk}, + {DID_Trigger_Vibration, 1, UDS_EXT_DIAG_SESSION, 1, Trigger_Vibration}, + {DID_DAC_Ref_Voltage, 1, UDS_EXT_DIAG_SESSION, 1, DAC_Ref_Voltage}, + {DID_Vibration_Gain, 1, UDS_EXT_DIAG_SESSION, 1, Vibration_Gain}, + {DID_DAC_Timer_Period, 1, UDS_EXT_DIAG_SESSION, 1, DAC_Timer_Period}, + {DID_Measure_Frame_Switch, 1, UDS_EXT_DIAG_SESSION, 1, Measure_Frame_Switch}, +}; + +/* ---------------------------------------------------------------------------- + * Public variables + */ + +/* ---------------------------------------------------------------------------- + * Public functions + */ +//uint8 UDS_WriteDiD_CB(uint8 id_h, uint8 id_l, uint8 *buf_data_rx, uint16 size) +//{ +// uint16 requested_id; +// tp_uds_write_data_by_identifier resp; +// t_UDS_ERR response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; +// +// resp = ISO15765_3_GET_RESP_DATA(tp_uds_write_data_by_identifier); +// +// /* Get the complete id */ +// requested_id = ((((uint16) (id_h)) << 8) | ((uint16) (id_l))); +// +// for (uint8 idx = 0; idx < NOOF(uds_did_write_commands_by_reference); idx++) { +// if (requested_id == uds_did_write_commands_by_reference[idx].did) { +// +// if (TRUE == isSessionAllowed(uds_did_write_commands_by_reference[idx].allowed_session)) { +// +// if (NULL != uds_did_write_commands_by_reference[idx].Setter) { +// +// if(size == uds_did_write_commands_by_reference[idx].size) { +// +// //if(UdsSecurityTaskQueryAccessStatus() != UDS_ECU_LOCKED) { +// +// if (TRUE == uds_did_write_commands_by_reference[idx].Setter(buf_data_rx)) { +// response_mode = ISO15765_3_POSITIVE_RESPONSE; +// } +// else { +// /** Callback returned error **/ +// response_mode = UDS_ERR_CONDITIONS_NOT_CORRECT; +// } +// //} +// //else +// //{ +// /* Security is not correct*/ +// //response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; +// //} +// } +// else { +// /** Wrong size **/ +// response_mode = UDS_ERR_INVALID_FORMAT; +// } +// +// } +// else { +// /** Callback not implemented **/ +// response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; +// } +// +// } +// else { +// /** Wrong Session **/ +// response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; +// } +// break; +// } +// } +// +// /* Finally in case of positive response we set the identifier in the response */ +// if (response_mode == ISO15765_3_POSITIVE_RESPONSE) { +// resp->id_high = id_h; +// resp->id_low = id_l; +// Iso15765_3IncrementResponseSize((UI_8) 2); +// +// } else { +// +// /* Do nothing */ +// } +// +// /* Send the response to ISO_3 layer */ +// Iso15765_3SendResponse(response_mode); +// +// return response_mode; +//} + +/* ---------------------------------------------------------------------------- + * Private functions + */ +//static boolean isSessionAllowed(t_UDS_Session did_session) +//{ +// boolean result = FALSE; +// +// if (did_session == Iso15765_3QueryActiveSession()) { +// result = TRUE; +// } +// else{ +// result = FALSE; +// } +// +// return result; +//} + +//#include "ASILB_Common_Lib.h" +//#include "ReactionManager.h" +//#include "SafetyExceptions.h" + +//void SupportIDCheckFor_2E(uint8 * resp, uint8 id_l) +//{ +// uint8 idmsb; +// uint8 idlsb; +// uint8 bytepos; +// uint8 bitpos; +// +// memset(resp, (UI_8) 0, (UI_8) 32); +// +// if ((id_l == 0xDF) || (id_l == 0xEC) || (id_l == 0xED) || (id_l == 0xEE)) { +// /* DID MSB Support Check */ +// for (uint8 idx = 0; idx < NOOF(uds_did_write_commands_by_reference) ; idx++) { +// idmsb = uds_did_write_commands_by_reference[idx].did >> (UI_8) 8; +// bytepos = idmsb / (UI_8) 8; +// bitpos = idmsb % (UI_8) 8; +// resp[bytepos] |= ((UI_8) 1 << (7 - bitpos)); +// } +// } else { +// /* DID LSM Support Check for Assigned MSB */ +// idmsb = id_l; +// for (uint8 idx = 0; idx < NOOF(uds_did_write_commands_by_reference) ; idx++) { +// if (idmsb == uds_did_write_commands_by_reference[idx].did >> (UI_8) 8) { +// idlsb = ((UI_8) uds_did_write_commands_by_reference[idx].did); +// bytepos = idlsb / (UI_8) 8; +// bitpos = idlsb % (UI_8) 8; +// resp[bytepos] |= ((UI_8) 1 << (7 - bitpos)); +// } +// } +// } +//} + +//static void onWriteFinished(BOOL ret) +//{ + /* Do Nothing */ +//} + + +uint8 GetWriteDidServiceNumber(void) +{ + return NOOF(uds_did_write_commands_by_reference); +} diff --git a/firmware/src/DiagnosticR/UDS/UDS_IORoutineControl.c b/firmware/src/DiagnosticR/UDS/UDS_IORoutineControl.c new file mode 100644 index 0000000..3510a17 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_IORoutineControl.c @@ -0,0 +1,136 @@ +/* + * + * Copyright (C) 2020-2022 Qing.zhou + * + * + */ + + +/* -------------------------------- Includes -------------------------------- */ +/* external head files */ + +/* internal head files */ +#include "UDS_ServicesType.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "calib_public.h" + +#define NOOF(a) (sizeof(a)/sizeof(a[0])) +/* -------------------------------- Defines --------------------------------- */ + +/* -------------------------------- Macros ---------------------------------- */ + +/* ------------------------------- Data Types ------------------------------- */ + +/* -------------------------- Function declaration -------------------------- */ +static t_UDS_ERR Calib_KeyUp(void); +static t_UDS_ERR Calib_KeyDown(void); +static t_UDS_ERR Calib_KeyLeft(void); +static t_UDS_ERR Calib_KeyRight(void); +static t_UDS_ERR Calib_KeyOK(void); +static t_UDS_ERR Calib_KeyFun1(void); +static t_UDS_ERR Calib_KeyFun2(void); +static t_UDS_ERR Calib_KeyFun3(void); + +/* ----------------------------- Local Variables ---------------------------- */ + +/* ---------------------------- Global Variables ---------------------------- */ +t_UDSIOControlSubCommands uds_io_control_commands[] = +{ + /* DID Service legth Session support Security {ReturnControl , Default, Freeze, Adjustment} */ + { 0xD101 , 1 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {NULL, NULL, NULL, NULL} }, +}; + +t_UDSRoutineControlCommands uds_routine_control_commands[] = +{ + /* DID Service legth Session support Security {Start Stop Request } */ + { 0xAE00 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyUp, NULL, NULL} }, + { 0xAE01 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyDown, NULL, NULL} }, + { 0xAE02 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyLeft, NULL, NULL} }, + { 0xAE03 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyRight, NULL, NULL} }, + { 0xAE04 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyOK, NULL, NULL} }, + { 0xAE05 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyFun1, NULL, NULL} }, + { 0xAE06 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyFun2, NULL, NULL} }, + { 0xAE07 , 0 , UDS_EXT_DIAG_SESSION , UDS_ECU_LOCKED, {Calib_KeyFun3, NULL, NULL} }, +}; + +/* --------------------------- Private Variables ---------------------------- */ + +/* --------------------------- Private Functions ---------------------------- */ + + + +static t_UDS_ERR Calib_KeyUp(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data0,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyDown(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data1,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyLeft(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data2,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyRight(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data3,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyOK(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data4,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyFun1(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data5,0); + + + return response_mode; +} +static t_UDS_ERR Calib_KeyFun2(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data6,0); + + return response_mode; +} +static t_UDS_ERR Calib_KeyFun3(void) { + t_UDS_ERR response_mode = ISO15765_3_POSITIVE_RESPONSE; + /* implementation */ + Calib_Trigger(data7,0); + + return response_mode; +} + + +/* ---------------------------- Public Functions ---------------------------- */ + +uint8 GetIoControlServiceNumber(void){ + return NOOF(uds_io_control_commands); +} + + +uint8 GetRoutineServiceNumber(void){ + return NOOF(uds_routine_control_commands); +} + diff --git a/firmware/src/DiagnosticR/UDS/UDS_ServicesType.h b/firmware/src/DiagnosticR/UDS/UDS_ServicesType.h new file mode 100644 index 0000000..33b95f5 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_ServicesType.h @@ -0,0 +1,83 @@ +/* + * + * Copyright (C) 2020-2022 Qing.zhou + * + * + */ + +#ifndef __UDS_SERVICETYPE_H__ +#define __UDS_SERVICETYPE_H__ +/* -------------------------------- Includes -------------------------------- */ +/* external head files */ +//#include "Global.h" +#include "Std_Types.h" +/* internal head files */ + + + +/* -------------------------------- Defines --------------------------------- */ + +/* -------------------------------- Macros ---------------------------------- */ + +/* ------------------------------- Data Types ------------------------------- */ +typedef uint8 t_UDS_ERR; +typedef uint8 t_UDS_Session; + +#ifndef uint8_t +typedef unsigned char uint8_t; +#endif + +#ifndef uint16_t +typedef unsigned short uint16_t; +#endif + +typedef struct{ + t_UDS_ERR (*ImplReturn)(uint8 * buf_data_rx); /*return control to ECU implement*/ + t_UDS_ERR (*ImplDefault)(uint8 * buf_data_rx); /*reset to default implement*/ + t_UDS_ERR (*ImplFreeze)(uint8 * buf_data_rx); /*freeze current state implement*/ + t_UDS_ERR (*ImplControl)(uint8 * buf_data_rx); /*Short term adjustment implement*/ +}t_UDSIOcontrolParameter; + +typedef struct{ + t_UDS_ERR (*ImplStart)(void); /*start routine implement*/ + t_UDS_ERR (*ImplStop)(void); /*stop routine implement*/ + t_UDS_ERR (*ImplReq)(void); /*request resuolt routine implement*/ +}t_UDSRoutineControlParameter; + +typedef struct { + uint16_t did; + uint16_t size; /* size is the control status record without io control type */ + t_UDS_Session allowed_session; + uint8 security; /*Security access level of each did*/ + t_UDSIOcontrolParameter func_impl; +} t_UDSIOControlSubCommands; + +typedef struct { + uint16_t did; + uint16_t size; /* size is the */ + t_UDS_Session allowed_session; + uint8 security; /*Security access level of each did*/ + t_UDSRoutineControlParameter func_impl; +} t_UDSRoutineControlCommands; + +typedef struct { + uint16_t did; + uint16_t size; + t_UDS_Session allowed_session; + t_UDS_ERR (*Getter)(uint8 * buf_data_rx); +} t_UDSReadDidSubCommands; + +typedef struct { + uint16 did; + uint16 size; + t_UDS_Session allowed_session; + uint8 security; /*Security access level of each did*/ + t_UDS_ERR (*Setter)(uint8 * buf_data_rx); + +} t_UDSWriteDiDSubCommandsReference; + +/* ---------------------------- Global Variables ---------------------------- */ + +/* -------------------------- Function declaration -------------------------- */ + +#endif /* __UDS_SERVICETYPE_H */ diff --git a/firmware/src/DiagnosticR/UDS/UDS_Services_Common.c b/firmware/src/DiagnosticR/UDS/UDS_Services_Common.c new file mode 100644 index 0000000..1584715 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_Services_Common.c @@ -0,0 +1,360 @@ +/* + * + * Copyright (C) 2020-2022 Qing.zhou + * + * + */ +/* -------------------------------- Includes -------------------------------- */ +/* external head files */ + +/* internal head files */ +#include "UDS_Services_Common.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +/* -------------------------------- Defines --------------------------------- */ + +/* -------------------------------- Macros ---------------------------------- */ + +/* ------------------------------- Data Types ------------------------------- */ + +/* -------------------------- Function declaration -------------------------- */ +static BOOL isSessionAllowed(t_UDS_Session did_session); +static boolean UDS_isSecurityUnlocked(uint8 did_security_level); + +/* ----------------------------- Local Variables ---------------------------- */ + +/* ---------------------------- Global Variables ---------------------------- */ + +/* --------------------------- Private Variables ---------------------------- */ + +/* --------------------------- Private Functions ---------------------------- */ +static BOOL isSessionAllowed(t_UDS_Session did_session) +{ + UI_8 curr_session; + BOOL ret = FALSE; + + curr_session = Iso15765_3QueryActiveSession(); + + ret = ((curr_session & did_session) == curr_session) ? TRUE : FALSE; + + return ret; +} + +static boolean UDS_isSecurityUnlocked(uint8 did_security_level) +{ + boolean result = FALSE; + + if (UDS_ECU_LOCKED == did_security_level) { + if (UDS_ECU_LOCKED == UdsSecurityTaskQueryAccessStatus()) { + result = FALSE; + } + else{ + result = TRUE; + } + } + else { + result = TRUE; + } + + result = TRUE; + + return result; +} + + +/* ---------------------------- Public Functions ---------------------------- */ +uint8 UDS_ReadDiD_CB(uint8 id_h, uint8 id_l) +{ + uint16_t requested_id; + uint16_t resp_pos; + tp_uds_read_data_by_identifier_resp resp; + t_UDS_ERR response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + + resp_pos = 0;//( - (UI_16) 1); + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_read_data_by_identifier_resp); + /* Send correct Ids */ + resp->buffer_dades[resp_pos + 0] = id_h; + resp->buffer_dades[resp_pos + 1] = id_l; + + resp_pos = resp_pos + 2; + + /* Get the complete id */ + requested_id = ((uint16_t) id_h) << 8; + requested_id = requested_id | (uint16_t) id_l; + + for (uint8 idx = 0; idx < GetReadDidServiceNumber(); idx++) { + + if (requested_id == uds_did_read_commands[idx].did) { + + if (TRUE == isSessionAllowed(uds_did_read_commands[idx].allowed_session)) { + + (void)uds_did_read_commands[idx].Getter((t_UDS_ERR*)&resp->buffer_dades[resp_pos]); + Iso15765_3IncrementResponseSize(uds_did_read_commands[idx].size); + /* assuming no errors reading */ + response_mode = ISO15765_3_POSITIVE_RESPONSE; + + } + else { + response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + } + break; + } + } + + /* Finally, in case of positive response, we set the identifier in the response */ + if (response_mode == ISO15765_3_POSITIVE_RESPONSE) { + Iso15765_3IncrementResponseSize((UI_8) 2); + } else { + + /* Do nothing */ + } + + /* Send the response to ISO_3 layer */ + return (uint8)(response_mode); +} + +uint8 UDS_WriteDiD_CB(uint8 id_h, uint8 id_l, uint8 *buf_data_rx, uint16_t size) +{ + uint16_t requested_id; + tp_uds_write_data_by_identifier resp; + t_UDS_ERR response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_write_data_by_identifier); + + /* Get the complete id */ + requested_id = ((((uint16_t) (id_h)) << 8) | ((uint16_t) (id_l))); + + for (uint8 idx = 0; idx < GetWriteDidServiceNumber(); idx++) { + if (requested_id == uds_did_write_commands_by_reference[idx].did) { + + if (TRUE == isSessionAllowed(uds_did_write_commands_by_reference[idx].allowed_session)) { + if (TRUE == UDS_isSecurityUnlocked(uds_did_write_commands_by_reference[idx].security)) { + if (NULL != uds_did_write_commands_by_reference[idx].Setter) { + + if(size == uds_did_write_commands_by_reference[idx].size) { + response_mode = uds_did_write_commands_by_reference[idx].Setter(buf_data_rx); + } + else { + /** Wrong size **/ + response_mode = UDS_ERR_INVALID_FORMAT; + } + + } + else { + /** Callback not implemented **/ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + } + else { + /** Security is not unlocked **/ + response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; + } + } + else { + /** Wrong Session **/ + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } + break; + } + } + + /* Finally in case of positive response we set the identifier in the response */ + if (response_mode == ISO15765_3_POSITIVE_RESPONSE) { + resp->id_high = id_h; + resp->id_low = id_l; + Iso15765_3IncrementResponseSize((UI_8) 2); + + } else { + + /* Do nothing */ + } + + /* Send the response to ISO_3 layer */ + Iso15765_3SendResponse(response_mode); + + return response_mode; +} + + +/*! + * @brief Routine functional unit + * + * @param[in] routine_ctrl_type: routineControlType + * @param[in] id_high: ID MSB + * @param[in] id_low: ID LSB + * @param[in] routine_entry_option: routineControlOption + * @param[in] size: data size + * @return None + */ +void UDS_RoutineControl_CB(uint8 routine_ctrl_type, uint8 id_high, uint8 id_low, uint8 *routine_entry_option, uint16 size) +{ + tp_uds_control_routine resp; + uint8 response_mode = ISO15765_3_POSITIVE_RESPONSE; + uint16 id; + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_control_routine); + /* Get the complete id */ + id = ((uint16) id_high << 8) | (uint16) id_low; + + for (uint8 idx =0; idx < GetRoutineServiceNumber(); idx++){ + if (id == uds_routine_control_commands[idx].did){ + if (size == uds_routine_control_commands[idx].size){ + if (TRUE == isSessionAllowed(uds_routine_control_commands[idx].allowed_session)){ + if (TRUE == UDS_isSecurityUnlocked(uds_routine_control_commands[idx].security)){ + switch(routine_ctrl_type){ + case UDS_CTRL_ROUTINE_START: //DamonChange 20230117 0 replace NULL + if (0 != uds_routine_control_commands[idx].func_impl.ImplStart()){ + response_mode = uds_routine_control_commands[idx].func_impl.ImplStart(); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + case UDS_CTRL_ROUTINE_STOP: //DamonChange 20230117 0 replace NULL + if (0 != uds_routine_control_commands[idx].func_impl.ImplStop()){ + response_mode = uds_routine_control_commands[idx].func_impl.ImplStop(); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + case UDS_CTRL_ROUTINE_RESULTS: //DamonChange 20230117 0 replace NULL + if (0 != uds_routine_control_commands[idx].func_impl.ImplReq()){ + response_mode = uds_routine_control_commands[idx].func_impl.ImplReq(); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + default: + response_mode = UDS_ERR_INVALID_FORMAT; + break; + } + } + else{ + /** Security is not unlocked **/ + response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; + } + } + else{ + /** Wrong Session **/ + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } + } + else{ + /** Wrong size **/ + response_mode = UDS_ERR_INVALID_FORMAT; + } + break; + } + } + +/* Finally in case of positive response we set the identifier in the response */ + if (ISO15765_3_POSITIVE_RESPONSE == response_mode) { + resp->routine_ctrl_type = routine_ctrl_type; + resp->routine_id_high = id_high; + resp->routine_id_low = id_low; + Iso15765_3IncrementResponseSize(3); + } + /* Send the response to ISO_3 layer */ + Iso15765_3SendResponse(response_mode); +} + +/*! + * @brief InputOutput Control functional unit + * + * @param[in] id_h: ID MSB + * @param[in] id_l: ID LSB + * @param[in] io_ctrl_type: iocontrol type + * @param[in] buf_data_rx: controlOptionRecord + * @param[in] size: data size of buf_data_rx + * @return None + */ +void UDS_IOControl_CB(uint8 id_h, uint8 id_l, uint8 io_ctrl_type, uint8* buf_data_rx, uint16 size) +{ + uint16 io_ctl_id; + tp_uds_input_output_control_by_id resp; + t_UDS_ERR response_mode = UDS_ERR_REQUEST_OUT_OF_RANGE; + + resp = ISO15765_3_GET_RESP_DATA(tp_uds_input_output_control_by_id); + /* Get the complete id */ + io_ctl_id = ((((uint16) (id_h)) << 8) | ((uint16) (id_l))); + + for (uint8 idx = 0; idx < GetIoControlServiceNumber(); idx++) { + if (io_ctl_id == uds_io_control_commands[idx].did) { + if (size == uds_io_control_commands[idx].size){ + if (TRUE == isSessionAllowed(uds_io_control_commands[idx].allowed_session)) { + if (TRUE == UDS_isSecurityUnlocked(uds_io_control_commands[idx].security)) { + switch (io_ctrl_type){ + case IO_CTL_RETURN_CONTOL: //DamonChange 20230117 0 replace NULL + if (0 != uds_io_control_commands[idx].func_impl.ImplReturn(buf_data_rx)){ + response_mode = uds_io_control_commands[idx].func_impl.ImplReturn(buf_data_rx); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + case IO_CTL_RESET: //DamonChange 20230117 0 replace NULL + if (0 != uds_io_control_commands[idx].func_impl.ImplDefault(buf_data_rx)){ + response_mode = uds_io_control_commands[idx].func_impl.ImplDefault(buf_data_rx); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + case IO_CTL_FREEZE: //DamonChange 20230117 0 replace NULL + if (0 != uds_io_control_commands[idx].func_impl.ImplFreeze(buf_data_rx)){ + response_mode = uds_io_control_commands[idx].func_impl.ImplFreeze(buf_data_rx); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + case IO_CTL_CONTROL: //DamonChange 20230117 0 replace NULL + if (0 != uds_io_control_commands[idx].func_impl.ImplControl(buf_data_rx)){ + response_mode = uds_io_control_commands[idx].func_impl.ImplControl(buf_data_rx); + } + else{ + response_mode = UDS_ERR_SUBFUNCTION_NOT_SUPPORTED; + } + break; + default: + response_mode = UDS_ERR_INVALID_FORMAT; + break; + } + } + else{ + /** Security is not unlocked **/ + response_mode = UDS_ERR_SECURITY_ACCESS_DENIED; + } + } + else{ + /** Wrong Session **/ + response_mode = UDS_ERR_SERVICE_NOT_SUPORTED_IN_ACTIVE_SESSION; + } + } + else{ + /** Wrong size **/ + response_mode = UDS_ERR_INVALID_FORMAT; + } + break; + } + } + + /* Finally in case of positive response we set the identifier in the response */ + if (response_mode == ISO15765_3_POSITIVE_RESPONSE) { + resp->id_high = id_h; + resp->id_low = id_l; + resp->io_ctrl_type = io_ctrl_type; + Iso15765_3IncrementResponseSize((UI_8) 3); + } else { + + /* Do nothing */ + } + + /* Send the response to ISO_3 layer */ + Iso15765_3SendResponse(response_mode); +} + + diff --git a/firmware/src/DiagnosticR/UDS/UDS_Services_Common.h b/firmware/src/DiagnosticR/UDS/UDS_Services_Common.h new file mode 100644 index 0000000..eecb734 --- /dev/null +++ b/firmware/src/DiagnosticR/UDS/UDS_Services_Common.h @@ -0,0 +1,236 @@ + +#ifndef _UDS_SERVICES_COMMON_H_ +#define _UDS_SERVICES_COMMON_H_ +//<> + +#include "UDS_ServicesType.h" +/* --------------------------------------------------------------------------- + * Includes + */ +//#include "Platform_Types.h" + +/* --------------------------------------------------------------------------- + * Exported Constants + */ +#define UDS_FICOSA_SESSION UDS_SYSTEM_SUPPLIER_SPECIFIC_SESSION_ID + +/** Redefine project_config.mk imports for: + * - IDE indexing consistency + * - Defaults set + */ +#ifndef ECU_HW_ID + #define ECU_HW_ID "000A00" + //#warning "Using default ECU_HW_ID" +#endif + +#ifndef ECU_SW_ID + #define ECU_SW_ID "A00RC3" + //#warning "Using default ECU_SW_ID" +#endif + +#define FICOSA_DEBUG +/** End of project_config redefines **/ +#define IO_CTL_RETURN_CONTOL ((UI_8)0x00) +#define IO_CTL_RESET ((UI_8)0x01) +#define IO_CTL_FREEZE ((UI_8)0x02) +#define IO_CTL_CONTROL ((UI_8)0x03) +/* --------------------------------------------------------------------------- + * Exported Macros + */ +#define DTC_SETTING_HIGH_VOLTAGE_NUM ((uint8)0) +#define DTC_SETTING_LOW_VOLTAGE_NUM ((uint8)1) +#define DTC_SETTING_INVALID_TCU_NUM ((uint8)2) +#define DTC_SETTING_INVALID_EMS_NUM ((uint8)3) +#define DTC_SETTING_INVALID_PEDAL_NUM ((uint8)30) +#define DTC_SETTING_INVALID_BCS_NUM ((uint8)4) +#define DTC_SETTING_INVALID_SPEED_NUM ((uint8)17) +#define DTC_SETTING_LOST_APA_NUM ((uint8)5) +#define DTC_SETTING_INVALID_APA_NUM ((uint8)6) +#define DTC_SETTING_LOST_BCM_NUM ((uint8)7) +#define DTC_SETTING_LOST_ICM_NUM ((uint8)9) +#define DTC_SETTING_INVALID_ICM_NUM ((uint8)10) +#define DTC_SETTING_LOST_EMS_NUM ((uint8)11) +//#define DTC_SETTING_LOST_TCU_NUM ((uint8)12) +#define DTC_SETTING_LOST_VCU_NUM ((uint8)12) +#define DTC_SETTING_LOST_BCS_NUM ((uint8)13) +#define DTC_SETTING_LOST_SRS_NUM ((uint8)15) +#define DTC_SETTING_BUS_OFF_NUM ((uint8)16) +#define DTC_SETTING_SENSOR_DIE1_FAULT_NUM ((uint8)18) +#define DTC_SETTING_SENSOR_DIE2_FAULT_NUM ((uint8)19) +#define DTC_SETTING_SENSOR_HEAVY_FAULT_NUM ((uint8)20) +#define DTC_SETTING_SWITCH_HEAVY_FAULT_NUM ((uint8)21) +#define DTC_SETTING_SWITCH1_OC_FAULT_NUM ((uint8)22) +#define DTC_SETTING_SWITCH1_GND_FAULT_NUM ((uint8)23) +#define DTC_SETTING_SWITCH1_VCC_FAULT_NUM ((uint8)24) +#define DTC_SETTING_SWITCH1_PRESSED_FAULT_NUM ((uint8)25) +#define DTC_SETTING_SWITCH2_OC_FAULT_NUM ((uint8)26) +#define DTC_SETTING_SWITCH2_GND_FAULT_NUM ((uint8)27) +#define DTC_SETTING_SWITCH2_VCC_FAULT_NUM ((uint8)28) +#define DTC_SETTING_SWITCH2_PRESSED_FAULT_NUM ((uint8)29) + +#define DTC_SETTING_PADDLE_OC_FAULT_NUM ((uint8)32) +#define DTC_SETTING_PADDLE_GND_FAULT_NUM ((uint8)33) +#define DTC_SETTING_PADDLE_VCC_FAULT_NUM ((uint8)34) +#define DTC_SETTING_PADDLE_PRESSED_FAULT_NUM ((uint8)35) + +#define DTC_SETTING_OL_GND_FAULT_NUM ((uint8)46) +#define DTC_SETTING_OL_VCC_FAULT_NUM ((uint8)47) + +#define DTC_SETTING_ECO_OC_FAULT_NUM ((uint8)49) +#define DTC_SETTING_ECO_GND_FAULT_NUM ((uint8)50) +#define DTC_SETTING_ECO_VCC_FAULT_NUM ((uint8)51) +#define DTC_SETTING_ECO_PRESSED_FAULT_NUM ((uint8)48) + +#define DTC_SETTING_LOST_ACM_NUM ((uint8)53) +#define DTC_SETTING_INVALID_ACM_NUM ((uint8)54) +#define DTC_SETTING_ACM_FAULT_NUM ((uint8)55) + +#define DTC_SETTING_GSS_FAULT_NUM ((uint8)56) +#define DTC_SETTING_SHIFT_STUCKED_FAULT_NUM ((uint8)57) +#define DTC_SETTING_SHIFT_CALIB_FAULT_NUM ((uint8)58) + +#define TEST_DTC_SETTING_ENABLE(v) ((((p_dtc_setting[v/8]>>(v%8))&0x01) > 0)?1:0) + +/* --------------------------------------------------------------------------- + * Exported Types + */ +typedef uint8 t_UDS_ERR; +typedef uint8 t_UDS_Session; +extern uint8* p_dtc_setting; +extern boolean clear_dtc_flag; +extern UI_16 g16_DiagTouchPressSenRes[3][15]; +/* --------------------------------------------------------------------------- + * Exported Variables + */ +extern t_UDSIOControlSubCommands uds_io_control_commands[]; +extern t_UDSRoutineControlCommands uds_routine_control_commands[]; +extern t_UDSReadDidSubCommands uds_did_read_commands[]; +extern t_UDSWriteDiDSubCommandsReference uds_did_write_commands_by_reference[]; +extern uint8 GetRoutineServiceNumber(void); +extern uint8 GetIoControlServiceNumber(void); +extern uint8 GetWriteDidServiceNumber(void); +extern uint8 GetReadDidServiceNumber(void); +/* --------------------------------------------------------------------------- + * Exported Functions + */ +uint8 UDS_ReadDiD_CB(uint8 id_h, uint8 id_l); +uint8 UDS_WriteDiD_CB(uint8 id_h, uint8 id_l, uint8 *buf_data_rx, uint16 size); +uint8 UDS_ReadMCAL_CB(uint16 requested_id, uint16 resp_pos); +void UDS_RoutineControl_CB(uint8 routine_ctrl_type, uint8 id_high, uint8 id_low, uint8 *routine_entry_option, uint16 size); +void UDS_IOControl_CB(uint8 id_h, uint8 id_l, uint8 io_ctrl_type, uint8* buf_data_rx, uint16 size); +void UDS_DTCSetting_CB(uint8 sub_function, uint8 *buf_data_rx, uint16 size); +/* NVM DIDs */ +t_UDS_ERR Get_DID_ECU_SN(uint8 *data); +t_UDS_ERR Set_DID_ECU_SN(uint8 *data); + +t_UDS_ERR Get_DID_CD_SYSID_VIN(uint8 *data); +t_UDS_ERR Set_DID_CD_VIN(uint8 *data); + +t_UDS_ERR Get_DID_TouchSen1_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen2_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen3_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen4_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen5_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen6_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen7_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen8_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen9_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen10_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen11_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen12_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen13_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen14_BaseLine(uint8 *data); +t_UDS_ERR Get_DID_TouchSen15_BaseLine(uint8 *data); + +t_UDS_ERR Get_DID_TouchSen1_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen2_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen3_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen4_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen5_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen6_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen7_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen8_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen9_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen10_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen11_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen12_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen13_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen14_Signal(uint8 *data); +t_UDS_ERR Get_DID_TouchSen15_Signal(uint8 *data); + +t_UDS_ERR Get_DID_PressSen_Baseline(uint8 *data); +t_UDS_ERR Get_DID_PressSen_Signal(uint8 *data); +t_UDS_ERR Get_DID_Pre_Value(uint8 *data); + +t_UDS_ERR Get_DID_CD_SYSID_CALIRATION_DATE(uint8 *data); +t_UDS_ERR Set_DID_CD_CALIRATION_DATE(uint8 *data); + +t_UDS_ERR Get_DID_CD_SYSID_MANUF_ECUHWNUM(uint8 *data); +t_UDS_ERR Set_DID_CD_MANUF_ECUHWNUM(uint8 *data); + +t_UDS_ERR Get_DID_Dtc_Setting(uint8 *data); +t_UDS_ERR Set_DID_Dtc_Setting(uint8 *data); + +t_UDS_ERR Get_DID_Transportation_Mode(uint8 *data); +t_UDS_ERR Set_DID_Transportation_Mode(uint8 *data); + +t_UDS_ERR Get_DID_Reprogramming_Counter(uint8 *data); +t_UDS_ERR Get_DID_Reprogramming_Attempt_Counter(uint8 *data); +t_UDS_ERR Get_DID_Reprogramming_Date(uint8 *data); +t_UDS_ERR Set_DID_Manufacture_Date(uint8 *data); +t_UDS_ERR Set_DID_Reprogramming_Date(uint8 *data); +t_UDS_ERR Get_DID_EcuManufacture_Date(uint8 *data); +t_UDS_ERR Get_DID_EcuInstallation_Date(uint8 *data); +t_UDS_ERR Set_DID_EcuInstallation_Date(uint8 *data); +t_UDS_ERR Get_DID_App_Sw_Finger_Print(uint8 *data); +t_UDS_ERR Set_DID_CD_APP_SW_FINGERPRINT(uint8 *data); +t_UDS_ERR Get_DID_Gac_Diagnostic_Version(uint8 *data); + +t_UDS_ERR Get_DID_GAC_Repair_Shop_Id(uint8 *data); +t_UDS_ERR Set_DID_Repair_Shop_Code(uint8 *data); + +t_UDS_ERR Get_DID_Gac_Hw_Version(uint8 *data); +t_UDS_ERR Get_DID_Gac_Ecusw_Version(uint8 *data); +t_UDS_ERR Get_DID_Gac_Spare_Number(uint8 *data); +t_UDS_ERR Get_DID_System_Supplier_Id(uint8 *data); +t_UDS_ERR Get_DID_Gac_Kit_Part_Number(uint8 *data); +t_UDS_ERR Get_DID_System_Name(uint8 *data); +t_UDS_ERR Get_DID_Uds_Protol_Version(uint8 *data); +t_UDS_ERR Get_DID_Boot_Version(uint8 *data); +t_UDS_ERR Get_DID_DCID(uint8 *data); +t_UDS_ERR Get_DID_Boot_ID(uint8 *data); + + +t_UDS_ERR Set_DID_Shield_Atp(uint8 *data); +t_UDS_ERR Get_DID_Shield_Atp(uint8 *data); + +t_UDS_ERR Set_DID_CD_Shared_key(uint8 *data); + +void UDS_DID_initNVM(void); + +uint8 Get_Drive_Mode(void); +void Set_RAM_Drive_Mode(uint8 mode); +uint8 GetNvmFaa(void); +uint8 GetNvmManufactoryMode(void); +uint8 GetNvmEolConfig(void); +uint8* GetNvmDtcSetting(void); +boolean doReset(void); + +/* Enable Engineering Mode */ +boolean isXCPEnabled(void); +boolean isWriteDriversAccessEnabled(void); +uint8 Get_FC_DevMode(uint8 *data); +uint8 Set_FC_DevMode(const uint8 *data); + +//t_UDS_ERR Set_DID_CD_Drive_Mode_Configure(uint8 *data); +t_UDS_ERR Get_DID_Drive_Mode_Configure(uint8 *data); + +void SupportIDCheckFor_2E(uint8 * resp, uint8 id_l); + +t_UDS_ERR UDS_ReadSBCResetReason (uint8* data); + +uint8 GetLastPosition(void); + +#endif /* _UDS_SERVICES_COMMON_H_ */ diff --git a/firmware/src/DiagnosticR/_configurations/FicosarCfg.h b/firmware/src/DiagnosticR/_configurations/FicosarCfg.h new file mode 100644 index 0000000..09d41e9 --- /dev/null +++ b/firmware/src/DiagnosticR/_configurations/FicosarCfg.h @@ -0,0 +1,135 @@ + +#ifndef FICOSARCFG_H_ +#define FICOSARCFG_H_ + +/*----------------------------- MICROCONTROLLER -----------------------------*/ + +/* Definition of over which micro the code will be running. Allowed Values: */ +#define MPC5604 (0) +#define RH850F1L (1) + +#define MICROCONTROLLER (RH850F1L) + +/*----------------------------- CONFIG VERSION -----------------------------*/ +/* Iteration of the configuration. Updated every time the config API changes */ + +#define HAL_FICOSAR_CFG_VERSION 5 + + + +///* AUTOSAR defines different prototypes for CanIf_RxIndication. */ +//#define VARIANT_4_0 0 +//#define VARIANT_4_2 1 +// +//#define AUTOSAR_VARIANT VARIANT_4_0 + +/*--------------------- CAN COMMUNICATIONS CONFIGURATION --------------------*/ + +/*Name of the external data structure containing the overall initialization */ +/*data for the CAN driver and affecting all controllers. */ +#define CAN_CONFIG_SET_0 (&Can_RSCAN_GstConfigType[0]) + +/* Extended CAN frames filter flag. Allowed values: */ +/* CAN_EXTENDED_FRAMES_NOTIFIED: Extended frames aren't filtered by HW */ +/* CAN_EXTENDED_FRAMES_FILTERED: Extended frames are filtered by HW */ +/* Extended frames reception is incompatible with recording via CAN. */ +#define CAN_EXTENDED_FRAMES (CAN_EXTENDED_FRAMES_FILTERED) + +/* Define here the number of CAN controllers used (1 or 2) */ +#define NO_OF_CAN_CONTROLLERS ((UI_8)1) +/* Configuration parameter of CANn enabling. */ +/* Allowed values: CAN_ENABLED, CAN_DISABLED. */ +#define CAN1_MODE (CAN_ENABLED) +#define CAN2_MODE (CAN_DISABLED) + +/* Define which controller uses each CAN logical channel */ +#define CAN1_CONTROLLER ((UI_8) 0x01) +#define CAN2_CONTROLLER ((UI_8) 0x02) + +/* Define here the number of TX HW buffers configured for each CAN Controller + * Current maximum hw buffers number supported is 2. */ +#define NO_OF_TX_CAN_BUFFERS (1) + +/* Configuration set for CAN1 */ +#define CAN_1_RX_HW_OBJECT0 (CanConf_CanHardwareObject_Ctrl_0_Rx_0) /* RECEIVE object of Can Controller ID = 0 */ +#define CAN_1_TX_HW_OBJECT0 (CanConf_CanHardwareObject_Ctrl_0_Tx_0) /* TRANSMIT object 1 of Can Controller ID = 0 */ +//#define CAN_1_TX_HW_OBJECT1 + +/* Configuration set for CAN2 */ +//#define CAN_2_RX_HW_OBJECT0 (CanConf_CanHardwareObject_CanHardwareObject1) /* RECEIVE object of Can Controller ID = 1 */ +//#define CAN_2_TX_HW_OBJECT0 (CanConf_CanHardwareObject_CanHardwareObject3) /* TRANSMIT object 1 of Can Controller ID = 1 */ +//#define CAN_2_TX_HW_OBJECT1 + +/* Callback Routines */ +/* The prototype of the function is void ((* func) (t_can_buf_hdl bhdl)) for */ +/* Rx and Tx. */ +/* The prototype of the function is void ((BOOL)(* func) (void)) for TxReq. */ +/* If you don't want to use any callback function, you should not define */ +/* this parameter. */ +#define CAN1_RX_CALLBACK (OsekComRxNotifCallbackSWTR) +#define CAN1_TXREQ_CALLBACK (OsekComTxReqCallbackSWTR) +#define CAN1_TX_CALLBACK (OsekComTxNotifCallbackSWTR) + +//#define CAN2_RX_CALLBACK (Can2_Rx_Cb) +//#define CAN2_TXREQ_CALLBACK (Can2_TxReq_Cb) +//#define CAN2_TX_CALLBACK (Can2_TxNotif_Cb) + +/*------------------------ TIMER CONFIGURATION --------------------------*/ + +/* Definition of GPT Configuration Set 0 handler */ +#define GPT_CONFIG_SET_0 (&Gpt_GstConfiguration[0]) +/* Definition of GPT Configuration Channel 0 handler */ +#define GPT_CONFIG_CHANNEL_0 (GptConf_GptChannelConfiguration_GptChannelConfiguration0) + +/* Definition of clock frequency for the system timer(set in ECU SPECTRUM) */ +#define FREQ_SYS_CLOCK (40) /* SYS_CLOCK = 40MHz */ + +/* Time units configuration parameter which TIMER_TIME_TICK parameter is */ +/* expressed. Allowed Values: */ +/* M_SECONDS if you pass a value in miliseconds */ +/* U_SECONDS if you pass a value in microseconds */ +#define TIMER_TIME_UNIT (M_SECONDS) + +/* Period between clock ticks configuration parameter. */ +/* Allowable Values when FREQ_CLOCK_MHZ is 8: */ +/* - If TIMER_TIME_UNIT is M_SECONDS: any in the range [1-63] */ +/* - If TIMER_TIME_UNIT is U_SECONDS: any in the range [1-255], */ +/* and the tick will be 125 x TIMER_TIME_TICK microseconds. */ +/* Example: TIMER_TIME_TICK = 2 --> tick of 250 microseconds */ +/* Allowable Values when FREQ_CLOCK_MHZ is 5: */ +/* - If TIMER_TIME_UNIT is M_SECONDS: any in the range [1-51] */ +/* - If TIMER_TIME_UNIT is U_SECONDS: any in the range [1-255], */ +/* and the tick will be 200 x TIMER_TIME_TICK microseconds. */ +/* Example: TIMER_TIME_TICK = 2 --> tick of 400 microseconds */ +/* Allowable Values when FREQ_CLOCK_MHZ is 12: */ +/* - If TIMER_TIME_UNIT is M_SECONDS: any in the range [1-42] */ +/* - If TIMER_TIME_UNIT is U_SECONDS: any in the range [1-255], */ +/* and the tick will be 166,666... x TIMER_TIME_TICK microseconds. */ +/* Example: TIMER_TIME_TICK = 3 --> tick of 500 microseconds */ +#define TIMER_TIME_TICK (1) + +/* Configuration parameter of the number of clock ticks that the main */ +/* program cycle works. Admisible Values: [1-127]. This value is obtained */ +/* by dividing the time of the program cycle period between the ticks. */ +/* For example, if you have a period of 250 microseconds between ticks */ +/* and we want a cycle of 5 ms, we have to set TIMER_TICKS_CICLE to: */ +/* 5000/250 = 20 */ +#define TIMER_TICKS_CICLE (2) + +/* Definition of the t_timer_time size that will be used in every FSM and */ +/* generated code. */ +/* Allowed values for TIMER_T_CLOCK_SIZE */ +/* T_TIMER_TIME_1_BYTE (1) */ +/* T_TIMER_TIME_2_BYTE (2) */ +/* T_TIMER_TIME_4_BYTE (3) */ +#define T_TIMER_TIME_SIZE (T_TIMER_TIME_4_BYTE) + +/* Name of the auxiliar callback function to execute each clock tick. */ +/* The prototype of the function is void (* func) (void)). If you don't want */ +/* to use any callback function, you should not define this parameter. The */ +/* user is responsible to calculate the increased cost in execution time */ +/* that the call of this function may cause. */ +#define TIMER_TICK_CALLBACK (SystemTick_callback) + + +#endif /* FICOSARCFG_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Dem_MemMap.h b/firmware/src/DiagnosticR/rte/Dem_MemMap.h new file mode 100644 index 0000000..677e1e3 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Dem_MemMap.h @@ -0,0 +1,24 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef DEM_MEMMAP_H_ +#define DEM_MEMMAP_H_ + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with Dcm service component. +#endif + + + +#endif /* DEM_MEMMAP_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Rte_ComM_Type.h b/firmware/src/DiagnosticR/rte/Rte_ComM_Type.h new file mode 100644 index 0000000..953e044 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_ComM_Type.h @@ -0,0 +1,33 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_COMM_TYPE_H_ +#define RTE_COMM_TYPE_H_ + +#define COMMM_NOT_SERVICE_COMPONENT +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with ComM service component. +#include "Rte_Type.h" +#else + +/** Current mode of the Communication Manager (main state of the state machine). */ +/** @req COMM879 */ +typedef uint8 ComM_ModeType; /** @req COMM867 @req COMM868 */ + +/** Inhibition status of ComM. */ +typedef uint8 ComM_InhibitionStatusType; + +typedef uint8 ComM_UserHandleType; +#endif +#endif // RTE_COMM_TYPE_H_ diff --git a/firmware/src/DiagnosticR/rte/Rte_Dcm_Type.h b/firmware/src/DiagnosticR/rte/Rte_Dcm_Type.h new file mode 100644 index 0000000..4960190 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_Dcm_Type.h @@ -0,0 +1,100 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_DCM_TYPE_H_ +#define RTE_DCM_TYPE_H_ + +#if !defined(DCM_UNIT_TEST) || (DCM_UNIT_TEST == STD_OFF) +#define DCM_NOT_SERVICE_COMPONENT +#endif + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with Dcm service component. +#include "Rte_Type.h" +#define DCM_RES_POS_OK ((Dcm_ConfirmationStatusType)0x00) +#define DCM_RES_POS_NOT_OK ((Dcm_ConfirmationStatusType)0x01) +#define DCM_RES_NEG_OK ((Dcm_ConfirmationStatusType)0x02) +#define DCM_RES_NEG_NOT_OK ((Dcm_ConfirmationStatusType)0x03) + +/* + * Dcm_SesCtrlType + */ +#ifndef DCM_DEFAULT_SESSION +#define DCM_DEFAULT_SESSION ((Dcm_SesCtrlType)0x01) +#endif +#ifndef DCM_PROGRAMMING_SESSION +#define DCM_PROGRAMMING_SESSION ((Dcm_SesCtrlType)0x02) +#endif +#ifndef DCM_EXTENDED_DIAGNOSTIC_SESSION +#define DCM_EXTENDED_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x03) +#endif +#ifndef DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION +#define DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x04) +#endif +#ifndef DCM_OBD_SESSION +#define DCM_OBD_SESSION ((Dcm_SesCtrlType)0x05)//only used for OBD diagnostic +#endif +#ifndef DCM_ALL_SESSION_LEVEL +#define DCM_ALL_SESSION_LEVEL ((Dcm_SesCtrlType)0xFF) +#endif + +#else +typedef uint8 Dcm_ConfirmationStatusType; +#define DCM_RES_POS_OK ((Dcm_ConfirmationStatusType)0x00) +#define DCM_RES_POS_NOT_OK ((Dcm_ConfirmationStatusType)0x01) +#define DCM_RES_NEG_OK ((Dcm_ConfirmationStatusType)0x02) +#define DCM_RES_NEG_NOT_OK ((Dcm_ConfirmationStatusType)0x03) + +typedef uint8 Dcm_NegativeResponseCodeType; + +typedef uint8 Dcm_OpStatusType; + +typedef uint8 Dcm_ProtocolType; + +typedef uint8 Dcm_SesCtrlType; + +/* + * Dcm_SesCtrlType + */ +#ifndef DCM_DEFAULT_SESSION +#define DCM_DEFAULT_SESSION ((Dcm_SesCtrlType)0x01) +#endif +#ifndef DCM_PROGRAMMING_SESSION +#define DCM_PROGRAMMING_SESSION ((Dcm_SesCtrlType)0x02) +#endif +#ifndef DCM_EXTENDED_DIAGNOSTIC_SESSION +#define DCM_EXTENDED_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x03) +#endif +#ifndef DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION +#define DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x04) +#endif +#ifndef DCM_OBD_SESSION +#define DCM_OBD_SESSION ((Dcm_SesCtrlType)0x05)//only used for OBD diagnostic +#endif +#ifndef DCM_ALL_SESSION_LEVEL +#define DCM_ALL_SESSION_LEVEL ((Dcm_SesCtrlType)0xFF) +#endif + + + +typedef uint8 Dcm_SecLevelType; + +typedef uint8 Dcm_RoeStateType; + +typedef uint8 DTRStatusType; + + + +#endif +#endif /*RTE_DCM_TYPE_H_*/ diff --git a/firmware/src/DiagnosticR/rte/Rte_Dem_Type.h b/firmware/src/DiagnosticR/rte/Rte_Dem_Type.h new file mode 100644 index 0000000..d7a923e --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_Dem_Type.h @@ -0,0 +1,38 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_DEM_TYPE_H_ +#define RTE_DEM_TYPE_H_ + +#define DEM_NOT_SERVICE_COMPONENT +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with Dem service component. +#include "Rte_Type.h" +typedef uint32 Dem_DTCType; +typedef sint8 Dem_FaultDetectionCounterType; +#else +typedef uint32 Dem_DTCType; +typedef uint16 Dem_EventIdType; +typedef sint8 Dem_FaultDetectionCounterType; +typedef uint8 Dem_IndicatorStatusType; +typedef uint8 Dem_InitMonitorReasonType; +typedef uint8 Dem_OperationCycleIdType; +typedef uint8 Dem_OperationCycleStateType; +typedef uint8 Dem_EventStatusType; +typedef uint8 Dem_EventStatusExtendedType; +typedef uint8 Dem_DTCFormatType; +typedef uint8 Dem_DTCOriginType; +typedef uint8 Dem_ReturnClearDTCType; +#endif +#endif /* RTE_DEM_TYPE_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Rte_Dlt_Type.h b/firmware/src/DiagnosticR/rte/Rte_Dlt_Type.h new file mode 100644 index 0000000..f7fead9 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_Dlt_Type.h @@ -0,0 +1,173 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_DLT_TYPE_H_ +#define RTE_DLT_TYPE_H_ + +#define DLT_NOT_SERVICE_COMPONENT + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with Dlt Service Component. +#include "Rte_Type.h" + +/* @req SWS_Dlt_00230 */ +/* @req SWS_Dlt_00010 */ +/** Enum literals for Dlt_MessageLogLevelType */ +#ifndef DLT_LOG_OFF +#define DLT_LOG_OFF 0U +#endif /* DLT_LOG_OFF */ + +#ifndef DLT_LOG_FATAL +#define DLT_LOG_FATAL 1U +#endif /* DLT_LOG_FATAL */ + +#ifndef DLT_LOG_ERROR +#define DLT_LOG_ERROR 2U +#endif /* DLT_LOG_ERROR */ + +#ifndef DLT_LOG_WARN +#define DLT_LOG_WARN 3U +#endif /* DLT_LOG_WARN */ + +#ifndef DLT_LOG_INFO +#define DLT_LOG_INFO 4U +#endif /* DLT_LOG_INFO */ + +#ifndef DLT_LOG_DEBUG +#define DLT_LOG_DEBUG 5U +#endif /* DLT_LOG_DEBUG */ + +#ifndef DLT_LOG_VERBOSE +#define DLT_LOG_VERBOSE 6U +#endif /* DLT_LOG_VERBOSE */ + +/** Enum literals for Dlt_MessageTraceType */ +#ifndef DLT_TRACE_VARIABLE +#define DLT_TRACE_VARIABLE 1U +#endif /* DLT_TRACE_VARIABLE */ + +#ifndef DLT_TRACE_FUNCTION_IN +#define DLT_TRACE_FUNCTION_IN 2U +#endif /* DLT_TRACE_FUNCTION_IN */ + +#ifndef DLT_TRACE_FUNCTION_OUT +#define DLT_TRACE_FUNCTION_OUT 3U +#endif /* DLT_TRACE_FUNCTION_OUT */ + +#ifndef DLT_TRACE_STATE +#define DLT_TRACE_STATE 4U +#endif /* DLT_TRACE_STATE */ + +#ifndef DLT_TRACE_VFB +#define DLT_TRACE_VFB 5U +#endif /* DLT_TRACE_VFB */ + +#else +/* @req SWS_Dlt_00225 */ +typedef uint32 Dlt_SessionIDType; + +/* @req SWS_Dlt_00226 *//* @req SWS_Dlt_00127 *//* @req SWS_Dlt_00312 */ +typedef uint8 Dlt_ApplicationIDType[4]; + +/* @req SWS_Dlt_00227 *//* @req SWS_Dlt_00128 *//* @req SWS_Dlt_00313 */ +typedef uint8 Dlt_ContextIDType[4]; + +/* @req SWS_Dlt_00228 */ +typedef uint32 Dlt_MessageIDType; + +/* @req SWS_Dlt_00229 */ +typedef uint8 Dlt_MessageOptionsType; + +/* @req SWS_Dlt_00235 */ +typedef uint16 Dlt_MessageArgumentCount; + +typedef uint8 Dlt_MessageLogLevelType; + +/* @req SWS_Dlt_00236 */ +typedef struct { + Dlt_MessageArgumentCount arg_count; + Dlt_MessageLogLevelType log_level; + Dlt_MessageOptionsType options; + Dlt_ContextIDType context_id; + Dlt_ApplicationIDType app_id; +} Dlt_MessageLogInfoType; + +/* @req SWS_Dlt_00230 */ +/* @req SWS_Dlt_00010 */ +/** Enum literals for Dlt_MessageLogLevelType */ +#ifndef DLT_LOG_OFF +#define DLT_LOG_OFF 0U +#endif /* DLT_LOG_OFF */ + +#ifndef DLT_LOG_FATAL +#define DLT_LOG_FATAL 1U +#endif /* DLT_LOG_FATAL */ + +#ifndef DLT_LOG_ERROR +#define DLT_LOG_ERROR 2U +#endif /* DLT_LOG_ERROR */ + +#ifndef DLT_LOG_WARN +#define DLT_LOG_WARN 3U +#endif /* DLT_LOG_WARN */ + +#ifndef DLT_LOG_INFO +#define DLT_LOG_INFO 4U +#endif /* DLT_LOG_INFO */ + +#ifndef DLT_LOG_DEBUG +#define DLT_LOG_DEBUG 5U +#endif /* DLT_LOG_DEBUG */ + +#ifndef DLT_LOG_VERBOSE +#define DLT_LOG_VERBOSE 6U +#endif /* DLT_LOG_VERBOSE */ + +typedef uint8 Dlt_MessageTraceType; + +/* @req SWS_Dlt_00237 */ +typedef struct { + Dlt_MessageTraceType trace_info; + Dlt_MessageOptionsType options; + Dlt_ContextIDType context; + Dlt_ApplicationIDType app_id; +} Dlt_MessageTraceInfoType; + +/** Enum literals for Dlt_MessageTraceType */ +#ifndef DLT_TRACE_VARIABLE +#define DLT_TRACE_VARIABLE 1U +#endif /* DLT_TRACE_VARIABLE */ + +#ifndef DLT_TRACE_FUNCTION_IN +#define DLT_TRACE_FUNCTION_IN 2U +#endif /* DLT_TRACE_FUNCTION_IN */ + +#ifndef DLT_TRACE_FUNCTION_OUT +#define DLT_TRACE_FUNCTION_OUT 3U +#endif /* DLT_TRACE_FUNCTION_OUT */ + +#ifndef DLT_TRACE_STATE +#define DLT_TRACE_STATE 4U +#endif /* DLT_TRACE_STATE */ + +#ifndef DLT_TRACE_VFB +#define DLT_TRACE_VFB 5U +#endif /* DLT_TRACE_VFB */ + +typedef uint8 Dlt_ReturnType; + + +#endif /* USE_RTE */ + +#endif /* RTE_DLT_TYPE_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Rte_EcuM_Type.h b/firmware/src/DiagnosticR/rte/Rte_EcuM_Type.h new file mode 100644 index 0000000..691144e --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_EcuM_Type.h @@ -0,0 +1,31 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_ECUM_TYPE_H_ +#define RTE_ECUM_TYPE_H_ + +#define ECUM_NOT_SERVICE_COMPONENT +#ifdef USE_RTE +#warning This file should only be used when NOT using an EcuM Service Component. +#include "Rte_Type.h" +#else +/* @req EcuM2664 */ +/* @req EcuM507 */ /* @req EcuM4039 */ +typedef uint8 EcuM_StateType; +/* @req EcuM4067 */ +typedef uint8 EcuM_UserType; +/* @req EcuM4042 */ +typedef uint8 EcuM_BootTargetType; +#endif +#endif /* RTE_ECUM_TYPE_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Rte_Main.h b/firmware/src/DiagnosticR/rte/Rte_Main.h new file mode 100644 index 0000000..74d6916 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_Main.h @@ -0,0 +1,25 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_MAIN_H_ +#define RTE_MAIN_H_ + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE. +#endif + +Std_ReturnType Rte_Start( void ); +Std_ReturnType Rte_Stop( void ); + +#endif /*RTE_MAIN_H_*/ diff --git a/firmware/src/DiagnosticR/rte/Rte_NvM_Type.h b/firmware/src/DiagnosticR/rte/Rte_NvM_Type.h new file mode 100644 index 0000000..63210c6 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_NvM_Type.h @@ -0,0 +1,52 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ +/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.0.3 */ + +#ifndef RTE_NVM_TYPE_H_ +#define RTE_NVM_TYPE_H_ + +#define NVM_NOT_SERVICE_COMPONENT + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with NvM Service Component. +#include "Rte_Type.h" +#define NVM_REQ_OK 0x00 +#define NVM_REQ_NOT_OK 0x01 +#define NVM_REQ_PENDING 0x02 +#define NVM_REQ_INTEGRITY_FAILED 0x03 +#define NVM_REQ_BLOCK_SKIPPED 0x04 +#define NVM_REQ_NV_INVALIDATED 0x05 +#define NVM_REQ_CANCELLED 0x06 +#define NVM_MULTI_BLOCK_REQUEST_ID 0 +#define NVM_REDUNDANT_BLOCK_FOR_CONFIG_ID 1 + +#else +typedef uint8 NvM_RequestResultType; /** @req NVM470 */ +#define NVM_REQ_OK 0x00 +#define NVM_REQ_NOT_OK 0x01 +#define NVM_REQ_PENDING 0x02 +#define NVM_REQ_INTEGRITY_FAILED 0x03 +#define NVM_REQ_BLOCK_SKIPPED 0x04 +#define NVM_REQ_NV_INVALIDATED 0x05 +#define NVM_REQ_CANCELLED 0x06 + +/** @req NVM471 */ +/* 0 and 1 is reserved, sequential order */ +typedef uint16 NvM_BlockIdType; + +#define NVM_MULTI_BLOCK_REQUEST_ID 0 +#define NVM_REDUNDANT_BLOCK_FOR_CONFIG_ID 1 +#endif + +#endif /* RTE_ECUM_TYPE_H_ */ diff --git a/firmware/src/DiagnosticR/rte/Rte_StbM_Type.h b/firmware/src/DiagnosticR/rte/Rte_StbM_Type.h new file mode 100644 index 0000000..e403af1 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_StbM_Type.h @@ -0,0 +1,52 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_STBM_TYPE_H_ +#define RTE_STBM_TYPE_H_ + +#ifdef USE_RTE +#warning This file should only be used when not using an RTE with StbM service component. +#include "Rte_Type.h" +#else + +/* @req 4.2.2/SWS_StbM_00239 */ +typedef uint8 StbM_TimeBaseStatusType; + + +/* @req 4.2.2/SWS_StbM_00241 */ +typedef struct{ + StbM_TimeBaseStatusType timeBaseStatus; /* Status of the Time Base */ + uint32 nanoseconds; /* Nanoseconds part of the time */ + uint32 seconds; /* 32 bit LSB of the 48 bits Seconds part of the time */ + uint16 secondsHi; /* 16 bit MSB of the 48 bits Seconds part of the time*/ +}StbM_TimeStampType; + + +/* @req 4.2.2/SWS_StbM_00242 */ +typedef struct{ + StbM_TimeBaseStatusType timeBaseStatus; /* Status of the Time Base */ + uint32 nanoseconds; /* Nanoseconds part of the time */ + uint64 seconds; /* 48 bit Seconds part of the time */ +}StbM_TimeStampExtendedType; + + +/* @req 4.2.2/SWS_StbM_00243 */ +typedef struct{ + uint8 userDataLength; /* User Data Length in bytes */ + uint8 userByte0; + uint8 userByte1; + uint8 userByte2; +}StbM_UserDataType; +#endif +#endif diff --git a/firmware/src/DiagnosticR/rte/Rte_WdgM_Type.h b/firmware/src/DiagnosticR/rte/Rte_WdgM_Type.h new file mode 100644 index 0000000..c07c635 --- /dev/null +++ b/firmware/src/DiagnosticR/rte/Rte_WdgM_Type.h @@ -0,0 +1,41 @@ +/*-------------------------------- Arctic Core ------------------------------ + * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com. + * Contact: + * + * You may ONLY use this file: + * 1)if you have a valid commercial ArcCore license and then in accordance with + * the terms contained in the written license agreement between you and ArcCore, + * or alternatively + * 2)if you follow the terms found in GNU General Public License version 2 as + * published by the Free Software Foundation and appearing in the file + * LICENSE.GPL included in the packaging of this file or here + * + *-------------------------------- Arctic Core -----------------------------*/ + +#ifndef RTE_WDGM_TYPE_H_ +#define RTE_WDGM_TYPE_H_ + +#define WDGM_NOT_SERVICE_COMPONENT +#ifdef USE_RTE +#warning This file should only be used when NOT using an EcuM Service Component. +#include "Rte_Type.h" +#else + +typedef uint8 WdgM_LocalStatusType; +typedef uint8 WdgM_GlobalStatusType; +typedef uint8 WdgM_ModeType; + + +/* NOTE: datatype depends on the maximal configured amount of supervised entities + * currently we assume that 16bit are necessary (alternative would be 8) + */ +typedef uint16 WdgM_SupervisedEntityIdType; + + +/* NOTE: datatype depends on the maximal configured amount of supervised entities + * currently we assume that 16bit are necessary (alternative would be 8) + */ +typedef uint16 WdgM_CheckpointIdType; +#endif + +#endif /* RTE_WDGM_TYPE_H_ */ diff --git a/firmware/src/FunctionState/FunctionState.c b/firmware/src/FunctionState/FunctionState.c new file mode 100644 index 0000000..4959fcd --- /dev/null +++ b/firmware/src/FunctionState/FunctionState.c @@ -0,0 +1,94 @@ +#include "FunctionState.h" +#include "plib_port.h" + +extern uint16 adc[2] ; +uint8 Fuction_State = 1 ; +uint8 Control_SDZ = 1 ; +uint16 LD_AD_Val; + + +void FunctionState_Task(void) +{ + static uint16 Into_A_count = 0; + + static uint16 Into_B_count = 0; + + static uint16 Into_C_count = 0; + + LD_AD_Val = adc[1]; + + switch(Fuction_State) + { + case Function_State_A: + Into_A_count = 0; + //if((adc[0]>649 && adc[0]<874) || (adc[0]>1777 && adc[0]<2003)) //A switch to B + if((adc[0]>581 && adc[0]<862) || (adc[0]>1788 && adc[0]<2014)) + { + Into_B_count++; + if(Into_B_count >= 800) //4000ms + { + Fuction_State = Function_State_B; + } + } + else if(adc[0]<581 || adc[0]>2014) //A switch to C + { + Into_C_count++; + if(Into_C_count >= 200) //1000ms + { + Fuction_State = Function_State_C; + } + } + break; + + + case Function_State_B: + Into_B_count = 0; + if(adc[0]>897&&adc[0]<1754) //B switch to A + { + Into_A_count++; + + + if(Into_A_count >= 100) //500ms + { + Fuction_State = Function_State_A; + } + } + else if(adc[0]<581 || adc[0]>2014) //B switch to C + { + Into_C_count++; + if(Into_C_count >= 200) //1000ms + { + Fuction_State = Function_State_C; + } + } + break; + + + case Function_State_C: + Into_C_count = 0; + if((adc[0]>614 && adc[0]<897) || (adc[0]>1754 && adc[0]<1979)) //C switch to B + { + Into_B_count++; + if(Into_B_count >= 800) //4000ms + { + Fuction_State = Function_State_B; + } + } + //else if(adc[0]>931&&adc[0]<1721) //C switch to A + else if(adc[0]>897&&adc[0]<1754) //8.25->7.95 15.25->15.55 + { + Into_A_count++; + + if(Into_A_count >= 100) //500ms + { + Fuction_State = Function_State_A; + } + } + break; + + default: + break; + + } + +} diff --git a/firmware/src/FunctionState/FunctionState.h b/firmware/src/FunctionState/FunctionState.h new file mode 100644 index 0000000..793b4b2 --- /dev/null +++ b/firmware/src/FunctionState/FunctionState.h @@ -0,0 +1,22 @@ +#ifndef __FunctionState_H__ +#define __FunctionState_H__ + +#include "Std_Types.h" + +#define Function_State_A 1 +#define Function_State_B 2 +#define Function_State_C 3 + +extern uint16 LD_AD_Val; + + +extern uint8 Fuction_State ; +extern uint8 Control_SDZ ; +extern void FunctionState_Task(void); + + + + + + +#endif \ No newline at end of file diff --git a/firmware/src/OsekCom/OsekCom.c b/firmware/src/OsekCom/OsekCom.c new file mode 100644 index 0000000..c5f6c18 --- /dev/null +++ b/firmware/src/OsekCom/OsekCom.c @@ -0,0 +1,3460 @@ + +/* -------------------------------- Includes -------------------------------- */ +#include ".\OsekCom.h" +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "Std_Types.h" +#include "DiagnosticR/FicOsek/FicOsekCom.h" +#include "RTE.h" +#include "FunctionState.h" +/* -------------------------------- Defines --------------------------------- */ +#define CAN_CALC_STD_ID(id) ((uint32_t)(id)) +/* ID in Target Process format of frames with static ID */ +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR06 (CAN_CALC_STD_ID(0x38U)) +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR05 (CAN_CALC_STD_ID(0x383U)) +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR04 (CAN_CALC_STD_ID(0x37FU)) +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR03 (CAN_CALC_STD_ID(0x37BU)) +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR02 (CAN_CALC_STD_ID(0x307U)) +#define ID_TP_FRM_SWTRPRIVATEDHUCANFR01 (CAN_CALC_STD_ID(0x309U)) +#define ID_TP_FRM_SWTRPRESSFR01 (CAN_CALC_STD_ID(0x410U)) +#define ID_TP_FRM_SWTRSENSORFR01 (CAN_CALC_STD_ID(0x411U)) +#define ID_TP_FRM_SWTRSENSORFR02 (CAN_CALC_STD_ID(0x412U)) +#define ID_TP_FRM_SWTRSENSORFR03 (CAN_CALC_STD_ID(0x413U)) +#define ID_TP_FRM_SWTRSENSORFR04 (CAN_CALC_STD_ID(0x414U)) +#define ID_TP_FRM_SWTRSENSORFR05 (CAN_CALC_STD_ID(0x415U)) +#define ID_TP_FRM_SWTRSENSORFR06 (CAN_CALC_STD_ID(0x416U)) +#define ID_TP_FRM_SWTRSENSORFR07 (CAN_CALC_STD_ID(0x417U)) +#define ID_TP_FRM_SWTRSENSORFR08 (CAN_CALC_STD_ID(0x418U)) +#define ID_TP_FRM_IHUPRIVATEDHUCANFR01 (CAN_CALC_STD_ID(0x30U)) +#define ID_TP_FRM_DIAG_PHYSRESP_SWTR (CAN_CALC_STD_ID(0x610U)) +#define ID_TP_FRM_DIAG_PHYSREQ_SWTR (CAN_CALC_STD_ID(0x710U)) +#define ID_TP_FRM_DIAG_FUNCREQ (CAN_CALC_STD_ID(0x7FFU)) +/* Max length of Tx Com frames */ +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR06 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR05 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR04 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR03 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR02 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRIVATEDHUCANFR01 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRPRESSFR01 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR01 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR02 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR03 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR04 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR05 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR06 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR07 ((uint16_t) 8) +#define MAX_LEN_FRM_SWTRSENSORFR08 ((uint16_t) 8) +#define MAX_LEN_FRM_DIAG_PHYSRESP_SWTR ((UI_16) 8) + +/* Min length of Rx frames to be able to decode each signal */ +#define MIN_LEN_FRM_SIG_TWLIBRISTS_UB ((uint16_t) 3) +#define MIN_LEN_FRM_SIG_TWLIBRISTS ((uint16_t) 3) +#define MIN_LEN_FRM_SIG_SWTOFKEYTONE_UB ((uint16_t) 1) +#define MIN_LEN_FRM_SIG_SWTOFKEYTONE ((uint16_t) 1) +#define MIN_LEN_FRM_SIG_INTRBRISTS_UB ((uint16_t) 1) +#define MIN_LEN_FRM_SIG_INTRBRISTS ((uint16_t) 1) +#define MIN_LEN_FRM_SIG_ACTVNOFSTEERWHLILLMN_UB ((uint16_t) 6) +#define MIN_LEN_FRM_SIG_ACTVNOFSTEERWHLILLMN ((uint16_t) 6) +#define MIN_LEN_FRM_SIG_DIAGNOSTICREQSWTR ((UI_16) 1) +#define MIN_LEN_FRM_SIG_DIAGNOSTICFUNCADDRREQ ((UI_16) 1) + +/* First byte of dynamic length signals */ +#define FB_SIG_DIAGNOSTICREQSWTR ((UI_8) 0) +#define FB_SIG_DIAGNOSTICFUNCADDRREQ ((UI_8) 0) +/* Maximum length of dynamic length signals */ +#define MAX_LEN_FRM_DIAG_PHYSRESP_SWTR ((UI_16) 8) +#define MAX_LEN_SIG_DIAGNOSTICRESPSWTR ((UI_16) 8) +#define MAX_LEN_SIG_DIAGNOSTICFUNCADDRREQ ((UI_8) 8) +#define MAX_LEN_SIG_DIAGNOSTICREQSWTR ((UI_8) 8) + + #define ENDIAN_BYTE(byte, alloc_size) (byte) + + + + + + + + +/* Macros of the TX_REQ flags */ +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x01)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xFE)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06() ((flag_swtr_com_tx_req0 & ((uint8_t)0x01)) == ((uint8_t) 0x01)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x02)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xFD)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02() ((flag_swtr_com_tx_req0 & ((uint8_t)0x02)) == ((uint8_t) 0x02)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x04)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xFB)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01() ((flag_swtr_com_tx_req0 & ((uint8_t)0x04)) == ((uint8_t) 0x04)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x08)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xF7)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03() ((flag_swtr_com_tx_req0 & ((uint8_t)0x08)) == ((uint8_t) 0x08)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x10)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xEF)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04() ((flag_swtr_com_tx_req0 & ((uint8_t)0x10)) == ((uint8_t) 0x10)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x20)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xDF)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05() ((flag_swtr_com_tx_req0 & ((uint8_t)0x20)) == ((uint8_t) 0x20)) + +#define SET_FLAG_TX_REQ_FRM_SWTRPRESSFR01() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x40)) +#define RST_FLAG_TX_REQ_FRM_SWTRPRESSFR01() (flag_swtr_com_tx_req0 &= ((uint8_t) 0xBF)) +#define TST_FLAG_TX_REQ_FRM_SWTRPRESSFR01() ((flag_swtr_com_tx_req0 & ((uint8_t)0x40)) == ((uint8_t) 0x40)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR01() (flag_swtr_com_tx_req0 |= ((uint8_t) 0x80)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR01() (flag_swtr_com_tx_req0 &= ((uint8_t) 0x7F)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR01() ((flag_swtr_com_tx_req0 & ((uint8_t)0x80)) == ((uint8_t) 0x80)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR02() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x01)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR02() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xFE)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR02() ((flag_swtr_com_tx_req1 & ((uint8_t)0x01)) == ((uint8_t) 0x01)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR03() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x02)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR03() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xFD)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR03() ((flag_swtr_com_tx_req1 & ((uint8_t)0x02)) == ((uint8_t) 0x02)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR04() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x04)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR04() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xFB)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR04() ((flag_swtr_com_tx_req1 & ((uint8_t)0x04)) == ((uint8_t) 0x04)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR05() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x08)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR05() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xF7)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR05() ((flag_swtr_com_tx_req1 & ((uint8_t)0x08)) == ((uint8_t) 0x08)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR06() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x10)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR06() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xEF)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR06() ((flag_swtr_com_tx_req1 & ((uint8_t)0x10)) == ((uint8_t) 0x10)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR07() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x20)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR07() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xDF)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR07() ((flag_swtr_com_tx_req1 & ((uint8_t)0x20)) == ((uint8_t) 0x20)) + +#define SET_FLAG_TX_REQ_FRM_SWTRSENSORFR08() (flag_swtr_com_tx_req1 |= ((uint8_t) 0x40)) +#define RST_FLAG_TX_REQ_FRM_SWTRSENSORFR08() (flag_swtr_com_tx_req1 &= ((uint8_t) 0xBF)) +#define TST_FLAG_TX_REQ_FRM_SWTRSENSORFR08() ((flag_swtr_com_tx_req1 & ((uint8_t)0x40)) == ((uint8_t) 0x40)) + +#define SET_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR() (flag_swtr_com_tx_req1 |= ((UI_8) 0x80)) +#define RST_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR() (flag_swtr_com_tx_req1 &= ((UI_8) 0x7F)) +#define TST_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR() ((flag_swtr_com_tx_req1 & ((UI_8)0x80)) == ((UI_8) 0x80)) + + +/* Cancel value to cancel a timer */ +#define TIMER_CANCEL ((uint16_t) 0xFFFF) + +/* Declaration of period time of the periodic or mixed Tx frames */ +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR06 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR06 ((uint32_t) (400)) +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR05 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR05 ((uint32_t) (400)) +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR04 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR04 ((uint32_t) (400)) +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR03 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR03 ((uint32_t) (400)) +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR02 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR02 ((uint32_t) (100)) +#define OT_TX_FRM_SWTRPRIVATEDHUCANFR01 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRIVATEDHUCANFR01 ((uint32_t) (100)) + +#define OT_TX_FRM_SWTRPRESSFR01 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRPRESSFR01 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR01 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR01 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR02 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR02 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR03 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR03 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR04 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR04 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR05 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR05 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR06 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR06 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR07 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR07 ((uint32_t) (50)) +#define OT_TX_FRM_SWTRSENSORFR08 ((uint32_t) (0)) +#define PT_TX_FRM_SWTRSENSORFR08 ((uint32_t) (50)) + +#define TIMER_MS_TO_TIME_RESTRICTIVE(t) ( (uint32_t) ((t)+(uint8_t)1) ) +/* Declaration of deadline monitoring values for Rx signals */ +#define TO_FRX_SIG_ACTVNOFSTEERWHLILLMN ((uint32_t) TIMER_MS_TO_TIME_RESTRICTIVE((uint16_t)200)) +#define TO_RX_SIG_ACTVNOFSTEERWHLILLMN ((uint32_t) TIMER_MS_TO_TIME_RESTRICTIVE((uint16_t)2000)) + +/* Declaration of deadline monitoring values of Tx frames */ +#define TO_TX_FRM_DIAG_PHYSRESP_SWTR ((t_timer_time) TIMER_MS_TO_TIME_RESTRICTIVE((UI_16)1)) + +/* Macros to Set notification flags */ +#define SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS() (flag_tx0 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS() (flag_tx0 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS() (flag_tx0 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS() (flag_tx0 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTR_UB() (flag_tx0 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_SWTRSERNONR4() (flag_tx0 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_SWTRSERNONR3() (flag_tx0 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_SWTRSERNONR2() (flag_tx0 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_SWTRSERNONR1() (flag_tx1 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_SWTRSERNO_UB() (flag_tx1 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR4() (flag_tx1 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR3() (flag_tx1 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR2() (flag_tx1 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR1() (flag_tx1 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN3() (flag_tx1 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN2() (flag_tx1 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN1() (flag_tx2 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_SWTRPARTNOCMPL_UB() (flag_tx2 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR5() (flag_tx2 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR4() (flag_tx2 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR3() (flag_tx2 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR2() (flag_tx2 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR1() (flag_tx2 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN3() (flag_tx2 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN2() (flag_tx3 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN1() (flag_tx3 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_SWPUPDWNSTSRI_UB() (flag_tx3 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_SWPUPDWNSTSRI() (flag_tx3 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_SWPLERISTSRI_UB() (flag_tx3 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_SWPLERISTSRI() (flag_tx3 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDVOICE_UB() (flag_tx3 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDVOICE() (flag_tx3 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDMENU_UB() (flag_tx4 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDMENU() (flag_tx4 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDDN_UB() (flag_tx4 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDDN() (flag_tx4 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_SLDVOLCTRLSTS_UB() (flag_tx4 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_SLDVOLCTRLSTS() (flag_tx4 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_RIMFCTACTSGUP_UB() (flag_tx4 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_RIMFCTACTSGUP() (flag_tx4 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_RIMFCTACTSGRI_UB() (flag_tx5 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_RIMFCTACTSGRI() (flag_tx5 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_RIMFCTACTSGLE_UB() (flag_tx5 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_RIMFCTACTSGLE() (flag_tx5 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_RIMFCTACTSGDN_UB() (flag_tx5 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_RIMFCTACTSGDN() (flag_tx5 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_RIMFCTACTSGCE_UB() (flag_tx5 |= (uint8_t) 0x40) +#define SET_FLAG_TX_SIG_RIMFCTACTSGCE() (flag_tx5 |= (uint8_t) 0x80) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRITOUCHPOSNY() (flag_tx6 |= (uint8_t) 0x01) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRITOUCHPOSNX() (flag_tx6 |= (uint8_t) 0x02) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS() (flag_tx6 |= (uint8_t) 0x04) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRICNTR() (flag_tx6 |= (uint8_t) 0x08) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRICHKS() (flag_tx6 |= (uint8_t) 0x10) +#define SET_FLAG_TX_SIG_STEERWHLTOUCHBDRI_UB() (flag_tx6 |= (uint8_t) 0x20) +#define SET_FLAG_TX_SIG_DIAGNOSTICRESPSWTR() (flag_tx6 |= (UI_8) 0x40) +#define SET_FLAG_RX_SIG_DIAGNOSTICREQSWTR() (flag_rx0 |= (UI_8) 0x01) +#define SET_FLAG_RX_SIG_DIAGNOSTICFUNCADDRREQ() (flag_rx0 |= (UI_8) 0x02) + +/* Macros of the flag of the estate of the communications */ +#define SET_FLAG_OSEK_COM_INIT() (flag_st_mode |= ((uint8_t) 0x10)) +#define RST_FLAG_OSEK_COM_INIT() (flag_st_mode &= ((uint8_t) 0xEF)) +#define TST_FLAG_OSEK_COM_INIT() ((flag_st_mode & ((uint8_t)0x10)) == ((uint8_t) 0x10)) +#define SET_FLAG_OSEK_COM_PER_TX() (flag_st_mode |= ((uint8_t) 0x20)) +#define RST_FLAG_OSEK_COM_PER_TX() (flag_st_mode &= ((uint8_t) 0xDF)) +#define TST_FLAG_OSEK_COM_PER_TX() ((flag_st_mode & ((uint8_t)0x20)) == ((uint8_t) 0x20)) + + +/* ------------------------------- Data Types ------------------------------- */ + +/* Type to allocate data structure for managed signals */ +typedef uint8_t t_alloc_sig_twlibrists_ub[1]; +typedef uint8_t t_alloc_sig_twlibrists[1]; +typedef uint8_t t_alloc_sig_swtofkeytone_ub[1]; +typedef uint8_t t_alloc_sig_swtofkeytone[1]; +typedef uint8_t t_alloc_sig_intrbrists_ub[1]; +typedef uint8_t t_alloc_sig_intrbrists[1]; +typedef uint8_t t_alloc_sig_actvnofsteerwhlillmn_ub[1]; +typedef uint8_t t_alloc_sig_actvnofsteerwhlillmn[1]; +typedef UI_8 t_alloc_sig_diagnosticreqswtr[8]; +typedef UI_8 t_alloc_sig_diagnosticfuncaddrreq[8]; + +/* ---------------------------- Global Variables ---------------------------- */ +extern uint8_t Test_frame_On; +/* Declaration of mode and state flag */ +static uint8_t flag_st_mode; + +/* Static length Rx Com signals internal objects declaration */ +static volatile t_alloc_sig_twlibrists_ub sig_twlibrists_ub; +static volatile t_alloc_sig_twlibrists sig_twlibrists; +static volatile t_alloc_sig_swtofkeytone_ub sig_swtofkeytone_ub; +static volatile t_alloc_sig_swtofkeytone sig_swtofkeytone; +static volatile t_alloc_sig_intrbrists_ub sig_intrbrists_ub; +static volatile t_alloc_sig_intrbrists sig_intrbrists; +static volatile t_alloc_sig_actvnofsteerwhlillmn_ub sig_actvnofsteerwhlillmn_ub; +static volatile t_alloc_sig_actvnofsteerwhlillmn sig_actvnofsteerwhlillmn; +static volatile t_alloc_sig_diagnosticreqswtr sig_diagnosticreqswtr; +static volatile UI_8 sig_len_diagnosticreqswtr; +static volatile t_alloc_sig_diagnosticfuncaddrreq sig_diagnosticfuncaddrreq; +static volatile UI_8 sig_len_diagnosticfuncaddrreq; + +/* Dynamic length Rx Com signals internal objects declaration */ + +/* Com Tx fames objects internal declaration */ +static uint8_t frm_swtrprivatedhucanfr06[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR06]; +static uint8_t frm_swtrprivatedhucanfr05[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR05]; +static uint8_t frm_swtrprivatedhucanfr04[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR04]; +static uint8_t frm_swtrprivatedhucanfr03[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR03]; +static uint8_t frm_swtrprivatedhucanfr02[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR02]; +static uint8_t frm_swtrprivatedhucanfr01[MAX_LEN_FRM_SWTRPRIVATEDHUCANFR01]; +static uint8_t frm_swtrpressfr01[MAX_LEN_FRM_SWTRPRESSFR01]; +static uint8_t frm_swtrsensorfr01[MAX_LEN_FRM_SWTRSENSORFR01]; +static uint8_t frm_swtrsensorfr02[MAX_LEN_FRM_SWTRSENSORFR02]; +static uint8_t frm_swtrsensorfr03[MAX_LEN_FRM_SWTRSENSORFR03]; +static uint8_t frm_swtrsensorfr04[MAX_LEN_FRM_SWTRSENSORFR04]; +static uint8_t frm_swtrsensorfr05[MAX_LEN_FRM_SWTRSENSORFR05]; +static uint8_t frm_swtrsensorfr06[MAX_LEN_FRM_SWTRSENSORFR06]; +static uint8_t frm_swtrsensorfr07[MAX_LEN_FRM_SWTRSENSORFR07]; +static uint8_t frm_swtrsensorfr08[MAX_LEN_FRM_SWTRSENSORFR08]; +UI_8 frm_diag_physresp_swtr[MAX_LEN_FRM_DIAG_PHYSRESP_SWTR]; +static UI_8 len_frm_diag_physresp_swtr; + +/* Tx request flags declaration */ +static volatile uint8_t flag_swtr_com_tx_req0; +static volatile uint8_t flag_swtr_com_tx_req1; + +/* Com traffic flags declaration */ +static volatile t_flag_value com_traffic_swtr; + +/* Declaration of the periodic timers of Tx frames */ +static uint32_t ptt_tx_frm_swtrprivatedhucanfr06; +static uint32_t ptt_tx_frm_swtrprivatedhucanfr05; +static uint32_t ptt_tx_frm_swtrprivatedhucanfr04; +static uint32_t ptt_tx_frm_swtrprivatedhucanfr03; +static uint32_t ptt_tx_frm_swtrprivatedhucanfr02; +static uint32_t ptt_tx_frm_swtrprivatedhucanfr01; +static uint32_t ptt_tx_frm_swtrpressfr01; +static uint32_t ptt_tx_frm_swtrsensorfr01; +static uint32_t ptt_tx_frm_swtrsensorfr02; +static uint32_t ptt_tx_frm_swtrsensorfr03; +static uint32_t ptt_tx_frm_swtrsensorfr04; +static uint32_t ptt_tx_frm_swtrsensorfr05; +static uint32_t ptt_tx_frm_swtrsensorfr06; +static uint32_t ptt_tx_frm_swtrsensorfr07; +static uint32_t ptt_tx_frm_swtrsensorfr08; +static volatile t_timer_time dmt_tx_frm_diag_physresp_swtr; +/* Declaration of deadline monitoring timers of Rx signals */ +static volatile uint32_t dmt_rx_sig_actvnofsteerwhlillmn; + +/* Declaration of class 2 (TxNotif) notification flags */ +static volatile uint8_t flag_tx0; +static volatile uint8_t flag_tx1; +static volatile uint8_t flag_tx2; +static volatile uint8_t flag_tx3; +static volatile uint8_t flag_tx4; +static volatile uint8_t flag_tx5; +static volatile uint8_t flag_tx6; +static volatile uint8_t flag_tx7; +uint8_t flag_rx0; +/* Declaration of timer diff between last tick and current tick */ +static uint32_t time_diff; + + + +/* --------------------------- Routine Prototypes --------------------------- */ +static void OsekComPeriodicTx(void); +static void OsekComDeadlineMonitRx(void); +//static void OsekComTxReqFrmSwtrPrivateDHUCanFr01(void); +static void OsekComTxReqFrmDIAG_PhysResp_SWTR(void); +/* -------------------------------- Routines -------------------------------- */ +uint32_t CanBufQueryIdTp(void); +uint8_t CanBufQueryDataByte(uint8_t hdl, uint8_t index); +#define CAN_BUF_QUERY_DATA_BYTE(bhdl, byte) (CanBufQueryDataByte(bhdl, byte)) +#define CAN_BUF_QUERY_DATA_LEN(HwCtl, bhdl) (CanBufQueryDataLen(HwCtl, bhdl)) +UI_8 CanBufQueryDataLen(t_can_handler can_handler, t_can_buf_hdl bhdl); +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reception of a new frame notification callback +| * This callback must be launched by the lower COM driver upon the reception +| of a new frame. +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the received frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComRxNotifCallbackSWTR(t_com_buf_hdl bhdl) +{ + t_flag_value aux_com_traffic = COM_TRUE; + uint32_t buf_idtp = CanBufQueryIdTp(); + uint8_t frm_len = 8; + + if (TST_FLAG_OSEK_COM_INIT()) { + /* Rx Com frames with static ID */ + switch (buf_idtp) { + case ID_TP_FRM_IHUPRIVATEDHUCANFR01: + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_TWLIBRISTS_UB) { + /* Decoding of signal sig_TwliBriSts_UB */ + sig_twlibrists_ub[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,2)) >> ((uint8_t)7)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_TWLIBRISTS) { + /* Decoding of signal sig_TwliBriSts */ + sig_twlibrists[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,2) & ((uint8_t)127)) >> ((uint8_t)6)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_SWTOFKEYTONE_UB) { + /* Decoding of signal sig_SwtOfKeyTone_UB */ + sig_swtofkeytone_ub[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,0) & ((uint8_t)63)) >> ((uint8_t)5)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_SWTOFKEYTONE) { + /* Decoding of signal sig_SwtOfKeyTone */ + sig_swtofkeytone[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,0)) >> ((uint8_t)6)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_INTRBRISTS_UB) { + /* Decoding of signal sig_IntrBriSts_UB */ + sig_intrbrists_ub[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,0) & ((uint8_t)31)) >> ((uint8_t)4)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_INTRBRISTS) { + /* Decoding of signal sig_IntrBriSts */ + sig_intrbrists[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,0) & ((uint8_t)15))); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_ACTVNOFSTEERWHLILLMN_UB) { + /* Decoding of signal sig_ActvnOfSteerWhlIllmn_UB */ + sig_actvnofsteerwhlillmn_ub[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,5) & ((uint8_t)7)) >> ((uint8_t)2)); + } + else { + /* Do nothing */ + } + + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_ACTVNOFSTEERWHLILLMN) { + /* Reset of the deadline monitoring timer */ + dmt_rx_sig_actvnofsteerwhlillmn = 0; + /* Decoding of signal sig_ActvnOfSteerWhlIllmn */ + sig_actvnofsteerwhlillmn[0] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,5) & ((uint8_t)15)) >> ((uint8_t)3)); + /* Rx notification callback */ + IhuPrivateDHUCanFr01_CALLBACK(); + } + else { + /* Do nothing */ + } + + break; + case ID_TP_FRM_DIAG_PHYSREQ_SWTR: + /* Test of the minimum Rx frames length required to decode the signal */ + + + if (frm_len >= MIN_LEN_FRM_SIG_DIAGNOSTICREQSWTR) { + /* Decoding of signal sig_DiagnosticReqSWTR */ + sig_diagnosticreqswtr[0] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,0)); + sig_diagnosticreqswtr[1] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,1)); + sig_diagnosticreqswtr[2] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,2)); + sig_diagnosticreqswtr[3] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,3)); + sig_diagnosticreqswtr[4] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,4)); + sig_diagnosticreqswtr[5] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,5)); + sig_diagnosticreqswtr[6] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,6)); + sig_diagnosticreqswtr[7] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,7))); + /* Length calculation of signal sig_DiagnosticReqPRNDL */ + sig_len_diagnosticreqswtr = frm_len - FB_SIG_DIAGNOSTICREQSWTR; + + /* Set of the Rx notification flag */ + SET_FLAG_RX_SIG_DIAGNOSTICREQSWTR(); + } + else { + /* Do nothing */ + } + break; + case ID_TP_FRM_DIAG_FUNCREQ: + /* Test of the minimum Rx frames length required to decode the signal */ + if (frm_len >= MIN_LEN_FRM_SIG_DIAGNOSTICFUNCADDRREQ) { + /* Decoding of signal sig_DiagnosticFuncAddrReq */ + sig_diagnosticfuncaddrreq[0] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,0)); + sig_diagnosticfuncaddrreq[1] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,1)); + sig_diagnosticfuncaddrreq[2] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,2)); + sig_diagnosticfuncaddrreq[3] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,3)); + sig_diagnosticfuncaddrreq[4] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,4)); + sig_diagnosticfuncaddrreq[5] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,5)); + sig_diagnosticfuncaddrreq[6] = (CAN_BUF_QUERY_DATA_BYTE(bhdl,6)); + sig_diagnosticfuncaddrreq[7] = ((CAN_BUF_QUERY_DATA_BYTE(bhdl,7))); + /* Length calculation of signal sig_DiagnosticFuncAddrReq */ + sig_len_diagnosticfuncaddrreq = frm_len - FB_SIG_DIAGNOSTICFUNCADDRREQ; + /* Set of the Rx notification flag */ + SET_FLAG_RX_SIG_DIAGNOSTICFUNCADDRREQ(); + } + else { + /* Do nothing */ + } + + break; + default: + /* Reset com traffic flag */ + aux_com_traffic = COM_FALSE; + break; + } + } + else { + /* Do nothing */ + } + /* Com traffic flag */ + if ((com_traffic_swtr == COM_FALSE) && (aux_com_traffic == COM_TRUE)) { + com_traffic_swtr = COM_TRUE; + } +} + +void CanTx(t_can_handler can_handler, bool notif, uint32_t idtp, uint16_t len, t_can_data can_data); +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Available transmission buffer notification callback +| * This callback must be launched by the lower COM driver upon a transmission +| buffer will become available after requesting one to perform a transmission. +|--------------------------------------------------------------------------- +| Parameters description: +| return: TRUE in case that after current transmission lower COM driver should +| call again this callback to transmit a new frame. +| FALSE otherwise. +/---------------------------------------------------------------------------*/ +bool OsekComTxReqCallbackSWTR(void) +{ + /* Check of the Tx request flag */ + if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06()) { + /* Transmission of the frame SwtrPrivateDHUCanFr06*/ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR06, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR06, frm_swtrprivatedhucanfr06); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02()) { + /* Transmission of the frame SwtrPrivateDHUCanFr02 */ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR02, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR02, frm_swtrprivatedhucanfr02); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01()) { + /* Transmission of the frame SwtrPrivateDHUCanFr01 */ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR01, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR01, frm_swtrprivatedhucanfr01); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03()) { + /* Transmission of the frame SwtrPrivateDHUCanFr03 */ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR03, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR03, frm_swtrprivatedhucanfr03); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04()) { + /* Transmission of the frame SwtrPrivateDHUCanFr04 */ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR04, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR04, frm_swtrprivatedhucanfr04); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05()) { + /* Transmission of the frame SwtrPrivateDHUCanFr05 */ + if(Fuction_State != Function_State_C) + { + CanTx(0, true, ID_TP_FRM_SWTRPRIVATEDHUCANFR05, MAX_LEN_FRM_SWTRPRIVATEDHUCANFR05, frm_swtrprivatedhucanfr05); + } + RST_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRPRESSFR01()) { + /* Transmission of the frame SwtrPressFr01 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRPRESSFR01, MAX_LEN_FRM_SWTRPRESSFR01, frm_swtrpressfr01); + } + RST_FLAG_TX_REQ_FRM_SWTRPRESSFR01(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR01()) { + /* Transmission of the frame SwtRSensorFr01 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR01, MAX_LEN_FRM_SWTRSENSORFR01, frm_swtrsensorfr01); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR01(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR02()) { + /* Transmission of the frame SwtRSensorFr02 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR02, MAX_LEN_FRM_SWTRSENSORFR02, frm_swtrsensorfr02); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR02(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR03()) { + /* Transmission of the frame SwtRSensorFr03 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR03, MAX_LEN_FRM_SWTRSENSORFR03, frm_swtrsensorfr03); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR03(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR04()) { + /* Transmission of the frame SwtRSensorFr04 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR04, MAX_LEN_FRM_SWTRSENSORFR04, frm_swtrsensorfr04); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR04(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR05()) { + /* Transmission of the frame SwtRSensorFr05 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR05, MAX_LEN_FRM_SWTRSENSORFR05, frm_swtrsensorfr05); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR05(); + } + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR06()) { + /* Transmission of the frame SwtRSensorFr06 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR06, MAX_LEN_FRM_SWTRSENSORFR06, frm_swtrsensorfr06); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR06(); + } + + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR08()) { + /* Transmission of the frame SwtRSensorFr08 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR08, MAX_LEN_FRM_SWTRSENSORFR08, frm_swtrsensorfr08); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR08(); + Fr08_send_flag=1; + } + + else if (TST_FLAG_TX_REQ_FRM_SWTRSENSORFR07()) { + /* Transmission of the frame SwtRSensorFr07 */ + if(Fuction_State != Function_State_C) + { + if(Test_frame_On == 1) + CanTx(0, true, ID_TP_FRM_SWTRSENSORFR07, MAX_LEN_FRM_SWTRSENSORFR07, frm_swtrsensorfr07); + } + RST_FLAG_TX_REQ_FRM_SWTRSENSORFR07(); + } + + else if(TST_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR()) + { + /* Transmission of the frame DIAG_PHYSRESP_SWTR */ + CanTx(0, true, ID_TP_FRM_DIAG_PHYSRESP_SWTR, MAX_LEN_FRM_DIAG_PHYSRESP_SWTR, frm_diag_physresp_swtr); + RST_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR(); + } + else { + /* Do nothing */ + } + + /* return checking pending transmissions */ + return (((flag_swtr_com_tx_req0 != 0) || (flag_swtr_com_tx_req1 != 0)) ? true : false); +} + +uint32_t CanBufQueryIdTp_Tx(void); +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Frame transmission confirmation notifying callback +| * This callback must be launched by the lower COM driver upon the completion +| of a frame transmission for which transmission confirmation has been requested +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the transmitted frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComTxNotifCallbackSWTR(t_com_buf_hdl bhdl) +{ + //uint32_t buf_idtp = CanBufQueryIdTp_Tx(); + uint32_t buf_idtp = CanBufQueryIdTp(); + buf_idtp = ID_TP_FRM_DIAG_PHYSREQ_SWTR; + switch (buf_idtp) { + + case ID_TP_FRM_SWTRPRIVATEDHUCANFR06: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_DIAGCFAILRTOUCHPANSWTR_UB(); + break; + case ID_TP_FRM_SWTRPRIVATEDHUCANFR05: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRSERNONR4(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRSERNONR3(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRSERNONR2(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRSERNONR1(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRSERNO_UB(); + break; + case ID_TP_FRM_SWTRPRIVATEDHUCANFR04: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR4(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR3(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR2(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLNR1(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN3(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN2(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPLENDSGN1(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNOCMPL_UB(); + break; + case ID_TP_FRM_SWTRPRIVATEDHUCANFR03: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR5(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR4(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR3(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR2(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLNR1(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN3(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN2(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWTRPARTNO10CMPLENDSGN1(); + break; + case ID_TP_FRM_SWTRPRIVATEDHUCANFR02: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWPUPDWNSTSRI_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWPUPDWNSTSRI(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWPLERISTSRI_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SWPLERISTSRI(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDVOICE_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDVOICE(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDMENU_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDMENU(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDDN_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDDN(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SLDVOLCTRLSTS_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_SLDVOLCTRLSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGUP_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGUP(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGRI_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGRI(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGLE_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGLE(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGDN_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGDN(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGCE_UB(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_RIMFCTACTSGCE(); + break; +case ID_TP_FRM_SWTRPRIVATEDHUCANFR01: + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRITOUCHPOSNY(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRITOUCHPOSNX(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRICNTR(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRICHKS(); + /* Set of Tx the notification flag */ + SET_FLAG_TX_SIG_STEERWHLTOUCHBDRI_UB(); + break; + case ID_TP_FRM_DIAG_PHYSREQ_SWTR:// //ID_TP_FRM_DIAG_PHYSRESP_SWTR ID_TP_FRM_DIAG_FUNCREQ + case ID_TP_FRM_DIAG_FUNCREQ: + SET_FLAG_TX_SIG_DIAGNOSTICRESPSWTR(); + break; + default: + /* Do nothing */ + break; + } +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to initialize OsekCom stack +| +| ------------------------------------------------- -------------------------- +| Parameters description: +| app_mode: OsekCom initialization mode (See t_com_application_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StartCom(t_com_application_mode_type app_mode) +{ + uint16_t ind; + uint8_t aux[8]; + const t_application_data_ref aux_ref = &aux; + + /* Get current timer tick */ + + + /* Buffer initialization */ + for(ind=0; ind < (uint16_t)8; ind++){ + aux[ind]=(uint8_t)0; + } + /* Register of the COM mode */ + flag_st_mode = app_mode & (uint8_t)0x0F; + + /* Set of the active communications flags */ + SET_FLAG_OSEK_COM_INIT(); + + /* Signals initialization to zero */ + for(ind=(uint16_t)0;inddata_ref< with +| the data stored in the internal stack for the object identified by >message<. +| * This service will reset the class 1 (RxNotif) and 3 (RxErrorNotif) flags +| associated to >message< +| * If >message< is an enqueued signal the service will return the data +| stored in the internal stack (initial value / last received value / last value +| set with InitMessage) +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not supported) +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be retrieved. +| data_ref: Pointer to a variable where to store the requested signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent, dynamic length or zero-length +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the queue of the signal identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type ReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref) +{ + t_status_type status=E_OK; + + /* Mutual exclusive access begin */ + //SuspendAllInterrupts(); + switch (message) { + case SIG_TWLIBRISTS_UB: + ((uint8_t *)data_ref)[0]=sig_twlibrists_ub[0]; + break; + case SIG_TWLIBRISTS: + ((uint8_t *)data_ref)[0]=sig_twlibrists[0]; + break; + case SIG_SWTOFKEYTONE_UB: + ((uint8_t *)data_ref)[0]=sig_swtofkeytone_ub[0]; + break; + case SIG_SWTOFKEYTONE: + ((uint8_t *)data_ref)[0]=sig_swtofkeytone[0]; + break; + case SIG_INTRBRISTS_UB: + ((uint8_t *)data_ref)[0]=sig_intrbrists_ub[0]; + break; + case SIG_INTRBRISTS: + ((uint8_t *)data_ref)[0]=sig_intrbrists[0]; + break; + case SIG_ACTVNOFSTEERWHLILLMN_UB: + ((uint8_t *)data_ref)[0]=sig_actvnofsteerwhlillmn_ub[0]; + break; + case SIG_ACTVNOFSTEERWHLILLMN: + ((uint8_t *)data_ref)[0]=sig_actvnofsteerwhlillmn[0]; + break; + default: + status=E_COM_ID; + break; + } + /* Mutual exclusive access end */ + //ResumeAllInterrupts(); + return status; +} + +t_status_type ReceiveDynamicMessage(t_symbolic_name message, + t_application_data_ref data_ref, + t_length_ref length_ref) +{ + t_status_type status=E_OK; + + /* Mutual exclusive access begin */ + // SuspendAllInterrupts(); + switch (message) { + case SIG_DIAGNOSTICREQSWTR: + ((UI_8 *)data_ref)[0]=sig_diagnosticreqswtr[0]; + ((UI_8 *)data_ref)[1]=sig_diagnosticreqswtr[1]; + ((UI_8 *)data_ref)[2]=sig_diagnosticreqswtr[2]; + ((UI_8 *)data_ref)[3]=sig_diagnosticreqswtr[3]; + ((UI_8 *)data_ref)[4]=sig_diagnosticreqswtr[4]; + ((UI_8 *)data_ref)[5]=sig_diagnosticreqswtr[5]; + ((UI_8 *)data_ref)[6]=sig_diagnosticreqswtr[6]; + ((UI_8 *)data_ref)[7]=sig_diagnosticreqswtr[7]; + *((UI_8 *)length_ref) = sig_len_diagnosticreqswtr; + /* Reset class 1 (RxNotif) flag */ + ResetFlagRxSigDiagnosticReqSWTR(); + break; + case SIG_DIAGNOSTICFUNCADDRREQ: + ((UI_8 *)data_ref)[0]=sig_diagnosticfuncaddrreq[0]; + ((UI_8 *)data_ref)[1]=sig_diagnosticfuncaddrreq[1]; + ((UI_8 *)data_ref)[2]=sig_diagnosticfuncaddrreq[2]; + ((UI_8 *)data_ref)[3]=sig_diagnosticfuncaddrreq[3]; + ((UI_8 *)data_ref)[4]=sig_diagnosticfuncaddrreq[4]; + ((UI_8 *)data_ref)[5]=sig_diagnosticfuncaddrreq[5]; + ((UI_8 *)data_ref)[6]=sig_diagnosticfuncaddrreq[6]; + ((UI_8 *)data_ref)[7]=sig_diagnosticfuncaddrreq[7]; + *((UI_8 *)length_ref) = sig_len_diagnosticfuncaddrreq; + /* Reset class 1 (RxNotif) flag */ + ResetFlagRxSigDiagnosticFuncAddrReq(); + break; + default: + status=E_COM_ID; + break; + } + /* Mutual exclusive access end */ + // ResumeAllInterrupts(); + return status; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< parameter. +| * This service will reset the class 2 (TxNotif) and 4 (TxErrorNotif) flags +| associated to >message< +| * If >message< has the Triggered Transfer Property, the update will be +| followed by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode. +| In this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| triggered by the usage of this service. +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| transmitted signal type. +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| (void)SendMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be transmitted. +| data_ref: Pointer to a variable containing the data to be transmitted. +| return: +| E_OK in case of no errors +| E_COM_ID is case the parameter >message< is out of range or if it refers +| to a message that is received or to a dynamic-length or +| zero-length message. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type SendMessage(t_symbolic_name message, + t_application_data_ref data_ref) +{ + t_status_type status; + t_symbolic_name aux_msg = message & (~NODE_ID_MASK); + + /* Case when FicOsek is initialized */ + if (TST_FLAG_OSEK_COM_INIT()) { + /* Case when message is not out of the range */ + if ((aux_msg >= FIRST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME) && + (aux_msg <= LAST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME)) { + /* Mutual exclusive access begin */ + // SuspendAllInterrupts(); + /* Set of message data */ + status=InitMessage(message,data_ref); + /* Switch for signals with Tx or TxError flags to reset */ + switch (message) { + case SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTR_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigDiagcFailrTouchPanSWTR_UB(); + break; + case SIG_SWTRSERNONR4: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRSerNoNr4(); + break; + case SIG_SWTRSERNONR3: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRSerNoNr3(); + break; + case SIG_SWTRSERNONR2: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRSerNoNr2(); + break; + case SIG_SWTRSERNONR1: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRSerNoNr1(); + break; + case SIG_SWTRSERNO_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRSerNo_UB(); + break; + case SIG_SWTRPARTNOCMPLNR4: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplNr4(); + break; + case SIG_SWTRPARTNOCMPLNR3: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplNr3(); + break; + case SIG_SWTRPARTNOCMPLNR2: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplNr2(); + break; + case SIG_SWTRPARTNOCMPLNR1: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplNr1(); + break; + case SIG_SWTRPARTNOCMPLENDSGN3: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplEndSgn3(); + break; + case SIG_SWTRPARTNOCMPLENDSGN2: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplEndSgn2(); + break; + case SIG_SWTRPARTNOCMPLENDSGN1: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmplEndSgn1(); + break; + case SIG_SWTRPARTNOCMPL_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNoCmpl_UB(); + break; + case SIG_SWTRPARTNO10CMPLNR5: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplNr5(); + break; + case SIG_SWTRPARTNO10CMPLNR4: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplNr4(); + break; + case SIG_SWTRPARTNO10CMPLNR3: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplNr3(); + break; + case SIG_SWTRPARTNO10CMPLNR2: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplNr2(); + break; + case SIG_SWTRPARTNO10CMPLNR1: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplNr1(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN3: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplEndSgn3(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN2: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplEndSgn2(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN1: + /* Reset Tx notification flag */ + ResetFlagTxSigSWTRPartNo10CmplEndSgn1(); + break; + case SIG_SWPUPDWNSTSRI_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSwpUpDwnStsRi_UB(); + break; + case SIG_SWPUPDWNSTSRI: + /* Reset Tx notification flag */ + ResetFlagTxSigSwpUpDwnStsRi(); + break; + case SIG_SWPLERISTSRI_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSwpLeRiStsRi_UB(); + break; + case SIG_SWPLERISTSRI: + /* Reset Tx notification flag */ + ResetFlagTxSigSwpLeRiStsRi(); + break; + case SIG_STEERWHLTOUCHBDVOICE_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdVoice_UB(); + break; + case SIG_STEERWHLTOUCHBDVOICE: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdVoice(); + break; + case SIG_STEERWHLTOUCHBDMENU_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdMenu_UB(); + break; + case SIG_STEERWHLTOUCHBDMENU: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdMenu(); + break; + case SIG_STEERWHLTOUCHBDDN_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdDn_UB(); + break; + case SIG_STEERWHLTOUCHBDDN: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdDn(); + break; + case SIG_SLDVOLCTRLSTS_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSldVolCtrlSts_UB(); + break; + case SIG_SLDVOLCTRLSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigSldVolCtrlSts(); + break; + case SIG_RIMFCTACTSGUP_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgUp_UB(); + break; + case SIG_RIMFCTACTSGUP: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgUp(); + break; + case SIG_RIMFCTACTSGRI_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgRi_UB(); + break; + case SIG_RIMFCTACTSGRI: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgRi(); + break; + case SIG_RIMFCTACTSGLE_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgLe_UB(); + break; + case SIG_RIMFCTACTSGLE: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgLe(); + break; + case SIG_RIMFCTACTSGDN_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgDn_UB(); + break; + case SIG_RIMFCTACTSGDN: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgDn(); + break; + case SIG_RIMFCTACTSGCE_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgCe_UB(); + break; + case SIG_RIMFCTACTSGCE: + /* Reset Tx notification flag */ + ResetFlagTxSigRiMFctActSgCe(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNY: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRiTouchPosnY(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNX: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRiTouchPosnX(); + break; + case SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(); + break; + case SIG_STEERWHLTOUCHBDRICNTR: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRiCntr(); + break; + case SIG_STEERWHLTOUCHBDRICHKS: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRiChks(); + break; + case SIG_STEERWHLTOUCHBDRI_UB: + /* Reset Tx notification flag */ + ResetFlagTxSigSteerWhlTouchBdRi_UB(); + break; + case SIG_DIAGNOSTICRESPSWTR: + ResetFlagTxSigDiagnosticRespSWTR(); + break; + default: + /* Do nothing */ + break; + } + /* Mutual exclusive access end */ + // ResumeAllInterrupts(); + } + /* Case when message is out of the range */ + else { + status=E_COM_ID; + } + } + /* Case when FicOsek is not initialized */ + else { + status=E_COM_SYS_NOINIT; + } + return status; +} + +t_status_type SendDynamicMessage(t_symbolic_name message, + t_application_data_ref data_ref, + t_length_ref length_ref) +{ + t_status_type status; + t_symbolic_name aux_msg = message & (~NODE_ID_MASK); + /* Case when FicOsek is initialized */ + if (TST_FLAG_OSEK_COM_INIT()) { + /* Case when message is not out of the range */ + if ((aux_msg >= FIRST_TX_DYN_LEN_SIGNAL_SYMBOLIC_NAME) && + (aux_msg <= LAST_TX_DYN_LEN_SIGNAL_SYMBOLIC_NAME)) { + /* Mutual exclusive access begin */ + // SuspendAllInterrupts(); + /* Set of signal data */ + status=InitMessage(message,data_ref); + /* Switch for signals */ + switch (message) { + case SIG_DIAGNOSTICRESPSWTR: + /* Set of signal length */ + len_frm_diag_physresp_swtr = MAX_LEN_FRM_DIAG_PHYSRESP_SWTR - MAX_LEN_SIG_DIAGNOSTICRESPSWTR + (*((UI_8 *)length_ref)); + /* Reset class 2 (TxNotif) flag */ + ResetFlagTxSigDiagnosticRespSWTR(); + /* Reset class 4 (TxErrorNotif) flag */ + // ResetFlagTxErrorSigDiagnosticRespSWTR(); + break; + default: + /* Do nothing */ + break; + } + /* Mutual exclusive access end */ + //ResumeAllInterrupts(); + /* Switch for triggered signal of direct or mixed frames */ + switch (message) { + case SIG_DIAGNOSTICRESPSWTR: + /* Trigger event to initiate the transmission of the frame */ + OsekComTxReqFrmDIAG_PhysResp_SWTR(); + break; + default: + /* Do nothing */ + break; + } + } + /* Case when message is out of the range */ + else { + status=E_COM_ID; + } + } + /* Case when FicOsek is not initialized */ + else { + status=E_COM_SYS_NOINIT; + } + return status; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< +| * This service will not reset any class flags associated to >message< +| * This service will not initiate any transmission. +| * The user is responsible of granting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| data_ref: Pointer to a variable containing the data. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type InitMessage(t_symbolic_name message, + t_application_data_ref data_ref) +{ + t_status_type status=E_OK; + + /* Mutual exclusive access begin */ + //SuspendAllInterrupts(); + switch (message) { + case SIG_TWLIBRISTS_UB: + /* Initialization of signal sig_TwliBriSts_UB */ + sig_twlibrists_ub[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_TWLIBRISTS: + /* Initialization of signal sig_TwliBriSts */ + sig_twlibrists[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_SWTOFKEYTONE_UB: + /* Initialization of signal sig_SwtOfKeyTone_UB */ + sig_swtofkeytone_ub[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_SWTOFKEYTONE: + /* Initialization of signal sig_SwtOfKeyTone */ + sig_swtofkeytone[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_INTRBRISTS_UB: + /* Initialization of signal sig_IntrBriSts_UB */ + sig_intrbrists_ub[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_INTRBRISTS: + /* Initialization of signal sig_IntrBriSts */ + sig_intrbrists[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_ACTVNOFSTEERWHLILLMN_UB: + /* Initialization of signal sig_ActvnOfSteerWhlIllmn_UB */ + sig_actvnofsteerwhlillmn_ub[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_ACTVNOFSTEERWHLILLMN: + /* Initialization of signal sig_ActvnOfSteerWhlIllmn */ + sig_actvnofsteerwhlillmn[0]=((uint8_t *)data_ref)[0]; + break; + case SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS: + /* Initial codification of the signal sig_DiagcFailrTouchPanSWTRVibrationFltSts */ + frm_swtrprivatedhucanfr06[0] &= (((uint8_t)0xFF) - (((uint8_t)3))); + frm_swtrprivatedhucanfr06[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3))); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS: + /* Initial codification of the signal sig_DiagcFailrTouchPanSWTRTouchdFltSts */ + frm_swtrprivatedhucanfr06[0] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)2))); + frm_swtrprivatedhucanfr06[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)2)); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS: + /* Initial codification of the signal sig_DiagcFailrTouchPanSWTRSnsrFltSts */ + frm_swtrprivatedhucanfr06[0] &= (((uint8_t)0xFF) - (((uint8_t)7) << ((uint8_t)4))); + frm_swtrprivatedhucanfr06[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)7)) << ((uint8_t)4)); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS: + /* Initial codification of the signal sig_DiagcFailrTouchPanSWTRCmnFltSts */ + frm_swtrprivatedhucanfr06[0] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)7))); + frm_swtrprivatedhucanfr06[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)7)); + break; + case SIG_DIAGCFAILRTOUCHPANSWTR_UB: + /* Initial codification of the signal sig_DiagcFailrTouchPanSWTR_UB */ + frm_swtrprivatedhucanfr06[1] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)7))); + frm_swtrprivatedhucanfr06[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)7)); + break; + case SIG_SWTRSERNONR4: + /* Initial codification of the signal sig_SWTRSerNoNr4 */ + frm_swtrprivatedhucanfr05[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr05[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRSERNONR3: + /* Initial codification of the signal sig_SWTRSerNoNr3 */ + frm_swtrprivatedhucanfr05[2] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr05[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRSERNONR2: + /* Initial codification of the signal sig_SWTRSerNoNr2 */ + frm_swtrprivatedhucanfr05[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr05[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRSERNONR1: + /* Initial codification of the signal sig_SWTRSerNoNr1 */ + frm_swtrprivatedhucanfr05[0] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr05[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRSERNO_UB: + /* Initial codification of the signal sig_SWTRSerNo_UB */ + frm_swtrprivatedhucanfr05[4] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)7))); + frm_swtrprivatedhucanfr05[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)7)); + break; + case SIG_SWTRPARTNOCMPLNR4: + /* Initial codification of the signal sig_SWTRPartNoCmplNr4 */ + frm_swtrprivatedhucanfr04[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLNR3: + /* Initial codification of the signal sig_SWTRPartNoCmplNr3 */ + frm_swtrprivatedhucanfr04[2] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLNR2: + /* Initial codification of the signal sig_SWTRPartNoCmplNr2 */ + frm_swtrprivatedhucanfr04[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLNR1: + /* Initial codification of the signal sig_SWTRPartNoCmplNr1 */ + frm_swtrprivatedhucanfr04[0] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLENDSGN3: + /* Initial codification of the signal sig_SWTRPartNoCmplEndSgn3 */ + frm_swtrprivatedhucanfr04[6] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[6] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLENDSGN2: + /* Initial codification of the signal sig_SWTRPartNoCmplEndSgn2 */ + frm_swtrprivatedhucanfr04[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[5] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPLENDSGN1: + /* Initial codification of the signal sig_SWTRPartNoCmplEndSgn1 */ + frm_swtrprivatedhucanfr04[4] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr04[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNOCMPL_UB: + /* Initial codification of the signal sig_SWTRPartNoCmpl_UB */ + frm_swtrprivatedhucanfr04[7] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)7))); + frm_swtrprivatedhucanfr04[7] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)7)); + break; + case SIG_SWTRPARTNO10CMPLNR5: + /* Initial codification of the signal sig_SWTRPartNo10CmplNr5 */ + frm_swtrprivatedhucanfr03[4] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLNR4: + /* Initial codification of the signal sig_SWTRPartNo10CmplNr4 */ + frm_swtrprivatedhucanfr03[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLNR3: + /* Initial codification of the signal sig_SWTRPartNo10CmplNr3 */ + frm_swtrprivatedhucanfr03[2] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLNR2: + /* Initial codification of the signal sig_SWTRPartNo10CmplNr2 */ + frm_swtrprivatedhucanfr03[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLNR1: + /* Initial codification of the signal sig_SWTRPartNo10CmplNr1 */ + frm_swtrprivatedhucanfr03[0] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLENDSGN3: + /* Initial codification of the signal sig_SWTRPartNo10CmplEndSgn3 */ + frm_swtrprivatedhucanfr03[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[7] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLENDSGN2: + /* Initial codification of the signal sig_SWTRPartNo10CmplEndSgn2 */ + frm_swtrprivatedhucanfr03[6] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[6] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWTRPARTNO10CMPLENDSGN1: + /* Initial codification of the signal sig_SWTRPartNo10CmplEndSgn1 */ + frm_swtrprivatedhucanfr03[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr03[5] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_SWPUPDWNSTSRI_UB: + /* Initial codification of the signal sig_SwpUpDwnStsRi_UB */ + frm_swtrprivatedhucanfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)1))); + frm_swtrprivatedhucanfr02[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1))); + break; + case SIG_SWPUPDWNSTSRI: + /* Initial codification of the signal sig_SwpUpDwnStsRi */ + frm_swtrprivatedhucanfr02[4] &= (((uint8_t)0xFF) - (((uint8_t)7) << ((uint8_t)1))); + frm_swtrprivatedhucanfr02[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)7)) << ((uint8_t)1)); + break; + case SIG_SWPLERISTSRI_UB: + /* Initial codification of the signal sig_SwpLeRiStsRi_UB */ + frm_swtrprivatedhucanfr02[4] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)4))); + frm_swtrprivatedhucanfr02[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)4)); + break; + case SIG_SWPLERISTSRI: + /* Initial codification of the signal sig_SwpLeRiStsRi */ + frm_swtrprivatedhucanfr02[4] &= (((uint8_t)0xFF) - (((uint8_t)7) << ((uint8_t)5))); + frm_swtrprivatedhucanfr02[4] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)7)) << ((uint8_t)5)); + break; + case SIG_STEERWHLTOUCHBDVOICE_UB: + /* Initial codification of the signal sig_SteerWhlTouchBdVoice_UB */ + frm_swtrprivatedhucanfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)5))); + frm_swtrprivatedhucanfr02[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)5)); + break; + case SIG_STEERWHLTOUCHBDVOICE: + /* Initial codification of the signal sig_SteerWhlTouchBdVoice */ + frm_swtrprivatedhucanfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)6))); + frm_swtrprivatedhucanfr02[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)6)); + break; + case SIG_STEERWHLTOUCHBDMENU_UB: + /* Initial codification of the signal sig_SteerWhlTouchBdMenu_UB */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)1))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)1)); + break; + case SIG_STEERWHLTOUCHBDMENU: + /* Initial codification of the signal sig_SteerWhlTouchBdMenu */ + frm_swtrprivatedhucanfr02[2] &= (((uint8_t)0xFF) - (((uint8_t)3))); + frm_swtrprivatedhucanfr02[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3))); + break; + case SIG_STEERWHLTOUCHBDDN_UB: + /* Initial codification of the signal sig_SteerWhlTouchBdDn_UB */ + frm_swtrprivatedhucanfr02[2] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)4))); + frm_swtrprivatedhucanfr02[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)4)); + break; + case SIG_STEERWHLTOUCHBDDN: + /* Initial codification of the signal sig_SteerWhlTouchBdDn */ + frm_swtrprivatedhucanfr02[2] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)2))); + frm_swtrprivatedhucanfr02[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)2)); + break; + case SIG_SLDVOLCTRLSTS_UB: + /* Initial codification of the signal sig_SldVolCtrlSts_UB */ + frm_swtrprivatedhucanfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)1))); + frm_swtrprivatedhucanfr02[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)1)); + break; + case SIG_SLDVOLCTRLSTS: + /* Initial codification of the signal sig_SldVolCtrlSts */ + frm_swtrprivatedhucanfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)7) << ((uint8_t)2))); + frm_swtrprivatedhucanfr02[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)7)) << ((uint8_t)2)); + break; + case SIG_RIMFCTACTSGUP_UB: + /* Initial codification of the signal sig_RiMFctActSgUp_UB */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)2))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)2)); + break; + case SIG_RIMFCTACTSGUP: + /* Initial codification of the signal sig_RiMFctActSgUp */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)3))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)3)); + break; + case SIG_RIMFCTACTSGRI_UB: + /* Initial codification of the signal sig_RiMFctActSgRi_UB */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)5))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)5)); + break; + case SIG_RIMFCTACTSGRI: + /* Initial codification of the signal sig_RiMFctActSgRi */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)6))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)6)); + break; + case SIG_RIMFCTACTSGLE_UB: + /* Initial codification of the signal sig_RiMFctActSgLe_UB */ + frm_swtrprivatedhucanfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)1))); + frm_swtrprivatedhucanfr02[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1))); + break; + case SIG_RIMFCTACTSGLE: + /* Initial codification of the signal sig_RiMFctActSgLe */ + frm_swtrprivatedhucanfr02[0] &= (((uint8_t)0xFF) - (((uint8_t)3))); + frm_swtrprivatedhucanfr02[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3))); + break; + case SIG_RIMFCTACTSGDN_UB: + /* Initial codification of the signal sig_RiMFctActSgDn_UB */ + frm_swtrprivatedhucanfr02[0] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)2))); + frm_swtrprivatedhucanfr02[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)2)); + break; + case SIG_RIMFCTACTSGDN: + /* Initial codification of the signal sig_RiMFctActSgDn */ + frm_swtrprivatedhucanfr02[0] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)3))); + frm_swtrprivatedhucanfr02[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)3)); + break; + case SIG_RIMFCTACTSGCE_UB: + /* Initial codification of the signal sig_RiMFctActSgCe_UB */ + frm_swtrprivatedhucanfr02[0] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)5))); + frm_swtrprivatedhucanfr02[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)5)); + break; + case SIG_RIMFCTACTSGCE: + /* Initial codification of the signal sig_RiMFctActSgCe */ + frm_swtrprivatedhucanfr02[0] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)6))); + frm_swtrprivatedhucanfr02[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)6)); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNY: + /* Initial codification of the signal sig_SteerWhlTouchBdRiTouchPosnY */ + frm_swtrprivatedhucanfr01[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr01[3] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNX: + /* Initial codification of the signal sig_SteerWhlTouchBdRiTouchPosnX */ + frm_swtrprivatedhucanfr01[2] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr01[2] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS: + /* Initial codification of the signal sig_SteerWhlTouchBdRiSteerWhlTouchBdSts */ + frm_swtrprivatedhucanfr01[0] &= (((uint8_t)0xFF) - (((uint8_t)3) << ((uint8_t)4))); + frm_swtrprivatedhucanfr01[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)3)) << ((uint8_t)4)); + break; + case SIG_STEERWHLTOUCHBDRICNTR: + /* Initial codification of the signal sig_SteerWhlTouchBdRiCntr */ + frm_swtrprivatedhucanfr01[0] &= (((uint8_t)0xFF) - (((uint8_t)15))); + frm_swtrprivatedhucanfr01[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)15))); + break; + case SIG_STEERWHLTOUCHBDRICHKS: + /* Initial codification of the signal sig_SteerWhlTouchBdRiChks */ + frm_swtrprivatedhucanfr01[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrprivatedhucanfr01[1] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)255))); + break; + case SIG_STEERWHLTOUCHBDRI_UB: + /* Initial codification of the signal sig_SteerWhlTouchBdRi_UB */ + frm_swtrprivatedhucanfr01[0] &= (((uint8_t)0xFF) - (((uint8_t)1) << ((uint8_t)6))); + frm_swtrprivatedhucanfr01[0] |= ((((uint8_t *)data_ref)[0] & ((uint8_t)1)) << ((uint8_t)6)); + break; + case SIG_SWTRPRESSBASELINE: + /* Initial codification of the signal sig_SwtrPressBaseline */ + frm_swtrpressfr01[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrpressfr01[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrpressfr01[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrpressfr01[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRPRESSSIGNAL: + /* Initial codification of the signal sig_SwtrPressSignal */ + frm_swtrpressfr01[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrpressfr01[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrpressfr01[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrpressfr01[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR1_BASELINE: + /* Initial codification of the signal sig_SwtRsensor1_baseline */ + frm_swtrsensorfr01[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr01[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr01[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr01[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR1_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor1_signal */ + frm_swtrsensorfr01[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr01[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr01[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr01[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR2_BASELINE: + /* Initial codification of the signal sig_SwtRsensor2_baseline */ + frm_swtrsensorfr01[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr01[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr01[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr01[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR2_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor2_signal */ + frm_swtrsensorfr01[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr01[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr01[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr01[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR3_BASELINE: + /* Initial codification of the signal sig_SwtRsensor3_baseline */ + frm_swtrsensorfr02[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr02[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr02[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr02[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR4_BASELINE: + /* Initial codification of the signal sig_SwtRsensor4_baseline */ + frm_swtrsensorfr02[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr02[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr02[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr02[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR3_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor3_signal */ + frm_swtrsensorfr02[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr02[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr02[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr02[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR4_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor4_signal */ + frm_swtrsensorfr02[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr02[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr02[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr02[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR5_BASELINE: + /* Initial codification of the signal sig_SwtRsensor5_baseline */ + frm_swtrsensorfr03[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr03[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr03[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr03[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR6_BASELINE: + /* Initial codification of the signal sig_SwtRsensor6_baseline */ + frm_swtrsensorfr03[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr03[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr03[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr03[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR5_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor5_signal */ + frm_swtrsensorfr03[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr03[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr03[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr03[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR6_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor6_signal */ + frm_swtrsensorfr03[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr03[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr03[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr03[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR7_BASELINE: + /* Initial codification of the signal sig_SwtRsensor7_baseline */ + frm_swtrsensorfr04[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr04[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr04[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr04[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR8_BASELINE: + /* Initial codification of the signal sig_SwtRsensor8_baseline */ + frm_swtrsensorfr04[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr04[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr04[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr04[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR7_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor7_signal */ + frm_swtrsensorfr04[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr04[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr04[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr04[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR8_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor8_signal */ + frm_swtrsensorfr04[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr04[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr04[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr04[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR9_BASELINE: + /* Initial codification of the signal sig_SwtRsensor9_baseline */ + frm_swtrsensorfr05[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr05[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr05[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr05[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR10_BASELINE: + /* Initial codification of the signal sig_SwtRsensor10_baseline */ + frm_swtrsensorfr05[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr05[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr05[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr05[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR9_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor9_signal */ + frm_swtrsensorfr05[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr05[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr05[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr05[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR10_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor10_signal */ + frm_swtrsensorfr05[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr05[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr05[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr05[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR11_BASELINE: + /* Initial codification of the signal sig_SwtRsensor11_baseline */ + frm_swtrsensorfr06[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr06[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr06[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr06[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR12_BASELINE: + /* Initial codification of the signal sig_SwtRsensor12_baseline */ + frm_swtrsensorfr06[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr06[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr06[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr06[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR11_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor11_signal */ + frm_swtrsensorfr06[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr06[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr06[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr06[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR12_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor12_signal */ + frm_swtrsensorfr06[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr06[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr06[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr06[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR13_BASELINE: + /* Initial codification of the signal sig_SwtRsensor13_baseline */ + frm_swtrsensorfr07[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr07[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr07[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr07[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR14_BASELINE: + /* Initial codification of the signal sig_SwtRsensor14_baseline */ + frm_swtrsensorfr07[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr07[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr07[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr07[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR13_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor13_signal */ + frm_swtrsensorfr07[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr07[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr07[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr07[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR14_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor14_signal */ + frm_swtrsensorfr07[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr07[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr07[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr07[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR15_BASELINE: + /* Initial codification of the signal sig_SwtRsensor15_baseline */ + frm_swtrsensorfr08[1] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr08[1] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr08[0] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr08[0] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR16_BASELINE: + /* Initial codification of the signal sig_SwtRsensor16_baseline */ + frm_swtrsensorfr08[3] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr08[3] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr08[2] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr08[2] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR15_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor15_signal */ + frm_swtrsensorfr08[5] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr08[5] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr08[4] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr08[4] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_SWTRSENSOR16_SIGNAL: + /* Initial codification of the signal sig_SwtRSensor16_signal */ + frm_swtrsensorfr08[7] &= (((uint8_t)0xFF) - (((uint8_t)255))); + frm_swtrsensorfr08[7] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(1,2)] & ((uint8_t)255))); + frm_swtrsensorfr08[6] &= ((uint8_t)0xFF) - ((uint8_t)255); + frm_swtrsensorfr08[6] |= ((((uint8_t *)data_ref)[ENDIAN_BYTE(0,2)] & ((uint8_t)255))); + break; + case SIG_DIAGNOSTICREQSWTR: + /* Initialization of signal sig_DiagnosticReqSWTR */ + sig_diagnosticreqswtr[0]=((UI_8 *)data_ref)[0]; + sig_diagnosticreqswtr[1]=((UI_8 *)data_ref)[1]; + sig_diagnosticreqswtr[2]=((UI_8 *)data_ref)[2]; + sig_diagnosticreqswtr[3]=((UI_8 *)data_ref)[3]; + sig_diagnosticreqswtr[4]=((UI_8 *)data_ref)[4]; + sig_diagnosticreqswtr[5]=((UI_8 *)data_ref)[5]; + sig_diagnosticreqswtr[6]=((UI_8 *)data_ref)[6]; + sig_diagnosticreqswtr[7]=((UI_8 *)data_ref)[7]; + sig_len_diagnosticreqswtr=MAX_LEN_SIG_DIAGNOSTICREQSWTR; + break; + case SIG_DIAGNOSTICFUNCADDRREQ: + /* Initialization of signal sig_DiagnosticFuncAddrReq */ + sig_diagnosticfuncaddrreq[0]=((UI_8 *)data_ref)[0]; + sig_diagnosticfuncaddrreq[1]=((UI_8 *)data_ref)[1]; + sig_diagnosticfuncaddrreq[2]=((UI_8 *)data_ref)[2]; + sig_diagnosticfuncaddrreq[3]=((UI_8 *)data_ref)[3]; + sig_diagnosticfuncaddrreq[4]=((UI_8 *)data_ref)[4]; + sig_diagnosticfuncaddrreq[5]=((UI_8 *)data_ref)[5]; + sig_diagnosticfuncaddrreq[6]=((UI_8 *)data_ref)[6]; + sig_diagnosticfuncaddrreq[7]=((UI_8 *)data_ref)[7]; + sig_len_diagnosticfuncaddrreq=MAX_LEN_SIG_DIAGNOSTICFUNCADDRREQ; + break; + case SIG_DIAGNOSTICRESPSWTR: + /* Initial codification of the signal sig_DiagnosticRespSWTR */ + frm_diag_physresp_swtr[0] &= (((UI_8)0xFF) - (((UI_8)255))); + frm_diag_physresp_swtr[0] |= ((((UI_8 *)data_ref)[0] & ((UI_8)255))); + frm_diag_physresp_swtr[1] = ((UI_8)0); + frm_diag_physresp_swtr[1] |= (((UI_8 *)data_ref)[1]); + frm_diag_physresp_swtr[2] = ((UI_8)0); + frm_diag_physresp_swtr[2] |= (((UI_8 *)data_ref)[2]); + frm_diag_physresp_swtr[3] = ((UI_8)0); + frm_diag_physresp_swtr[3] |= (((UI_8 *)data_ref)[3]); + frm_diag_physresp_swtr[4] = ((UI_8)0); + frm_diag_physresp_swtr[4] |= (((UI_8 *)data_ref)[4]); + frm_diag_physresp_swtr[5] = ((UI_8)0); + frm_diag_physresp_swtr[5] |= (((UI_8 *)data_ref)[5]); + frm_diag_physresp_swtr[6] = ((UI_8)0); + frm_diag_physresp_swtr[6] |= (((UI_8 *)data_ref)[6]); + frm_diag_physresp_swtr[7] &= ((UI_8)0xFF) - ((UI_8)255); + frm_diag_physresp_swtr[7] |= ((((UI_8 *)data_ref)[7] & ((UI_8)255))); + /* Set of signal length */ + len_frm_diag_physresp_swtr = MAX_LEN_FRM_DIAG_PHYSRESP_SWTR; + break; + default: + status=E_COM_ID; + break; + } + /* Mutual exclusive access end */ + //ResumeAllInterrupts(); + return status; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if has not been detected any communication activity since +| last clear +| COM_TRUE if has been detected communication activity since last clear +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagComTrafficSWTR(void) +{ + return com_traffic_swtr; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void ResetFlagComTrafficSWTR(void) +{ + com_traffic_swtr = COM_FALSE; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to retrieve the state of class 1 (RxNotif), +| class 3 (Rx_ErrorNotif), class 2 (TxNotif) and class 4 (Tx_ErrorNotif) flags +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagTxSig(t_symbolic_name message) +{ + t_flag_value result; + switch (message) { + case SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS: + result = ReadFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS: + result = ReadFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS: + result = ReadFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS: + result = ReadFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTR_UB: + result = ReadFlagTxSigDiagcFailrTouchPanSWTR_UB(); + break; + case SIG_SWTRSERNONR4: + result = ReadFlagTxSigSWTRSerNoNr4(); + break; + case SIG_SWTRSERNONR3: + result = ReadFlagTxSigSWTRSerNoNr3(); + break; + case SIG_SWTRSERNONR2: + result = ReadFlagTxSigSWTRSerNoNr2(); + break; + case SIG_SWTRSERNONR1: + result = ReadFlagTxSigSWTRSerNoNr1(); + break; + case SIG_SWTRSERNO_UB: + result = ReadFlagTxSigSWTRSerNo_UB(); + break; + case SIG_SWTRPARTNOCMPLNR4: + result = ReadFlagTxSigSWTRPartNoCmplNr4(); + break; + case SIG_SWTRPARTNOCMPLNR3: + result = ReadFlagTxSigSWTRPartNoCmplNr3(); + break; + case SIG_SWTRPARTNOCMPLNR2: + result = ReadFlagTxSigSWTRPartNoCmplNr2(); + break; + case SIG_SWTRPARTNOCMPLNR1: + result = ReadFlagTxSigSWTRPartNoCmplNr1(); + break; + case SIG_SWTRPARTNOCMPLENDSGN3: + result = ReadFlagTxSigSWTRPartNoCmplEndSgn3(); + break; + case SIG_SWTRPARTNOCMPLENDSGN2: + result = ReadFlagTxSigSWTRPartNoCmplEndSgn2(); + break; + case SIG_SWTRPARTNOCMPLENDSGN1: + result = ReadFlagTxSigSWTRPartNoCmplEndSgn1(); + break; + case SIG_SWTRPARTNOCMPL_UB: + result = ReadFlagTxSigSWTRPartNoCmpl_UB(); + break; + case SIG_SWTRPARTNO10CMPLNR5: + result = ReadFlagTxSigSWTRPartNo10CmplNr5(); + break; + case SIG_SWTRPARTNO10CMPLNR4: + result = ReadFlagTxSigSWTRPartNo10CmplNr4(); + break; + case SIG_SWTRPARTNO10CMPLNR3: + result = ReadFlagTxSigSWTRPartNo10CmplNr3(); + break; + case SIG_SWTRPARTNO10CMPLNR2: + result = ReadFlagTxSigSWTRPartNo10CmplNr2(); + break; + case SIG_SWTRPARTNO10CMPLNR1: + result = ReadFlagTxSigSWTRPartNo10CmplNr1(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN3: + result = ReadFlagTxSigSWTRPartNo10CmplEndSgn3(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN2: + result = ReadFlagTxSigSWTRPartNo10CmplEndSgn2(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN1: + result = ReadFlagTxSigSWTRPartNo10CmplEndSgn1(); + break; + case SIG_SWPUPDWNSTSRI_UB: + result = ReadFlagTxSigSwpUpDwnStsRi_UB(); + break; + case SIG_SWPUPDWNSTSRI: + result = ReadFlagTxSigSwpUpDwnStsRi(); + break; + case SIG_SWPLERISTSRI_UB: + result = ReadFlagTxSigSwpLeRiStsRi_UB(); + break; + case SIG_SWPLERISTSRI: + result = ReadFlagTxSigSwpLeRiStsRi(); + break; + case SIG_STEERWHLTOUCHBDVOICE_UB: + result = ReadFlagTxSigSteerWhlTouchBdVoice_UB(); + break; + case SIG_STEERWHLTOUCHBDVOICE: + result = ReadFlagTxSigSteerWhlTouchBdVoice(); + break; + case SIG_STEERWHLTOUCHBDMENU_UB: + result = ReadFlagTxSigSteerWhlTouchBdMenu_UB(); + break; + case SIG_STEERWHLTOUCHBDMENU: + result = ReadFlagTxSigSteerWhlTouchBdMenu(); + break; + case SIG_STEERWHLTOUCHBDDN_UB: + result = ReadFlagTxSigSteerWhlTouchBdDn_UB(); + break; + case SIG_STEERWHLTOUCHBDDN: + result = ReadFlagTxSigSteerWhlTouchBdDn(); + break; + case SIG_SLDVOLCTRLSTS_UB: + result = ReadFlagTxSigSldVolCtrlSts_UB(); + break; + case SIG_SLDVOLCTRLSTS: + result = ReadFlagTxSigSldVolCtrlSts(); + break; + case SIG_RIMFCTACTSGUP_UB: + result = ReadFlagTxSigRiMFctActSgUp_UB(); + break; + case SIG_RIMFCTACTSGUP: + result = ReadFlagTxSigRiMFctActSgUp(); + break; + case SIG_RIMFCTACTSGRI_UB: + result = ReadFlagTxSigRiMFctActSgRi_UB(); + break; + case SIG_RIMFCTACTSGRI: + result = ReadFlagTxSigRiMFctActSgRi(); + break; + case SIG_RIMFCTACTSGLE_UB: + result = ReadFlagTxSigRiMFctActSgLe_UB(); + break; + case SIG_RIMFCTACTSGLE: + result = ReadFlagTxSigRiMFctActSgLe(); + break; + case SIG_RIMFCTACTSGDN_UB: + result = ReadFlagTxSigRiMFctActSgDn_UB(); + break; + case SIG_RIMFCTACTSGDN: + result = ReadFlagTxSigRiMFctActSgDn(); + break; + case SIG_RIMFCTACTSGCE_UB: + result = ReadFlagTxSigRiMFctActSgCe_UB(); + break; + case SIG_RIMFCTACTSGCE: + result = ReadFlagTxSigRiMFctActSgCe(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNY: + result = ReadFlagTxSigSteerWhlTouchBdRiTouchPosnY(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNX: + result = ReadFlagTxSigSteerWhlTouchBdRiTouchPosnX(); + break; + case SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS: + result = ReadFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(); + break; + case SIG_STEERWHLTOUCHBDRICNTR: + result = ReadFlagTxSigSteerWhlTouchBdRiCntr(); + break; + case SIG_STEERWHLTOUCHBDRICHKS: + result = ReadFlagTxSigSteerWhlTouchBdRiChks(); + break; + case SIG_STEERWHLTOUCHBDRI_UB: + result = ReadFlagTxSigSteerWhlTouchBdRi_UB(); + break; + case SIG_DIAGNOSTICRESPSWTR: + result = ReadFlagTxSigDiagnosticRespSWTR(); + break; + default: + result = COM_FALSE; + break; + } + return result; +} + +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(void) +{ + return (((flag_tx0 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(void) +{ + return (((flag_tx0 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(void) +{ + return (((flag_tx0 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(void) +{ + return (((flag_tx0 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTR_UB(void) +{ + return (((flag_tx0 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRSerNoNr4(void) +{ + return (((flag_tx0 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRSerNoNr3(void) +{ + return (((flag_tx0 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRSerNoNr2(void) +{ + return (((flag_tx0 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRSerNoNr1(void) +{ + return (((flag_tx1 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRSerNo_UB(void) +{ + return (((flag_tx1 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr4(void) +{ + return (((flag_tx1 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr3(void) +{ + return (((flag_tx1 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr2(void) +{ + return (((flag_tx1 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr1(void) +{ + return (((flag_tx1 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn3(void) +{ + return (((flag_tx1 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn2(void) +{ + return (((flag_tx1 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn1(void) +{ + return (((flag_tx2 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNoCmpl_UB(void) +{ + return (((flag_tx2 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr5(void) +{ + return (((flag_tx2 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr4(void) +{ + return (((flag_tx2 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr3(void) +{ + return (((flag_tx2 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr2(void) +{ + return (((flag_tx2 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr1(void) +{ + return (((flag_tx2 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn3(void) +{ + return (((flag_tx2 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn2(void) +{ + return (((flag_tx3 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn1(void) +{ + return (((flag_tx3 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSwpUpDwnStsRi_UB(void) +{ + return (((flag_tx3 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSwpUpDwnStsRi(void) +{ + return (((flag_tx3 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSwpLeRiStsRi_UB(void) +{ + return (((flag_tx3 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSwpLeRiStsRi(void) +{ + return (((flag_tx3 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdVoice_UB(void) +{ + return (((flag_tx3 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdVoice(void) +{ + return (((flag_tx3 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdMenu_UB(void) +{ + return (((flag_tx4 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdMenu(void) +{ + return (((flag_tx4 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdDn_UB(void) +{ + return (((flag_tx4 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdDn(void) +{ + return (((flag_tx4 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSldVolCtrlSts_UB(void) +{ + return (((flag_tx4 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSldVolCtrlSts(void) +{ + return (((flag_tx4 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgUp_UB(void) +{ + return (((flag_tx4 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgUp(void) +{ + return (((flag_tx4 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgRi_UB(void) +{ + return (((flag_tx5 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgRi(void) +{ + return (((flag_tx5 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgLe_UB(void) +{ + return (((flag_tx5 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgLe(void) +{ + return (((flag_tx5 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgDn_UB(void) +{ + return (((flag_tx5 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgDn(void) +{ + return (((flag_tx5 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgCe_UB(void) +{ + return (((flag_tx5 & ((uint8_t) 0x40)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigRiMFctActSgCe(void) +{ + return (((flag_tx5 & ((uint8_t) 0x80)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiTouchPosnY(void) +{ + return (((flag_tx6 & ((uint8_t) 0x01)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiTouchPosnX(void) +{ + return (((flag_tx6 & ((uint8_t) 0x02)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(void) +{ + return (((flag_tx6 & ((uint8_t) 0x04)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiCntr(void) +{ + return (((flag_tx6 & ((uint8_t) 0x08)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiChks(void) +{ + return (((flag_tx6 & ((uint8_t) 0x10)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigSteerWhlTouchBdRi_UB(void) +{ + return (((flag_tx6 & ((uint8_t) 0x20)) > ((uint8_t) 0)) ? COM_TRUE : COM_FALSE); +} + +t_flag_value ReadFlagTxSigDiagnosticRespSWTR(void) +{ + return (((flag_tx6 & ((UI_8) 0x40)) > ((UI_8) 0)) ? COM_TRUE : COM_FALSE); +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to retrieve the state of class 1 (RxNotif), +| class 3 (Rx_ErrorNotif), class 2 (TxNotif) and class 4 (Tx_ErrorNotif) flags +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagRxSig(t_symbolic_name message) +{ + t_flag_value result; + switch (message) + { + case SIG_DIAGNOSTICREQSWTR: + result = ReadFlagRxSigDiagnosticReqSWTR(); + break; + case SIG_DIAGNOSTICFUNCADDRREQ: + result = ReadFlagRxSigDiagnosticFuncAddrReq(); + break; + default: + result = COM_FALSE; + break; + } + return result; +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the notify class 1 (RxNotif) class 3 (RxErrorNotif) +| class 2 (TxNotif) and class 4 (TxErrorNotif) +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +/---------------------------------------------------------------------------*/ +void ResetFlagTxSig(t_symbolic_name message) +{ + switch (message) { + case SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS: + ResetFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS: + ResetFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS: + ResetFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS: + ResetFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(); + break; + case SIG_DIAGCFAILRTOUCHPANSWTR_UB: + ResetFlagTxSigDiagcFailrTouchPanSWTR_UB(); + break; + case SIG_SWTRSERNONR4: + ResetFlagTxSigSWTRSerNoNr4(); + break; + case SIG_SWTRSERNONR3: + ResetFlagTxSigSWTRSerNoNr3(); + break; + case SIG_SWTRSERNONR2: + ResetFlagTxSigSWTRSerNoNr2(); + break; + case SIG_SWTRSERNONR1: + ResetFlagTxSigSWTRSerNoNr1(); + break; + case SIG_SWTRSERNO_UB: + ResetFlagTxSigSWTRSerNo_UB(); + break; + case SIG_SWTRPARTNOCMPLNR4: + ResetFlagTxSigSWTRPartNoCmplNr4(); + break; + case SIG_SWTRPARTNOCMPLNR3: + ResetFlagTxSigSWTRPartNoCmplNr3(); + break; + case SIG_SWTRPARTNOCMPLNR2: + ResetFlagTxSigSWTRPartNoCmplNr2(); + break; + case SIG_SWTRPARTNOCMPLNR1: + ResetFlagTxSigSWTRPartNoCmplNr1(); + break; + case SIG_SWTRPARTNOCMPLENDSGN3: + ResetFlagTxSigSWTRPartNoCmplEndSgn3(); + break; + case SIG_SWTRPARTNOCMPLENDSGN2: + ResetFlagTxSigSWTRPartNoCmplEndSgn2(); + break; + case SIG_SWTRPARTNOCMPLENDSGN1: + ResetFlagTxSigSWTRPartNoCmplEndSgn1(); + break; + case SIG_SWTRPARTNOCMPL_UB: + ResetFlagTxSigSWTRPartNoCmpl_UB(); + break; + case SIG_SWTRPARTNO10CMPLNR5: + ResetFlagTxSigSWTRPartNo10CmplNr5(); + break; + case SIG_SWTRPARTNO10CMPLNR4: + ResetFlagTxSigSWTRPartNo10CmplNr4(); + break; + case SIG_SWTRPARTNO10CMPLNR3: + ResetFlagTxSigSWTRPartNo10CmplNr3(); + break; + case SIG_SWTRPARTNO10CMPLNR2: + ResetFlagTxSigSWTRPartNo10CmplNr2(); + break; + case SIG_SWTRPARTNO10CMPLNR1: + ResetFlagTxSigSWTRPartNo10CmplNr1(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN3: + ResetFlagTxSigSWTRPartNo10CmplEndSgn3(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN2: + ResetFlagTxSigSWTRPartNo10CmplEndSgn2(); + break; + case SIG_SWTRPARTNO10CMPLENDSGN1: + ResetFlagTxSigSWTRPartNo10CmplEndSgn1(); + break; + case SIG_SWPUPDWNSTSRI_UB: + ResetFlagTxSigSwpUpDwnStsRi_UB(); + break; + case SIG_SWPUPDWNSTSRI: + ResetFlagTxSigSwpUpDwnStsRi(); + break; + case SIG_SWPLERISTSRI_UB: + ResetFlagTxSigSwpLeRiStsRi_UB(); + break; + case SIG_SWPLERISTSRI: + ResetFlagTxSigSwpLeRiStsRi(); + break; + case SIG_STEERWHLTOUCHBDVOICE_UB: + ResetFlagTxSigSteerWhlTouchBdVoice_UB(); + break; + case SIG_STEERWHLTOUCHBDVOICE: + ResetFlagTxSigSteerWhlTouchBdVoice(); + break; + case SIG_STEERWHLTOUCHBDMENU_UB: + ResetFlagTxSigSteerWhlTouchBdMenu_UB(); + break; + case SIG_STEERWHLTOUCHBDMENU: + ResetFlagTxSigSteerWhlTouchBdMenu(); + break; + case SIG_STEERWHLTOUCHBDDN_UB: + ResetFlagTxSigSteerWhlTouchBdDn_UB(); + break; + case SIG_STEERWHLTOUCHBDDN: + ResetFlagTxSigSteerWhlTouchBdDn(); + break; + case SIG_SLDVOLCTRLSTS_UB: + ResetFlagTxSigSldVolCtrlSts_UB(); + break; + case SIG_SLDVOLCTRLSTS: + ResetFlagTxSigSldVolCtrlSts(); + break; + case SIG_RIMFCTACTSGUP_UB: + ResetFlagTxSigRiMFctActSgUp_UB(); + break; + case SIG_RIMFCTACTSGUP: + ResetFlagTxSigRiMFctActSgUp(); + break; + case SIG_RIMFCTACTSGRI_UB: + ResetFlagTxSigRiMFctActSgRi_UB(); + break; + case SIG_RIMFCTACTSGRI: + ResetFlagTxSigRiMFctActSgRi(); + break; + case SIG_RIMFCTACTSGLE_UB: + ResetFlagTxSigRiMFctActSgLe_UB(); + break; + case SIG_RIMFCTACTSGLE: + ResetFlagTxSigRiMFctActSgLe(); + break; + case SIG_RIMFCTACTSGDN_UB: + ResetFlagTxSigRiMFctActSgDn_UB(); + break; + case SIG_RIMFCTACTSGDN: + ResetFlagTxSigRiMFctActSgDn(); + break; + case SIG_RIMFCTACTSGCE_UB: + ResetFlagTxSigRiMFctActSgCe_UB(); + break; + case SIG_RIMFCTACTSGCE: + ResetFlagTxSigRiMFctActSgCe(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNY: + ResetFlagTxSigSteerWhlTouchBdRiTouchPosnY(); + break; + case SIG_STEERWHLTOUCHBDRITOUCHPOSNX: + ResetFlagTxSigSteerWhlTouchBdRiTouchPosnX(); + break; + case SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS: + ResetFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(); + break; + case SIG_STEERWHLTOUCHBDRICNTR: + ResetFlagTxSigSteerWhlTouchBdRiCntr(); + break; + case SIG_STEERWHLTOUCHBDRICHKS: + ResetFlagTxSigSteerWhlTouchBdRiChks(); + break; + case SIG_STEERWHLTOUCHBDRI_UB: + ResetFlagTxSigSteerWhlTouchBdRi_UB(); + break; + case SIG_DIAGNOSTICRESPSWTR: + ResetFlagTxSigDiagnosticRespSWTR(); + break; + default: + /* Do nothing */ + break; + } +} + +void ResetFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(void) +{ + flag_tx0 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(void) +{ + flag_tx0 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(void) +{ + flag_tx0 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(void) +{ + flag_tx0 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigDiagcFailrTouchPanSWTR_UB(void) +{ + flag_tx0 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSWTRSerNoNr4(void) +{ + flag_tx0 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigSWTRSerNoNr3(void) +{ + flag_tx0 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigSWTRSerNoNr2(void) +{ + flag_tx0 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigSWTRSerNoNr1(void) +{ + flag_tx1 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigSWTRSerNo_UB(void) +{ + flag_tx1 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigSWTRPartNoCmplNr4(void) +{ + flag_tx1 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigSWTRPartNoCmplNr3(void) +{ + flag_tx1 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigSWTRPartNoCmplNr2(void) +{ + flag_tx1 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSWTRPartNoCmplNr1(void) +{ + flag_tx1 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigSWTRPartNoCmplEndSgn3(void) +{ + flag_tx1 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigSWTRPartNoCmplEndSgn2(void) +{ + flag_tx1 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigSWTRPartNoCmplEndSgn1(void) +{ + flag_tx2 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigSWTRPartNoCmpl_UB(void) +{ + flag_tx2 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigSWTRPartNo10CmplNr5(void) +{ + flag_tx2 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigSWTRPartNo10CmplNr4(void) +{ + flag_tx2 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigSWTRPartNo10CmplNr3(void) +{ + flag_tx2 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSWTRPartNo10CmplNr2(void) +{ + flag_tx2 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigSWTRPartNo10CmplNr1(void) +{ + flag_tx2 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigSWTRPartNo10CmplEndSgn3(void) +{ + flag_tx2 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigSWTRPartNo10CmplEndSgn2(void) +{ + flag_tx3 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigSWTRPartNo10CmplEndSgn1(void) +{ + flag_tx3 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigSwpUpDwnStsRi_UB(void) +{ + flag_tx3 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigSwpUpDwnStsRi(void) +{ + flag_tx3 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigSwpLeRiStsRi_UB(void) +{ + flag_tx3 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSwpLeRiStsRi(void) +{ + flag_tx3 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigSteerWhlTouchBdVoice_UB(void) +{ + flag_tx3 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigSteerWhlTouchBdVoice(void) +{ + flag_tx3 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigSteerWhlTouchBdMenu_UB(void) +{ + flag_tx4 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigSteerWhlTouchBdMenu(void) +{ + flag_tx4 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigSteerWhlTouchBdDn_UB(void) +{ + flag_tx4 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigSteerWhlTouchBdDn(void) +{ + flag_tx4 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigSldVolCtrlSts_UB(void) +{ + flag_tx4 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSldVolCtrlSts(void) +{ + flag_tx4 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigRiMFctActSgUp_UB(void) +{ + flag_tx4 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigRiMFctActSgUp(void) +{ + flag_tx4 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigRiMFctActSgRi_UB(void) +{ + flag_tx5 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigRiMFctActSgRi(void) +{ + flag_tx5 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigRiMFctActSgLe_UB(void) +{ + flag_tx5 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigRiMFctActSgLe(void) +{ + flag_tx5 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigRiMFctActSgDn_UB(void) +{ + flag_tx5 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigRiMFctActSgDn(void) +{ + flag_tx5 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigRiMFctActSgCe_UB(void) +{ + flag_tx5 &= ((uint8_t) 0xBF); +} + +void ResetFlagTxSigRiMFctActSgCe(void) +{ + flag_tx5 &= ((uint8_t) 0x7F); +} + +void ResetFlagTxSigSteerWhlTouchBdRiTouchPosnY(void) +{ + flag_tx6 &= ((uint8_t) 0xFE); +} + +void ResetFlagTxSigSteerWhlTouchBdRiTouchPosnX(void) +{ + flag_tx6 &= ((uint8_t) 0xFD); +} + +void ResetFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(void) +{ + flag_tx6 &= ((uint8_t) 0xFB); +} + +void ResetFlagTxSigSteerWhlTouchBdRiCntr(void) +{ + flag_tx6 &= ((uint8_t) 0xF7); +} + +void ResetFlagTxSigSteerWhlTouchBdRiChks(void) +{ + flag_tx6 &= ((uint8_t) 0xEF); +} + +void ResetFlagTxSigSteerWhlTouchBdRi_UB(void) +{ + flag_tx6 &= ((uint8_t) 0xDF); +} + +void ResetFlagTxSigDiagnosticRespSWTR(void) +{ + flag_tx6 &= ((UI_8) 0xBF); +} + +t_flag_value ReadFlagRxSigDiagnosticReqSWTR(void) +{ + return (((flag_rx0 & ((UI_8) 0x01)) > ((UI_8) 0)) ? COM_TRUE : COM_FALSE); +} +t_flag_value ReadFlagRxSigDiagnosticFuncAddrReq(void) +{ + return (((flag_rx0 & ((UI_8) 0x02)) > ((UI_8) 0)) ? COM_TRUE : COM_FALSE); +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the notify class 1 (RxNotif) class 3 (RxErrorNotif) +| class 2 (TxNotif) and class 4 (TxErrorNotif) +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +/---------------------------------------------------------------------------*/ +void ResetFlagRxSig(t_symbolic_name message) +{ + switch (message) { + + case SIG_DIAGNOSTICREQSWTR: + ResetFlagRxSigDiagnosticReqSWTR(); + break; + case SIG_DIAGNOSTICFUNCADDRREQ: + ResetFlagRxSigDiagnosticFuncAddrReq(); + break; + default: + /* Do nothing */ + break; + } +} + + +void ResetFlagRxSigDiagnosticReqSWTR(void) +{ + flag_rx0 &= ((UI_8) 0xFE); +} + +void ResetFlagRxSigDiagnosticFuncAddrReq(void) +{ + flag_rx0 &= ((UI_8) 0xFD); +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Main runnable of the OsekCom stack intended to be called periodically by +| the system scheduler with a period equal to FICOSEK_COM_TASK_TICKS +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void OsekComTask(void) +{ + if (TST_FLAG_OSEK_COM_INIT()) { + /* Get timer difference since last task execution */ + time_diff = FICOSEK_COM_TASK_TICKS; + + OsekComDeadlineMonitRx(); + OsekComPeriodicTx(); + } +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Runnable responsible of managing the transmission timers of periodic and +| mixed frames. +| * The transmission timer value will be rounded down to first multiple of +| FICOSEK_COM_TASK_TICKS +| --------------------------------------------------------------------------- +| Parameters description: +/ --------------------------------------------------------------------------- */ +static void OsekComPeriodicTx(void) +{ + /* Test whether Tx of periodic frames is active */ + if (TST_FLAG_OSEK_COM_PER_TX()) { + /* Com frames monitoring */ + + /* Tx frame SwtrPrivateDHUCanFr06 end of period monitoring */ + ptt_tx_frm_swtrprivatedhucanfr06 += time_diff; + if (ptt_tx_frm_swtrprivatedhucanfr06 >= PT_TX_FRM_SWTRPRIVATEDHUCANFR06) { + /* Reset timer */ + ptt_tx_frm_swtrprivatedhucanfr06 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR06(); + + OsekComTxReqCallbackSWTR(); + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtrPrivateDHUCanFr05 end of period monitoring */ + ptt_tx_frm_swtrprivatedhucanfr05 += time_diff; + if (ptt_tx_frm_swtrprivatedhucanfr05 >= PT_TX_FRM_SWTRPRIVATEDHUCANFR05) { + /* Reset timer */ + ptt_tx_frm_swtrprivatedhucanfr05 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR05(); + + OsekComTxReqCallbackSWTR(); + //ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtrPrivateDHUCanFr04 end of period monitoring */ + ptt_tx_frm_swtrprivatedhucanfr04 += time_diff; + if (ptt_tx_frm_swtrprivatedhucanfr04 >= PT_TX_FRM_SWTRPRIVATEDHUCANFR04) { + /* Reset timer */ + ptt_tx_frm_swtrprivatedhucanfr04 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR04(); + + OsekComTxReqCallbackSWTR(); + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtrPrivateDHUCanFr03 end of period monitoring */ + ptt_tx_frm_swtrprivatedhucanfr03 += time_diff; + if (ptt_tx_frm_swtrprivatedhucanfr03 >= PT_TX_FRM_SWTRPRIVATEDHUCANFR03) { + /* Reset timer */ + ptt_tx_frm_swtrprivatedhucanfr03 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR03(); + + OsekComTxReqCallbackSWTR(); + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } +#if 0 + /* Tx frame SwtrPrivateDHUCanFr02 end of period monitoring */ + ptt_tx_frm_swtrprivatedhucanfr02 += time_diff; + if (ptt_tx_frm_swtrprivatedhucanfr02 >= PT_TX_FRM_SWTRPRIVATEDHUCANFR02) { + /* Reset timer */ + ptt_tx_frm_swtrprivatedhucanfr02 = 0; /* Tx frame */ + //SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02(); + OsekComTxReqCallbackSWTR(); + //ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + #endif + /* Tx frame SwtrPressFr01 end of period monitoring */ + ptt_tx_frm_swtrpressfr01 += time_diff; + if (ptt_tx_frm_swtrpressfr01 >= PT_TX_FRM_SWTRPRESSFR01) { + /* Reset timer */ + ptt_tx_frm_swtrpressfr01 = 0; /* Tx frame */ + //SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRPRESSFR01(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + + + /* Tx frame SwtRSensorFr01 end of period monitoring */ + ptt_tx_frm_swtrsensorfr01 += time_diff; + if (ptt_tx_frm_swtrsensorfr01 >= PT_TX_FRM_SWTRSENSORFR01) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr01 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR01(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr02 end of period monitoring */ + ptt_tx_frm_swtrsensorfr02 += time_diff; + if (ptt_tx_frm_swtrsensorfr02 >= PT_TX_FRM_SWTRSENSORFR02) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr02 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR02(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr03 end of period monitoring */ + ptt_tx_frm_swtrsensorfr03 += time_diff; + if (ptt_tx_frm_swtrsensorfr03 >= PT_TX_FRM_SWTRSENSORFR03) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr03 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR03(); + + OsekComTxReqCallbackSWTR(); + + //ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr04 end of period monitoring */ + ptt_tx_frm_swtrsensorfr04 += time_diff; + if (ptt_tx_frm_swtrsensorfr04 >= PT_TX_FRM_SWTRSENSORFR04) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr04 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR04(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr05 end of period monitoring */ + ptt_tx_frm_swtrsensorfr05 += time_diff; + if (ptt_tx_frm_swtrsensorfr05 >= PT_TX_FRM_SWTRSENSORFR05) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr05 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR05(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr06 end of period monitoring */ + ptt_tx_frm_swtrsensorfr06 += time_diff; + if (ptt_tx_frm_swtrsensorfr06 >= PT_TX_FRM_SWTRSENSORFR06) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr06 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR06(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr07 end of period monitoring */ + ptt_tx_frm_swtrsensorfr07 += time_diff; + if (ptt_tx_frm_swtrsensorfr07 >= PT_TX_FRM_SWTRSENSORFR07) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr07 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR07(); + + OsekComTxReqCallbackSWTR(); + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + + /* Tx frame SwtRSensorFr08 end of period monitoring */ + ptt_tx_frm_swtrsensorfr08 += time_diff; + if (ptt_tx_frm_swtrsensorfr08 >= PT_TX_FRM_SWTRSENSORFR08) { + /* Reset timer */ + ptt_tx_frm_swtrsensorfr08 = 0; /* Tx frame */ + // SuspendAllInterrupts(); + + SET_FLAG_TX_REQ_FRM_SWTRSENSORFR08(); + + OsekComTxReqCallbackSWTR(); + + + + + // ResumeAllInterrupts(); + } + else { + /* Do nothing */ + } + } +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Runnable responsible of managing the reception time-out timers of +| periodic and mixed frames. +| * The timer value will be rounded down to first multiple of FICOSEK_COM_TASK_TICKS +| --------------------------------------------------------------------------- +| Parameters description: +/ --------------------------------------------------------------------------- */ +static void OsekComDeadlineMonitRx(void) +{ + /* Management of timers of Rx Error Signals */ + + /* Increasing Timer */ + dmt_rx_sig_actvnofsteerwhlillmn += time_diff; + /* Rx deadline case time out signal ActvnOfSteerWhlIllmn */ + if (dmt_rx_sig_actvnofsteerwhlillmn >= TO_RX_SIG_ACTVNOFSTEERWHLILLMN) { + /* Reset monitoring timer */ + dmt_rx_sig_actvnofsteerwhlillmn = 0; + /* RxError notification callback */ + IhuPrivateDHUCanFr01_Timeout_CALLBACK(); + } + /* Case normal counting */ + else { + /* Do Nothing */ + } +} + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Routine responsible of initiating on event transmissions of direct and +| mixed frames +| --------------------------------------------------------------------------- +| Parameters description: +/ --------------------------------------------------------------------------- */ + void OsekComTxReqFrmSwtrPrivateDHUCanFr01(void) +{ + /* Tx frame */ + + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR01(); + OsekComTxReqCallbackSWTR(); +} + + void OsekComTxReqFrmSwtrPrivateDHUCanFr02(void) +{ + /* Tx frame */ + + SET_FLAG_TX_REQ_FRM_SWTRPRIVATEDHUCANFR02(); + OsekComTxReqCallbackSWTR(); +} + + /*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Routine responsible of initiating on event transmissions of direct and +| mixed frames +| --------------------------------------------------------------------------- +| Parameters description: +/ --------------------------------------------------------------------------- */ +static void OsekComTxReqFrmDIAG_PhysResp_SWTR(void) +{ + /* Start of the Tx deadline monitoring timer */ + //SuspendAllInterrupts(); + if (dmt_tx_frm_diag_physresp_swtr == TIMER_CANCEL) { + dmt_tx_frm_diag_physresp_swtr = 0; + } + else { + /* Do nothing */ + } + /* Tx frame */ + SET_FLAG_TX_REQ_FRM_DIAG_PHYSRESP_SWTR(); + // CanTxRequest(0); + OsekComTxReqCallbackSWTR(); + // ResumeAllInterrupts(); +} + diff --git a/firmware/src/OsekCom/OsekCom.h b/firmware/src/OsekCom/OsekCom.h new file mode 100644 index 0000000..4334d9f --- /dev/null +++ b/firmware/src/OsekCom/OsekCom.h @@ -0,0 +1,827 @@ + +#ifndef __OSEKCOM_H +#define __OSEKCOM_H + +/*-------------------------------- Includes ------------------------------*/ +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes + +/*-------------------------------- Defines -------------------------------*/ +/* CAN handlers definition */ +typedef enum { + CAN1_HANDLER = 0x00, /* CAN1 handler */ + CAN2_HANDLER = 0x01, /* CAN2 handler */ + CAN_HANDLER_UNKNOWN = 0xFF +}t_can_handler; + +typedef uint8_t t_can_data[8]; + +#ifndef uint8_t +typedef unsigned char uint8_t; +#endif + +#ifndef uint16_t +typedef unsigned short uint16_t; +#endif + +#ifndef bool +typedef unsigned char bool; +#endif +/* Theoretical time between two consecutive executions of OsekCom task */ +#define FICOSEK_COM_TASK_TICKS (1) + +/* Return type of the calls OSEK COM */ +#ifndef STD_TYPES_H + #define E_OK ((uint8_t)0x00) /* Service call has succeeded */ +#endif +#define E_COM_ID ((uint8_t)0x01) /* Given message or mode identifier */ + /* is out of range or invalid */ +#define E_COM_LENGTH ((uint8_t)0x02) /* Given data length is out of range */ +#define E_COM_LIMIT ((uint8_t)0x03) /* Overflow of message queue */ +#define E_COM_NOMSG ((uint8_t)0x04) /* Message queue is empty */ +#define E_COM_SYS_NOINIT ((uint8_t)0x05) /* User defined E_COM_SYS_?? */ + + +/* Acceptable values for the signal sig_DiagcFailrTouchPanSWTRVibrationFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS_FLTSTS_INVALID ((t_sig_diagcfailrtouchpanswtrvibrationfltsts) 3) +#define SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS_FLTSTS_VIBRATIONOPENCIRC ((t_sig_diagcfailrtouchpanswtrvibrationfltsts) 2) +#define SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS_FLTSTS_VIBRATIONSHOCIRC ((t_sig_diagcfailrtouchpanswtrvibrationfltsts) 1) +#define SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS_FLTSTS_NOFLT ((t_sig_diagcfailrtouchpanswtrvibrationfltsts) 0) + +/* Acceptable values for the signal sig_DiagcFailrTouchPanSWTRTouchdFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS_FLTSTS_TOUCHDOUTDOFRNG ((t_sig_diagcfailrtouchpanswtrtouchdfltsts) 2) +#define SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS_FLTSTS_TOUCHDINVLD ((t_sig_diagcfailrtouchpanswtrtouchdfltsts) 1) +#define SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS_FLTSTS_NOFLT ((t_sig_diagcfailrtouchpanswtrtouchdfltsts) 0) + +/* Acceptable values for the signal sig_DiagcFailrTouchPanSWTRSnsrFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS_SNSRFLTSTS_FSNSROPENCIRC ((t_sig_diagcfailrtouchpanswtrsnsrfltsts) 4) +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS_SNSRFLTSTS_FSNSRSHOCIRCTOBATT ((t_sig_diagcfailrtouchpanswtrsnsrfltsts) 3) +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS_SNSRFLTSTS_FSNSRSHOCIRCTOGND ((t_sig_diagcfailrtouchpanswtrsnsrfltsts) 2) +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS_SNSRFLTSTS_FSNSRINVLD ((t_sig_diagcfailrtouchpanswtrsnsrfltsts) 1) +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS_SNSRFLTSTS_NOFLT ((t_sig_diagcfailrtouchpanswtrsnsrfltsts) 0) + +/* Acceptable values for the signal sig_DiagcFailrTouchPanSWTRCmnFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS_CMNFLTSTS_OUTDURNG ((t_sig_diagcfailrtouchpanswtrcmnfltsts) 1) +#define SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS_CMNFLTSTS_NOFLT ((t_sig_diagcfailrtouchpanswtrcmnfltsts) 0) + +/* Acceptable values for the signal sig_SwpUpDwnStsRi */ +#define SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_LONGSLIDEDOWN ((t_sig_swpupdwnstsri) 4) +#define SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_LONGSLIDEUP ((t_sig_swpupdwnstsri) 3) +#define SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_SHORTSLIDEDOWN ((t_sig_swpupdwnstsri) 2) +#define SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_SHORTSLIDEUP ((t_sig_swpupdwnstsri) 1) +#define SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_IDLE ((t_sig_swpupdwnstsri) 0) + +/* Acceptable values for the signal sig_SwpLeRiStsRi */ +#define SIG_SWPLERISTSRI_SWPLERIREQSTS_LONGSLIDERIGHT ((t_sig_swpleristsri) 4) +#define SIG_SWPLERISTSRI_SWPLERIREQSTS_LONGSLIDELEFT ((t_sig_swpleristsri) 3) +#define SIG_SWPLERISTSRI_SWPLERIREQSTS_SHORTSLIDERIGHT ((t_sig_swpleristsri) 2) +#define SIG_SWPLERISTSRI_SWPLERIREQSTS_SHORTSLIDELEFT ((t_sig_swpleristsri) 1) +#define SIG_SWPLERISTSRI_SWPLERIREQSTS_IDLE ((t_sig_swpleristsri) 0) + +/* Acceptable values for the signal sig_SteerWhlTouchBdVoice */ +#define SIG_STEERWHLTOUCHBDVOICE_STEERWHLTOUCHBDSTS_INVALID ((t_sig_steerwhltouchbdvoice) 3) +#define SIG_STEERWHLTOUCHBDVOICE_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_steerwhltouchbdvoice) 2) +#define SIG_STEERWHLTOUCHBDVOICE_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_steerwhltouchbdvoice) 1) +#define SIG_STEERWHLTOUCHBDVOICE_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_steerwhltouchbdvoice) 0) + +/* Acceptable values for the signal sig_SteerWhlTouchBdMenu */ +#define SIG_STEERWHLTOUCHBDMENU_STEERWHLTOUCHBDSTS_INVALID ((t_sig_steerwhltouchbdmenu) 3) +#define SIG_STEERWHLTOUCHBDMENU_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_steerwhltouchbdmenu) 2) +#define SIG_STEERWHLTOUCHBDMENU_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_steerwhltouchbdmenu) 1) +#define SIG_STEERWHLTOUCHBDMENU_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_steerwhltouchbdmenu) 0) + +/* Acceptable values for the signal sig_SteerWhlTouchBdDn */ +#define SIG_STEERWHLTOUCHBDDN_STEERWHLTOUCHBDSTS_INVALID ((t_sig_steerwhltouchbddn) 3) +#define SIG_STEERWHLTOUCHBDDN_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_steerwhltouchbddn) 2) +#define SIG_STEERWHLTOUCHBDDN_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_steerwhltouchbddn) 1) +#define SIG_STEERWHLTOUCHBDDN_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_steerwhltouchbddn) 0) + +/* Acceptable values for the signal sig_SldVolCtrlSts */ +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_ERROR ((t_sig_sldvolctrlsts) 7) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_INCREASETHIRD ((t_sig_sldvolctrlsts) 6) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_DECREASETHIRD ((t_sig_sldvolctrlsts) 5) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_INCREASEDOUBLE ((t_sig_sldvolctrlsts) 4) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_DECREASEDOUBLE ((t_sig_sldvolctrlsts) 3) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_VOLUMEINCREASE ((t_sig_sldvolctrlsts) 2) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_VOLUMEDECREASE ((t_sig_sldvolctrlsts) 1) +#define SIG_SLDVOLCTRLSTS_SLIPSWITCH_IDLE ((t_sig_sldvolctrlsts) 0) + +/* Acceptable values for the signal sig_RiMFctActSgUp */ +#define SIG_RIMFCTACTSGUP_STEERWHLTOUCHBDSTS_INVALID ((t_sig_rimfctactsgup) 3) +#define SIG_RIMFCTACTSGUP_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_rimfctactsgup) 2) +#define SIG_RIMFCTACTSGUP_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_rimfctactsgup) 1) +#define SIG_RIMFCTACTSGUP_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_rimfctactsgup) 0) + +/* Acceptable values for the signal sig_RiMFctActSgRi */ +#define SIG_RIMFCTACTSGRI_STEERWHLTOUCHBDSTS_INVALID ((t_sig_rimfctactsgri) 3) +#define SIG_RIMFCTACTSGRI_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_rimfctactsgri) 2) +#define SIG_RIMFCTACTSGRI_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_rimfctactsgri) 1) +#define SIG_RIMFCTACTSGRI_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_rimfctactsgri) 0) + +/* Acceptable values for the signal sig_RiMFctActSgLe */ +#define SIG_RIMFCTACTSGLE_STEERWHLTOUCHBDSTS_INVALID ((t_sig_rimfctactsgle) 3) +#define SIG_RIMFCTACTSGLE_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_rimfctactsgle) 2) +#define SIG_RIMFCTACTSGLE_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_rimfctactsgle) 1) +#define SIG_RIMFCTACTSGLE_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_rimfctactsgle) 0) + +/* Acceptable values for the signal sig_RiMFctActSgDn */ +#define SIG_RIMFCTACTSGDN_STEERWHLTOUCHBDSTS_INVALID ((t_sig_rimfctactsgdn) 3) +#define SIG_RIMFCTACTSGDN_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_rimfctactsgdn) 2) +#define SIG_RIMFCTACTSGDN_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_rimfctactsgdn) 1) +#define SIG_RIMFCTACTSGDN_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_rimfctactsgdn) 0) + +/* Acceptable values for the signal sig_RiMFctActSgCe */ +#define SIG_RIMFCTACTSGCE_STEERWHLTOUCHBDSTS_INVALID ((t_sig_rimfctactsgce) 3) +#define SIG_RIMFCTACTSGCE_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_rimfctactsgce) 2) +#define SIG_RIMFCTACTSGCE_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_rimfctactsgce) 1) +#define SIG_RIMFCTACTSGCE_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_rimfctactsgce) 0) + +/* Acceptable values for the signal sig_SteerWhlTouchBdRiSteerWhlTouchBdSts */ +#define SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS_STEERWHLTOUCHBDSTS_INVALID ((t_sig_steerwhltouchbdristeerwhltouchbdsts) 3) +#define SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS_STEERWHLTOUCHBDSTS_TOUCHANDPRESS ((t_sig_steerwhltouchbdristeerwhltouchbdsts) 2) +#define SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS_STEERWHLTOUCHBDSTS_TOUCH ((t_sig_steerwhltouchbdristeerwhltouchbdsts) 1) +#define SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS_STEERWHLTOUCHBDSTS_NOTACTIVE ((t_sig_steerwhltouchbdristeerwhltouchbdsts) 0) + +/* Acceptable values for the signal sig_TwliBriSts */ +#define SIG_TWLIBRISTS_TWLIBRISTS1_DAY ((t_sig_twlibrists) 1) +#define SIG_TWLIBRISTS_TWLIBRISTS1_NIGHT ((t_sig_twlibrists) 0) + +/* Acceptable values for the signal sig_ActvnOfSteerWhlIllmn */ +#define SIG_ACTVNOFSTEERWHLILLMN_BOOLEAN_TRUE ((t_sig_actvnofsteerwhlillmn) 1) +#define SIG_ACTVNOFSTEERWHLILLMN_BOOLEAN_FALSE ((t_sig_actvnofsteerwhlillmn) 0) +/* Node id */ +#define NODE_ID_MASK ((uint16_t) 0xF000U) /* Mask to get nodes id */ +#define NODE_ID_SWTR (((uint16_t) 0x1000U) & NODE_ID_MASK) /* Symbolic name of the node SWTR */ + +/* Symbolic names for Tx signals with static length */ +/* First Tx signal */ +#define FIRST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS) +#define SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS (((uint16_t) 1) | NODE_ID_SWTR) /* Symbolic name of the signal DiagcFailrTouchPanSWTRCmnFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS (((uint16_t) 2) | NODE_ID_SWTR) /* Symbolic name of the signal DiagcFailrTouchPanSWTRSnsrFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS (((uint16_t) 3) | NODE_ID_SWTR) /* Symbolic name of the signal DiagcFailrTouchPanSWTRTouchdFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS (((uint16_t) 4) | NODE_ID_SWTR) /* Symbolic name of the signal DiagcFailrTouchPanSWTRVibrationFltSts */ +#define SIG_DIAGCFAILRTOUCHPANSWTR_UB (((uint16_t) 5) | NODE_ID_SWTR) /* Symbolic name of the signal DiagcFailrTouchPanSWTR_UB */ +#define SIG_RIMFCTACTSGCE (((uint16_t) 6) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgCe */ +#define SIG_RIMFCTACTSGCE_UB (((uint16_t) 7) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgCe_UB */ +#define SIG_RIMFCTACTSGDN (((uint16_t) 8) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgDn */ +#define SIG_RIMFCTACTSGDN_UB (((uint16_t) 9) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgDn_UB */ +#define SIG_RIMFCTACTSGLE (((uint16_t) 10) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgLe */ +#define SIG_RIMFCTACTSGLE_UB (((uint16_t) 11) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgLe_UB */ +#define SIG_RIMFCTACTSGRI (((uint16_t) 12) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgRi */ +#define SIG_RIMFCTACTSGRI_UB (((uint16_t) 13) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgRi_UB */ +#define SIG_RIMFCTACTSGUP (((uint16_t) 14) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgUp */ +#define SIG_RIMFCTACTSGUP_UB (((uint16_t) 15) | NODE_ID_SWTR) /* Symbolic name of the signal RiMFctActSgUp_UB */ +#define SIG_SLDVOLCTRLSTS (((uint16_t) 16) | NODE_ID_SWTR) /* Symbolic name of the signal SldVolCtrlSts */ +#define SIG_SLDVOLCTRLSTS_UB (((uint16_t) 17) | NODE_ID_SWTR) /* Symbolic name of the signal SldVolCtrlSts_UB */ +#define SIG_STEERWHLTOUCHBDDN (((uint16_t) 18) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdDn */ +#define SIG_STEERWHLTOUCHBDDN_UB (((uint16_t) 19) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdDn_UB */ +#define SIG_STEERWHLTOUCHBDMENU (((uint16_t) 20) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdMenu */ +#define SIG_STEERWHLTOUCHBDMENU_UB (((uint16_t) 21) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdMenu_UB */ +#define SIG_STEERWHLTOUCHBDRICHKS (((uint16_t) 22) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRiChks */ +#define SIG_STEERWHLTOUCHBDRICNTR (((uint16_t) 23) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRiCntr */ +#define SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS (((uint16_t) 24) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRiSteerWhlTouchBdSts */ +#define SIG_STEERWHLTOUCHBDRITOUCHPOSNX (((uint16_t) 25) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRiTouchPosnX */ +#define SIG_STEERWHLTOUCHBDRITOUCHPOSNY (((uint16_t) 26) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRiTouchPosnY */ +#define SIG_STEERWHLTOUCHBDRI_UB (((uint16_t) 27) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdRi_UB */ +#define SIG_STEERWHLTOUCHBDVOICE (((uint16_t) 28) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdVoice */ +#define SIG_STEERWHLTOUCHBDVOICE_UB (((uint16_t) 29) | NODE_ID_SWTR) /* Symbolic name of the signal SteerWhlTouchBdVoice_UB */ +#define SIG_SWPLERISTSRI (((uint16_t) 30) | NODE_ID_SWTR) /* Symbolic name of the signal SwpLeRiStsRi */ +#define SIG_SWPLERISTSRI_UB (((uint16_t) 31) | NODE_ID_SWTR) /* Symbolic name of the signal SwpLeRiStsRi_UB */ +#define SIG_SWPUPDWNSTSRI (((uint16_t) 32) | NODE_ID_SWTR) /* Symbolic name of the signal SwpUpDwnStsRi */ +#define SIG_SWPUPDWNSTSRI_UB (((uint16_t) 33) | NODE_ID_SWTR) /* Symbolic name of the signal SwpUpDwnStsRi_UB */ +#define SIG_SWTRPARTNO10CMPLENDSGN1 (((uint16_t) 34) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplEndSgn1 */ +#define SIG_SWTRPARTNO10CMPLENDSGN2 (((uint16_t) 35) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplEndSgn2 */ +#define SIG_SWTRPARTNO10CMPLENDSGN3 (((uint16_t) 36) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplEndSgn3 */ +#define SIG_SWTRPARTNO10CMPLNR1 (((uint16_t) 37) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplNr1 */ +#define SIG_SWTRPARTNO10CMPLNR2 (((uint16_t) 38) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplNr2 */ +#define SIG_SWTRPARTNO10CMPLNR3 (((uint16_t) 39) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplNr3 */ +#define SIG_SWTRPARTNO10CMPLNR4 (((uint16_t) 40) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplNr4 */ +#define SIG_SWTRPARTNO10CMPLNR5 (((uint16_t) 41) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNo10CmplNr5 */ +#define SIG_SWTRPARTNOCMPLENDSGN1 (((uint16_t) 42) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplEndSgn1 */ +#define SIG_SWTRPARTNOCMPLENDSGN2 (((uint16_t) 43) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplEndSgn2 */ +#define SIG_SWTRPARTNOCMPLENDSGN3 (((uint16_t) 44) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplEndSgn3 */ +#define SIG_SWTRPARTNOCMPLNR1 (((uint16_t) 45) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplNr1 */ +#define SIG_SWTRPARTNOCMPLNR2 (((uint16_t) 46) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplNr2 */ +#define SIG_SWTRPARTNOCMPLNR3 (((uint16_t) 47) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplNr3 */ +#define SIG_SWTRPARTNOCMPLNR4 (((uint16_t) 48) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmplNr4 */ +#define SIG_SWTRPARTNOCMPL_UB (((uint16_t) 49) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRPartNoCmpl_UB */ +#define SIG_SWTRPRESSBASELINE (((uint16_t) 50) | NODE_ID_SWTR) /* Symbolic name of the signal SwtrPressBaseline */ +#define SIG_SWTRPRESSSIGNAL (((uint16_t) 51) | NODE_ID_SWTR) /* Symbolic name of the signal SwtrPressSignal */ +#define SIG_SWTRSENSOR10_BASELINE (((uint16_t) 52) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor10_baseline */ +#define SIG_SWTRSENSOR10_SIGNAL (((uint16_t) 53) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor10_signal */ +#define SIG_SWTRSENSOR11_BASELINE (((uint16_t) 54) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor11_baseline */ +#define SIG_SWTRSENSOR11_SIGNAL (((uint16_t) 55) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor11_signal */ +#define SIG_SWTRSENSOR12_BASELINE (((uint16_t) 56) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor12_baseline */ +#define SIG_SWTRSENSOR12_SIGNAL (((uint16_t) 57) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor12_signal */ +#define SIG_SWTRSENSOR13_BASELINE (((uint16_t) 58) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor13_baseline */ +#define SIG_SWTRSENSOR13_SIGNAL (((uint16_t) 59) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor13_signal */ +#define SIG_SWTRSENSOR14_BASELINE (((uint16_t) 60) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor14_baseline */ +#define SIG_SWTRSENSOR14_SIGNAL (((uint16_t) 61) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor14_signal */ +#define SIG_SWTRSENSOR15_BASELINE (((uint16_t) 62) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor15_baseline */ +#define SIG_SWTRSENSOR15_SIGNAL (((uint16_t) 63) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor15_signal */ +#define SIG_SWTRSENSOR16_BASELINE (((uint16_t) 64) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor16_baseline */ +#define SIG_SWTRSENSOR16_SIGNAL (((uint16_t) 65) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor16_signal */ +#define SIG_SWTRSENSOR1_BASELINE (((uint16_t) 66) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor1_baseline */ +#define SIG_SWTRSENSOR1_SIGNAL (((uint16_t) 67) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor1_signal */ +#define SIG_SWTRSENSOR2_BASELINE (((uint16_t) 68) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor2_baseline */ +#define SIG_SWTRSENSOR2_SIGNAL (((uint16_t) 69) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor2_signal */ +#define SIG_SWTRSENSOR3_BASELINE (((uint16_t) 70) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor3_baseline */ +#define SIG_SWTRSENSOR3_SIGNAL (((uint16_t) 71) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor3_signal */ +#define SIG_SWTRSENSOR4_BASELINE (((uint16_t) 72) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor4_baseline */ +#define SIG_SWTRSENSOR4_SIGNAL (((uint16_t) 73) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor4_signal */ +#define SIG_SWTRSENSOR5_BASELINE (((uint16_t) 74) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor5_baseline */ +#define SIG_SWTRSENSOR5_SIGNAL (((uint16_t) 75) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor5_signal */ +#define SIG_SWTRSENSOR6_BASELINE (((uint16_t) 76) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor6_baseline */ +#define SIG_SWTRSENSOR6_SIGNAL (((uint16_t) 77) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor6_signal */ +#define SIG_SWTRSENSOR7_BASELINE (((uint16_t) 78) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor7_baseline */ +#define SIG_SWTRSENSOR7_SIGNAL (((uint16_t) 79) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor7_signal */ +#define SIG_SWTRSENSOR8_BASELINE (((uint16_t) 80) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor8_baseline */ +#define SIG_SWTRSENSOR8_SIGNAL (((uint16_t) 81) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor8_signal */ +#define SIG_SWTRSENSOR9_BASELINE (((uint16_t) 82) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRsensor9_baseline */ +#define SIG_SWTRSENSOR9_SIGNAL (((uint16_t) 83) | NODE_ID_SWTR) /* Symbolic name of the signal SwtRSensor9_signal */ +#define SIG_SWTRSERNONR1 (((uint16_t) 84) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRSerNoNr1 */ +#define SIG_SWTRSERNONR2 (((uint16_t) 85) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRSerNoNr2 */ +#define SIG_SWTRSERNONR3 (((uint16_t) 86) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRSerNoNr3 */ +#define SIG_SWTRSERNONR4 (((uint16_t) 87) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRSerNoNr4 */ +#define SIG_SWTRSERNO_UB (((uint16_t) 88) | NODE_ID_SWTR) /* Symbolic name of the signal SWTRSerNo_UB */ +/* Last Tx signal */ +#define LAST_TX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_SWTRSERNO_UB) + +/* Symbolic names for Tx signals with dynamic length */ +/* First Tx signal */ +#define FIRST_TX_DYN_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_DIAGNOSTICRESPSWTR) +#define SIG_DIAGNOSTICRESPSWTR (((UI_16) 89) | NODE_ID_SWTR) /* Symbolic name of the signal SIG_DIAGNOSTICRESPSWTR */ +/* Last Tx signal */ +#define LAST_TX_DYN_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_DIAGNOSTICRESPSWTR) + +/* Symbolic names for Rx signals */ +#define SIG_ACTVNOFSTEERWHLILLMN (((uint16_t) 90) | NODE_ID_SWTR) /* Symbolic name of the signal ActvnOfSteerWhlIllmn */ +#define SIG_ACTVNOFSTEERWHLILLMN_UB (((uint16_t) 91) | NODE_ID_SWTR) /* Symbolic name of the signal ActvnOfSteerWhlIllmn_UB */ +#define SIG_INTRBRISTS (((uint16_t) 92) | NODE_ID_SWTR) /* Symbolic name of the signal IntrBriSts */ +#define SIG_INTRBRISTS_UB (((uint16_t) 93) | NODE_ID_SWTR) /* Symbolic name of the signal IntrBriSts_UB */ +#define SIG_SWTOFKEYTONE (((uint16_t) 94) | NODE_ID_SWTR) /* Symbolic name of the signal SwtOfKeyTone */ +#define SIG_SWTOFKEYTONE_UB (((uint16_t) 95) | NODE_ID_SWTR) /* Symbolic name of the signal SwtOfKeyTone_UB */ +#define SIG_TWLIBRISTS (((uint16_t) 96) | NODE_ID_SWTR) /* Symbolic name of the signal TwliBriSts */ +#define SIG_TWLIBRISTS_UB (((uint16_t) 97) | NODE_ID_SWTR) /* Symbolic name of the signal TwliBriSts_UB */ + +/*Symbolic names for Rx signals with dynamic length*/ +#define SIG_DIAGNOSTICREQSWTR (((UI_16) 98) | NODE_ID_SWTR) /* Symbolic name of the signal SIG_DIAGNOSTICREQSWTR */ +#define SIG_DIAGNOSTICFUNCADDRREQ (((UI_16) 99) | NODE_ID_SWTR) /* Symbolic name of the signal DiagnosticFuncAddrReq */ +/* Last Rx signal */ +#define LAST_RX_STA_LEN_SIGNAL_SYMBOLIC_NAME ((~NODE_ID_MASK) & SIG_DIAGNOSTICFUNCADDRREQ) + +/* Last OsekCom signal */ +#define LAST_OSEK_COM_SIGNAL_SYMBOLIC_NAME ((uint16_t) 99) + +/* Symbolic names for Dummy signal */ +#define SIGDUMMY ((uint16_t)0x0FFF) /* Symbolic name of the signal SIGDUMMY */ + + +/*----------------------------- Data Types -------------------------------*/ +/* Type definition of internal signals */ +typedef uint8_t t_sig_diagcfailrtouchpanswtrvibrationfltsts; +typedef uint8_t t_sig_diagcfailrtouchpanswtrtouchdfltsts; +typedef uint8_t t_sig_diagcfailrtouchpanswtrsnsrfltsts; +typedef uint8_t t_sig_diagcfailrtouchpanswtrcmnfltsts; +typedef uint8_t t_sig_diagcfailrtouchpanswtr_ub; +typedef uint8_t t_sig_swtrsernonr4; +typedef uint8_t t_sig_swtrsernonr3; +typedef uint8_t t_sig_swtrsernonr2; +typedef uint8_t t_sig_swtrsernonr1; +typedef uint8_t t_sig_swtrserno_ub; +typedef uint8_t t_sig_swtrpartnocmplnr4; +typedef uint8_t t_sig_swtrpartnocmplnr3; +typedef uint8_t t_sig_swtrpartnocmplnr2; +typedef uint8_t t_sig_swtrpartnocmplnr1; +typedef uint8_t t_sig_swtrpartnocmplendsgn3; +typedef uint8_t t_sig_swtrpartnocmplendsgn2; +typedef uint8_t t_sig_swtrpartnocmplendsgn1; +typedef uint8_t t_sig_swtrpartnocmpl_ub; +typedef uint8_t t_sig_swtrpartno10cmplnr5; +typedef uint8_t t_sig_swtrpartno10cmplnr4; +typedef uint8_t t_sig_swtrpartno10cmplnr3; +typedef uint8_t t_sig_swtrpartno10cmplnr2; +typedef uint8_t t_sig_swtrpartno10cmplnr1; +typedef uint8_t t_sig_swtrpartno10cmplendsgn3; +typedef uint8_t t_sig_swtrpartno10cmplendsgn2; +typedef uint8_t t_sig_swtrpartno10cmplendsgn1; +typedef uint8_t t_sig_swpupdwnstsri_ub; +typedef uint8_t t_sig_swpupdwnstsri; +typedef uint8_t t_sig_swpleristsri_ub; +typedef uint8_t t_sig_swpleristsri; +typedef uint8_t t_sig_steerwhltouchbdvoice_ub; +typedef uint8_t t_sig_steerwhltouchbdvoice; +typedef uint8_t t_sig_steerwhltouchbdmenu_ub; +typedef uint8_t t_sig_steerwhltouchbdmenu; +typedef uint8_t t_sig_steerwhltouchbddn_ub; +typedef uint8_t t_sig_steerwhltouchbddn; +typedef uint8_t t_sig_sldvolctrlsts_ub; +typedef uint8_t t_sig_sldvolctrlsts; +typedef uint8_t t_sig_rimfctactsgup_ub; +typedef uint8_t t_sig_rimfctactsgup; +typedef uint8_t t_sig_rimfctactsgri_ub; +typedef uint8_t t_sig_rimfctactsgri; +typedef uint8_t t_sig_rimfctactsgle_ub; +typedef uint8_t t_sig_rimfctactsgle; +typedef uint8_t t_sig_rimfctactsgdn_ub; +typedef uint8_t t_sig_rimfctactsgdn; +typedef uint8_t t_sig_rimfctactsgce_ub; +typedef uint8_t t_sig_rimfctactsgce; +typedef uint8_t t_sig_steerwhltouchbdritouchposny; +typedef uint8_t t_sig_steerwhltouchbdritouchposnx; +typedef uint8_t t_sig_steerwhltouchbdristeerwhltouchbdsts; +typedef uint8_t t_sig_steerwhltouchbdricntr; +typedef uint8_t t_sig_steerwhltouchbdrichks; +typedef uint8_t t_sig_steerwhltouchbdri_ub; +typedef uint16_t t_sig_swtrpressbaseline; +typedef uint16_t t_sig_swtrpresssignal; +typedef uint16_t t_sig_swtrsensor1_baseline; +typedef uint16_t t_sig_swtrsensor1_signal; +typedef uint16_t t_sig_swtrsensor2_baseline; +typedef uint16_t t_sig_swtrsensor2_signal; +typedef uint16_t t_sig_swtrsensor3_baseline; +typedef uint16_t t_sig_swtrsensor4_baseline; +typedef uint16_t t_sig_swtrsensor3_signal; +typedef uint16_t t_sig_swtrsensor4_signal; +typedef uint16_t t_sig_swtrsensor5_baseline; +typedef uint16_t t_sig_swtrsensor6_baseline; +typedef uint16_t t_sig_swtrsensor5_signal; +typedef uint16_t t_sig_swtrsensor6_signal; +typedef uint16_t t_sig_swtrsensor7_baseline; +typedef uint16_t t_sig_swtrsensor8_baseline; +typedef uint16_t t_sig_swtrsensor7_signal; +typedef uint16_t t_sig_swtrsensor8_signal; +typedef uint16_t t_sig_swtrsensor9_baseline; +typedef uint16_t t_sig_swtrsensor10_baseline; +typedef uint16_t t_sig_swtrsensor9_signal; +typedef uint16_t t_sig_swtrsensor10_signal; +typedef uint16_t t_sig_swtrsensor11_baseline; +typedef uint16_t t_sig_swtrsensor12_baseline; +typedef uint16_t t_sig_swtrsensor11_signal; +typedef uint16_t t_sig_swtrsensor12_signal; +typedef uint16_t t_sig_swtrsensor13_baseline; +typedef uint16_t t_sig_swtrsensor14_baseline; +typedef uint16_t t_sig_swtrsensor13_signal; +typedef uint16_t t_sig_swtrsensor14_signal; +typedef uint16_t t_sig_swtrsensor15_baseline; +typedef uint16_t t_sig_swtrsensor16_baseline; +typedef uint16_t t_sig_swtrsensor15_signal; +typedef uint16_t t_sig_swtrsensor16_signal; +typedef uint8_t t_sig_twlibrists_ub; +typedef uint8_t t_sig_twlibrists; +typedef uint8_t t_sig_swtofkeytone_ub; +typedef uint8_t t_sig_swtofkeytone; +typedef uint8_t t_sig_intrbrists_ub; +typedef uint8_t t_sig_intrbrists; +typedef uint8_t t_sig_actvnofsteerwhlillmn_ub; +typedef uint8_t t_sig_actvnofsteerwhlillmn; + + +#ifndef _OSEKCOM_H +#define _OSEKCOM_H + +/* Type definition of the symbolic names for signals */ +typedef uint16_t t_symbolic_name; +typedef uint16_t t_symbolic_frm_name; + +/* Return type of the calls OSEK COM */ +typedef uint8_t t_status_type; + +/* Structure of data type passed by reference in */ +/* the calls of OSEK COM */ +typedef void *t_application_data_ref; +typedef void *t_length_ref; + +/* Flag types of OSEK COM */ +typedef enum { + COM_FALSE = 0x00, /* Flag down */ + COM_TRUE = 0x01 /* Flag up */ +} t_flag_value; + +/* Stop mode of OSEK COM */ +typedef enum { + COM_SHUTDOWN_IMMEDIATE = 0 /* Apagat immediat */ +} t_com_shutdown_mode_type; + +/* Initialize mode of OSEK COM */ +typedef enum { + COM_NORMAL_MODE = 0 /* No es processen trames de COM de Debug */ +} t_com_application_mode_type; + +#endif + + + +/*--------------------------- Global Variables ---------------------------*/ + +/*----------- Prototypes of Callback Function Provided by User ----------*/ + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Notification Callbacks provided by user for class 1 (RxNotif), 3 (RxErrorNotif) +| 2 (TxNotif) and 4 (TxErrorNotif) +| --------------------------------------------------------------------------- +| Parameters description: +/ ------------------------------------------------- -------------------------- */ +#define COMCallback(CallbackRoutineName) void CallbackRoutineName(void) + +COMCallback(IhuPrivateDHUCanFr01_CALLBACK); +COMCallback(IhuPrivateDHUCanFr01_Timeout_CALLBACK); + + +/* --------------------------- Routine Prototypes --------------------------- */ +typedef uint8_t t_com_buf_hdl; +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reception of a new frame notification callback +| * This callback must be launched by the lower COM driver upon the reception +| of a new frame. +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the received frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComRxNotifCallbackSWTR(t_com_buf_hdl bhdl); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Available transmission buffer notification callback +| * This callback must be launched by the lower COM driver upon a transmission +| buffer will become available after requesting one to perform a transmission. +|--------------------------------------------------------------------------- +| Parameters description: +| return: TRUE in case that after current transmission lower COM driver should +| call again this callback to transmit a new frame. +| FALSE otherwise. +/---------------------------------------------------------------------------*/ +bool OsekComTxReqCallbackSWTR(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Frame transmission confirmation notifying callback +| * This callback must be launched by the lower COM driver upon the completion +| of a frame transmission for which transmission confirmation has been requested +|--------------------------------------------------------------------------- +| Parameters description: +| bhdl: Handler of the buffer where the transmitted frame is stored. +/---------------------------------------------------------------------------*/ +void OsekComTxNotifCallbackSWTR(t_com_buf_hdl bhdl); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to initialize OsekCom stack +| +| ------------------------------------------------- -------------------------- +| Parameters description: +| app_mode: OsekCom initialization mode (See t_com_application_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StartCom(t_com_application_mode_type app_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to inquiry in which mode OsekCom has been initialized. +| * If this service is called before initializing the communications stack +| a random mode will be returned. +| --------------------------------------------------------------------------- +| Parameters description: +| return: OsekCom initialization mode(See t_com_application_mode_type) +/ --------------------------------------------------------------------------- */ +t_com_application_mode_type GetComApplicationMode(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to close the OsekCom stack. +| * This service stops the transmission of periodic frames. +| * After calling this service communications could be re-established +| calling again service StartCom. +| * This service does not change the state of any lower COM driver. +| --------------------------------------------------------------------------- +| Parameters description: +| shtdwn_mode: OsekCom stop mode (See t_com_shutdown_mode_type) +| return: E_OK in case of no errors +| Other (see t_status_type). +/ --------------------------------------------------------------------------- */ +t_status_type StopCom(t_com_shutdown_mode_type shtdwn_mode); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to start the transmission of periodic or mixed frames. +| * If this service is re-executed then transmission timers will be re-started. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StartPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Service to stop the transmission of periodic or mixed frames. +| * To re-start the transmission of periodic or mixed frames service +| StartPeriodic must be called. +|--------------------------------------------------------------------------- +| Parameters description: +| return: E_OK in case of no errors +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type StopPeriodic(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates the application variable referenced by >data_ref< with +| the data stored in the internal stack for the object identified by >message<. +| * This service will reset the class 1 (RxNotif) and 3 (RxErrorNotif) flags +| associated to >message< +| * If >message< is an enqueued signal the service will return the data +| stored in the internal stack (initial value / last received value / last value +| set with InitMessage) +| If >message< is a queued signal the service will return the first value +| available in the queue or error if the queue is empty. (Mode not supported) +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| received signal type +| * Usage example: +| t_vehicle_speed vehicle_speed; +| (void)ReceiveMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be retrieved. +| data_ref: Pointer to a variable where to store the requested signal. +| return: +| E_OK in case of no errors +| E_COM_ID in case the parameter >message< is out of range or if it refers +| to signal that is sent, dynamic length or zero-length +| E_COM_NOMSG in case the queued signal identified by >message< is empty. +| E_COM_LIMIT in case an overflow of the queue of the signal identified by >message< +| occurred since the last call to ReceiveMessage for >message<. +| E_COM_LIMIT indicates that at least one message has been discarded +| since the message queue filled. Nevertheless the service is +| performed and a message is returned. The service ReceiveMessage +| clears the overflow condition for >message<. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type ReceiveMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< parameter. +| * This service will reset the class 2 (TxNotif) and 4 (TxErrorNotif) flags +| associated to >message< +| * If >message< has the Triggered Transfer Property, the update will be +| followed by immediate transmission of the I-PDU associated with the signal except +| when the signal is packed into an I-PDU with Periodic Transmission Mode. +| In this case, no transmission is initiated by the call to this service. +| * If >message< has the Pending Transfer Property, no transmission is +| triggered by the usage of this service. +| * The user is responsible of granting that the parameter >data_ref< +| points to a variable correctly allocated and compatible in size with the +| transmitted signal type. +| * Usage example: +| t_vehicle_speed vehicle_speed = 20; +| (void)SendMessage(SIG_VEHICLE_SPEED,&vehicle_speed); +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal to be transmitted. +| data_ref: Pointer to a variable containing the data to be transmitted. +| return: +| E_OK in case of no errors +| E_COM_ID is case the parameter >message< is out of range or if it refers +| to a message that is received or to a dynamic-length or +| zero-length message. +| other (see t_status_type). +/---------------------------------------------------------------------------*/ +#define OSEK_SENDMESSAGE +t_status_type SendMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * This service updates OsekCom internal data structure of the signal +| identified by >message< with the data referenced by the variable +| referenced by >data_ref< +| * This service will not reset any class flags associated to >message< +| * This service will not initiate any transmission. +| * The user is responsible of granting that the parameter 'data_ref' +| points to an address correctly allocated and compatible in size with the +| transmitted signal type. +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| data_ref: Pointer to a variable containing the data. +| return: +| E_OK in case of no errors +| E_COM_ID if the message or signal to initialize don't exist +| Other (see t_status_type). +/---------------------------------------------------------------------------*/ +t_status_type InitMessage(t_symbolic_name message, + t_application_data_ref data_ref); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +| return: +| COM_FALSE if has not been detected any communication activity since +| last clear +| COM_TRUE if has been detected communication activity since last clear +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagComTrafficSWTR(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the flag of COM traffic. +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void ResetFlagComTrafficSWTR(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Consult service to retrieve the state of class 1 (RxNotif), +| class 3 (Rx_ErrorNotif), class 2 (TxNotif) and class 4 (Tx_ErrorNotif) flags +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +| return: +| COM_FALSE if the flag is down +| COM_TRUE if the flag is up +/---------------------------------------------------------------------------*/ +t_flag_value ReadFlagTxSig(t_symbolic_name message); +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(void); +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(void); +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(void); +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(void); +t_flag_value ReadFlagTxSigDiagcFailrTouchPanSWTR_UB(void); +t_flag_value ReadFlagTxSigSWTRSerNoNr4(void); +t_flag_value ReadFlagTxSigSWTRSerNoNr3(void); +t_flag_value ReadFlagTxSigSWTRSerNoNr2(void); +t_flag_value ReadFlagTxSigSWTRSerNoNr1(void); +t_flag_value ReadFlagTxSigSWTRSerNo_UB(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr4(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr3(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr2(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplNr1(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn3(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn2(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmplEndSgn1(void); +t_flag_value ReadFlagTxSigSWTRPartNoCmpl_UB(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr5(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr4(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr3(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr2(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplNr1(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn3(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn2(void); +t_flag_value ReadFlagTxSigSWTRPartNo10CmplEndSgn1(void); +t_flag_value ReadFlagTxSigSwpUpDwnStsRi_UB(void); +t_flag_value ReadFlagTxSigSwpUpDwnStsRi(void); +t_flag_value ReadFlagTxSigSwpLeRiStsRi_UB(void); +t_flag_value ReadFlagTxSigSwpLeRiStsRi(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdVoice_UB(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdVoice(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdMenu_UB(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdMenu(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdDn_UB(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdDn(void); +t_flag_value ReadFlagTxSigSldVolCtrlSts_UB(void); +t_flag_value ReadFlagTxSigSldVolCtrlSts(void); +t_flag_value ReadFlagTxSigRiMFctActSgUp_UB(void); +t_flag_value ReadFlagTxSigRiMFctActSgUp(void); +t_flag_value ReadFlagTxSigRiMFctActSgRi_UB(void); +t_flag_value ReadFlagTxSigRiMFctActSgRi(void); +t_flag_value ReadFlagTxSigRiMFctActSgLe_UB(void); +t_flag_value ReadFlagTxSigRiMFctActSgLe(void); +t_flag_value ReadFlagTxSigRiMFctActSgDn_UB(void); +t_flag_value ReadFlagTxSigRiMFctActSgDn(void); +t_flag_value ReadFlagTxSigRiMFctActSgCe_UB(void); +t_flag_value ReadFlagTxSigRiMFctActSgCe(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiTouchPosnY(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiTouchPosnX(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiCntr(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRiChks(void); +t_flag_value ReadFlagTxSigSteerWhlTouchBdRi_UB(void); +t_flag_value ReadFlagTxSigDiagnosticRespSWTR(void); +t_flag_value ReadFlagRxSigDiagnosticReqSWTR(void); +t_flag_value ReadFlagRxSigDiagnosticFuncAddrReq(void); +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Reset service for the notify class 1 (RxNotif) class 3 (RxErrorNotif) +| class 2 (TxNotif) and class 4 (TxErrorNotif) +|--------------------------------------------------------------------------- +| Parameters description: +| message: Identification of the signal. +/---------------------------------------------------------------------------*/ +void ResetFlagTxSig(t_symbolic_name message); +void ResetFlagTxSigDiagcFailrTouchPanSWTRVibrationFltSts(void); +void ResetFlagTxSigDiagcFailrTouchPanSWTRTouchdFltSts(void); +void ResetFlagTxSigDiagcFailrTouchPanSWTRSnsrFltSts(void); +void ResetFlagTxSigDiagcFailrTouchPanSWTRCmnFltSts(void); +void ResetFlagTxSigDiagcFailrTouchPanSWTR_UB(void); +void ResetFlagTxSigSWTRSerNoNr4(void); +void ResetFlagTxSigSWTRSerNoNr3(void); +void ResetFlagTxSigSWTRSerNoNr2(void); +void ResetFlagTxSigSWTRSerNoNr1(void); +void ResetFlagTxSigSWTRSerNo_UB(void); +void ResetFlagTxSigSWTRPartNoCmplNr4(void); +void ResetFlagTxSigSWTRPartNoCmplNr3(void); +void ResetFlagTxSigSWTRPartNoCmplNr2(void); +void ResetFlagTxSigSWTRPartNoCmplNr1(void); +void ResetFlagTxSigSWTRPartNoCmplEndSgn3(void); +void ResetFlagTxSigSWTRPartNoCmplEndSgn2(void); +void ResetFlagTxSigSWTRPartNoCmplEndSgn1(void); +void ResetFlagTxSigSWTRPartNoCmpl_UB(void); +void ResetFlagTxSigSWTRPartNo10CmplNr5(void); +void ResetFlagTxSigSWTRPartNo10CmplNr4(void); +void ResetFlagTxSigSWTRPartNo10CmplNr3(void); +void ResetFlagTxSigSWTRPartNo10CmplNr2(void); +void ResetFlagTxSigSWTRPartNo10CmplNr1(void); +void ResetFlagTxSigSWTRPartNo10CmplEndSgn3(void); +void ResetFlagTxSigSWTRPartNo10CmplEndSgn2(void); +void ResetFlagTxSigSWTRPartNo10CmplEndSgn1(void); +void ResetFlagTxSigSwpUpDwnStsRi_UB(void); +void ResetFlagTxSigSwpUpDwnStsRi(void); +void ResetFlagTxSigSwpLeRiStsRi_UB(void); +void ResetFlagTxSigSwpLeRiStsRi(void); +void ResetFlagTxSigSteerWhlTouchBdVoice_UB(void); +void ResetFlagTxSigSteerWhlTouchBdVoice(void); +void ResetFlagTxSigSteerWhlTouchBdMenu_UB(void); +void ResetFlagTxSigSteerWhlTouchBdMenu(void); +void ResetFlagTxSigSteerWhlTouchBdDn_UB(void); +void ResetFlagTxSigSteerWhlTouchBdDn(void); +void ResetFlagTxSigSldVolCtrlSts_UB(void); +void ResetFlagTxSigSldVolCtrlSts(void); +void ResetFlagTxSigRiMFctActSgUp_UB(void); +void ResetFlagTxSigRiMFctActSgUp(void); +void ResetFlagTxSigRiMFctActSgRi_UB(void); +void ResetFlagTxSigRiMFctActSgRi(void); +void ResetFlagTxSigRiMFctActSgLe_UB(void); +void ResetFlagTxSigRiMFctActSgLe(void); +void ResetFlagTxSigRiMFctActSgDn_UB(void); +void ResetFlagTxSigRiMFctActSgDn(void); +void ResetFlagTxSigRiMFctActSgCe_UB(void); +void ResetFlagTxSigRiMFctActSgCe(void); +void ResetFlagTxSigSteerWhlTouchBdRiTouchPosnY(void); +void ResetFlagTxSigSteerWhlTouchBdRiTouchPosnX(void); +void ResetFlagTxSigSteerWhlTouchBdRiSteerWhlTouchBdSts(void); +void ResetFlagTxSigSteerWhlTouchBdRiCntr(void); +void ResetFlagTxSigSteerWhlTouchBdRiChks(void); +void ResetFlagTxSigSteerWhlTouchBdRi_UB(void); +void ResetFlagTxSigDiagnosticRespSWTR(void); +void ResetFlagRxSig(t_symbolic_name message); +void ResetFlagRxSigDiagnosticReqSWTR(void); +void ResetFlagRxSigDiagnosticFuncAddrReq(void); + +/*--------------------------------------------------------------------------- +| Portability: Target platform independent +|---------------------------------------------------------------------------- +| Routine description: +| * Main runnable of the OsekCom stack intended to be called periodically by +| the system scheduler with a period equal to FICOSEK_COM_TASK_TICKS +|--------------------------------------------------------------------------- +| Parameters description: +/---------------------------------------------------------------------------*/ +void OsekComTask(void); +void OsekComTxReqFrmSwtrPrivateDHUCanFr01(void); +void OsekComTxReqFrmSwtrPrivateDHUCanFr02(void); +#endif + diff --git a/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c b/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c new file mode 100644 index 0000000..4249df4 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.c @@ -0,0 +1,41 @@ +/* + * File: ACT_control_20ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "ACT_control_20ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/ACT_control_20ms' */ +void P417_SWTR_App_ACT_control_20ms(uint8_T rtu_Set_0x305_Send_Req, uint8_T + rtu_Set_0x300_Send_Req) +{ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + RTE_Set_ACT_Vibration((uint8_T)((rtu_Set_0x305_Send_Req > 0) || + (rtu_Set_0x300_Send_Req > 0))); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.h b/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.h new file mode 100644 index 0000000..6e8c0d9 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/ACT_control_20ms.h @@ -0,0 +1,34 @@ +/* + * File: ACT_control_20ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_ACT_control_20ms_h_ +#define RTW_HEADER_ACT_control_20ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_SWTR_App_ACT_control_20ms(uint8_T rtu_Set_0x305_Send_Req, + uint8_T rtu_Set_0x300_Send_Req); + +#endif /* RTW_HEADER_ACT_control_20ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c new file mode 100644 index 0000000..872483b --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c @@ -0,0 +1,33 @@ +/* + * File: CAN_0x307_1000ms_Control.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "CAN_0x307_1000ms_Control.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/CAN_0x307_1000ms_Control' */ +void P417_S_CAN_0x307_1000ms_Control(uint8_T rtu_Set_0x305_Send_Req) +{ + /* Switch: '/Switch1' */ + RTE_Set_SEND_CAN_0x307_1000ms((uint8_T)!(rtu_Set_0x305_Send_Req > 0)); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.h b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.h new file mode 100644 index 0000000..6b00c43 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.h @@ -0,0 +1,33 @@ +/* + * File: CAN_0x307_1000ms_Control.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_CAN_0x307_1000ms_Control_h_ +#define RTW_HEADER_CAN_0x307_1000ms_Control_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_S_CAN_0x307_1000ms_Control(uint8_T rtu_Set_0x305_Send_Req); + +#endif /* RTW_HEADER_CAN_0x307_1000ms_Control_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c new file mode 100644 index 0000000..988fd06 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c @@ -0,0 +1,33 @@ +/* + * File: CAN_0x307_25ms_Control.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "CAN_0x307_25ms_Control.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/CAN_0x307_25ms_Control' */ +void P417_SWT_CAN_0x307_25ms_Control(uint8_T rtu_Set_0x305_Send_Req) +{ + /* Switch: '/Switch1' */ + RTE_Set_SEND_CAN_0x307_25ms((uint8_T)(rtu_Set_0x305_Send_Req > 0)); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.h b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.h new file mode 100644 index 0000000..3b94e90 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.h @@ -0,0 +1,33 @@ +/* + * File: CAN_0x307_25ms_Control.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_CAN_0x307_25ms_Control_h_ +#define RTW_HEADER_CAN_0x307_25ms_Control_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_SWT_CAN_0x307_25ms_Control(uint8_T rtu_Set_0x305_Send_Req); + +#endif /* RTW_HEADER_CAN_0x307_25ms_Control_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c new file mode 100644 index 0000000..0f9d350 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c @@ -0,0 +1,33 @@ +/* + * File: Get_0x309_CRC_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "Get_0x309_CRC_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/Get_0x309_CRC_10ms' */ +void P417_SWTR_Ap_Get_0x309_CRC_10ms(uint8_T rtu_Get_SteerWhlTouchBdRiChks) +{ + /* Gain: '/Gain' */ + RTE_Set_CAN_SteerWhlTouchBdRiChks(rtu_Get_SteerWhlTouchBdRiChks); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.h new file mode 100644 index 0000000..e5033fe --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.h @@ -0,0 +1,34 @@ +/* + * File: Get_0x309_CRC_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_Get_0x309_CRC_10ms_h_ +#define RTW_HEADER_Get_0x309_CRC_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_SWTR_Ap_Get_0x309_CRC_10ms(uint8_T + rtu_Get_SteerWhlTouchBdRiChks); + +#endif /* RTW_HEADER_Get_0x309_CRC_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c new file mode 100644 index 0000000..b0d6247 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.c @@ -0,0 +1,150 @@ +/* + * File: LED_Control_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "LED_Control_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/LED_Control_10ms' */ +void P417_SWTR_App_LED_Control_10ms(uint8_T rtu_ActvnOfSteerWhlIllmn_after_, + uint8_T rtu_Day1_Night0_Mode_after_hand, uint8_T rtu_IntrBriSts_after_handle, + DW_LED_Control_10ms_P417_SWTR_T *localDW) +{ + uint32_T rtb_NightSwitch; + + /* MultiPortSwitch: '/Night Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Night1' + * Constant: '/Night10' + * Constant: '/Night11' + * Constant: '/Night12' + * Constant: '/Night13' + * Constant: '/Night14' + * Constant: '/Night15' + * Constant: '/Night16' + * Constant: '/Night2' + * Constant: '/Night3' + * Constant: '/Night4' + * Constant: '/Night5' + * Constant: '/Night6' + * Constant: '/Night7' + * Constant: '/Night8' + * Constant: '/Night9' + * Sum: '/Add' + * UnitDelay: '/Unit Delay' + */ + switch ((uint8_T)(rtu_IntrBriSts_after_handle + 1U)) { + case 1: + rtb_NightSwitch = 625U; + break; + + case 2: + rtb_NightSwitch = 729U; + break; + + case 3: + rtb_NightSwitch = 937U; + break; + + case 4: + rtb_NightSwitch = 1146U; + break; + + case 5: + rtb_NightSwitch = 1354U; + break; + + case 6: + rtb_NightSwitch = 1563U; + break; + + case 7: + rtb_NightSwitch = 1875U; + break; + + case 8: + rtb_NightSwitch = 2292U; + break; + + case 9: + rtb_NightSwitch = 2813U; + break; + + case 10: + rtb_NightSwitch = 3333U; + break; + + case 11: + rtb_NightSwitch = 4063U; + break; + + case 12: + rtb_NightSwitch = 4896U; + break; + + case 13: + rtb_NightSwitch = 5938U; + break; + + case 14: + rtb_NightSwitch = 7188U; + break; + + case 15: + rtb_NightSwitch = 8646U; + break; + + case 16: + rtb_NightSwitch = 10417U; + break; + + default: + rtb_NightSwitch = localDW->UnitDelay_DSTATE; + break; + } + + /* End of MultiPortSwitch: '/Night Switch' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/Off' + */ + if (rtu_ActvnOfSteerWhlIllmn_after_ > 0) { + /* Switch: '/Switch1' incorporates: + * Constant: '/Day' + */ + if (rtu_Day1_Night0_Mode_after_hand > 0) { + RTE_Set_illumination_BL_PWM(100000U); + } else { + RTE_Set_illumination_BL_PWM(rtb_NightSwitch); + } + + /* End of Switch: '/Switch1' */ + } else { + RTE_Set_illumination_BL_PWM(0U); + } + + /* End of Switch: '/Switch' */ + + /* Update for UnitDelay: '/Unit Delay' */ + localDW->UnitDelay_DSTATE = rtb_NightSwitch; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.h new file mode 100644 index 0000000..7019f16 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/LED_Control_10ms.h @@ -0,0 +1,40 @@ +/* + * File: LED_Control_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_LED_Control_10ms_h_ +#define RTW_HEADER_LED_Control_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Block states (auto storage) for system '/LED_Control_10ms' */ +typedef struct { + uint32_T UnitDelay_DSTATE; /* '/Unit Delay' */ +} DW_LED_Control_10ms_P417_SWTR_T; + +extern void P417_SWTR_App_LED_Control_10ms(uint8_T + rtu_ActvnOfSteerWhlIllmn_after_, uint8_T rtu_Day1_Night0_Mode_after_hand, + uint8_T rtu_IntrBriSts_after_handle, DW_LED_Control_10ms_P417_SWTR_T *localDW); + +#endif /* RTW_HEADER_LED_Control_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.bat b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.bat new file mode 100644 index 0000000..6db371c --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.bat @@ -0,0 +1,12 @@ +set MATLAB=D:\MATLAB\R2017b + +cd . + +if "%1"=="" ("D:\MATLAB\R2017b\bin\win64\gmake" -f P417_SWTR_App.mk all) else ("D:\MATLAB\R2017b\bin\win64\gmake" -f P417_SWTR_App.mk %1) +@if errorlevel 1 goto error_exit + +exit /B 0 + +:error_exit +echo The make command returned an error of %errorlevel% +An_error_occurred_during_the_call_to_make diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c new file mode 100644 index 0000000..7ea5e13 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.c @@ -0,0 +1,454 @@ +/* + * File: P417_SWTR_App.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Block signals (auto storage) */ +B_P417_SWTR_App_T P417_SWTR_App_B; + +/* Block states (auto storage) */ +DW_P417_SWTR_App_T P417_SWTR_App_DW; + +/* Real-time model */ +RT_MODEL_P417_SWTR_App_T P417_SWTR_App_M_; +RT_MODEL_P417_SWTR_App_T *const P417_SWTR_App_M = &P417_SWTR_App_M_; + +/* Model step function */ +void P417_SWTR_App_step(void) +{ + uint8_T Switch; + uint8_T Switch_p; + uint8_T tmp; + + /* S-Function (fcncallgen): '/Function-Call Generator' incorporates: + * Chart: '/Task Scheduler' + */ + /* Chart: '/Task Scheduler' incorporates: + * Inport: '/In1' + * Inport: '/In10' + * Inport: '/In11' + * Inport: '/In12' + * Inport: '/In13' + * Inport: '/In17' + * Inport: '/In18' + * Inport: '/In19' + * Inport: '/In20' + * Inport: '/In21' + * Inport: '/In22' + * Inport: '/In23' + * Inport: '/In24' + * Inport: '/In3' + * Inport: '/In4' + * Inport: '/In5' + * Inport: '/In6' + * Inport: '/In7' + * Inport: '/In8' + * Inport: '/In9' + * Switch: '/Switch1' + */ + if (P417_SWTR_App_DW.temporalCounter_i1 < 2) { + P417_SWTR_App_DW.temporalCounter_i1++; + } + + if (P417_SWTR_App_DW.temporalCounter_i2 < 10) { + P417_SWTR_App_DW.temporalCounter_i2++; + } + + if (P417_SWTR_App_DW.temporalCounter_i3 < 20) { + P417_SWTR_App_DW.temporalCounter_i3++; + } + + if (P417_SWTR_App_DW.temporalCounter_i4 < 25) { + P417_SWTR_App_DW.temporalCounter_i4++; + } + + if (P417_SWTR_App_DW.temporalCounter_i5 < 1000) { + P417_SWTR_App_DW.temporalCounter_i5++; + } + + if (P417_SWTR_App_DW.temporalCounter_i1 == 2) { + /* Outputs for Function Call SubSystem: '/TouchBoard_up_handle_4ms' */ + P417_S_TouchBoard_up_handle_4ms(RTE_Get_TouchBoard_Up_Sts(), + &P417_SWTR_App_B.TouchBoard_Up_Sts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_up_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Down_handle_4ms' */ + P417_TouchBoard_Down_handle_4ms(RTE_Get_TouchBoard_Down_Sts(), + &P417_SWTR_App_B.TouchBoard_Down_Sts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_Down_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Left_handle_4ms' */ + P417_TouchBoard_Left_handle_4ms(RTE_Get_TouchBoard_Left_Sts(), + &P417_SWTR_App_B.TouchBoard_Left_Sts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_Left_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Right_handle_4ms' */ + P41_TouchBoard_Right_handle_4ms(RTE_Get_TouchBoard_Right_Sts(), + &P417_SWTR_App_B.TouchBoard_Right_Sts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_Right_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Center_handle_4ms' */ + P4_TouchBoard_Center_handle_4ms(RTE_Get_TouchBoard_Center_Sts(), + &P417_SWTR_App_B.TouchBoard_Center_Sts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_Center_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_VOICE_handle_4ms' */ + P41_TouchBoard_VOICE_handle_4ms(RTE_Get_TouchBoard_VOICE1_Sts(), + RTE_Get_Voice_XY_trig(), &P417_SWTR_App_B.TouchBoard_VOICE_Sts_input, + &P417_SWTR_App_B.Voice_XY_trig_in); + + /* End of Outputs for SubSystem: '/TouchBoard_VOICE_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_MENU_handle_4ms' */ + P417_TouchBoard_MENU_handle_4ms(RTE_Get_TouchBoard_MENU1_Sts(), + RTE_Get_Menu_XY_trig(), &P417_SWTR_App_B.TouchBoard_MENU_Sts_input, + &P417_SWTR_App_B.Menu_XY_trig_in); + + /* End of Outputs for SubSystem: '/TouchBoard_MENU_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_VOL_handle_4ms' */ + P417__TouchBoard_VOL_handle_4ms(RTE_Get_TouchBoard_VOL1_Sts(), + RTE_Get_Vol_XY_trig(), RTE_Get_Pad_XY_trig(), + &P417_SWTR_App_B.TouchBoard_VOL_Sts_input, &P417_SWTR_App_B.Vol_XY_trig_in, + &P417_SWTR_App_B.Pad_XY_trig_in); + + /* End of Outputs for SubSystem: '/TouchBoard_VOL_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Left_Right_Slide_handle_4ms' */ + TouchBoard_Left_Right_Slide_han(RTE_Get_TouchBoard_Left_Right_Slide_Sts(), + &P417_SWTR_App_B.TouchBoard_Left_Right_Slide_Sts); + + /* End of Outputs for SubSystem: '/TouchBoard_Left_Right_Slide_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Up_Down_Slide_handle_4ms' */ + TouchBoard_Up_Down_Slide_handle(RTE_Get_TouchBoard_Up_Down_Slide_Sts(), + RTE_Get_SldVolCtrlSts(), &P417_SWTR_App_B.TouchBoard_Up_Down_Slide_Sts_in, + &P417_SWTR_App_B.SldVolCtrlSts_input); + + /* End of Outputs for SubSystem: '/TouchBoard_Up_Down_Slide_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoardXY_handle_4ms' */ + P417_SW_TouchBoardXY_handle_4ms(RTE_Get_TouchBoard_XY_Sts(), + P417_SWTR_App_B.TouchBoard_VOICE_Sts_input, + P417_SWTR_App_B.TouchBoard_VOL_Sts_input, + P417_SWTR_App_B.TouchBoard_MENU_Sts_input, + RTE_Get_TouchBoard_XY_Touch_And_Below_1N(), + &P417_SWTR_App_B.MultiportSwitch, &P417_SWTR_App_B.XY_Touch_And_Below_1N, + &P417_SWTR_App_B.TouchBoardXY_handle_4ms, + &P417_SWTR_App_DW.TouchBoardXY_handle_4ms); + + /* End of Outputs for SubSystem: '/TouchBoardXY_handle_4ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_0x307_Send_And_ACT_Req_4ms' */ + TouchBoard_0x307_Send_And_ACT_R(P417_SWTR_App_B.TouchBoard_Up_Sts_input, + P417_SWTR_App_B.TouchBoard_Down_Sts_input, + P417_SWTR_App_B.TouchBoard_Left_Sts_input, + P417_SWTR_App_B.TouchBoard_Right_Sts_input, + P417_SWTR_App_B.TouchBoard_Center_Sts_input, + P417_SWTR_App_B.TouchBoard_Up_Down_Slide_Sts_in, + P417_SWTR_App_B.TouchBoard_Left_Right_Slide_Sts, + P417_SWTR_App_B.TouchBoard_MENU_Sts_input, + P417_SWTR_App_B.TouchBoard_VOICE_Sts_input, + P417_SWTR_App_B.TouchBoard_VOL_Sts_input, + &P417_SWTR_App_B.DataTypeConversion); + + /* End of Outputs for SubSystem: '/TouchBoard_0x307_Send_And_ACT_Req_4ms' */ + } + + if (P417_SWTR_App_DW.temporalCounter_i2 == 10) { + /* Outputs for Function Call SubSystem: '/illumination_control_10ms' */ + P417__illumination_control_10ms(RTE_Get_CAN_ActvnOfSteerWhlIllmn(), + RTE_Get_CAN_IhuPrivateDHUCanFr01_Frame_Timeout(), &Switch_p, + &P417_SWTR_App_B.illumination_control_10ms, + &P417_SWTR_App_DW.illumination_control_10ms); + + /* End of Outputs for SubSystem: '/illumination_control_10ms' */ + + /* Outputs for Function Call SubSystem: '/Day_Night_handle_10ms' */ + + /* Chart: '/Fault_Debounce_Chart' incorporates: + * Inport: '/In1' + * Inport: '/In3' + */ + P417_SWTR__Fault_Debounce_Chart + (RTE_Get_CAN_IhuPrivateDHUCanFr01_Frame_Timeout(), + &P417_SWTR_App_B.Fault_confirmed_i, + &P417_SWTR_App_DW.sf_Fault_Debounce_Chart, 3U, 3U); + + /* End of Outputs for SubSystem: '/Day_Night_handle_10ms' */ + + /* Outputs for Function Call SubSystem: '/IntrBriSts_handle_10ms' */ + /* Chart: '/Fault_Debounce_Chart' incorporates: + * Inport: '/In3' + */ + P417_SWTR__Fault_Debounce_Chart + (RTE_Get_CAN_IhuPrivateDHUCanFr01_Frame_Timeout(), + &P417_SWTR_App_B.Fault_confirmed, + &P417_SWTR_App_DW.sf_Fault_Debounce_Chart_d, 3U, 3U); + + /* Switch: '/Switch' incorporates: + * Inport: '/In16' + * UnitDelay: '/Unit Delay' + */ + if (P417_SWTR_App_B.Fault_confirmed > 0) { + Switch = P417_SWTR_App_DW.UnitDelay_DSTATE; + } else { + Switch = RTE_Get_CAN_IntrBriSts(); + } + + /* End of Switch: '/Switch' */ + + /* Update for UnitDelay: '/Unit Delay' */ + P417_SWTR_App_DW.UnitDelay_DSTATE = Switch; + + /* End of Outputs for SubSystem: '/IntrBriSts_handle_10ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_X_handle_10ms' */ + P417_S_TouchBoard_X_handle_10ms(P417_SWTR_App_B.Pad_XY_trig_in, + P417_SWTR_App_B.Voice_XY_trig_in, P417_SWTR_App_B.Vol_XY_trig_in, + P417_SWTR_App_B.Menu_XY_trig_in, P417_SWTR_App_B.TouchBoard_Up_Sts_input, + P417_SWTR_App_B.TouchBoard_Down_Sts_input, + P417_SWTR_App_B.TouchBoard_Left_Sts_input, + P417_SWTR_App_B.TouchBoard_Right_Sts_input, + P417_SWTR_App_B.TouchBoard_Center_Sts_input, + &P417_SWTR_App_B.TouchBoard_X_handle_10ms); + + /* End of Outputs for SubSystem: '/TouchBoard_X_handle_10ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_Y_handle_10ms' */ + P417_S_TouchBoard_Y_handle_10ms(P417_SWTR_App_B.Pad_XY_trig_in, + P417_SWTR_App_B.Voice_XY_trig_in, P417_SWTR_App_B.Vol_XY_trig_in, + P417_SWTR_App_B.Menu_XY_trig_in, P417_SWTR_App_B.TouchBoard_Up_Sts_input, + P417_SWTR_App_B.TouchBoard_Down_Sts_input, + P417_SWTR_App_B.TouchBoard_Left_Sts_input, + P417_SWTR_App_B.TouchBoard_Right_Sts_input, + P417_SWTR_App_B.TouchBoard_Center_Sts_input, + &P417_SWTR_App_B.TouchBoard_Y_handle_10ms); + + /* End of Outputs for SubSystem: '/TouchBoard_Y_handle_10ms' */ + + /* Outputs for Function Call SubSystem: '/Day_Night_handle_10ms' */ + /* Switch: '/Switch' incorporates: + * Constant: '/ Default' + * Inport: '/In2' + */ + if (P417_SWTR_App_B.Fault_confirmed_i > 0) { + tmp = 0U; + } else { + tmp = RTE_Get_CAN_TwliBriSts(); + } + + /* End of Switch: '/Switch' */ + + /* Outputs for Function Call SubSystem: '/LED_Control_10ms' */ + P417_SWTR_App_LED_Control_10ms(Switch_p, (uint8_T)(tmp > 0), Switch, + &P417_SWTR_App_DW.LED_Control_10ms); + + /* End of Outputs for SubSystem: '/LED_Control_10ms' */ + + /* End of Outputs for SubSystem: '/Day_Night_handle_10ms' */ + + /* Outputs for Function Call SubSystem: '/Set_0x309_RC_10ms' */ + P417_SWTR_App_Set_0x309_RC_10ms(P417_SWTR_App_B.Gain1); + + /* End of Outputs for SubSystem: '/Set_0x309_RC_10ms' */ + + /* Outputs for Function Call SubSystem: '/Get_0x309_CRC_10ms' */ + P417_SWTR_Ap_Get_0x309_CRC_10ms(RTE_Get_TouchBoard_CRC()); + + /* End of Outputs for SubSystem: '/Get_0x309_CRC_10ms' */ + + /* Outputs for Function Call SubSystem: '/TouchBoard_0x309_Send_And_ACT_Req_10ms' */ + TouchBoard_0x309_Send_And_ACT_R(P417_SWTR_App_B.XY_Touch_And_Below_1N, + &P417_SWTR_App_B.DataTypeConversion_g, &P417_SWTR_App_B.Gain1); + + /* End of Outputs for SubSystem: '/TouchBoard_0x309_Send_And_ACT_Req_10ms' */ + } + + if (P417_SWTR_App_DW.temporalCounter_i3 == 20) { + /* Outputs for Function Call SubSystem: '/Set_Diag_20ms' */ + P417_SWTR_App_Set_Diag_20ms(&P417_SWTR_App_ConstB.Set_Diag_20ms); + + /* End of Outputs for SubSystem: '/Set_Diag_20ms' */ + + /* Outputs for Function Call SubSystem: '/ACT_control_20ms' */ + P417_SWTR_App_ACT_control_20ms(P417_SWTR_App_B.DataTypeConversion, + P417_SWTR_App_B.DataTypeConversion_g); + + /* End of Outputs for SubSystem: '/ACT_control_20ms' */ + } + + if (P417_SWTR_App_DW.temporalCounter_i4 == 25) { + /* Outputs for Function Call SubSystem: '/CAN_0x307_25ms_Control' */ + P417_SWT_CAN_0x307_25ms_Control(P417_SWTR_App_B.DataTypeConversion); + + /* End of Outputs for SubSystem: '/CAN_0x307_25ms_Control' */ + } + + if (P417_SWTR_App_DW.temporalCounter_i5 == 1000) { + /* Outputs for Function Call SubSystem: '/CAN_0x307_1000ms_Control' */ + P417_S_CAN_0x307_1000ms_Control(P417_SWTR_App_B.DataTypeConversion); + + /* End of Outputs for SubSystem: '/CAN_0x307_1000ms_Control' */ + } + + if (P417_SWTR_App_DW.temporalCounter_i1 == 2) { + P417_SWTR_App_DW.temporalCounter_i1 = 0U; + } + + if (P417_SWTR_App_DW.temporalCounter_i2 == 10) { + P417_SWTR_App_DW.temporalCounter_i2 = 0U; + } + + if (P417_SWTR_App_DW.temporalCounter_i3 == 20) { + P417_SWTR_App_DW.temporalCounter_i3 = 0U; + } + + if (P417_SWTR_App_DW.temporalCounter_i4 == 25) { + P417_SWTR_App_DW.temporalCounter_i4 = 0U; + } + + if (P417_SWTR_App_DW.temporalCounter_i5 == 1000) { + P417_SWTR_App_DW.temporalCounter_i5 = 0U; + } + + /* End of Chart: '/Task Scheduler' */ + /* End of Outputs for S-Function (fcncallgen): '/Function-Call Generator' */ + + /* Gain: '/Gain4' */ + RTE_Set_CAN_RiMFctActSgCe(P417_SWTR_App_B.TouchBoard_Center_Sts_input); + + /* Gain: '/Gain1' */ + RTE_Set_CAN_RiMFctActSgDn(P417_SWTR_App_B.TouchBoard_Down_Sts_input); + + /* Gain: '/Gain2' */ + RTE_Set_CAN_RiMFctActSgLe(P417_SWTR_App_B.TouchBoard_Left_Sts_input); + + /* Gain: '/Gain3' */ + RTE_Set_CAN_RiMFctActSgRi(P417_SWTR_App_B.TouchBoard_Right_Sts_input); + + /* Gain: '/Gain' */ + RTE_Set_CAN_RiMFctActSgUp(P417_SWTR_App_B.TouchBoard_Up_Sts_input); + + /* Gain: '/Gain5' */ + RTE_Set_CAN_SteerWhlTouchBdVoice(P417_SWTR_App_B.TouchBoard_VOICE_Sts_input); + + /* Gain: '/Gain9' */ + RTE_Set_CAN_SwpLeRiStsRi(P417_SWTR_App_B.TouchBoard_Left_Right_Slide_Sts); + + /* Gain: '/Gain8' */ + RTE_Set_CAN_SwpUpDwnStsRi(P417_SWTR_App_B.TouchBoard_Up_Down_Slide_Sts_in); + + /* Gain: '/Gain6' */ + RTE_Set_CAN_SteerWhlTouchBdMenu(P417_SWTR_App_B.TouchBoard_MENU_Sts_input); + + /* Gain: '/Gain7' */ + RTE_Set_CAN_SteerWhlTouchBdDn(P417_SWTR_App_B.TouchBoard_VOL_Sts_input); + + /* Gain: '/Gain10' */ + RTE_Set_CAN_SteerWhlTouchBdRiSteerWhlTouchBdSts + (P417_SWTR_App_B.MultiportSwitch); + + /* Gain: '/Gain11' */ + RTE_Set_CAN_SldVolCtrlSts(P417_SWTR_App_B.SldVolCtrlSts_input); +} + +/* Model initialize function */ +void P417_SWTR_App_initialize(void) +{ + /* Registration code */ + + /* initialize error status */ + rtmSetErrorStatus(P417_SWTR_App_M, (NULL)); + + /* block I/O */ + (void) memset(((void *) &P417_SWTR_App_B), 0, + sizeof(B_P417_SWTR_App_T)); + + /* states (dwork) */ + (void) memset((void *)&P417_SWTR_App_DW, 0, + sizeof(DW_P417_SWTR_App_T)); + + /* SystemInitialize for S-Function (fcncallgen): '/Function-Call Generator' incorporates: + * Chart: '/Task Scheduler' + */ + /* Chart: '/Task Scheduler' */ + /* Chart: '/Task Scheduler' */ + P417_SWTR_App_DW.temporalCounter_i1 = 0U; + P417_SWTR_App_DW.temporalCounter_i2 = 0U; + P417_SWTR_App_DW.temporalCounter_i3 = 0U; + P417_SWTR_App_DW.temporalCounter_i4 = 0U; + P417_SWTR_App_DW.temporalCounter_i5 = 0U; + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/illumination_control_10ms' + */ + illumination_control_10ms_Init(&P417_SWTR_App_B.illumination_control_10ms, + &P417_SWTR_App_DW.illumination_control_10ms); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/Day_Night_handle_10ms' + */ + /* SystemInitialize for Chart: '/Fault_Debounce_Chart' */ + P417__Fault_Debounce_Chart_Init(&P417_SWTR_App_B.Fault_confirmed_i, + &P417_SWTR_App_DW.sf_Fault_Debounce_Chart); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/IntrBriSts_handle_10ms' + */ + /* SystemInitialize for Chart: '/Fault_Debounce_Chart' */ + P417__Fault_Debounce_Chart_Init(&P417_SWTR_App_B.Fault_confirmed, + &P417_SWTR_App_DW.sf_Fault_Debounce_Chart_d); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/TouchBoard_X_handle_10ms' + */ + P_TouchBoard_X_handle_10ms_Init(&P417_SWTR_App_B.TouchBoard_X_handle_10ms); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/TouchBoard_Y_handle_10ms' + */ + P_TouchBoard_Y_handle_10ms_Init(&P417_SWTR_App_B.TouchBoard_Y_handle_10ms); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/Set_Diag_20ms' + */ + P417_SWTR_Ap_Set_Diag_20ms_Init(&P417_SWTR_App_ConstB.Set_Diag_20ms); + + /* SystemInitialize for Chart: '/Task Scheduler' incorporates: + * SubSystem: '/TouchBoardXY_handle_4ms' + */ + P4_TouchBoardXY_handle_4ms_Init(&P417_SWTR_App_B.TouchBoardXY_handle_4ms); + + /* End of SystemInitialize for S-Function (fcncallgen): '/Function-Call Generator' */ +} + +/* Model terminate function */ +void P417_SWTR_App_terminate(void) +{ + /* (no terminate code required) */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.h b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.h new file mode 100644 index 0000000..2a01dd3 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.h @@ -0,0 +1,228 @@ +/* + * File: P417_SWTR_App.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_P417_SWTR_App_h_ +#define RTW_HEADER_P417_SWTR_App_h_ +#include +#include +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Child system includes */ +#include "ACT_control_20ms.h" +#include "CAN_0x307_1000ms_Control.h" +#include "CAN_0x307_25ms_Control.h" +#include "Get_0x309_CRC_10ms.h" +#include "LED_Control_10ms.h" +#include "Set_0x309_RC_10ms.h" +#include "Set_Diag_20ms.h" +#include "TouchBoardXY_handle_4ms.h" +#include "TouchBoard_0x307_Send_And_ACT_Req_4ms.h" +#include "TouchBoard_0x309_Send_And_ACT_Req_10ms.h" +#include "TouchBoard_Center_handle_4ms.h" +#include "TouchBoard_Down_handle_4ms.h" +#include "TouchBoard_Left_Right_Slide_handle_4ms.h" +#include "TouchBoard_Left_handle_4ms.h" +#include "TouchBoard_MENU_handle_4ms.h" +#include "TouchBoard_Right_handle_4ms.h" +#include "TouchBoard_Up_Down_Slide_handle_4ms.h" +#include "TouchBoard_VOICE_handle_4ms.h" +#include "TouchBoard_VOL_handle_4ms.h" +#include "TouchBoard_X_handle_10ms.h" +#include "TouchBoard_Y_handle_10ms.h" +#include "TouchBoard_up_handle_4ms.h" +#include "illumination_control_10ms.h" +#include "rt_sys_P417_SWTR_App_0.h" + +/* Macros for accessing real-time model data structure */ +#ifndef rtmGetErrorStatus +# define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) +#endif + +#ifndef rtmSetErrorStatus +# define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) +#endif + +/* Block signals (auto storage) */ +typedef struct { + uint8_T DataTypeConversion; /* '/Data Type Conversion' */ + uint8_T MultiportSwitch; /* '/Multiport Switch' */ + uint8_T XY_Touch_And_Below_1N; /* '/XY_Touch_And_Below_1N' */ + uint8_T TouchBoard_Up_Down_Slide_Sts_in;/* '/TouchBoard_Up_Down_Slide_Sts_input' */ + uint8_T SldVolCtrlSts_input; /* '/SldVolCtrlSts_input' */ + uint8_T TouchBoard_Left_Right_Slide_Sts;/* '/TouchBoard_Left_Right_Slide_Sts_input' */ + uint8_T TouchBoard_VOL_Sts_input; /* '/TouchBoard_VOL_Sts_input' */ + uint8_T Vol_XY_trig_in; /* '/Vol_XY_trig_in' */ + uint8_T Pad_XY_trig_in; /* '/Pad_XY_trig_in' */ + uint8_T TouchBoard_MENU_Sts_input; /* '/TouchBoard_MENU_Sts_input' */ + uint8_T Menu_XY_trig_in; /* '/Menu_XY_trig_in' */ + uint8_T TouchBoard_VOICE_Sts_input; /* '/TouchBoard_VOICE_Sts_input' */ + uint8_T Voice_XY_trig_in; /* '/Voice_XY_trig_in' */ + uint8_T TouchBoard_Center_Sts_input; /* '/TouchBoard_Center_Sts_input' */ + uint8_T TouchBoard_Right_Sts_input; /* '/TouchBoard_Right_Sts_input' */ + uint8_T TouchBoard_Left_Sts_input; /* '/TouchBoard_Left_Sts_input' */ + uint8_T TouchBoard_Down_Sts_input; /* '/TouchBoard_Down_Sts_input' */ + uint8_T TouchBoard_Up_Sts_input; /* '/TouchBoard_Up_Sts_input' */ + uint8_T DataTypeConversion_g; /* '/Data Type Conversion' */ + uint8_T Gain1; /* '/Gain1' */ + uint8_T Fault_confirmed; /* '/Fault_Debounce_Chart' */ + uint8_T Fault_confirmed_i; /* '/Fault_Debounce_Chart' */ + B_TouchBoardXY_handle_4ms_P41_T TouchBoardXY_handle_4ms;/* '/TouchBoardXY_handle_4ms' */ + B_TouchBoard_Y_handle_10ms_P4_T TouchBoard_Y_handle_10ms;/* '/TouchBoard_Y_handle_10ms' */ + B_TouchBoard_X_handle_10ms_P4_T TouchBoard_X_handle_10ms;/* '/TouchBoard_X_handle_10ms' */ + B_illumination_control_10ms_P_T illumination_control_10ms;/* '/illumination_control_10ms' */ +} B_P417_SWTR_App_T; + +/* Block states (auto storage) for system '' */ +typedef struct { + uint16_T temporalCounter_i5; /* '/Task Scheduler' */ + uint8_T UnitDelay_DSTATE; /* '/Unit Delay' */ + uint8_T temporalCounter_i1; /* '/Task Scheduler' */ + uint8_T temporalCounter_i2; /* '/Task Scheduler' */ + uint8_T temporalCounter_i3; /* '/Task Scheduler' */ + uint8_T temporalCounter_i4; /* '/Task Scheduler' */ + DW_TouchBoardXY_handle_4ms_P4_T TouchBoardXY_handle_4ms;/* '/TouchBoardXY_handle_4ms' */ + DW_LED_Control_10ms_P417_SWTR_T LED_Control_10ms;/* '/LED_Control_10ms' */ + DW_Fault_Debounce_Chart_P417__T sf_Fault_Debounce_Chart_d;/* '/Fault_Debounce_Chart' */ + DW_Fault_Debounce_Chart_P417__T sf_Fault_Debounce_Chart;/* '/Fault_Debounce_Chart' */ + DW_illumination_control_10ms__T illumination_control_10ms;/* '/illumination_control_10ms' */ +} DW_P417_SWTR_App_T; + +/* Invariant block signals (auto storage) */ +typedef struct { + ConstB_Set_Diag_20ms_P417_SWT_T Set_Diag_20ms;/* '/Set_Diag_20ms' */ +} ConstB_P417_SWTR_App_T; + +/* Real-time Model Data Structure */ +struct tag_RTM_P417_SWTR_App_T { + const char_T *errorStatus; +}; + +/* Block signals (auto storage) */ +extern B_P417_SWTR_App_T P417_SWTR_App_B; + +/* Block states (auto storage) */ +extern DW_P417_SWTR_App_T P417_SWTR_App_DW; +extern const ConstB_P417_SWTR_App_T P417_SWTR_App_ConstB;/* constant block i/o */ + +/* Model entry point functions */ +extern void P417_SWTR_App_initialize(void); +extern void P417_SWTR_App_step(void); +extern void P417_SWTR_App_terminate(void); + +/* Real-time Model object */ +extern RT_MODEL_P417_SWTR_App_T *const P417_SWTR_App_M; + +/*- + * The generated code includes comments that allow you to trace directly + * back to the appropriate location in the model. The basic format + * is /block_name, where system is the system number (uniquely + * assigned by Simulink) and block_name is the name of the block. + * + * Use the MATLAB hilite_system command to trace the generated code back + * to the model. For example, + * + * hilite_system('') - opens system 3 + * hilite_system('/Kp') - opens and selects block Kp which resides in S3 + * + * Here is the system hierarchy for this model + * + * '' : 'P417_SWTR_App' + * '' : 'P417_SWTR_App/SWTL_Functions' + * '' : 'P417_SWTR_App/Signal_Front_handle' + * '' : 'P417_SWTR_App/Task Scheduler' + * '' : 'P417_SWTR_App/SWTL_Functions/ACT_control_20ms' + * '' : 'P417_SWTR_App/SWTL_Functions/CAN_0x307_1000ms_Control' + * '' : 'P417_SWTR_App/SWTL_Functions/CAN_0x307_25ms_Control' + * '' : 'P417_SWTR_App/SWTL_Functions/Get_0x309_CRC_10ms' + * '' : 'P417_SWTR_App/SWTL_Functions/LED_Control_10ms' + * '' : 'P417_SWTR_App/SWTL_Functions/Set_0x309_RC_10ms' + * '' : 'P417_SWTR_App/SWTL_Functions/Set_Diag_20ms' + * '' : 'P417_SWTR_App/SWTL_Functions/ACT_control_20ms/Compare To Zero' + * '' : 'P417_SWTR_App/SWTL_Functions/ACT_control_20ms/Compare To Zero1' + * '' : 'P417_SWTR_App/Signal_Front_handle/Day_Night_handle_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/IntrBriSts_handle_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x309_Send_And_ACT_Req_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Center_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Down_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Left_Right_Slide_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Left_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_MENU_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Right_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Up_Down_Slide_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_VOICE_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_VOL_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_up_handle_4ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/illumination_control_10ms' + * '' : 'P417_SWTR_App/Signal_Front_handle/Day_Night_handle_10ms/Fault Debounce' + * '' : 'P417_SWTR_App/Signal_Front_handle/Day_Night_handle_10ms/Fault Debounce/Fault_Debounce_Chart' + * '' : 'P417_SWTR_App/Signal_Front_handle/IntrBriSts_handle_10ms/Fault Debounce' + * '' : 'P417_SWTR_App/Signal_Front_handle/IntrBriSts_handle_10ms/Fault Debounce/Fault_Debounce_Chart' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms/Compare To Constant' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms/Compare To Constant1' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms/Compare To Constant2' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms/Compare To Constant3' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoardXY_handle_4ms/Slect_Touch' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero1' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero2' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero3' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero4' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero5' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero6' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero7' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero8' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x307_Send_And_ACT_Req_4ms/Compare To Zero9' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_0x309_Send_And_ACT_Req_10ms/Compare To Zero4' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant1' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant2' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant3' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant4' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant5' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant6' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant7' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Compare To Constant8' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Subsystem_selX' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_X_handle_10ms/Subsystem_selX/Slect_X' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant1' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant2' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant3' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant4' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant5' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant6' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant7' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Compare To Constant8' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Subsyste_selY' + * '' : 'P417_SWTR_App/Signal_Front_handle/TouchBoard_Y_handle_10ms/Subsyste_selY/Slect_X' + * '' : 'P417_SWTR_App/Signal_Front_handle/illumination_control_10ms/Fault Debounce' + * '' : 'P417_SWTR_App/Signal_Front_handle/illumination_control_10ms/Fault Debounce/Fault_Debounce_Chart' + */ +#endif /* RTW_HEADER_P417_SWTR_App_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.mk b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.mk new file mode 100644 index 0000000..6731229 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App.mk @@ -0,0 +1,358 @@ +########################################################################### +## Makefile generated for Simulink model 'P417_SWTR_App'. +## +## Makefile : P417_SWTR_App.mk +## Generated on : Sun Jun 25 21:59:21 2023 +## MATLAB Coder version: 3.4 (R2017b) +## +## Build Info: +## +## Final product: $(RELATIVE_PATH_TO_ANCHOR)/P417_SWTR_App.exe +## Product type : executable +## Build type : Top-Level Standalone Executable +## +########################################################################### + +########################################################################### +## MACROS +########################################################################### + +# Macro Descriptions: +# PRODUCT_NAME Name of the system to build +# MAKEFILE Name of this makefile +# COMPUTER Computer type. See the MATLAB "computer" command. +# MODELREF_LINK_RSPFILE Include paths for the model reference build +# GEN_LINKER_RESPONSE Command to generate a linker response file +# CMD_FILE Command file + +PRODUCT_NAME = P417_SWTR_App +MAKEFILE = P417_SWTR_App.mk +COMPUTER = PCWIN64 +MATLAB_ROOT = D:/MATLAB/R2017b +MATLAB_BIN = D:/MATLAB/R2017b/bin +MATLAB_ARCH_BIN = $(MATLAB_BIN)/win64 +MASTER_ANCHOR_DIR = +START_DIR = G:/WorkSpace/Ongoing/solve_RC/20230425/P417_SWTR_App +ARCH = win64 +SOLVER = +SOLVER_OBJ = +CLASSIC_INTERFACE = 0 +TGT_FCN_LIB = ISO_C +MODEL_HAS_DYNAMICALLY_LOADED_SFCNS = 0 +MODELREF_LINK_RSPFILE_NAME = P417_SWTR_App_ref.rsp +RELATIVE_PATH_TO_ANCHOR = .. +MODELREF_LINK_RSPFILE = P417_SWTR_App_ref.rsp +GEN_LINKER_RESPONSE = $(MATLAB_ARCH_BIN)/createResponseFile.exe 1 +CMD_FILE = $(PRODUCT_NAME).rsp +C_STANDARD_OPTS = +CPP_STANDARD_OPTS = + +########################################################################### +## TOOLCHAIN SPECIFICATIONS +########################################################################### + +# Toolchain Name: LCC-win64 v2.4.1 | gmake (64-bit Windows) +# Supported Version(s): 2.4.1 +# ToolchainInfo Version: R2017b +# Specification Revision: 1.0 +# + +#----------- +# MACROS +#----------- + +SHELL = cmd +LCC_ROOT = $(MATLAB_ROOT)/sys/lcc64/lcc64 +LCC_BUILDLIB = $(LCC_ROOT)/bin/buildlib +LCC_LIB = $(LCC_ROOT)/lib64 +MW_EXTERNLIB_DIR = $(MATLAB_ROOT)/extern/lib/win64/microsoft +MW_LIB_DIR = $(MATLAB_ROOT)/lib/win64 +TOOLCHAIN_INCLUDES = -I$(LCC_ROOT)/include64 +MEX_OPTS_FILE = $(MATLAB_ROOT/rtw/c/tools/lcc-win64.xml + +TOOLCHAIN_SRCS = +TOOLCHAIN_INCS = +TOOLCHAIN_LIBS = + +#------------------------ +# BUILD TOOL COMMANDS +#------------------------ + +# C Compiler: Lcc-win64 C Compiler +CC_PATH = $(LCC_ROOT)/bin +CC = "$(CC_PATH)/lcc64" + +# Linker: Lcc-win64 Linker +LD_PATH = $(LCC_ROOT)/bin +LD = "$(LD_PATH)/lcclnk64" + +# Archiver: Lcc-win64 Archiver +AR_PATH = $(LCC_ROOT)/bin +AR = "$(AR_PATH)/lcclib64" + +# MEX Tool: MEX Tool +MEX_PATH = $(MATLAB_ARCH_BIN) +MEX = "$(MEX_PATH)/mex" + +# Download: Download +DOWNLOAD = + +# Execute: Execute +EXECUTE = $(PRODUCT) + +# Builder: GMAKE Utility +MAKE_PATH = %MATLAB%\bin\win64 +MAKE = "$(MAKE_PATH)/gmake" + + +#------------------------- +# Directives/Utilities +#------------------------- + +CDEBUG = -g +C_OUTPUT_FLAG = -Fo +LDDEBUG = +OUTPUT_FLAG = -o +ARDEBUG = +STATICLIB_OUTPUT_FLAG = /out: +MEX_DEBUG = -g +RM = @del /F +ECHO = @echo +MV = @move +RUN = + +#---------------------------------------- +# "Faster Builds" Build Configuration +#---------------------------------------- + +ARFLAGS = +CFLAGS = -c -w -noregistrylookup -nodeclspec -I$(LCC_ROOT)/include64 +DOWNLOAD_FLAGS = +EXECUTE_FLAGS = +LDFLAGS = -s -L$(LCC_LIB) $(LDFLAGS_ADDITIONAL) +MEX_CPPFLAGS = +MEX_CPPLDFLAGS = +MEX_CFLAGS = -win64 $(MEX_SRC) $(MEX_OPT_FILE)$(INCLUDES) -outdir $(RELATIVE_PATH_TO_ANCHOR) +MEX_LDFLAGS = LINKFLAGS="$$LINKFLAGS $(LDFLAGS_ADDITIONAL)" +MAKE_FLAGS = -f $(MAKEFILE) +SHAREDLIB_LDFLAGS = -dll -entry LibMain -s -L$(LCC_LIB) $(LDFLAGS_ADDITIONAL) $(DEF_FILE) + +#-------------------- +# File extensions +#-------------------- + +H_EXT = .h +OBJ_EXT = .obj +C_EXT = .c +EXE_EXT = .exe +SHAREDLIB_EXT = .dll +STATICLIB_EXT = .lib +MEX_EXT = .mexw64 +MAKE_EXT = .mk + + +########################################################################### +## OUTPUT INFO +########################################################################### + +PRODUCT = $(RELATIVE_PATH_TO_ANCHOR)/P417_SWTR_App.exe +PRODUCT_TYPE = "executable" +BUILD_TYPE = "Top-Level Standalone Executable" + +########################################################################### +## INCLUDE PATHS +########################################################################### + +INCLUDES_BUILDINFO = -I$(START_DIR) -I$(MATLAB_ROOT)/simulink/include/sf_runtime -I$(START_DIR)/P417_SWTR_App_ert_rtw -I$(MATLAB_ROOT)/extern/include -I$(MATLAB_ROOT)/simulink/include -I$(MATLAB_ROOT)/rtw/c/src -I$(MATLAB_ROOT)/rtw/c/src/ext_mode/common -I$(MATLAB_ROOT)/rtw/c/ert + +INCLUDES = $(INCLUDES_BUILDINFO) + +########################################################################### +## DEFINES +########################################################################### + +DEFINES_BUILD_ARGS = -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0 -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 +DEFINES_IMPLIED = -DTID01EQ=0 +DEFINES_STANDARD = -DMODEL=P417_SWTR_App -DNUMST=1 -DNCSTATES=0 -DHAVESTDIO + +DEFINES = $(DEFINES_BUILD_ARGS) $(DEFINES_IMPLIED) $(DEFINES_STANDARD) + +########################################################################### +## SOURCE FILES +########################################################################### + +SRCS = $(START_DIR)/P417_SWTR_App_ert_rtw/ACT_control_20ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/CAN_0x307_1000ms_Control.c $(START_DIR)/P417_SWTR_App_ert_rtw/CAN_0x307_25ms_Control.c $(START_DIR)/P417_SWTR_App_ert_rtw/Get_0x309_CRC_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/LED_Control_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/P417_SWTR_App.c $(START_DIR)/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c $(START_DIR)/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/illumination_control_10ms.c $(START_DIR)/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c $(START_DIR)/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c + +MAIN_SRC = $(MATLAB_ROOT)/rtw/c/src/common/rt_main.c + +ALL_SRCS = $(SRCS) $(MAIN_SRC) + +########################################################################### +## OBJECTS +########################################################################### + +OBJS = ACT_control_20ms.obj CAN_0x307_1000ms_Control.obj CAN_0x307_25ms_Control.obj Get_0x309_CRC_10ms.obj LED_Control_10ms.obj P417_SWTR_App.obj P417_SWTR_App_data.obj Set_0x309_RC_10ms.obj Set_Diag_20ms.obj TouchBoardXY_handle_4ms.obj TouchBoard_0x307_Send_And_ACT_Req_4ms.obj TouchBoard_0x309_Send_And_ACT_Req_10ms.obj TouchBoard_Center_handle_4ms.obj TouchBoard_Down_handle_4ms.obj TouchBoard_Left_Right_Slide_handle_4ms.obj TouchBoard_Left_handle_4ms.obj TouchBoard_MENU_handle_4ms.obj TouchBoard_Right_handle_4ms.obj TouchBoard_Up_Down_Slide_handle_4ms.obj TouchBoard_VOICE_handle_4ms.obj TouchBoard_VOL_handle_4ms.obj TouchBoard_X_handle_10ms.obj TouchBoard_Y_handle_10ms.obj TouchBoard_up_handle_4ms.obj illumination_control_10ms.obj rt_sys_P417_SWTR_App_0.obj rt_sys_P417_SWTR_App_5.obj + +MAIN_OBJ = rt_main.obj + +ALL_OBJS = $(OBJS) $(MAIN_OBJ) + +########################################################################### +## PREBUILT OBJECT FILES +########################################################################### + +PREBUILT_OBJS = + +########################################################################### +## LIBRARIES +########################################################################### + +LIBS = + +########################################################################### +## SYSTEM LIBRARIES +########################################################################### + +SYSTEM_LIBS = + +########################################################################### +## ADDITIONAL TOOLCHAIN FLAGS +########################################################################### + +#--------------- +# C Compiler +#--------------- + +CFLAGS_BASIC = $(DEFINES) $(INCLUDES) + +CFLAGS += $(CFLAGS_BASIC) + +########################################################################### +## INLINED COMMANDS +########################################################################### + +########################################################################### +## PHONY TARGETS +########################################################################### + +.PHONY : all build buildobj clean info prebuild download execute + + +all : build + @echo "### Successfully generated all binary outputs." + + +build : prebuild $(PRODUCT) + + +buildobj : prebuild $(OBJS) $(PREBUILT_OBJS) + @echo "### Successfully generated all binary outputs." + + +prebuild : + + +download : build + + +execute : download + @echo "### Invoking postbuild tool "Execute" ..." + $(EXECUTE) $(EXECUTE_FLAGS) + @echo "### Done invoking postbuild tool." + + +########################################################################### +## FINAL TARGET +########################################################################### + +#------------------------------------------- +# Create a standalone executable +#------------------------------------------- + +$(PRODUCT) : $(OBJS) $(PREBUILT_OBJS) $(MAIN_OBJ) + $(GEN_LINKER_RESPONSE) $(CMD_FILE) $(subst /,\,$(OBJS)) + @echo "### Creating standalone executable "$(PRODUCT)" ..." + $(LD) $(LDFLAGS) -o $(PRODUCT) @$(CMD_FILE) $(subst /,\,$(subst /,\,$(MAIN_OBJ))) $(subst /,\,$(subst /,\,$(SYSTEM_LIBS))) $(subst /,\,$(subst /,\,$(TOOLCHAIN_LIBS))) + @echo "### Created: $(PRODUCT)" + $(RM) $(CMD_FILE) + + +########################################################################### +## INTERMEDIATE TARGETS +########################################################################### + +#--------------------- +# SOURCE-TO-OBJECT +#--------------------- + +%.obj : %.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +%.obj : $(RELATIVE_PATH_TO_ANCHOR)/%.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +%.obj : $(START_DIR)/%.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +%.obj : $(START_DIR)/P417_SWTR_App_ert_rtw/%.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +%.obj : $(MATLAB_ROOT)/rtw/c/src/%.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +%.obj : $(MATLAB_ROOT)/simulink/src/%.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +rt_main.obj : $(MATLAB_ROOT)/rtw/c/src/common/rt_main.c + $(CC) $(CFLAGS) -Fo"$@" $(subst /,\,"$<") + + +########################################################################### +## DEPENDENCIES +########################################################################### + +$(ALL_OBJS) : $(MAKEFILE) rtw_proj.tmw + + +########################################################################### +## MISCELLANEOUS TARGETS +########################################################################### + +info : + @echo "### PRODUCT = $(PRODUCT)" + @echo "### PRODUCT_TYPE = $(PRODUCT_TYPE)" + @echo "### BUILD_TYPE = $(BUILD_TYPE)" + @echo "### INCLUDES = $(INCLUDES)" + @echo "### DEFINES = $(DEFINES)" + @echo "### ALL_SRCS = $(ALL_SRCS)" + @echo "### ALL_OBJS = $(ALL_OBJS)" + @echo "### LIBS = $(LIBS)" + @echo "### MODELREF_LIBS = $(MODELREF_LIBS)" + @echo "### SYSTEM_LIBS = $(SYSTEM_LIBS)" + @echo "### TOOLCHAIN_LIBS = $(TOOLCHAIN_LIBS)" + @echo "### CFLAGS = $(CFLAGS)" + @echo "### LDFLAGS = $(LDFLAGS)" + @echo "### SHAREDLIB_LDFLAGS = $(SHAREDLIB_LDFLAGS)" + @echo "### ARFLAGS = $(ARFLAGS)" + @echo "### MEX_CFLAGS = $(MEX_CFLAGS)" + @echo "### MEX_CPPFLAGS = $(MEX_CPPFLAGS)" + @echo "### MEX_LDFLAGS = $(MEX_LDFLAGS)" + @echo "### MEX_CPPLDFLAGS = $(MEX_CPPLDFLAGS)" + @echo "### DOWNLOAD_FLAGS = $(DOWNLOAD_FLAGS)" + @echo "### EXECUTE_FLAGS = $(EXECUTE_FLAGS)" + @echo "### MAKE_FLAGS = $(MAKE_FLAGS)" + + +clean : + $(ECHO) "### Deleting all derived files..." + $(RM) $(subst /,\,$(PRODUCT)) + $(RM) $(subst /,\,$(ALL_OBJS)) + $(ECHO) "### Deleted all derived files." + + diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c new file mode 100644 index 0000000..9054e2c --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_data.c @@ -0,0 +1,32 @@ +/* + * File: P417_SWTR_App_data.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Invariant block signals (auto storage) */ +const ConstB_P417_SWTR_App_T P417_SWTR_App_ConstB = { + /* Start of '/Set_Diag_20ms' */ + { + 0U /* '/Off' */ + } + /* End of '/Set_Diag_20ms' */ +}; + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_private.h b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_private.h new file mode 100644 index 0000000..bd73042 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_private.h @@ -0,0 +1,75 @@ +/* + * File: P417_SWTR_App_private.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_P417_SWTR_App_private_h_ +#define RTW_HEADER_P417_SWTR_App_private_h_ +#include "rtwtypes.h" + +/* Includes for objects with custom storage classes. */ +#include "RTE.h" +#ifndef UCHAR_MAX +#include +#endif + +#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) ) +#error Code was generated for compiler with different sized uchar/char. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) ) +#error Code was generated for compiler with different sized ushort/short. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) ) +#error Code was generated for compiler with different sized uint/int. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) ) +#error Code was generated for compiler with different sized ulong/long. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif +#endif /* RTW_HEADER_P417_SWTR_App_private_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_ref.rsp b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_ref.rsp new file mode 100644 index 0000000..e69de29 diff --git a/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_types.h b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_types.h new file mode 100644 index 0000000..fb94b7e --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/P417_SWTR_App_types.h @@ -0,0 +1,28 @@ +/* + * File: P417_SWTR_App_types.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_P417_SWTR_App_types_h_ +#define RTW_HEADER_P417_SWTR_App_types_h_ + +/* Forward declaration for rtModel */ +typedef struct tag_RTM_P417_SWTR_App_T RT_MODEL_P417_SWTR_App_T; + +#endif /* RTW_HEADER_P417_SWTR_App_types_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c new file mode 100644 index 0000000..85f9997 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.c @@ -0,0 +1,33 @@ +/* + * File: Set_0x309_RC_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "Set_0x309_RC_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/Set_0x309_RC_10ms' */ +void P417_SWTR_App_Set_0x309_RC_10ms(uint8_T rtu_Set_0x309_Send_RC) +{ + /* Gain: '/Gain1' */ + RTE_Set_SEND_CAN_0x309_immediately(rtu_Set_0x309_Send_RC); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.h new file mode 100644 index 0000000..6572db4 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Set_0x309_RC_10ms.h @@ -0,0 +1,33 @@ +/* + * File: Set_0x309_RC_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_Set_0x309_RC_10ms_h_ +#define RTW_HEADER_Set_0x309_RC_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_SWTR_App_Set_0x309_RC_10ms(uint8_T rtu_Set_0x309_Send_RC); + +#endif /* RTW_HEADER_Set_0x309_RC_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c b/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c new file mode 100644 index 0000000..3f28009 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.c @@ -0,0 +1,59 @@ +/* + * File: Set_Diag_20ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "Set_Diag_20ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* System initialize for function-call system: '/Set_Diag_20ms' */ +void P417_SWTR_Ap_Set_Diag_20ms_Init(const ConstB_Set_Diag_20ms_P417_SWT_T + *localC) +{ + /* SystemInitialize for SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRCmnFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRCmnFltSts(localC->Off); + + /* SystemInitialize for SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRSnsrFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRSnsrFltSts(localC->Off); + + /* SystemInitialize for SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRTouchdFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRTouchdFltSts(localC->Off); + + /* SystemInitialize for SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRVibrationFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRVibrationFltSts(localC->Off); +} + +/* Output and update for function-call system: '/Set_Diag_20ms' */ +void P417_SWTR_App_Set_Diag_20ms(const ConstB_Set_Diag_20ms_P417_SWT_T *localC) +{ + /* SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRCmnFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRCmnFltSts(localC->Off); + + /* SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRSnsrFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRSnsrFltSts(localC->Off); + + /* SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRTouchdFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRTouchdFltSts(localC->Off); + + /* SignalConversion: '/OutportBufferForSet_DiagcFailrTouchPanSWTRVibrationFltSts' */ + RTE_Set_CAN_DiagcFailrTouchPanSWTRVibrationFltSts(localC->Off); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.h b/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.h new file mode 100644 index 0000000..e993b89 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/Set_Diag_20ms.h @@ -0,0 +1,41 @@ +/* + * File: Set_Diag_20ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_Set_Diag_20ms_h_ +#define RTW_HEADER_Set_Diag_20ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Invariant block signals for system '/Set_Diag_20ms' */ +typedef struct { + const uint8_T Off; /* '/Off' */ +} ConstB_Set_Diag_20ms_P417_SWT_T; + +extern void P417_SWTR_Ap_Set_Diag_20ms_Init(const + ConstB_Set_Diag_20ms_P417_SWT_T *localC); +extern void P417_SWTR_App_Set_Diag_20ms(const ConstB_Set_Diag_20ms_P417_SWT_T + *localC); + +#endif /* RTW_HEADER_Set_Diag_20ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c new file mode 100644 index 0000000..4b9d748 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.c @@ -0,0 +1,122 @@ +/* + * File: TouchBoardXY_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoardXY_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* System initialize for function-call system: '/TouchBoardXY_handle_4ms' */ +void P4_TouchBoardXY_handle_4ms_Init(B_TouchBoardXY_handle_4ms_P41_T *localB) +{ + /* SystemInitialize for Chart: '/Slect_Touch' */ + localB->Sts_Control = 0U; +} + +/* Output and update for function-call system: '/TouchBoardXY_handle_4ms' */ +void P417_SW_TouchBoardXY_handle_4ms(uint8_T rtu_TouchBoard_XY_Sts_input, + uint8_T rtu_Voice_Sts_Select, uint8_T rtu_Vol_Sts_Select, uint8_T + rtu_Menu_Sts_Select, uint8_T rtu_XY_Touch_And_Below_1N, uint8_T + *rty_TouchBoard_XY_Sts_after_han, uint8_T *rty_XY_Touch_And_Below_1N_af_hd, + B_TouchBoardXY_handle_4ms_P41_T *localB, DW_TouchBoardXY_handle_4ms_P4_T + *localDW) +{ + uint8_T rtb_Compare_oa; + uint8_T rtb_Compare_eb; + uint8_T rtb_Compare_ll; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_oa = (uint8_T)(rtu_Voice_Sts_Select > 0); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_eb = (uint8_T)(rtu_Vol_Sts_Select > 0); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ll = (uint8_T)(rtu_Menu_Sts_Select > 0); + + /* Chart: '/Slect_Touch' incorporates: + * Constant: '/Constant' + * RelationalOperator: '/Compare' + */ + /* Die2_A_Position_Judgement */ + if ((rtb_Compare_oa == 0) && (rtb_Compare_eb == 0) && (rtb_Compare_ll == 0) && + (rtu_TouchBoard_XY_Sts_input > 0)) { + localB->Sts_Control = 1U; + } else if ((rtb_Compare_oa == 1) && (rtb_Compare_eb == 0) && (rtb_Compare_ll == + 0)) { + localB->Sts_Control = 2U; + } else if ((rtb_Compare_oa == 0) && (rtb_Compare_eb == 1) && (rtb_Compare_ll == + 0)) { + localB->Sts_Control = 3U; + } else { + if ((rtb_Compare_oa == 0) && (rtb_Compare_eb == 0) && (rtb_Compare_ll == 1)) + { + localB->Sts_Control = 4U; + } + } + + /* End of Chart: '/Slect_Touch' */ + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * UnitDelay: '/Unit Delay' + */ + switch (localB->Sts_Control) { + case 1: + *rty_TouchBoard_XY_Sts_after_han = rtu_TouchBoard_XY_Sts_input; + break; + + case 2: + *rty_TouchBoard_XY_Sts_after_han = rtu_Voice_Sts_Select; + break; + + case 3: + *rty_TouchBoard_XY_Sts_after_han = rtu_Vol_Sts_Select; + break; + + case 4: + *rty_TouchBoard_XY_Sts_after_han = rtu_Menu_Sts_Select; + break; + + case 5: + *rty_TouchBoard_XY_Sts_after_han = 0U; + break; + + default: + *rty_TouchBoard_XY_Sts_after_han = localDW->UnitDelay_DSTATE; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Inport: '/XY_Touch_And_Below_1N' */ + *rty_XY_Touch_And_Below_1N_af_hd = rtu_XY_Touch_And_Below_1N; + + /* Update for UnitDelay: '/Unit Delay' */ + localDW->UnitDelay_DSTATE = *rty_TouchBoard_XY_Sts_after_han; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.h new file mode 100644 index 0000000..f3fb230 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoardXY_handle_4ms.h @@ -0,0 +1,50 @@ +/* + * File: TouchBoardXY_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoardXY_handle_4ms_h_ +#define RTW_HEADER_TouchBoardXY_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Block signals for system '/TouchBoardXY_handle_4ms' */ +typedef struct { + uint8_T Sts_Control; /* '/Slect_Touch' */ +} B_TouchBoardXY_handle_4ms_P41_T; + +/* Block states (auto storage) for system '/TouchBoardXY_handle_4ms' */ +typedef struct { + uint8_T UnitDelay_DSTATE; /* '/Unit Delay' */ +} DW_TouchBoardXY_handle_4ms_P4_T; + +extern void P4_TouchBoardXY_handle_4ms_Init(B_TouchBoardXY_handle_4ms_P41_T + *localB); +extern void P417_SW_TouchBoardXY_handle_4ms(uint8_T rtu_TouchBoard_XY_Sts_input, + uint8_T rtu_Voice_Sts_Select, uint8_T rtu_Vol_Sts_Select, uint8_T + rtu_Menu_Sts_Select, uint8_T rtu_XY_Touch_And_Below_1N, uint8_T + *rty_TouchBoard_XY_Sts_after_han, uint8_T *rty_XY_Touch_And_Below_1N_af_hd, + B_TouchBoardXY_handle_4ms_P41_T *localB, DW_TouchBoardXY_handle_4ms_P4_T + *localDW); + +#endif /* RTW_HEADER_TouchBoardXY_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c new file mode 100644 index 0000000..1210dad --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.c @@ -0,0 +1,70 @@ +/* + * File: TouchBoard_0x307_Send_And_ACT_Req_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_0x307_Send_And_ACT_Req_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_0x307_Send_And_ACT_Req_4ms' */ +void TouchBoard_0x307_Send_And_ACT_R(uint8_T rtu_RiMFctActSgUp_after_handle, + uint8_T rtu_RiMFctActSgDn_after_handle, uint8_T rtu_RiMFctActSgLe_after_handle, + uint8_T rtu_RiMFctActSgRi_after_handle, uint8_T rtu_RiMFctActSgCe_after_handle, + uint8_T rtu_SwpUpDwnStsRi_after_handle, uint8_T rtu_SwpLeRiStsRi_after_handle, + uint8_T rtu_SteerWhlTouchBdVOICE_after_, uint8_T + rtu_SteerWhlTouchBdCrsMENUSteer, uint8_T rtu_SteerWhlTouchBdVOLSteerWhlT, + uint8_T *rty_Set_0x307_Send_And_ACT_Req) +{ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Gain: '/Gain' + * Gain: '/Gain1' + * Gain: '/Gain2' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + *rty_Set_0x307_Send_And_ACT_Req = (uint8_T)((rtu_RiMFctActSgUp_after_handle > + 0) || (rtu_RiMFctActSgDn_after_handle > 0) || + (rtu_RiMFctActSgLe_after_handle > 0) || (rtu_RiMFctActSgRi_after_handle > 0) + || (rtu_RiMFctActSgCe_after_handle > 0) || (rtu_SwpUpDwnStsRi_after_handle > + 0) || (rtu_SwpLeRiStsRi_after_handle > 0) || + (rtu_SteerWhlTouchBdVOICE_after_ > 0) || (rtu_SteerWhlTouchBdCrsMENUSteer > + 0) || (rtu_SteerWhlTouchBdVOLSteerWhlT > 0)); +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.h new file mode 100644 index 0000000..e175755 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x307_Send_And_ACT_Req_4ms.h @@ -0,0 +1,39 @@ +/* + * File: TouchBoard_0x307_Send_And_ACT_Req_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_0x307_Send_And_ACT_Req_4ms_h_ +#define RTW_HEADER_TouchBoard_0x307_Send_And_ACT_Req_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void TouchBoard_0x307_Send_And_ACT_R(uint8_T + rtu_RiMFctActSgUp_after_handle, uint8_T rtu_RiMFctActSgDn_after_handle, + uint8_T rtu_RiMFctActSgLe_after_handle, uint8_T rtu_RiMFctActSgRi_after_handle, + uint8_T rtu_RiMFctActSgCe_after_handle, uint8_T rtu_SwpUpDwnStsRi_after_handle, + uint8_T rtu_SwpLeRiStsRi_after_handle, uint8_T rtu_SteerWhlTouchBdVOICE_after_, + uint8_T rtu_SteerWhlTouchBdCrsMENUSteer, uint8_T + rtu_SteerWhlTouchBdVOLSteerWhlT, uint8_T *rty_Set_0x307_Send_And_ACT_Req); + +#endif /* RTW_HEADER_TouchBoard_0x307_Send_And_ACT_Req_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c new file mode 100644 index 0000000..9680c14 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.c @@ -0,0 +1,41 @@ +/* + * File: TouchBoard_0x309_Send_And_ACT_Req_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_0x309_Send_And_ACT_Req_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_0x309_Send_And_ACT_Req_10ms' */ +void TouchBoard_0x309_Send_And_ACT_R(uint8_T rtu_XY_Touch_And_Below_1N_af_hd, + uint8_T *rty_Set_0x309_Send_And_ACT_Req, uint8_T *rty_Set_0x309_Send) +{ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Constant: '/Constant' + * RelationalOperator: '/Compare' + */ + *rty_Set_0x309_Send_And_ACT_Req = (uint8_T)(rtu_XY_Touch_And_Below_1N_af_hd > + 0); + + /* Gain: '/Gain1' */ + *rty_Set_0x309_Send = *rty_Set_0x309_Send_And_ACT_Req; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.h new file mode 100644 index 0000000..fb2e80d --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_0x309_Send_And_ACT_Req_10ms.h @@ -0,0 +1,35 @@ +/* + * File: TouchBoard_0x309_Send_And_ACT_Req_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_0x309_Send_And_ACT_Req_10ms_h_ +#define RTW_HEADER_TouchBoard_0x309_Send_And_ACT_Req_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void TouchBoard_0x309_Send_And_ACT_R(uint8_T + rtu_XY_Touch_And_Below_1N_af_hd, uint8_T *rty_Set_0x309_Send_And_ACT_Req, + uint8_T *rty_Set_0x309_Send); + +#endif /* RTW_HEADER_TouchBoard_0x309_Send_And_ACT_Req_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c new file mode 100644 index 0000000..2841e74 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Center_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Center_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Center_handle_4ms' */ +void P4_TouchBoard_Center_handle_4ms(uint8_T rtu_TouchBoard_Center_Sts_input, + uint8_T *rty_TouchBoard_Center_Sts_after) +{ + /* Inport: '/TouchBoard_Center_Sts_input' */ + *rty_TouchBoard_Center_Sts_after = rtu_TouchBoard_Center_Sts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.h new file mode 100644 index 0000000..1f280c0 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Center_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Center_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Center_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Center_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P4_TouchBoard_Center_handle_4ms(uint8_T + rtu_TouchBoard_Center_Sts_input, uint8_T *rty_TouchBoard_Center_Sts_after); + +#endif /* RTW_HEADER_TouchBoard_Center_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c new file mode 100644 index 0000000..52b5cdc --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Down_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Down_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Down_handle_4ms' */ +void P417_TouchBoard_Down_handle_4ms(uint8_T rtu_TouchBoard_Down_Sts_input, + uint8_T *rty_TouchBoard_Down_Sts_after_h) +{ + /* Inport: '/TouchBoard_Down_Sts_input' */ + *rty_TouchBoard_Down_Sts_after_h = rtu_TouchBoard_Down_Sts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.h new file mode 100644 index 0000000..dae33ff --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Down_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Down_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Down_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Down_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_TouchBoard_Down_handle_4ms(uint8_T + rtu_TouchBoard_Down_Sts_input, uint8_T *rty_TouchBoard_Down_Sts_after_h); + +#endif /* RTW_HEADER_TouchBoard_Down_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c new file mode 100644 index 0000000..95056b1 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Left_Right_Slide_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Left_Right_Slide_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Left_Right_Slide_handle_4ms' */ +void TouchBoard_Left_Right_Slide_han(uint8_T rtu_TouchBoard_Left_Right_Slide, + uint8_T *rty_TouchBoard_Left_Right_Slide) +{ + /* Inport: '/TouchBoard_Left_Right_Slide_Sts_input' */ + *rty_TouchBoard_Left_Right_Slide = rtu_TouchBoard_Left_Right_Slide; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.h new file mode 100644 index 0000000..e4b3f17 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_Right_Slide_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Left_Right_Slide_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Left_Right_Slide_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Left_Right_Slide_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void TouchBoard_Left_Right_Slide_han(uint8_T + rtu_TouchBoard_Left_Right_Slide, uint8_T *rty_TouchBoard_Left_Right_Slide); + +#endif /* RTW_HEADER_TouchBoard_Left_Right_Slide_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c new file mode 100644 index 0000000..49e70ab --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Left_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Left_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Left_handle_4ms' */ +void P417_TouchBoard_Left_handle_4ms(uint8_T rtu_TouchBoard_Left_Sts_input, + uint8_T *rty_TouchBoard_Left_Sts_after_h) +{ + /* Inport: '/TouchBoard_Left_Sts_input' */ + *rty_TouchBoard_Left_Sts_after_h = rtu_TouchBoard_Left_Sts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.h new file mode 100644 index 0000000..7072067 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Left_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Left_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Left_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Left_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_TouchBoard_Left_handle_4ms(uint8_T + rtu_TouchBoard_Left_Sts_input, uint8_T *rty_TouchBoard_Left_Sts_after_h); + +#endif /* RTW_HEADER_TouchBoard_Left_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c new file mode 100644 index 0000000..7598a83 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.c @@ -0,0 +1,38 @@ +/* + * File: TouchBoard_MENU_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_MENU_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_MENU_handle_4ms' */ +void P417_TouchBoard_MENU_handle_4ms(uint8_T rtu_TouchBoard_MENU_Sts_input, + uint8_T rtu_Menu_XY_trig_in, uint8_T *rty_TouchBoard_MENU_Sts_after_h, uint8_T + *rty_Menu_XY_trig_afhd) +{ + /* Inport: '/TouchBoard_MENU_Sts_input' */ + *rty_TouchBoard_MENU_Sts_after_h = rtu_TouchBoard_MENU_Sts_input; + + /* Inport: '/Menu_XY_trig_in' */ + *rty_Menu_XY_trig_afhd = rtu_Menu_XY_trig_in; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.h new file mode 100644 index 0000000..293115e --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_MENU_handle_4ms.h @@ -0,0 +1,35 @@ +/* + * File: TouchBoard_MENU_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_MENU_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_MENU_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_TouchBoard_MENU_handle_4ms(uint8_T + rtu_TouchBoard_MENU_Sts_input, uint8_T rtu_Menu_XY_trig_in, uint8_T + *rty_TouchBoard_MENU_Sts_after_h, uint8_T *rty_Menu_XY_trig_afhd); + +#endif /* RTW_HEADER_TouchBoard_MENU_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c new file mode 100644 index 0000000..f8a89f5 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Right_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Right_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Right_handle_4ms' */ +void P41_TouchBoard_Right_handle_4ms(uint8_T rtu_TouchBoard_Right_Sts_input, + uint8_T *rty_TouchBoard_Right_Sts_after_) +{ + /* Inport: '/TouchBoard_Right_Sts_input' */ + *rty_TouchBoard_Right_Sts_after_ = rtu_TouchBoard_Right_Sts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.h new file mode 100644 index 0000000..477d1bf --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Right_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_Right_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Right_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Right_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P41_TouchBoard_Right_handle_4ms(uint8_T + rtu_TouchBoard_Right_Sts_input, uint8_T *rty_TouchBoard_Right_Sts_after_); + +#endif /* RTW_HEADER_TouchBoard_Right_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c new file mode 100644 index 0000000..e106cf9 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.c @@ -0,0 +1,38 @@ +/* + * File: TouchBoard_Up_Down_Slide_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Up_Down_Slide_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_Up_Down_Slide_handle_4ms' */ +void TouchBoard_Up_Down_Slide_handle(uint8_T rtu_TouchBoard_Up_Down_Slide_St, + uint8_T rtu_SldVolCtrlSts_input, uint8_T *rty_TouchBoard_Up_Down_Slide_St, + uint8_T *rty_SldVolCtrlSts_out) +{ + /* Inport: '/TouchBoard_Up_Down_Slide_Sts_input' */ + *rty_TouchBoard_Up_Down_Slide_St = rtu_TouchBoard_Up_Down_Slide_St; + + /* Inport: '/SldVolCtrlSts_input' */ + *rty_SldVolCtrlSts_out = rtu_SldVolCtrlSts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.h new file mode 100644 index 0000000..94c6943 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Up_Down_Slide_handle_4ms.h @@ -0,0 +1,35 @@ +/* + * File: TouchBoard_Up_Down_Slide_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Up_Down_Slide_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_Up_Down_Slide_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void TouchBoard_Up_Down_Slide_handle(uint8_T + rtu_TouchBoard_Up_Down_Slide_St, uint8_T rtu_SldVolCtrlSts_input, uint8_T + *rty_TouchBoard_Up_Down_Slide_St, uint8_T *rty_SldVolCtrlSts_out); + +#endif /* RTW_HEADER_TouchBoard_Up_Down_Slide_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c new file mode 100644 index 0000000..4622d31 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.c @@ -0,0 +1,38 @@ +/* + * File: TouchBoard_VOICE_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_VOICE_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_VOICE_handle_4ms' */ +void P41_TouchBoard_VOICE_handle_4ms(uint8_T rtu_TouchBoard_VOICE_Sts_input, + uint8_T rtu_Voice_XY_trig_in, uint8_T *rty_TouchBoard_VOICE_Sts_after_, + uint8_T *rty_Voice_XY_trig_afhd) +{ + /* Inport: '/TouchBoard_VOICE_Sts_input' */ + *rty_TouchBoard_VOICE_Sts_after_ = rtu_TouchBoard_VOICE_Sts_input; + + /* Inport: '/Voice_XY_trig_in' */ + *rty_Voice_XY_trig_afhd = rtu_Voice_XY_trig_in; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.h new file mode 100644 index 0000000..905d11d --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOICE_handle_4ms.h @@ -0,0 +1,35 @@ +/* + * File: TouchBoard_VOICE_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_VOICE_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_VOICE_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P41_TouchBoard_VOICE_handle_4ms(uint8_T + rtu_TouchBoard_VOICE_Sts_input, uint8_T rtu_Voice_XY_trig_in, uint8_T + *rty_TouchBoard_VOICE_Sts_after_, uint8_T *rty_Voice_XY_trig_afhd); + +#endif /* RTW_HEADER_TouchBoard_VOICE_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c new file mode 100644 index 0000000..75d889c --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.c @@ -0,0 +1,42 @@ +/* + * File: TouchBoard_VOL_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_VOL_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_VOL_handle_4ms' */ +void P417__TouchBoard_VOL_handle_4ms(uint8_T rtu_TouchBoard_VOL_Sts_input, + uint8_T rtu_Vol_XY_trig_in, uint8_T rtu_Pad_XY_trig_in, uint8_T + *rty_TouchBoard_VOL_Sts_after_ha, uint8_T *rty_Vol_XY_trig_afhd, uint8_T + *rty_Pad_XY_trig_afhd) +{ + /* Inport: '/TouchBoard_VOL_Sts_input' */ + *rty_TouchBoard_VOL_Sts_after_ha = rtu_TouchBoard_VOL_Sts_input; + + /* Inport: '/Vol_XY_trig_in' */ + *rty_Vol_XY_trig_afhd = rtu_Vol_XY_trig_in; + + /* Inport: '/Pad_XY_trig_in' */ + *rty_Pad_XY_trig_afhd = rtu_Pad_XY_trig_in; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.h new file mode 100644 index 0000000..df361b2 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_VOL_handle_4ms.h @@ -0,0 +1,36 @@ +/* + * File: TouchBoard_VOL_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_VOL_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_VOL_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417__TouchBoard_VOL_handle_4ms(uint8_T rtu_TouchBoard_VOL_Sts_input, + uint8_T rtu_Vol_XY_trig_in, uint8_T rtu_Pad_XY_trig_in, uint8_T + *rty_TouchBoard_VOL_Sts_after_ha, uint8_T *rty_Vol_XY_trig_afhd, uint8_T + *rty_Pad_XY_trig_afhd); + +#endif /* RTW_HEADER_TouchBoard_VOL_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c new file mode 100644 index 0000000..7a0918d --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.c @@ -0,0 +1,125 @@ +/* + * File: TouchBoard_X_handle_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_X_handle_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* System initialize for function-call system: '/TouchBoard_X_handle_10ms' */ +void P_TouchBoard_X_handle_10ms_Init(B_TouchBoard_X_handle_10ms_P4_T *localB) +{ + /* SystemInitialize for Atomic SubSystem: '/Subsystem_selX' */ + P417_SWTR_A_Subsystem_selX_Init(&localB->Slect); + + /* End of SystemInitialize for SubSystem: '/Subsystem_selX' */ +} + +/* Output and update for function-call system: '/TouchBoard_X_handle_10ms' */ +void P417_S_TouchBoard_X_handle_10ms(uint8_T rtu_Board_XY_Trigg_afhd_in, uint8_T + rtu_Voice_Trigg_afhd_in, uint8_T rtu_Vol_Trigg_afhd_in, uint8_T + rtu_Menu_Trigg_afhd_in, uint8_T rtu_Up_Trigg_afhd_in, uint8_T + rtu_Down_Trigg_afhd_in, uint8_T rtu_Left_Trigg_afhd_in, uint8_T + rtu_Right_Trigg_afhd_in, uint8_T rtu_Center_Trigg_afhd_in, + B_TouchBoard_X_handle_10ms_P4_T *localB) +{ + /* Outputs for Atomic SubSystem: '/Subsystem_selX' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + P417_SWTR_App_Subsystem_selX((uint8_T)(rtu_Board_XY_Trigg_afhd_in > 0), + (uint8_T)(rtu_Voice_Trigg_afhd_in > 0), (uint8_T)(rtu_Vol_Trigg_afhd_in > 0), + (uint8_T)(rtu_Menu_Trigg_afhd_in > 0), (uint8_T)(rtu_Up_Trigg_afhd_in > 0), + (uint8_T)(rtu_Down_Trigg_afhd_in > 0), (uint8_T)(rtu_Left_Trigg_afhd_in > 0), + (uint8_T)(rtu_Right_Trigg_afhd_in > 0), (uint8_T)(rtu_Center_Trigg_afhd_in > + 0), &localB->Slect); + + /* End of Outputs for SubSystem: '/Subsystem_selX' */ + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + */ + switch (localB->Slect) { + case 1: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(0U); + break; + + case 2: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(0U); + break; + + case 3: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(0U); + break; + + case 4: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(0U); + break; + + case 5: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(172U); + break; + + case 6: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(172U); + break; + + case 7: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(120U); + break; + + case 8: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(225U); + break; + + case 9: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(172U); + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.h new file mode 100644 index 0000000..27cd6c6 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_X_handle_10ms.h @@ -0,0 +1,48 @@ +/* + * File: TouchBoard_X_handle_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_X_handle_10ms_h_ +#define RTW_HEADER_TouchBoard_X_handle_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Child system includes */ +#include "rt_sys_P417_SWTR_App_5.h" + +/* Block signals for system '/TouchBoard_X_handle_10ms' */ +typedef struct { + uint8_T Slect; /* '/Slect_X' */ +} B_TouchBoard_X_handle_10ms_P4_T; + +extern void P_TouchBoard_X_handle_10ms_Init(B_TouchBoard_X_handle_10ms_P4_T + *localB); +extern void P417_S_TouchBoard_X_handle_10ms(uint8_T rtu_Board_XY_Trigg_afhd_in, + uint8_T rtu_Voice_Trigg_afhd_in, uint8_T rtu_Vol_Trigg_afhd_in, uint8_T + rtu_Menu_Trigg_afhd_in, uint8_T rtu_Up_Trigg_afhd_in, uint8_T + rtu_Down_Trigg_afhd_in, uint8_T rtu_Left_Trigg_afhd_in, uint8_T + rtu_Right_Trigg_afhd_in, uint8_T rtu_Center_Trigg_afhd_in, + B_TouchBoard_X_handle_10ms_P4_T *localB); + +#endif /* RTW_HEADER_TouchBoard_X_handle_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c new file mode 100644 index 0000000..c4b7a35 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.c @@ -0,0 +1,125 @@ +/* + * File: TouchBoard_Y_handle_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_Y_handle_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* System initialize for function-call system: '/TouchBoard_Y_handle_10ms' */ +void P_TouchBoard_Y_handle_10ms_Init(B_TouchBoard_Y_handle_10ms_P4_T *localB) +{ + /* SystemInitialize for Atomic SubSystem: '/Subsyste_selY' */ + P417_SWTR_A_Subsystem_selX_Init(&localB->Slect); + + /* End of SystemInitialize for SubSystem: '/Subsyste_selY' */ +} + +/* Output and update for function-call system: '/TouchBoard_Y_handle_10ms' */ +void P417_S_TouchBoard_Y_handle_10ms(uint8_T rtu_Board_XY_Triggafhd_in, uint8_T + rtu_Voice_Triggafhd_in, uint8_T rtu_Vol_Triggafhd_in, uint8_T + rtu_Menu_Triggafhd_in, uint8_T rtu_Up_Trigg_afhd_in, uint8_T + rtu_Down_Trigg_afhd_in, uint8_T rtu_Left_Trigg_afhd_in, uint8_T + rtu_Right_Trigg_afhd_in, uint8_T rtu_Center_Trigg_afhd_in, + B_TouchBoard_Y_handle_10ms_P4_T *localB) +{ + /* Outputs for Atomic SubSystem: '/Subsyste_selY' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + P417_SWTR_App_Subsystem_selX((uint8_T)(rtu_Board_XY_Triggafhd_in > 0), + (uint8_T)(rtu_Voice_Triggafhd_in > 0), (uint8_T)(rtu_Vol_Triggafhd_in > 0), + (uint8_T)(rtu_Menu_Triggafhd_in > 0), (uint8_T)(rtu_Up_Trigg_afhd_in > 0), + (uint8_T)(rtu_Down_Trigg_afhd_in > 0), (uint8_T)(rtu_Left_Trigg_afhd_in > 0), + (uint8_T)(rtu_Right_Trigg_afhd_in > 0), (uint8_T)(rtu_Center_Trigg_afhd_in > + 0), &localB->Slect); + + /* End of Outputs for SubSystem: '/Subsyste_selY' */ + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + */ + switch (localB->Slect) { + case 1: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(0U); + break; + + case 2: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(41U); + break; + + case 3: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(125U); + break; + + case 4: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(210U); + break; + + case 5: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(55U); + break; + + case 6: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(203U); + break; + + case 7: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(130U); + break; + + case 8: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(130U); + break; + + case 9: + RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(130U); + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.h new file mode 100644 index 0000000..262f67c --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_Y_handle_10ms.h @@ -0,0 +1,48 @@ +/* + * File: TouchBoard_Y_handle_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_Y_handle_10ms_h_ +#define RTW_HEADER_TouchBoard_Y_handle_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Child system includes */ +#include "rt_sys_P417_SWTR_App_5.h" + +/* Block signals for system '/TouchBoard_Y_handle_10ms' */ +typedef struct { + uint8_T Slect; /* '/Slect_X' */ +} B_TouchBoard_Y_handle_10ms_P4_T; + +extern void P_TouchBoard_Y_handle_10ms_Init(B_TouchBoard_Y_handle_10ms_P4_T + *localB); +extern void P417_S_TouchBoard_Y_handle_10ms(uint8_T rtu_Board_XY_Triggafhd_in, + uint8_T rtu_Voice_Triggafhd_in, uint8_T rtu_Vol_Triggafhd_in, uint8_T + rtu_Menu_Triggafhd_in, uint8_T rtu_Up_Trigg_afhd_in, uint8_T + rtu_Down_Trigg_afhd_in, uint8_T rtu_Left_Trigg_afhd_in, uint8_T + rtu_Right_Trigg_afhd_in, uint8_T rtu_Center_Trigg_afhd_in, + B_TouchBoard_Y_handle_10ms_P4_T *localB); + +#endif /* RTW_HEADER_TouchBoard_Y_handle_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c new file mode 100644 index 0000000..bf7fa81 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.c @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_up_handle_4ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "TouchBoard_up_handle_4ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Output and update for function-call system: '/TouchBoard_up_handle_4ms' */ +void P417_S_TouchBoard_up_handle_4ms(uint8_T rtu_TouchBoard_Up_Sts_input, + uint8_T *rty_TouchBoard_Up_Sts_after_han) +{ + /* Inport: '/TouchBoard_Up_Sts_input' */ + *rty_TouchBoard_Up_Sts_after_han = rtu_TouchBoard_Up_Sts_input; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.h b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.h new file mode 100644 index 0000000..1bfefbe --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/TouchBoard_up_handle_4ms.h @@ -0,0 +1,34 @@ +/* + * File: TouchBoard_up_handle_4ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_TouchBoard_up_handle_4ms_h_ +#define RTW_HEADER_TouchBoard_up_handle_4ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_S_TouchBoard_up_handle_4ms(uint8_T rtu_TouchBoard_Up_Sts_input, + uint8_T *rty_TouchBoard_Up_Sts_after_han); + +#endif /* RTW_HEADER_TouchBoard_up_handle_4ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/buildInfo.mat b/firmware/src/P417_SWTR_App_ert_rtw/buildInfo.mat new file mode 100644 index 0000000..d6d2673 Binary files /dev/null and b/firmware/src/P417_SWTR_App_ert_rtw/buildInfo.mat differ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/build_exception.mat b/firmware/src/P417_SWTR_App_ert_rtw/build_exception.mat new file mode 100644 index 0000000..38820c7 Binary files /dev/null and b/firmware/src/P417_SWTR_App_ert_rtw/build_exception.mat differ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/codeInfo.mat b/firmware/src/P417_SWTR_App_ert_rtw/codeInfo.mat new file mode 100644 index 0000000..471ad12 Binary files /dev/null and b/firmware/src/P417_SWTR_App_ert_rtw/codeInfo.mat differ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/codedescriptor.dmr b/firmware/src/P417_SWTR_App_ert_rtw/codedescriptor.dmr new file mode 100644 index 0000000..9561039 Binary files /dev/null and b/firmware/src/P417_SWTR_App_ert_rtw/codedescriptor.dmr differ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/defines.txt b/firmware/src/P417_SWTR_App_ert_rtw/defines.txt new file mode 100644 index 0000000..6686b11 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/defines.txt @@ -0,0 +1,13 @@ +MODEL=P417_SWTR_App +NUMST=1 +NCSTATES=0 +HAVESTDIO +TERMFCN=1 +ONESTEPFCN=1 +MAT_FILE=0 +MULTI_INSTANCE_CODE=0 +INTEGER_CODE=0 +MT=0 +CLASSIC_INTERFACE=0 +ALLOCATIONFCN=0 +TID01EQ=0 diff --git a/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c b/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c new file mode 100644 index 0000000..c1550a3 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.c @@ -0,0 +1,60 @@ +/* + * File: illumination_control_10ms.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "illumination_control_10ms.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* System initialize for function-call system: '/illumination_control_10ms' */ +void illumination_control_10ms_Init(B_illumination_control_10ms_P_T *localB, + DW_illumination_control_10ms__T *localDW) +{ + /* SystemInitialize for Chart: '/Fault_Debounce_Chart' */ + P417__Fault_Debounce_Chart_Init(&localB->Fault_confirmed, + &localDW->sf_Fault_Debounce_Chart); +} + +/* Output and update for function-call system: '/illumination_control_10ms' */ +void P417__illumination_control_10ms(uint8_T rtu_ActvnOfSteerWhlIllmn_input, + uint8_T rtu_Frame_0x30_Timeout, uint8_T *rty_ActvnOfSteerWhlIllmn_after_, + B_illumination_control_10ms_P_T *localB, DW_illumination_control_10ms__T + *localDW) +{ + /* Chart: '/Fault_Debounce_Chart' */ + P417_SWTR__Fault_Debounce_Chart(rtu_Frame_0x30_Timeout, + &localB->Fault_confirmed, &localDW->sf_Fault_Debounce_Chart, 3U, 3U); + + /* Switch: '/Switch' incorporates: + * UnitDelay: '/Unit Delay' + */ + if (localB->Fault_confirmed > 0) { + *rty_ActvnOfSteerWhlIllmn_after_ = localDW->UnitDelay_DSTATE; + } else { + *rty_ActvnOfSteerWhlIllmn_after_ = rtu_ActvnOfSteerWhlIllmn_input; + } + + /* End of Switch: '/Switch' */ + + /* Update for UnitDelay: '/Unit Delay' */ + localDW->UnitDelay_DSTATE = *rty_ActvnOfSteerWhlIllmn_after_; +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.h b/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.h new file mode 100644 index 0000000..f4c6eac --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/illumination_control_10ms.h @@ -0,0 +1,52 @@ +/* + * File: illumination_control_10ms.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_illumination_control_10ms_h_ +#define RTW_HEADER_illumination_control_10ms_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Child system includes */ +#include "rt_sys_P417_SWTR_App_0.h" + +/* Block signals for system '/illumination_control_10ms' */ +typedef struct { + uint8_T Fault_confirmed; /* '/Fault_Debounce_Chart' */ +} B_illumination_control_10ms_P_T; + +/* Block states (auto storage) for system '/illumination_control_10ms' */ +typedef struct { + uint8_T UnitDelay_DSTATE; /* '/Unit Delay' */ + DW_Fault_Debounce_Chart_P417__T sf_Fault_Debounce_Chart;/* '/Fault_Debounce_Chart' */ +} DW_illumination_control_10ms__T; + +extern void illumination_control_10ms_Init(B_illumination_control_10ms_P_T + *localB, DW_illumination_control_10ms__T *localDW); +extern void P417__illumination_control_10ms(uint8_T + rtu_ActvnOfSteerWhlIllmn_input, uint8_T rtu_Frame_0x30_Timeout, uint8_T + *rty_ActvnOfSteerWhlIllmn_after_, B_illumination_control_10ms_P_T *localB, + DW_illumination_control_10ms__T *localDW); + +#endif /* RTW_HEADER_illumination_control_10ms_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/modelsources.txt b/firmware/src/P417_SWTR_App_ert_rtw/modelsources.txt new file mode 100644 index 0000000..076daf6 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/modelsources.txt @@ -0,0 +1 @@ + P417_SWTR_App.c rt_sys_P417_SWTR_App_0.c illumination_control_10ms.c rt_sys_P417_SWTR_App_5.c TouchBoard_X_handle_10ms.c TouchBoard_Y_handle_10ms.c LED_Control_10ms.c Set_0x309_RC_10ms.c Get_0x309_CRC_10ms.c TouchBoard_0x309_Send_And_ACT_Req_10ms.c CAN_0x307_25ms_Control.c CAN_0x307_1000ms_Control.c Set_Diag_20ms.c ACT_control_20ms.c TouchBoard_up_handle_4ms.c TouchBoard_Down_handle_4ms.c TouchBoard_Left_handle_4ms.c TouchBoard_Right_handle_4ms.c TouchBoard_Center_handle_4ms.c TouchBoard_VOICE_handle_4ms.c TouchBoard_MENU_handle_4ms.c TouchBoard_VOL_handle_4ms.c TouchBoard_Left_Right_Slide_handle_4ms.c TouchBoard_Up_Down_Slide_handle_4ms.c TouchBoardXY_handle_4ms.c TouchBoard_0x307_Send_And_ACT_Req_4ms.c diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c new file mode 100644 index 0000000..866f15e --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.c @@ -0,0 +1,114 @@ +/* + * File: rt_sys_P417_SWTR_App_0.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "rt_sys_P417_SWTR_App_0.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* Named constants for Chart: '/Fault_Debounce_Chart' */ +#define P417_SWTR_Ap_IN_NO_ACTIVE_CHILD ((uint8_T)0U) +#define P417_SWTR_App_IN_Fault_Recovery ((uint8_T)1U) +#define P417_SWTR_App_IN_Fault_confirm ((uint8_T)2U) +#define P417_SWTR_App_IN_Fault_happened ((uint8_T)3U) +#define P417_SWTR_App_IN_Fault_off ((uint8_T)4U) + +/* + * System initialize for atomic system: + * '/Fault_Debounce_Chart' + * '/Fault_Debounce_Chart' + * '/Fault_Debounce_Chart' + */ +void P417__Fault_Debounce_Chart_Init(uint8_T *rty_Fault_confirmed, + DW_Fault_Debounce_Chart_P417__T *localDW) +{ + localDW->temporalCounter_i1 = 0U; + localDW->is_active_c2_Debounce_Models = 0U; + localDW->is_c2_Debounce_Models = P417_SWTR_Ap_IN_NO_ACTIVE_CHILD; + *rty_Fault_confirmed = 0U; +} + +/* + * Output and update for atomic system: + * '/Fault_Debounce_Chart' + * '/Fault_Debounce_Chart' + * '/Fault_Debounce_Chart' + */ +void P417_SWTR__Fault_Debounce_Chart(uint8_T rtu_Fault_in, uint8_T + *rty_Fault_confirmed, DW_Fault_Debounce_Chart_P417__T *localDW, uint8_T + rtp_Fault_confirm_count, uint8_T rtp_Fault_recovery_count) +{ + /* Chart: '/Fault_Debounce_Chart' */ + if (localDW->temporalCounter_i1 < 255U) { + localDW->temporalCounter_i1++; + } + + if (localDW->is_active_c2_Debounce_Models == 0U) { + localDW->is_active_c2_Debounce_Models = 1U; + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_off; + *rty_Fault_confirmed = 0U; + } else { + switch (localDW->is_c2_Debounce_Models) { + case P417_SWTR_App_IN_Fault_Recovery: + if (rtu_Fault_in == 1) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_happened; + localDW->temporalCounter_i1 = 0U; + } else { + if (localDW->temporalCounter_i1 >= rtp_Fault_recovery_count) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_off; + *rty_Fault_confirmed = 0U; + } + } + break; + + case P417_SWTR_App_IN_Fault_confirm: + *rty_Fault_confirmed = 1U; + if (rtu_Fault_in == 0) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_Recovery; + localDW->temporalCounter_i1 = 0U; + } + break; + + case P417_SWTR_App_IN_Fault_happened: + if (localDW->temporalCounter_i1 >= rtp_Fault_confirm_count) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_confirm; + *rty_Fault_confirmed = 1U; + } else { + if (rtu_Fault_in == 0) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_Recovery; + localDW->temporalCounter_i1 = 0U; + } + } + break; + + default: + *rty_Fault_confirmed = 0U; + if (rtu_Fault_in == 1) { + localDW->is_c2_Debounce_Models = P417_SWTR_App_IN_Fault_happened; + localDW->temporalCounter_i1 = 0U; + } + break; + } + } + + /* End of Chart: '/Fault_Debounce_Chart' */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.h b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.h new file mode 100644 index 0000000..1f83b34 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_0.h @@ -0,0 +1,44 @@ +/* + * File: rt_sys_P417_SWTR_App_0.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_rt_sys_P417_SWTR_App_0_h_ +#define RTW_HEADER_rt_sys_P417_SWTR_App_0_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +/* Block states (auto storage) for system '/Fault_Debounce_Chart' */ +typedef struct { + uint8_T is_active_c2_Debounce_Models;/* '/Fault_Debounce_Chart' */ + uint8_T is_c2_Debounce_Models; /* '/Fault_Debounce_Chart' */ + uint8_T temporalCounter_i1; /* '/Fault_Debounce_Chart' */ +} DW_Fault_Debounce_Chart_P417__T; + +extern void P417__Fault_Debounce_Chart_Init(uint8_T *rty_Fault_confirmed, + DW_Fault_Debounce_Chart_P417__T *localDW); +extern void P417_SWTR__Fault_Debounce_Chart(uint8_T rtu_Fault_in, uint8_T + *rty_Fault_confirmed, DW_Fault_Debounce_Chart_P417__T *localDW, uint8_T + rtp_Fault_confirm_count, uint8_T rtp_Fault_recovery_count); + +#endif /* RTW_HEADER_rt_sys_P417_SWTR_App_0_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c new file mode 100644 index 0000000..e7c9eed --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.c @@ -0,0 +1,94 @@ +/* + * File: rt_sys_P417_SWTR_App_5.c + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "rt_sys_P417_SWTR_App_5.h" + +/* Include model header file for global data */ +#include "P417_SWTR_App.h" +#include "P417_SWTR_App_private.h" + +/* + * System initialize for atomic system: + * '/Subsystem_selX' + * '/Subsyste_selY' + */ +void P417_SWTR_A_Subsystem_selX_Init(uint8_T *rty_SLECT) +{ + /* SystemInitialize for Chart: '/Slect_X' */ + *rty_SLECT = 0U; +} + +/* + * Output and update for atomic system: + * '/Subsystem_selX' + * '/Subsyste_selY' + */ +void P417_SWTR_App_Subsystem_selX(uint8_T rtu_Board_XY_Trigg, uint8_T + rtu_Voice_Trigg, uint8_T rtu_Vol_Trigg, uint8_T rtu_Menu_Trigg, uint8_T + rtu_Up_Trigg, uint8_T rtu_Down_Trigg, uint8_T rtu_Left_Trigg, uint8_T + rtu_Right_Trigg, uint8_T rtu_Center_Trigg, uint8_T *rty_SLECT) +{ + /* Chart: '/Slect_X' */ + /* Die2_A_Position_Judgement */ + if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == 0) && + (rtu_Board_XY_Trigg == 0) && (rtu_Up_Trigg == 0) && (rtu_Down_Trigg == 0) && + (rtu_Left_Trigg == 0) && (rtu_Right_Trigg == 0) && (rtu_Center_Trigg == 0)) + { + *rty_SLECT = 1U; + } else if ((rtu_Voice_Trigg == 1) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 0)) { + *rty_SLECT = 2U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 1) && (rtu_Menu_Trigg == + 0)) { + *rty_SLECT = 3U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 1)) { + *rty_SLECT = 4U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 0) && (rtu_Up_Trigg == 1) && (rtu_Down_Trigg == 0) && + (rtu_Left_Trigg == 0) && (rtu_Right_Trigg == 0) && + (rtu_Center_Trigg == 0)) { + *rty_SLECT = 5U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 0) && (rtu_Up_Trigg == 0) && (rtu_Down_Trigg == 1) && + (rtu_Left_Trigg == 0) && (rtu_Right_Trigg == 0) && + (rtu_Center_Trigg == 0)) { + *rty_SLECT = 6U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 0) && (rtu_Up_Trigg == 0) && (rtu_Down_Trigg == 0) && + (rtu_Left_Trigg == 1) && (rtu_Right_Trigg == 0) && + (rtu_Center_Trigg == 0)) { + *rty_SLECT = 7U; + } else if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == + 0) && (rtu_Up_Trigg == 0) && (rtu_Down_Trigg == 0) && + (rtu_Left_Trigg == 0) && (rtu_Right_Trigg == 1) && + (rtu_Center_Trigg == 0)) { + *rty_SLECT = 8U; + } else { + if ((rtu_Voice_Trigg == 0) && (rtu_Vol_Trigg == 0) && (rtu_Menu_Trigg == 0) && + (rtu_Up_Trigg == 0) && (rtu_Down_Trigg == 0) && (rtu_Left_Trigg == 0) && + (rtu_Right_Trigg == 0) && (rtu_Center_Trigg == 1)) { + *rty_SLECT = 9U; + } + } + + /* End of Chart: '/Slect_X' */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.h b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.h new file mode 100644 index 0000000..6ae9809 --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rt_sys_P417_SWTR_App_5.h @@ -0,0 +1,37 @@ +/* + * File: rt_sys_P417_SWTR_App_5.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_rt_sys_P417_SWTR_App_5_h_ +#define RTW_HEADER_rt_sys_P417_SWTR_App_5_h_ +#ifndef P417_SWTR_App_COMMON_INCLUDES_ +# define P417_SWTR_App_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* P417_SWTR_App_COMMON_INCLUDES_ */ + +#include "P417_SWTR_App_types.h" + +extern void P417_SWTR_A_Subsystem_selX_Init(uint8_T *rty_SLECT); +extern void P417_SWTR_App_Subsystem_selX(uint8_T rtu_Board_XY_Trigg, uint8_T + rtu_Voice_Trigg, uint8_T rtu_Vol_Trigg, uint8_T rtu_Menu_Trigg, uint8_T + rtu_Up_Trigg, uint8_T rtu_Down_Trigg, uint8_T rtu_Left_Trigg, uint8_T + rtu_Right_Trigg, uint8_T rtu_Center_Trigg, uint8_T *rty_SLECT); + +#endif /* RTW_HEADER_rt_sys_P417_SWTR_App_5_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rtmodel.h b/firmware/src/P417_SWTR_App_ert_rtw/rtmodel.h new file mode 100644 index 0000000..30905cf --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rtmodel.h @@ -0,0 +1,30 @@ +/* + * File: rtmodel.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_rtmodel_h_ +#define RTW_HEADER_rtmodel_h_ +#include "P417_SWTR_App.h" + +/* Macros generated for backwards compatibility */ +#ifndef rtmGetStopRequested +# define rtmGetStopRequested(rtm) ((void*) 0) +#endif +#endif /* RTW_HEADER_rtmodel_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rtw_proj.tmw b/firmware/src/P417_SWTR_App_ert_rtw/rtw_proj.tmw new file mode 100644 index 0000000..d640ddd --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rtw_proj.tmw @@ -0,0 +1,4 @@ +Simulink Coder project for P417_SWTR_App using . MATLAB root = D:\MATLAB\R2017b. SimStruct date: 27-7-2017 18:43:00 +This file is generated by Simulink Coder for use by the make utility +to determine when to rebuild objects when the name of the current Simulink Coder project changes. +The rtwinfomat located at: ..\slprj\ert\P417_SWTR_App\tmwinternal\binfo.mat diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rtwtypes.h b/firmware/src/P417_SWTR_App_ert_rtw/rtwtypes.h new file mode 100644 index 0000000..34ae24f --- /dev/null +++ b/firmware/src/P417_SWTR_App_ert_rtw/rtwtypes.h @@ -0,0 +1,156 @@ +/* + * File: rtwtypes.h + * + * Code generated for Simulink model 'P417_SWTR_App'. + * + * Model version : 1.165 + * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 + * C/C++ source code generated on : Sun Jun 25 21:59:14 2023 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTWTYPES_H +#define RTWTYPES_H + +/* Logical type definitions */ +#if (!defined(__cplusplus)) +# ifndef false +# define false (0U) +# endif + +# ifndef true +# define true (1U) +# endif +#endif + +/*=======================================================================* + * Target hardware information + * Device type: Intel->x86-64 (Windows64) + * Number of bits: char: 8 short: 16 int: 32 + * long: 32 + * native word size: 64 + * Byte ordering: LittleEndian + * Signed integer division rounds to: Zero + * Shift right on a signed integer as arithmetic shift: on + *=======================================================================*/ + +/*=======================================================================* + * Fixed width word size data types: * + * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * + * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * + * real32_T, real64_T - 32 and 64 bit floating point numbers * + *=======================================================================*/ +typedef signed char int8_T; +typedef unsigned char uint8_T; +typedef short int16_T; +typedef unsigned short uint16_T; +typedef int int32_T; +typedef unsigned int uint32_T; +typedef float real32_T; +typedef double real64_T; + +/*===========================================================================* + * Generic type definitions: boolean_T, char_T, byte_T, int_T, uint_T, * + * real_T, time_T, ulong_T. * + *===========================================================================*/ +typedef double real_T; +typedef double time_T; +typedef unsigned char boolean_T; +typedef int int_T; +typedef unsigned int uint_T; +typedef unsigned long ulong_T; +typedef char char_T; +typedef unsigned char uchar_T; +typedef char_T byte_T; + +/*===========================================================================* + * Complex number type definitions * + *===========================================================================*/ +#define CREAL_T + +typedef struct { + real32_T re; + real32_T im; +} creal32_T; + +typedef struct { + real64_T re; + real64_T im; +} creal64_T; + +typedef struct { + real_T re; + real_T im; +} creal_T; + +#define CINT8_T + +typedef struct { + int8_T re; + int8_T im; +} cint8_T; + +#define CUINT8_T + +typedef struct { + uint8_T re; + uint8_T im; +} cuint8_T; + +#define CINT16_T + +typedef struct { + int16_T re; + int16_T im; +} cint16_T; + +#define CUINT16_T + +typedef struct { + uint16_T re; + uint16_T im; +} cuint16_T; + +#define CINT32_T + +typedef struct { + int32_T re; + int32_T im; +} cint32_T; + +#define CUINT32_T + +typedef struct { + uint32_T re; + uint32_T im; +} cuint32_T; + +/*=======================================================================* + * Min and Max: * + * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * + * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * + *=======================================================================*/ +#define MAX_int8_T ((int8_T)(127)) +#define MIN_int8_T ((int8_T)(-128)) +#define MAX_uint8_T ((uint8_T)(255U)) +#define MAX_int16_T ((int16_T)(32767)) +#define MIN_int16_T ((int16_T)(-32768)) +#define MAX_uint16_T ((uint16_T)(65535U)) +#define MAX_int32_T ((int32_T)(2147483647)) +#define MIN_int32_T ((int32_T)(-2147483647-1)) +#define MAX_uint32_T ((uint32_T)(0xFFFFFFFFU)) + +/* Block D-Work pointer type */ +typedef void * pointer_T; + +#endif /* RTWTYPES_H */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/firmware/src/P417_SWTR_App_ert_rtw/rtwtypeschksum.mat b/firmware/src/P417_SWTR_App_ert_rtw/rtwtypeschksum.mat new file mode 100644 index 0000000..5add3d3 Binary files /dev/null and b/firmware/src/P417_SWTR_App_ert_rtw/rtwtypeschksum.mat differ diff --git a/firmware/src/RTE/RTE.c b/firmware/src/RTE/RTE.c new file mode 100644 index 0000000..e053c98 --- /dev/null +++ b/firmware/src/RTE/RTE.c @@ -0,0 +1,1532 @@ +//For SWTR + +#include "RTE.h" + + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "../OsekCom/OsekCom.h" +#include "../Speaker/Speaker.h" +#include "TouchPanel/TouchPanel.h" +//For SWTL + +#include "forceSnsr.h" +#include "forceSnsr_Cfg.h" +#include "forcedetect.h" +#include "TouchPanel.h" +//#include "TouchPanel_Cfg.h" +#include "Std_Types.h" +#include "device.h" +#include "touch/touch.h" +#include "math.h" +#include "stdlib.h" + + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "OsekCom/OsekCom.h" +#include "Speaker/Speaker.h" + +#include "TouchPanel/TouchPanel.h" +#include "forceSnsr/forcedetect.h" +#include "TLE9263/TLE926x_Main.h" +#include "DiagnosticR/UDS/UDS_Services_Common.h" +#include "plib_systick.h" +#include "FunctionState.h" + + + + +//#include "Global.h" +#ifndef uint8_t +#define uint8_t unsigned char +#endif + +#ifndef uint16_t +#define uint16_t unsigned short +#endif + +#ifndef uint32_t +#define uint32_t unsigned int +#endif +extern uint8 CurrentPosition; +extern uint8_t PressState; +uint16 Fr08_send_flag; + +uint8_t Two_Finger_Y_count = 0; +uint8_t Two_Finger_X_count = 0; +uint8_t X_count = 0; +uint8_t Y_count = 0; + +uint16_t Touch_Sensor_Sts00; + uint16_t Touch_Sensor_Sts01; + uint16_t Touch_Sensor_Sts02; + uint16_t Touch_Sensor_Sts03; + uint16_t Touch_Sensor_Sts04; + uint16_t Touch_Sensor_Sts05; + uint16_t Touch_Sensor_Sts06; + uint16_t Touch_Sensor_Sts07; + uint16_t Touch_Sensor_Sts08; + uint16_t Touch_Sensor_Sts09; + uint16_t Touch_Sensor_Sts10; + uint16_t Touch_Sensor_Sts11; + uint16_t Touch_Sensor_Sts12; + uint16_t Touch_Sensor_Sts13; + uint16_t Touch_Sensor_Sts14; + uint8_t Allow_Touch_flag = 0; + +#if 0 +static uint8_t autoCrc_Table[256] = + + { + + 0x00u, 0x1du, 0x3au, 0x27u, 0x74u, 0x69u, 0x4eu, 0x53u, + + 0xe8u, 0xf5u, 0xd2u, 0xcfu, 0x9cu, 0x81u, 0xa6u, 0xbbu, + + 0xcdu, 0xd0u, 0xf7u, 0xeau, 0xb9u, 0xa4u, 0x83u, 0x9eu, + + 0x25u, 0x38u, 0x1fu, 0x02u, 0x51u, 0x4cu, 0x6bu, 0x76u, + + 0x87u, 0x9au, 0xbdu, 0xa0u, 0xf3u, 0xeeu, 0xc9u, 0xd4u, + + 0x6fu, 0x72u, 0x55u, 0x48u, 0x1bu, 0x06u, 0x21u, 0x3cu, + + 0x4au, 0x57u, 0x70u, 0x6du, 0x3eu, 0x23u, 0x04u, 0x19u, + + 0xa2u, 0xbfu, 0x98u, 0x85u, 0xd6u, 0xcbu, 0xecu, 0xf1u, + + 0x13u, 0x0eu, 0x29u, 0x34u, 0x67u, 0x7au, 0x5du, 0x40u, + + 0xfbu, 0xe6u, 0xc1u, 0xdcu, 0x8fu, 0x92u, 0xb5u, 0xa8u, + + 0xdeu, 0xc3u, 0xe4u, 0xf9u, 0xaau, 0xb7u, 0x90u, 0x8du, + + 0x36u, 0x2bu, 0x0cu, 0x11u, 0x42u, 0x5fu, 0x78u, 0x65u, + + 0x94u, 0x89u, 0xaeu, 0xb3u, 0xe0u, 0xfdu, 0xdau, 0xc7u, + + 0x7cu, 0x61u, 0x46u, 0x5bu, 0x08u, 0x15u, 0x32u, 0x2fu, + + 0x59u, 0x44u, 0x63u, 0x7eu, 0x2du, 0x30u, 0x17u, 0x0au, + + 0xb1u, 0xacu, 0x8bu, 0x96u, 0xc5u, 0xd8u, 0xffu, 0xe2u, + + 0x26u, 0x3bu, 0x1cu, 0x01u, 0x52u, 0x4fu, 0x68u, 0x75u, + + 0xceu, 0xd3u, 0xf4u, 0xe9u, 0xbau, 0xa7u, 0x80u, 0x9du, + + 0xebu, 0xf6u, 0xd1u, 0xccu, 0x9fu, 0x82u, 0xa5u, 0xb8u, + + 0x03u, 0x1eu, 0x39u, 0x24u, 0x77u, 0x6au, 0x4du, 0x50u, + + 0xa1u, 0xbcu, 0x9bu, 0x86u, 0xd5u, 0xc8u, 0xefu, 0xf2u, + + 0x49u, 0x54u, 0x73u, 0x6eu, 0x3du, 0x20u, 0x07u, 0x1au, + + 0x6cu, 0x71u, 0x56u, 0x4bu, 0x18u, 0x05u, 0x22u, 0x3fu, + + 0x84u, 0x99u, 0xbeu, 0xa3u, 0xf0u, 0xedu, 0xcau, 0xd7u, + + 0x35u, 0x28u, 0x0fu, 0x12u, 0x41u, 0x5cu, 0x7bu, 0x66u, + + 0xddu, 0xc0u, 0xe7u, 0xfau, 0xa9u, 0xb4u, 0x93u, 0x8eu, + + 0xf8u, 0xe5u, 0xc2u, 0xdfu, 0x8cu, 0x91u, 0xb6u, 0xabu, + + 0x10u, 0x0du, 0x2au, 0x37u, 0x64u, 0x79u, 0x5eu, 0x43u, + + 0xb2u, 0xafu, 0x88u, 0x95u, 0xc6u, 0xdbu, 0xfcu, 0xe1u, + + 0x5au, 0x47u, 0x60u, 0x7du, 0x2eu, 0x33u, 0x14u, 0x09u, + + 0x7fu, 0x62u, 0x45u, 0x58u, 0x0bu, 0x16u, 0x31u, 0x2cu, + + 0x97u, 0x8au, 0xadu, 0xb0u, 0xe3u, 0xfeu, 0xd9u, 0xc4u + + }; +#endif + + +//volatile uint8_t TouchBoard_RC; + +//volatile uint8_t TouchBoard_Sts; +//volatile uint8_t TouchBoard_X; +//volatile uint8_t TouchBoard_Y; +uint8_t RTE_Get_TouchBoard_CRC(void) +{ + return 0; +} + + + + + + +//Input Sensor +//uint16_t RTE_Get_Power_AD_SNS(void); + +//uint8_t RTE_Get_Pressure_Sensor_xxxx(void);//IIC DATA? + +//Not active,Touch,Touch and Press,invalid from sensor + + +uint8_t RTE_Get_SldVolCtrlSts(void) //0 slip idle 1 decrease ,2 increase , 3 decrease double , 4 increase double ,5 decrease third, 6 increase third +{ + TP_SlideLevel_Enum UD_SlideLevel = TP_SlideLevel_NONE; + UD_SlideLevel = TouchPanel_SlideUpDownLevelRead(); + return (uint8_t)UD_SlideLevel; +} + + +uint8_t RTE_Get_TouchBoard_Up_Sts(void) +{ + /* y:a7, x: e6 */ + /* y:8d, x: eb */ + /* y:75, x: ed */ + /* y:6a, x: eb */ + /* y:75, x: eb */ + Buttons_SignalType Signal = BUTTON_RELEASE; + if(CurrentPosition == 4) + { + Signal = TouchPanel_BtnSignalRead(BTN_UP); + } + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + + return Signal; +} + +uint8_t RTE_Get_TouchBoard_Down_Sts(void) +{ + /* x:26, y: 96 */ + /* x:20, y: 80 */ + /* x:20, y: 80 */ + Buttons_SignalType Signal = BUTTON_RELEASE; + if(CurrentPosition == 5) + { + Signal = TouchPanel_BtnSignalRead(BTN_DOWN);} + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} + +uint8_t RTE_Get_TouchBoard_Left_Sts(void) +{ + /* x:95, y: ec */ + /* x:97, y: e9 */ + Buttons_SignalType Signal = BUTTON_RELEASE; + if(CurrentPosition == 6) + { + Signal = TouchPanel_BtnSignalRead(BTN_LEFT);} + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} + +uint8_t RTE_Get_TouchBoard_Right_Sts(void) +{ + /* x:98, y: 22 */ + /* x:9d, y: 27 */ + /* x:94, y: 25 */ + Buttons_SignalType Signal = BUTTON_RELEASE; + if(CurrentPosition == 7) + { + Signal = TouchPanel_BtnSignalRead(BTN_RIGHT);} + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} + +uint8_t RTE_Get_TouchBoard_Center_Sts(void) +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + if(CurrentPosition == 8) + { + Signal = TouchPanel_BtnSignalRead(BTN_CONFIRM);} + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} + +uint8_t g_VOICE_Touch_And_Below_1N = 0; +uint8_t RTE_Get_TouchBoard_VOICE1_Sts(void)//TJP1 +{ +#if 0 + Buttons_SignalType Signal; + // PanelPress_LevelType Press_Level; + Signal = TouchPanel_BtnSignalRead(BTN_VOICE1); + //Press_Level = TouchPanel_PressLevelRead(); + if( TouchButton_is_TouchActive(BTN_VOICE1) == TRUE)//PANEL_PRESS_LEVEL0 == Press_Level && + { + g_VOICE_Touch_And_Below_1N = 0x01; + }else{ + g_VOICE_Touch_And_Below_1N = 0x00; + } + + return Signal; +#endif + Buttons_SignalType Signal = BUTTON_RELEASE; + static uint8_t Voice_Zero_Count = 0; + if(CurrentPosition == 1) + { + Signal=k_voice_touch_Sts; + } + if( Signal != 0 )//PANEL_PRESS_LEVEL0 == Press_Level && + { + g_VOICE_Touch_And_Below_1N = 0x01; + Voice_Zero_Count = 0; + }else{ + Voice_Zero_Count++; + if(Voice_Zero_Count>6) + { + g_VOICE_Touch_And_Below_1N = 0x00; + Voice_Zero_Count = 7; + } + } + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} +uint8_t RTE_Get_TouchBoard_VOICE2_Sts(void)//TJP2 +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + //Signal = TouchPanel_BtnSignalRead(BTN_VOICE2); + + return Signal; +} + +uint8_t g_MENU_Touch_And_Below_1N = 0; +uint8_t RTE_Get_TouchBoard_MENU1_Sts(void)//Resume1 +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + static uint8_t Menu_Zero_Count = 0; + if(CurrentPosition == 3) + { + Signal = k_menu_touch_Sts;//TouchPanel_BtnSignalRead(BTN_MENU1); + } + if( Signal != 0)//PANEL_PRESS_LEVEL0 == Press_Level && + { + g_MENU_Touch_And_Below_1N = 0x01; + Menu_Zero_Count = 0; + }else{ + Menu_Zero_Count++; + if(Menu_Zero_Count > 6) + { + g_MENU_Touch_And_Below_1N = 0x00; + Menu_Zero_Count = 7; + } + } + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} +uint8_t RTE_Get_TouchBoard_MENU2_Sts(void)//Resume2 +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + //Signal = TouchPanel_BtnSignalRead(BTN_MENU2); + + return Signal; +} + +uint8_t g_VOL_Touch_And_Below_1N = 0; +uint8_t RTE_Get_TouchBoard_VOL1_Sts(void)//Cancel1 +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + static uint8_t VOL_Zero_Count = 0; + if(CurrentPosition == 2) + { + // PanelPress_LevelType Press_Level; + Signal = k_vol_touch_Sts;//TouchPanel_BtnSignalRead(BTN_VOL1); + //Press_Level = TouchPanel_PressLevelRead(); + } + + if(Signal != 0)//PANEL_PRESS_LEVEL0 == Press_Level && + { + g_VOL_Touch_And_Below_1N = 0x01; + VOL_Zero_Count=0; + }else{ + VOL_Zero_Count++; + if(VOL_Zero_Count>6) + { + g_VOL_Touch_And_Below_1N = 0x00; + VOL_Zero_Count=7; + } + } + if(Allow_Touch_flag==0) + { + Signal = 0; + } + if (PressState == 0) + { + Signal = BUTTON_RELEASE; + } + return Signal; +} +uint8_t RTE_Get_TouchBoard_VOL2_Sts(void)//Cancel2 +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + //Signal = TouchPanel_BtnSignalRead(BTN_VOL2); + + return Signal; +} + + +//touch borad left/right slide: 0:idle, 1:short slide left 2:short slide right 3:long slide left 4:long slide right +uint8_t RTE_Get_TouchBoard_Left_Right_Slide_Sts(void) +{ + uint8_t retval = SIG_SWPLERISTSRI_SWPLERIREQSTS_IDLE; +#if 1 + TP_SlideDirection_Enum SlideDir; + SlideDir = TouchPanel_SlideEventRead(); + switch(SlideDir) + { + case TP_SlideDirection_ShortLEFT: + retval = SIG_SWPLERISTSRI_SWPLERIREQSTS_SHORTSLIDELEFT; + break; + case TP_SlideDirection_LongLEFT: + retval = SIG_SWPLERISTSRI_SWPLERIREQSTS_LONGSLIDELEFT; + break; + case TP_SlideDirection_ShortRIGHT: + retval = SIG_SWPLERISTSRI_SWPLERIREQSTS_SHORTSLIDERIGHT; + break; + case TP_SlideDirection_LongRIGHT: + retval = SIG_SWPLERISTSRI_SWPLERIREQSTS_LONGSLIDERIGHT; + break; + default: break; + } +#endif + return retval; +} + +//touch borad Up/Down slide: 0:idle, 1:short slide up 2:short slide down 3:long slide up 4:long slide down +uint8_t RTE_Get_TouchBoard_Up_Down_Slide_Sts(void) +{ + uint8_t retval = SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_IDLE; +#if 1 + TP_SlideDirection_Enum SlideDir; + SlideDir = TouchPanel_SlideEventRead(); + switch(SlideDir) + { + case TP_SlideDirection_ShortUP: + retval = SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_SHORTSLIDEUP; + break; + case TP_SlideDirection_LongUP: + retval = SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_LONGSLIDEUP; + break; + case TP_SlideDirection_ShortDOWN: + retval = SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_SHORTSLIDEDOWN; + break; + case TP_SlideDirection_LongDOWN: + retval = SIG_SWPUPDWNSTSRI_SWPUPDWNREQSTS_LONGSLIDEDOWN; + break; + default: break; + } + +#endif + return retval; +} + + +//uint8_t RTE_Get_INTB_PRSS_SNS(void); + + + +//uint8_t RTE_Get_X1_SNS(void); +//uint8_t RTE_Get_X2_SNS(void); +//uint8_t RTE_Get_X3_SNS(void); +//uint8_t RTE_Get_X4_SNS(void); +//uint8_t RTE_Get_X5_SNS(void); + + +#define X_Length 6 +#define Y_Length 6 + +#define Initial_Movement_Hysteresis 10 +#define Next_Movement_Hysteresis 5 + +uint8_t X_Buf[X_Length]; +uint8_t Y_Buf[Y_Length]; +uint8_t X_CNT=0; +uint8_t Y_CNT=0; +uint8_t Stable_CNT_X=0; +uint8_t Stable_CNT_Y=0; +uint8_t X_Update_Flg=1; +uint8_t Y_Update_Flg=1; +uint8_t X_Update=0; +uint8_t Y_Update=0; +uint8_t rtn_X=0; +uint8_t rtn_Y=0; + +uint8_t RTE_Get_X_SNS(void) +{ +#if 0 + uint8_t count; + uint16_t sum_x=0; + uint8 x_pos; + GetSurface_Position(&x_pos, NULL_PTR); + X_Buf[X_CNT++]=x_pos; + if(X_CNT==X_Length) + { + X_CNT=0; + } + for(count=0;countX_Buf[i+1]) + { + temp=X_Buf[i]; + X_Buf[i]=X_Buf[i+1]; + X_Buf[i+1]=temp; + } + } + } + if(X_Buf[X_Length-1]-X_Buf[0]10) + { + Stable_CNT_X=10; + X_Update_Flg=0; + rtn_X= X_Update; + if( (X_Buf[0]+X_Buf[X_Length-1])/2-X_Update>0) + { + if((X_Buf[0]+X_Buf[X_Length-1])/2-X_Update>Next_Movement_Hysteresis) + { + Stable_CNT_X=0; + X_Update_Flg=1; + } + } + else + { + if(X_Update-(X_Buf[0]+X_Buf[X_Length-1])/2>Next_Movement_Hysteresis) + { + Stable_CNT_X=0; + X_Update_Flg=1; + } + } + } + } + else + { + Stable_CNT_X=0; + X_Update_Flg=1; + rtn_X= (X_Buf[X_Length/2]+X_Buf[X_Length/2-1])/2; + } + if(x_pos==0) + { + rtn_X=0; + } + return rtn_X; + +#endif + +} + + +//uint8_t RTE_Get_Y1_SNS(void); +//uint8_t RTE_Get_Y2_SNS(void); +//uint8_t RTE_Get_Y3_SNS(void); +//uint8_t RTE_Get_Y4_SNS(void); +//uint8_t RTE_Get_Y5_SNS(void); +uint8_t RTE_Get_Y_SNS(void) +{ +#if 0 + uint8_t count; + uint16_t sum_y=0; + uint8 y_pos; + GetSurface_Position(NULL_PTR, &y_pos); + Y_Buf[Y_CNT++]=y_pos; + if(Y_CNT==Y_Length) + { + Y_CNT=0; + } + for(count=0;countY_Buf[i+1]) + { + temp=Y_Buf[i]; + Y_Buf[i]=Y_Buf[i+1]; + Y_Buf[i+1]=temp; + } + } + } + + if(Y_Buf[Y_Length-1]-Y_Buf[0]10) + { + Stable_CNT_Y=10; + Y_Update_Flg=0; + rtn_Y= Y_Update; + if( (Y_Buf[0]+Y_Buf[Y_Length-1])/2-Y_Update>0) + { + if((Y_Buf[0]+Y_Buf[Y_Length-1])/2-Y_Update>Next_Movement_Hysteresis) + { + Stable_CNT_Y=0; + Y_Update_Flg=1; + } + } + else + { + if(Y_Update-(Y_Buf[0]+Y_Buf[Y_Length-1])/2>Next_Movement_Hysteresis) + { + Stable_CNT_Y=0; + Y_Update_Flg=1; + } + } + } + } + else + { + Stable_CNT_Y=0; + Y_Update_Flg=1; + + rtn_Y=(Y_Buf[Y_Length/2]+Y_Buf[Y_Length/2-1])/2; + + } + + if(y_pos==0) + { + rtn_Y=0; + } + return rtn_Y; +#endif + +} + +uint8_t g_XY_Touch_And_Below_1N = 0; + + + + +uint8_t RTE_Get_TouchBoard_XY_Sts(void)//Not active,Touch,Touch and Press,invalid from sensor +{ + //PanelPress_LevelType Press_Level; + Buttons_SignalType XY_Sts = BUTTON_RELEASE; + + XY_Sts = TouchSurface_XY_StsRead(); + + //Press_Level = TouchPanel_PressLevelRead(); + if( TouchSurface_is_TouchActive() == TRUE)//PANEL_PRESS_LEVEL0 == Press_Level && + { + g_XY_Touch_And_Below_1N = 0x01; + }else{ + g_XY_Touch_And_Below_1N = 0x00; + } + return XY_Sts; +} + +#if 1 +uint8_t RTE_Get_TouchBoard_XY_Touch_And_Below_1N(void) // 0 false 1 true +{ + uint8_t ret_val = 0; + uint8_t Two_Finger_Y_data[5] = {}; +uint8_t Two_Finger_X_data [5] = {}; + + + +uint8_t i,m; + + +Two_Finger_Y_data[0]=Touch_Sensor_Sts05; +Two_Finger_Y_data[1]=Touch_Sensor_Sts06; +Two_Finger_Y_data[2]=Touch_Sensor_Sts07; +Two_Finger_Y_data[3]=Touch_Sensor_Sts08; +Two_Finger_Y_data[4]=Touch_Sensor_Sts09; + +Two_Finger_X_data[0]=Touch_Sensor_Sts10; +Two_Finger_X_data[1]=Touch_Sensor_Sts11; +Two_Finger_X_data[2]=Touch_Sensor_Sts12; +Two_Finger_X_data[3]=Touch_Sensor_Sts13; +Two_Finger_X_data[4]=Touch_Sensor_Sts14; + + + + + +Two_Finger_Y_count=0; +for(i=0;i<5;i++) +{ + if(Two_Finger_Y_data[i]>25) + { + Two_Finger_Y_count++; + } + +} + +i=0; +Y_count=0; +while(Two_Finger_Y_data[i++]<=25 && i<5); +i--; +for(;i<5;i++) +{ + if(Two_Finger_Y_data[i]<=25) + break; + else + Y_count++; +} + + + +Two_Finger_X_count=0; +for(m=0;m<5;m++) +{ + if(Two_Finger_X_data[m]>25) + { + Two_Finger_X_count++; + } + +} +m=0; +X_count=0; +while(Two_Finger_X_data[m++]<=25 && m<5); +m--; +for(;m<5;m++) +{ + if(Two_Finger_X_data[m]<=25) + break; + else + X_count++; +} + + +if((Two_Finger_Y_count<=4 && Y_count == Two_Finger_Y_count)&&(Two_Finger_X_count<=4 && X_count == Two_Finger_X_count)) +{ + Allow_Touch_flag=1; + if(g_XY_Touch_And_Below_1N == TRUE || g_VOICE_Touch_And_Below_1N == TRUE || + g_MENU_Touch_And_Below_1N == TRUE || g_VOL_Touch_And_Below_1N == TRUE) + { + ret_val = 0x01; + } + } +else +{ + Allow_Touch_flag=0; +} + return ret_val; +} +#endif + + + +uint8_t RTE_Get_Pad_XY_trig(void) +{ + Buttons_SignalType XY_Sts = BUTTON_RELEASE; + XY_Sts = TouchSurface_is_TouchActive(); + if (PressState == 0) + { + XY_Sts = 0; + } + return XY_Sts; +} +uint8_t RTE_Get_Voice_XY_trig(void) +{ + Buttons_SignalType Signal; + Signal=k_voice_touch_Sts; + if (PressState == 0) + { + Signal = 0; + } + + return Signal; + +} +uint8_t RTE_Get_Menu_XY_trig(void) +{ + Buttons_SignalType Signal; + Signal = k_menu_touch_Sts;//TouchButton_is_TouchActive(BTN_MENU1); + if (PressState == 0) + { + Signal = 0; + } + + return Signal; +} +uint8_t RTE_Get_Vol_XY_trig(void) +{ + Buttons_SignalType Signal; + Signal = k_vol_touch_Sts;//TouchButton_is_TouchActive(BTN_VOL1); + if (PressState == 0) + { + Signal = 0; + } + + return Signal; +} + + + + +uint8_t RTE_Get_ACT_FAULT_OUT_SNS(void) +{ + return 0; +} +uint8_t RTE_Get_ACT_LD_OUT_SNS(void) +{ + return 0; +} + + +//Input CAN +uint8_t rtn_data = 0; + +//LED on off control +uint8_t RTE_Get_CAN_ActvnOfSteerWhlIllmn(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + (void)ReceiveMessage(SIG_ACTVNOFSTEERWHLILLMN, &rtn_data); + + return rtn_data; +} +//LED Day/Night Mode switch +uint8_t RTE_Get_CAN_TwliBriSts(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + (void)ReceiveMessage(SIG_TWLIBRISTS, &rtn_data); + + return rtn_data; +} + + +uint8_t RTE_Get_CAN_IntrBriSts(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + (void)ReceiveMessage(SIG_INTRBRISTS, &rtn_data); + + return rtn_data; +} + +uint8_t RTE_Get_CAN_SteerWhlTouchBdLeFaildFb(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + //(void)ReceiveMessage(SIG_INTRBRISTS, &rtn_data); + + return rtn_data; +} + +uint8_t RTE_Get_CAN_SwtOfKeyTone(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + (void)ReceiveMessage(SIG_SWTOFKEYTONE, &rtn_data); + + return rtn_data; +} + +//Vibration control +uint8_t RTE_Get_CAN_VibrationFbToSwtp(void) +{ + //uint8_t temp = 0; + rtn_data = 0; + + //(void)ReceiveMessage(SIG_SWTOFKEYTONE, &rtn_data); + + return rtn_data; +} + +uint8_t RTE_Get_CAN_IhuPrivateDHUCanFr01_Frame_Timeout(void)//0x030 frame +{ + bool result = false; + //if (ReadFlagRxErrorSig(SIG_) == COM_TRUE) + //{ + // result = true; + //} + return result; +} + +//Output Control + +void RTE_Set_illumination_BL_PWM(uint32_t Percent) +{ + /* to set PWM for LED ,PWM from 0 to 100*/ + uint32_t temp = 0; + static uint32_t local_percent = 0xffffffff; + // uint8_t LED_Delay = 0; + // LED_Delay = SYSTICK_Get1_5_S_Flag(); + // if(LED_Delay==1) + // { + if(Fuction_State == Function_State_A) + { + if(local_percent != Percent) + { + local_percent = Percent; + if(Percent==100000 || Percent==0) //Day mode + { + temp = (7999/100) * Percent/1000; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else//Night mode + { + if(Percent==625) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==729) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==937) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==1146) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==1354) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==1563) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==1875) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==2292) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==2813) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==3333) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==4063) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==4896) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==5938) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==7188) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==8646) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + else if(Percent==10417) + { + temp = (7999/100) * Percent/1000; + temp/=2; + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)temp); + } + } + } + } + // } +} + + +//void RTE_Set_Power_AD_Ctrl(uint8_t Value); + + + + +//ACT control?? +uint8_t trigger_ACT = 0; +void RTE_Set_ACT_Vibration(uint8_t Sts) +{ + if (Sts==1) + { + if (trigger_ACT == 0) + { + trigger_ACT = 1; + // speeker_Tig_Once(50, SA51024_STRENGTH_LEVEL3); + } + + } +else + { + trigger_ACT = 0; + } + +} +//void RTE_Set_Gain0(uint8_t Value); +//void RTE_Set_Gain1(uint8_t Value); +//void RTE_Set_SDZ(uint8_t Value); +//void RTE_Set_INP(uint8_t Value); + +//Output CAN +void RTE_Set_CAN_RiMFctActSgCe(uint8_t Value) +{ + InitMessage(SIG_RIMFCTACTSGCE, &Value); +} + +void RTE_Set_CAN_RiMFctActSgDn(uint8_t Value) +{ + InitMessage(SIG_RIMFCTACTSGDN, &Value); +} + +void RTE_Set_CAN_RiMFctActSgLe(uint8_t Value) +{ + InitMessage(SIG_RIMFCTACTSGLE, &Value); +} + +void RTE_Set_CAN_RiMFctActSgRi(uint8_t Value) +{ + InitMessage(SIG_RIMFCTACTSGRI, &Value); +} + +void RTE_Set_CAN_RiMFctActSgUp(uint8_t Value) +{ + InitMessage(SIG_RIMFCTACTSGUP, &Value); +} + +void RTE_Set_CAN_SteerWhlTouchBdVoice(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDVOICE, &Value); +} + +void RTE_Set_CAN_SwpLeRiStsRi(uint8_t Value) +{ + InitMessage(SIG_SWPLERISTSRI, &Value); +} + +void RTE_Set_CAN_SwpUpDwnStsRi(uint8_t Value) +{ + InitMessage(SIG_SWPUPDWNSTSRI, &Value); +} + +void RTE_Set_CAN_SldVolCtrlSts(uint8_t Value) +{ + InitMessage(SIG_SLDVOLCTRLSTS, &Value); +} + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRCmnFltSts(uint8_t Value) +{ + //InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRCMNFLTSTS, &Value); +} + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRTouchdFltSts(uint8_t Value) +{ + //InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRTOUCHDFLTSTS, &Value); +} + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRVibrationFltSts(uint8_t Value) +{ + //InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRVIBRATIONFLTSTS, &Value); +} + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRSnsrFltSts(uint8_t Value) +{ + //InitMessage(SIG_DIAGCFAILRTOUCHPANSWTRSNSRFLTSTS, &Value); +} + + + +void RTE_Set_CAN_SteerWhlTouchBdMenu(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDMENU, &Value); + +} + + + +void RTE_Set_CAN_SteerWhlTouchBdDn(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDDN, &Value); +} + +void RTE_Set_CAN_SteerWhlTouchBdRiChks(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDRICHKS, &Value); + +} + +void RTE_Set_CAN_SteerWhlTouchBdRiCntr(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDRICNTR, &Value); + //TouchBoard_RC=Value; +} + + +uint8_t g_last_SteerWhlTouchBdSts = BUTTON_RELEASE; +void RTE_Set_CAN_SteerWhlTouchBdRiSteerWhlTouchBdSts(uint8_t Value) +{ + + + //Vibra_force_level=Vibra_PressCheck(); + // if((Vibra_force_level == 2 && last_Vibra_force_level != 2) || + // (Vibra_force_level != 1 && last_Vibra_force_level == 1)) + // { + // speeker_Tig_Once(49, SA51024_STRENGTH_LEVEL2); + // } + // g_last_SteerWhlTouchBdSts = Value; + //last_Vibra_force_level=Vibra_force_level; + InitMessage(SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS, &Value); + //TouchBoard_Sts=Value; +} + + +void RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDRITOUCHPOSNX, &Value); + // TouchBoard_X=Value; +} +void RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(uint8_t Value) +{ + InitMessage(SIG_STEERWHLTOUCHBDRITOUCHPOSNY, &Value); + //TouchBoard_Y=Value; +} + +uint8_t Pre_309_req; +uint8_t Remain_frame; +uint8_t Remain_cnt; +uint8_t Remain_X = 0; +uint8_t Remain_Y = 0; +uint8_t Frame_0x309_RC = 15; +void RTE_Set_SEND_CAN_0x309_immediately(uint8_t Value) //called immediately in 10ms task when touch,or touch and press in XY area +{ + uint8_t Current_309_req; + Current_309_req=Value; + + if(Value==1) + { + if(Frame_0x309_RC > 14){ + Frame_0x309_RC = 0; + }else{ + Frame_0x309_RC++; + } + InitMessage(SIG_STEERWHLTOUCHBDRICNTR, &Frame_0x309_RC); + //Send a 0x309 frame + + OsekComTxReqFrmSwtrPrivateDHUCanFr01(); + } + if(Value==0&&Pre_309_req==1) + { + Remain_frame=1; + } + Pre_309_req=Current_309_req; + + if(Remain_frame==1) + { + InitMessage(SIG_STEERWHLTOUCHBDRITOUCHPOSNX, &Remain_X); + InitMessage(SIG_STEERWHLTOUCHBDRITOUCHPOSNY, &Remain_Y); + InitMessage(SIG_STEERWHLTOUCHBDRISTEERWHLTOUCHBDSTS, &Remain_Y); + if(Remain_cnt<2) + { + if(Frame_0x309_RC > 14){ + Frame_0x309_RC = 0; + }else{ + Frame_0x309_RC++; + } + InitMessage(SIG_STEERWHLTOUCHBDRICNTR, &Frame_0x309_RC); + OsekComTxReqFrmSwtrPrivateDHUCanFr01(); + Remain_cnt++; + } + else + { + Remain_frame=0; + Remain_cnt=0; + } + } + +} +void RTE_Set_SEND_CAN_0x307_25ms(uint8_t Value) // when touch,or touch and press in 3 button area,0x305 is sent every 25ms +{ + if(Value==1) + { + + //Send a 0x307 frame + + OsekComTxReqFrmSwtrPrivateDHUCanFr02(); + } +} + +void RTE_Set_SEND_CAN_0x307_1000ms(uint8_t Value) // when 3 button area is not active,0x305 is Sent every 1000ms +{ + if(Value==1) + { + + //Send a 0x307 frame + + OsekComTxReqFrmSwtrPrivateDHUCanFr02(); + } +} + +uint8_t UbInitValue = 1; +void RTE_Set_All_UB(void) +{ + InitMessage(SIG_DIAGCFAILRTOUCHPANSWTR_UB, &UbInitValue); + InitMessage(SIG_RIMFCTACTSGCE_UB, &UbInitValue); + InitMessage(SIG_RIMFCTACTSGDN_UB, &UbInitValue); +InitMessage(SIG_RIMFCTACTSGLE_UB, &UbInitValue); +InitMessage(SIG_RIMFCTACTSGRI_UB, &UbInitValue); +InitMessage(SIG_RIMFCTACTSGUP_UB, &UbInitValue); +InitMessage(SIG_SLDVOLCTRLSTS_UB, &UbInitValue); +InitMessage(SIG_STEERWHLTOUCHBDDN_UB, &UbInitValue); +InitMessage(SIG_STEERWHLTOUCHBDMENU_UB, &UbInitValue); +InitMessage(SIG_STEERWHLTOUCHBDRI_UB, &UbInitValue); +InitMessage(SIG_STEERWHLTOUCHBDVOICE_UB, &UbInitValue); +InitMessage(SIG_SWPLERISTSRI_UB, &UbInitValue); +InitMessage(SIG_SWPUPDWNSTSRI_UB, &UbInitValue); +InitMessage(SIG_SWTRPARTNOCMPL_UB, &UbInitValue); +InitMessage(SIG_SWTRSERNO_UB, &UbInitValue); +} + + + +#if 1 +void RTE_Set_All_Test_Value(void) +{ +#if 1 + uint16_t Press_baseline; + uint16_t Press_signal,Press_preload; + Press_baseline=Get_forcedetect_basline_value(); + Press_signal=Get_forcedetect_force_value(); + Press_preload = Get_forcedetect_preload_value(); + //uint16 temp = CurrentPosition; + InitMessage(SIG_SWTRPRESSBASELINE, &Press_baseline);//Press_baseline + if(Press_signal<4000) + { + InitMessage(SIG_SWTRPRESSSIGNAL, &Press_signal);//Press_signal-Convert to N: TouchPanel_PressNValue = ((float32)Press_signal / (float32)0xF2); + } + //InitMessage(SIG_SWTRPRESSSIGNAL, &Fr08_send_flag); +#endif + +#if 0 +//extern volatile uint8 Over3N_vibra_req; +//extern volatile uint8 Below1P5N_vibra_req; +uint16_t Press_baseline; + uint16_t Press_signal; + Press_baseline=Get_forcedetect_basline_value(); + Press_signal=Get_forcedetect_force_value(); + + +InitMessage(SIG_SWTRPRESSBASELINE, &Below1P5N_vibra_req);//Press_baseline +InitMessage(SIG_SWTRPRESSSIGNAL, &Over3N_vibra_req); + +#endif + +//uint8_t Two_Finger_X_count = 0; + +//uint8_t X_count = 0; + +#if 0 + uint16_t Press_baseline; + uint16_t Press_signal; + Press_baseline=(uint16_t)Two_Finger_X_count; + Press_signal=(uint16_t)X_count; + //uint16 temp = CurrentPosition; + + + + InitMessage(SIG_SWTRPRESSBASELINE, &Press_baseline);//Press_baseline + InitMessage(SIG_SWTRPRESSSIGNAL, &Press_signal); +#endif + + + + + uint16_t Touch_Sensor_Ref00; + uint16_t Touch_Sensor_Ref01; + uint16_t Touch_Sensor_Ref02; + uint16_t Touch_Sensor_Ref03; + uint16_t Touch_Sensor_Ref04; + uint16_t Touch_Sensor_Ref05; + uint16_t Touch_Sensor_Ref06; + uint16_t Touch_Sensor_Ref07; + uint16_t Touch_Sensor_Ref08; + uint16_t Touch_Sensor_Ref09; + uint16_t Touch_Sensor_Ref10; + uint16_t Touch_Sensor_Ref11; + uint16_t Touch_Sensor_Ref12; + uint16_t Touch_Sensor_Ref13; + uint16_t Touch_Sensor_Ref14; + + //uint8_t Touch_Sensor_Sts13; +#if 1 + //Touch_Sensor_Sts00 = (uint16_t)g_VOICE_Touch_And_Below_1N; + //Touch_Sensor_Sts01 = (uint16_t)g_MENU_Touch_And_Below_1N; + //Touch_Sensor_Sts02= (uint16_t)g_VOL_Touch_And_Below_1N; + + Touch_Sensor_Sts00 = abs(get_sensor_node_signal(0U)-get_sensor_node_reference(0U)); + Touch_Sensor_Sts01 = abs(get_sensor_node_signal(1U)-get_sensor_node_reference(1U)); + Touch_Sensor_Sts02= abs(get_sensor_node_signal(2U)-get_sensor_node_reference(2U)); + Touch_Sensor_Sts03= abs(get_sensor_node_signal(3U)-get_sensor_node_reference(3U)); + Touch_Sensor_Sts04= abs(get_sensor_node_signal(4U)-get_sensor_node_reference(4U)); + Touch_Sensor_Sts05= abs(get_sensor_node_signal(5U)-get_sensor_node_reference(5U)); + Touch_Sensor_Sts06= abs(get_sensor_node_signal(6U)-get_sensor_node_reference(6U)); + Touch_Sensor_Sts07= abs(get_sensor_node_signal(7U)-get_sensor_node_reference(7U)); + Touch_Sensor_Sts08= abs(get_sensor_node_signal(8U)-get_sensor_node_reference(8U)); + Touch_Sensor_Sts09=abs(get_sensor_node_signal(9U)-get_sensor_node_reference(9U)); + Touch_Sensor_Sts10= abs(get_sensor_node_signal(10U)-get_sensor_node_reference(10U)); + Touch_Sensor_Sts11= abs(get_sensor_node_signal(11U)-get_sensor_node_reference(11U)); + Touch_Sensor_Sts12= abs(get_sensor_node_signal(12U)-get_sensor_node_reference(12U)); + Touch_Sensor_Sts13= abs(get_sensor_node_signal(13U)-get_sensor_node_reference(13U)); + Touch_Sensor_Sts14= abs(get_sensor_node_signal(14U)-get_sensor_node_reference(14U)); +#endif + +#if 0 + + Touch_Sensor_Sts00 = get_scroller_position(0x00); + + +#endif + + + //get_sensor_state + + + + + + +#if 1 + //k_voice_touch_Sts + //Touch_Sensor_Ref00=(uint16_t)k_voice_touch_Sts; + //Touch_Sensor_Ref01=(uint16_t)k_vol_touch_Sts; + //Touch_Sensor_Ref02=(uint16_t)k_menu_touch_Sts; + Touch_Sensor_Ref00=get_sensor_node_reference(0U); + Touch_Sensor_Ref01=get_sensor_node_reference(1U); + Touch_Sensor_Ref02=get_sensor_node_reference(2U); + Touch_Sensor_Ref03=get_sensor_node_reference(3U); + Touch_Sensor_Ref04=get_sensor_node_reference(4U); + Touch_Sensor_Ref05=get_sensor_node_reference(5U); + Touch_Sensor_Ref06=get_sensor_node_reference(6U); + Touch_Sensor_Ref07=get_sensor_node_reference(7U); + Touch_Sensor_Ref08=get_sensor_node_reference(8U); + Touch_Sensor_Ref09=get_sensor_node_reference(9U); + Touch_Sensor_Ref10=get_sensor_node_reference(10U); + Touch_Sensor_Ref11=get_sensor_node_reference(11U); + Touch_Sensor_Ref12=get_sensor_node_reference(12U); + Touch_Sensor_Ref13=get_sensor_node_reference(13U); + Touch_Sensor_Ref14=get_sensor_node_reference(14U); +#endif + + + //Touch_Sensor_Sts13=g_XY_Touch_And_Below_1N; + + InitMessage(SIG_SWTRSENSOR1_SIGNAL, &Touch_Sensor_Sts00); + InitMessage(SIG_SWTRSENSOR2_SIGNAL, &Touch_Sensor_Sts01); + InitMessage(SIG_SWTRSENSOR3_SIGNAL, &Touch_Sensor_Sts02); + InitMessage(SIG_SWTRSENSOR4_SIGNAL, &Touch_Sensor_Sts03); + InitMessage(SIG_SWTRSENSOR5_SIGNAL, &Touch_Sensor_Sts04); + InitMessage(SIG_SWTRSENSOR6_SIGNAL, &Touch_Sensor_Sts05); + InitMessage(SIG_SWTRSENSOR7_SIGNAL, &Touch_Sensor_Sts06); + InitMessage(SIG_SWTRSENSOR8_SIGNAL, &Touch_Sensor_Sts07); + InitMessage(SIG_SWTRSENSOR9_SIGNAL, &Touch_Sensor_Sts08); + InitMessage(SIG_SWTRSENSOR10_SIGNAL, &Touch_Sensor_Sts09); + InitMessage(SIG_SWTRSENSOR11_SIGNAL, &Touch_Sensor_Sts10); + InitMessage(SIG_SWTRSENSOR12_SIGNAL, &Touch_Sensor_Sts11); + InitMessage(SIG_SWTRSENSOR13_SIGNAL, &Touch_Sensor_Sts12); + InitMessage(SIG_SWTRSENSOR14_SIGNAL, &Touch_Sensor_Sts13); + InitMessage(SIG_SWTRSENSOR15_SIGNAL, &Touch_Sensor_Sts14); + + InitMessage(SIG_SWTRSENSOR1_BASELINE, &Touch_Sensor_Ref00); + InitMessage(SIG_SWTRSENSOR2_BASELINE, &Touch_Sensor_Ref01); + InitMessage(SIG_SWTRSENSOR3_BASELINE, &Touch_Sensor_Ref02); + InitMessage(SIG_SWTRSENSOR4_BASELINE, &Touch_Sensor_Ref03); + InitMessage(SIG_SWTRSENSOR5_BASELINE, &Touch_Sensor_Ref04); + InitMessage(SIG_SWTRSENSOR6_BASELINE, &Touch_Sensor_Ref05); + InitMessage(SIG_SWTRSENSOR7_BASELINE, &Touch_Sensor_Ref06); + InitMessage(SIG_SWTRSENSOR8_BASELINE, &Touch_Sensor_Ref07); + InitMessage(SIG_SWTRSENSOR9_BASELINE, &Touch_Sensor_Ref08); + InitMessage(SIG_SWTRSENSOR10_BASELINE, &Touch_Sensor_Ref09); + InitMessage(SIG_SWTRSENSOR11_BASELINE, &Touch_Sensor_Ref10); + InitMessage(SIG_SWTRSENSOR12_BASELINE, &Touch_Sensor_Ref11); + InitMessage(SIG_SWTRSENSOR13_BASELINE, &Touch_Sensor_Ref12); + InitMessage(SIG_SWTRSENSOR14_BASELINE, &Touch_Sensor_Ref13); + InitMessage(SIG_SWTRSENSOR15_BASELINE, &Touch_Sensor_Ref14); + + g16_DiagTouchPressSenRes[0][0] = Touch_Sensor_Ref00; + g16_DiagTouchPressSenRes[0][1] = Touch_Sensor_Ref01; + g16_DiagTouchPressSenRes[0][2] = Touch_Sensor_Ref02; + g16_DiagTouchPressSenRes[0][3] = Touch_Sensor_Ref03; + g16_DiagTouchPressSenRes[0][4] = Touch_Sensor_Ref04; + g16_DiagTouchPressSenRes[0][5] = Touch_Sensor_Ref05; + g16_DiagTouchPressSenRes[0][6] = Touch_Sensor_Ref06; + g16_DiagTouchPressSenRes[0][7] = Touch_Sensor_Ref07; + g16_DiagTouchPressSenRes[0][8] = Touch_Sensor_Ref08; + g16_DiagTouchPressSenRes[0][9] = Touch_Sensor_Ref09; + g16_DiagTouchPressSenRes[0][10] = Touch_Sensor_Ref10; + g16_DiagTouchPressSenRes[0][11] = Touch_Sensor_Ref11; + g16_DiagTouchPressSenRes[0][12] = Touch_Sensor_Ref12; + g16_DiagTouchPressSenRes[0][13] = Touch_Sensor_Ref13; + g16_DiagTouchPressSenRes[0][14] = Touch_Sensor_Ref14; + + g16_DiagTouchPressSenRes[1][0] = Touch_Sensor_Sts00; + g16_DiagTouchPressSenRes[1][1] = Touch_Sensor_Sts01; + g16_DiagTouchPressSenRes[1][2] = Touch_Sensor_Sts02; + g16_DiagTouchPressSenRes[1][3] = Touch_Sensor_Sts03; + g16_DiagTouchPressSenRes[1][4] = Touch_Sensor_Sts04; + g16_DiagTouchPressSenRes[1][5] = Touch_Sensor_Sts05; + g16_DiagTouchPressSenRes[1][6] = Touch_Sensor_Sts06; + g16_DiagTouchPressSenRes[1][7] = Touch_Sensor_Sts07; + g16_DiagTouchPressSenRes[1][8] = Touch_Sensor_Sts08; + g16_DiagTouchPressSenRes[1][9] = Touch_Sensor_Sts09; + g16_DiagTouchPressSenRes[1][10] = Touch_Sensor_Sts10; + g16_DiagTouchPressSenRes[1][11] = Touch_Sensor_Sts11; + g16_DiagTouchPressSenRes[1][12] = Touch_Sensor_Sts12; + g16_DiagTouchPressSenRes[1][13] = Touch_Sensor_Sts13; + g16_DiagTouchPressSenRes[1][14] = Touch_Sensor_Sts14; + + g16_DiagTouchPressSenRes[2][0] = Press_baseline; + g16_DiagTouchPressSenRes[2][1] = Press_signal; + g16_DiagTouchPressSenRes[2][2] = Press_preload; + + + uint16_t vol_test_sig=(uint16_t)k_vol_touch_Sts; + InitMessage(SIG_SWTRSENSOR16_SIGNAL, &vol_test_sig); + + +} + +#endif \ No newline at end of file diff --git a/firmware/src/RTE/RTE.h b/firmware/src/RTE/RTE.h new file mode 100644 index 0000000..43a945b --- /dev/null +++ b/firmware/src/RTE/RTE.h @@ -0,0 +1,187 @@ + + +#ifndef RTE_H +#define RTE_H + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "../P417_SWTR_App_ert_rtw/rtwtypes.h" +//For SWTL + +//#include "Global.h" + + +extern uint8_T Two_Finger_X_count; + +extern uint8_T X_count; + +extern uint8_T Two_Finger_Y_count; + + +extern uint8_T Y_count; + + +#if 1 +extern uint16_T Touch_Sensor_Sts00; +extern uint16_T Touch_Sensor_Sts01; +extern uint16_T Touch_Sensor_Sts02; +extern uint16_T Touch_Sensor_Sts03; +extern uint16_T Touch_Sensor_Sts04; +extern uint16_T Touch_Sensor_Sts05; +extern uint16_T Touch_Sensor_Sts06; +extern uint16_T Touch_Sensor_Sts07; +extern uint16_T Touch_Sensor_Sts08; +extern uint16_T Touch_Sensor_Sts09; +extern uint16_T Touch_Sensor_Sts10; +extern uint16_T Touch_Sensor_Sts11; +extern uint16_T Touch_Sensor_Sts12; +extern uint16_T Touch_Sensor_Sts13; +extern uint16_T Touch_Sensor_Sts14; +#endif + +//Input Sensor +//uint16_t RTE_Get_Power_AD_SNS(void);//to get power voltage +extern uint16_T Fr08_send_flag; +uint8_T RTE_Get_SldVolCtrlSts(void); + +//uint8_T RTE_Get_Pressure_Sensor_xxxx(void);//IIC DATA? +uint8_T RTE_Get_TouchBoard_CRC(void); + + +//button Not active,Touch,Touch and Press,invalid from sensor +uint8_T RTE_Get_TouchBoard_Up_Sts(void); +uint8_T RTE_Get_TouchBoard_Down_Sts(void); +uint8_T RTE_Get_TouchBoard_Left_Sts(void); +uint8_T RTE_Get_TouchBoard_Right_Sts(void); +uint8_T RTE_Get_TouchBoard_Center_Sts(void); +uint8_T RTE_Get_TouchBoard_VOICE1_Sts(void);//TJP1 +uint8_T RTE_Get_TouchBoard_VOICE2_Sts(void);//TJP2 +uint8_T RTE_Get_TouchBoard_MENU1_Sts(void);//Resume1 +uint8_T RTE_Get_TouchBoard_MENU2_Sts(void);//Resume2 +uint8_T RTE_Get_TouchBoard_VOL1_Sts(void);//Cancel1 +uint8_T RTE_Get_TouchBoard_VOL2_Sts(void);//Cancel2 + + +//touch borad left/right slide: 0:idle, 1:short slide left 2:short slide right 3:long slide left 4:long slide right +uint8_T RTE_Get_TouchBoard_Left_Right_Slide_Sts(void); + +//touch borad Up/Down slide: 0:idle, 1:short slide up 2:short slide down 3:long slide up 4:long slide down +uint8_T RTE_Get_TouchBoard_Up_Down_Slide_Sts(void); + +//uint8_T RTE_Get_INTB_PRSS_SNS(void); + + + +//uint8_T RTE_Get_X1_SNS(void); +//uint8_T RTE_Get_X2_SNS(void); +//uint8_T RTE_Get_X3_SNS(void); +//uint8_T RTE_Get_X4_SNS(void); +//uint8_T RTE_Get_X5_SNS(void); +uint8_T RTE_Get_X_SNS(void); + + +//uint8_T RTE_Get_Y1_SNS(void); +//uint8_T RTE_Get_Y2_SNS(void); +//uint8_T RTE_Get_Y3_SNS(void); +//uint8_T RTE_Get_Y4_SNS(void); +//uint8_T RTE_Get_Y5_SNS(void); +uint8_T RTE_Get_Y_SNS(void); + +uint8_T RTE_Get_TouchBoard_XY_Sts(void);//Not active,Touch,Touch and Press,invalid from sensor +uint8_T RTE_Get_TouchBoard_XY_Touch_And_Below_1N(void); + + +uint8_T RTE_Get_Pad_XY_trig(void); +uint8_T RTE_Get_Voice_XY_trig(void); +uint8_T RTE_Get_Menu_XY_trig(void); +uint8_T RTE_Get_Vol_XY_trig(void); + + +uint8_T RTE_Get_ACT_FAULT_OUT_SNS(void); +uint8_T RTE_Get_ACT_LD_OUT_SNS(void); + + +//Input CAN + +//LED on off control +uint8_T RTE_Get_CAN_ActvnOfSteerWhlIllmn(void); +//LED Day/Night Mode switch +uint8_T RTE_Get_CAN_TwliBriSts(void); + + +uint8_T RTE_Get_CAN_IntrBriSts(void); + +uint8_T RTE_Get_CAN_SteerWhlTouchBdLeFaildFb(void); + +uint8_T RTE_Get_CAN_SwtOfKeyTone(void); + +//Vibration control +uint8_T RTE_Get_CAN_VibrationFbToSwtp(void); + +uint8_T RTE_Get_CAN_IhuPrivateDHUCanFr01_Frame_Timeout(void);//0x030 frame + + +//Output Control + +void RTE_Set_illumination_BL_PWM(uint32_T Percent); + +//void RTE_Set_Power_AD_Ctrl(uint8_T Value);//to enable power AD diag + +//ACT control?? +void RTE_Set_ACT_Vibration(uint8_T Value); +//void RTE_Set_Gain0(uint8_T Value); +//void RTE_Set_Gain1(uint8_T Value); +//void RTE_Set_SDZ(uint8_T Value); +//void RTE_Set_INP(uint8_T Value); + +//Output CAN +void RTE_Set_CAN_RiMFctActSgCe(uint8_T Value); +void RTE_Set_CAN_RiMFctActSgDn(uint8_T Value); +void RTE_Set_CAN_RiMFctActSgLe(uint8_T Value); +void RTE_Set_CAN_RiMFctActSgRi(uint8_T Value); +void RTE_Set_CAN_RiMFctActSgUp(uint8_T Value); + +void RTE_Set_CAN_SteerWhlTouchBdVoice(uint8_T Value); + +void RTE_Set_CAN_SwpLeRiStsRi(uint8_T Value); + +void RTE_Set_CAN_SwpUpDwnStsRi(uint8_T Value); + +void RTE_Set_CAN_SldVolCtrlSts(uint8_T Value); + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRCmnFltSts(uint8_T Value); + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRTouchdFltSts(uint8_T Value); + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRVibrationFltSts(uint8_T Value); + +void RTE_Set_CAN_DiagcFailrTouchPanSWTRSnsrFltSts(uint8_T Value); + + + +void RTE_Set_CAN_SteerWhlTouchBdMenu(uint8_T Value); + + +void RTE_Set_CAN_SteerWhlTouchBdDn(uint8_T Value); + +void RTE_Set_CAN_SteerWhlTouchBdRiChks(uint8_T Value); + +void RTE_Set_CAN_SteerWhlTouchBdRiCntr(uint8_T Value); + +void RTE_Set_CAN_SteerWhlTouchBdRiSteerWhlTouchBdSts(uint8_T Value); + + +void RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnX(uint8_T Value); +void RTE_Set_CAN_SteerWhlTouchBdRiTouchPosnY(uint8_T Value); + +void RTE_Set_SEND_CAN_0x309_immediately(uint8_T Value); //called immediately when touch,or touch and press in XY area +void RTE_Set_SEND_CAN_0x307_25ms(uint8_T Value); // when touch,or touch and press in 3 button area,0x305 is sent every 25ms + + +void RTE_Set_SEND_CAN_0x307_1000ms(uint8_T Value); // when 3 button area is not active,0x305 is Sent every 1000ms + +void RTE_Set_All_UB(void); +void RTE_Set_All_Test_Value(void); + +#endif diff --git a/firmware/src/Speaker/SA51024.c b/firmware/src/Speaker/SA51024.c new file mode 100644 index 0000000..7ef2fa5 --- /dev/null +++ b/firmware/src/Speaker/SA51024.c @@ -0,0 +1,91 @@ +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + +#include +#include ".\SA51024.h" +#include "../config/mcal/peripheral/tc/plib_tc0.h" +#include "../config/mcal/peripheral/port/plib_port.h" + +extern STATE_UINT16 speaker_cycle_u16; + +void SA51024_MainTask(void); + + +void TC0_CallBack_Function (TC_TIMER_STATUS status, uintptr_t context) +{ + if ((DAC_IsReady(DAC_CHANNEL_0) == true)) + { + SA51024_MainTask(); + } +} + + +/* +sa51024 related var init +*/ +void SA51024_Init(void) +{ + uint16 index = 0; + + sa51024_state = SA51024_IDLE; + sa51024_strength= SA51024_STRENGTH_LEVEL0; + sa51024_wave_index = 0; + + for(index =0; index < NUM_ELEMENTS; index++) + { + sa51024_wave_tbl_u16_new[index] = (uint16)((Raw_data[index]/32.0) + 2048); + } + + TC0_TimerCallbackRegister(TC0_CallBack_Function, 0); + TC0_TimerStart(); +} + + +/*100us task*/ +void SA51024_MainTask(void) +{ + /*output sin wave*/ + if(SA51024_WORKING == SA51024_WAVE_STATE ) + { + SA51024_WAVE_INDEX++; + + if(SA51024_WAVE_INDEX>=SA51024_WAVE_MAX_NUM)//SA51024_WAVE_MAX_ID + { + SA51024_WAVE_INDEX = 0; + speaker_cycle_u16 = SA51024_WAVE_MAX_NUM; + SA51024_WAVE_STATE = SA51024_STOP; + } + + SA51024_TRIG_ADC(SA51024_WAVE_TABLE[SA51024_WAVE_INDEX]); + + } + else if(SA51024_STOP == SA51024_WAVE_STATE ) + {/*output 0V*/ + SA51024_WAVE_INDEX = 0; + SA51024_TRIG_ADC(2048); + SA51024_WAVE_STATE = SA51024_IDLE; + } + else{ + SA51024_TRIG_ADC(2048); + } +} + +/* +set sa51024 control state +para state woking->vibrate +para level ->vibrate strenght +*/ +void SA51024_Set_State(FA51024_main_e_typ state,FA51024_ctrl_e_typ level) +{ + if(SA51024_WORKING == state) + { + SA51024_WAVE_STATE = SA51024_WORKING; + } + else + { + SA51024_WAVE_STATE = SA51024_STOP; + } +} diff --git a/firmware/src/Speaker/SA51024.h b/firmware/src/Speaker/SA51024.h new file mode 100644 index 0000000..d417e74 --- /dev/null +++ b/firmware/src/Speaker/SA51024.h @@ -0,0 +1,35 @@ +#ifndef __SA51024_H__ +#define __SA51024_H__ +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ +#include "SA51024_Cfg.h" + +/***************************datatype define end************************************/ + + +#define SA51024_WAVE_INDEX SA51024_Cfg_Main_Str.wave_index[0] +#define SA51024_WAVE_STATE SA51024_Cfg_Main_Str.state[0] +#define SA51024_WAVE_STRENGHT SA51024_Cfg_Main_Str.state[0] +#define SA51024_WAVE_TABLE SA51024_Cfg_Main_Str.wave_tbl + + +/***************************enum define begin************************************/ + +/***************************enum define end************************************/ + + +/*****************************main control function begin**********************************/ +/*********************************main control function end*******************************/ + + +/***************************extern function begin************************************/ +extern void SA51024_Init(void); +extern void SA51024_MainTask(void); +extern void SA51024_Set_State(FA51024_main_e_typ state,FA51024_ctrl_e_typ level); +/***************************extern function end************************************/ + + +#endif diff --git a/firmware/src/Speaker/SA51024_Cfg.c b/firmware/src/Speaker/SA51024_Cfg.c new file mode 100644 index 0000000..7ff5563 --- /dev/null +++ b/firmware/src/Speaker/SA51024_Cfg.c @@ -0,0 +1,62 @@ +#include ".\SA51024_Cfg.h" +#include "Std_Types.h" +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + +FA51024_main_e_typ sa51024_state; +FA51024_ctrl_e_typ sa51024_strength; +STATE_UINT16 sa51024_wave_index; + + + + +STATE_UINT16 sa51024_wave_tbl_u16_new[NUM_ELEMENTS] = {0}; + +float32 Raw_data[NUM_ELEMENTS] = { + 0, 92, 367, 807, 1407, 2126, 2951, 3833, /* 0-7 */ +4745, 5637, 6472, 7210, 7800, 8221, 8417, 8384, /* 8-15 */ +8078, 7500, 6629, 5479, 4050, 2366, 453, -1654, /* 16-23 */ +-3912, -6270, -8673, -11065, -13375, -15550, -17518, -19221, /* 24-31 */ +-20600, -21602, -22184, -22303, -21938, -21061, -19680, -17784, /* 32-39 */ +-15410, -12573, -9324, -5715, -1810, 2314, 6434, 10422, /* 40-47 */ +14210, 17706, 20853, 23585, 25842, 27588, 28781, 29399, /* 48-55 */ +29434, 28879, 27746, 26065, 23857, 21180, 18075, 14611, /* 56-63 */ +10857, 6885, 2775, -1389, -5527, -9552, -13389, -16957, /* 64-71 */ +-20189, -23016, -25383, -27248, -28563, -29314, -29477, -29051, /* 72-79 */ +-28048, -26485, -24390, -21814, -18798, -15407, -11716, -7778, /* 80-87 */ +-3700, 466, 4578, 8541, 12275, 15702, 18771, 21413, /* 88-95 */ +23591, 25260, 26406, 26999, 27054, 26563, 25550, 24052, /* 96-103 */ +22090, 19728, 17011, 13998, 10765, 7367, 3884, 388, /* 104-111 */ +-3059, -6375, -9513, -12395, -14984, -17220, -19072, -20511, /* 112-119 */ +-21510, -22062, -22164, -21818, -21049, -19871, -18322, -16441, /* 120-127 */ +-14267, -11859, -9260, -6537, -3739, -930, 1836, 4505, /* 128-135 */ +7018, 9341, 11413, 13219, 14708, 15875, 16690, 17153, /* 136-143 */ +17261, 17022, 16445, 15559, 14377, 12945, 11290, 9450, /* 144-151 */ +7480, 5407, 3289, 1168, -923, -2919, -4810, -6535, /* 152-159 */ +-8081, -9413, -10513, -11363, -11959, -12289, -12361, -12185, /* 160-167 */ +-11758, -11122, -10271, -9254, -8081, -6793, -5419, -3986, /* 168-175 */ +-2540, -1092, 305, 1640, 2878, 3999, 4986, 5820, /* 176-183 */ +6492, 6995, 7328, 7483, 7482, 7315, 7008, 6572, /* 184-191 */ +6016, 5377, 4656, 3889, 3088, 2282, 1484, 720, /* 192-199 */ + -2, -655, -1237, -1734, -2138, -2449, -2661, -2780, /* 200-207 */ +-2807, -2759, -2623, -2445, -2194, -1930, -1624, -1326, /* 208-215 */ +-1024, -746, -500, -291, -137, -40, 0 +}; + + +const SA51024_Cfg_Main_Str_typ SA51024_Cfg_Main_Str = +{ + &sa51024_state, + &sa51024_strength, + &sa51024_wave_index, + (STATE_UINT16 *)&sa51024_wave_tbl_u16_new +}; +//sa51024_wave_tbl_u16_new + + +/***************************main function define end ************************************/ + + diff --git a/firmware/src/Speaker/SA51024_Cfg.h b/firmware/src/Speaker/SA51024_Cfg.h new file mode 100644 index 0000000..a848d73 --- /dev/null +++ b/firmware/src/Speaker/SA51024_Cfg.h @@ -0,0 +1,100 @@ +#ifndef __SA51024_CFG_H__ +#define __SA51024_CFG_H__ + +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + +#include "../config/mcal/peripheral/dac/plib_dac.h" +#include "../config/mcal/peripheral/port/plib_port.h" +#include "Std_Types.h" +/*************************************************************** +Macro Definition and enum define +***************************************************************/ + +#ifndef TRUE +#define TRUE true +#endif + +#ifndef FALSE +#define FALSE false +#endif + + +typedef enum +{ + SA51024_IDLE = 0x00, + SA51024_WORKING , + SA51024_STOP , +}FA51024_main_e_typ; + + +typedef enum +{ + SA51024_STRENGTH_LEVEL0 = 0x00, + SA51024_STRENGTH_LEVEL1 , + SA51024_STRENGTH_LEVEL2, + SA51024_STRENGTH_LEVEL3 +}FA51024_ctrl_e_typ; + + +/***************************datatype define begin************************************/ +#ifndef STATE_UINT8 +#define STATE_UINT8 unsigned char +#endif + +#ifndef STATE_SINT8 +#define STATE_SINT8 char +#endif + +#ifndef STATE_UINT16 +#define STATE_UINT16 unsigned short +#endif + +#ifndef STATE_SINT16 +#define STATE_SINT16 short +#endif + +#ifndef STATE_UINT32 +#define STATE_UINT32 unsigned int +#endif + +#ifndef STATE_SINT32 +#define STATE_SINT32 int +#endif + +#define NUM_ELEMENTS 223 +//#define SA51024_WAVE_MAX_ID ((STATE_SINT16)23760) +//#define SA51024_WAVE_MAX_NUM ((STATE_SINT16)23761) + + +#define SA51024_WAVE_MAX_ID ((STATE_SINT16)(NUM_ELEMENTS - 1)) +#define SA51024_WAVE_MAX_NUM ((STATE_SINT16)(NUM_ELEMENTS)) + +#define SA51024_TRIG_ADC(val) DAC_DataWrite(0,val) + +typedef struct +{ + FA51024_main_e_typ *state; + FA51024_ctrl_e_typ * strngth; + STATE_UINT16 *wave_index; + STATE_UINT16 * wave_tbl; +}SA51024_Cfg_Main_Str_typ; + +/*************************************************************** +extern variable +***************************************************************/ + + +extern FA51024_main_e_typ sa51024_state; +extern FA51024_ctrl_e_typ sa51024_strength; +extern STATE_UINT16 sa51024_wave_index; + +extern const SA51024_Cfg_Main_Str_typ SA51024_Cfg_Main_Str ; +extern float32 Raw_data[NUM_ELEMENTS]; +extern STATE_UINT16 sa51024_wave_tbl_u16_new[NUM_ELEMENTS]; + + +#endif diff --git a/firmware/src/Speaker/Speaker.c b/firmware/src/Speaker/Speaker.c new file mode 100644 index 0000000..547e179 --- /dev/null +++ b/firmware/src/Speaker/Speaker.c @@ -0,0 +1,287 @@ +#include +#include "Speaker.h" + +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ +speaker_queue_str speaker_queue; +Speaker_main_e_typ speaker_main_state_str; +STATE_UINT16 speaker_cycle_u16; +speaker_ctrl_Str speaker_ctrl_buf_str; +static uint8_t DAC_Initialize_status = 0; +static uint8_t DAC_Initialize_RetryCnt = 3; +/************************************ +Get Sw Fifo empty condition +************************************/ + +uint8_t speaker_queue_is_empty(void) +{ + uint8_t fl_temp_U8; + __disable_irq(); + if(speaker_queue.queue_in == speaker_queue.queue_out) + { + fl_temp_U8 = TRUE; + } + else + { + fl_temp_U8 = FALSE; + } + __enable_irq(); + return fl_temp_U8; +} + +/************************************ +Get Sw Fifo Full condition +************************************/ + +uint8_t speaker_queue_is_full(void) +{ + uint8_t fl_temp_U8; + __disable_irq(); + fl_temp_U8 = (speaker_queue.queue_in + 1) % (sizeof(speaker_queue.queue)/sizeof(speaker_queue.queue[0])); + if(fl_temp_U8 == speaker_queue.queue_out) + { + fl_temp_U8 = TRUE; + } + else + { + fl_temp_U8 = FALSE; + } + __enable_irq(); + return fl_temp_U8; +} + + +/************************************ +Push a element data to queue +************************************/ + +uint8_t speaker_queue_push_e(speaker_ctrl_Str fl_str_e) +{ + uint8_t fl_temp_U8; + + if(TRUE == speaker_queue_is_full()) + { + return FALSE; + } + else + { + + __disable_irq(); + fl_temp_U8 = (speaker_queue.queue_in + 1) % (sizeof(speaker_queue.queue)/sizeof(speaker_queue.queue[0])); + speaker_queue.queue_in = fl_temp_U8; + speaker_queue.queue[fl_temp_U8] = fl_str_e; + __enable_irq(); + return TRUE; + } +} + + +/************************************ +Get Data from Rx Sw Fifo +return: TRUE->OK FALSE->Fail +************************************/ + +uint8_t speaker_queue_pull_e(speaker_ctrl_Str *fl_str_e) +{ + uint8_t fl_temp_U8; + + if(TRUE == speaker_queue_is_empty()) + { + return FALSE; + } + else + { + __disable_irq(); + fl_temp_U8 = (speaker_queue.queue_out + 1) % (sizeof(speaker_queue.queue)/sizeof(speaker_queue.queue[0])); + speaker_queue.queue_out = fl_temp_U8; + fl_str_e[0] = speaker_queue.queue[fl_temp_U8]; + + __enable_irq(); + + return TRUE; + } +} + +/************************************ +uart init +************************************/ + +void speaker_Init(void) +{ + SA51024_Init(); + memset(&speaker_queue,0,sizeof(speaker_queue)); + speaker_main_state_str = SPEAKER_INIT; + DAC_Initialize_RetryCnt = 0x03; + DAC_Initialize_status = 0; +} + +/* +para level 0~~3,other value force set to 3 +return void +*/ +/*level ->0 ------ 1 ----------2 ---------3*/ +/*gain0/1->00 ------ 10----------01---------11*/ + +void speaker_set_strenght(FA51024_ctrl_e_typ level) +{ + + //PORT_PinWrite(PORT_PIN_PA13,1);/*SHUTDOWN = 1~{o< t~}urn on chip*/ + + if(level == SA51024_STRENGTH_LEVEL0) + { + PORT_PinWrite(PORT_PIN_PB14,0);/*GAIN1*/ + PORT_PinWrite(PORT_PIN_PB15,0);/*GAIN0*/ + } + else if(level == SA51024_STRENGTH_LEVEL1) + { + PORT_PinWrite(PORT_PIN_PB14,0);/*GAIN1*/ + PORT_PinWrite(PORT_PIN_PB15,1);/*GAIN0*/ + } + else if(level == SA51024_STRENGTH_LEVEL2) + { + PORT_PinWrite(PORT_PIN_PB14,1);/*GAIN1*/ + PORT_PinWrite(PORT_PIN_PB15,0);/*GAIN0*/ + } + else + { + PORT_PinWrite(PORT_PIN_PB14,1);/*GAIN1*/ + PORT_PinWrite(PORT_PIN_PB15,1);/*GAIN0*/ + } +} + +/* +speaker main control state task +*/ +void speaker_MainTask(void) +{ + speaker_ctrl_Str fl_str_e; + + + switch(speaker_main_state_str) + { + case SPEAKER_INIT: + //SA51024_Set_State(SA51024_STOP,speaker_ctrl_buf_str.strenght); + PORT_PinWrite(PORT_PIN_PA13,0);/*SHUTDOWN = 1~{o< t~}urn on chip*/ + PORT_PinWrite(PORT_PIN_PA25,0); + speaker_set_strenght(SA51024_STRENGTH_LEVEL0); + speaker_main_state_str = SPEAKER_INIT_CYCLE; + speaker_cycle_u16 = 0; + break; + case SPEAKER_INIT_CYCLE: + if(speaker_cycle_u16++ >= 10)//20ms + { + DAC_Initialize_status = 0x01; + } + + if(speaker_cycle_u16++ >= ((SPEAKER_INTERVAL_CYCLE_TIMES)/(SPEAKER_TASK_PERIOD))) + { + DAC_REGS->DAC_CTRLA &= ~DAC_CTRLA_ENABLE_Msk; + PORT_PinGPIOConfig(PORT_PIN_PA02); + speaker_main_state_str = SPEAKER_IDLE; + } + break; + case SPEAKER_IDLE: + //SA51024_TRIG_ADC(2047); + PORT_PinWrite(PORT_PIN_PA25,0); + if(TRUE == speaker_queue_pull_e(&fl_str_e)) + { + speaker_ctrl_buf_str = fl_str_e; + speaker_main_state_str = SPEAKER_SET_STRENGHT; + } + break; + + case SPEAKER_SET_STRENGHT: + { + speaker_set_strenght(speaker_ctrl_buf_str.strenght); + PORT_PinWrite(PORT_PIN_PA13,1); + speaker_main_state_str = SPEAKER_INTERVAL; + speaker_cycle_u16 = 0; + } + break; + + case SPEAKER_INTERVAL: + if(speaker_cycle_u16++ >= ((SPEAKER_INTERVAL_CYCLE_TIMES)/(SPEAKER_TASK_PERIOD))) + { + speaker_main_state_str = SPEAKER_START; + } + break; + + case SPEAKER_START: + { + PORT_PinPeripheralFunctionConfig(PORT_PIN_PA02,PERIPHERAL_FUNCTION_B); + PORT_PinWrite(PORT_PIN_PA25,0); + DAC_REGS->DAC_CTRLA |= DAC_CTRLA_ENABLE_Msk; + SA51024_Set_State(SA51024_WORKING,speaker_ctrl_buf_str.strenght); + speaker_cycle_u16 = 0; + speaker_main_state_str = SPEAKER_UPDATE_CYCLE; + } + break; + + case SPEAKER_UPDATE_CYCLE: + // if(speaker_cycle_u16++ >= speaker_ctrl_buf_str.cycle) + if(speaker_cycle_u16 >= SA51024_WAVE_MAX_NUM) + { + speaker_main_state_str = SPEAKER_STOP; + } + break; + + default: + case SPEAKER_STOP: + { + SA51024_Set_State(SA51024_STOP,SA51024_STRENGTH_LEVEL0); + speaker_set_strenght(SA51024_STRENGTH_LEVEL0); + PORT_PinWrite(PORT_PIN_PA25,0); + PORT_PinWrite(PORT_PIN_PA13,0);/*SHUTDOWN = 0，turn off chip*/ + speaker_main_state_str = SPEAKER_IDLE; + speaker_cycle_u16 = 0; + + /* Disable DAC */ + // DAC_REGS->DAC_CTRLA &= ~~DAC_CTRLA_ENABLE_Msk; + PORT_PinGPIOConfig(PORT_PIN_PA02); + } + break; + + + } + + +} + +/* +para1 cycle time unit ms +para2 level 0~~3,other value force set to 3 +return FALSE tigger fail,TRUE tigger sucess +*/ +STATE_UINT8 speeker_Tig_Once(uint16_t cycle_time,FA51024_ctrl_e_typ level) +{ + speaker_ctrl_Str fl_str_e; + STATE_UINT8 ret = FALSE; + + if(cycle_time <= (SPEAKER_MAX_CYCLE_TIMES)) + { + if(level <= SA51024_STRENGTH_LEVEL3) + { + fl_str_e.cycle = cycle_time/SPEAKER_TASK_PERIOD; + fl_str_e.strenght = level; + if(TRUE == speaker_queue_push_e(fl_str_e)) + { + ret = TRUE; + } + } + } + + return ret; +} + + +Speaker_main_e_typ Get_Speaker_Main_State(void) +{ + return speaker_main_state_str; +} + + + + diff --git a/firmware/src/Speaker/Speaker.h b/firmware/src/Speaker/Speaker.h new file mode 100644 index 0000000..092cafc --- /dev/null +++ b/firmware/src/Speaker/Speaker.h @@ -0,0 +1,58 @@ +#ifndef __TMP1780_H__ +#define __TMP1780_H__ +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ +#include ".\SA51024.h" + + +/***************************enum define begin************************************/ +typedef enum +{ + SPEAKER_IDLE = 0x00, + SPEAKER_INIT, + SPEAKER_INIT_CYCLE, + SPEAKER_SET_STRENGHT , + SPEAKER_START , + SPEAKER_UPDATE_CYCLE , + SPEAKER_STOP , + SPEAKER_INTERVAL , +}Speaker_main_e_typ; + + +typedef struct +{ + FA51024_ctrl_e_typ strenght; + STATE_UINT16 cycle; +} speaker_ctrl_Str; + +typedef struct +{ + speaker_ctrl_Str queue[2]; + STATE_UINT8 queue_in; + STATE_UINT8 queue_out; +}speaker_queue_str; + +/***************************enum define end************************************/ + +#define SPEAKER_TASK_PERIOD 2 +#define SPEAKER_MAX_CYCLE_TIMES ((STATE_UINT16)1000) /*unit:ms*/ +#define SPEAKER_INTERVAL_CYCLE_TIMES ((STATE_UINT16)20) /*unit:ms*///132 + +/*****************************main control function begin**********************************/ + +/*********************************main control function end*******************************/ + + +/***************************extern function begin************************************/ +extern void speaker_Init(void); +extern void speaker_MainTask(void); +extern STATE_UINT8 speeker_Tig_Once(uint16_t cycle_time,FA51024_ctrl_e_typ level); +extern Speaker_main_e_typ Get_Speaker_Main_State(void); + +/***************************extern function end************************************/ + + +#endif diff --git a/firmware/src/Std_Types.h b/firmware/src/Std_Types.h new file mode 100644 index 0000000..d6f104f --- /dev/null +++ b/firmware/src/Std_Types.h @@ -0,0 +1,85 @@ +#ifndef STD_TYPES_H +#define STD_TYPES_H + +typedef unsigned char BOOL; +typedef unsigned char UI_8; +typedef unsigned short UI_16; +typedef unsigned long UI_32; +typedef signed char SI_8; +typedef unsigned char t_error; +typedef UI_8 t_com_buf_hdl; +typedef UI_32 t_timer_time; +typedef unsigned char boolean; /* TRUE .. FALSE */ + +typedef signed char sint8; /* -128 .. +127 */ +typedef unsigned char uint8; /* 0 .. 255 */ +typedef signed short sint16; /* -32768 .. +32767 */ +typedef unsigned short uint16; /* 0 .. 65535 */ +typedef signed long sint32; /* -2147483648 .. +2147483647 */ +typedef unsigned long uint32; /* 0 .. 4294967295 */ + +typedef signed int sint8_least; /* At least 7 bit + 1 bit sign */ +typedef unsigned int uint8_least; /* At least 8 bit */ +typedef signed int sint16_least; /* At least 15 bit + 1 bit sign */ +typedef unsigned int uint16_least; /* At least 16 bit */ +typedef signed int sint32_least; /* At least 31 bit + 1 bit sign */ +typedef unsigned int uint32_least; /* At least 32 bit */ + +typedef float float32; +typedef double float64; + +#ifndef TRUE + #define TRUE 1u +#endif + +#ifndef FALSE + #define FALSE 0u +#endif + + +#ifndef NULL_PTR + #define NULL_PTR ((void *)0) +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#define STD_HIGH 1u /* Physical state 5V or 3.3V */ +#define STD_LOW 0u /* Physical state 0V */ + +#define STD_ACTIVE 1u /* Logical state active */ +#define STD_IDLE 0u /* Logical state idle */ + +#define STD_ON 1u +#define STD_OFF 0u + +#ifndef E_OK +#define E_OK 0u +#endif + +#ifndef E_NOT_OK +#define E_NOT_OK 1u +#endif + + +typedef uint8 Std_ReturnType; + +typedef unsigned char t_error; +#define ERROR_OK ((t_error)0) +#define ERROR_GENERIC ((t_error)0xFF) +#define ERROR_FUNC_NOT_IMPLEMENTED ((t_error)0xFE) + + +#define E_NO_DTC_AVAILABLE (Std_ReturnType)2u +#define E_SESSION_NOT_ALLOWED (Std_ReturnType)4u +#define E_PROTOCOL_NOT_ALLOWED (Std_ReturnType)5u +#define E_REQUEST_NOT_ACCEPTED (Std_ReturnType)8u +#define E_REQUEST_ENV_NOK (Std_ReturnType)9u +#define E_PENDING (Std_ReturnType)10u +#define E_COMPARE_KEY_FAILED (Std_ReturnType)11u +#define E_FORCE_RCRRP (Std_ReturnType)12u + + + +#endif diff --git a/firmware/src/TLE9263/SBC_TLE926x.h b/firmware/src/TLE9263/SBC_TLE926x.h new file mode 100644 index 0000000..41b273f --- /dev/null +++ b/firmware/src/TLE9263/SBC_TLE926x.h @@ -0,0 +1,125 @@ +/** + * @cond + *********************************************************************************************************************** + * + * Copyright (c) 2018, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **********************************************************************************************************************/ +#ifndef SBC_TLE926X_H +#define SBC_TLE926X_H + +/* XML Version 0.0.1 */ +#define SBC_XML_VERSION (00001) + +#define CW_BUS_CTRL_1 (0x3) /*decimal 3*/ + +#define CW_BUS_CTRL_2 (0x0) /*decimal 0*/ + +#define CW_GPIO_CTRL (0x0) /*decimal 0*/ + +#define CW_HS_CTRL1 (0x0) /*decimal 0*/ + +#define CW_HS_CTRL2 (0x0) /*decimal 0*/ + +#define CW_HW_CTRL (0x80) /*decimal 128*/ + +#define CW_M_S_CTRL (0x18) /*decimal 8*/ + +#define CW_PWM1_CTRL (0x0) /*decimal 0*/ + +#define CW_PWM2_CTRL (0x0) /*decimal 0*/ + +#define CW_PWM_FREQ_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_BTL1_CTRL (0x50) /*decimal 80*/ + +#define CW_SWK_BTL2_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_CDR_CTRL2 (0x1) /*decimal 1*/ + +#define CW_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/ + +#define CW_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/ + +#define CW_SWK_DATA_H_CTRL 0x00000000 + +#define CW_SWK_DATA_L_CTRL 0x00000000 + +#define CW_SWK_DLC_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_ID0_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_ID1_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_ID2_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_ID3_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_MASK_ID0_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_MASK_ID1_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_MASK_ID2_CTRL (0x0) /*decimal 0*/ + +#define CW_SWK_MASK_ID3_CTRL (0x0) /*decimal 0*/ + +#define CW_SW_SD_CTRL (0x0) /*decimal 0*/ + +#define CW_TIMER1_CTRL (0x0) /*decimal 0*/ + +#define CW_TIMER2_CTRL (0x0) /*decimal 0*/ + +#define CW_WD_CTRL (0x4) /*decimal 4*/ + +#define CW_WK_CTRL_1 (0x0) /*decimal 0*/ + +#define CW_WK_CTRL_2 (0x7) /*decimal 7*/ + +#define CW_WK_FLT_CTRL (0x0) /*decimal 0*/ + +#define CW_WK_PUPD_CTRL (0x3F) /*decimal 63*/ + +#define LED_EXTENDED_ID (0x1) /*decimal 1*/ + +#define LED_EXTENDED_ID_MASK (0x1) /*decimal 1*/ + +#define MATH_BAUDRADE (0x2) /*decimal 2*/ + +#define MATH_DOUBLE_CDR_FREQ (0x0) /*decimal 0*/ + +#define MATH_EN_PN (0x0) /*decimal 0*/ + +#define UI_PWM1_DC (0.0) + +#define UI_PWM2_DC (0.0) + +#define UI_SWK_IDx_CTRL 0x00000000 + +#define UI_SWK_MASK_IDx_CTRL 0x00000000 + +#define UI_VARIANT (0x3) /*decimal 3*/ + +#endif /* SBC_TLE926X_H */ diff --git a/firmware/src/TLE9263/TLE926x.c b/firmware/src/TLE9263/TLE926x.c new file mode 100644 index 0000000..dd90605 --- /dev/null +++ b/firmware/src/TLE9263/TLE926x.c @@ -0,0 +1,983 @@ +/********************************************************************************************************************* + * Copyright (c) 2021, Infineon Technologies AG + * + * + * Distributed under the Boost Software License, Version 1.0. + * + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + *********************************************************************************************************************/ + + +/******************************************************************************************************** + * @file TLE926x.c + * + * @brief Implementation of main library functions + * + * @version V1.0.0 + * @date + * @author Fedy Farhat + * @author Michael Schaffarczyk + ********************************************************************************************************/ + + +/* ================================================================================ */ +/* ============================ HEADER FILES ================================ */ +/* ================================================================================ */ + +#include "TLE926x.h" +#include "SBC_TLE926x.h" +#include +#include "plib_port.h" + + +/* ================================================================================ */ +/* ============================== Variables ================================= */ +/* ================================================================================ */ +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +static uint8_t wd_config; +/* -------------------------------- ISR Handling --------------------------------- */ + + +static SBC_Func_Callback SBC_ISR_Callbacks[60]; +static uint32_t SBC_ISR_Vectors[60]; +static uint8_t SBC_ISR_ReadOutRegs[60]; +static uint8_t SBC_ISR_ReadOutVals[60]; +static uint8_t SBC_RegisteredCallbacks = 0; +static uint8_t SBC_RegisteredRedoutRegs = 0; +uint16_t SBC_Mode=0; +uint16_t SBC_Mode_VCC1=0; +uint16_t SBC_Mode_VCC2=0; + +/* ================================================================================ */ +/* =========================== Library Functions ============================ */ +/* ================================================================================ */ + + +/* -------------------------------- Main Functions ------------------------------- */ + +// trigger the Watchdog +SBC_ErrorCode sbc_wd_trigger(void) { + SBC_ErrorCode errCode; +// if (wd_config == (sbc_read_reg(SBC_WD_CTRL)&0xFF)) { +// return sbc_write_reg(SBC_WD_CTRL, wd_config, NULL); +// } + sbc_write_reg(SBC_WD_CTRL, wd_config, NULL); + +// SBC_Mode_VCC2 = sbc_read_reg(SBC_SUP_STAT_1); +// SBC_Mode_VCC1 = sbc_read_reg(SBC_SUP_STAT_2); +// sbc_write_reg(SBC_M_S_CTRL,0x8,0); +// errCode.SBC_Register = SBC_WD_CTRL; +// errCode.flippedBitsMask = ((uint8_t)sbc_read_reg(SBC_WD_CTRL)) ^ wd_config; +// errCode.expectedValue = wd_config; + errCode.SBC_Register = 0; + errCode.flippedBitsMask = 0; + errCode.expectedValue = 0; + return errCode; +} +void sbc_trig_reset(void) +{ + /*soft reset*/ + //sbc_write_reg_field (SBC_M_S_CTRL, MODE_MASK, SBC_RESET, 0x00); // M_S_CTRL(0x81) + sbc_init(); +} + +// Read the addressed register +uint16_t sbc_read_reg(sbc_register_t sbc_register) { + /* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */ + return SBC_SPI_TRANSFER16(SBC_READ_MASK & sbc_register, 0x00); +} + +// Read register bit +uint8_t sbc_read_reg_field(sbc_register_t sbc_register, sbc_bit_mask_t bit_mask) { + uint8_t data = ((uint8_t)sbc_read_reg(sbc_register)) & 0xFFU; + return (data & bit_mask) >> SBC_BITPOSITION(bit_mask); +} + + +// Write value to a register +SBC_ErrorCode sbc_write_reg(sbc_register_t sbc_register, uint8_t SBC_Val, uint16_t * returnval) { + SBC_ErrorCode errCode; + uint16_t returndata = SBC_SPI_TRANSFER16(SBC_WRITE_BIT | sbc_register, SBC_Val); + if(returnval != NULL) { + *returnval = returndata; + } + +// errCode.SBC_Register = sbc_register; +// errCode.flippedBitsMask = ((uint8_t)sbc_read_reg(sbc_register)) ^ SBC_Val; +// errCode.expectedValue = SBC_Val; + errCode.SBC_Register = 0; + errCode.flippedBitsMask = 0; + errCode.expectedValue = 0; + + return errCode; +} + +/*Write bit value in register*/ +SBC_ErrorCode sbc_write_reg_field(sbc_register_t sbc_register, sbc_bit_mask_t bit_mask, uint8_t val, uint16_t * returnval) { + SBC_ErrorCode errCode; + + /* Read data out of register to be manipulated */ + uint16_t returndata = sbc_read_reg(sbc_register); + if(returnval != NULL) { + *returnval = returndata; + } + /* pick the first 8 bit of read SBC_Reg, meant register data [7:0]*/ + uint8_t data = (uint8_t)returndata; + + /* Set the used bit field to all 0 */ + data &= ~(bit_mask); + + /* Configure new data to bit field */ + data |= (val << SBC_BITPOSITION(bit_mask)); + + (void)SBC_SPI_TRANSFER16(SBC_WRITE_BIT | sbc_register, data); + + errCode.SBC_Register = sbc_register; + errCode.expectedValue = (val << SBC_BITPOSITION(bit_mask)); + uint8_t actualValue = ((uint8_t)sbc_read_reg(sbc_register)) & bit_mask; + errCode.flippedBitsMask = errCode.expectedValue ^ actualValue; + + return errCode; +} + +void delay(uint32_t val) +{ + uint32_t temp = 0xFFFF; + + while(val--) + { + while(temp--); + temp = 0xFFFF; + } +} + +void CyclicTskSchM_TimerSync (void); + +/* initialize SBC */ +SBC_ErrorCode sbc_init(void) { + SBC_ErrorCode errCode; + uint8_t i; + uint8_t delay_cnt; + uint8_t WD_CTRL = CW_WD_CTRL; + uint8_t checksum = WD_CTRL; + uint16_t readback; + + checksum = checksum ^ checksum >> 4; + checksum = checksum ^ checksum >> 2; + checksum = checksum ^ checksum >> 1; + + + if((checksum & 1) > 0) { + /* Set parity bit */ + WD_CTRL = WD_CTRL | 0x80U; // + } + wd_config = WD_CTRL; + + /* Describes initialization sequence. + init Sequence containing {reg_address, reg_value}*/ + uint8_t initSequence[4][2] = { + {SBC_WD_CTRL, WD_CTRL},//0x04 TimeOut; 200ms period + {SBC_M_S_CTRL, CW_M_S_CTRL},//0x18 SBC normal;vcc3off;vcc2 on in normal; + {SBC_BUS_CTRL_1, CW_BUS_CTRL_1},//0x03 lin off; can normal + + /* End Configuration */ + {0x00U, 0x00U} + }; + + + delay_cnt = 10; + do{ + CyclicTskSchM_TimerSync(); + }while(delay_cnt--); + + + + /* Write all initialization items to Lite SBC + write the above defined reg_values inside the real registers on Lite SBC*/ + i =0; + while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) { + while((readback&0xff) != initSequence[i][1]) + { + errCode = sbc_write_reg((sbc_register_t) initSequence[i][0],(sbc_register_t) initSequence[i][1], &readback); + } + + i++; + } + + errCode.SBC_Register = 0x00; + errCode.flippedBitsMask = 0x00; + errCode.expectedValue = 0x00; + return errCode; +} +#if 0 +/* initialize SBC */ +SBC_ErrorCode sbc_init(void) { + SBC_ErrorCode errCode; + + uint16_t famprod; + uint8_t sbc_family; + //uint8_t sbc_product; + uint8_t i; + uint8_t cond; + uint8_t delay_cnt; + + uint8_t sbc_reset_init; + uint8_t sbc_init; + uint8_t sbc_init_cnt; + + uint8_t WD_CTRL = CW_WD_CTRL; + //uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL; + //uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL; + uint8_t SWK_CAN_FD_CTRL = CW_SWK_CAN_FD_CTRL; + + uint8_t checksum = WD_CTRL; + + + checksum = checksum ^ checksum >> 4; + checksum = checksum ^ checksum >> 2; + checksum = checksum ^ checksum >> 1; + + + if((checksum & 1) > 0) { + /* Set parity bit */ + WD_CTRL = WD_CTRL | 0x80U; // + } + wd_config = WD_CTRL; + + /* Check if ID is configured to be extended */ + if((CW_SWK_ID0_CTRL & IDE_MASK ) == SBC_IDE_EXTENDED) { + + } else { + + } + + + /* DIS_ERR_CNT is set only when FD Tolerance is set. + Set DIS_ERR_CNT value to 1 if the value of CAN_FD_EN is 1 */ + + if((CW_SWK_CAN_FD_CTRL & CAN_FD_EN_MASK) == SBC_CAN_FD_EN_ENABLED) { + SWK_CAN_FD_CTRL |= SBC_DIS_ERR_CNT_DISABLED << SBC_BITPOSITION(DIS_ERR_CNT_MASK); + } + + /* Describes initialization sequence. + init Sequence containing {reg_address, reg_value}*/ + uint8_t initSequence[45][2] = { + {SBC_WD_CTRL, WD_CTRL}, + {SBC_M_S_CTRL, CW_M_S_CTRL}, + {SBC_BUS_CTRL_1, CW_BUS_CTRL_1}, + {SBC_WK_CTRL_1, CW_WK_CTRL_1}, + {0x00U, 0x00U}, + {SBC_HW_CTRL, CW_HW_CTRL}, + {SBC_BUS_CTRL_2, CW_BUS_CTRL_2}, + {SBC_WK_CTRL_2, CW_WK_CTRL_2}, + {SBC_WK_PUPD_CTRL, CW_WK_PUPD_CTRL}, + {SBC_WK_FLT_CTRL, CW_WK_FLT_CTRL}, + {SBC_TIMER1_CTRL, CW_TIMER1_CTRL}, + {SBC_TIMER2_CTRL, CW_TIMER2_CTRL}, + {SBC_SW_SD_CTRL, CW_SW_SD_CTRL}, + {SBC_HS_CTRL_1, CW_HS_CTRL1}, + {SBC_HS_CTRL_2, CW_HS_CTRL2}, + {SBC_PWM1_CTRL, CW_PWM1_CTRL}, + {SBC_PWM2_CTRL, CW_PWM2_CTRL}, + {SBC_PWM_FREQ_CTRL, CW_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */ + {SBC_GPIO_CTRL, CW_GPIO_CTRL}, + + /* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */ + + /* Configuring CDR */ // CDR = Clock and Data Recovery + {SBC_SWK_CDR_CTRL2, CW_SWK_CDR_CTRL2}, + {SBC_SWK_BTL1_CTRL, CW_SWK_BTL1_CTRL}, + {SBC_SWK_BTL2_CTRL, CW_SWK_BTL2_CTRL}, + {SBC_SWK_CDR_LIMIT_HIGH, CW_SWK_CDR_LIMIT_HIGH_CTRL}, + {SBC_SWK_CDR_LIMIT_LOW, CW_SWK_CDR_LIMIT_LOW_CTRL}, + {SBC_SWK_CDR_CTRL1, ((SBC_SEL_FILT_TC16 << SBC_BITPOSITION(SELFILT_MASK)) | (SBC_CDR_EN_ENABLED << SBC_BITPOSITION(CDR_EN_MASK)))}, + + + + /* Set ID */ + {SBC_SWK_ID3_CTRL, CW_SWK_ID3_CTRL}, + {SBC_SWK_ID2_CTRL, CW_SWK_ID2_CTRL}, + {SBC_SWK_ID1_CTRL, CW_SWK_ID1_CTRL}, + {SBC_SWK_ID0_CTRL, CW_SWK_ID0_CTRL}, + + /* Set Mask */ + {SBC_SWK_MASK_ID3_CTRL, CW_SWK_MASK_ID3_CTRL}, + {SBC_SWK_MASK_ID2_CTRL, CW_SWK_MASK_ID2_CTRL}, + {SBC_SWK_MASK_ID1_CTRL, CW_SWK_MASK_ID1_CTRL}, + {SBC_SWK_MASK_ID0_CTRL, CW_SWK_MASK_ID0_CTRL}, + + /* Set Data */ + + {SBC_SWK_DATA7_CTRL, (uint8_t)(CW_SWK_DATA_H_CTRL >> 24)}, + {SBC_SWK_DATA6_CTRL, (uint8_t)(CW_SWK_DATA_H_CTRL >> 16)}, + {SBC_SWK_DATA5_CTRL, (uint8_t)(CW_SWK_DATA_H_CTRL >> 8)}, + {SBC_SWK_DATA4_CTRL, (uint8_t)(CW_SWK_DATA_H_CTRL >> 0)}, + {SBC_SWK_DATA3_CTRL, (uint8_t)(CW_SWK_DATA_L_CTRL >> 24)}, + {SBC_SWK_DATA2_CTRL, (uint8_t)(CW_SWK_DATA_L_CTRL >> 16)}, + {SBC_SWK_DATA1_CTRL, (uint8_t)(CW_SWK_DATA_L_CTRL >> 8)}, + {SBC_SWK_DATA0_CTRL, (uint8_t)(CW_SWK_DATA_L_CTRL >> 0)}, + + + + /* Set DLC */ + {SBC_SWK_DLC_CTRL, CW_SWK_DLC_CTRL}, + + {SBC_SWK_CAN_FD_CTRL, CW_SWK_CAN_FD_CTRL}, + {SBC_BUS_CTRL_1, CW_BUS_CTRL_1}, + /* End Configuration */ + {0x00U, 0x00U} + }; + + /* Call SPI Init */ + if(sbc_spi_init() != 0) { + errCode.SBC_Register = 0x00; + errCode.flippedBitsMask = 0x01; + errCode.expectedValue = 0x00; + return errCode; + }; + + +/* Check if SBC is Mid-Range SBC */ + famprod = sbc_read_reg(SBC_FAM_PROD_STAT); + sbc_family = (famprod & FAM_MASK) >> 8; + cond = (sbc_family == MID_RANGE_SBC_FAMILY) || (sbc_family == MID_RANGE_PLUS_SBC_FAMILY); + if (!cond) { + + } + PORT_PinWrite(PORT_PIN_PA15, 1); + + while(1) + { + sbc_reset_init = TRUE; + /*soft reset*/ + sbc_write_reg_field (SBC_M_S_CTRL, MODE_MASK, SBC_RESET, 0x00); // M_S_CTRL(0x81) + delay_cnt = 10; + do{ + CyclicTskSchM_TimerSync(); + }while(delay_cnt--); + + /* reset index */ + i =0; + sbc_init_cnt = 0; + /* Write all initialization items to Lite SBC + write the above defined reg_values inside the real registers on Lite SBC*/ + while(1) + { + sbc_init = TRUE; + while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) { + errCode = sbc_write_reg((sbc_register_t) initSequence[i][0],(sbc_register_t) initSequence[i][1], NULL); + if(errCode.flippedBitsMask > 0) { + //return errCode; + sbc_init = FALSE; + break; + } + i++; + } + if(sbc_init == TRUE) + { + break; + } + else + { + sbc_init_cnt ++; + if(sbc_init_cnt >= 10) + { + sbc_reset_init = FALSE; + break; + } + } + } + if(sbc_reset_init == TRUE)/*init ok*/ + { + break; + } + } + PORT_PinWrite(PORT_PIN_PA15, 0); + errCode.SBC_Register = 0x00; + errCode.flippedBitsMask = 0x00; + errCode.expectedValue = 0x00; + return errCode; +} +#endif + + + + +/* -------------------------------- ISR Functions -------------------------------- */ + +/* Callback function*/ +void sbc_register_callback(uint32_t vector_isr, void (*Callback_Handler)(uint8_t callbackHandler)) { + + /* Save callback */ + SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler; + + /* Save callback vector */ + + SBC_ISR_Vectors[SBC_RegisteredCallbacks] = vector_isr; + + /* Check if the register will be readout already to avoid double-readout later */ + uint8_t RegFound = 0; + for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { + if (SBC_ISR_ReadOutRegs[i] == ( vector_isr >> 24)) { + + + RegFound = 1; + } + } + + /* If readout status-reg was not found, register in the readout list */ + if (RegFound == 0) { + SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)( vector_isr>> 24); + SBC_RegisteredRedoutRegs++; + } + + SBC_RegisteredCallbacks++; +} + + +SBC_ErrorCode SBC_ISR(void) { + SBC_ErrorCode errCode; + + /* Readout all registered status-registers */ + for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { + SBC_ISR_ReadOutVals[i] = (uint8_t) sbc_read_reg( (sbc_register_t) SBC_ISR_ReadOutRegs[i]); + } + + /* Handle all interrupts */ + + for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) { + /* Decode ISR Vector */ + uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i]; + uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8); + uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16); + uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24); + + /* Readback of associated status-bit */ + uint8_t ReadBack = 0; + for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) { + if (SBC_ISR_ReadOutRegs[j] == RegAddr) { + ReadBack = SBC_ISR_ReadOutVals[j]; + break; + } + } + + /* If compare-values matched -> proceed callback and clear field */ + if (((ReadBack & FieldMsk) >> FieldPos) == Compare) { + SBC_ISR_Callbacks[i](ReadBack); + } + } + + /* Clear all ISR related registers */ + for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { + errCode = sbc_write_reg( (sbc_register_t) SBC_ISR_ReadOutRegs[i], 0x00U, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + } + + errCode.SBC_Register = 0x00U; + errCode.flippedBitsMask = 0x00U; + errCode.expectedValue = 0x00U; + return errCode; +} + + + +/* -------------------------------- API Calls ----------------------------------- */ +/* enter Normal Mode*/ +SBC_ErrorCode sbc_mode_normal(void) { + return sbc_write_reg_field(SBC_M_S_CTRL, MODE_MASK, SBC_NORMAL_MODE, NULL); +} + +/* enter Stop Mode*/ +SBC_ErrorCode sbc_mode_stop (void) { + return sbc_write_reg_field(SBC_M_S_CTRL, MODE_MASK, SBC_STOP_MODE, NULL); +} + +/* enter Sleep Mode*/ +SBC_ErrorCode sbc_mode_sleep(void) { + uint8_t registerReadOut; + + SBC_ErrorCode errCode; + + + +/* Check SBC in Normal Mode */ + uint8_t readData = sbc_read_reg(SBC_M_S_CTRL); + readData >>= SBC_BITPOSITION(MODE_MASK); + + if (readData != SBC_NORMAL_MODE) { + errCode = sbc_mode_normal(); + return errCode; + } + + /* If CAN PN is configured */ + if(MATH_EN_PN != 0) { + + /* Reading value of SWK_STAT. */ + registerReadOut = (uint8_t)sbc_read_reg(SBC_SWK_STAT); + + /* The selective wake routine should be aborted if sync is not set. + Note: for SYNC to be set the transceiver must have been in Normal Mode and */ + if((registerReadOut & SYNC_MASK ) >> SBC_BITPOSITION(SYNC_MASK) != SYNC_VALID_FRAME_RECEIVED) { + errCode.SBC_Register = SBC_SWK_STAT; + errCode.flippedBitsMask = SYNC_MASK; + errCode.expectedValue = SYNC_VALID_FRAME_RECEIVED << SBC_BITPOSITION(SYNC_MASK); + return errCode; + } + + + /* Set SWK Configuration valid */ + // set CFG_VAL = 1 + + errCode = sbc_write_reg_field(SBC_SWK_CTRL, CFG_VAL_MASK, SBC_CFG_VAL_VALID, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + + /* Clear SYSERR bit */ + + errCode = sbc_write_reg_field(SBC_BUS_STAT_1, SYSERR_MASK, 0x00, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + /* Set CAN Mode to off and once again to desired configuration */ + // CAN OFF + errCode = sbc_write_reg_field(SBC_BUS_CTRL_1, CAN_MASK, CAN_OFF, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + // CAN ON (with SWK) + errCode = sbc_write_reg_field(SBC_BUS_CTRL_1, CAN_MASK, CAN_WAKECAPABLE_SWK, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + /* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */ + registerReadOut = (uint8_t)sbc_read_reg(SBC_SWK_STAT); + if( ((SYNC_MASK & registerReadOut) == SYNC_MASK) + && ((SWK_SET_MASK & registerReadOut) == SWK_SET_MASK) + && ((WUP_MASK & registerReadOut) != WUP_MASK) + && ((WUF_MASK & registerReadOut) != WUF_MASK)) { + /* Empty */ + + } else { + errCode.SBC_Register = SBC_SWK_STAT; + errCode.expectedValue = 0b01000100U; + errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut; + return errCode; + } + + + + } + + + + /* Clear Wake Status Registers, so that SBC can sleep. */ + errCode = sbc_write_reg(SBC_WK_STAT_1, 0x00, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg(SBC_WK_STAT_2, 0x00, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + /* Select sleep mode */ + sbc_write_reg_field(SBC_M_S_CTRL, MODE_MASK, SBC_SLEEP_MODE, NULL); + + errCode.SBC_Register = 0x00U; + errCode.flippedBitsMask = 0x00U; + errCode.expectedValue = 0x00U; + return errCode; +} + +/* configure HSx */ +SBC_ErrorCode sbc_hsx_config(sbc_hsx_t hsX, sbc_hs_config_t hsConfig) { + SBC_ErrorCode errCode = {0,0,0}; + + switch (hsX) { + case HS1: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS1_MASK, hsConfig, NULL); + break; + case HS2: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS2_MASK, hsConfig, NULL); + break; + case HS3: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS3_MASK, hsConfig, NULL); + break; + case HS4: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS4_MASK, hsConfig, NULL); + break; + + default: + return errCode; + } + return errCode; +} + + + +/* CAN MODE*/ +SBC_ErrorCode sbc_can_mode(sbc_can_t CANmode ) +{ + SBC_ErrorCode errCode; + errCode = sbc_write_reg_field(SBC_BUS_CTRL_1, CAN_MASK, CANmode, NULL); + +return errCode; +} + + +/* LIN MODE */ +SBC_ErrorCode sbc_lin_mode(sbc_lin_module_t linModule, sbc_lin_mode_t linMode) { + SBC_ErrorCode errCode = {0,0,0}; + uint8_t mr_sbc_variant = sbc_read_reg(SBC_FAM_PROD_STAT) & PROD_MASK; + /* check if it is a variant with minimum 1 LIN interface*/ + if (mr_sbc_variant & 0b1000) { + if (linModule == LIN1) { + errCode = sbc_write_reg_field(SBC_BUS_CTRL_1, LIN1_MASK, linMode, NULL); + } else { + /* cheack if it is a variant with 2 LIN interfaces*/ + if (mr_sbc_variant & 0b1100) { + errCode = sbc_write_reg_field(SBC_BUS_CTRL_2, LIN2_MASK, linMode, NULL); + } else { + + return errCode; // default value 0 + } + } + } else { + + return errCode; // default value 0 + } + return errCode; +} +/* WRITE IN System status register*/ +SBC_ErrorCode sbc_sys_stat_write(uint8_t status) { + return sbc_write_reg(SBC_SYS_STAT_CTRL, status, NULL); +} + +/* Read register system status*/ +uint8_t sbc_sys_stat_read(void) { + return sbc_read_reg(SBC_SYS_STAT_CTRL); +} +// disabling WD and entering stop mode +SBC_ErrorCode sbc_mode_stop_without_watchdog(void) { + SBC_ErrorCode errCode = sbc_write_reg_field(SBC_WK_CTRL_1, WD_STM_EN_1_MASK, WATCHDOG_DEACTIVED_IN_STOP_MODE, NULL); + + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WD_CTRL, WD_STM_EN_0_MASK, WATCHDOG_DEACTIVED_IN_STOP_MODE, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + return sbc_mode_stop(); +} + + +/* configure cyclic sense function*/ +SBC_ErrorCode sbc_cyclicsense(sbc_timer_t timer, sbc_timer_per_t timerPeriod, sbc_timer_on_t timerOnTime, sbc_hsx_t hsX, sbc_wk_t wk, sbc_wk_pupd_t pupdConfig) { + SBC_ErrorCode errCode={0,0,0}; + + if (timer == TIMER1) { + errCode = sbc_write_reg_field(SBC_TIMER1_CTRL, TIMER1_ON_MASK, TIMER_ONTIME_OFF_LOW, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + switch (hsX) + { + case HS1: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS1_MASK, CONTROLLED_BY_TIMER1, NULL); + break; + case HS2: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS2_MASK, CONTROLLED_BY_TIMER1, NULL); + break; + case HS3: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS3_MASK, CONTROLLED_BY_TIMER1, NULL); + break; + case HS4: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS4_MASK, CONTROLLED_BY_TIMER1, NULL); + break; + default: + return errCode; + } + + if(errCode.flippedBitsMask > 0){ + return errCode; + } + switch (wk) { + case WK1: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK1_FLT_MASK, FILTER_ONTIME_END_TIMER1, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK1_PUPD_MASK, pupdConfig, NULL); + break; + case WK2: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK2_FLT_MASK, FILTER_ONTIME_END_TIMER1, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK2_PUPD_MASK, pupdConfig, NULL); + break; + case WK3: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK3_FLT_MASK, FILTER_ONTIME_END_TIMER1, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK3_PUPD_MASK, pupdConfig, NULL); + break; + default: + break; + } + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + errCode = sbc_write_reg_field(SBC_TIMER1_CTRL, TIMER1_PER_MASK, timerPeriod, NULL); + + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_TIMER1_CTRL, TIMER1_ON_MASK, timerOnTime, NULL); + } + else if (timer == TIMER2) + { + errCode = sbc_write_reg_field(SBC_TIMER2_CTRL, TIMER2_ON_MASK, TIMER_ONTIME_OFF_LOW, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + switch (hsX) { + case HS1: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS1_MASK, CONTROLLED_BY_TIMER2, NULL); + break; + case HS2: + errCode = sbc_write_reg_field(SBC_HS_CTRL_1, HS2_MASK, CONTROLLED_BY_TIMER2, NULL); + break; + case HS3: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS3_MASK, CONTROLLED_BY_TIMER2, NULL); + break; + case HS4: + errCode = sbc_write_reg_field(SBC_HS_CTRL_2, HS4_MASK, CONTROLLED_BY_TIMER2, NULL); + break; + default: + return errCode; + } + + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + switch (wk) + { + case WK1: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK1_FLT_MASK, FILTER_ONTIME_END_TIMER2, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK1_PUPD_MASK, pupdConfig, NULL); + break; + case WK2: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK2_FLT_MASK, FILTER_ONTIME_END_TIMER2, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK2_PUPD_MASK, pupdConfig, NULL); + break; + case WK3: + errCode = sbc_write_reg_field(SBC_WK_FLT_CTRL, WK3_FLT_MASK, FILTER_ONTIME_END_TIMER2, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_PUPD_CTRL, WK3_PUPD_MASK, pupdConfig, NULL); + break; + default: + break; + } + errCode = sbc_write_reg_field(SBC_TIMER2_CTRL, TIMER2_PER_MASK, timerPeriod, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_TIMER2_CTRL, TIMER2_ON_MASK, timerOnTime, NULL); + } else { + return errCode; + } + return errCode; +} + +/* configure cyclic wake function*/ +SBC_ErrorCode sbc_cyclicwake(sbc_timer_t timer, sbc_timer_per_t timer_period, sbc_timer_on_t timer_on_time) { + SBC_ErrorCode errCode={0,0,0}; + + if (timer == TIMER1) { + errCode = sbc_write_reg_field(SBC_WK_CTRL_1, TIMER1_WK_EN_MASK, TIMER_WAKE_DISABLED, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_TIMER1_CTRL, TIMER1_PER_MASK, timer_period, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_TIMER1_CTRL, TIMER1_ON_MASK, timer_on_time, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_CTRL_1, TIMER1_WK_EN_MASK, TIMER_WAKE_ENABLED, NULL); + } + else if (timer == TIMER2) { + errCode = sbc_write_reg_field(SBC_WK_CTRL_1, TIMER2_WK_EN_MASK, TIMER_WAKE_DISABLED, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + + errCode = sbc_write_reg_field(SBC_TIMER2_CTRL, TIMER2_PER_MASK, timer_period, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_TIMER2_CTRL, TIMER2_ON_MASK, timer_on_time, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_WK_CTRL_1, TIMER2_WK_EN_MASK, TIMER_WAKE_ENABLED, NULL); +} else { + return errCode; + } + return errCode; +} + + +/* configure watchdog*/ +SBC_ErrorCode sbc_configure_watchdog(sbc_wd_win_t wdWindow, sbc_wd_en_wk_bus_t wdEnableAfterBusWake, sbc_wd_timer_t wdTimer) { + SBC_ErrorCode errCode; + /* Calculate checksum */ + uint8_t wd_ctrl = (wdWindow << SBC_BITPOSITION(WD_WIN_MASK)) + | (wdEnableAfterBusWake << SBC_BITPOSITION(WD_EN_WK_BUS_MASK)) + | (wdTimer << SBC_BITPOSITION(WD_TIMER_MASK)); + uint8_t checksum = wd_ctrl; + + + + checksum = checksum ^ checksum >> 4; + checksum = checksum ^ checksum >> 2; + checksum = checksum ^ checksum >> 1; + + + if((checksum & 1) > 0) { + /* Set parity bit */ + wd_ctrl = wd_ctrl | 0x80U; // + } + errCode = sbc_write_reg(SBC_WD_CTRL, wd_ctrl, NULL); + if (errCode.flippedBitsMask == 0) { + + /* Save new Watchdog configuration to global variable */ + wd_config = wd_ctrl; + } + return errCode; +} + +/* configure PWM*/ +SBC_ErrorCode sbc_configure_pwm(sbc_pwm_t pwm, sbc_pwm_freq_t frequency, uint8_t dutyCycle) { + SBC_ErrorCode errCode={0,0,0}; + switch (pwm) { + case PWM1: + errCode = sbc_write_reg(SBC_PWM1_CTRL, dutyCycle, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_PWM_FREQ_CTRL, PWM1_FREQ_MASK, frequency, NULL); + break; + case PWM2: + errCode = sbc_write_reg(SBC_PWM2_CTRL, dutyCycle, NULL); + if(errCode.flippedBitsMask > 0) { + return errCode; + } + errCode = sbc_write_reg_field(SBC_PWM_FREQ_CTRL, PWM2_FREQ_MASK, frequency, NULL); + break; + + default: + return errCode; + } + return errCode; +} + +/* configure PWM percentage*/ +SBC_ErrorCode sbc_configure_pwm_percentage(sbc_pwm_t pwm, sbc_pwm_freq_t frequency, double duty_cycle) { + return sbc_configure_pwm(pwm, frequency, (uint8_t)(duty_cycle*0xFFU)); +} + +/* Configure GPIO*/ +SBC_ErrorCode sbc_configure_gpio(sbc_gpiox_t gpio, sbc_gpio_t gpio_config) { + SBC_ErrorCode errCode= {0,0,0}; + switch (gpio) { + case GPIO1: + errCode = sbc_write_reg_field(SBC_GPIO_CTRL, GPIO1_MASK, gpio_config, NULL); + break; + case GPIO2: + errCode = sbc_write_reg_field(SBC_GPIO_CTRL, GPIO2_MASK, gpio_config, NULL); + break; + + default: + return errCode; + } + + return errCode; +} + + +/* Configure Failure Output*/ +SBC_ErrorCode sbc_fo_x(uint8_t on) { + if (on) { + return sbc_write_reg_field(SBC_HW_CTRL, FO_ON_MASK, FO_ON_ACTIVE, NULL); + } else { + return sbc_write_reg_field(SBC_HW_CTRL, FO_ON_MASK, FO_ON_NOT_ACTIVE, NULL); + } +} +/* configure VCC2*/ +SBC_ErrorCode sbc_switch_vcc2(sbc_vcc2_on_t vcc2_value) { + SBC_ErrorCode errCode; + + errCode = sbc_write_reg_field(SBC_M_S_CTRL, VCC2_ON_MASK, vcc2_value, NULL); + + return errCode; +} +/* configure VCC3*/ +SBC_ErrorCode sbc_switch_vcc3(sbc_vcc3_on_t vcc3_value) { + SBC_ErrorCode errCode; + errCode = sbc_write_reg_field(SBC_M_S_CTRL, VCC3_ON_MASK , vcc3_value, NULL); + + return errCode; +} diff --git a/firmware/src/TLE9263/TLE926x.h b/firmware/src/TLE9263/TLE926x.h new file mode 100644 index 0000000..2f3831b --- /dev/null +++ b/firmware/src/TLE9263/TLE926x.h @@ -0,0 +1,511 @@ +/********************************************************************************************************************* + * Copyright (c) 2021, Infineon Technologies AG + * + * + * Distributed under the Boost Software License, Version 1.0. + * + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + *********************************************************************************************************************/ + + +/******************************************************************************************************** + * @file TLE926x.h + * + * @brief Main header declaration file for TLE926x SBC family device + * + * @version V1.0.0 + * @date + * @author Fedy Farhat + * @author Michael Schaffarczyk + ********************************************************************************************************/ + +#ifndef TLE926x_H +#define TLE926x_H + +/* ================================================================================ */ +/* ============================ HEADER FILES ================================ */ +/* ================================================================================ */ + +#include "TLE926x_DEFINES.h" +#include "TLE926x_ISR.h" +#include "TLE926x_SPI.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ================================================================================ */ +/* ================================ MACROS ================================== */ +/* ================================================================================ */ + + +/** + * \def SBC_WRITE_BIT + * + * \brief This bit has to be set in order to write to a register. + */ +#define SBC_WRITE_BIT (0x80U) + +/** + * \def SBC_READ_MASK + * + * \brief A mask to prevent the user from accidentally writing to a register. + */ +#define SBC_READ_MASK (0x7FU) + + + + + +/* ================================================================================ */ +/* =========================== Library Functions ============================ */ +/* ================================================================================ */ + + + +/** + * @def SBC_ErrorCode + + * @brief A structure for simple error readout. + * + * @param flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue. + * !< Masks the bits that differ from the expected value. Is 0 if readout is as expected. + * @param SBC_Register is The register where an error occurred. + * @param expectedValue ! 5) { + sbc_wd_trigger(); + timeref = 0; + } + + /* Handle SBC_ISR() if INTN was toggeled */ + if (irqSBC) { + irqSBC = 0; + } +} diff --git a/firmware/src/TLE9263/TLE926x_Main.h b/firmware/src/TLE9263/TLE926x_Main.h new file mode 100644 index 0000000..55f91c3 --- /dev/null +++ b/firmware/src/TLE9263/TLE926x_Main.h @@ -0,0 +1,9 @@ +#ifndef __TLE926x_MAIN__ +#define __TLE926x_MAIN__ + + +void Tle9263_Init(void); +void Tle9263_MainTask(void); + + +#endif diff --git a/firmware/src/TLE9263/TLE926x_SPI.c b/firmware/src/TLE9263/TLE926x_SPI.c new file mode 100644 index 0000000..27876e1 --- /dev/null +++ b/firmware/src/TLE9263/TLE926x_SPI.c @@ -0,0 +1,120 @@ +/********************************************************************************************************************* + * Copyright (c) 2021, Infineon Technologies AG + * + * + * Distributed under the Boost Software License, Version 1.0. + * + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + *********************************************************************************************************************/ + + +/******************************************************************************************************** + * @file TLE926x_SPI.c + * + * @brief Implementation of all SPI related functions + * + * @version V1.0.0 + * @date + * @author Fedy Farhat + * @author Michael Schaffarczyk + ********************************************************************************************************/ + + + +/* ================================================================================ */ +/* ============================ HEADER FILES ================================ */ +/* ================================================================================ */ + +#include "TLE926x_SPI.h" +#include "..\config\mcal\peripheral\sercom\spi_master\plib_sercom0_spi_master.h" +#include "..\config\mcal\peripheral\port\plib_port.h" + + + +uint16_t TLE9263_Tx_Buff_u16; +uint16_t TLE9263_Rx_Buff_u16; +uint32_t TLF9263_SPI_Tx_Flag = 0; + + +void CALLBACK(uintptr_t context) +{ + TLF9263_SPI_Tx_Flag = 0; +} + + +/* ================================================================================ */ +/* ======================= SPI communication functions ====================== */ +/* ================================================================================ */ + + + +uint8_t sbc_spi_init(void) +{ + //SERCOM0_SPI_CallbackRegister (&CALLBACK, (uintptr_t)NULL ); + return 0; +} + + + +uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) +{ + + bool ret; + uint16_t temp; + + TLE9263_Tx_Buff_u16 = ((uint16_t)Upper); + TLE9263_Tx_Buff_u16 |= (((uint16_t)Lower)<< 8); + TLF9263_SPI_Tx_Flag = 0x1; + Spi_Software_Trigger_Clear(); + ret = SERCOM0_SPI_WriteRead(&TLE9263_Tx_Buff_u16,2,&TLE9263_Rx_Buff_u16,2); + + if(ret) + { + while(SERCOM0_SPI_IsTransmitterBusy() == 1); + } + Spi_Software_Trigger_Set(); + /* + if(ret) + { + for(;;){ + __enable_irq(); + if(TLF9263_SPI_Tx_Flag == 0 ) + { + break; + } + __disable_irq(); + } + }*/ + + temp = TLE9263_Rx_Buff_u16<<8; + TLE9263_Rx_Buff_u16 = TLE9263_Rx_Buff_u16>>8; + TLE9263_Rx_Buff_u16 = (TLE9263_Rx_Buff_u16&0xFF) | (temp&0xFF00); + return TLE9263_Rx_Buff_u16; +} + + + diff --git a/firmware/src/TLE9263/TLE926x_SPI.h b/firmware/src/TLE9263/TLE926x_SPI.h new file mode 100644 index 0000000..b11b752 --- /dev/null +++ b/firmware/src/TLE9263/TLE926x_SPI.h @@ -0,0 +1,106 @@ +/********************************************************************************************************************* + * Copyright (c) 2021, Infineon Technologies AG + * + * + * Distributed under the Boost Software License, Version 1.0. + * + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + *********************************************************************************************************************/ + + +/******************************************************************************************************** + * @file TLE926x_SPI.h + * + * @brief Declaration file for TLE926x SBC family device SPI functions + * + * @version V1.0.0 + * @date + * @author Fedy Farhat + * @author Michael Schaffarczyk + ********************************************************************************************************/ + + + + +#ifndef TLE926x_SPI_H +#define TLE926x_SPI_H + + + + + + +/* ================================================================================ */ +/* ============================ HEADER FILES ================================ */ +/* ================================================================================ */ + + +#ifndef uint8_t +typedef unsigned char uint8_t; +#endif + +#ifndef uint16_t +typedef unsigned short uint16_t; +#endif + +#ifndef bool +typedef unsigned char bool; +#endif + + + +/* ================================================================================ */ +/* ============================= SPI Functions ============================== */ +/* ================================================================================ */ + +/** + * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER + * + * The function has to initialze the SPI of the uC and will be called once during SBC_Init(). + * In case, the SPI hardware is already initialized by some other code before, it can be left blank. + * + * @retval Method has to return 0 if initialization was successful. + */ +uint8_t sbc_spi_init(void); + +/** + * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER + * + * The function will be called by the library everytime when a SPI communication is needed. + * The function proceeds a bidirectional 16-bit transfer to/from the SBC . + * As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments. + * For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples. + * + * @param Upper The first 8 bit to transmit to the SBC. + * @param Lower The second 8 bit to transmit to the SBC. + * @retval The function will return all 16 bits received from the SBC. + * Bit[15:8] are the first 8 bits received (Status-Information-Field). + * Bit[7:0] is the data-field transmitted of the SBC. + */ +uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower); + +#endif /* TLE926x_SPI_H */ diff --git a/firmware/src/TLE9263/sbc_tle9263.icwp b/firmware/src/TLE9263/sbc_tle9263.icwp new file mode 100644 index 0000000..8c20a27 --- /dev/null +++ b/firmware/src/TLE9263/sbc_tle9263.icwp @@ -0,0 +1,328 @@ + + + 938a5187cdcc759f78b6bae262f689a50c384e539a95618defe57f554fa7fafd + TLE926x_Lib.xml + V0.0.1 + + + CW.M_S_CTRL[2] + 0 + 0 + + + CW.M_S_CTRL[1:0] + 0 + 0 + + + CW.HW_CTRL[3] + 0 + 0 + + + CW.HW_CTRL[1] + 0 + 0 + + + CW.M_S_CTRL[5] + 0 + 0 + + + CW.BUS_CTRL_2[1:0] + 0 + 0 + + + CW.BUS_CTRL_1[5] + 1 + 1 + + + CW.BUS_CTRL_1[6] + 0 + 0 + + + CW.BUS_CTRL_1[7] + 0 + 0 + + + MATH.EN_PN + 0 + 0 + + + CW.SWK_CAN_FD_CTRL[0] + 1 + 0 + + + CW.SWK_CAN_FD_CTRL[5] + 1 + 0 + + + CW.SWK_CAN_FD_CTRL[3:1] + 2 + 0 + + + MATH.BAUDRADE + 2 + 2 + + + MATH.DOUBLE_CDR_FREQ + 0 + 0 + + + CW.SWK_BTL2_CTRL[5:0] + 0 + 0 + + + CW.SWK_ID0_CTRL[0] + 0 + 0 + + + UI.SWK_IDx_CTRL + 0x00000000 + 0 + + + UI.SWK_MASK_IDx_CTRL + 0x00000000 + 0 + + + CW.SWK_DLC_CTRL[3:0] + 0 + 0 + + + CW.SWK_DATA_H_CTRL + 0x00000000 + 0x00000000 + + + CW.SWK_DATA_L_CTRL + 0x00000000 + 0x00000000 + + + CW.GPIO_CTRL[2:0] + 0 + 0 + + + CW.GPIO_CTRL[5:3] + 0 + 0 + + + CW.GPIO_CTRL[7:6] + 0 + 0 + + + CW.WK_CTRL_2[7] + 0 + 0 + + + CW.HW_CTRL[0] + 0 + 0 + + + CW.HW_CTRL[5] + 0 + 0 + + + CW.HW_CTRL[6] + 0 + 0 + + + CW.WD_CTRL[4] + 0 + 0 + + + CW.WD_CTRL[5] + 0 + 0 + + + CW.WK_CTRL_2[5] + 0 + 0 + + + CW.WK_CTRL_2[0] + 1 + 1 + + + CW.WK_CTRL_2[1] + 1 + 1 + + + CW.WK_CTRL_2[2] + 1 + 1 + + + CW.WK_FLT_CTRL[1:0] + 0 + 0 + + + CW.WK_FLT_CTRL[3:2] + 0 + 0 + + + CW.WK_FLT_CTRL[5:4] + 0 + 0 + + + CW.WK_CTRL_1[6] + 0 + 0 + + + CW.TIMER1_CTRL[2:0] + 0 + 0 + + + CW.TIMER1_CTRL[6:4] + 0 + 0 + + + CW.WK_CTRL_1[7] + 0 + 0 + + + CW.TIMER2_CTRL[2:0] + 0 + 0 + + + CW.TIMER2_CTRL[6:4] + 0 + 0 + + + CW.PWM_FREQ_CTRL[0] + 0 + 0 + + + UI.PWM1_DC + 0 + 0.0 + + + CW.PWM_FREQ_CTRL[2] + 0 + 0 + + + UI.PWM2_DC + 0 + 0.0 + + + CW.SW_SD_CTRL[6] + 0 + 0 + + + CW.SW_SD_CTRL[5] + 0 + 0 + + + CW.SW_SD_CTRL[4] + 0 + 0 + + + CW.HS_CTRL1[2:0] + 0 + 0 + + + CW.HS_CTRL1[6:4] + 0 + 0 + + + CW.HS_CTRL2[2:0] + 0 + 0 + + + CW.HS_CTRL2[6:4] + 0 + 0 + + + UI.VARIANT + 3 + 3 + + + CW.M_S_CTRL[4:3] + 1 + 1 + + + CW.BUS_CTRL_1[2:0] + 3 + 3 + + + CW.BUS_CTRL_1[4:3] + 3 + 3 + + + CW.WD_CTRL[2:0] + 6 + 6 + + + CW.HW_CTRL[7] + 1 + 1 + + + CW.WK_PUPD_CTRL[1:0] + 3 + 3 + + + CW.WK_PUPD_CTRL[3:2] + 3 + 3 + + + CW.WK_PUPD_CTRL[5:4] + 3 + 3 + + + \ No newline at end of file diff --git a/firmware/src/TouchPanel/TouchPanel.c b/firmware/src/TouchPanel/TouchPanel.c new file mode 100644 index 0000000..ffc053d --- /dev/null +++ b/firmware/src/TouchPanel/TouchPanel.c @@ -0,0 +1,2192 @@ +#include "TouchPanel.h" +//#include "TouchPanel_Cfg.h" +#include "Std_Types.h" +#include "device.h" +#include "touch/touch.h" +#include "math.h" +#include "stdlib.h" + + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "OsekCom/OsekCom.h" +#include "Speaker/Speaker.h" +#include "P417_SWTR_App_ert_rtw/P417_SWTR_App.h" +#include "TouchPanel/TouchPanel.h" +#include "forceSnsr/forcedetect.h" +#include "TLE9263/TLE926x_Main.h" +#include "RTE.h" +#include "calib_public.h" +#include "smartee.h" +#include "SysDiagDetect.h" +//#define DEBUG_TEST +//#define PRESS_DEBUG +static uint16 sensor_signal[DEF_NUM_CHANNELS] = {0}; +static uint16 sensor_reference[DEF_NUM_CHANNELS] = {0}; +static TouchButtons_type key_status[BTN_MAX_CH_NUM - 5U] = {0}; +static TouchSurface_type TouchSurface; +static TouchScroller_type TouchScroller; +static Buttons_SignalType Buttons_Signal[BTN_MAX_CH_NUM] = {BUTTON_RELEASE}; +static TouchSlideEvent_type TouchSlideEvent; +TouchSurface_Convert_type Surface_Convert; +static PanelPress_LevelType TouchPanel_PressLevel = PANEL_PRESS_LEVEL0; +static float32 TouchPanel_PressNValue = 0.0f;//0N +static uint8 TouchPanel_SurfaceStatus = 0; +static uint8 TouchPanel_ScrollerStatus = 0; +static uint16 TouchPanel_PressRawData = 0; +//extern volatile uint8 Vibra_force_level; + +//kailong add +volatile uint16 g_Trig_Threshold=350; +volatile uint16 g_Release_Threshold=175; +volatile uint8 K_Vibra_Trig=0; +volatile uint8 Reach2_flag = 0x00; +volatile uint8 Vibra_force_level=0; +volatile uint8 last_Vibra_force_level=0; + uint16 Over3N_vibra_req = 0x00; + uint16 Below1P5N_vibra_req = 0x00; + +uint8 UDS_Vibration_Gain = 0; +uint8 UDS_DAC_Timer_Period = 80; +uint8 Touch_Flag = TOUCH_KET_OFF; +uint8_t PressState=0; + +#ifdef PRESS_DEBUG +extern void CanTx(t_can_handler can_handler, bool notif, uint32_t idtp, uint16_t len, t_can_data can_data); +#endif + +uint8 CurrentPosition = 0xff;//0xff no position 1:fun1 2:fun2 3:fun3 4:up 5:down 6:left 7:right 8:ok +uint8 Surface_Button = 0xff; +#define Voice1_DEFAULT 339 +#define Vol1_DEFAULT 412 +#define Menu1_DEFAULT 576 +#define BTN_UP_DEFAULT 269 +#define BTN_DOWN_DEFAULT 398 +#define BTN_LEFT_DEFAULT 261 +#define BTN_RIGHT_DEFAULT 372 +#define BTN_CONFIRM_DEFAULT 303 +//force Trig threshold +static uint16 Button0_GetVoice1_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(0U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Voice1_DEFAULT; + } + else + { + rtn=Calib_GetData(0U); + } + + return rtn; +} + +//static uint16 Button1_GetVoice2_Trig_Threshold(void) +//{ +// return 400; +//} + +//static uint16 Button2_GetVol2_Trig_Threshold(void) +//{ +// return 1600; +//} + +static uint16 Button3_GetVol1_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(1U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Vol1_DEFAULT; + } + else + { + rtn=Calib_GetData(1U); + } + + return rtn; +} + +//static uint16 Button4_GetMenu2_Trig_Threshold(void) +//{ +// return 1600; +//} + +static uint16 Button5_GetMenu1_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(2U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Menu1_DEFAULT; + } + else + { + rtn=Calib_GetData(2U); + } + + return rtn; +} + +static uint16 Button6_GetBTN_UP_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(3U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_UP_DEFAULT; + } + else + { + rtn=Calib_GetData(3U); + } + + return rtn; +} + +static uint16 Button7_GetBTN_DOWN_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(4U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_DOWN_DEFAULT; + } + else + { + rtn=Calib_GetData(4U); + } + + return rtn; +} + +static uint16 Button8_GetBTN_LEFT_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(5U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_LEFT_DEFAULT; + } + else + { + rtn=Calib_GetData(5U); + } + + return rtn; +} + +static uint16 Button9_GetBTN_RIGHT_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(6U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_RIGHT_DEFAULT; + } + else + { + rtn=Calib_GetData(6U); + } + + return rtn; +} + +static uint16 Button10_GetBTN_CONFIRM_Trig_Threshold(void) +{ + uint16 temp = Calib_GetData(7U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_CONFIRM_DEFAULT; + } + else + { + rtn=Calib_GetData(7U); + } + + return rtn; +} + +//force Release threshold +static uint16 Button0_GetVoice1_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(0U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Voice1_DEFAULT/2; + } + else + { + rtn=Calib_GetData(0U)/2; + } + + return rtn; +} + +//static uint16 Button1_GetVoice2_Release_Threshold(void) +//{ +// return 200; +//} + +//static uint16 Button2_GetVol2_Release_Threshold(void) +//{ +// return 400; +//} + +static uint16 Button3_GetVol1_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(1U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Vol1_DEFAULT/2; + } + else + { + rtn=Calib_GetData(1U)/2; + } + + return rtn; +} + +//static uint16 Button4_GetMenu2_Release_Threshold(void) +//{ +// return 400; +//} + +static uint16 Button5_GetMenu1_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(2U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=Menu1_DEFAULT/2; + } + else + { + rtn=Calib_GetData(2U)/2; + } + + return rtn; +} + +static uint16 Button6_GetBTN_UP_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(3U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_UP_DEFAULT/2; + } + else + { + rtn=Calib_GetData(3U)/2; + } + + return rtn; +} + +static uint16 Button7_GetBTN_DOWN_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(4U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_DOWN_DEFAULT/2; + } + else + { + rtn=Calib_GetData(4U)/2; + } + + return rtn; +} + +static uint16 Button8_GetBTN_LEFT_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(5U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_LEFT_DEFAULT/2; + } + else + { + rtn=Calib_GetData(5U)/2; + } + + return rtn; +} + +static uint16 Button9_GetBTN_RIGHT_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(6U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_RIGHT_DEFAULT/2; + } + else + { + rtn=Calib_GetData(6U)/2; + } + + return rtn; +} + +static uint16 Button10_GetBTN_CONFIRM_Release_Threshold(void) +{ + uint16 temp = Calib_GetData(7U); + uint16 rtn = 0; + if(temp == 0) + { + rtn=BTN_CONFIRM_DEFAULT/2; + } + else + { + rtn=Calib_GetData(7U)/2; + } + + return rtn; +} + + + + + + + + + +/** + * \brief Sets buffers to a specified byte value. + * \param pDestP buffer with set value + * \param u8ValueP byte value + * \param BytesCountP number of bytes + * \return None + */ +static void LIB_Mem_MemSet (void * const pDestP, const uint8 u8ValueP, const uint32 u32BytesCountP) +{ + + uint8 * pu8BufL = (uint8 *)pDestP; + uint32 u32IdxL; + + if( (NULL_PTR != pu8BufL) ) + { + u32IdxL = u32BytesCountP; + + while( u32IdxL > (uint32)0 ) + { + --u32IdxL; + + (*pu8BufL) = u8ValueP; + pu8BufL = &pu8BufL[1]; + } + } +} + +static float32 AlideAverage_Filter(uint8 mode, float32 RawData) +{ + #define MAX_ALIDE_AVG_NUM 8 + static uint16 CalcAverageNum = 0; + static uint16 DIndex = 0; + static uint16 Mode_Status = 0; + static float32 RawData_Table[MAX_ALIDE_AVG_NUM] = {0}; + uint16 i; + float32 Sum = 0; + float32 AverageValue = 0; + if(mode == 0x00){ + CalcAverageNum = 0; + DIndex = 0; + Mode_Status = 0; + for(i=0; i= MAX_ALIDE_AVG_NUM) + { + Mode_Status = 0x01; + DIndex = 0; + } + AverageValue = Sum/((float32)CalcAverageNum + 0.000001f); + } + else + { + RawData_Table[DIndex++] = RawData; + if(DIndex >= MAX_ALIDE_AVG_NUM){ + DIndex = 0x00; + } + for(i=0; i= 40) + { + UDS_DAC_Timer_Period = eedata[2]; + } + else + { + UDS_DAC_Timer_Period = 110; + } + TC0_REGS->COUNT16.TC_CC[0U] = UDS_DAC_Timer_Period; + AlideAverage_Filter(0, 0); + TouchPanel_PressLevel = PANEL_PRESS_LEVEL0; + TouchPanel_PressNValue = 0.0f;//0N + TouchPanel_SurfaceStatus = 0; + TouchPanel_ScrollerStatus = 0; + TouchPanel_PressRawData = 0; + for(index = 0; index< DEF_NUM_CHANNELS; index++) + { + sensor_signal[index] = 0x00; + sensor_reference[index] = 0x00; + if(index < (BTN_MAX_CH_NUM-5u)){ + key_status[index].status = 0x00; + key_status[index].RunCycle = 0x00; + } + if(index < BTN_MAX_CH_NUM ){ + Buttons_Signal[index] = BUTTON_RELEASE; + } + } +} + +void GetSurface_Position(uint8 *x, uint8 *y) +{ + if(x != NULL_PTR){ + *x = Surface_Convert.convert_x; + } + if(y != NULL_PTR){ + *y = Surface_Convert.convert_y; + } +} + +void GetScroller_Position(uint8 *x, uint8 *y) +{ + if(x != NULL_PTR){ + *x = TouchScroller.x_position; + } + if(y != NULL_PTR){ + *y = TouchScroller.y_position; + } +} + + +TP_SlideDirection_Enum TouchPanel_SlideEventRead(void) +{ + TP_SlideDirection_Enum Dir = TP_SlideDirection_NONE; + if(TouchSlideEvent.Event == TRUE){ + Dir = TouchSlideEvent.Direction; + } + return Dir; +} + + +TP_SlideLevel_Enum TouchPanel_SlideUpDownLevelRead(void) +{ + TP_SlideLevel_Enum SlideLevel = TP_SlideLevel_NONE; + if(TouchSlideEvent.Event == TRUE){ + SlideLevel = TouchSlideEvent.UpDown_SlideLevel; + } + return SlideLevel; +} + +Buttons_SignalType TouchPanel_BtnSignalRead(Buttons_ChType ChId) +{ + Buttons_SignalType Signal = BUTTON_RELEASE; + + if(ChId < BTN_MAX_CH_NUM) + { + Signal = Buttons_Signal[ChId]; + } + + return Signal; +} + +PanelPress_LevelType TouchPanel_PressLevelRead(void) +{ + return TouchPanel_PressLevel; +} + +boolean TouchSurface_is_TouchActive(void) +{ + boolean ret = FALSE; + if (TouchPanel_SurfaceStatus & TOUCH_ACTIVE) + { + ret = TRUE; + } + if (PressState == 0) + { + ret = FALSE; + } + return ret; +} + +boolean TouchButton_is_TouchActive(Buttons_ChType BtId) +{ + boolean ret = FALSE; + if (QTM_KEY_STATE_DETECT == (key_status[BtId].status) && BtId < BTN_UP) + { + ret = TRUE; + } + if (PressState == 0) + { + ret = FALSE; + } + return ret; +} + +boolean TouchScroller_is_TouchActive(void) +{ + boolean ret = FALSE; + if (TouchPanel_ScrollerStatus & TOUCH_ACTIVE) + { + ret = TRUE; + } + if (PressState == 0) + { + ret = FALSE; + } + return ret; +} + +Buttons_SignalType TouchSurface_XY_StsRead(void) +{ + Buttons_SignalType XY_Sts = BUTTON_RELEASE; + if (TouchPanel_SurfaceStatus & TOUCH_ACTIVE) + { + + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + XY_Sts = BUTTON_TOUCH; + break; + case PANEL_PRESS_LEVEL1: + XY_Sts = BUTTON_TOUCH; + break; + case PANEL_PRESS_LEVEL2: + XY_Sts = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + + + + } + if (PressState == 0) + { + XY_Sts = PANEL_PRESS_LEVEL0; + } + + return XY_Sts; +} + +//kailong + +#if 0 +uint8 Vibra_PressCheck(void) +{ + uint16 RawData = 0; + uint16 temp_RawData = 0; + static uint16 LastRawData = 0; + static PanelPress_LevelType Last_PressLevel = PANEL_PRESS_LEVEL0; + PanelPress_LevelType ret_Press = PANEL_PRESS_LEVEL0; + float32 FilterValue; + float32 PressNValueTable[3][2] = { + {1.5f, 3.0f}, + {0.5f, 3.0f}, + {1.0f, 1.8f} + }; + + if(Last_PressLevel > PANEL_PRESS_LEVEL2){ Last_PressLevel = PANEL_PRESS_LEVEL0;} + ////if(TRUE == GET_TouchPanel_is_Press()) + temp_RawData = (0xfff & Get_forcedetect_force_value()); + if(SPEAKER_UPDATE_CYCLE == Get_Speaker_Main_State()) + { + RawData = LastRawData; + } + else + { + if(temp_RawData&0x800)//negative + { + RawData = 0x00; + }else{ + RawData = temp_RawData; + } + + if(abs(RawData - LastRawData) > (10*0xF2)) + { + RawData = LastRawData; + } + } + + TouchPanel_PressRawData = RawData; + TouchPanel_PressNValue = ((float32)RawData / (float32)0xF2); + FilterValue = AlideAverage_Filter(1, TouchPanel_PressNValue); + if(FilterValue < PressNValueTable[Last_PressLevel][0]){//< 1N + ret_Press = PANEL_PRESS_LEVEL0; + //Vibra_force_level=PANEL_PRESS_LEVEL0; + }else if(FilterValue >= PressNValueTable[Last_PressLevel][0] && + FilterValue < PressNValueTable[Last_PressLevel][1]){//1N~3N + ret_Press = PANEL_PRESS_LEVEL1; + //Vibra_force_level=PANEL_PRESS_LEVEL1; + }else{//>=3 + ret_Press = PANEL_PRESS_LEVEL2; + //Vibra_force_level=PANEL_PRESS_LEVEL2; + } + + + + LastRawData = RawData; + Last_PressLevel = ret_Press; + return ret_Press; +} + +#endif + +//kailong + + + + + + static PanelPress_LevelType TouchPanel_PressCheck(void) +{ + //static uint16 ForceHcount = 0; + //static uint16 ForceMcount = 0; + //static uint16 ForceLcount = 0; + + static uint16 tempForcePress = 0; + static uint16 tempForceRelease = 0; + + uint16 RawData = 0; + uint16 temp_RawData = 0; + static uint16 LastRawData = 0; + static PanelPress_LevelType Last_PressLevel = PANEL_PRESS_LEVEL0; + static uint8 P_force_Reach2_flag = 0; + PanelPress_LevelType ret_Press = PANEL_PRESS_LEVEL0; + float32 FilterValue; + uint16 Backup_Force_Value_Pad; + uint16 Backup_Force_Value_Button; + Backup_Force_Value_Pad=Touch_Sensor_Sts05+Touch_Sensor_Sts06+Touch_Sensor_Sts07+Touch_Sensor_Sts08+Touch_Sensor_Sts09+ + +Touch_Sensor_Sts10+Touch_Sensor_Sts11+Touch_Sensor_Sts12+Touch_Sensor_Sts13+Touch_Sensor_Sts14; + Backup_Force_Value_Button=Touch_Sensor_Sts00+Touch_Sensor_Sts01+Touch_Sensor_Sts02+Touch_Sensor_Sts03+Touch_Sensor_Sts04; + //float32 PressNValueTable[3][2] = { + // {1.21f, 1.73f}, + // {0.5f, 3.0f}, + // {1.0f, 1.8f} + //}; + + if(CurrentPosition != 0xff) + { + tempForcePress = g_Trig_Threshold; + tempForceRelease = g_Release_Threshold; + } + //else + //{ + // return PANEL_PRESS_LEVEL0; + //} + + if(Last_PressLevel > PANEL_PRESS_LEVEL2){ Last_PressLevel = PANEL_PRESS_LEVEL0;} + ////if(TRUE == GET_TouchPanel_is_Press()) + temp_RawData = (0xfff & Get_forcedetect_force_value()); + if(SPEAKER_UPDATE_CYCLE == Get_Speaker_Main_State()) + { + RawData = LastRawData; + } + else + { + if(temp_RawData&0x800)//negative + { + RawData = 0x00; + }else{ + RawData = temp_RawData; + } + + if(abs(RawData - LastRawData) > (10*0xF2)) + { + RawData = LastRawData; + } + } + + TouchPanel_PressRawData = RawData; + TouchPanel_PressNValue = ((float32)RawData / (float32)0xF2); + FilterValue = AlideAverage_Filter(1, TouchPanel_PressNValue); + + if(Force_Sens_Err == 0) + { + if(FilterValue <= ((float32)tempForceRelease/ (float32)0xF2)){//< 1.5N + // ForceHcount = 0; + // ForceMcount = 0; + //ForceLcount++; + P_force_Reach2_flag = 0; + // if(ForceLcount > 40) + //{ + // ForceLcount = 40; + + ret_Press = PANEL_PRESS_LEVEL0; + + //} + Vibra_force_level=PANEL_PRESS_LEVEL0; + } + else if(FilterValue >= ((float32)tempForceRelease/ (float32)0xF2) && + FilterValue < ((float32)tempForcePress/ (float32)0xF2)){//1.5N~3N + + //ForceHcount = 0; + // ForceMcount++; + // ForceLcount = 0; + // if(ForceMcount > 40) + // { + // ForceMcount = 40; + if(P_force_Reach2_flag==1) + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL2; + ret_Press = PANEL_PRESS_LEVEL2; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + else + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL1; + ret_Press = PANEL_PRESS_LEVEL1; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + } + + + else {//>=3 + //ForceHcount++; + //ForceMcount = 0; + // ForceLcount = 0; + P_force_Reach2_flag = 1; + // if(ForceHcount > 40) + // { + // ForceHcount = 40; + + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + ret_Press = PANEL_PRESS_LEVEL2; + + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + + Vibra_force_level=PANEL_PRESS_LEVEL2; + } + } + else//backup When force sensor error happened + { + if(CurrentPosition <=3 ) //Button + { + if(Backup_Force_Value_Button <= 35){//< 1.5N + // ForceHcount = 0; + // ForceMcount = 0; + //ForceLcount++; + P_force_Reach2_flag = 0; + // if(ForceLcount > 40) + //{ + // ForceLcount = 40; + + ret_Press = PANEL_PRESS_LEVEL0; + + //} + Vibra_force_level=PANEL_PRESS_LEVEL0; + } + else if(Backup_Force_Value_Button >35 && + Backup_Force_Value_Button < 70){//1.5N~3N + + //ForceHcount = 0; + // ForceMcount++; + // ForceLcount = 0; + // if(ForceMcount > 40) + // { + // ForceMcount = 40; + if(P_force_Reach2_flag==1) + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL2; + ret_Press = PANEL_PRESS_LEVEL2; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + else + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL1; + ret_Press = PANEL_PRESS_LEVEL1; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + } + + + else {//>=3 + //ForceHcount++; + //ForceMcount = 0; + // ForceLcount = 0; + P_force_Reach2_flag = 1; + // if(ForceHcount > 40) + // { + // ForceHcount = 40; + + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + ret_Press = PANEL_PRESS_LEVEL2; + + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + + Vibra_force_level=PANEL_PRESS_LEVEL2; + } + } + else//Pad + { + if(Backup_Force_Value_Pad <= 100){//< 1.5N + // ForceHcount = 0; + // ForceMcount = 0; + //ForceLcount++; + P_force_Reach2_flag = 0; + // if(ForceLcount > 40) + //{ + // ForceLcount = 40; + + ret_Press = PANEL_PRESS_LEVEL0; + + //} + Vibra_force_level=PANEL_PRESS_LEVEL0; + } + else if(Backup_Force_Value_Pad >100 && + Backup_Force_Value_Pad < 200){//1.5N~3N + + //ForceHcount = 0; + // ForceMcount++; + // ForceLcount = 0; + // if(ForceMcount > 40) + // { + // ForceMcount = 40; + if(P_force_Reach2_flag==1) + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL2; + ret_Press = PANEL_PRESS_LEVEL2; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + else + { + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + + Vibra_force_level=PANEL_PRESS_LEVEL1; + ret_Press = PANEL_PRESS_LEVEL1; + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + } + } + + + else {//>=3 + //ForceHcount++; + //ForceMcount = 0; + // ForceLcount = 0; + P_force_Reach2_flag = 1; + // if(ForceHcount > 40) + // { + // ForceHcount = 40; + + //if(TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM > get_contact_size()) + //{ + ret_Press = PANEL_PRESS_LEVEL2; + + //} + //else + //{ + // ret_Press = PANEL_PRESS_LEVEL0; + // Vibra_force_level=PANEL_PRESS_LEVEL0; + //} + + Vibra_force_level=PANEL_PRESS_LEVEL2; + } + } + } + + LastRawData = RawData; + Last_PressLevel = ret_Press; +#ifdef PRESS_DEBUG +{ + uint8 data[8] = {0}; + uint8 data2[8] = {0}; + uint16 g_sss = TouchScroller.y_position; + data[0] = ((GET_TouchPanel_is_Press())<<2); + data[1] = ret_Press; + // data[5] =(uint8)(TouchPanel_PressRawData & 0xff) ; + // data[4] =(uint8)(( TouchPanel_PressRawData &0xff00)>>8); + + data[5] =(uint8)(g_sss & 0xff) ; + data[4] =(uint8)(( g_sss &0xff00)>>8); + CanTx(0, true, 0x111, 8, data); + + + data2[0] = key_status[0].status; + data2[1] = key_status[1].status; + data2[2] = key_status[2].status; + data2[3] = key_status[3].status; + data2[4] = key_status[4].status; + CanTx(0, true, 0x222, 8, data2); + + + +} +#endif + return ret_Press; +} + +static Buttons_SignalType TouchSurface_BntCheck(Buttons_ChType ChId, TouchPanel_EventType TP_Event) +{ + Buttons_SignalType BSignal = BUTTON_RELEASE; + //static uint8 PB_force_Reach2_flag = 0; + //uint8 x_pos = 0, y_pos = 0; + uint8 data_ready = 0x00; + //GetSurface_Position(&x_pos, &y_pos); + switch(ChId) + { + case BTN_UP: + if (Surface_Button ==1)//37 + { + data_ready = 0x01; + } + break; + case BTN_DOWN: + if (Surface_Button ==2)//223 + { + data_ready = 0x01; + } + break; + case BTN_LEFT: + if (Surface_Button ==3) + { + data_ready = 0x01; + } + break; + case BTN_RIGHT: + if (Surface_Button ==4) + { + data_ready = 0x01; + } + break; + case BTN_CONFIRM: + if (Surface_Button ==5) + { + data_ready = 0x01; + } + break; + default: break; + } + + if(data_ready != 0x00) + { + if(TP_Event == TOUCH_PANEL_PRESS_EVENT) + { + + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + //PB_force_Reach2_flag = 0; + BSignal = BUTTON_TOUCH; + case PANEL_PRESS_LEVEL1: + //if(PB_force_Reach2_flag == 1) + //{ + //BSignal = BUTTON_TOUCH_AND_PRESS; + // } + // else + //{ + BSignal = BUTTON_TOUCH; + // } + break; + case PANEL_PRESS_LEVEL2: + //PB_force_Reach2_flag = 1; + BSignal = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + + + + }else if(TP_Event == TOUCH_PANEL_BERR_EVENT){ + BSignal = BUTTON_RELEASE;//////////////BUTTON_INVALID; + } + } + + return BSignal; +} + +static Buttons_SignalType TouchButton_BntCheck(Buttons_ChType ChId) +{ + Buttons_SignalType BSignal = BUTTON_RELEASE; + //static uint8 TB_force_Reach2_flag = 0; + if(ChId < BTN_UP) + { + key_status[ChId].status = get_sensor_state(ChId); + if (QTM_KEY_STATE_DETECT == (key_status[ChId].status)) {//KEY_TOUCHED_MASK + //Touch detect + key_status[ChId].RunCycle++; + if(TP_RUNNING_ERROR_CYCLE <= key_status[ChId].RunCycle){ + key_status[ChId].RunCycle = TP_RUNNING_ERROR_CYCLE; + BSignal = BUTTON_RELEASE;//BUTTON_INVALID; + }else{ + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + //TB_force_Reach2_flag = 0; + BSignal = BUTTON_TOUCH; + case PANEL_PRESS_LEVEL1: + //if(TB_force_Reach2_flag == 1) + //{ + //BSignal = BUTTON_TOUCH_AND_PRESS; + // } + // else + //{ + BSignal = BUTTON_TOUCH; + //} + break; + case PANEL_PRESS_LEVEL2: + //TB_force_Reach2_flag = 1; + BSignal = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + } + } else { + //Touch No detect + key_status[ChId].RunCycle = 0x00; + } + } + return BSignal; +} + +static float32 GetSlide_Angle(float32 dx, float32 dy) +{ + return(atan2(dy, dx) * 180 / PI); +} + +/**************************************************************/ +// x X(y) +// ^ ^ +// | mapping | +// | =======> | +// | | +// y <----------|(0,0) X(-y)<-------|(0,0) +/*************************************************************/ +static void CheckSlide_Level(TP_SlideDirection_Enum SlideDir, uint8 AbsX, uint8 AbsY) +{ + switch(SlideDir) + { + case TP_SlideDirection_ShortUP: + case TP_SlideDirection_LongUP: + TouchSlideEvent.UpDown_SlideDistance = AbsY; + if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL1_DISTANCE && TouchSlideEvent.UpDown_SlideDistance <= SLIDE_UD_LEVEL2_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel1_UP; + } + else if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL2_DISTANCE && TouchSlideEvent.UpDown_SlideDistance <= SLIDE_UD_LEVEL3_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel2_UP; + } + else if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL3_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel3_UP; + } + else{ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel_NONE; + } + break; + case TP_SlideDirection_ShortDOWN: + case TP_SlideDirection_LongDOWN: + TouchSlideEvent.UpDown_SlideDistance = AbsY; + if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL1_DISTANCE && TouchSlideEvent.UpDown_SlideDistance <= SLIDE_UD_LEVEL2_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel1_DOWN; + } + else if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL2_DISTANCE && TouchSlideEvent.UpDown_SlideDistance <= SLIDE_UD_LEVEL3_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel2_DOWN; + } + else if(TouchSlideEvent.UpDown_SlideDistance > SLIDE_UD_LEVEL3_DISTANCE){ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel3_DOWN; + } + else{ + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel_NONE; + } + break; + default: + TouchSlideEvent.UpDown_SlideDistance = 0x00; + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel_NONE; + break; + } +} +static TP_SlideDirection_Enum GetSlide_Direction(uint8 startX, uint8 startY, uint8 endX, uint8 endY) +{ + TP_SlideDirection_Enum result = TP_SlideDirection_NONE; + sint32 CoordMapping_sx,CoordMapping_sy; + sint32 CoordMapping_ex,CoordMapping_ey; + uint16 absx,absy; + sint32 dy,dx; + float32 angle; + + CoordMapping_sx = (1u * (sint32)startX); + CoordMapping_sy = (-1u * (sint32)startY); + CoordMapping_ex = (1u * (sint32)endX); + CoordMapping_ey = (-1u * (sint32)(endY)); + dx = CoordMapping_ex - CoordMapping_sx; + dy = CoordMapping_ey - CoordMapping_sy; + + absx = abs(dx); + absy = abs(dy); + if(TouchSurface.Event == TOUCH_PANEL_MOVE_EVENT && (absx > SLIDE_LR_MIN_DISTANCE || absy > SLIDE_UD_MIN_DISTANCE) ) + { + /*Ignore small Slide*/ + angle = GetSlide_Angle(dx, dy); + if (angle >= -45.0 && angle < 45.0) + { + if(absx > SLIDE_LR_SHORT_DISTANCE_NUM){ + result = TP_SlideDirection_LongRIGHT; + }else{ + result = TP_SlideDirection_ShortRIGHT; + } + } + else if (angle >= 45.0 && angle < 135.0) + { + if(absy > SLIDE_UD_SHORT_DISTANCE_NUM){ + result = TP_SlideDirection_LongUP; + }else{ + result = TP_SlideDirection_ShortUP; + } + } else if (angle >= -135.0 && angle < -45.0) + { + if(absy > SLIDE_UD_SHORT_DISTANCE_NUM){ + result = TP_SlideDirection_LongDOWN; + }else{ + result = TP_SlideDirection_ShortDOWN; + } + } + else if ((angle >= 135.0 && angle <= 180.0) || (angle >= -180.0 && angle < -135.0)) + { + if(absx > SLIDE_LR_SHORT_DISTANCE_NUM){ + result = TP_SlideDirection_LongLEFT; + }else{ + result = TP_SlideDirection_ShortLEFT; + } + } + CheckSlide_Level(result, absx, absy); + } + + return result; +} + +#if 0 +uint8 KalmanFilter(uint8 inData, uint8 Dtype) +{ + static float32 kalman[2] = {0}; + static float32 p[2] = {10, 10}; + float32 q = 0.001; + float32 r = 0.001; + float32 kg = 0; + if(Dtype < 2) + { + p[Dtype] += q; + kg = p[Dtype] / ( p[Dtype] + r ); + kalman[Dtype] = kalman[Dtype] + (kg * (inData - kalman[Dtype])); + p[Dtype] = (1 - kg) * p[Dtype]; + } + return (uint8)kalman[Dtype]; +} +#endif + +struct Point { + float x; + float y; +}; + +// 判断一个点是否在三角形内部 +uint8_t point_in_triangle(struct Point p, struct Point p1, struct Point p2, struct Point p3) { + float s = p1.y * p3.x - p1.x * p3.y + (p3.y - p1.y) * p.x + (p1.x - p3.x) * p.y; + float t = p1.x * p2.y - p1.y * p2.x + (p1.y - p2.y) * p.x + (p2.x - p1.x) * p.y; + if ((s < 0) != (t < 0)) return 0; + float A = -p2.y * p3.x + p1.y * (p3.x - p2.x) + p1.x * (p2.y - p3.y) + p2.x * p3.y; + if (A < 0.0) { + s = -s; + t = -t; + A = -A; + } + return (s > 0 && t > 0 && (s + t) < A); +} + +// 判断一个点是否在四边形内部 +uint8_t point_in_quadrilateral(struct Point p, struct Point q1, struct Point q2, struct Point q3, struct Point q4) { + return point_in_triangle(p, q1, q2, q3) || point_in_triangle(p, q1, q3, q4); +} + +static void TouchPanel_XY_Convert(uint8 origin_x, uint8 origin_y) +{ +#define Y_OFFSET 40 +#define START_X 95 +#define START_Y 240 +#define END_X 255 +#define END_Y 197 + TouchXY_type start,end; + float32 k,b,y; + + uint8 temp_x,temp_y; + uint8 convert_x,convert_y; + float32 f_x; + temp_x = 255u - origin_y; + f_x = (((float32)temp_x)/(255.0f/160.0f));// 255u-95u + if(f_x - (uint32)(f_x) < 0.5f){ + convert_x = (uint8)f_x + 95u; + }else{ convert_x = (uint8)f_x + 1u + 95u;} + + temp_y = 255u - origin_x; + convert_y = temp_y; + /*******************************************/ + + start.x = START_X; + start.y = START_Y; + end.x = END_X; + end.y = END_Y; + + k = ((end.y - start.y)/(end.x - start.x)); + b = (start.y - k * start.x); + y = k*convert_x + b; + convert_y =(uint8)(((float32)temp_y * (y - Y_OFFSET))/255 + Y_OFFSET); + + Surface_Convert.convert_x = convert_x; //KalmanFilter(convert_x, 0); + Surface_Convert.convert_y = convert_y; //KalmanFilter(convert_y, 0); +} + + +extern void CanTx(t_can_handler can_handler, bool notif, uint32_t idtp, uint16_t len, t_can_data can_data); +//static uint16_t touch_delay = 500; + +void TouchPanel_MainFunction(void) +{ + uint8 index; + uint8 x1,y1, x2,y2, Temp_x,Temp_y; + uint8 touchEnd_flag = 0x00; + + uint8 voice_temp,voice_x,voice_y;//by kailong + uint8 pad_trig_x,pad_trig_y; + + uint8 count = 0; + + + static uint8 threshold_select_voice = 0; + static uint8 threshold_select_menu = 0; + static uint8 threshold_select_vol = 0; + static uint8 threshold_select_up = 0; + static uint8 threshold_select_down = 0; + static uint8 threshold_select_left = 0; + static uint8 threshold_select_right = 0; + static uint8 threshold_select_confirm = 0; + + #ifdef DEBUG_TEST + volatile uint8 button_touch = 0; + volatile uint8 touch_pannel = 0; + #endif + /* + if(Get_forcedetect_force_value() < 50 || Get_forcedetect_force_value()>2047) + { + if (touch_delay > 0) + { + touch_delay--; + } + else + { + PressState = 0; + return; + } + + } + else + { + PressState = 1; + touch_delay = 500; + } + */ + PressState = 1; + touch_process(); + + + //add by kailong + if(get_scroller_state(0) & TOUCH_ACTIVE) + { + voice_y = get_scroller_position(0x00); + if(voice_y>=10 && voice_y<=73) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 1; + threshold_select_voice = 1; + //} + }else + { + threshold_select_voice = 0; + } + if(voice_y>=103 && voice_y<=160) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 2; + threshold_select_vol = 1; + //} + }else + { + threshold_select_vol = 0; + } + if(voice_y>=190 && voice_y<=250) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 3; + threshold_select_menu = 1; + //} + }else + { + threshold_select_menu = 0; + } + + } + else + { + threshold_select_voice = 0; + threshold_select_menu = 0; + threshold_select_vol = 0; + } + /* + if(TouchButton_is_TouchActive(BTN_MENU1)==1) + { + if(CurrentPosition == 0xff) + { + CurrentPosition = 3; + threshold_select_menu=1; + } + } + else + { + threshold_select_menu=0; + } + + if(TouchButton_is_TouchActive(BTN_VOL1)==1) + { + if(CurrentPosition == 0xff) + { + CurrentPosition = 2; + threshold_select_vol=1; + } + } + else + { + threshold_select_vol=0; + } + */ + + //add by kailong + + + + + + if((TouchPanel_SurfaceStatus & TOUCH_ACTIVE) == 1) + { + struct Point Current_XY; + + struct Point Point_Up[4] = { + {76,0}, + {255,41}, + {206,87}, + {135,87}, + }; + + struct Point Point_Down[4] = { + {135,169}, + {206,169}, + {255,199}, + {106,255}, + }; + + struct Point Point_Left[4] = { + {76,21}, + {135,87}, + {135,169}, + {96,255}, + }; + + struct Point Point_Right[4] = { + {206,87}, + {255,48}, + {255,183}, + {206,169}, + }; + +#if 1 + struct Point Point_Confirm[4] = { + {140,92}, + {206,92}, + {206,164}, + {140,164}, + }; +#endif + //point_in_quadrilateral(Current_XY,Point_Up[0],Point_Up[1],Point_Up[2],Point_Up[3]) + + GetSurface_Position(&pad_trig_x, &pad_trig_y); + Current_XY.x = (float)pad_trig_x; + Current_XY.y = (float)pad_trig_y; + + + if(point_in_quadrilateral(Current_XY,Point_Up[0],Point_Up[1],Point_Up[2],Point_Up[3])) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 4; + K_Vibra_Trig=1; + threshold_select_up = 1; + Surface_Button = 1; + // } + } + else if(point_in_quadrilateral(Current_XY,Point_Down[0],Point_Down[1],Point_Down[2],Point_Down[3])) + { + // if(CurrentPosition == 0xff) + //{ + CurrentPosition = 5; + K_Vibra_Trig=1; + threshold_select_down = 1; + Surface_Button = 2; + //} + } + else if(point_in_quadrilateral(Current_XY,Point_Left[0],Point_Left[1],Point_Left[2],Point_Left[3])) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 6; + K_Vibra_Trig=1; + threshold_select_left = 1; + Surface_Button = 3; + //} + } + else if(point_in_quadrilateral(Current_XY,Point_Right[0],Point_Right[1],Point_Right[2],Point_Right[3])) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 7; + K_Vibra_Trig=1; + threshold_select_right = 1; + Surface_Button = 4; + //} + } + + else if(point_in_quadrilateral(Current_XY,Point_Confirm[0],Point_Confirm[1],Point_Confirm[2],Point_Confirm[3])) + //else if(((pad_trig_x>= 150) && (pad_trig_x<= 196)) && ((pad_trig_y>= 102) && (pad_trig_y<= 158))) + { + //if(CurrentPosition == 0xff) + //{ + CurrentPosition = 8; + K_Vibra_Trig=1; + threshold_select_confirm = 1; + Surface_Button = 5; + //} + } + + + + } + else + { + + K_Vibra_Trig=0; + threshold_select_up = 0; + threshold_select_down = 0; + threshold_select_left = 0; + threshold_select_right = 0; + threshold_select_confirm = 0; + Surface_Button = 0; + } + + //volatile uint8 g_Trig_Threshold=0; + //volatile uint8 g_Release_Threshold=0; + + + if(threshold_select_voice == 1 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button0_GetVoice1_Trig_Threshold(); + g_Release_Threshold=Button0_GetVoice1_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==1 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold= Button5_GetMenu1_Trig_Threshold(); + g_Release_Threshold= Button5_GetMenu1_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==1 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button3_GetVol1_Trig_Threshold(); + g_Release_Threshold= Button3_GetVol1_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==1 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button6_GetBTN_UP_Trig_Threshold(); + g_Release_Threshold= Button6_GetBTN_UP_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==1 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button7_GetBTN_DOWN_Trig_Threshold(); + g_Release_Threshold= Button7_GetBTN_DOWN_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==1 && threshold_select_right==0 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button8_GetBTN_LEFT_Trig_Threshold(); + g_Release_Threshold= Button8_GetBTN_LEFT_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==1 && threshold_select_confirm==0 ) + { + g_Trig_Threshold=Button9_GetBTN_RIGHT_Trig_Threshold(); + g_Release_Threshold= Button9_GetBTN_RIGHT_Release_Threshold(); + } + else if(threshold_select_voice == 0 && threshold_select_menu==0 && threshold_select_vol==0 && threshold_select_up==0 && threshold_select_down==0 && threshold_select_left==0 && threshold_select_right==0 && threshold_select_confirm==1 ) + { + g_Trig_Threshold=Button10_GetBTN_CONFIRM_Trig_Threshold(); + g_Release_Threshold= Button10_GetBTN_CONFIRM_Release_Threshold(); + } + else + { + //g_Trig_Threshold=Button10_GetBTN_CONFIRM_Trig_Threshold(); + //g_Release_Threshold= Button10_GetBTN_CONFIRM_Release_Threshold(); + } + + TouchPanel_PressLevel = TouchPanel_PressCheck(); + + + + //add by kailong + //static uint8 Voice_force_Reach2_flag = 0; + // static uint8 Vol_force_Reach2_flag = 0; + // static uint8 Menu_force_Reach2_flag = 0; + k_voice_touch_Sts = BUTTON_RELEASE; + k_vol_touch_Sts = BUTTON_RELEASE; + k_menu_touch_Sts = BUTTON_RELEASE; + voice_temp = get_scroller_state(0); + if(voice_temp & TOUCH_ACTIVE) + { + voice_y = get_scroller_position(0x00); + }else{ + voice_y = 0x00; + } + GetSurface_Position(&voice_x, NULL_PTR); + if(voice_y>=10&&voice_y<=73) + { + + + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + //Voice_force_Reach2_flag = 0; + k_voice_touch_Sts = BUTTON_TOUCH; + break; + case PANEL_PRESS_LEVEL1: + //if(Voice_force_Reach2_flag == 1) + // { + //k_voice_touch_Sts = BUTTON_TOUCH_AND_PRESS; + //} + //else + //{ + k_voice_touch_Sts = BUTTON_TOUCH; + //} + break; + case PANEL_PRESS_LEVEL2: + //Voice_force_Reach2_flag = 1; + k_voice_touch_Sts = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + + + } + else if(voice_y>=103&&voice_y<=160) + { + + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + //Vol_force_Reach2_flag = 0; + k_vol_touch_Sts = BUTTON_TOUCH; + break; + case PANEL_PRESS_LEVEL1: + //if(Vol_force_Reach2_flag == 1) + //{ + // k_vol_touch_Sts = BUTTON_TOUCH_AND_PRESS; + //} + //else + //{ + k_vol_touch_Sts = BUTTON_TOUCH; + //} + break; + case PANEL_PRESS_LEVEL2: + //Vol_force_Reach2_flag = 1; + k_vol_touch_Sts = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + + + } + else if(voice_y>=190&&voice_y<=250) + { + + switch (TouchPanel_PressLevel) + { + case PANEL_PRESS_LEVEL0: + //Menu_force_Reach2_flag = 0; + k_menu_touch_Sts = BUTTON_TOUCH; + break; + case PANEL_PRESS_LEVEL1: + //if(Menu_force_Reach2_flag == 1) + // { + // k_menu_touch_Sts = BUTTON_TOUCH_AND_PRESS; + //} + // else + // { + k_menu_touch_Sts = BUTTON_TOUCH; + // } + break; + case PANEL_PRESS_LEVEL2: + //Menu_force_Reach2_flag = 1; + k_menu_touch_Sts = BUTTON_TOUCH_AND_PRESS; + break; + default: + break; + } + + + } + + + //add by kailong + + if(measurement_done_touch == 1) + { + // process touch data + for(index = 0; index< DEF_NUM_CHANNELS; index++){ + sensor_signal[index] = get_sensor_node_signal(index); + sensor_reference[index] = get_sensor_node_reference(index); + } + TouchScroller.x_position = 0x00; + TouchPanel_ScrollerStatus = get_scroller_state(0); + if(TouchPanel_ScrollerStatus & TOUCH_ACTIVE) + { + TouchScroller.y_position = get_scroller_position(0x00); + }else{ + TouchScroller.y_position = 0x00; + } + TouchPanel_SurfaceStatus = get_surface_status(); + if (TouchPanel_SurfaceStatus & TOUCH_ACTIVE) + { + Temp_x = get_surface_position(HOR_POS); + Temp_y = get_surface_position(VER_POS); + TouchPanel_XY_Convert(Temp_x, Temp_y); + TouchSurface.x_position = Surface_Convert.convert_x; + TouchSurface.y_position = Surface_Convert.convert_y; + + if(TouchSurface.end_x_pos == 0x00 && TouchSurface.end_y_pos == 0x00){ + TouchSurface.end_x_pos = TouchSurface.x_position; + TouchSurface.end_y_pos = TouchSurface.y_position; + } + + if(TouchSurface.Event == TOUCH_PANEL_NONE_EVENT){ + x1 = TouchSurface.end_x_pos; y1 = TouchSurface.end_y_pos; + x2 = TouchSurface.x_position; y2 = TouchSurface.y_position; + }else{ + x1 = TouchSurface.origin_x_pos; y1 = TouchSurface.origin_y_pos; + x2 = TouchSurface.x_position; y2 = TouchSurface.y_position; + } + + TouchSurface.CheckCycle++; + TouchSurface.TouchCycle++; + if((abs(x2-x1) < TP_ERR_RANGE) && (abs(y2-y1) < TP_ERR_RANGE)) + { + // sampling error <= +- TP_ERR_RANGE + if (TouchSurface.CheckCycle >= TP_DEBOUNCE_CYCLE) + { + if(TOUCH_PANEL_NONE_EVENT == TouchSurface.Event){ + TouchSurface.origin_x_pos = (x1+x2)/2; + TouchSurface.origin_y_pos = (y1+y2)/2; + TouchSurface.Event = TOUCH_PANEL_PRESS_EVENT; + } + TouchSurface.CheckCycle = TP_DEBOUNCE_CYCLE; + } + TouchSurface.end_x_pos = x2; + TouchSurface.end_y_pos = y2; + } + else + { + if(TOUCH_PANEL_PRESS_EVENT == TouchSurface.Event || TOUCH_PANEL_MOVE_EVENT == TouchSurface.Event) + { + TouchSurface.Event = TOUCH_PANEL_MOVE_EVENT; + }else{ + TouchSurface.Event = TOUCH_PANEL_NONE_EVENT; + TouchSurface.origin_x_pos = 0x00; + TouchSurface.origin_y_pos = 0x00; + } + TouchSurface.end_x_pos = x2; + TouchSurface.end_y_pos = y2; + } + } + else + { + x1 = TouchSurface.origin_x_pos; y1 = TouchSurface.origin_y_pos; + x2 = TouchSurface.end_x_pos; y2 = TouchSurface.end_y_pos; + if(TOUCH_PANEL_MOVE_EVENT == TouchSurface.Event) + { + if((abs(x2-x1) < TP_ERR_RANGE) && (abs(y2-y1) < TP_ERR_RANGE)) + { + TouchSurface.Event = TOUCH_PANEL_RES_EVENT; + }else{ + TouchSurface.Event = TOUCH_PANEL_MOVE_EVENT; + TouchSlideEvent.Direction = GetSlide_Direction(x1, y1, x2, y2); + if(TouchSlideEvent.Direction != TP_SlideDirection_NONE){ + TouchSlideEvent.keep_cycle = SLIDE_CAN_EVENT_KEEP_CYCLE; + TouchSlideEvent.Event = TRUE; + } + } + } + else if(TOUCH_PANEL_PRESS_EVENT == TouchSurface.Event) + { + //do nothing + } + else + { + TouchSurface.Event = TOUCH_PANEL_NONE_EVENT; + } + + TouchSurface.end_x_pos = 0x00; + TouchSurface.end_y_pos = 0x00; + TouchSurface.CheckCycle = 0x00; + TouchSurface.origin_x_pos = 0x00; + TouchSurface.origin_y_pos = 0x00; + TouchSurface.x_position = 0; + TouchSurface.y_position = 0; + TouchSurface.TouchCycle = 0; + Surface_Convert.convert_x = 0x00; + Surface_Convert.convert_y = 0x00; + touchEnd_flag = 0x01; + } + + if(TouchSurface.TouchCycle >= TP_RUNNING_ERROR_CYCLE){ + TouchSurface.TouchCycle = TP_RUNNING_ERROR_CYCLE; + TouchSurface.Event = TOUCH_PANEL_BERR_EVENT; + } + + + switch(CurrentPosition) + { + case 1:{ + Buttons_Signal[BTN_VOICE1] = TouchButton_BntCheck(BTN_VOICE1); + if(Buttons_Signal[BTN_VOICE1] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 2:{ + Buttons_Signal[BTN_VOL1] = TouchButton_BntCheck(BTN_VOL1); + if(Buttons_Signal[BTN_VOL1] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 3:{ + Buttons_Signal[BTN_MENU1] = TouchButton_BntCheck(BTN_MENU1); + if(Buttons_Signal[BTN_MENU1] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 4:{ + Buttons_Signal[BTN_UP] = TouchSurface_BntCheck(BTN_UP, 1); + if(Buttons_Signal[BTN_UP] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 5:{ + Buttons_Signal[BTN_DOWN] = TouchSurface_BntCheck(BTN_DOWN, 1); + if(Buttons_Signal[BTN_DOWN] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 6:{ + Buttons_Signal[BTN_LEFT] = TouchSurface_BntCheck(BTN_LEFT, 1); + if(Buttons_Signal[BTN_LEFT] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 7:{ + Buttons_Signal[BTN_RIGHT] = TouchSurface_BntCheck(BTN_RIGHT, 1); + if(Buttons_Signal[BTN_RIGHT] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + case 8:{ + Buttons_Signal[BTN_CONFIRM] = TouchSurface_BntCheck(BTN_CONFIRM, 1); + if(Buttons_Signal[BTN_CONFIRM] >= BUTTON_TOUCH) + { + break; + }else + { + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + } + break; + } + default:{ + for(index = 0; index< BTN_MAX_CH_NUM; index++) + { + if(index< (BTN_MAX_CH_NUM - 5U)){ + Buttons_Signal[index] = TouchButton_BntCheck(index); + }else{ + Buttons_Signal[index] = TouchSurface_BntCheck(index, 1); + } + + if(Buttons_Signal[index] < BUTTON_TOUCH) + { + count++; + } + } + break; + } + } + + if(count == 10) + { + CurrentPosition = 0xff; + } + + if(touchEnd_flag != 0x00){ + TouchSurface.Event = TOUCH_PANEL_NONE_EVENT; + } + +#ifdef DEBUG_TEST + for(index = 0; index< 3; index++) + { + if(Buttons_Signal[index] != BUTTON_RELEASE) + { + button_touch++; + } + //g_key_status[index] |= get_sensor_state(index) & KEY_TOUCHED_MASK; + } + + for(index = 3; index< 8; index++) + { + if(Buttons_Signal[index] != BUTTON_RELEASE) + { + touch_pannel++; + } + } + + if(button_touch == 1 || touch_pannel > 0) + { + if(button_touch == 1) + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)1); + else + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)400); + button_touch = 0; + }else{ + (void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, (uint16_t)6000); + } +#endif + measurement_done_touch = 0; + } + + if(TouchSlideEvent.Event == TRUE) + { + if(TouchSlideEvent.keep_cycle != 0x00){ + TouchSlideEvent.keep_cycle--; + } + if(TouchSlideEvent.keep_cycle == 0x00){ + TouchSlideEvent.Direction = TP_SlideDirection_NONE; + TouchSlideEvent.UpDown_SlideLevel = TP_SlideLevel_NONE; + TouchSlideEvent.Event = FALSE; + } + } + if(TouchSurface.Event == TOUCH_PANEL_BERR_EVENT) + { + TouchSurface.Event = TOUCH_PANEL_NONE_EVENT; + } + + + +#if 0 + if (TouchPanel_SurfaceStatus & TOUCH_ACTIVE) + { + K_Vibra_Trig=1; + } + else + { + K_Vibra_Trig=0; + } +#endif + + //uint8_t Two_Finger_happen_flag = 0; + //uint8_t Two_Finger_release_count = 0; + //uint8_t Two_Finger_Vibra_req = 0; + + + + if(Vibra_force_level == 2 && last_Vibra_force_level != 2 && + ((Two_Finger_Y_count<=4 && Y_count == Two_Finger_Y_count)&&(Two_Finger_X_count<=4 && X_count == Two_Finger_X_count)) + ) + { + Over3N_vibra_req = 1; + Below1P5N_vibra_req = 0; + + } + else if(Vibra_force_level == 0 && last_Vibra_force_level != 0) + { + Below1P5N_vibra_req = 1; + Over3N_vibra_req = 0; + } + last_Vibra_force_level=Vibra_force_level; + //(K_Vibra_Trig==1||k_voice_touch_Sts!=0||TouchButton_is_TouchActive(BTN_MENU1)==1||TouchButton_is_TouchActive(BTN_VOL1)==1)&& + if(Vibra_force_level==2) + { + Reach2_flag=1; + } + //TouchButton_is_TouchActive(BTN_MENU1)==1 //TouchButton_is_TouchActive(BTN_VOL1)==1 + if((K_Vibra_Trig==1||k_voice_touch_Sts!=0||k_menu_touch_Sts!=0||k_vol_touch_Sts!=0)&&Over3N_vibra_req == 1 ) + { + Touch_Flag = TOUCH_KET_ON; + speeker_Tig_Once(49, UDS_Vibration_Gain); + Over3N_vibra_req = 0; + } + else if(Below1P5N_vibra_req ==1 && Reach2_flag==1) // + { + if(TOUCH_KET_ON == Touch_Flag) + { + speeker_Tig_Once(49, UDS_Vibration_Gain); + Touch_Flag = TOUCH_KET_OFF; + } + Below1P5N_vibra_req = 0; + Reach2_flag = 0; + } + +#if 0 + if((K_Vibra_Trig==1&&Vibra_force_level == 2 && last_Vibra_force_level != 2) || + (K_Vibra_Trig==1&&Vibra_force_level != 1 && last_Vibra_force_level == 1)) + { + speeker_Tig_Once(49, SA51024_STRENGTH_LEVEL0); + } + last_Vibra_force_level=Vibra_force_level; +#endif +} diff --git a/firmware/src/TouchPanel/TouchPanel.h b/firmware/src/TouchPanel/TouchPanel.h new file mode 100644 index 0000000..8008240 --- /dev/null +++ b/firmware/src/TouchPanel/TouchPanel.h @@ -0,0 +1,170 @@ +#ifndef TOUCH_PANEL_H +#define TOUCH_PANEL_H +#include "Std_Types.h" +#include "forceSnsr/forcedetect.h" + +#define PI 3.1415926f + +#define TP_ERR_RANGE 15 +#define TP_DEBOUNCE_CYCLE 1 +#define TP_RUNNING_ERROR_CYCLE 60000 + +#define SLIDE_LR_MIN_DISTANCE (30) +#define SLIDE_LR_SHORT_DISTANCE_NUM 90 +#define SLIDE_UD_MIN_DISTANCE (1.59*SLIDE_LR_MIN_DISTANCE) +#define SLIDE_UD_SHORT_DISTANCE_NUM 140 + + +#define SLIDE_UD_LEVEL1_DISTANCE SLIDE_UD_MIN_DISTANCE +#define SLIDE_UD_LEVEL2_DISTANCE (SLIDE_UD_MIN_DISTANCE + 69) //((SLIDE_UD_MIN_DISTANCE+SLIDE_UD_SHORT_DISTANCE_NUM)/2) +#define SLIDE_UD_LEVEL3_DISTANCE (SLIDE_UD_LEVEL2_DISTANCE + 69)//SLIDE_UD_SHORT_DISTANCE_NUM + +#define SLIDE_CAN_EVENT_KEEP_CYCLE 30//2MS*30 + +#define TOUCH_SCREEN_CONTACT_AREA_INVALID_NUM 350 +#define TOUCH_KET_ON 1 +#define TOUCH_KET_OFF 0 + + +extern uint16 Over3N_vibra_req; +extern uint16 Below1P5N_vibra_req; + + + +typedef enum +{ + TP_SlideDirection_NONE = 0, + TP_SlideDirection_ShortUP, + TP_SlideDirection_LongUP, + TP_SlideDirection_ShortDOWN, + TP_SlideDirection_LongDOWN, + TP_SlideDirection_ShortLEFT, + TP_SlideDirection_LongLEFT, + TP_SlideDirection_ShortRIGHT, + TP_SlideDirection_LongRIGHT +} TP_SlideDirection_Enum; + + +/*0 slip idle 1 decrease ,2 increase , 3 decrease double , 4 increase double ,5 decrease third, 6 increase third*/ +typedef enum +{ + TP_SlideLevel_NONE = 0, + TP_SlideLevel1_DOWN, + TP_SlideLevel1_UP, + TP_SlideLevel2_DOWN, + TP_SlideLevel2_UP, + TP_SlideLevel3_DOWN, + TP_SlideLevel3_UP +} TP_SlideLevel_Enum; + + +typedef enum{ + TOUCH_PANEL_NONE_EVENT = 0, + TOUCH_PANEL_PRESS_EVENT, + TOUCH_PANEL_RES_EVENT, + TOUCH_PANEL_MOVE_EVENT, + TOUCH_PANEL_BERR_EVENT +}TouchPanel_EventType; + +typedef enum{ + PANEL_PRESS_LEVEL0 = 0,/*< 1N*/ + PANEL_PRESS_LEVEL1,/*1N <= X < 3N*/ + PANEL_PRESS_LEVEL2 /*>= 3N*/ +}PanelPress_LevelType; + + + + + + + + + + +typedef struct{ + boolean Event; + uint32 keep_cycle; + TP_SlideDirection_Enum Direction; + uint8 UpDown_SlideDistance; + TP_SlideLevel_Enum UpDown_SlideLevel; +}TouchSlideEvent_type; + +typedef struct{ + uint8 x_position; + uint8 y_position; + uint8 origin_x_pos; + uint8 origin_y_pos; + uint8 end_x_pos; + uint8 end_y_pos; + + TouchPanel_EventType Event; + uint32 CheckCycle; + uint32 TouchCycle; +}TouchSurface_type; + +typedef struct{ + uint8 x_position; + uint8 y_position; +}TouchScroller_type; + +typedef struct{ + uint8 convert_x; + uint8 convert_y; +}TouchSurface_Convert_type; + +typedef struct{ + float32 x; + float32 y; +}TouchXY_type; + +typedef struct{ + uint16 status; + uint32 RunCycle; +}TouchButtons_type; + +typedef enum{ + BTN_VOICE1 = 0,//MENU1 pin + //BTN_VOICE2,//MENU2 //not used + BTN_VOL2,//VOL1 + BTN_VOL1,//VOL2 + BTN_MENU2,//VOICE1 + BTN_MENU1,//VOICE1 + /****************/ + BTN_UP, + BTN_DOWN, + BTN_LEFT, + BTN_RIGHT, + BTN_CONFIRM, + /****************/ + BTN_MAX_CH_NUM +}Buttons_ChType; + +typedef enum{ + BUTTON_RELEASE = 0,//notcative + BUTTON_TOUCH, + BUTTON_TOUCH_AND_PRESS, + //BUTTON_INVALID +}Buttons_SignalType; + +#define GET_TouchPanel_is_Press Get_forcedetect_btn_is_press_state + +extern volatile uint8 measurement_done_touch; +extern volatile uint8 k_voice_touch_Sts,k_menu_touch_Sts,k_vol_touch_Sts; +extern volatile uint8 Vibra_force_level; +extern volatile uint8 last_Vibra_force_level; + +extern uint8 Vibra_PressCheck(void); + +void TouchPanel_init(void); +void GetSurface_Position(uint8 *x, uint8 *y); +void GetScroller_Position(uint8 *x, uint8 *y); +Buttons_SignalType TouchPanel_BtnSignalRead(Buttons_ChType ChId); +void TouchPanel_MainFunction(void); +TP_SlideDirection_Enum TouchPanel_SlideEventRead(void); +Buttons_SignalType TouchSurface_XY_StsRead(void); +TP_SlideLevel_Enum TouchPanel_SlideUpDownLevelRead(void); +PanelPress_LevelType TouchPanel_PressLevelRead(void); +boolean TouchSurface_is_TouchActive(void); +boolean TouchButton_is_TouchActive(Buttons_ChType BtId); +boolean TouchScroller_is_TouchActive(void); +#endif \ No newline at end of file diff --git a/firmware/src/config/mcal/ATSAME51J19A.ld b/firmware/src/config/mcal/ATSAME51J19A.ld new file mode 100644 index 0000000..bbb1de8 --- /dev/null +++ b/firmware/src/config/mcal/ATSAME51J19A.ld @@ -0,0 +1,271 @@ +/*-------------------------------------------------------------------------- + * MPLAB XC32 Compiler - ATSAME51J19A linker script + * + * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* + * Define the __XC32_RESET_HANDLER_NAME macro on the command line when you + * want to use a different name for the Reset Handler function. + */ +#ifndef __XC32_RESET_HANDLER_NAME +#define __XC32_RESET_HANDLER_NAME Reset_Handler +#endif /* __XC32_RESET_HANDLER_NAME */ + +/* Set the entry point in the ELF file. Once the entry point is in the ELF + * file, you can then use the --write-sla option to xc32-bin2hex to place + * the address into the hex file using the SLA field (RECTYPE 5). This hex + * record may be useful for a bootloader that needs to determine the entry + * point to the application. + */ +ENTRY(__XC32_RESET_HANDLER_NAME) + +/************************************************************************* + * Memory-Region Macro Definitions + * The XC32 linker preprocesses linker scripts. You may define these + * macros in the MPLAB X project properties or on the command line when + * calling the linker via the xc32-gcc shell. + *************************************************************************/ + +#ifndef ROM_ORIGIN +# define ROM_ORIGIN 0x0 +#endif +#ifndef ROM_LENGTH +# define ROM_LENGTH 0x80000 +#elif (ROM_LENGTH > 0x80000) +# error ROM_LENGTH is greater than the max size of 0x80000 +#endif +#ifndef RAM_ORIGIN +# define RAM_ORIGIN 0x20000000 +#endif +#ifndef RAM_LENGTH +# define RAM_LENGTH 0x30000 +#elif (RAM_LENGTH > 0x30000) +# error RAM_LENGTH is greater than the max size of 0x30000 +#endif +#ifndef TCM_ORIGIN +# define TCM_ORIGIN 0x3000000 +#endif +#ifndef __XC32_TCM_LENGTH +# define __XC32_TCM_LENGTH 0x0 +#elif (defined(__XC32_TCM_LENGTH) && __XC32_TCM_LENGTH != 0x0 && __XC32_TCM_LENGTH != 0x800 && __XC32_TCM_LENGTH != 0xc00 && __XC32_TCM_LENGTH != 0x1000) +# warning Non-standard ITCM length, using default 0x1000 +# undef __XC32_TCM_LENGTH +# define __XC32_TCM_LENGTH 0x1000 +#endif +#ifndef BKUPRAM_ORIGIN +# define BKUPRAM_ORIGIN 0x47000000 +#endif +#ifndef BKUPRAM_LENGTH +# define BKUPRAM_LENGTH 0x2000 +#elif (BKUPRAM_LENGTH > 0x2000) +# error BKUPRAM_LENGTH is greater than the max size of 0x2000 +#endif + + +/************************************************************************* + * Memory-Region Definitions + * The MEMORY command describes the location and size of blocks of memory + * on the target device. The command below uses the macros defined above. + *************************************************************************/ +MEMORY +{ + rom (LRX) : ORIGIN = 0x18000, LENGTH = 0x40000 + /* rom (LRX) : ORIGIN = ROM_ORIGIN, LENGTH = ROM_LENGTH */ + ram (WX!R) : ORIGIN = RAM_ORIGIN+16, LENGTH = RAM_LENGTH-16 + tcm (WX) : ORIGIN = TCM_ORIGIN, LENGTH = __XC32_TCM_LENGTH + bkupram : ORIGIN = BKUPRAM_ORIGIN, LENGTH = BKUPRAM_LENGTH + config_00804000 : ORIGIN = 0x00804000, LENGTH = 0x4 + config_00804008 : ORIGIN = 0x00804008, LENGTH = 0x4 + config_00804004 : ORIGIN = 0x00804004, LENGTH = 0x4 + +} +/************************************************************************* + * Output region definitions. + * CODE_REGION defines the output region for .text/.rodata. + * DATA_REGION defines the output region for .data/.bss + * VECTOR_REGION defines the output region for .vectors. + * + * CODE_REGION defaults to 'rom', if rom is present (non-zero length), + * and 'ram' otherwise. + * DATA_REGION defaults to 'ram', which must be present. + * VECTOR_REGION defaults to CODE_REGION, unless 'boot_rom' is present. + */ +#ifndef CODE_REGION +# if ROM_LENGTH > 0 +# define CODE_REGION rom +# else +# define CODE_REGION ram +# endif +#endif +#ifndef DATA_REGION +# define DATA_REGION ram +#endif +#ifndef VECTOR_REGION +# define VECTOR_REGION CODE_REGION +#endif + +__rom_end = ORIGIN(rom) + LENGTH(rom); +__ram_end = ORIGIN(ram) + LENGTH(ram); + +/************************************************************************* + * Section Definitions - Map input sections to output sections + *************************************************************************/ +SECTIONS +{ + .config_00804000 : { + KEEP(*(.config_00804000)) + } > config_00804000 + .config_00804008 : { + KEEP(*(.config_00804008)) + } > config_00804008 + .config_00804004 : { + KEEP(*(.config_00804004)) + } > config_00804004 + + /* + * The linker moves the .vectors section into itcm when itcm is + * enabled via the -mitcm option, but only when this .vectors output + * section exists in the linker script. + */ + .vectors : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.* .vectors_default .vectors_default.*)) + KEEP(*(.isr_vector)) + KEEP(*(.reset*)) + KEEP(*(.after_vectors)) + } > VECTOR_REGION + /* + * Code Sections - Note that standard input sections such as + * *(.text), *(.text.*), *(.rodata), & *(.rodata.*) + * are not mapped here. The best-fit allocator locates them, + * so that input sections may flow around absolute sections + * as needed. + */ + .text : + { + . = ALIGN(4); + *(.glue_7t) *(.glue_7) + *(.gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > CODE_REGION + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > CODE_REGION + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + + /* + * Align here to ensure that the .bss section occupies space up to + * _end. Align after .bss to ensure correct alignment even if the + * .bss section disappears because there are no input sections. + * + * Note that input sections named .bss* are no longer mapped here. + * The best-fit allocator locates them, so that they may flow + * around absolute sections as needed. + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = . ; + _szero = .; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = . ; + _ezero = .; + } > DATA_REGION + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; + + .bkupram_bss : + { + *(.bkupram_bss .bkupram_bss.*) + *(.pbss .pbss.*) + } > bkupram +} + diff --git a/firmware/src/config/mcal/definitions.h b/firmware/src/config/mcal/definitions.h new file mode 100644 index 0000000..05230f8 --- /dev/null +++ b/firmware/src/config/mcal/definitions.h @@ -0,0 +1,150 @@ +/******************************************************************************* + System Definitions + + File Name: + definitions.h + + Summary: + project system definitions. + + Description: + This file contains the system-wide prototypes and definitions for a project. + + *******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +//DOM-IGNORE-END + +#ifndef DEFINITIONS_H +#define DEFINITIONS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include +#include +#include +#include "peripheral/nvmctrl/plib_nvmctrl.h" +#include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" +#include "peripheral/evsys/plib_evsys.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" +#include "peripheral/can/plib_can1.h" +#include "peripheral/port/plib_port.h" +#include "peripheral/clock/plib_clock.h" +#include "peripheral/nvic/plib_nvic.h" +#include "peripheral/systick/plib_systick.h" +#include "peripheral/wdt/plib_wdt.h" +#include "peripheral/cmcc/plib_cmcc.h" +#include "touch/touch.h" +#include "peripheral/rtc/plib_rtc.h" +#include "peripheral/tc/plib_tc0.h" +#include "peripheral/dac/plib_dac.h" +#include "peripheral/tcc/plib_tcc0.h" +#include "peripheral/adc/plib_adc0.h" +#include "peripheral/adc/plib_adc1.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +/* CPU clock frequency */ +#define CPU_CLOCK_FREQUENCY 120000000 + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* System Initialization Function + + Function: + void SYS_Initialize( void *data ) + + Summary: + Function that initializes all modules in the system. + + Description: + This function initializes all modules in the system, including any drivers, + services, middleware, and applications. + + Precondition: + None. + + Parameters: + data - Pointer to the data structure containing any data + necessary to initialize the module. This pointer may + be null if no data is required and default initialization + is to be used. + + Returns: + None. + + Example: + + SYS_Initialize ( NULL ); + + while ( true ) + { + SYS_Tasks ( ); + } + + + Remarks: + This function will only be called once, after system reset. +*/ + +void SYS_Initialize( void *data ); + +/* Nullify SYS_Tasks() if only PLIBs are used. */ +#define SYS_Tasks() + +// ***************************************************************************** +// ***************************************************************************** +// Section: extern declarations +// ***************************************************************************** +// ***************************************************************************** + + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* DEFINITIONS_H */ +/******************************************************************************* + End of File +*/ + diff --git a/firmware/src/config/mcal/device.h b/firmware/src/config/mcal/device.h new file mode 100644 index 0000000..36c2ad1 --- /dev/null +++ b/firmware/src/config/mcal/device.h @@ -0,0 +1,65 @@ +/******************************************************************************* + Device Header File + + Company: + Microchip Technology Inc. + + File Name: + device.h + + Summary: + This file includes the selected device from within the project. + The device will provide access to respective device packs. + + Description: + None + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_H +#define DEVICE_H + +#pragma GCC diagnostic push +#ifndef __cplusplus +#pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#ifndef DONT_USE_PREDEFINED_CORE_HANDLERS + #define DONT_USE_PREDEFINED_CORE_HANDLERS +#endif //DONT_USE_PREDEFINED_CORE_HANDLERS +#ifndef DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#endif //DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#include "same51j19a.h" +#pragma GCC diagnostic pop +#include "device_cache.h" +#include "toolchain_specifics.h" + +#endif //DEVICE_H diff --git a/firmware/src/config/mcal/device_cache.h b/firmware/src/config/mcal/device_cache.h new file mode 100644 index 0000000..891f829 --- /dev/null +++ b/firmware/src/config/mcal/device_cache.h @@ -0,0 +1,94 @@ +/******************************************************************************* + Cortex-M L1 Cache Header + + File Name: + device_cache.h + + Summary: + Preprocessor definitions to provide L1 Cache control. + + Description: + An MPLAB PLIB or Project can include this header to perform cache cleans, + invalidates etc. For the DCache and ICache. + + Remarks: + This header should not define any prototypes or data definitions, or + include any files that do. The file only provides macro definitions for + build-time. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_CACHE_H +#define DEVICE_CACHE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section Includes other configuration headers necessary to completely + define this configuration. +*/ + +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: L1 Cache Configuration +// ***************************************************************************** +// ***************************************************************************** + + +#define ICACHE_ENABLE() +#define ICACHE_DISABLE() +#define ICACHE_INVALIDATE() + +#define DCACHE_ENABLE() +#define DCACHE_DISABLE() +#define DCACHE_INVALIDATE() +#define DCACHE_CLEAN() +#define DCACHE_CLEAN_INVALIDATE() +#define DCACHE_CLEAN_BY_ADDR(addr,sz) +#define DCACHE_INVALIDATE_BY_ADDR(addr,sz) +#define DCACHE_CLEAN_INVALIDATE_BY_ADDR(addr,sz) + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif // #ifndef DEVICE_CACHE_H diff --git a/firmware/src/config/mcal/device_vectors.h b/firmware/src/config/mcal/device_vectors.h new file mode 100644 index 0000000..f27cf75 --- /dev/null +++ b/firmware/src/config/mcal/device_vectors.h @@ -0,0 +1,223 @@ +/******************************************************************************* + Cortex-M device vectors file + + Company: + Microchip Technology Inc. + + File Name: + device_vectors.h + + Summary: + Harmony3 device handler structure for cortex-M devices + + Description: + This file contains Harmony3 device handler structure for cortex-M devices + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_VECTORS_H +#define DEVICE_VECTORS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +/* Function pointer type for vector handlers */ +typedef void (*pfn_handler_t)(void); + +/* Structure defining device vector types */ +typedef struct H3DeviceVectorsTag +{ + /* Stack pointer */ + uint32_t* pvStack; + + /* CORTEX-M4 handlers */ + pfn_handler_t pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + pfn_handler_t pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + pfn_handler_t pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + pfn_handler_t pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + pfn_handler_t pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + pfn_handler_t pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + pfn_handler_t pfnReservedC9; + pfn_handler_t pfnReservedC8; + pfn_handler_t pfnReservedC7; + pfn_handler_t pfnReservedC6; + pfn_handler_t pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + pfn_handler_t pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + pfn_handler_t pfnReservedC3; + pfn_handler_t pfnPendSV_Handler; /* -2 Pendable request for system service */ + pfn_handler_t pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + pfn_handler_t pfnPM_Handler; /* 0 Power Manager */ + pfn_handler_t pfnMCLK_Handler; /* 1 Main Clock */ + pfn_handler_t pfnOSCCTRL_XOSC0_Handler; /* 2 External Oscillator 0 */ + pfn_handler_t pfnOSCCTRL_XOSC1_Handler; /* 3 External Oscillator 1 */ + pfn_handler_t pfnOSCCTRL_DFLL_Handler; /* 4 Digital Frequency Locked Loop */ + pfn_handler_t pfnOSCCTRL_DPLL0_Handler; /* 5 Digital Phase Locked Loop 0 */ + pfn_handler_t pfnOSCCTRL_DPLL1_Handler; /* 6 Digital Phase Locked Loop 1 */ + pfn_handler_t pfnOSC32KCTRL_Handler; /* 7 32Khz Oscillator Controller */ + pfn_handler_t pfnSUPC_OTHER_Handler; /* 8 Suppyly controller */ + pfn_handler_t pfnSUPC_BODDET_Handler; /* 9 Brown Out Detection */ + pfn_handler_t pfnWDT_Handler; /* 10 Watch Dog Timer */ + pfn_handler_t pfnRTC_Handler; /* 11 Real Time Counter */ + pfn_handler_t pfnEIC_EXTINT_0_Handler; /* 12 EIC Channel 0 */ + pfn_handler_t pfnEIC_EXTINT_1_Handler; /* 13 EIC Channel 1 */ + pfn_handler_t pfnEIC_EXTINT_2_Handler; /* 14 EIC Channel 2 */ + pfn_handler_t pfnEIC_EXTINT_3_Handler; /* 15 EIC Channel 3 */ + pfn_handler_t pfnEIC_EXTINT_4_Handler; /* 16 EIC Channel 4 */ + pfn_handler_t pfnEIC_EXTINT_5_Handler; /* 17 EIC Channel 5 */ + pfn_handler_t pfnEIC_EXTINT_6_Handler; /* 18 EIC Channel 6 */ + pfn_handler_t pfnEIC_EXTINT_7_Handler; /* 19 EIC Channel 7 */ + pfn_handler_t pfnEIC_EXTINT_8_Handler; /* 20 EIC Channel 8 */ + pfn_handler_t pfnEIC_EXTINT_9_Handler; /* 21 EIC Channel 9 */ + pfn_handler_t pfnEIC_EXTINT_10_Handler; /* 22 EIC Channel 10 */ + pfn_handler_t pfnEIC_EXTINT_11_Handler; /* 23 EIC Channel 11 */ + pfn_handler_t pfnEIC_EXTINT_12_Handler; /* 24 EIC Channel 12 */ + pfn_handler_t pfnEIC_EXTINT_13_Handler; /* 25 EIC Channel 13 */ + pfn_handler_t pfnEIC_EXTINT_14_Handler; /* 26 EIC Channel 14 */ + pfn_handler_t pfnEIC_EXTINT_15_Handler; /* 27 EIC Channel 15 */ + pfn_handler_t pfnFREQM_Handler; /* 28 Frequency Meter */ + pfn_handler_t pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller */ + pfn_handler_t pfnNVMCTRL_1_Handler; /* 30 NVMCTRL SmartEEPROM Interrupts */ + pfn_handler_t pfnDMAC_0_Handler; /* 31 DMA Channel 0 */ + pfn_handler_t pfnDMAC_1_Handler; /* 32 DMA Channel 1 */ + pfn_handler_t pfnDMAC_2_Handler; /* 33 DMA Channel 2 */ + pfn_handler_t pfnDMAC_3_Handler; /* 34 DMA Channel 3 */ + pfn_handler_t pfnDMAC_OTHER_Handler; /* 35 DMA Channel 4..X */ + pfn_handler_t pfnEVSYS_0_Handler; /* 36 Event System Channel 0 */ + pfn_handler_t pfnEVSYS_1_Handler; /* 37 Event System Channel 1 */ + pfn_handler_t pfnEVSYS_2_Handler; /* 38 Event System Channel 2 */ + pfn_handler_t pfnEVSYS_3_Handler; /* 39 Event System Channel 3 */ + pfn_handler_t pfnEVSYS_OTHER_Handler; /* 40 Event System Channel 4..X */ + pfn_handler_t pfnPAC_Handler; /* 41 Peripheral Access Controller */ + pfn_handler_t pfnReserved42; + pfn_handler_t pfnReserved43; + pfn_handler_t pfnReserved44; + pfn_handler_t pfnRAMECC_Handler; /* 45 RAM Error Correction Code */ + pfn_handler_t pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 */ + pfn_handler_t pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 */ + pfn_handler_t pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 */ + pfn_handler_t pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface 3 */ + pfn_handler_t pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 */ + pfn_handler_t pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 */ + pfn_handler_t pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 */ + pfn_handler_t pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface 4 */ + pfn_handler_t pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 */ + pfn_handler_t pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 */ + pfn_handler_t pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 */ + pfn_handler_t pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface 5 */ + pfn_handler_t pfnReserved70; + pfn_handler_t pfnReserved71; + pfn_handler_t pfnReserved72; + pfn_handler_t pfnReserved73; + pfn_handler_t pfnReserved74; + pfn_handler_t pfnReserved75; + pfn_handler_t pfnReserved76; + pfn_handler_t pfnReserved77; + pfn_handler_t pfnCAN0_Handler; /* 78 Controller Area Network 0 */ + pfn_handler_t pfnCAN1_Handler; /* 79 Controller Area Network 1 */ + pfn_handler_t pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus */ + pfn_handler_t pfnUSB_SOF_HSOF_Handler; /* 81 USB Start of Frame */ + pfn_handler_t pfnUSB_TRCPT0_Handler; /* 82 USB Transfer Complete 0 */ + pfn_handler_t pfnUSB_TRCPT1_Handler; /* 83 USB Transfer Complete 1 */ + pfn_handler_t pfnReserved84; + pfn_handler_t pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control 0 */ + pfn_handler_t pfnTCC0_MC0_Handler; /* 86 TCC Match/Compare 0 */ + pfn_handler_t pfnTCC0_MC1_Handler; /* 87 TCC Match/Compare 1 */ + pfn_handler_t pfnTCC0_MC2_Handler; /* 88 TCC Match/Compare 2 */ + pfn_handler_t pfnTCC0_MC3_Handler; /* 89 TCC Match/Compare 3 */ + pfn_handler_t pfnTCC0_MC4_Handler; /* 90 TCC Match/Compare 4 */ + pfn_handler_t pfnTCC0_MC5_Handler; /* 91 TCC Match/Compare 5 */ + pfn_handler_t pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control 1 */ + pfn_handler_t pfnTCC1_MC0_Handler; /* 93 TCC Match/Compare 0 */ + pfn_handler_t pfnTCC1_MC1_Handler; /* 94 TCC Match/Compare 1 */ + pfn_handler_t pfnTCC1_MC2_Handler; /* 95 TCC Match/Compare 2 */ + pfn_handler_t pfnTCC1_MC3_Handler; /* 96 TCC Match/Compare 3 */ + pfn_handler_t pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control 2 */ + pfn_handler_t pfnTCC2_MC0_Handler; /* 98 TCC Match/Compare 0 */ + pfn_handler_t pfnTCC2_MC1_Handler; /* 99 TCC Match/Compare 1 */ + pfn_handler_t pfnTCC2_MC2_Handler; /* 100 TCC Match/Compare 2 */ + pfn_handler_t pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control 3 */ + pfn_handler_t pfnTCC3_MC0_Handler; /* 102 TCC Match/Compare 0 */ + pfn_handler_t pfnTCC3_MC1_Handler; /* 103 TCC Match/Compare 1 */ + pfn_handler_t pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control 4 */ + pfn_handler_t pfnTCC4_MC0_Handler; /* 105 TCC Match/Compare 0 */ + pfn_handler_t pfnTCC4_MC1_Handler; /* 106 TCC Match/Compare 1 */ + pfn_handler_t pfnTC0_Handler; /* 107 Timer Counter 0 */ + pfn_handler_t pfnTC1_Handler; /* 108 Timer Counter 1 */ + pfn_handler_t pfnTC2_Handler; /* 109 Timer Counter 2 */ + pfn_handler_t pfnTC3_Handler; /* 110 Timer Counter 3 */ + pfn_handler_t pfnTC4_Handler; /* 111 Timer Counter 4 */ + pfn_handler_t pfnTC5_Handler; /* 112 Timer Counter 5 */ + pfn_handler_t pfnReserved113; + pfn_handler_t pfnReserved114; + pfn_handler_t pfnPDEC_OTHER_Handler; /* 115 Position Decoder */ + pfn_handler_t pfnPDEC_MC0_Handler; /* 116 PDEC Match/Compare 0 */ + pfn_handler_t pfnPDEC_MC1_Handler; /* 117 PDEC Match Compare 1 */ + pfn_handler_t pfnADC0_OTHER_Handler; /* 118 Analog To Digital Converter 0 */ + pfn_handler_t pfnADC0_RESRDY_Handler; /* 119 ADC0 Result Ready */ + pfn_handler_t pfnADC1_OTHER_Handler; /* 120 Analog To Digital Converter 1 */ + pfn_handler_t pfnADC1_RESRDY_Handler; /* 121 ADC1 Result Ready */ + pfn_handler_t pfnAC_Handler; /* 122 Analog Comparator */ + pfn_handler_t pfnDAC_OTHER_Handler; /* 123 Digital to Analog Converter */ + pfn_handler_t pfnDAC_EMPTY_0_Handler; /* 124 DAC Buffer 0 Empty */ + pfn_handler_t pfnDAC_EMPTY_1_Handler; /* 125 DAC Buffer 1 Empty */ + pfn_handler_t pfnDAC_RESRDY_0_Handler; /* 126 DAC Filter 0 Result Ready */ + pfn_handler_t pfnDAC_RESRDY_1_Handler; /* 127 DAC Filter 1 Result Ready */ + pfn_handler_t pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + pfn_handler_t pfnPCC_Handler; /* 129 Parallel Capture Controller */ + pfn_handler_t pfnAES_Handler; /* 130 Advanced Encryption Standard */ + pfn_handler_t pfnTRNG_Handler; /* 131 True Random Generator */ + pfn_handler_t pfnICM_Handler; /* 132 Integrity Check Monitor */ + pfn_handler_t pfnPUKCC_Handler; /* 133 Public-Key Cryptography Controller */ + pfn_handler_t pfnQSPI_Handler; /* 134 Quad SPI interface */ + pfn_handler_t pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ +}H3DeviceVectors; + +#endif //DEVICE_VECTORS_H diff --git a/firmware/src/config/mcal/exceptions.c b/firmware/src/config/mcal/exceptions.c new file mode 100644 index 0000000..fb43ab8 --- /dev/null +++ b/firmware/src/config/mcal/exceptions.c @@ -0,0 +1,120 @@ +/******************************************************************************* + System Exceptions File + + File Name: + exceptions.c + + Summary: + This file contains a function which overrides the default _weak_ exception + handlers provided by the interrupt.c file. + + Description: + This file redefines the default _weak_ exception handler with a more debug + friendly one. If an unexpected exception occurs the code will stop in a + while(1) loop. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "definitions.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Exception Handling Routine +// ***************************************************************************** +// ***************************************************************************** + +/* Brief default interrupt handlers for core IRQs.*/ + +void __attribute__((noreturn)) NonMaskableInt_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn)) HardFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn)) DebugMonitor_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn)) MemoryManagement_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn)) BusFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn)) UsageFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} +/******************************************************************************* + End of File + */ + diff --git a/firmware/src/config/mcal/harmony-manifest-success.yml b/firmware/src/config/mcal/harmony-manifest-success.yml new file mode 100644 index 0000000..d0a48d1 --- /dev/null +++ b/firmware/src/config/mcal/harmony-manifest-success.yml @@ -0,0 +1,19 @@ + +# This file has been autogenerated by MPLAB Harmony Configurator. Please do not edit this file. +# Project "P417_SWTR" has been created by using mentioned Harmony 3 packages + + +project: P417_SWTR +creation_date: 2024-06-27T16:42:30.665+08:00[Asia/Shanghai] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +operating_system: Windows 10 +mhc_mode: IDE # [IDE|Standalone|Headless] +mhc_version: v3.8.5 +mplabx_version: v6.00 # if MPLAB X plugin only +plugin_version: v3.6.4 # if MPLAB X plugin only +compiler: XC32 (4.10) + +modules: + - {name: "csp", version: "v3.14.0"} + - {name: "dev_packs", version: "v3.14.0"} + - {name: "touch", version: "v3.12.1"} + diff --git a/firmware/src/config/mcal/initialization.c b/firmware/src/config/mcal/initialization.c new file mode 100644 index 0000000..99ca0ec --- /dev/null +++ b/firmware/src/config/mcal/initialization.c @@ -0,0 +1,170 @@ +/******************************************************************************* + System Initialization File + + File Name: + initialization.c + + Summary: + This file contains source code necessary to initialize the system. + + Description: + This file contains source code necessary to initialize the system. It + implements the "SYS_Initialize" function, defines the configuration bits, + and allocates any necessary global system resources, + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "definitions.h" +#include "device.h" + + + +// **************************************************************************** +// **************************************************************************** +// Section: Configuration Bits +// **************************************************************************** +// **************************************************************************** +#pragma config BOD33_DIS = SET +#pragma config BOD33USERLEVEL = 0x1cU +#pragma config BOD33_ACTION = RESET +#pragma config BOD33_HYST = 0x2U +#pragma config NVMCTRL_BOOTPROT = 0xf +#pragma config NVMCTRL_SEESBLK = 0x1U +#pragma config NVMCTRL_SEEPSZ = 0x2U +#pragma config RAMECC_ECCDIS = SET +#pragma config WDT_ENABLE = CLEAR +#pragma config WDT_ALWAYSON = CLEAR +#pragma config WDT_PER = CYC8192 +#pragma config WDT_WINDOW = CYC8192 +#pragma config WDT_EWOFFSET = CYC8192 +#pragma config WDT_WEN = CLEAR +#pragma config NVMCTRL_REGION_LOCKS = 0xffffffffU + + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Driver Initialization Data +// ***************************************************************************** +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Data +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Library/Stack Initialization Data +// ***************************************************************************** +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Initialization +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local initialization functions +// ***************************************************************************** +// ***************************************************************************** + + + +/******************************************************************************* + Function: + void SYS_Initialize ( void *data ) + + Summary: + Initializes the board, services, drivers, application and other modules. + + Remarks: + */ + +void SYS_Initialize ( void* data ) +{ + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_1 */ + + NVMCTRL_Initialize( ); + + + PORT_Initialize(); + + CLOCK_Initialize(); + + + + + SERCOM1_I2C_Initialize(); + + EVSYS_Initialize(); + + SERCOM0_SPI_Initialize(); + + CAN1_Initialize(); + + SYSTICK_TimerInitialize(); + RTC_Initialize(); + + TC0_TimerInitialize(); + + DAC_Initialize(); + + TCC0_PWMInitialize(); + + ADC0_Initialize(); + ADC1_Initialize(); + + + + + touch_init(); + + + NVIC_Initialize(); + + /* MISRAC 2012 deviation block end */ +} + + +/******************************************************************************* + End of File +*/ diff --git a/firmware/src/config/mcal/interrupts.c b/firmware/src/config/mcal/interrupts.c new file mode 100644 index 0000000..c5b16c8 --- /dev/null +++ b/firmware/src/config/mcal/interrupts.c @@ -0,0 +1,343 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.c + + Summary: + Interrupt vectors mapping + + Description: + This file maps all the interrupt vectors to their corresponding + implementations. If a particular module interrupt is used, then its ISR + definition can be found in corresponding PLIB source file. If a module + interrupt is not used, then its ISR implementation is mapped to dummy + handler. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device_vectors.h" +#include "interrupts.h" +#include "definitions.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Interrupt Vector Functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRA C-2012 Rule 8.6 deviated below. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +extern uint32_t _stack; +extern const H3DeviceVectors exception_table; + +extern void Dummy_Handler(void); + +/* Brief default interrupt handler for unused IRQs.*/ +void __attribute__((optimize("-O1"),section(".text.Dummy_Handler"),long_call, noreturn))Dummy_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 deviated 108 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* Device vectors list dummy definition*/ +extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void MCLK_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSCCTRL_XOSC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSCCTRL_XOSC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSCCTRL_DFLL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSCCTRL_DPLL0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSCCTRL_DPLL1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void OSC32KCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SUPC_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SUPC_BODDET_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_6_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_7_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_8_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_9_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_10_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_11_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_12_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_13_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_14_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EIC_EXTINT_15_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void NVMCTRL_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void NVMCTRL_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DMAC_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DMAC_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DMAC_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DMAC_3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DMAC_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EVSYS_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EVSYS_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EVSYS_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EVSYS_3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void EVSYS_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void RAMECC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM2_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM2_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM2_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM2_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM3_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM3_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM3_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM3_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM4_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM4_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM4_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM4_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM5_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM5_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM5_2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SERCOM5_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void CAN0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void USB_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void USB_SOF_HSOF_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void USB_TRCPT0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void USB_TRCPT1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC0_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC0_MC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC0_MC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC0_MC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC0_MC5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC1_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC1_MC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC1_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC1_MC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC1_MC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC2_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC2_MC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC2_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC2_MC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC3_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC3_MC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC3_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC4_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC4_MC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TCC4_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TC5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PDEC_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PDEC_MC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PDEC_MC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void ADC0_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void ADC1_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void AC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DAC_OTHER_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DAC_EMPTY_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DAC_EMPTY_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DAC_RESRDY_0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void DAC_RESRDY_1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void I2S_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PCC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void AES_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void TRNG_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void ICM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void PUKCC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void QSPI_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); +extern void SDHC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"))); + + +/* MISRAC 2012 deviation block end */ + +/* Multiple handlers for vector */ + + + +__attribute__ ((section(".vectors"))) +const H3DeviceVectors exception_table= +{ + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = &_stack, + + .pfnReset_Handler = Reset_Handler, + .pfnNonMaskableInt_Handler = NonMaskableInt_Handler, + .pfnHardFault_Handler = HardFault_Handler, + .pfnMemoryManagement_Handler = MemoryManagement_Handler, + .pfnBusFault_Handler = BusFault_Handler, + .pfnUsageFault_Handler = UsageFault_Handler, + .pfnSVCall_Handler = SVCall_Handler, + .pfnDebugMonitor_Handler = DebugMonitor_Handler, + .pfnPendSV_Handler = PendSV_Handler, + .pfnSysTick_Handler = SysTick_Handler, + .pfnPM_Handler = PM_Handler, + .pfnMCLK_Handler = MCLK_Handler, + .pfnOSCCTRL_XOSC0_Handler = OSCCTRL_XOSC0_Handler, + .pfnOSCCTRL_XOSC1_Handler = OSCCTRL_XOSC1_Handler, + .pfnOSCCTRL_DFLL_Handler = OSCCTRL_DFLL_Handler, + .pfnOSCCTRL_DPLL0_Handler = OSCCTRL_DPLL0_Handler, + .pfnOSCCTRL_DPLL1_Handler = OSCCTRL_DPLL1_Handler, + .pfnOSC32KCTRL_Handler = OSC32KCTRL_Handler, + .pfnSUPC_OTHER_Handler = SUPC_OTHER_Handler, + .pfnSUPC_BODDET_Handler = SUPC_BODDET_Handler, + .pfnWDT_Handler = WDT_InterruptHandler, + .pfnRTC_Handler = RTC_InterruptHandler, + .pfnEIC_EXTINT_0_Handler = EIC_EXTINT_0_Handler, + .pfnEIC_EXTINT_1_Handler = EIC_EXTINT_1_Handler, + .pfnEIC_EXTINT_2_Handler = EIC_EXTINT_2_Handler, + .pfnEIC_EXTINT_3_Handler = EIC_EXTINT_3_Handler, + .pfnEIC_EXTINT_4_Handler = EIC_EXTINT_4_Handler, + .pfnEIC_EXTINT_5_Handler = EIC_EXTINT_5_Handler, + .pfnEIC_EXTINT_6_Handler = EIC_EXTINT_6_Handler, + .pfnEIC_EXTINT_7_Handler = EIC_EXTINT_7_Handler, + .pfnEIC_EXTINT_8_Handler = EIC_EXTINT_8_Handler, + .pfnEIC_EXTINT_9_Handler = EIC_EXTINT_9_Handler, + .pfnEIC_EXTINT_10_Handler = EIC_EXTINT_10_Handler, + .pfnEIC_EXTINT_11_Handler = EIC_EXTINT_11_Handler, + .pfnEIC_EXTINT_12_Handler = EIC_EXTINT_12_Handler, + .pfnEIC_EXTINT_13_Handler = EIC_EXTINT_13_Handler, + .pfnEIC_EXTINT_14_Handler = EIC_EXTINT_14_Handler, + .pfnEIC_EXTINT_15_Handler = EIC_EXTINT_15_Handler, + .pfnFREQM_Handler = FREQM_Handler, + .pfnNVMCTRL_0_Handler = NVMCTRL_0_Handler, + .pfnNVMCTRL_1_Handler = NVMCTRL_1_Handler, + .pfnDMAC_0_Handler = DMAC_0_Handler, + .pfnDMAC_1_Handler = DMAC_1_Handler, + .pfnDMAC_2_Handler = DMAC_2_Handler, + .pfnDMAC_3_Handler = DMAC_3_Handler, + .pfnDMAC_OTHER_Handler = DMAC_OTHER_Handler, + .pfnEVSYS_0_Handler = EVSYS_0_Handler, + .pfnEVSYS_1_Handler = EVSYS_1_Handler, + .pfnEVSYS_2_Handler = EVSYS_2_Handler, + .pfnEVSYS_3_Handler = EVSYS_3_Handler, + .pfnEVSYS_OTHER_Handler = EVSYS_OTHER_Handler, + .pfnPAC_Handler = PAC_Handler, + .pfnRAMECC_Handler = RAMECC_Handler, + .pfnSERCOM0_0_Handler = SERCOM0_SPI_InterruptHandler, + .pfnSERCOM0_1_Handler = SERCOM0_SPI_InterruptHandler, + .pfnSERCOM0_2_Handler = SERCOM0_SPI_InterruptHandler, + .pfnSERCOM0_OTHER_Handler = SERCOM0_SPI_InterruptHandler, + .pfnSERCOM1_0_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM1_1_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM1_2_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM1_OTHER_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM2_0_Handler = SERCOM2_0_Handler, + .pfnSERCOM2_1_Handler = SERCOM2_1_Handler, + .pfnSERCOM2_2_Handler = SERCOM2_2_Handler, + .pfnSERCOM2_OTHER_Handler = SERCOM2_OTHER_Handler, + .pfnSERCOM3_0_Handler = SERCOM3_0_Handler, + .pfnSERCOM3_1_Handler = SERCOM3_1_Handler, + .pfnSERCOM3_2_Handler = SERCOM3_2_Handler, + .pfnSERCOM3_OTHER_Handler = SERCOM3_OTHER_Handler, + .pfnSERCOM4_0_Handler = SERCOM4_0_Handler, + .pfnSERCOM4_1_Handler = SERCOM4_1_Handler, + .pfnSERCOM4_2_Handler = SERCOM4_2_Handler, + .pfnSERCOM4_OTHER_Handler = SERCOM4_OTHER_Handler, + .pfnSERCOM5_0_Handler = SERCOM5_0_Handler, + .pfnSERCOM5_1_Handler = SERCOM5_1_Handler, + .pfnSERCOM5_2_Handler = SERCOM5_2_Handler, + .pfnSERCOM5_OTHER_Handler = SERCOM5_OTHER_Handler, + .pfnCAN0_Handler = CAN0_Handler, + .pfnCAN1_Handler = CAN1_InterruptHandler, + .pfnUSB_OTHER_Handler = USB_OTHER_Handler, + .pfnUSB_SOF_HSOF_Handler = USB_SOF_HSOF_Handler, + .pfnUSB_TRCPT0_Handler = USB_TRCPT0_Handler, + .pfnUSB_TRCPT1_Handler = USB_TRCPT1_Handler, + .pfnTCC0_OTHER_Handler = TCC0_OTHER_InterruptHandler, + .pfnTCC0_MC0_Handler = TCC0_MC0_InterruptHandler, + .pfnTCC0_MC1_Handler = TCC0_MC1_Handler, + .pfnTCC0_MC2_Handler = TCC0_MC2_Handler, + .pfnTCC0_MC3_Handler = TCC0_MC3_Handler, + .pfnTCC0_MC4_Handler = TCC0_MC4_Handler, + .pfnTCC0_MC5_Handler = TCC0_MC5_Handler, + .pfnTCC1_OTHER_Handler = TCC1_OTHER_Handler, + .pfnTCC1_MC0_Handler = TCC1_MC0_Handler, + .pfnTCC1_MC1_Handler = TCC1_MC1_Handler, + .pfnTCC1_MC2_Handler = TCC1_MC2_Handler, + .pfnTCC1_MC3_Handler = TCC1_MC3_Handler, + .pfnTCC2_OTHER_Handler = TCC2_OTHER_Handler, + .pfnTCC2_MC0_Handler = TCC2_MC0_Handler, + .pfnTCC2_MC1_Handler = TCC2_MC1_Handler, + .pfnTCC2_MC2_Handler = TCC2_MC2_Handler, + .pfnTCC3_OTHER_Handler = TCC3_OTHER_Handler, + .pfnTCC3_MC0_Handler = TCC3_MC0_Handler, + .pfnTCC3_MC1_Handler = TCC3_MC1_Handler, + .pfnTCC4_OTHER_Handler = TCC4_OTHER_Handler, + .pfnTCC4_MC0_Handler = TCC4_MC0_Handler, + .pfnTCC4_MC1_Handler = TCC4_MC1_Handler, + .pfnTC0_Handler = TC0_TimerInterruptHandler, + .pfnTC1_Handler = TC1_Handler, + .pfnTC2_Handler = TC2_Handler, + .pfnTC3_Handler = TC3_Handler, + .pfnTC4_Handler = TC4_Handler, + .pfnTC5_Handler = TC5_Handler, + .pfnPDEC_OTHER_Handler = PDEC_OTHER_Handler, + .pfnPDEC_MC0_Handler = PDEC_MC0_Handler, + .pfnPDEC_MC1_Handler = PDEC_MC1_Handler, + .pfnADC0_OTHER_Handler = ADC0_OTHER_Handler, + .pfnADC0_RESRDY_Handler = ADC0_1_Handler, + .pfnADC1_OTHER_Handler = ADC1_OTHER_Handler, + .pfnADC1_RESRDY_Handler = ADC1_RESRDY_InterruptHandler, + .pfnAC_Handler = AC_Handler, + .pfnDAC_OTHER_Handler = DAC_OTHER_Handler, + .pfnDAC_EMPTY_0_Handler = DAC_EMPTY_0_Handler, + .pfnDAC_EMPTY_1_Handler = DAC_EMPTY_1_Handler, + .pfnDAC_RESRDY_0_Handler = DAC_RESRDY_0_Handler, + .pfnDAC_RESRDY_1_Handler = DAC_RESRDY_1_Handler, + .pfnI2S_Handler = I2S_Handler, + .pfnPCC_Handler = PCC_Handler, + .pfnAES_Handler = AES_Handler, + .pfnTRNG_Handler = TRNG_Handler, + .pfnICM_Handler = ICM_Handler, + .pfnPUKCC_Handler = PUKCC_Handler, + .pfnQSPI_Handler = QSPI_Handler, + .pfnSDHC0_Handler = SDHC0_Handler, + + +}; + +/******************************************************************************* + End of File +*/ diff --git a/firmware/src/config/mcal/interrupts.h b/firmware/src/config/mcal/interrupts.h new file mode 100644 index 0000000..ece5642 --- /dev/null +++ b/firmware/src/config/mcal/interrupts.h @@ -0,0 +1,81 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.h + + Summary: + Interrupt vectors mapping + + Description: + This file contains declarations of device vectors used by Harmony 3 + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Handler Routines +// ***************************************************************************** +// ***************************************************************************** + +void Reset_Handler (void); +void NonMaskableInt_Handler (void); +void HardFault_Handler (void); +void MemoryManagement_Handler (void); +void BusFault_Handler (void); +void UsageFault_Handler (void); +void DebugMonitor_Handler (void); +void SysTick_Handler (void); +void WDT_InterruptHandler (void); +void RTC_InterruptHandler (void); +void SERCOM0_SPI_InterruptHandler (void); +void SERCOM1_I2C_InterruptHandler (void); +void CAN1_InterruptHandler (void); +void TCC0_OTHER_InterruptHandler (void); +void TCC0_MC0_InterruptHandler (void); +void TC0_TimerInterruptHandler (void); +void ADC0_1_Handler (void); +void ADC1_RESRDY_InterruptHandler (void); + + + +#endif // INTERRUPTS_H diff --git a/firmware/src/config/mcal/libc_syscalls.c b/firmware/src/config/mcal/libc_syscalls.c new file mode 100644 index 0000000..238ff02 --- /dev/null +++ b/firmware/src/config/mcal/libc_syscalls.c @@ -0,0 +1,61 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include +#include "device.h" /* for ARM CMSIS __BKPT() */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated twice. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* Harmony specific + * We implement only the syscalls we want over the stubs provided by libpic32c + */ +extern void _exit(int status); + +void _exit(int status) +{ + /* Software breakpoint */ +#ifdef __DEBUG + __BKPT(0); +#endif + + /* halt CPU */ + while (true) + { + } +} + +#ifdef __cplusplus +} +#endif + +/* MISRAC 2012 deviation block end */ diff --git a/firmware/src/config/mcal/mcal.mhc/GraphSettings.yml b/firmware/src/config/mcal/mcal.mhc/GraphSettings.yml new file mode 100644 index 0000000..c4114fd --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/GraphSettings.yml @@ -0,0 +1,3 @@ +format_version: v1.0 +type: GraphSettings +attributes: {canvasWidth: '876', id: GraphSettings, canvasHeight: '571'} diff --git a/firmware/src/config/mcal/mcal.mhc/adc0.yml b/firmware/src/config/mcal/mcal.mhc/adc0.yml new file mode 100644 index 0000000..68f1ed2 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/adc0.yml @@ -0,0 +1,144 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: adc0} +children: +- type: Symbols + children: + - type: String + attributes: {id: ADC_CALLBACK_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_CallbackRegister} + - type: String + attributes: {id: ADC_CHANNEL_SELECT_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_ChannelSelect} + - type: String + attributes: {id: ADC_CH_PHASE_U} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_PHASE_V} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_POT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_VDC_BUS} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_GET_RESULT_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_ConversionResultGet} + - type: String + attributes: {id: ADC_GND} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC_NEGINPUT_GND} + - type: String + attributes: {id: ADC_INT_CLEAR_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_InterruptsClear} + - type: String + attributes: {id: ADC_INT_DISABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_InterruptsDisable} + - type: String + attributes: {id: ADC_INT_ENABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_InterruptsEnable} + - type: String + attributes: {id: ADC_IS_RESULT_READY_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_ConversionStatusGet} + - type: Comment + attributes: {id: ADC_SAMPCTRL_SAMPLEN_TIME} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** Conversion Time is 16.0 uS ****'} + - type: String + attributes: {id: ADC_START_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_Enable} + - type: String + attributes: {id: ADC_START_CONV_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_ConversionStart} + - type: String + attributes: {id: ADC_STOP_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_Disable} + - type: String + attributes: {id: INTERRUPT_ADC_RESULT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc0, value: ADC0_RESRDY_IRQn} +- type: Attachments + children: + - type: DirectCapability + attributes: {id: ADC0_ADC} + children: + - type: Attributes + children: + - type: String + attributes: {id: targetComponentID} + children: + - {type: Value, value: ptc} + - type: String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: lib_acquire} +- type: ElementPosition + attributes: {x: '298', y: '239', id: adc0} diff --git a/firmware/src/config/mcal/mcal.mhc/adc1.yml b/firmware/src/config/mcal/mcal.mhc/adc1.yml new file mode 100644 index 0000000..907b5a9 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/adc1.yml @@ -0,0 +1,164 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: adc1} +children: +- type: Symbols + children: + - type: String + attributes: {id: ADC_CALLBACK_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_CallbackRegister} + - type: String + attributes: {id: ADC_CHANNEL_SELECT_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_ChannelSelect} + - type: String + attributes: {id: ADC_CH_PHASE_U} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_PHASE_V} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_POT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC_POSINPUT_AIN0} + - type: String + attributes: {id: ADC_CH_VDC_BUS} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC_POSINPUT_AIN0} + - type: Combo + attributes: {id: ADC_CONV_TRIGGER} + children: + - type: Values + children: + - type: User + attributes: {value: SW Trigger} + - type: KeyValueSet + attributes: {id: ADC_CTRLA_PRESCALER} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: String + attributes: {id: ADC_GET_RESULT_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_ConversionResultGet} + - type: String + attributes: {id: ADC_GND} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC_NEGINPUT_GND} + - type: KeyValueSet + attributes: {id: ADC_INPUTCTRL_MUXPOS} + children: + - type: Values + children: + - type: User + attributes: {value: '4'} + - type: Boolean + attributes: {id: ADC_INTENSET_RESRDY} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: String + attributes: {id: ADC_INT_CLEAR_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_InterruptsClear} + - type: String + attributes: {id: ADC_INT_DISABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_InterruptsDisable} + - type: String + attributes: {id: ADC_INT_ENABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_InterruptsEnable} + - type: String + attributes: {id: ADC_IS_RESULT_READY_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_ConversionStatusGet} + - type: Integer + attributes: {id: ADC_SAMPCTRL_SAMPLEN} + children: + - type: Values + children: + - type: User + attributes: {value: '28'} + - type: Comment + attributes: {id: ADC_SAMPCTRL_SAMPLEN_TIME} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** Conversion Time is 40.0 uS ****'} + - type: String + attributes: {id: ADC_START_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_Enable} + - type: String + attributes: {id: ADC_START_CONV_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_ConversionStart} + - type: String + attributes: {id: ADC_STOP_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_Disable} + - type: String + attributes: {id: INTERRUPT_ADC_RESULT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_RESRDY_IRQn} +- type: ElementPosition + attributes: {x: '426', y: '423', id: adc1} diff --git a/firmware/src/config/mcal/mcal.mhc/can1.yml b/firmware/src/config/mcal/mcal.mhc/can1.yml new file mode 100644 index 0000000..486c986 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/can1.yml @@ -0,0 +1,190 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: can1} +children: +- type: Symbols + children: + - type: Integer + attributes: {id: CALCULATED_NOMINAL_BITRATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '500'} + - type: String + attributes: {id: CALCULATED_NOMINAL_ERRORRATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '0.000'} + - type: Menu + attributes: {id: CAN1_STD_FILTER1} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Hex + attributes: {id: CAN1_STD_FILTER1_SFID2} + children: + - type: Values + children: + - type: User + attributes: {value: '2047'} + - type: KeyValueSet + attributes: {id: CAN1_STD_FILTER1_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: Integer + attributes: {id: CAN_CORE_CLOCK_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '8000000'} + - type: Comment + attributes: {id: CAN_CORE_CLOCK_INVALID_COMMENT} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Comment + attributes: {id: CAN_TIME_QUANTA_INVALID_COMMENT} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: FILTERS_STD} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: Boolean + attributes: {id: INTERRUPT_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: NBTP_NSJW} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '3'} + - type: Integer + attributes: {id: NBTP_NTSEG1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '12'} + - type: Integer + attributes: {id: NBTP_NTSEG2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '3'} + - type: Integer + attributes: {id: NBTP_TOTAL_TIME_QUANTA} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '16'} + - type: Float + attributes: {id: NOMINAL_SAMPLE_POINT} + children: + - type: Values + children: + - type: User + attributes: {value: '81.25'} + - type: String + attributes: {id: NOMINAL_TIME_QUANTA_PERIOD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '125.000'} + - type: Integer + attributes: {id: RXF0_ELEMENTS} + children: + - type: Values + children: + - type: User + attributes: {value: '8'} + - type: Integer + attributes: {id: RXF0_WATERMARK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '0'} + - type: Integer + attributes: {id: RXF1_ELEMENTS} + children: + - type: Values + children: + - type: User + attributes: {value: '8'} + - type: Integer + attributes: {id: RXF1_WATERMARK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '0'} + - type: Integer + attributes: {id: TX_FIFO_ELEMENTS} + children: + - type: Values + children: + - type: User + attributes: {value: '16'} + - type: Integer + attributes: {id: TX_FIFO_WATERMARK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: '0'} + - type: File + attributes: {id: instHeaderFile} + children: + - type: Attributes + children: + - type: String + attributes: {id: source} + children: + - {type: Value, value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl} + - type: File + attributes: {id: sourceFile} + children: + - type: Attributes + children: + - type: String + attributes: {id: source} + children: + - {type: Value, value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl} +- type: ElementPosition + attributes: {x: '20', y: '213', id: can1} diff --git a/firmware/src/config/mcal/mcal.mhc/cmsis.yml b/firmware/src/config/mcal/mcal.mhc/cmsis.yml new file mode 100644 index 0000000..23961c0 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/cmsis.yml @@ -0,0 +1,6 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: cmsis} +children: +- type: ElementPosition + attributes: {x: '660', y: '20', id: cmsis} diff --git a/firmware/src/config/mcal/mcal.mhc/core.yml b/firmware/src/config/mcal/mcal.mhc/core.yml new file mode 100644 index 0000000..f306814 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/core.yml @@ -0,0 +1,4329 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: core} +children: +- type: Symbols + children: + - type: Boolean + attributes: {id: ADC0_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: 'true'} + - type: Integer + attributes: {id: ADC0_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: ADC0_RESRDY_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: ADC1_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: 'true'} + - type: Integer + attributes: {id: ADC1_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: ADC1_RESRDY_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: 'true'} + - type: Boolean + attributes: {id: ADC1_RESRDY_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: ADC1_RESRDY_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: ADC1_RESRDY_InterruptHandler} + - type: Boolean + attributes: {id: ADC1_RESRDY_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: adc1, value: 'true'} + - type: Boolean + attributes: {id: CAN1_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: 'true'} + - type: Integer + attributes: {id: CAN1_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: CAN1_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: 'true'} + - type: Boolean + attributes: {id: CAN1_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: CAN1_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: CAN1_InterruptHandler} + - type: Boolean + attributes: {id: CAN1_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: can1, value: 'true'} + - type: KeyValueSet + attributes: {id: COMPILER_CHOICE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0'} + - type: Boolean + attributes: {id: CONFIG_CLOCK_DFLL_RUNSTDY} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL0_DIVIDER} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL0_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '4'} + - type: Boolean + attributes: {id: CONFIG_CLOCK_DPLL0_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL0_LDR_INTEGER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '119'} + - type: User + attributes: {value: '59'} + - type: Float + attributes: {id: CONFIG_CLOCK_DPLL0_MULTIPLIER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '60.0'} + - type: KeyValueSet + attributes: {id: CONFIG_CLOCK_DPLL0_REF_CLOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '3'} + - type: User + attributes: {value: '2'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL1_DIVIDER} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL1_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '4'} + - type: Boolean + attributes: {id: CONFIG_CLOCK_DPLL1_ENABLE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: CONFIG_CLOCK_DPLL1_LDR_INTEGER} + children: + - type: Values + children: + - type: User + attributes: {value: '47'} + - type: Float + attributes: {id: CONFIG_CLOCK_DPLL1_MULTIPLIER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '48.0'} + - type: KeyValueSet + attributes: {id: CONFIG_CLOCK_DPLL1_REF_CLOCK} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: Boolean + attributes: {id: CONFIG_CLOCK_XOSC1_ENABLE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: CPU_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '120000000'} + - type: Menu + attributes: {id: CoreIARMenu} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Menu + attributes: {id: CoreKEILMenu} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: DAC_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: dac, value: 'true'} + - type: Integer + attributes: {id: DAC_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '2000000'} + - type: KeyValueSet + attributes: {id: DEVICE_SECURITY_CMD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0'} + - type: KeyValueSet + attributes: {id: DEVICE_TCM_SIZE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0'} + - type: Integer + attributes: {id: DPLL0_CLOCK_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '120000000'} + - type: Integer + attributes: {id: DPLL1_CLOCK_FREQ} + children: + - type: Values + children: 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type: Dynamic + attributes: {id: core, value: '6'} + - type: User + attributes: {value: '5'} + - type: Integer + attributes: {id: GCLK_2_DIV} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '48'} + - type: Integer + attributes: {id: GCLK_2_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '48'} + - type: Integer + attributes: {id: GCLK_2_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '1000000'} + - type: KeyValueSet + attributes: {id: GCLK_2_SRC} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '6'} + - type: Integer + attributes: {id: GCLK_3_DIV} + children: + - type: Values + children: + - type: User + attributes: {value: '4'} + - type: Integer + attributes: {id: GCLK_3_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '4'} + - type: Integer + attributes: {id: GCLK_3_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '2000000'} + - type: KeyValueSet + attributes: {id: GCLK_3_SRC} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: Integer + attributes: {id: GCLK_4_DIV} + children: + - type: Values + children: + - type: User + attributes: {value: '12'} + - type: Integer + attributes: {id: GCLK_4_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '12'} + - type: Integer + attributes: {id: GCLK_4_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: KeyValueSet + attributes: {id: GCLK_4_SRC} + children: + - type: Values + children: + - type: User + attributes: {value: '8'} + - type: Integer + attributes: {id: GCLK_5_DIV} + children: + - type: Values + children: + - type: User + attributes: {value: '3'} + - type: Integer + attributes: {id: GCLK_5_DIVIDER_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '3'} + - type: Integer + attributes: {id: GCLK_5_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '16000000'} + - type: ListEntry + attributes: {id: GCLK_CODE} + children: + - type: Attributes + children: + - type: StringArray + attributes: {id: values} + children: + - type: Values + children: + - {type: Value, value: ' FDPLL0_Initialize();'} + - {type: Value, value: ' FDPLL1_Initialize();'} + - {type: Value, value: ' GCLK3_Initialize();'} + - {type: Value, value: ' DFLL_Initialize();'} + - {type: Value, value: ' GCLK0_Initialize();'} + - {type: Value, value: ' GCLK4_Initialize();'} + - {type: Value, value: ' GCLK1_Initialize();'} + - {type: Value, value: ' GCLK2_Initialize();'} + - {type: Value, value: ' GCLK5_Initialize();'} + - type: Boolean + attributes: {id: GCLK_CYCLE_FORMED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: GCLK_ID_1_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_1_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '1000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_1_GENSEL} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '2'} + - type: Boolean + attributes: {id: GCLK_ID_25_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_25_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: GCLK_ID_28_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_28_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_28_GENSEL} + children: + - type: Values + children: + - type: User + attributes: {value: '4'} + - type: Boolean + attributes: {id: GCLK_ID_2_CHEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_2_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: GCLK_ID_40_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_40_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_40_GENSEL} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: '1'} + - type: Boolean + attributes: {id: GCLK_ID_41_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_41_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_41_GENSEL} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: Boolean + attributes: {id: GCLK_ID_42_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_42_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '2000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_42_GENSEL} + children: + - type: Values + children: + - type: User + attributes: {value: '3'} + - type: Boolean + attributes: {id: GCLK_ID_7_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_7_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: GCLK_ID_8_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_8_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: GCLK_ID_9_CHEN} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Integer + attributes: {id: GCLK_ID_9_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '1000000'} + - type: KeyValueSet + attributes: {id: GCLK_ID_9_GENSEL} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: Boolean + attributes: {id: GCLK_INST_NUM1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: GCLK_INST_NUM2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: GCLK_INST_NUM3} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: GCLK_INST_NUM4} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: GCLK_INST_NUM5} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: String + attributes: {id: KEIL_STACK_HEAP_SIZE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1200'} + - type: Integer + attributes: {id: MAIN_CLOCK_FREQUENCY} + children: + - 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children: + - type: User + attributes: {value: Out} + - type: String + attributes: {id: PIN_30_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: SDZ} + - type: String + attributes: {id: PIN_30_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_30_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_30_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_30_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_35_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: X1_SNS} + - type: String + attributes: {id: PIN_35_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X10/Y10} + - type: String + attributes: {id: PIN_35_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_35_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_36_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: X2_SNS} + - type: String + attributes: {id: PIN_36_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X11/Y11} + - type: String + attributes: {id: PIN_36_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_36_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_37_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: X3_SNS} + - type: String + attributes: {id: PIN_37_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X12/Y12} + - type: String + attributes: {id: PIN_37_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_37_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_38_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: X4_SNS} + - type: String + attributes: {id: PIN_38_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X13/Y13} + - type: String + attributes: {id: PIN_38_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_38_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_3_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: Out} + - type: String + attributes: {id: PIN_3_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: INP} + - type: String + attributes: {id: PIN_3_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: User + attributes: {value: DAC_VOUT0} + - type: String + attributes: {id: PIN_3_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_3_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_3_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_41_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: X5_SNS} + - type: String + attributes: {id: PIN_41_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X14/Y14} + - type: String + attributes: {id: PIN_41_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_41_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_42_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_RES1_SNS} + - type: String + attributes: {id: PIN_42_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X15/Y15} + - type: User + attributes: {value: ADC0_X15/Y15} + - type: String + attributes: {id: PIN_42_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_42_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_43_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_CANCEL2_SNS} + - type: String + attributes: {id: PIN_43_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X16/Y16} + - type: String + attributes: {id: PIN_43_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_43_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_44_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_CANCEL1_SNS} + - type: String + attributes: {id: PIN_44_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X17/Y17} + - type: String + attributes: {id: PIN_44_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_44_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_46_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: Out} + - type: String + attributes: {id: PIN_46_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: INP_0_EN} + - type: String + attributes: {id: PIN_46_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_46_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_46_LAT} + children: + - type: Values + children: + - type: User + attributes: {value: High} + - type: String + attributes: {id: PIN_46_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_46_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_49_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_49_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_49_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: OSCCTRL_XIN1} + - type: String + attributes: {id: PIN_4_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: String + attributes: {id: PIN_50_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_50_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_50_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: OSCCTRL_XOUT1} + - type: String + attributes: {id: PIN_51_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: String + attributes: {id: PIN_51_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_57_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: String + attributes: {id: PIN_59_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: Out} + - type: String + attributes: {id: PIN_59_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: SBC_INT} + - type: String + attributes: {id: PIN_59_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: EIC_EXTINT14} + - type: String + attributes: {id: PIN_59_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'True'} + - type: String + attributes: {id: PIN_59_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_59_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: A} + - type: String + attributes: {id: PIN_5_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: AD_LDO} + - type: String + attributes: {id: PIN_5_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: User + attributes: {value: ADC1_AIN6} + - type: String + attributes: {id: PIN_5_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_5_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_60_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_60_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: INTB_PRSS} + - type: String + attributes: {id: PIN_60_FUNCTION_TYPE} + children: + - type: Values + children: + - type: User + attributes: {value: EIC_EXTINT15} + - type: String + attributes: {id: PIN_60_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'True'} + - type: String + attributes: {id: PIN_60_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_60_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: A} + - type: String + attributes: {id: PIN_60_PULLEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_61_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_61_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_TJP2_SNS} + - type: String + attributes: {id: PIN_61_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_AIN12/X30/Y30} + - type: User + attributes: {value: ADC0_AIN12/X30/Y30} + - type: String + attributes: {id: PIN_61_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'True'} + - type: String + attributes: {id: PIN_61_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_61_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_61_PULLEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_62_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_TJP1_SNS} + - type: String + attributes: {id: PIN_62_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_AIN13/X31/Y31} + - type: User + attributes: {value: ADC0_AIN13/X31/Y31} + - type: String + attributes: {id: PIN_62_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_62_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_63_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: Out} + - type: String + attributes: {id: PIN_63_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: Power_AD_Ctrl} + - type: String + attributes: {id: PIN_63_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_63_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_63_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_63_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: GPIO} + - type: String + attributes: {id: PIN_64_DIR} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_64_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: CAP_RES2_SNS} + - type: String + attributes: {id: PIN_64_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: User + attributes: {value: ADC0_AIN15/X21/Y21} + - type: String + attributes: {id: PIN_64_INEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'True'} + - type: String + attributes: {id: PIN_64_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_64_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_64_PULLEN} + children: + - type: Values + children: + - type: User + attributes: {value: ''} + - type: String + attributes: {id: PIN_6_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: LD_OUT} + - type: String + attributes: {id: PIN_6_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ''} + - type: User + attributes: {value: ADC1_AIN7} + - type: String + attributes: {id: PIN_6_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_6_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: String + attributes: {id: PIN_9_FUNCTION_NAME} + children: + - type: Values + children: + - type: User + attributes: {value: Y1_SNS} + - type: String + attributes: {id: PIN_9_FUNCTION_TYPE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ADC0_X24/Y24} + - type: String + attributes: {id: PIN_9_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: ANALOG} + - type: String + attributes: {id: PIN_9_PERIPHERAL_FUNCTION} + children: + - type: Values + children: + - type: User + attributes: {value: B} + - type: Boolean + attributes: {id: PORT_GROUP_0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: PORT_GROUP_0_DIR} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x2002404'} + - type: String + attributes: {id: PORT_GROUP_0_OUT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x2000400'} + - type: String + attributes: {id: PORT_GROUP_0_PAD_0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA00} + - type: String + attributes: {id: PORT_GROUP_0_PAD_1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA01} + - type: String + attributes: {id: PORT_GROUP_0_PAD_10} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA10} + - type: String + attributes: {id: PORT_GROUP_0_PAD_11} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA11} + - type: String + attributes: {id: PORT_GROUP_0_PAD_12} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA12} + - type: String + attributes: {id: PORT_GROUP_0_PAD_13} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA13} + - type: String + attributes: {id: PORT_GROUP_0_PAD_16} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA16} + - type: String + attributes: {id: PORT_GROUP_0_PAD_17} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA17} + - type: String + attributes: {id: PORT_GROUP_0_PAD_18} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA18} + - type: String + attributes: {id: PORT_GROUP_0_PAD_19} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA19} + - type: String + attributes: {id: PORT_GROUP_0_PAD_2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA02} + - type: String + attributes: {id: PORT_GROUP_0_PAD_20} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA20} + - type: String + attributes: {id: PORT_GROUP_0_PAD_21} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA21} + - type: String + attributes: {id: PORT_GROUP_0_PAD_22} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA22} + - type: String + attributes: {id: PORT_GROUP_0_PAD_23} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA23} + - type: String + attributes: {id: PORT_GROUP_0_PAD_25} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA25} + - type: String + attributes: {id: PORT_GROUP_0_PAD_27} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA27} + - type: String + attributes: {id: PORT_GROUP_0_PAD_4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA04} + - type: String + attributes: {id: PORT_GROUP_0_PAD_6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA06} + - type: String + attributes: {id: PORT_GROUP_0_PAD_7} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA07} + - type: String + attributes: {id: PORT_GROUP_0_PAD_8} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA08} + - type: String + attributes: {id: PORT_GROUP_0_PAD_9} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PA09} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG10} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG11} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG12} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x3'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG13} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG16} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG17} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG18} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG19} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG20} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG21} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG22} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG23} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG25} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG27} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG7} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG8} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PINCFG9} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_0_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_10_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_11_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_12_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_13_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_16_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_17_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_18_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_19_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_1_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_20_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_21_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_22_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_23_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_25_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_27_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_2_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_4_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_6_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_7_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_8_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_0_PIN_9_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x33'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX10} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX11} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX12} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX13} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX3} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x22'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX5} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x20'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX8} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_0_PMUX9} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: Boolean + attributes: {id: PORT_GROUP_1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: PORT_GROUP_1_DIR} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x4000c004'} + - type: String + attributes: {id: PORT_GROUP_1_PAD_0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB00} + - type: String + attributes: {id: PORT_GROUP_1_PAD_1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB01} + - type: String + attributes: {id: PORT_GROUP_1_PAD_10} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB10} + - type: String + attributes: {id: PORT_GROUP_1_PAD_12} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB12} + - type: String + attributes: {id: PORT_GROUP_1_PAD_13} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB13} + - type: String + attributes: {id: PORT_GROUP_1_PAD_14} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB14} + - type: String + attributes: {id: PORT_GROUP_1_PAD_15} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB15} + - type: String + attributes: {id: PORT_GROUP_1_PAD_2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB02} + - type: String + attributes: {id: PORT_GROUP_1_PAD_22} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB22} + - type: String + attributes: {id: PORT_GROUP_1_PAD_23} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB23} + - type: String + attributes: {id: PORT_GROUP_1_PAD_3} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB03} + - type: String + attributes: {id: PORT_GROUP_1_PAD_30} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB30} + - type: String + attributes: {id: PORT_GROUP_1_PAD_31} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB31} + - type: String + attributes: {id: PORT_GROUP_1_PAD_4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB04} + - type: String + attributes: {id: PORT_GROUP_1_PAD_5} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB05} + - type: String + attributes: {id: PORT_GROUP_1_PAD_6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB06} + - type: String + attributes: {id: PORT_GROUP_1_PAD_7} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB07} + - type: String + attributes: {id: PORT_GROUP_1_PAD_8} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB08} + - type: String + attributes: {id: PORT_GROUP_1_PAD_9} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PB09} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x3'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG10} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG12} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG13} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG14} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG15} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG22} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG23} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG3} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x3'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG30} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x3'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG31} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x3'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG5} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG7} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG8} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: String + attributes: {id: PORT_GROUP_1_PINCFG9} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_0_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_10_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_12_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_13_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_14_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_15_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_1_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_22_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_23_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_2_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_30_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_31_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_3_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_4_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_5_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_6_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_7_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_8_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: PORT_GROUP_1_PIN_9_USED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX1} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x10'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX11} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX15} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX2} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX3} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX4} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x11'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX5} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x5'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX6} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x77'} + - type: String + attributes: {id: PORT_GROUP_1_PMUX7} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x0'} + - type: String + attributes: {id: PORT_REG_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: PORT} + - type: Integer + attributes: {id: QSPI_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0'} + - type: Boolean + attributes: {id: RTC_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: 'true'} + - type: Boolean + attributes: {id: RTC_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: RTC_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_InterruptHandler} + - type: Boolean + attributes: {id: RTC_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_0_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_0_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM0_0_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: SERCOM0_SPI_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM0_0_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_1_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_1_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM0_1_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: SERCOM0_SPI_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM0_1_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_2_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_2_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM0_2_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: SERCOM0_SPI_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM0_2_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_CORE_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Integer + attributes: {id: SERCOM0_CORE_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: SERCOM0_OTHER_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM0_OTHER_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM0_OTHER_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: SERCOM0_SPI_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM0_OTHER_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_0_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_0_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM1_0_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: SERCOM1_I2C_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM1_0_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_1_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_1_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM1_1_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: SERCOM1_I2C_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM1_1_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_2_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_2_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM1_2_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: SERCOM1_I2C_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM1_2_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_CORE_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Integer + attributes: {id: SERCOM1_CORE_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: SERCOM1_OTHER_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: SERCOM1_OTHER_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: SERCOM1_OTHER_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: SERCOM1_I2C_InterruptHandler} + - type: Boolean + attributes: {id: SERCOM1_OTHER_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: File + attributes: {id: SYSTICK_FILE_0} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SYSTICK_FILE_1} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SYSTICK_FILE_2} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Menu + attributes: {id: SYSTICK_MENU_0} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: String + attributes: {id: SYSTICK_PERIOD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '0x1D4C0'} + - type: Float + attributes: {id: SYSTICK_PERIOD_MS} + children: + - type: Attributes + children: + - type: Float + attributes: {id: max} + children: + - {type: Value, value: '139.81012'} + - type: Integer + attributes: {id: SYSTICK_PERIOD_US} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '1000'} + - type: Boolean + attributes: {id: SysTick_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: SysTick_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: Boolean + attributes: {id: SysTick_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: TC0_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: 'true'} + - type: Integer + attributes: {id: TC0_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '1000000'} + - type: Boolean + attributes: {id: TC0_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: 'true'} + - type: Boolean + attributes: {id: TC0_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: TC0_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: TC0_TimerInterruptHandler} + - type: Boolean + attributes: {id: TC0_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: 'true'} + - type: Boolean + attributes: {id: TCC0_CLOCK_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Integer + attributes: {id: TCC0_CLOCK_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: TCC0_MC0_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Boolean + attributes: {id: TCC0_MC0_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: TCC0_MC0_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC0_InterruptHandler} + - type: Boolean + attributes: {id: TCC0_MC0_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Boolean + attributes: {id: TCC0_MC1_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC1_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: TCC0_MC1_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC1_Handler} + - type: Boolean + attributes: {id: TCC0_MC1_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC2_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC2_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: TCC0_MC2_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC2_Handler} + - type: Boolean + attributes: {id: TCC0_MC2_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC3_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC3_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: TCC0_MC3_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC3_Handler} + - type: Boolean + attributes: {id: TCC0_MC3_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC4_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC4_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: TCC0_MC4_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC4_Handler} + - type: Boolean + attributes: {id: TCC0_MC4_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC5_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_MC5_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: String + attributes: {id: TCC0_MC5_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_MC5_Handler} + - type: Boolean + attributes: {id: TCC0_MC5_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'false'} + - type: Boolean + attributes: {id: TCC0_OTHER_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Boolean + attributes: {id: TCC0_OTHER_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: TCC0_OTHER_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_OTHER_InterruptHandler} + - type: Boolean + attributes: {id: TCC0_OTHER_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Boolean + attributes: {id: USE_SYSTICK_INTERRUPT} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Comment + attributes: {id: WDT_CONFIG_COMMENT} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: WDT_EW_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: File + attributes: {id: WDT_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: WDT_INTERRUPT_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: Boolean + attributes: {id: WDT_INTERRUPT_ENABLE_UPDATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'false'} + - type: String + attributes: {id: WDT_INTERRUPT_HANDLER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: WDT_InterruptHandler} + - type: Boolean + attributes: {id: WDT_INTERRUPT_HANDLER_LOCK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: 'true'} + - type: File + attributes: {id: WDT_SOURCE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: WDT_SYS_DEF} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: WDT_USE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: XOSC1_FREQ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: core, value: '8000000'} + - type: Boolean + attributes: {id: systickEnable} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: File + attributes: {id: systickSystemInitFile} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} +- type: ElementPosition + attributes: {x: '560', y: '19', id: core} diff --git a/firmware/src/config/mcal/mcal.mhc/dac.yml b/firmware/src/config/mcal/mcal.mhc/dac.yml new file mode 100644 index 0000000..c4e748e --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/dac.yml @@ -0,0 +1,43 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: dac} +children: +- type: Symbols + children: + - type: Boolean + attributes: {id: DAC_CHANNEL_0_ENABLE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: KeyValueSet + attributes: {id: DAC_CHANNEL_0_OVERSAMPLE} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DAC_CHANNEL_0_REFRESH} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DAC_CHANNEL_0_SPEED} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DAC_REFSEL} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} +- type: ElementPosition + attributes: {x: '25', y: '335', id: dac} diff --git a/firmware/src/config/mcal/mcal.mhc/dfp.yml b/firmware/src/config/mcal/mcal.mhc/dfp.yml new file mode 100644 index 0000000..0c78008 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/dfp.yml @@ -0,0 +1,6 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: dfp} +children: +- type: ElementPosition + attributes: {x: '339', y: '20', id: dfp} diff --git a/firmware/src/config/mcal/mcal.mhc/evsys.yml b/firmware/src/config/mcal/mcal.mhc/evsys.yml new file mode 100644 index 0000000..c07ad76 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/evsys.yml @@ -0,0 +1,232 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: evsys} +children: +- type: Symbols + children: + - type: Boolean + attributes: {id: EVSYS_CHANNEL_0_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_10_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_11_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_12_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_13_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_14_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_15_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_16_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_17_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_18_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_19_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_1_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_20_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_21_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_22_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_23_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_24_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_25_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_26_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_27_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_28_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_29_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_2_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_30_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_31_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_3_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_4_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_5_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_6_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_7_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_8_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} + - type: Boolean + attributes: {id: EVSYS_CHANNEL_9_USER_READY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: evsys, value: 'false'} +- type: ElementPosition + attributes: {x: '180', y: '20', id: evsys} diff --git a/firmware/src/config/mcal/mcal.mhc/lib_qtouch.yml b/firmware/src/config/mcal/mcal.mhc/lib_qtouch.yml new file mode 100644 index 0000000..60c7063 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/lib_qtouch.yml @@ -0,0 +1,1293 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: lib_qtouch} +children: +- type: Symbols + children: + - type: KeyValueSet + attributes: {id: DEF_ANTI_TCH_RECAL_THRSHLD} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN0} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN1} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN10} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN11} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN12} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN13} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN14} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN2} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN3} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN4} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN5} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN6} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN7} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN8} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_DIGI_FILT_GAIN9} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS0} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS1} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS10} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS11} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS12} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS13} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS14} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS2} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS3} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS4} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS5} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS6} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS7} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS8} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_AKS9} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA0} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA1} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA10} + 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DEF_NOD_GAIN_ANA4} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA5} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA6} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA7} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA8} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_GAIN_ANA9} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER0} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER1} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER10} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER11} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER12} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER13} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER14} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER2} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER3} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER4} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER5} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER6} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER7} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER8} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: KeyValueSet + attributes: {id: DEF_NOD_PTC_PRESCALER9} + children: + - type: Values + children: + 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DEF_SENSOR_DET_THRESHOLD4} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_SENSOR_DET_THRESHOLD5} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_SENSOR_DET_THRESHOLD6} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_SENSOR_DET_THRESHOLD7} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_SENSOR_DET_THRESHOLD8} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_SENSOR_DET_THRESHOLD9} + children: + - type: Values + children: + - type: User + attributes: {value: '40'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY0} + children: + - type: Values + children: + - type: User + attributes: {value: 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children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY3} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY4} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY5} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY6} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY7} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - type: Integer + attributes: {id: DEF_TOUCH_CHARGE_SHARE_DELAY8} + children: + - type: Values + children: + - type: User + attributes: {value: '10'} + - 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type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_CH_6} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_CH_7} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_CH_8} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_CH_9} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_0} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_1} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_10} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_11} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_12} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_13} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_14} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_2} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_3} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_4} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_5} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_6} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_7} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_8} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_KEY_9} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_ENABLE_SCROLLER_0} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: File + attributes: {id: TOUCH_GESTURE_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: Library + attributes: {id: TOUCH_GESTURE_LIB} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: TOUCH_KEY_ENABLE_CNT} + children: + - type: Values + children: + - type: User + attributes: {value: '15'} + - type: Boolean + attributes: {id: TOUCH_LOADED} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TOUCH_PRE_GENERATE} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: String + attributes: {id: TOUCH_SCRIPT_EVENT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: ptcclock} + - type: Integer + attributes: {id: TOUCH_SCROLLER_ENABLE_CNT} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: File + attributes: {id: TOUCH_SCR_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Library + attributes: {id: TOUCH_SCR_LIB} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Integer + attributes: {id: TOUCH_SCR_SIZE0} + children: + - type: Values + children: + - type: User + attributes: {value: '5'} + - type: Integer + attributes: {id: TOUCH_SCR_START_KEY0} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: File + attributes: {id: TOUCH_SURFACE1T_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: Library + attributes: {id: TOUCH_SURFACE1T_LIB} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: String + attributes: {id: TOUCH_TIMER_INSTANCE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: RTC} + - type: Menu + attributes: {id: TOUCH_WARNING} + children: + - type: Attributes + children: + - type: String + attributes: {id: description} + children: + - {type: Value, value: Open touch configurator and save project} + - type: String + attributes: {id: label} + children: + - {type: Value, value: '!!!Warning PTC clock out of sync'} + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Integer + attributes: {id: VERT_NUM_KEY} + children: + - type: Values + children: + - type: User + attributes: {value: '5'} + - type: Integer + attributes: {id: VERT_START_KEY} + children: + - type: Values + children: + - type: User + attributes: {value: '5'} +- type: Attachments + children: + - type: DirectDependency + attributes: {id: Touch_timer} + children: + - type: Attributes + children: + - type: String + attributes: {id: targetComponentID} + children: + - {type: Value, value: rtc} + - type: String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: RTC_TMR} + - type: DirectDependency + attributes: {id: lib_acquire} + children: + - type: Attributes + children: + - type: String + attributes: {id: targetComponentID} + children: + - {type: Value, value: ptc} + - type: String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: ptc_Acq_Engine} +- type: ElementPosition + attributes: {x: '653', y: '211', id: lib_qtouch} diff --git a/firmware/src/config/mcal/mcal.mhc/nvmctrl.yml b/firmware/src/config/mcal/mcal.mhc/nvmctrl.yml new file mode 100644 index 0000000..379aab5 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/nvmctrl.yml @@ -0,0 +1,15 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: nvmctrl} +children: +- type: Symbols + children: + - type: Integer + attributes: {id: NVM_RWS} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: nvmctrl, value: '5'} +- type: ElementPosition + attributes: {x: '20', y: '20', id: nvmctrl} diff --git a/firmware/src/config/mcal/mcal.mhc/project.yml b/firmware/src/config/mcal/mcal.mhc/project.yml new file mode 100644 index 0000000..94f7469 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/project.yml @@ -0,0 +1,1300 @@ +files: +- generatedChecksum: 9D5EE038B893127B787BC03DFA6B467F + logicalPath: config/mcal + name: exceptions.c + physicalPath: '' + security: NON_SECURE + type: SOURCE + userChecksum: 9D5EE038B893127B787BC03DFA6B467F +- generatedChecksum: 42FB251FAB94DD70B6CF9DF3F0EFAC8E + logicalPath: config/mcal + name: initialization.c + physicalPath: '' + security: NON_SECURE + type: SOURCE + userChecksum: DF1DE1CDF95426864E9D23D1FBD58C02 +- generatedChecksum: 0060B9116375E8DD3C2CAA02ECA89615 + logicalPath: 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String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: ADC0_ADC} + - type: DirectCapability + attributes: {id: ptc_Acq_Engine} + children: + - type: Attributes + children: + - type: String + attributes: {id: targetComponentID} + children: + - {type: Value, value: lib_qtouch} + - type: String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: lib_acquire} +- type: ElementPosition + attributes: {x: '468', y: '253', id: ptc} diff --git a/firmware/src/config/mcal/mcal.mhc/rtc.yml b/firmware/src/config/mcal/mcal.mhc/rtc.yml new file mode 100644 index 0000000..97b0f73 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/rtc.yml @@ -0,0 +1,142 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: rtc} +children: +- type: Symbols + children: + - type: String + attributes: {id: CALLBACK_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32CallbackRegister} + - type: String + attributes: {id: COMPARE_SET_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32Compare0Set} + - type: String + attributes: {id: COUNTER_GET_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32CounterGet} + - type: String + attributes: {id: FREQUENCY_GET_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32FrequencyGet} + - type: String + attributes: {id: IRQ_ENUM_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_IRQn} + - type: String + attributes: {id: PERIOD_SET_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: ''} + - type: Boolean + attributes: {id: RTC_COUNTSYNC_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: 'false'} + - type: Hex + attributes: {id: RTC_MODE0_INTENSET} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: '256'} + - type: Boolean + attributes: {id: RTC_MODE0_INTENSET_CMP0_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: 'true'} + - type: Boolean + attributes: {id: RTC_MODE0_MATCHCLR} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: 'true'} + - type: KeyValueSet + attributes: {id: RTC_MODE0_PRESCALER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: '1'} + - type: Hex + attributes: {id: RTC_MODE0_TIMER_COMPARE0} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: '1'} + - type: KeyValueSet + attributes: {id: RTC_MODULE_SELECTION} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: lib_qtouch, value: '0'} + - type: String + attributes: {id: TIMER_PERIOD_MAX} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: '0xFFFFFFFF'} + - type: String + attributes: {id: TIMER_START_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32Start} + - type: String + attributes: {id: TIMER_STOP_API_NAME} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: RTC_Timer32Stop} + - type: Integer + attributes: {id: TIMER_WIDTH} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: rtc, value: '32'} +- type: Attachments + children: + - type: DirectCapability + attributes: {id: RTC_TMR} + children: + - type: Attributes + children: + - type: String + attributes: {id: targetComponentID} + children: + - {type: Value, value: lib_qtouch} + - type: String + attributes: {id: targetAttachmentID} + children: + - {type: Value, value: Touch_timer} +- type: ElementPosition + attributes: {x: '470', y: '159', id: rtc} diff --git a/firmware/src/config/mcal/mcal.mhc/sercom0.yml b/firmware/src/config/mcal/mcal.mhc/sercom0.yml new file mode 100644 index 0000000..9151df1 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/sercom0.yml @@ -0,0 +1,405 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: sercom0} +children: +- type: Symbols + children: + - type: Hex + attributes: {id: I2CM_BAUD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '34'} + - type: Integer + attributes: {id: I2CS_SDASETUP_TIME_NS} + children: + - type: Attributes + children: + - type: Integer + attributes: {id: max} + children: + - {type: Value, value: '2050'} + - type: Integer + attributes: {id: I2CS_SDASETUP_TIME_REG_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '1'} + - type: Boolean + attributes: {id: I2CS_SDASETUP_TIME_SUPPORT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: String + attributes: {id: RECEIVE_DATA_REGISTER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)'} + - type: KeyValueSet + attributes: {id: SERCOM_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: File + attributes: {id: SERCOM_SPIM_COMMON_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SERCOM_SPIM_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SERCOM_SPIM_SOURCE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SERCOM_USART_COMMON_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: File + attributes: {id: SERCOM_USART_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: File + attributes: {id: SERCOM_USART_SOURCE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: SPI_BAUD_RATE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Integer + attributes: {id: SPI_BAUD_REG_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '3'} + - type: KeyValueSet + attributes: {id: SPI_CHARSIZE_BITS} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Comment + attributes: {id: SPI_CLOCK_MODE_COMMENT} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '***SPI Transfer Mode 1 is Selected***'} + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: KeyValueSet + attributes: {id: SPI_CLOCK_PHASE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: SPI_CLOCK_POLARITY} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: KeyValueSet + attributes: {id: SPI_DATA_ORDER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: '1'} + - type: KeyValueSet + attributes: {id: SPI_DIPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: '3'} + - type: KeyValueSet + attributes: {id: SPI_DOPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: SPI_INTERRUPT_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: SPI_MSSEN} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: SPI_RECIEVER_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Boolean + attributes: {id: SPI_RUNSTDBY} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: String + attributes: {id: TRANSMIT_DATA_REGISTER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)'} + - type: Integer + attributes: {id: USART_BAUD_RATE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: USART_BAUD_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '50436'} + - type: KeyValueSet + attributes: {id: USART_CHARSIZE_BITS} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: String + attributes: {id: USART_DATA_BITS} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: DRV_USART_DATA_8_BIT} + - type: KeyValueSet + attributes: {id: USART_FORM} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '0'} + - type: Boolean + attributes: {id: USART_INTERRUPT_MODE_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: Boolean + attributes: {id: USART_LIN_MASTER_SUPPORTED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'true'} + - type: KeyValueSet + attributes: {id: USART_OPERATING_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_PARITY_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_RING_BUFFER_MODE_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: 'false'} + - type: Boolean + attributes: {id: USART_RUNSTDBY} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_RXPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_RX_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: USART_SAMPLE_COUNT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '16'} + - type: Integer + attributes: {id: USART_SAMPLE_RATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom0, value: '0'} + - type: Boolean + attributes: {id: USART_SFDE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_STOP_BIT} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_TXPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_TX_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} +- type: ElementPosition + attributes: {x: '15', y: '409', id: sercom0} diff --git a/firmware/src/config/mcal/mcal.mhc/sercom1.yml b/firmware/src/config/mcal/mcal.mhc/sercom1.yml new file mode 100644 index 0000000..39cf596 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/sercom1.yml @@ -0,0 +1,361 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: sercom1} +children: +- type: Symbols + children: + - type: Hex + attributes: {id: I2CM_BAUD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '4'} + - type: KeyValueSet + attributes: {id: I2CM_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: Integer + attributes: {id: I2CM_TRISE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Integer + attributes: {id: I2CS_SDASETUP_TIME_NS} + children: + - type: Attributes + children: + - type: Integer + attributes: {id: max} + children: + - {type: Value, value: '2050'} + - type: Integer + attributes: {id: I2CS_SDASETUP_TIME_REG_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '1'} + - type: Boolean + attributes: {id: I2CS_SDASETUP_TIME_SUPPORT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: I2C_ADDR_TENBITEN} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: 'false'} + - type: Integer + attributes: {id: I2C_CLOCK_SPEED} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Values + children: + - type: User + attributes: {value: '400'} + - type: Integer + attributes: {id: I2C_CLOCK_SPEED_HZ} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '400000'} + - type: Boolean + attributes: {id: I2C_RUNSTDBY} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: Integer + attributes: {id: I2C_SCLSM} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '0'} + - type: KeyValueSet + attributes: {id: I2C_SDAHOLD_TIME} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'true'} + - type: String + attributes: {id: RECEIVE_DATA_REGISTER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: ''} + - type: File + attributes: {id: SERCOM_I2CM_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SERCOM_I2CM_MASTER_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: File + attributes: {id: SERCOM_I2CM_SOURCE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'true'} + - type: KeyValueSet + attributes: {id: SERCOM_MODE} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} + - type: File + attributes: {id: SERCOM_USART_COMMON_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: File + attributes: {id: SERCOM_USART_HEADER} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: File + attributes: {id: SERCOM_USART_SOURCE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: enabled} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: SPI_BAUD_REG_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '3'} + - type: String + attributes: {id: TRANSMIT_DATA_REGISTER} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: ''} + - type: Integer + attributes: {id: USART_BAUD_RATE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: USART_BAUD_VALUE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '50436'} + - type: KeyValueSet + attributes: {id: USART_CHARSIZE_BITS} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: String + attributes: {id: USART_DATA_BITS} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: DRV_USART_DATA_8_BIT} + - type: KeyValueSet + attributes: {id: USART_FORM} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '0'} + - type: Boolean + attributes: {id: USART_INTERRUPT_MODE_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: Boolean + attributes: {id: USART_LIN_MASTER_SUPPORTED} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'true'} + - type: KeyValueSet + attributes: {id: USART_OPERATING_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_PARITY_MODE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_RING_BUFFER_MODE_ENABLE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: 'false'} + - type: Boolean + attributes: {id: USART_RUNSTDBY} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_RXPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_RX_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Integer + attributes: {id: USART_SAMPLE_COUNT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '16'} + - type: Integer + attributes: {id: USART_SAMPLE_RATE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: sercom1, value: '0'} + - type: Boolean + attributes: {id: USART_SFDE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_STOP_BIT} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: USART_TXPO} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: Boolean + attributes: {id: USART_TX_ENABLE} + children: + - type: Attributes + children: + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} +- type: ElementPosition + attributes: {x: '140', y: '411', id: sercom1} diff --git a/firmware/src/config/mcal/mcal.mhc/settings.yml b/firmware/src/config/mcal/mcal.mhc/settings.yml new file mode 100644 index 0000000..e72d59d --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/settings.yml @@ -0,0 +1,14 @@ +configName: mcal +folderName: p417 +format_version: v1.0 +frameworkPath: ..\..\Microchip\Harmony3 +processor: ATSAME51J19A +projectName: p417 +settings: + PackageFilter: csp;dev_packs;harmony-services;quick_docs;touch;touch_apps + FORCE_OPTIMIZATION: 'false' + GENERATE_BACKUP: 'true' + TRUSTZONE: 'false' + CMSISPath: .\dev_packs\arm\CMSIS\5.8.0 + MERGE_STRATEGY: USER_ALL + DFPPath: .\dev_packs\Microchip\SAME51_DFP\3.6.130\atdf\ATSAME51J19A.atdf diff --git a/firmware/src/config/mcal/mcal.mhc/tc0.yml b/firmware/src/config/mcal/mcal.mhc/tc0.yml new file mode 100644 index 0000000..bbeb8e8 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/tc0.yml @@ -0,0 +1,73 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: tc0} +children: +- type: Symbols + children: + - type: Comment + attributes: {id: TC_COMPARE_PERIOD_COMMENT} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** Compare Period is 24.0 us ****'} + - type: KeyValueSet + attributes: {id: TC_CTRLA_PRESCALER} + children: + - type: Values + children: + - type: User + attributes: {value: '0'} + - type: Integer + attributes: {id: TC_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: '1000000'} + - type: Comment + attributes: {id: TC_Resolution} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '****Timer resolution is 1000.0 nS****'} + - type: Long + attributes: {id: TC_TIMER_PERIOD} + children: + - type: Attributes + children: + - type: Long + attributes: {id: max} + children: + - {type: Value, value: '65535'} + - type: Values + children: + - type: Dynamic + attributes: {id: tc0, value: '125'} + - type: Float + attributes: {id: TC_TIMER_TIME_MS} + children: + - type: Attributes + children: + - type: Float + attributes: {id: max} + children: + - {type: Value, value: '65536.0'} + - type: Values + children: + - type: User + attributes: {value: '125.0'} + - type: Combo + attributes: {id: TC_TIMER_UNIT} + children: + - type: Values + children: + - type: User + attributes: {value: microsecond} +- type: ElementPosition + attributes: {x: '296', y: '427', id: tc0} diff --git a/firmware/src/config/mcal/mcal.mhc/tcc0.yml b/firmware/src/config/mcal/mcal.mhc/tcc0.yml new file mode 100644 index 0000000..7b304e3 --- /dev/null +++ b/firmware/src/config/mcal/mcal.mhc/tcc0.yml @@ -0,0 +1,211 @@ +format_version: v1.0 +type: UniqueComponent +attributes: {id: tcc0} +children: +- type: Symbols + children: + - type: String + attributes: {id: INTR_PWM_FAULT} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_OTHER_IRQn} + - type: String + attributes: {id: PWM_CALLBACK_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWMCallbackRegister} + - type: String + attributes: {id: PWM_GET_PERIOD_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWM24bitPeriodGet} + - type: String + attributes: {id: PWM_OUTPUT_DISABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWMPatternSet} + - type: String + attributes: {id: PWM_OUTPUT_ENABLE_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWMPatternSet} + - type: Hex + attributes: {id: PWM_PATTERN_MASK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: '119'} + - type: Hex + attributes: {id: PWM_PH_MASK} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: '7'} + - type: String + attributes: {id: PWM_PH_U} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0CHANNEL0} + - type: String + attributes: {id: PWM_PH_V} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0CHANNEL1} + - type: String + attributes: {id: PWM_PH_W} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0CHANNEL2} + - type: String + attributes: {id: PWM_SET_DUTY_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWM24bitDutySet} + - type: String + attributes: {id: PWM_START_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWMStart} + - type: String + attributes: {id: PWM_STOP_API} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: TCC0_PWMStop} + - type: Boolean + attributes: {id: TCC_0_WEXCTRL_DTIEN} + children: + - type: Values + children: + - type: User + attributes: {value: 'false'} + - type: Comment + attributes: {id: TCC_COMPARE_PERIOD_COMMENT} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** Waveform Period is 65535.0 us ****'} + - type: Boolean + attributes: {id: visible} + children: + - {type: Value, value: 'false'} + - type: KeyValueSet + attributes: {id: TCC_CTRLA_PRESCALER} + children: + - type: Values + children: + - type: User + attributes: {value: '3'} + - type: Comment + attributes: {id: TCC_DTHS_COMMENT} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** High side dead time is 8.0 uS ****'} + - type: Comment + attributes: {id: TCC_DTLS_COMMENT} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** Low side dead time is 8.0 uS ****'} + - type: Comment + attributes: {id: TCC_FREQUENCY} + children: + - type: Attributes + children: + - type: String + attributes: {id: text} + children: + - {type: Value, value: '**** PWM Frequency is 124 Hz ****'} + - type: Boolean + attributes: {id: TCC_INTENSET_MC_0} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Boolean + attributes: {id: TCC_INTENSET_OVF} + children: + - type: Values + children: + - type: User + attributes: {value: 'true'} + - type: Integer + attributes: {id: TCC_MODULE_FREQUENCY} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: '1000000'} + - type: Integer + attributes: {id: TCC_PER_PER} + children: + - type: Values + children: + - type: User + attributes: {value: '8000'} + - type: Boolean + attributes: {id: TCC_PWM_INTERRUPT_MODE} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: 'true'} + - type: Long + attributes: {id: TCC_TIMER_PERIOD} + children: + - type: Values + children: + - type: Dynamic + attributes: {id: tcc0, value: '1000'} + - type: Float + attributes: {id: TCC_TIMER_TIME_MS} + children: + - type: Attributes + children: + - type: Float + attributes: {id: max} + children: + - {type: Value, value: '16777.217'} + - type: KeyValueSet + attributes: {id: TCC_WEXCTRL_OTMX} + children: + - type: Values + children: + - type: User + attributes: {value: '2'} +- type: ElementPosition + attributes: {x: '21', y: '125', id: tcc0} diff --git a/firmware/src/config/mcal/peripheral/adc/plib_adc0.c b/firmware/src/config/mcal/peripheral/adc/plib_adc0.c new file mode 100644 index 0000000..30a7d6a --- /dev/null +++ b/firmware/src/config/mcal/peripheral/adc/plib_adc0.c @@ -0,0 +1,232 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.c + + Summary + ADC0 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_adc0.h" +#include "interrupts.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +#define ADC0_BIASCOMP_POS (2U) +#define ADC0_BIASCOMP_Msk (0x7U << ADC0_BIASCOMP_POS) + +#define ADC0_BIASREFBUF_POS (5U) +#define ADC0_BIASREFBUF_Msk (0x7U << ADC0_BIASREFBUF_POS) + +#define ADC0_BIASR2R_POS (8U) +#define ADC0_BIASR2R_Msk (0x7UL << ADC0_BIASR2R_POS) + + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC0 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC0_Initialize( void ) +{ + /* Reset ADC */ + ADC0_REGS->ADC_CTRLA = ADC_CTRLA_SWRST_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + + /* Writing calibration values in BIASREFBUF, BIASCOMP and BIASR2R */ + ADC0_REGS->ADC_CALIB =(uint16_t)((ADC_CALIB_BIASCOMP((((*(uint32_t*)SW0_ADDR) & ADC0_BIASCOMP_Msk) >> ADC0_BIASCOMP_POS))) \ + | ADC_CALIB_BIASR2R((((*(uint32_t*)SW0_ADDR) & ADC0_BIASR2R_Msk) >> ADC0_BIASR2R_POS)) + | ADC_CALIB_BIASREFBUF(((*(uint32_t*)SW0_ADDR) & ADC0_BIASREFBUF_Msk)>> ADC0_BIASREFBUF_POS )); + + /* prescaler */ + ADC0_REGS->ADC_CTRLA = ADC_CTRLA_PRESCALER_DIV8; + + /* Sampling length */ + ADC0_REGS->ADC_SAMPCTRL = ADC_SAMPCTRL_SAMPLEN(3U); + + /* reference */ + ADC0_REGS->ADC_REFCTRL = ADC_REFCTRL_REFSEL_INTVCC1; + + + /* positive and negative input pins */ + ADC0_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0 | (uint16_t) ADC_NEGINPUT_GND ; + + /* Resolution & Operation Mode */ + ADC0_REGS->ADC_CTRLB = ADC_CTRLB_RESSEL_12BIT | ADC_CTRLB_WINMODE(0U) | ADC_CTRLB_FREERUN_Msk; + + + /* Clear all interrupt flags */ + ADC0_REGS->ADC_INTFLAG = ADC_INTFLAG_Msk; + + while(ADC0_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC0_Enable( void ) +{ + ADC0_REGS->ADC_CTRLA |= ADC_CTRLA_ENABLE_Msk; + while(ADC0_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC0_Disable( void ) +{ + ADC0_REGS->ADC_CTRLA &=(uint16_t) ~ADC_CTRLA_ENABLE_Msk; + while(ADC0_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure positive and negative input pins */ + uint16_t channel; + channel = ADC0_REGS->ADC_INPUTCTRL; + channel &= (uint16_t)~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_MUXNEG_Msk); + channel |= (uint16_t) positiveInput | (uint16_t) negativeInput; + ADC0_REGS->ADC_INPUTCTRL = channel; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC0_ConversionStart( void ) +{ + /* Start conversion */ + ADC0_REGS->ADC_SWTRIG |= ADC_SWTRIG_START_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure window comparison threshold values */ +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC0_REGS->ADC_WINLT = low_threshold; + ADC0_REGS->ADC_WINUT = high_threshold; + while(ADC0_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +void ADC0_WindowModeSet(ADC_WINMODE mode) +{ + ADC0_REGS->ADC_CTRLB &= (uint16_t)~ADC_CTRLB_WINMODE_Msk; + ADC0_REGS->ADC_CTRLB |= (uint16_t)mode << ADC_CTRLB_WINMODE_Pos; + while(ADC0_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC0_ConversionResultGet( void ) +{ + return (uint16_t)ADC0_REGS->ADC_RESULT; +} + +/* Read the last conversion result */ +uint16_t ADC0_LastConversionResultGet( void ) +{ + return (uint16_t)ADC0_REGS->ADC_RESS; +} + +void ADC0_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTFLAG = interruptMask; +} + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENSET = interruptMask; +} + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENCLR = interruptMask; +} + +/* Check whether result is ready */ +bool ADC0_ConversionStatusGet( void ) +{ + bool status; + status = (((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); + if (status == true) + { + /* Clear interrupt flag */ + ADC0_REGS->ADC_INTFLAG = ADC_INTFLAG_RESRDY_Msk; + } + return status; +} + diff --git a/firmware/src/config/mcal/peripheral/adc/plib_adc0.h b/firmware/src/config/mcal/peripheral/adc/plib_adc0.h new file mode 100644 index 0000000..6722789 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/adc/plib_adc0.h @@ -0,0 +1,127 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.h + + Summary + ADC0 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC0_H // Guards against multiple inclusion +#define PLIB_ADC0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC0_Initialize( void ); + +void ADC0_Enable( void ); + +void ADC0_Disable( void ); + +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC0_ConversionStart( void ); + +uint16_t ADC0_ConversionResultGet( void ); + +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC0_WindowModeSet(ADC_WINMODE mode); + +uint16_t ADC0_LastConversionResultGet( void ); + +void ADC0_InterruptsClear(ADC_STATUS interruptMask); + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask); + + +bool ADC0_ConversionStatusGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC0_H */ diff --git a/firmware/src/config/mcal/peripheral/adc/plib_adc1.c b/firmware/src/config/mcal/peripheral/adc/plib_adc1.c new file mode 100644 index 0000000..a9620b5 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/adc/plib_adc1.c @@ -0,0 +1,240 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.c + + Summary + ADC1 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_adc1.h" +#include "interrupts.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +static ADC_CALLBACK_OBJ ADC1_CallbackObject; + +#define ADC1_BIASCOMP_POS (16U) +#define ADC1_BIASCOMP_Msk (0x7UL << ADC1_BIASCOMP_POS) + +#define ADC1_BIASREFBUF_POS (19U) +#define ADC1_BIASREFBUF_Msk (0x7UL << ADC1_BIASREFBUF_POS) + +#define ADC1_BIASR2R_POS (22U) +#define ADC1_BIASR2R_Msk (0x7UL << ADC1_BIASR2R_POS) + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC1 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC1_Initialize( void ) +{ + /* Reset ADC */ + ADC1_REGS->ADC_CTRLA = ADC_CTRLA_SWRST_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + + /* Writing calibration values in BIASREFBUF, BIASCOMP and BIASR2R */ + ADC1_REGS->ADC_CALIB =(uint16_t)((ADC_CALIB_BIASCOMP((((*(uint32_t*)SW0_ADDR) & ADC1_BIASCOMP_Msk) >> ADC1_BIASCOMP_POS))) \ + | ADC_CALIB_BIASR2R((((*(uint32_t*)SW0_ADDR) & ADC1_BIASR2R_Msk) >> ADC1_BIASR2R_POS)) + | ADC_CALIB_BIASREFBUF(((*(uint32_t*)SW0_ADDR) & ADC1_BIASREFBUF_Msk)>> ADC1_BIASREFBUF_POS )); + + /* prescaler */ + ADC1_REGS->ADC_CTRLA = ADC_CTRLA_PRESCALER_DIV8; + + /* Sampling length */ + ADC1_REGS->ADC_SAMPCTRL = ADC_SAMPCTRL_SAMPLEN(27U); + + /* reference */ + ADC1_REGS->ADC_REFCTRL = ADC_REFCTRL_REFSEL_INTVCC1; + + + /* positive and negative input pins */ + ADC1_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN6 | (uint16_t) ADC_NEGINPUT_GND ; + + /* Resolution & Operation Mode */ + ADC1_REGS->ADC_CTRLB = ADC_CTRLB_RESSEL_12BIT | ADC_CTRLB_WINMODE(0U) ; + + + /* Clear all interrupt flags */ + ADC1_REGS->ADC_INTFLAG = ADC_INTFLAG_Msk; + /* Enable interrupts */ + ADC1_REGS->ADC_INTENSET = ADC_INTENSET_RESRDY_Msk; + + while(ADC1_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC1_Enable( void ) +{ + ADC1_REGS->ADC_CTRLA |= ADC_CTRLA_ENABLE_Msk; + while(ADC1_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC1_Disable( void ) +{ + ADC1_REGS->ADC_CTRLA &=(uint16_t) ~ADC_CTRLA_ENABLE_Msk; + while(ADC1_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure positive and negative input pins */ + uint16_t channel; + channel = ADC1_REGS->ADC_INPUTCTRL; + channel &= (uint16_t)~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_MUXNEG_Msk); + channel |= (uint16_t) positiveInput | (uint16_t) negativeInput; + ADC1_REGS->ADC_INPUTCTRL = channel; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC1_ConversionStart( void ) +{ + /* Start conversion */ + ADC1_REGS->ADC_SWTRIG |= ADC_SWTRIG_START_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure window comparison threshold values */ +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC1_REGS->ADC_WINLT = low_threshold; + ADC1_REGS->ADC_WINUT = high_threshold; + while(ADC1_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +void ADC1_WindowModeSet(ADC_WINMODE mode) +{ + ADC1_REGS->ADC_CTRLB &= (uint16_t)~ADC_CTRLB_WINMODE_Msk; + ADC1_REGS->ADC_CTRLB |= (uint16_t)mode << ADC_CTRLB_WINMODE_Pos; + while(ADC1_REGS->ADC_SYNCBUSY != 0U) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC1_ConversionResultGet( void ) +{ + return (uint16_t)ADC1_REGS->ADC_RESULT; +} + +/* Read the last conversion result */ +uint16_t ADC1_LastConversionResultGet( void ) +{ + return (uint16_t)ADC1_REGS->ADC_RESS; +} + +void ADC1_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTFLAG = interruptMask; +} + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENSET = interruptMask; +} + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENCLR = interruptMask; +} + +/* Register callback function */ +void ADC1_CallbackRegister( ADC_CALLBACK callback, uintptr_t context ) +{ + ADC1_CallbackObject.callback = callback; + + ADC1_CallbackObject.context = context; +} + +void ADC1_RESRDY_InterruptHandler( void ) +{ + ADC_STATUS status; + status = (ADC_STATUS) (ADC1_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk); + /* Clear interrupt flag */ + ADC1_REGS->ADC_INTFLAG = ADC_INTFLAG_RESRDY_Msk; + if (ADC1_CallbackObject.callback != NULL) + { + ADC1_CallbackObject.callback(status, ADC1_CallbackObject.context); + } +} diff --git a/firmware/src/config/mcal/peripheral/adc/plib_adc1.h b/firmware/src/config/mcal/peripheral/adc/plib_adc1.h new file mode 100644 index 0000000..8fdd848 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/adc/plib_adc1.h @@ -0,0 +1,128 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.h + + Summary + ADC1 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC1_H // Guards against multiple inclusion +#define PLIB_ADC1_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC1_Initialize( void ); + +void ADC1_Enable( void ); + +void ADC1_Disable( void ); + +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC1_ConversionStart( void ); + +uint16_t ADC1_ConversionResultGet( void ); + +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC1_WindowModeSet(ADC_WINMODE mode); + +uint16_t ADC1_LastConversionResultGet( void ); + +void ADC1_InterruptsClear(ADC_STATUS interruptMask); + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask); + + +void ADC1_CallbackRegister( ADC_CALLBACK callback, uintptr_t context ); + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC1_H */ diff --git a/firmware/src/config/mcal/peripheral/adc/plib_adc_common.h b/firmware/src/config/mcal/peripheral/adc/plib_adc_common.h new file mode 100644 index 0000000..542fc29 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/adc/plib_adc_common.h @@ -0,0 +1,160 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC) Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_adc_common.h + + Summary + ADC Peripheral Library Interface Header File. + + Description + This file defines the common types for the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC_COMMON_H // Guards against multiple inclusion +#define PLIB_ADC_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +#define ADC_STATUS_NONE (0U) +#define ADC_STATUS_RESRDY (ADC_INTFLAG_RESRDY_Msk) +#define ADC_STATUS_OVERRUN (ADC_INTFLAG_OVERRUN_Msk) +#define ADC_STATUS_WINMON (ADC_INTFLAG_WINMON_Msk) +#define ADC_STATUS_MASK (ADC_STATUS_RESRDY | ADC_STATUS_OVERRUN | ADC_STATUS_WINMON) + +typedef uint8_t ADC_STATUS; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +typedef enum +{ + ADC_POSINPUT_AIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, + ADC_POSINPUT_AIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, + ADC_POSINPUT_AIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, + ADC_POSINPUT_AIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, + ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, + ADC_POSINPUT_AIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, + ADC_POSINPUT_AIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, + ADC_POSINPUT_AIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, + ADC_POSINPUT_AIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, + ADC_POSINPUT_AIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, + ADC_POSINPUT_AIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, + ADC_POSINPUT_AIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, + ADC_POSINPUT_AIN12 = ADC_INPUTCTRL_MUXPOS_AIN12, + ADC_POSINPUT_AIN13 = ADC_INPUTCTRL_MUXPOS_AIN13, + ADC_POSINPUT_AIN14 = ADC_INPUTCTRL_MUXPOS_AIN14, + ADC_POSINPUT_AIN15 = ADC_INPUTCTRL_MUXPOS_AIN15, + ADC_POSINPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + ADC_POSINPUT_SCALEDVBAT = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT, + ADC_POSINPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + ADC_POSINPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + ADC_POSINPUT_PTAT = ADC_INPUTCTRL_MUXPOS_PTAT, + ADC_POSINPUT_CTAT = ADC_INPUTCTRL_MUXPOS_CTAT, + ADC_POSINPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, + ADC_POSINPUT_PTC = ADC_INPUTCTRL_MUXPOS_PTC, +}ADC_POSINPUT; + +// ***************************************************************************** + +typedef enum +{ + ADC_NEGINPUT_AIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, + ADC_NEGINPUT_AIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, + ADC_NEGINPUT_AIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, + ADC_NEGINPUT_AIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, + ADC_NEGINPUT_AIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, + ADC_NEGINPUT_AIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, + ADC_NEGINPUT_AIN6 = ADC_INPUTCTRL_MUXNEG_AIN6, + ADC_NEGINPUT_AIN7 = ADC_INPUTCTRL_MUXNEG_AIN7, + ADC_NEGINPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, +}ADC_NEGINPUT; + + +typedef enum +{ + ADC_WINMODE_DISABLED = ADC_CTRLB_WINMODE_DISABLE_Val, + ADC_WINMODE_GREATER_THAN_WINLT = ADC_CTRLB_WINMODE_MODE1_Val, + ADC_WINMODE_LESS_THAN_WINUT = ADC_CTRLB_WINMODE_MODE2_Val, + ADC_WINMODE_BETWEEN_WINLT_AND_WINUT = ADC_CTRLB_WINMODE_MODE3_Val, + ADC_WINMODE_OUTSIDE_WINLT_AND_WINUT = ADC_CTRLB_WINMODE_MODE4_Val +}ADC_WINMODE; +// ***************************************************************************** + + +typedef void (*ADC_CALLBACK)(ADC_STATUS status, uintptr_t context); + + +typedef struct +{ + ADC_CALLBACK callback; + + uintptr_t context; + +} ADC_CALLBACK_OBJ; + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC_COMMON_H*/ diff --git a/firmware/src/config/mcal/peripheral/can/plib_can1.c b/firmware/src/config/mcal/peripheral/can/plib_can1.c new file mode 100644 index 0000000..1a4be8d --- /dev/null +++ b/firmware/src/config/mcal/peripheral/can/plib_can1.c @@ -0,0 +1,835 @@ +/******************************************************************************* + Controller Area Network (CAN) Peripheral Library Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_can1.c + + Summary: + CAN peripheral library interface. + + Description: + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Header Includes +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include "interrupts.h" +#include "plib_can1.h" + +// ***************************************************************************** +// ***************************************************************************** +// Global Data +// ***************************************************************************** +// ***************************************************************************** +#define CAN_STD_ID_Msk 0x7FFU + +static CAN_TX_FIFO_CALLBACK_OBJ can1TxFifoCallbackObj; +static CAN_TX_EVENT_FIFO_CALLBACK_OBJ can1TxEventFifoCallbackObj; +static CAN_RX_FIFO_CALLBACK_OBJ can1RxFifoCallbackObj[2]; +static CAN_CALLBACK_OBJ can1CallbackObj; +static CAN_OBJ can1Obj; + +static const can_sidfe_registers_t can1StdFilter[] = +{ + { + .CAN_SIDFE_0 = CAN_SIDFE_0_SFT(0UL) | + CAN_SIDFE_0_SFID1(0x0UL) | + CAN_SIDFE_0_SFID2(0x7ffUL) | + CAN_SIDFE_0_SFEC(1UL) + }, +}; + +// ***************************************************************************** +// ***************************************************************************** +// CAN1 PLib Interface Routines +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void CAN1_Initialize(void) + + Summary: + Initializes given instance of the CAN peripheral. + + Precondition: + None. + + Parameters: + None. + + Returns: + None +*/ +void CAN1_Initialize(void) +{ + /* Start CAN initialization */ + CAN1_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Nominal Bit timing and Prescaler Register */ + CAN1_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(2UL) | CAN_NBTP_NTSEG1(11UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(2UL); + + + /* Global Filter Configuration Register */ + CAN1_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + + /* Set the operation mode */ + + + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Select interrupt line */ + CAN1_REGS->CAN_ILS = 0x0U; + + /* Enable interrupt line */ + CAN1_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; + + /* Enable CAN interrupts */ + CAN1_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk + | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk + | CAN_IE_TFEE_Msk + | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk + | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk + | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk + + | CAN_IE_MRAFE_Msk; + + (void) memset(&can1Obj.msgRAMConfig, 0x00, sizeof(CAN_MSG_RAM_CONFIG)); +} + + +// ***************************************************************************** +/* Function: + bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + + Summary: + Transmit multiple messages into CAN bus from Tx FIFO. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfMessage - Total number of message. + txBuffer - Pointer to Tx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +{ + uint8_t *txFifo = NULL; + uint8_t *txBuf = (uint8_t *)txBuffer; + uint32_t bufferNumber = 0U; + uint8_t tfqpi = 0U; + uint8_t count = 0U; + bool transmitFifo_event = false; + + if (!(((numberOfMessage < 1U) || (numberOfMessage > 16U)) || (txBuffer == NULL))) + { + tfqpi = (uint8_t)((CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + + for (count = 0U; count < numberOfMessage; count++) + { + txFifo = (uint8_t *)((uint8_t*)can1Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE)); + + (void) memcpy(txFifo, txBuf, CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE); + + txBuf += CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE; + bufferNumber |= (1UL << tfqpi); + tfqpi++; + if (tfqpi == 16U) + { + tfqpi = 0U; + } + } + + /* Set Transmission request */ + CAN1_REGS->CAN_TXBAR = bufferNumber; + + transmitFifo_event = true; + } + return transmitFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN1_TxFifoFreeLevelGet(void) + + Summary: + Returns Tx FIFO Free Level. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx FIFO Free Level. +*/ +uint8_t CAN1_TxFifoFreeLevelGet(void) +{ + return (uint8_t)(CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); +} + +// ***************************************************************************** +/* Function: + bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) + + Summary: + Check if Transmission request is pending for the specific Tx buffer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + true - Transmission request is pending. + false - Transmission request is not pending. +*/ +bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) +{ + return ((CAN1_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); +} + +// ***************************************************************************** +/* Function: + bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + + Summary: + Read Tx Event FIFO for the transmitted messages. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfTxEvent - Total number of Tx Event + txEventFifo - Pointer to Tx Event FIFO + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +{ + uint8_t txefgi = 0U; + uint8_t count = 0U; + uint8_t *txEvent = NULL; + uint8_t *txEvtFifo = (uint8_t *)txEventFifo; + bool txFifo_event = false; + + if (txEventFifo != NULL) + { + /* Read data from the Rx FIFO0 */ + txefgi = (uint8_t)((CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + for (count = 0U; count < numberOfTxEvent; count++) + { + txEvent = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); + + (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); + + if ((count + 1U) == numberOfTxEvent) + { + break; + } + txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); + txefgi++; + if (txefgi == 16U) + { + txefgi = 0U; + } + } + + /* Ack the Tx Event FIFO position */ + CAN1_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + txFifo_event = true; + } + return txFifo_event; +} + + +// ***************************************************************************** +/* Function: + bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + + Summary: + Read messages from Rx FIFO0/FIFO1. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO number + numberOfMessage - Total number of message + rxBuffer - Pointer to Rx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +{ + uint8_t rxgi = 0U; + uint8_t count = 0U; + uint8_t *rxFifo = NULL; + uint8_t *rxBuf = (uint8_t *)rxBuffer; + bool status = false; + + if (rxBuffer != NULL) + { + switch (rxFifoNum) + { + case CAN_RX_FIFO_0: + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN1_RX_FIFO0_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO0_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN1_RX_FIFO0_ELEMENT_SIZE; + rxgi++; + if (rxgi == 8U) + { + rxgi = 0U; + } + } + + /* Ack the fifo position */ + CAN1_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + status = true; + break; + case CAN_RX_FIFO_1: + /* Read data from the Rx FIFO1 */ + rxgi = (uint8_t)((CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN1_RX_FIFO1_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO1_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN1_RX_FIFO1_ELEMENT_SIZE; + rxgi++; + if (rxgi == 8U) + { + rxgi = 0U; + } + } + /* Ack the fifo position */ + CAN1_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); + + status = true; + break; + default: + /* Do nothing */ + break; + } + } + return status; +} + +// ***************************************************************************** +/* Function: + CAN_ERROR CAN1_ErrorGet(void) + + Summary: + Returns the error during transfer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Error during transfer. +*/ +CAN_ERROR CAN1_ErrorGet(void) +{ + CAN_ERROR error; + uint32_t errorStatus = CAN1_REGS->CAN_PSR; + + error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) + | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); + + if ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + } + + return error; +} + +// ***************************************************************************** +/* Function: + void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) + + Summary: + Returns the transmit and receive error count during transfer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + txErrorCount - Transmit Error Count to be received + rxErrorCount - Receive Error Count to be received + + Returns: + None. +*/ +void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) +{ + *txErrorCount = (uint8_t)(CAN1_REGS->CAN_ECR & CAN_ECR_TEC_Msk); + *rxErrorCount = (uint8_t)((CAN1_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); +} + +// ***************************************************************************** +/* Function: + void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) + + Summary: + Set the Message RAM Configuration. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. + Application must allocate buffer from non-cached + contiguous memory and buffer size must be + CAN1_MESSAGE_RAM_CONFIG_SIZE + + Returns: + None +*/ +void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) +{ + uint32_t offset = 0U; + + (void) memset(msgRAMConfigBaseAddress, 0x00, CAN1_MESSAGE_RAM_CONFIG_SIZE); + + /* Set CAN CCCR Init for Message RAM Configuration */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + can1Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddress; + offset = CAN1_RX_FIFO0_SIZE; + /* Receive FIFO 0 Configuration Register */ + CAN1_REGS->CAN_RXF0C = CAN_RXF0C_F0S(8UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN_RXF0C_F0SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO0Address); + + can1Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddress + offset); + offset += CAN1_RX_FIFO1_SIZE; + /* Receive FIFO 1 Configuration Register */ + CAN1_REGS->CAN_RXF1C = CAN_RXF1C_F1S(8UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | + CAN_RXF1C_F1SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO1Address); + + can1Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddress + offset); + offset += CAN1_TX_FIFO_BUFFER_SIZE; + /* Transmit Buffer/FIFO Configuration Register */ + CAN1_REGS->CAN_TXBC = CAN_TXBC_TFQS(16UL) | + CAN_TXBC_TBSA((uint32_t)can1Obj.msgRAMConfig.txBuffersAddress); + + can1Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddress + offset); + offset += CAN1_TX_EVENT_FIFO_SIZE; + /* Transmit Event FIFO Configuration Register */ + CAN1_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(16UL) | + CAN_TXEFC_EFSA((uint32_t)can1Obj.msgRAMConfig.txEventFIFOAddress); + + can1Obj.msgRAMConfig.stdMsgIDFilterAddress = (can_sidfe_registers_t *)(msgRAMConfigBaseAddress + offset); + (void) memcpy(can1Obj.msgRAMConfig.stdMsgIDFilterAddress, + (const void *)can1StdFilter, + CAN1_STD_MSG_ID_FILTER_SIZE); + offset += CAN1_STD_MSG_ID_FILTER_SIZE; + /* Standard ID Filter Configuration Register */ + CAN1_REGS->CAN_SIDFC = CAN_SIDFC_LSS(1UL) | + CAN_SIDFC_FLSSA((uint32_t)can1Obj.msgRAMConfig.stdMsgIDFilterAddress); + + + /* Reference offset variable once to remove warning about the variable not being used after increment */ + (void)offset; + + /* Complete Message RAM Configuration by clearing CAN CCCR Init */ + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for configuration complete */ + } +} + +// ***************************************************************************** +/* Function: + bool CAN1_StandardFilterElementSet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement) + + Summary: + Set a standard filter element configuration. + + Precondition: + CAN1_Initialize and CAN1_MessageRAMConfigSet must have been called + for the associated CAN instance. + + Parameters: + filterNumber - Standard Filter number to be configured. + stdMsgIDFilterElement - Pointer to Standard Filter Element configuration to be set on specific filterNumber. + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_StandardFilterElementSet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement) +{ + bool retval = false; + if (!((filterNumber > 1U) || (stdMsgIDFilterElement == NULL))) + { + can1Obj.msgRAMConfig.stdMsgIDFilterAddress[filterNumber - 1U].CAN_SIDFE_0 = stdMsgIDFilterElement->CAN_SIDFE_0; + retval = true; + } + return retval; +} + +// ***************************************************************************** +/* Function: + bool CAN1_StandardFilterElementGet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement) + + Summary: + Get a standard filter element configuration. + + Precondition: + CAN1_Initialize and CAN1_MessageRAMConfigSet must have been called + for the associated CAN instance. + + Parameters: + filterNumber - Standard Filter number to get filter configuration. + stdMsgIDFilterElement - Pointer to Standard Filter Element configuration for storing filter configuration. + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_StandardFilterElementGet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement) +{ + bool retval = false; + if (!((filterNumber > 1U) || (stdMsgIDFilterElement == NULL))) + { + stdMsgIDFilterElement->CAN_SIDFE_0 = can1Obj.msgRAMConfig.stdMsgIDFilterAddress[filterNumber - 1U].CAN_SIDFE_0; + retval = true; + } + return retval; +} + + +void CAN1_SleepModeEnter(void) +{ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) + { + /* Wait for clock stop request to complete */ + } +} + +void CAN1_SleepModeExit(void) +{ + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) + { + /* Wait for no clock stop */ + } + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } +} + + +// ***************************************************************************** +/* Function: + void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1TxFifoCallbackObj.callback = callback; + can1TxFifoCallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_EVENT_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1TxEventFifoCallbackObj.callback = callback; + can1TxEventFifoCallbackObj.context = contextHandle; + + } +} + + +// ***************************************************************************** +/* Function: + void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO Number + + callback - A pointer to a function with a calling signature defined + by the CAN_RX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1RxFifoCallbackObj[rxFifoNum].callback = callback; + can1RxFifoCallbackObj[rxFifoNum].context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1CallbackObj.callback = callback; + can1CallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_InterruptHandler(void) + + Summary: + CAN1 Peripheral Interrupt Handler. + + Description: + This function is CAN1 Peripheral Interrupt Handler and will + called on every CAN1 interrupt. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Remarks: + The function is called as peripheral instance's interrupt handler if the + instance interrupt is enabled. If peripheral instance's interrupt is not + enabled user need to call it from the main while loop of the application. +*/ +void CAN1_InterruptHandler(void) +{ + uint8_t numberOfMessage = 0; + uint8_t numberOfTxEvent = 0; + + uint32_t ir = CAN1_REGS->CAN_IR; + + if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) + { + CAN1_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); + if (can1CallbackObj.callback != NULL) + { + can1CallbackObj.callback(ir, can1CallbackObj.context); + } + } + /* New Message in Rx FIFO 0 */ + if ((ir & CAN_IR_RF0N_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_RF0N_Msk; + + numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); + + if (can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) + { + can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, can1RxFifoCallbackObj[CAN_RX_FIFO_0].context); + } + } + /* New Message in Rx FIFO 1 */ + if ((ir & CAN_IR_RF1N_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_RF1N_Msk; + + numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); + + if (can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) + { + can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, can1RxFifoCallbackObj[CAN_RX_FIFO_1].context); + } + } + + /* TX FIFO is empty */ + if ((ir & CAN_IR_TFE_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_TFE_Msk; + if (can1TxFifoCallbackObj.callback != NULL) + { + can1TxFifoCallbackObj.callback(can1TxFifoCallbackObj.context); + } + } + /* Tx Event FIFO new entry */ + if ((ir & CAN_IR_TEFN_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_TEFN_Msk; + + numberOfTxEvent = (uint8_t)(CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); + + if (can1TxEventFifoCallbackObj.callback != NULL) + { + can1TxEventFifoCallbackObj.callback(numberOfTxEvent, can1TxEventFifoCallbackObj.context); + } + } +} + +/******************************************************************************* + End of File +*/ diff --git a/firmware/src/config/mcal/peripheral/can/plib_can1.h b/firmware/src/config/mcal/peripheral/can/plib_can1.h new file mode 100644 index 0000000..dfb5fb2 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/can/plib_can1.h @@ -0,0 +1,122 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_can1.h + + Summary: + CAN PLIB interface declarations. + + Description: + The CAN plib provides a simple interface to manage the CAN modules on + Microchip microcontrollers. This file defines the interface declarations + for the CAN plib. + + Remarks: + None. + +*******************************************************************************/ +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END + +#ifndef PLIB_CAN1_H +#define PLIB_CAN1_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* + * This section lists the other files that are included in this file. + */ +#include +#include + +#include "device.h" +#include "plib_can_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* CAN1 Message RAM Configuration Size */ +#define CAN1_RX_FIFO0_ELEMENT_SIZE 16U +#define CAN1_RX_FIFO0_SIZE 128U +#define CAN1_RX_FIFO1_ELEMENT_SIZE 16U +#define CAN1_RX_FIFO1_SIZE 128U +#define CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE 16U +#define CAN1_TX_FIFO_BUFFER_SIZE 256U +#define CAN1_TX_EVENT_FIFO_SIZE 128U +#define CAN1_STD_MSG_ID_FILTER_SIZE 4U + +/* CAN1_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver + for allocating buffer from non-cached contiguous memory */ +#define CAN1_MESSAGE_RAM_CONFIG_SIZE 644U + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +void CAN1_Initialize(void); +bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); +uint8_t CAN1_TxFifoFreeLevelGet(void); +bool CAN1_TxBufferIsBusy(uint8_t bufferNumber); +bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); +bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +CAN_ERROR CAN1_ErrorGet(void); +void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); +bool CAN1_StandardFilterElementSet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement); +bool CAN1_StandardFilterElementGet(uint8_t filterNumber, can_sidfe_registers_t *stdMsgIDFilterElement); +void CAN1_SleepModeEnter(void); +void CAN1_SleepModeExit(void); +void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif +// DOM-IGNORE-END + +#endif // PLIB_CAN1_H + +/******************************************************************************* + End of File +*/ diff --git a/firmware/src/config/mcal/peripheral/can/plib_can_common.h b/firmware/src/config/mcal/peripheral/can/plib_can_common.h new file mode 100644 index 0000000..9278d0f --- /dev/null +++ b/firmware/src/config/mcal/peripheral/can/plib_can_common.h @@ -0,0 +1,545 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_can_common.h + + Summary + CAN peripheral library interface. + + Description + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_CAN_COMMON_H +#define PLIB_CAN_COMMON_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + + // ***************************************************************************** +/* CAN Transfer Errors + + Summary: + CAN Transfer Error macros. + + Description: + Helper macros to identify CAN errors. + + Remarks: + None. +*/ + +#define CAN_ERROR_NONE 0x0U +#define CAN_ERROR_LEC_STUFF 0x1U +#define CAN_ERROR_LEC_FORM 0x2U +#define CAN_ERROR_LEC_ACK 0x3U +#define CAN_ERROR_LEC_BIT1 0x4U +#define CAN_ERROR_LEC_BIT0 0x5U +#define CAN_ERROR_LEC_CRC 0x6U +#define CAN_ERROR_LEC_NC 0x7U +#define CAN_ERROR_PASSIVE 0x20U +#define CAN_ERROR_WARNING_STATUS 0x40U +#define CAN_ERROR_BUS_OFF 0x80U +#define CAN_ERROR_DLEC_STUFF 0x100U +#define CAN_ERROR_DLEC_FORM 0x200U +#define CAN_ERROR_DLEC_ACK 0x300U +#define CAN_ERROR_DLEC_BIT1 0x400U +#define CAN_ERROR_DLEC_BIT0 0x500U +#define CAN_ERROR_DLEC_CRC 0x600U +#define CAN_ERROR_DLEC_NC 0x700U +#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U +#define CAN_ERROR_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* CAN Rx FIFO Number + + Summary: + CAN Rx FIFO Number. + + Description: + This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. + + Remarks: + None. +*/ +typedef enum +{ + CAN_RX_FIFO_0 = 0U, + CAN_RX_FIFO_1 +} CAN_RX_FIFO_NUM; + +// ***************************************************************************** +/* CAN Interrupt Mask + + Summary: + CAN Interrupt Mask. + + Description: + This data type defines the CAN Interrupt sources number. + + Remarks: + None. +*/ +typedef enum +{ + CAN_INTERRUPT_RF0N_MASK = (1UL << 0U), + CAN_INTERRUPT_RF0W_MASK = (1UL << 1U), + CAN_INTERRUPT_RF0F_MASK = (1UL << 2U), + CAN_INTERRUPT_RF0L_MASK = (1UL << 3U), + CAN_INTERRUPT_RF1N_MASK = (1UL << 4U), + CAN_INTERRUPT_RF1W_MASK = (1UL << 5U), + CAN_INTERRUPT_RF1F_MASK = (1UL << 6U), + CAN_INTERRUPT_RF1L_MASK = (1UL << 7U), + CAN_INTERRUPT_HPM_MASK = (1UL << 8U), + CAN_INTERRUPT_TC_MASK = (1UL << 9U), + CAN_INTERRUPT_TCF_MASK = (1UL << 10U), + CAN_INTERRUPT_TFE_MASK = (1UL << 11U), + CAN_INTERRUPT_TEFN_MASK = (1UL << 12U), + CAN_INTERRUPT_TEFW_MASK = (1UL << 13U), + CAN_INTERRUPT_TEFF_MASK = (1UL << 14U), + CAN_INTERRUPT_TEFL_MASK = (1UL << 15U), + CAN_INTERRUPT_TSW_MASK = (1UL << 16U), + CAN_INTERRUPT_MRAF_MASK = (1UL << 17U), + CAN_INTERRUPT_TOO_MASK = (1UL << 18U), + CAN_INTERRUPT_DRX_MASK = (1UL << 19U), + CAN_INTERRUPT_ELO_MASK = (1UL << 22U), + CAN_INTERRUPT_EP_MASK = (1UL << 23U), + CAN_INTERRUPT_EW_MASK = (1UL << 24U), + CAN_INTERRUPT_BO_MASK = (1UL << 25U), + CAN_INTERRUPT_WDI_MASK = (1UL << 26U), + CAN_INTERRUPT_PEA_MASK = (1UL << 27U), + CAN_INTERRUPT_PED_MASK = (1UL << 28U), + CAN_INTERRUPT_ARA_MASK = (1UL << 29U) +}CAN_INTERRUPT_MASK; + +// ***************************************************************************** +/* CAN Transfer Error + + Summary: + CAN Transfer Error data type. + + Description: + This data type defines the CAN Transfer Error. + + Remarks: + None. +*/ +typedef uint32_t CAN_ERROR; + +// ***************************************************************************** +/* CAN Tx FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN TX/RX Buffers Callback + + Summary: + CAN Callback Function Pointer for TX/RX Buffers. + + Description: + This data type defines the CAN Callback Function Pointer for TX/RX Buffers. + + Remarks: + None. +*/ +typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx Event FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx Event FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback + + Summary: + CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Description: + This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Remarks: + None. +*/ +typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Callback + + Summary: + CAN Callback Function Pointer. + + Description: + This data type defines the CAN Callback Function Pointer. + + Remarks: + None. +*/ +typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Message RAM Configuration + + Summary: + CAN Message RAM Configuration structure. + + Description: + This data structure defines the CAN Message RAM Base address for Rx FIFO0, + Rx FIFO1, Rx Buffers, Tx Buffers/FIFO, Tx Event FIFO, Standard Message ID Filter and + Extended Message ID Filter configuration. + + Remarks: + None. +*/ +typedef struct +{ + /* Rx FIFO0 base address */ + can_rxf0e_registers_t *rxFIFO0Address; + + /* Rx FIFO1 base address */ + can_rxf1e_registers_t *rxFIFO1Address; + + /* Rx Buffer base address */ + can_rxbe_registers_t *rxBuffersAddress; + + /* Tx Buffers/FIFO base address */ + can_txbe_registers_t *txBuffersAddress; + + /* Tx Event FIFO base address */ + can_txefe_registers_t *txEventFIFOAddress; + + /* Standard Message ID Filter base address */ + can_sidfe_registers_t *stdMsgIDFilterAddress; + + /* Extended Message ID Filter base address */ + can_xidfe_registers_t *extMsgIDFilterAddress; +} CAN_MSG_RAM_CONFIG; + +// ***************************************************************************** +/* CAN Rx Buffer and FIFO Element + + Summary: + CAN Rx Buffer and FIFO Element Structure. + + Description: + This data structure defines CAN Rx Buffer and FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Rx Timestamp */ + unsigned int rxts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :2; + /* Filter Index */ + unsigned int fidx:7; + /* Accepted Non-matching Frame */ + unsigned int anmf:1; + + /* Data field */ + uint8_t data[8]; + +} CAN_RX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Buffer Element + + Summary: + CAN Tx Buffer Element Structure. + + Description: + This data structure defines CAN Tx Buffer Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Reserved */ + unsigned int :16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :1; + /* Event FIFO Control */ + unsigned int efc:1; + /* Message Marker */ + unsigned int mm:8; + + /* Data field */ + uint8_t data[8]; + +} CAN_TX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Event FIFO Element + + Summary: + CAN Tx Event FIFO Element Structure. + + Description: + This data structure defines CAN Tx Event FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Tx Timestamp */ + unsigned int txts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switch */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Event Type */ + unsigned int et:2; + /* Message Marker */ + unsigned int mm:8; + +} CAN_TX_EVENT_FIFO; + +// ***************************************************************************** +/* CAN Tx FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx/Rx Buffers Callback Object + + Summary: + CAN transfer event callback structure for Tx/Rx Buffers. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TXRX_BUFFERS_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TXRX_BUFFERS_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx Event FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_EVENT_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback Object + + Summary: + CAN transfer event callback structure for Rx FIFO0/FIFO1. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_RX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_RX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Callback Object + + Summary: + CAN interrupt status callback structure. + + Description: + This data structure stores interrupt status callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* CAN Interrupt Status Callback */ + CAN_CALLBACK callback; + + /* CAN Interrupt Status Callback Context */ + uintptr_t context; +} CAN_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN PLib Instance Object + + Summary: + CAN PLib Object structure. + + Description: + This data structure defines the CAN PLib Instance Object. + + Remarks: + None. +*/ +typedef struct +{ + /* Message RAM Configuration */ + CAN_MSG_RAM_CONFIG msgRAMConfig; + +} CAN_OBJ; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif //PLIB_CAN_COMMON_H +/******************************************************************************* + End of File +*/ diff --git a/firmware/src/config/mcal/peripheral/clock/plib_clock.c b/firmware/src/config/mcal/peripheral/clock/plib_clock.c new file mode 100644 index 0000000..cb069e2 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/clock/plib_clock.c @@ -0,0 +1,292 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.c + + Summary: + CLOCK PLIB Implementation File. + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_clock.h" +#include "device.h" + +static void OSCCTRL_Initialize(void) +{ + + /****************** XOSC1 Initialization ********************************/ + + /* Configure External Oscillator */ + OSCCTRL_REGS->OSCCTRL_XOSCCTRL[1] = OSCCTRL_XOSCCTRL_STARTUP(0U) | OSCCTRL_XOSCCTRL_IMULT(3U) | OSCCTRL_XOSCCTRL_IPTAT(2U) | OSCCTRL_XOSCCTRL_XTALEN_Msk | OSCCTRL_XOSCCTRL_ENABLE_Msk; + while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_XOSCRDY1_Msk) != OSCCTRL_STATUS_XOSCRDY1_Msk) + { + /* Waiting for the XOSC Ready state */ + } +} + +static void OSC32KCTRL_Initialize(void) +{ + + OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0U); +} + +static void FDPLL0_Initialize(void) +{ + + /****************** DPLL0 Initialization *********************************/ + + /* Configure DPLL */ + OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0U) | OSCCTRL_DPLLCTRLB_LTIME(0x0U)| OSCCTRL_DPLLCTRLB_REFCLK(3U) | OSCCTRL_DPLLCTRLB_DIV(1U); + + + OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0U) | OSCCTRL_DPLLRATIO_LDR(59U); + + while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) + { + /* Waiting for the synchronization */ + } + + /* Enable DPLL */ + OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk ; + + while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk ) + { + /* Waiting for the DPLL enable synchronization */ + } + + while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) != + (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) + { + /* Waiting for the Ready state */ + } +} + +static void FDPLL1_Initialize(void) +{ + + /****************** DPLL1 Initialization *********************************/ + + /* Configure DPLL */ + OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0U) | OSCCTRL_DPLLCTRLB_LTIME(0x0U)| OSCCTRL_DPLLCTRLB_REFCLK(3U) | OSCCTRL_DPLLCTRLB_DIV(1U); + + + OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0U) | OSCCTRL_DPLLRATIO_LDR(47U); + + while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) + { + /* Waiting for the synchronization */ + } + + /* Enable DPLL */ + OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk ; + + while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk ) + { + /* Waiting for the DPLL enable synchronization */ + } + + while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) != + (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) + { + /* Waiting for the Ready state */ + } +} + +static void DFLL_Initialize(void) +{ + OSCCTRL_REGS->OSCCTRL_DFLLCTRLA = OSCCTRL_DFLLCTRLA_ENABLE_Msk | OSCCTRL_DFLLCTRLA_ONDEMAND_Msk | OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk ; +} + + +static void GCLK0_Initialize(void) +{ + + /* selection of the CPU clock Division */ + MCLK_REGS->MCLK_CPUDIV = MCLK_CPUDIV_DIV(0x01U); + + while((MCLK_REGS->MCLK_INTFLAG & MCLK_INTFLAG_CKRDY_Msk) != MCLK_INTFLAG_CKRDY_Msk) + { + /* Wait for the Main Clock to be Ready */ + } + GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1U) | GCLK_GENCTRL_SRC(7U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK0) == GCLK_SYNCBUSY_GENCTRL_GCLK0) + { + /* wait for the Generator 0 synchronization */ + } +} + +static void GCLK1_Initialize(void) +{ + GCLK_REGS->GCLK_GENCTRL[1] = GCLK_GENCTRL_DIV(6U) | GCLK_GENCTRL_SRC(6U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK1) == GCLK_SYNCBUSY_GENCTRL_GCLK1) + { + /* wait for the Generator 1 synchronization */ + } +} + +static void GCLK2_Initialize(void) +{ + GCLK_REGS->GCLK_GENCTRL[2] = GCLK_GENCTRL_DIV(48U) | GCLK_GENCTRL_SRC(6U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK2) == GCLK_SYNCBUSY_GENCTRL_GCLK2) + { + /* wait for the Generator 2 synchronization */ + } +} + +static void GCLK3_Initialize(void) +{ + GCLK_REGS->GCLK_GENCTRL[3] = GCLK_GENCTRL_DIV(4U) | GCLK_GENCTRL_SRC(1U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK3) == GCLK_SYNCBUSY_GENCTRL_GCLK3) + { + /* wait for the Generator 3 synchronization */ + } +} + +static void GCLK4_Initialize(void) +{ + GCLK_REGS->GCLK_GENCTRL[4] = GCLK_GENCTRL_DIV(12U) | GCLK_GENCTRL_SRC(8U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK4) == GCLK_SYNCBUSY_GENCTRL_GCLK4) + { + /* wait for the Generator 4 synchronization */ + } +} + +static void GCLK5_Initialize(void) +{ + GCLK_REGS->GCLK_GENCTRL[5] = GCLK_GENCTRL_DIV(3U) | GCLK_GENCTRL_SRC(6U) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK5) == GCLK_SYNCBUSY_GENCTRL_GCLK5) + { + /* wait for the Generator 5 synchronization */ + } +} + +void CLOCK_Initialize (void) +{ + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_2 */ + + /* Function to Initialize the Oscillators */ + OSCCTRL_Initialize(); + + /* Function to Initialize the 32KHz Oscillators */ + OSC32KCTRL_Initialize(); + + FDPLL0_Initialize(); + FDPLL1_Initialize(); + GCLK3_Initialize(); + DFLL_Initialize(); + GCLK0_Initialize(); + GCLK4_Initialize(); + GCLK1_Initialize(); + GCLK2_Initialize(); + GCLK5_Initialize(); + + /* MISRAC 2012 deviation block end */ + + /* Selection of the Generator and write Lock for SERCOM0_CORE */ + GCLK_REGS->GCLK_PCHCTRL[7] = GCLK_PCHCTRL_GEN(0x1U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[7] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM1_CORE */ + GCLK_REGS->GCLK_PCHCTRL[8] = GCLK_PCHCTRL_GEN(0x1U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[8] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for TC0 TC1 */ + GCLK_REGS->GCLK_PCHCTRL[9] = GCLK_PCHCTRL_GEN(0x2U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[9] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for TCC0 TCC1 */ + GCLK_REGS->GCLK_PCHCTRL[25] = GCLK_PCHCTRL_GEN(0x1U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[25] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for CAN1 */ + GCLK_REGS->GCLK_PCHCTRL[28] = GCLK_PCHCTRL_GEN(0x4U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[28] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for ADC0 */ + GCLK_REGS->GCLK_PCHCTRL[40] = GCLK_PCHCTRL_GEN(0x1U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[40] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for ADC1 */ + GCLK_REGS->GCLK_PCHCTRL[41] = GCLK_PCHCTRL_GEN(0x1U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[41] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for DAC */ + GCLK_REGS->GCLK_PCHCTRL[42] = GCLK_PCHCTRL_GEN(0x3U) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[42] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + + /* Configure the AHB Bridge Clocks */ + MCLK_REGS->MCLK_AHBMASK = 0xffffffU; + + /* Configure the APBA Bridge Clocks */ + MCLK_REGS->MCLK_APBAMASK = 0x77ffU; + + /* Configure the APBB Bridge Clocks */ + MCLK_REGS->MCLK_APBBMASK = 0x18856U; + + /* Configure the APBD Bridge Clocks */ + MCLK_REGS->MCLK_APBDMASK = 0x380U; + + +} diff --git a/firmware/src/config/mcal/peripheral/clock/plib_clock.h b/firmware/src/config/mcal/peripheral/clock/plib_clock.h new file mode 100644 index 0000000..a81d838 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/clock/plib_clock.h @@ -0,0 +1,140 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.h + + Summary: + CLOCK PLIB Header File. + + Description: + The Clock PLIB initializes all the oscillators based on the + requirements. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_CLOCK_H +#define PLIB_CLOCK_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void CLOCK_Initialize (void); + + Summary: + Initializes all the modules related to the system clock. + + Description: + This function initializes the clock as defined by the MHC and Clock Manager + selections. The function will configure the NVM Flash Wait states based on + the configured CPU operational frequency. It will then configure the + oscillators. + + For each of the clock sources (External Oscillator, Digital Phase Locked + Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal + 32KHz oscillator) enabled in MHC, the function will configure the clock + settings and will then wait till the clock is ready. In case of DPLL, the + function will wait till a lock is obtained. + + The function will then configure the Generic clock generators based on MHC + configurations. If a Generic Clock is enabled in MHC, this will be enabled + in the CLOCK_Initialize() function. The function will apply the CPU clock + divider and will wait for the Main Clock module to get ready. If the Main + Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these + will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock + Channels were enabled in MHC, these will be enabled in the + CLOCK_Initialize() function. + + The peripheral AHB and APB main clock and peripheral channel clocks will be + enabled when the peripheral specific initialize functions are called. This + will override the setting in MHC. The Generic Clock Generator source for + desired peripheral channel must be configured in MHC. + + Precondition: + MHC GUI should be configured with the right values. Incorrect configuration + of the Clock will result in incorrect peripheral behavior or a non + functional device. + + Parameters: + None. + + Returns: + None. + + Example: + + CLOCK_Initialize(); + + + Remarks: + This function should be called before calling other Clock library functions. +*/ + +void CLOCK_Initialize (void); + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_CLOCK_H */ diff --git a/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.c b/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.c new file mode 100644 index 0000000..a78b433 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.c @@ -0,0 +1,108 @@ +/******************************************************************************* + CMCC(Cortex M Cache Controller) Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_cmcc.c + + Summary: + CMCC Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "peripheral/cmcc/plib_cmcc.h" +#include "interrupts.h" + +void CMCC_Disable (void ) +{ + CMCC_REGS->CMCC_CTRL &=(~CMCC_CTRL_CEN_Msk); + + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } +} + +void CMCC_EnableICache (void ) +{ + CMCC_REGS->CMCC_CTRL &= (~CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_CFG &= (~CMCC_CFG_ICDIS_Msk); + CMCC_REGS->CMCC_CTRL = (CMCC_CTRL_CEN_Msk); +} + +void CMCC_DisableICache (void ) +{ + CMCC_REGS->CMCC_CTRL &= (~CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_CFG |= (CMCC_CFG_ICDIS_Msk); + CMCC_REGS->CMCC_CTRL = (CMCC_CTRL_CEN_Msk); +} + +void CMCC_EnableDCache (void ) +{ + CMCC_REGS->CMCC_CTRL &= (~CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_CFG &= (~CMCC_CFG_DCDIS_Msk); + CMCC_REGS->CMCC_CTRL = (CMCC_CTRL_CEN_Msk); +} + +void CMCC_DisableDCache (void ) +{ + CMCC_REGS->CMCC_CTRL &= (~CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_CFG |= (CMCC_CFG_DCDIS_Msk); + CMCC_REGS->CMCC_CTRL = (CMCC_CTRL_CEN_Msk); +} + +void CMCC_InvalidateAll (void ) +{ + CMCC_REGS->CMCC_CTRL &= (~CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_MAINT0 = CMCC_MAINT0_INVALL_Msk; +} + diff --git a/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.h b/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.h new file mode 100644 index 0000000..1bf74ce --- /dev/null +++ b/firmware/src/config/mcal/peripheral/cmcc/plib_cmcc.h @@ -0,0 +1,74 @@ +/******************************************************************************* + Interface definition of CMCC PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_cmcc.h + + Summary: + Interface definition of the CMCC(Cortex M Cache Controller) Peripheral Library + + Description: + This file defines the interface for the CMCC Plib. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_CMCC_H // Guards against multiple inclusion +#define PLIB_CMCC_H + + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + +#define CMCC_NO_OF_WAYS (4U) +#define CMCC_LINE_PER_WAY (64U) +#define CMCC_LINE_SIZE (16U) +#define CMCC_WAY_SIZE (1024U) + +/***************************** CMCC API *******************************/ +void CMCC_Disable (void ); +void CMCC_EnableDCache (void ); +void CMCC_DisableDCache (void ); + +void CMCC_EnableICache (void ); +void CMCC_DisableICache (void ); + +void CMCC_InvalidateAll (void ); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/dac/plib_dac.c b/firmware/src/config/mcal/peripheral/dac/plib_dac.c new file mode 100644 index 0000000..7000f3b --- /dev/null +++ b/firmware/src/config/mcal/peripheral/dac/plib_dac.c @@ -0,0 +1,110 @@ +/******************************************************************************* + Digital-to-Analog Converter (DAC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_dac.c + + Summary: + DAC PLIB Implementation file + + Description: + This file defines the interface to the DAC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "plib_dac.h" +#include "device.h" +#include "smartee.h" + + +/* (DAC DATA) Mask DATA[15:12] Bit */ +#define DAC_DATA_MSB_MASK (0x0FFFU) + +/* (DAC DATA) Mask DATA[3:0] Bit */ +#define DAC_DATA_LSB_MASK (0xFFF0U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: DAC Implementation +// ***************************************************************************** +// ***************************************************************************** +uint8 UDS_DAC_Ref_Voltage; +void DAC_Initialize (void) +{ + /* Reset DAC Peripheral */ + // DAC_REGS->DAC_CTRLA = DAC_CTRLA_SWRST_Msk; + // while (((DAC_REGS->DAC_CTRLA & DAC_CTRLA_SWRST_Msk) == DAC_CTRLA_SWRST_Msk) && ((DAC_REGS->DAC_SYNCBUSY & DAC_SYNCBUSY_SWRST_Msk) == DAC_SYNCBUSY_SWRST_Msk)) + //{ + /* Wait for synchronization */ + // } + uint8_t eedata[5]; + SmartEE_Read(0x781, eedata, 1); + if(eedata[0]< 8) + { + UDS_DAC_Ref_Voltage = eedata[0]; + }else + { + UDS_DAC_Ref_Voltage = 3; + } + + DAC_REGS->DAC_CTRLB = DAC_CTRLB_REFSEL (3U); + SUPC_REGS->SUPC_VREF = SUPC_VREF_SEL(UDS_DAC_Ref_Voltage); + + DAC_REGS->DAC_DACCTRL[0] = DAC_DACCTRL_ENABLE_Msk | DAC_DACCTRL_CCTRL (0x2U) | DAC_DACCTRL_OSR (0U) | DAC_DACCTRL_REFRESH (1U) ; + + + /* Enable DAC */ + DAC_REGS->DAC_CTRLA |= DAC_CTRLA_ENABLE_Msk; + while ((DAC_REGS->DAC_SYNCBUSY & DAC_SYNCBUSY_ENABLE_Msk) == DAC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for synchronization */ + } +} + +void DAC_DataWrite (DAC_CHANNEL_NUM channel, uint16_t data) +{ + /* Write Data to DATA0 Register for conversion(DATA[11:0]) */ + DAC_REGS->DAC_DATA[0] = DAC_DATA_MSB_MASK & DAC_DATA_DATA(data); + while ((DAC_REGS->DAC_SYNCBUSY & DAC_SYNCBUSY_DATA0_Msk) == DAC_SYNCBUSY_DATA0_Msk) + { + /* Wait for synchronization */ +} +} + + + + + +bool DAC_IsReady (DAC_CHANNEL_NUM channel) +{ + return (((DAC_REGS->DAC_STATUS >> channel) & DAC_STATUS_READY0_Msk) == DAC_STATUS_READY0_Msk); +} diff --git a/firmware/src/config/mcal/peripheral/dac/plib_dac.h b/firmware/src/config/mcal/peripheral/dac/plib_dac.h new file mode 100644 index 0000000..185c589 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/dac/plib_dac.h @@ -0,0 +1,78 @@ +/******************************************************************************* + Digital-to-Analog Converter (DAC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_dac.h + + Summary: + DAC PLIB Header file + + Description: + This file defines the interface to the DAC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_DAC_H +#define PLIB_DAC_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +#define DAC_CHANNEL_0 (0U) +#define DAC_CHANNEL_1 (1U) + +typedef uint8_t DAC_CHANNEL_NUM; + +void DAC_Initialize (void); +void DAC_DataWrite (DAC_CHANNEL_NUM channel, uint16_t data); + + +bool DAC_IsReady (DAC_CHANNEL_NUM channel); + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_DAC_H */ diff --git a/firmware/src/config/mcal/peripheral/evsys/plib_evsys.c b/firmware/src/config/mcal/peripheral/evsys/plib_evsys.c new file mode 100644 index 0000000..d8611ac --- /dev/null +++ b/firmware/src/config/mcal/peripheral/evsys/plib_evsys.c @@ -0,0 +1,52 @@ +/******************************************************************************* + EVSYS Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.c + + Summary: + EVSYS Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_evsys.h" +#include "interrupts.h" + + + +void EVSYS_Initialize( void ) +{ + /*Event Channel User Configuration*/ + +} + + diff --git a/firmware/src/config/mcal/peripheral/evsys/plib_evsys.h b/firmware/src/config/mcal/peripheral/evsys/plib_evsys.h new file mode 100644 index 0000000..1220d7e --- /dev/null +++ b/firmware/src/config/mcal/peripheral/evsys/plib_evsys.h @@ -0,0 +1,68 @@ +/******************************************************************************* + Interface definition of EVSYS PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.h + + Summary: + Interface definition of the Event System Plib (EVSYS). + + Description: + This file defines the interface for the EVSYS Plib. + It allows user to setup event generators and users. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef EVSYS_H // Guards against multiple inclusion +#define EVSYS_H + +#include "device.h" +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + + + +/***************************** EVSYS API *******************************/ +void EVSYS_Initialize( void ); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif diff --git a/firmware/src/config/mcal/peripheral/nvic/plib_nvic.c b/firmware/src/config/mcal/peripheral/nvic/plib_nvic.c new file mode 100644 index 0000000..fb9b81d --- /dev/null +++ b/firmware/src/config/mcal/peripheral/nvic/plib_nvic.c @@ -0,0 +1,133 @@ +/******************************************************************************* + NVIC PLIB Implementation + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.c + + Summary: + NVIC PLIB Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "plib_nvic.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVIC Implementation +// ***************************************************************************** +// ***************************************************************************** + +void NVIC_Initialize( void ) +{ + /* Priority 0 to 7 and no sub-priority. 0 is the highest priority */ + NVIC_SetPriorityGrouping( 0x00 ); + + /* Enable NVIC Controller */ + __DMB(); + __enable_irq(); + + /* Enable the interrupt sources and configure the priorities as configured + * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(WDT_IRQn, 7); + NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(RTC_IRQn, 7); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(SERCOM0_0_IRQn, 7); + NVIC_EnableIRQ(SERCOM0_0_IRQn); + NVIC_SetPriority(SERCOM0_1_IRQn, 7); + NVIC_EnableIRQ(SERCOM0_1_IRQn); + NVIC_SetPriority(SERCOM0_2_IRQn, 7); + NVIC_EnableIRQ(SERCOM0_2_IRQn); + NVIC_SetPriority(SERCOM0_OTHER_IRQn, 7); + NVIC_EnableIRQ(SERCOM0_OTHER_IRQn); + NVIC_SetPriority(SERCOM1_0_IRQn, 7); + NVIC_EnableIRQ(SERCOM1_0_IRQn); + NVIC_SetPriority(SERCOM1_1_IRQn, 7); + NVIC_EnableIRQ(SERCOM1_1_IRQn); + NVIC_SetPriority(SERCOM1_2_IRQn, 7); + NVIC_EnableIRQ(SERCOM1_2_IRQn); + NVIC_SetPriority(SERCOM1_OTHER_IRQn, 7); + NVIC_EnableIRQ(SERCOM1_OTHER_IRQn); + NVIC_SetPriority(CAN1_IRQn, 7); + NVIC_EnableIRQ(CAN1_IRQn); + NVIC_SetPriority(TCC0_OTHER_IRQn, 7); + NVIC_EnableIRQ(TCC0_OTHER_IRQn); + NVIC_SetPriority(TCC0_MC0_IRQn, 7); + NVIC_EnableIRQ(TCC0_MC0_IRQn); + NVIC_SetPriority(TC0_IRQn, 7); + NVIC_EnableIRQ(TC0_IRQn); + NVIC_SetPriority(ADC0_RESRDY_IRQn, 7); + NVIC_EnableIRQ(ADC0_RESRDY_IRQn); + NVIC_SetPriority(ADC1_RESRDY_IRQn, 7); + NVIC_EnableIRQ(ADC1_RESRDY_IRQn); + + /* Enable Usage fault */ + SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk); + /* Trap divide by zero */ + SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; + + /* Enable Bus fault */ + SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk); + +} + +void NVIC_INT_Enable( void ) +{ + __DMB(); + __enable_irq(); +} + +bool NVIC_INT_Disable( void ) +{ + bool processorStatus = (__get_PRIMASK() == 0U); + + __disable_irq(); + __DMB(); + + return processorStatus; +} + +void NVIC_INT_Restore( bool state ) +{ + if( state == true ) + { + __DMB(); + __enable_irq(); + } + else + { + __disable_irq(); + __DMB(); + } +} diff --git a/firmware/src/config/mcal/peripheral/nvic/plib_nvic.h b/firmware/src/config/mcal/peripheral/nvic/plib_nvic.h new file mode 100644 index 0000000..f50f90b --- /dev/null +++ b/firmware/src/config/mcal/peripheral/nvic/plib_nvic.h @@ -0,0 +1,71 @@ +/******************************************************************************* + NVIC PLIB Header + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.h + + Summary: + NVIC PLIB Header File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_NVIC_H +#define PLIB_NVIC_H + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +/***************************** NVIC Inline *******************************/ + +void NVIC_Initialize( void ); +void NVIC_INT_Enable( void ); +bool NVIC_INT_Disable( void ); +void NVIC_INT_Restore( bool state ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END +#endif // PLIB_NVIC_H diff --git a/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c b/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c new file mode 100644 index 0000000..55d0c55 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.c @@ -0,0 +1,382 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.c + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include "plib_nvmctrl.h" +#include "interrupts.h" + +static volatile uint16_t nvm_error; + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVMCTRL Implementation +// ***************************************************************************** +// ***************************************************************************** + + + +void NVMCTRL_Initialize(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)NVMCTRL_CTRLA_RWS(5U) | NVMCTRL_CTRLA_AUTOWS_Msk; +} + +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t* paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +void NVMCTRL_SetWriteMode(NVMCTRL_WRITEMODE mode) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)((NVMCTRL_REGS->NVMCTRL_CTRLA & (~NVMCTRL_CTRLA_WMODE_Msk)) | (uint16_t)mode); +} + +bool NVMCTRL_QuadWordWrite(const uint32_t *data, const uint32_t address) +{ + uint8_t i = 0U; + bool wr_status = false; + uint32_t * paddress = (uint32_t *)address; + uint16_t wr_mode = (NVMCTRL_REGS->NVMCTRL_CTRLA & NVMCTRL_CTRLA_WMODE_Msk); + + /* Clear global error flag */ + nvm_error = 0U; + + /* If the address is not a quad word address, return error */ + if((address & 0x0fU) != 0U) + { + wr_status = false; + } + else + { + /* Configure Quad Word Write */ + NVMCTRL_SetWriteMode(NVMCTRL_WMODE_AQW); + + /* Writing 32-bit data into the given address. Writes to the page buffer must be 32 bits. */ + for (i = 0U; i <= 3U; i++) + { + *paddress = data[i]; + paddress++; + } + /* Restore the write mode */ + NVMCTRL_SetWriteMode(wr_mode); + wr_status = true; + } + return wr_status; +} + +bool NVMCTRL_DoubleWordWrite(const uint32_t *data, const uint32_t address) +{ + uint8_t i = 0U; + bool wr_status = false; + uint32_t * paddress = (uint32_t *)address; + uint16_t wr_mode = (NVMCTRL_REGS->NVMCTRL_CTRLA & NVMCTRL_CTRLA_WMODE_Msk); + + /* Clear global error flag */ + nvm_error = 0U; + + /* If the address is not a double word address, return error */ + if((address & 0x07U) != 0U) + { + wr_status = false; + } + else + { + /* Configure Double Word Write */ + NVMCTRL_SetWriteMode(NVMCTRL_WMODE_ADW); + + /* Writing 32-bit data into the given address. Writes to the page buffer must be 32 bits. */ + for (i = 0U; i <= 1U; i++) + { + *paddress = data[i]; + paddress++; + } + /* Restore the write mode */ + NVMCTRL_SetWriteMode(wr_mode); + wr_status = true; + } + return wr_status; +} + +/* This function only loads the internal NVM page buffer. This function must be used when multiple updates + * to the same page are expected. Once all the updates are done, call the NVMCTRL_PageBufferCommit API + * to write the contents of the page buffer to the NVM memory. This functionality only works in manual write mode. + */ +bool NVMCTRL_PageBufferWrite( const uint32_t *data, const uint32_t address) +{ + uint32_t i = 0U; + uint32_t * paddress = (uint32_t *)address; + + /* Clear global error flag */ + nvm_error = 0U; + + /* writing 32-bit data into the given address. Writes to the page buffer must be 32 bits */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = data[i]; + paddress++; + } + + return true; +} + +/* This API must be used to write the contents of the page buffer to the NVM memory when the manual write mode is enabled */ +bool NVMCTRL_PageBufferCommit( const uint32_t address ) +{ + /* Clear global error flag */ + nvm_error = 0U; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address; + + /* If write mode is manual, */ + if ((NVMCTRL_REGS->NVMCTRL_CTRLA & NVMCTRL_CTRLA_WMODE_Msk) == NVMCTRL_CTRLA_WMODE_MAN) + { + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY; + } + + return true; +} + +/* This function assumes that the page written is fresh or it is erased by + * calling NVMCTRL_BlockErase + */ +bool NVMCTRL_PageWrite( const uint32_t *data, const uint32_t address ) +{ + uint32_t i = 0U; + uint32_t * paddress = (uint32_t *)address; + + /* Clear global error flag */ + nvm_error = 0U; + + /* writing 32-bit data into the given address. Writes to the page buffer must be 32 bits */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = data[i]; + paddress++; + } + + /* If write mode is manual, */ + if ((NVMCTRL_REGS->NVMCTRL_CTRLA & NVMCTRL_CTRLA_WMODE_Msk) == NVMCTRL_CTRLA_WMODE_MAN) + { + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY; + } + + return true; +} + +bool NVMCTRL_BlockErase( uint32_t address ) +{ + /* Clear global error flag */ + nvm_error = 0U; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address; + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY; + + return true; +} + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i = 0U; + uint32_t wr_count = 0U; + uint32_t * paddress = (uint32_t *)address; + uint32_t * pdata = data; + bool rowwrite = false; + + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= ((NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE) - NVMCTRL_USERROW_PAGESIZE))) + { + /* Clear global error flag */ + nvm_error = 0U; + + for (wr_count = 0U; wr_count < (NVMCTRL_USERROW_PAGESIZE / NVMCTRL_USERROW_WQW_SIZE); wr_count++) + { + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_USERROW_WQW_SIZE / 4U); i++) + { + *paddress = *pdata; + paddress++; + pdata++; + } + + /* Set address */ + NVMCTRL_REGS->NVMCTRL_ADDR = (address + (wr_count * NVMCTRL_USERROW_WQW_SIZE)); + + /* Set command */ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_WQW | NVMCTRL_CTRLB_CMDEX_KEY; + + while (NVMCTRL_IsBusy() == true) + { + // Wait for write complete + } + } + + rowwrite = true; + } + + return rowwrite; +} + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ) +{ + bool rowerase = false; + + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= (NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE))) + { + /* Clear global error flag */ + nvm_error = 0U; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address; + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_EP | NVMCTRL_CTRLB_CMDEX_KEY; + + rowerase = true; + } + + return rowerase; +} + +uint16_t NVMCTRL_ErrorGet( void ) +{ + uint16_t temp; + /* Store previous and current error flags */ + temp = NVMCTRL_REGS->NVMCTRL_INTFLAG; + + nvm_error |= temp; + + /* Clear NVMCTRL INTFLAG register */ + NVMCTRL_REGS->NVMCTRL_INTFLAG = nvm_error; + + return nvm_error; +} + +uint16_t NVMCTRL_StatusGet( void ) +{ + uint16_t nvm_status; + + nvm_status = NVMCTRL_REGS->NVMCTRL_STATUS; + + return nvm_status; +} + +bool NVMCTRL_IsBusy(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_STATUS & NVMCTRL_STATUS_READY_Msk) == 0U); +} + +void NVMCTRL_RegionLock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address; + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_LR | NVMCTRL_CTRLB_CMDEX_KEY; +} + +void NVMCTRL_RegionUnlock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address; + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_UR | NVMCTRL_CTRLB_CMDEX_KEY; +} + +uint32_t NVMCTRL_RegionLockStatusGet (void) +{ + return (NVMCTRL_REGS->NVMCTRL_RUNLOCK); +} + +void NVMCTRL_SecurityBitSet(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_SSB | NVMCTRL_CTRLB_CMDEX_KEY; +} + +bool NVMCTRL_SmartEEPROM_IsBusy(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_SEESTAT & NVMCTRL_SEESTAT_BUSY_Msk) != 0U); +} + +uint32_t NVMCTRL_SmartEEPROMStatusGet( void ) +{ + uint32_t smart_eep_status; + + smart_eep_status = NVMCTRL_REGS->NVMCTRL_SEESTAT; + + return smart_eep_status; +} + +bool NVMCTRL_SmartEEPROM_IsActiveSectorFull(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_SEESFULL_Msk) != 0U); +} + +/* Use BankSwap only when there are valid applications in both NVM Banks */ +void NVMCTRL_BankSwap(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_BKSWRST | NVMCTRL_CTRLB_CMDEX_KEY; +} + +void NVMCTRL_SmartEEPROMSectorReallocate(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_SEERALOC | NVMCTRL_CTRLB_CMDEX_KEY; +} + +void NVMCTRL_SmartEEPROMFlushPageBuffer(void) +{ + /* Clear global error flag */ + nvm_error = 0U; + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_CMD_SEEFLUSH | NVMCTRL_CTRLB_CMDEX_KEY; +} + + + diff --git a/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.h b/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.h new file mode 100644 index 0000000..c43103f --- /dev/null +++ b/firmware/src/config/mcal/peripheral/nvmctrl/plib_nvmctrl.h @@ -0,0 +1,140 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.h + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_NVMCTRL_H +#define PLIB_NVMCTRL_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + +// DOM-IGNORE-END + +#define NVMCTRL_FLASH_START_ADDRESS (0U) +#define NVMCTRL_FLASH_PAGESIZE (512U) +#define NVMCTRL_FLASH_BLOCKSIZE (8192U) + +/* NVM supports four write modes */ + +#define NVMCTRL_WMODE_MAN NVMCTRL_CTRLA_WMODE_MAN +#define NVMCTRL_WMODE_ADW NVMCTRL_CTRLA_WMODE_ADW +#define NVMCTRL_WMODE_AQW NVMCTRL_CTRLA_WMODE_AQW +#define NVMCTRL_WMODE_AP NVMCTRL_CTRLA_WMODE_AP + +typedef uint16_t NVMCTRL_WRITEMODE; + +#define NVMCTRL_USERROW_START_ADDRESS (0x00804000U) +#define NVMCTRL_USERROW_SIZE (0x200U) +#define NVMCTRL_USERROW_PAGESIZE (512U) +#define NVMCTRL_USERROW_WQW_SIZE (16U) + + + + +void NVMCTRL_Initialize(void); + +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +void NVMCTRL_SetWriteMode(NVMCTRL_WRITEMODE mode); + +bool NVMCTRL_QuadWordWrite(const uint32_t *data, const uint32_t address); + +bool NVMCTRL_DoubleWordWrite(const uint32_t *data, const uint32_t address); + +bool NVMCTRL_PageWrite( const uint32_t* data, const uint32_t address ); + +bool NVMCTRL_PageBufferWrite( const uint32_t *data, const uint32_t address); + +bool NVMCTRL_PageBufferCommit( const uint32_t address ); + +bool NVMCTRL_BlockErase( uint32_t address ); + +uint16_t NVMCTRL_ErrorGet( void ); + +uint16_t NVMCTRL_StatusGet( void ); + +bool NVMCTRL_IsBusy( void ); + +void NVMCTRL_RegionLock (uint32_t address); + +void NVMCTRL_RegionUnlock (uint32_t address); + +uint32_t NVMCTRL_RegionLockStatusGet (void); + +void NVMCTRL_SecurityBitSet(void); + +bool NVMCTRL_SmartEEPROM_IsBusy(void); + +uint32_t NVMCTRL_SmartEEPROMStatusGet( void ); + +bool NVMCTRL_SmartEEPROM_IsActiveSectorFull(void); + +void NVMCTRL_SmartEEPROMSectorReallocate(void); + +void NVMCTRL_SmartEEPROMFlushPageBuffer(void); + +void NVMCTRL_BankSwap(void); + + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END +#endif // PLIB_NVMCTRL_H diff --git a/firmware/src/config/mcal/peripheral/port/plib_port.c b/firmware/src/config/mcal/peripheral/port/plib_port.c new file mode 100644 index 0000000..1c22f7d --- /dev/null +++ b/firmware/src/config/mcal/peripheral/port/plib_port.c @@ -0,0 +1,385 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.c + + Summary: + Interface definition of PORT PLIB + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_port.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_Initialize(void) +{ + /************************** GROUP 0 Initialization *************************/ + PORT_REGS->GROUP[0].PORT_DIR = 0x2002404U; + PORT_REGS->GROUP[0].PORT_OUT = 0x2000400U; + PORT_REGS->GROUP[0].PORT_PINCFG[0] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[1] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[2] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[4] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[8] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[9] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[10] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[11] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[12] = 0x3U; + PORT_REGS->GROUP[0].PORT_PINCFG[13] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[16] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[17] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[18] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[19] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[20] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[21] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[22] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[23] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[25] = 0x0U; + + PORT_REGS->GROUP[0].PORT_PMUX[0] = 0x33U; + PORT_REGS->GROUP[0].PORT_PMUX[1] = 0x1U; + PORT_REGS->GROUP[0].PORT_PMUX[2] = 0x1U; + PORT_REGS->GROUP[0].PORT_PMUX[4] = 0x22U; + PORT_REGS->GROUP[0].PORT_PMUX[5] = 0x20U; + PORT_REGS->GROUP[0].PORT_PMUX[6] = 0x0U; + PORT_REGS->GROUP[0].PORT_PMUX[8] = 0x11U; + PORT_REGS->GROUP[0].PORT_PMUX[9] = 0x11U; + PORT_REGS->GROUP[0].PORT_PMUX[10] = 0x11U; + PORT_REGS->GROUP[0].PORT_PMUX[11] = 0x11U; + PORT_REGS->GROUP[0].PORT_PMUX[12] = 0x0U; + + /************************** GROUP 1 Initialization *************************/ + PORT_REGS->GROUP[1].PORT_DIR = 0x4000c004U; + PORT_REGS->GROUP[1].PORT_PINCFG[0] = 0x3U; + PORT_REGS->GROUP[1].PORT_PINCFG[1] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[2] = 0x0U; + PORT_REGS->GROUP[1].PORT_PINCFG[3] = 0x3U; + PORT_REGS->GROUP[1].PORT_PINCFG[4] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[5] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[6] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[7] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[8] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[9] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[10] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[12] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[13] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[14] = 0x0U; + PORT_REGS->GROUP[1].PORT_PINCFG[15] = 0x0U; + PORT_REGS->GROUP[1].PORT_PINCFG[30] = 0x3U; + PORT_REGS->GROUP[1].PORT_PINCFG[31] = 0x3U; + + PORT_REGS->GROUP[1].PORT_PMUX[0] = 0x11U; + PORT_REGS->GROUP[1].PORT_PMUX[1] = 0x10U; + PORT_REGS->GROUP[1].PORT_PMUX[2] = 0x11U; + PORT_REGS->GROUP[1].PORT_PMUX[3] = 0x11U; + PORT_REGS->GROUP[1].PORT_PMUX[4] = 0x11U; + PORT_REGS->GROUP[1].PORT_PMUX[5] = 0x5U; + PORT_REGS->GROUP[1].PORT_PMUX[6] = 0x77U; + PORT_REGS->GROUP[1].PORT_PMUX[7] = 0x0U; + PORT_REGS->GROUP[1].PORT_PMUX[15] = 0x0U; + + +} +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_IN); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value) +{ + /* Write the desired value */ + ((port_group_registers_t*)group)->PORT_OUT = (((port_group_registers_t*)group)->PORT_OUT & (~mask)) | (mask & value); +} + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_OUT); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTCLR = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTTGL = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRCLR = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) +{ + uint32_t periph_func = (uint32_t) function; + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + uint32_t pinmux_val = (uint32_t)((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)]; + + /* For odd pins */ + if (0U != (pin_num & 0x01U)) + { + pinmux_val = (pinmux_val & ~0xF0U) | (periph_func << 4); + } + else + { + pinmux_val = (pinmux_val & ~0x0FU) | periph_func; + } + ((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)] = (uint8_t)pinmux_val; + + /* Enable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk; +} + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinGPIOConfig(PORT_PIN pin) +{ + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + + /* Disable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); +} \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/port/plib_port.h b/firmware/src/config/mcal/peripheral/port/plib_port.h new file mode 100644 index 0000000..fdcf77b --- /dev/null +++ b/firmware/src/config/mcal/peripheral/port/plib_port.h @@ -0,0 +1,1209 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.h + + Summary: + PORT PLIB Header File + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_PORT_H +#define PLIB_PORT_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data types and constants +// ***************************************************************************** +// ***************************************************************************** + +/*** Macros for SDA pin ***/ +#define SDA_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 0U)) & 0x01U) +#define SDA_PIN PORT_PIN_PA00 + +/*** Macros for SCL pin ***/ +#define SCL_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 1U)) & 0x01U) +#define SCL_PIN PORT_PIN_PA01 + +/*** Macros for INP pin ***/ +#define INP_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 2U)) & 0x01U) +#define INP_PIN PORT_PIN_PA02 + +/*** Macros for AD_LDO pin ***/ +#define AD_LDO_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 4U)) & 0x01U) +#define AD_LDO_PIN PORT_PIN_PB04 + +/*** Macros for LD_OUT pin ***/ +#define LD_OUT_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 5U)) & 0x01U) +#define LD_OUT_PIN PORT_PIN_PB05 + +/*** Macros for Y1_SNS pin ***/ +#define Y1_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 6U)) & 0x01U) +#define Y1_SNS_PIN PORT_PIN_PB06 + +/*** Macros for Y2_SNS pin ***/ +#define Y2_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 7U)) & 0x01U) +#define Y2_SNS_PIN PORT_PIN_PB07 + +/*** Macros for Y3_SNS pin ***/ +#define Y3_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 8U)) & 0x01U) +#define Y3_SNS_PIN PORT_PIN_PB08 + +/*** Macros for Y4_SNS pin ***/ +#define Y4_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 9U)) & 0x01U) +#define Y4_SNS_PIN PORT_PIN_PB09 + +/*** Macros for Y5_SNS pin ***/ +#define Y5_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 4U)) & 0x01U) +#define Y5_SNS_PIN PORT_PIN_PA04 + +/*** Macros for MOSI pin ***/ +#define MOSI_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 8U)) & 0x01U) +#define MOSI_PIN PORT_PIN_PA08 + +/*** Macros for CLK pin ***/ +#define CLK_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 9U)) & 0x01U) +#define CLK_PIN PORT_PIN_PA09 + +/*** Macros for Spi_Software_Trigger pin ***/ +#define Spi_Software_Trigger_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 10U)) +#define Spi_Software_Trigger_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 10U)) +#define Spi_Software_Trigger_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 10U)) +#define Spi_Software_Trigger_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 10U)) +#define Spi_Software_Trigger_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 10U)) +#define Spi_Software_Trigger_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 10U)) & 0x01U) +#define Spi_Software_Trigger_PIN PORT_PIN_PA10 + +/*** Macros for MISO pin ***/ +#define MISO_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 11U)) & 0x01U) +#define MISO_PIN PORT_PIN_PA11 + +/*** Macros for BL_PWM pin ***/ +#define BL_PWM_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 10U)) & 0x01U) +#define BL_PWM_PIN PORT_PIN_PB10 + +/*** Macros for CAN_TXD pin ***/ +#define CAN_TXD_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 12U)) & 0x01U) +#define CAN_TXD_PIN PORT_PIN_PB12 + +/*** Macros for CAN_RXD pin ***/ +#define CAN_RXD_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 13U)) & 0x01U) +#define CAN_RXD_PIN PORT_PIN_PB13 + +/*** Macros for Gain1 pin ***/ +#define Gain1_Set() (PORT_REGS->GROUP[1].PORT_OUTSET = ((uint32_t)1U << 14U)) +#define Gain1_Clear() (PORT_REGS->GROUP[1].PORT_OUTCLR = ((uint32_t)1U << 14U)) +#define Gain1_Toggle() (PORT_REGS->GROUP[1].PORT_OUTTGL = ((uint32_t)1U << 14U)) +#define Gain1_OutputEnable() (PORT_REGS->GROUP[1].PORT_DIRSET = ((uint32_t)1U << 14U)) +#define Gain1_InputEnable() (PORT_REGS->GROUP[1].PORT_DIRCLR = ((uint32_t)1U << 14U)) +#define Gain1_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 14U)) & 0x01U) +#define Gain1_PIN PORT_PIN_PB14 + +/*** Macros for Gain0 pin ***/ +#define Gain0_Set() (PORT_REGS->GROUP[1].PORT_OUTSET = ((uint32_t)1U << 15U)) +#define Gain0_Clear() (PORT_REGS->GROUP[1].PORT_OUTCLR = ((uint32_t)1U << 15U)) +#define Gain0_Toggle() (PORT_REGS->GROUP[1].PORT_OUTTGL = ((uint32_t)1U << 15U)) +#define Gain0_OutputEnable() (PORT_REGS->GROUP[1].PORT_DIRSET = ((uint32_t)1U << 15U)) +#define Gain0_InputEnable() (PORT_REGS->GROUP[1].PORT_DIRCLR = ((uint32_t)1U << 15U)) +#define Gain0_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 15U)) & 0x01U) +#define Gain0_PIN PORT_PIN_PB15 + +/*** Macros for FAULT_OUT pin ***/ +#define FAULT_OUT_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 12U)) & 0x01U) +#define FAULT_OUT_PIN PORT_PIN_PA12 + +/*** Macros for SDZ pin ***/ +#define SDZ_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 13U)) +#define SDZ_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 13U)) +#define SDZ_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 13U)) +#define SDZ_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 13U)) +#define SDZ_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 13U)) +#define SDZ_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 13U)) & 0x01U) +#define SDZ_PIN PORT_PIN_PA13 + +/*** Macros for X1_SNS pin ***/ +#define X1_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 16U)) & 0x01U) +#define X1_SNS_PIN PORT_PIN_PA16 + +/*** Macros for X2_SNS pin ***/ +#define X2_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 17U)) & 0x01U) +#define X2_SNS_PIN PORT_PIN_PA17 + +/*** Macros for X3_SNS pin ***/ +#define X3_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 18U)) & 0x01U) +#define X3_SNS_PIN PORT_PIN_PA18 + +/*** Macros for X4_SNS pin ***/ +#define X4_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 19U)) & 0x01U) +#define X4_SNS_PIN PORT_PIN_PA19 + +/*** Macros for X5_SNS pin ***/ +#define X5_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 20U)) & 0x01U) +#define X5_SNS_PIN PORT_PIN_PA20 + +/*** Macros for CAP_RES1_SNS pin ***/ +#define CAP_RES1_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 21U)) & 0x01U) +#define CAP_RES1_SNS_PIN PORT_PIN_PA21 + +/*** Macros for CAP_CANCEL2_SNS pin ***/ +#define CAP_CANCEL2_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 22U)) & 0x01U) +#define CAP_CANCEL2_SNS_PIN PORT_PIN_PA22 + +/*** Macros for CAP_CANCEL1_SNS pin ***/ +#define CAP_CANCEL1_SNS_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 23U)) & 0x01U) +#define CAP_CANCEL1_SNS_PIN PORT_PIN_PA23 + +/*** Macros for INP_0_EN pin ***/ +#define INP_0_EN_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 25U)) +#define INP_0_EN_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 25U)) +#define INP_0_EN_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 25U)) +#define INP_0_EN_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 25U)) +#define INP_0_EN_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 25U)) +#define INP_0_EN_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 25U)) & 0x01U) +#define INP_0_EN_PIN PORT_PIN_PA25 + +/*** Macros for SBC_INT pin ***/ +#define SBC_INT_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 30U)) & 0x01U) +#define SBC_INT_PIN PORT_PIN_PB30 + +/*** Macros for INTB_PRSS pin ***/ +#define INTB_PRSS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 31U)) & 0x01U) +#define INTB_PRSS_PIN PORT_PIN_PB31 + +/*** Macros for CAP_TJP2_SNS pin ***/ +#define CAP_TJP2_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 0U)) & 0x01U) +#define CAP_TJP2_SNS_PIN PORT_PIN_PB00 + +/*** Macros for CAP_TJP1_SNS pin ***/ +#define CAP_TJP1_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 1U)) & 0x01U) +#define CAP_TJP1_SNS_PIN PORT_PIN_PB01 + +/*** Macros for Power_AD_Ctrl pin ***/ +#define Power_AD_Ctrl_Set() (PORT_REGS->GROUP[1].PORT_OUTSET = ((uint32_t)1U << 2U)) +#define Power_AD_Ctrl_Clear() (PORT_REGS->GROUP[1].PORT_OUTCLR = ((uint32_t)1U << 2U)) +#define Power_AD_Ctrl_Toggle() (PORT_REGS->GROUP[1].PORT_OUTTGL = ((uint32_t)1U << 2U)) +#define Power_AD_Ctrl_OutputEnable() (PORT_REGS->GROUP[1].PORT_DIRSET = ((uint32_t)1U << 2U)) +#define Power_AD_Ctrl_InputEnable() (PORT_REGS->GROUP[1].PORT_DIRCLR = ((uint32_t)1U << 2U)) +#define Power_AD_Ctrl_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 2U)) & 0x01U) +#define Power_AD_Ctrl_PIN PORT_PIN_PB02 + +/*** Macros for CAP_RES2_SNS pin ***/ +#define CAP_RES2_SNS_Get() (((PORT_REGS->GROUP[1].PORT_IN >> 3U)) & 0x01U) +#define CAP_RES2_SNS_PIN PORT_PIN_PB03 + +// ***************************************************************************** +/* PORT Group + + Summary: + Identifies the port groups available on the device. + + Description: + These macros identifies all the ports groups that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the preprocessor macros as these may vary between devices. + + Port groups shown here are the ones available on the selected device. Not + all ports groups are implemented. Refer to the device specific datasheet + for more details. The MHC will generate these macros with the port + groups that are available on the device. +*/ + +/* Group 0 */ +#define PORT_GROUP_0 (PORT_BASE_ADDRESS + (0U * 0x80U)) + +/* Group 1 */ +#define PORT_GROUP_1 (PORT_BASE_ADDRESS + (1U * 0x80U)) + + +/* Helper macros to get port information from the pin */ +#define GET_PORT_GROUP(pin) ((PORT_GROUP)(PORT_BASE_ADDRESS + (0x80U * (((uint32_t)pin) >> 5U)))) +#define GET_PIN_MASK(pin) (((uint32_t)(0x1U)) << (((uint32_t)pin) & 0x1FU)) + +/* Named type for port group */ +typedef uint32_t PORT_GROUP; + + +typedef enum +{ +PERIPHERAL_FUNCTION_A = 0x0, +PERIPHERAL_FUNCTION_B = 0x1, +PERIPHERAL_FUNCTION_C = 0x2, +PERIPHERAL_FUNCTION_D = 0x3, +PERIPHERAL_FUNCTION_E = 0x4, +PERIPHERAL_FUNCTION_F = 0x5, +PERIPHERAL_FUNCTION_G = 0x6, +PERIPHERAL_FUNCTION_H = 0x7, +PERIPHERAL_FUNCTION_I = 0x8, +PERIPHERAL_FUNCTION_J = 0x9, +PERIPHERAL_FUNCTION_K = 0xA, +PERIPHERAL_FUNCTION_L = 0xB, +PERIPHERAL_FUNCTION_M = 0xC, +PERIPHERAL_FUNCTION_N = 0xD, + +}PERIPHERAL_FUNCTION; + +// ***************************************************************************** +/* PORT Pins + + Summary: + Identifies the available Ports pins. + + Description: + This enumeration identifies all the ports pins that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the enumeration constants as these may vary between devices. + + Port pins shown here are the ones available on the selected device. Not + all ports pins within a port group are implemented. Refer to the device + specific datasheet for more details. +*/ + +typedef enum +{ + /* PA00 pin */ + PORT_PIN_PA00 = 0U, + + /* PA01 pin */ + PORT_PIN_PA01 = 1U, + + /* PA02 pin */ + PORT_PIN_PA02 = 2U, + + /* PA03 pin */ + PORT_PIN_PA03 = 3U, + + /* PA04 pin */ + PORT_PIN_PA04 = 4U, + + /* PA05 pin */ + PORT_PIN_PA05 = 5U, + + /* PA06 pin */ + PORT_PIN_PA06 = 6U, + + /* PA07 pin */ + PORT_PIN_PA07 = 7U, + + /* PA08 pin */ + PORT_PIN_PA08 = 8U, + + /* PA09 pin */ + PORT_PIN_PA09 = 9U, + + /* PA10 pin */ + PORT_PIN_PA10 = 10U, + + /* PA11 pin */ + PORT_PIN_PA11 = 11U, + + /* PA12 pin */ + PORT_PIN_PA12 = 12U, + + /* PA13 pin */ + PORT_PIN_PA13 = 13U, + + /* PA14 pin */ + PORT_PIN_PA14 = 14U, + + /* PA15 pin */ + PORT_PIN_PA15 = 15U, + + /* PA16 pin */ + PORT_PIN_PA16 = 16U, + + /* PA17 pin */ + PORT_PIN_PA17 = 17U, + + /* PA18 pin */ + PORT_PIN_PA18 = 18U, + + /* PA19 pin */ + PORT_PIN_PA19 = 19U, + + /* PA20 pin */ + PORT_PIN_PA20 = 20U, + + /* PA21 pin */ + PORT_PIN_PA21 = 21U, + + /* PA22 pin */ + PORT_PIN_PA22 = 22U, + + /* PA23 pin */ + PORT_PIN_PA23 = 23U, + + /* PA24 pin */ + PORT_PIN_PA24 = 24U, + + /* PA25 pin */ + PORT_PIN_PA25 = 25U, + + /* PA27 pin */ + PORT_PIN_PA27 = 27U, + + /* PA30 pin */ + PORT_PIN_PA30 = 30U, + + /* PA31 pin */ + PORT_PIN_PA31 = 31U, + + /* PB00 pin */ + PORT_PIN_PB00 = 32U, + + /* PB01 pin */ + PORT_PIN_PB01 = 33U, + + /* PB02 pin */ + PORT_PIN_PB02 = 34U, + + /* PB03 pin */ + PORT_PIN_PB03 = 35U, + + /* PB04 pin */ + PORT_PIN_PB04 = 36U, + + /* PB05 pin */ + PORT_PIN_PB05 = 37U, + + /* PB06 pin */ + PORT_PIN_PB06 = 38U, + + /* PB07 pin */ + PORT_PIN_PB07 = 39U, + + /* PB08 pin */ + PORT_PIN_PB08 = 40U, + + /* PB09 pin */ + PORT_PIN_PB09 = 41U, + + /* PB10 pin */ + PORT_PIN_PB10 = 42U, + + /* PB11 pin */ + PORT_PIN_PB11 = 43U, + + /* PB12 pin */ + PORT_PIN_PB12 = 44U, + + /* PB13 pin */ + PORT_PIN_PB13 = 45U, + + /* PB14 pin */ + PORT_PIN_PB14 = 46U, + + /* PB15 pin */ + PORT_PIN_PB15 = 47U, + + /* PB16 pin */ + PORT_PIN_PB16 = 48U, + + /* PB17 pin */ + PORT_PIN_PB17 = 49U, + + /* PB22 pin */ + PORT_PIN_PB22 = 54U, + + /* PB23 pin */ + PORT_PIN_PB23 = 55U, + + /* PB30 pin */ + PORT_PIN_PB30 = 62U, + + /* PB31 pin */ + PORT_PIN_PB31 = 63U, + + /* This element should not be used in any of the PORT APIs. + * It will be used by other modules or application to denote that none of + * the PORT Pin is used */ + PORT_PIN_NONE = 65535U, + +} PORT_PIN; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Generated API based on pin configurations done in Pin Manager +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Example: + + + PORT_Initialize(); + + + + Remarks: + The function should be called once before calling any other PORTS PLIB + functions. +*/ + +void PORT_Initialize(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on multiple pins of a group +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the hardware state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_Read(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the output state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_GroupLatchRead(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + mask - A 32 bit value in which positions of 0s and 1s decide + which IO pins of the selected port group will be written. + 1's - Will write to corresponding IO pins. + 0's - Will remain unchanged. + + value - Value which has to be written/driven on the I/O + lines of the selected port for which mask bits are '1'. + Values for the corresponding mask bit '0' will be ignored. + Refer to the function description for effect on pins + which are not configured for output. + + Returns: + None. + + Example: + + + PORT_GroupWrite(PORT_GROUP_C, 0x0F, 0xF563D453); + + + + Remarks: + None. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 1. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupSet(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 1 on this pin will cause the pull + up to be enabled. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 0. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupClear(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will be toggled. If the + value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupToggle(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. Driving a logic 1 on this pin will cause the pull up to + be enabled. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + input. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupInputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + output. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupOutputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + None +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function); + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + None +*/ +void PORT_PinGPIOConfig(PORT_PIN pin); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on one pin at a time +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void PORT_PinWrite(PORT_PIN pin, bool value) + + Summary: + Writes the specified value to the selected pin. + + Description: + This function writes/drives the "value" on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called once. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + value - value to be written on the selected pin. + true = set pin to high (1). + false = clear pin to low (0). + + Returns: + None. + + Example: + + + bool value = true; + PORT_PinWrite(PORT_PIN_PB3, value); + + + + Remarks: + Calling this function with an input pin with the pull-up/pull-down feature + enabled will affect the pull-up/pull-down configuration. If the value is + false, the pull-down will be enabled. If the value is true, the pull-up will + be enabled. +*/ + +static inline void PORT_PinWrite(PORT_PIN pin, bool value) +{ + PORT_GroupWrite(GET_PORT_GROUP(pin), + GET_PIN_MASK(pin), + (value ? GET_PIN_MASK(pin) : 0U)); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinRead(PORT_PIN pin) + + Summary: + Read the selected pin value. + + Description: + This function reads the present state at the selected input pin. The + function can also be called to read the value of an output pin if input + sampling on the output pin is enabled in MHC. If input synchronization on + the pin is disabled in MHC, the function will cause a 2 PORT Clock cycles + delay. Enabling the synchronization eliminates the delay but will increase + power consumption. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + pin - the port pin whose state needs to be read. + + Returns: + true - the state at the pin is a logic high. + false - the state at the pin is a logic low. + + Example: + + + bool value; + value = PORT_PinRead(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline bool PORT_PinRead(PORT_PIN pin) +{ + return ((PORT_GroupRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinLatchRead(PORT_PIN pin) + + Summary: + Read the value driven on the selected pin. + + Description: + This function reads the data driven on the selected I/O line/pin. The + function does not sample the state of the hardware pin. It only returns the + value that is written to output register. Refer to the PORT_PinRead() + function if the state of the output pin needs to be read. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + true - the present value in the output latch is a logic high. + false - the present value in the output latch is a logic low. + + Example: + + + bool value; + value = PORT_PinLatchRead(PORT_PIN_PB3); + + + + Remarks: + To read actual pin value, PIN_Read API should be used. +*/ + +static inline bool PORT_PinLatchRead(PORT_PIN pin) +{ + return ((PORT_GroupLatchRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinToggle(PORT_PIN pin) + + Summary: + Toggles the selected pin. + + Description: + This function toggles/inverts the present value on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinToggle(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinToggle(PORT_PIN pin) +{ + PORT_GroupToggle(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinSet(PORT_PIN pin) + + Summary: + Sets the selected pin. + + Description: + This function drives a logic 1 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinSet(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinSet(PORT_PIN pin) +{ + PORT_GroupSet(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinClear(PORT_PIN pin) + + Summary: + Clears the selected pin. + + Description: + This function drives a logic 0 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinClear(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinClear(PORT_PIN pin) +{ + PORT_GroupClear(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinInputEnable(PORT_PIN pin) + + Summary: + Configures the selected IO pin as input. + + Description: + This function configures the selected IO pin as input. This function + override the MHC input output pin settings. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinInputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinInputEnable(PORT_PIN pin) +{ + PORT_GroupInputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinOutputEnable(PORT_PIN pin) + + Summary: + Enables selected IO pin as output. + + Description: + This function enables selected IO pin as output. Calling this function will + override the MHC input output pin configuration. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinOutputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinOutputEnable(PORT_PIN pin) +{ + PORT_GroupOutputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +} + +#endif +// DOM-IGNORE-END +#endif // PLIB_PORT_H diff --git a/firmware/src/config/mcal/peripheral/rtc/plib_rtc.h b/firmware/src/config/mcal/peripheral/rtc/plib_rtc.h new file mode 100644 index 0000000..b022b73 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/rtc/plib_rtc.h @@ -0,0 +1,140 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc.h + + Summary: + RTC PLIB Header file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_RTC_H +#define PLIB_RTC_H + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +/* Frequency of Counter Clock for RTC */ +#define RTC_COUNTER_CLOCK_FREQUENCY (1024U / (1UL << (0x1U - 1U))) + +#define RTC_TIMER32_INT_MASK_PER0 RTC_MODE0_INTENSET_PER0_Msk +#define RTC_TIMER32_INT_MASK_PER1 RTC_MODE0_INTENSET_PER1_Msk +#define RTC_TIMER32_INT_MASK_PER2 RTC_MODE0_INTENSET_PER2_Msk +#define RTC_TIMER32_INT_MASK_PER3 RTC_MODE0_INTENSET_PER3_Msk +#define RTC_TIMER32_INT_MASK_PER4 RTC_MODE0_INTENSET_PER4_Msk +#define RTC_TIMER32_INT_MASK_PER5 RTC_MODE0_INTENSET_PER5_Msk +#define RTC_TIMER32_INT_MASK_PER6 RTC_MODE0_INTENSET_PER6_Msk +#define RTC_TIMER32_INT_MASK_PER7 RTC_MODE0_INTENSET_PER7_Msk +#define RTC_TIMER32_INT_MASK_CMP0 RTC_MODE0_INTENSET_CMP0_Msk +#define RTC_TIMER32_INT_MASK_CMP1 RTC_MODE0_INTENSET_CMP1_Msk +#define RTC_TIMER32_INT_MASK_TAMPER RTC_MODE0_INTENSET_TAMPER_Msk +#define RTC_TIMER32_INT_MASK_OVF RTC_MODE0_INTENSET_OVF_Msk +#define RTC_TIMER32_INT_MASK_INVALID 0xFFFFFFFFU +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +typedef uint32_t RTC_TIMER32_INT_MASK; +typedef enum +{ + BACKUP_REGISTER_0 = 0U, + BACKUP_REGISTER_1 = 1U, + BACKUP_REGISTER_2 = 2U, + BACKUP_REGISTER_3 = 3U, + BACKUP_REGISTER_4 = 4U, + BACKUP_REGISTER_5 = 5U, + BACKUP_REGISTER_6 = 6U, + BACKUP_REGISTER_7 = 7U +} BACKUP_REGISTER; + #define TAMPER_CHANNEL_0 (0U) + #define TAMPER_CHANNEL_1 (1U) + #define TAMPER_CHANNEL_2 (2U) + #define TAMPER_CHANNEL_3 (3U) + #define TAMPER_CHANNEL_4 (4U) +typedef uint32_t TAMPER_CHANNEL; +typedef void (*RTC_TIMER32_CALLBACK)( RTC_TIMER32_INT_MASK intCause, uintptr_t context ); + +typedef struct +{ + /* Timer 32Bit */ + RTC_TIMER32_CALLBACK timer32BitCallback; + RTC_TIMER32_INT_MASK timer32intCause; + uintptr_t context; +} RTC_OBJECT; + +void RTC_Initialize(void); +void RTC_Timer32CountSyncEnable ( void ); +void RTC_Timer32CountSyncDisable ( void ); +void RTC_Timer32Start ( void ); +void RTC_Timer32Stop ( void ); +void RTC_Timer32CounterSet ( uint32_t count ); +uint32_t RTC_Timer32CounterGet ( void ); +uint32_t RTC_Timer32FrequencyGet ( void ); +void RTC_Timer32Compare0Set ( uint32_t compareValue ); +void RTC_Timer32Compare1Set ( uint32_t compareValue ); +uint32_t RTC_Timer32PeriodGet ( void ); +void RTC_Timer32InterruptEnable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32InterruptDisable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_BackupRegisterSet( BACKUP_REGISTER reg, uint32_t value ); +uint32_t RTC_BackupRegisterGet( BACKUP_REGISTER reg ); +TAMPER_CHANNEL RTC_TamperSourceGet( void ); +uint32_t RTC_Timer32TimeStampGet( void ); +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_RTC_H */ diff --git a/firmware/src/config/mcal/peripheral/rtc/plib_rtc_timer.c b/firmware/src/config/mcal/peripheral/rtc/plib_rtc_timer.c new file mode 100644 index 0000000..71ea13c --- /dev/null +++ b/firmware/src/config/mcal/peripheral/rtc/plib_rtc_timer.c @@ -0,0 +1,229 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc_timer.c + + Summary: + RTC PLIB Implementation file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance in timer mode. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_rtc.h" +#include +#include + +static RTC_OBJECT rtcObj; + + +void RTC_Initialize(void) +{ + RTC_REGS->MODE0.RTC_CTRLA = RTC_MODE0_CTRLA_SWRST_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_SWRST_Msk) == RTC_MODE0_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization after Software Reset */ + } + + + + RTC_REGS->MODE0.RTC_CTRLA = (uint16_t)(RTC_MODE0_CTRLA_MODE(0UL) | RTC_MODE0_CTRLA_PRESCALER(0x1UL) |RTC_MODE0_CTRLA_MATCHCLR_Msk ); + RTC_REGS->MODE0.RTC_COMP[0] = 0x1U; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } + + RTC_REGS->MODE0.RTC_COMP[1] = 0x0U; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP1_Msk) == RTC_MODE0_SYNCBUSY_COMP1_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } + + RTC_REGS->MODE0.RTC_INTENSET = 0x100U; + +} + + +void RTC_Timer32CountSyncEnable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32CountSyncDisable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_COUNTSYNC_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32Start ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_ENABLE_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for synchronization after Enabling RTC */ + } +} + + +void RTC_Timer32Stop ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_ENABLE_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization after Disabling RTC */ + } +} + +void RTC_Timer32CounterSet ( uint32_t count ) +{ + RTC_REGS->MODE0.RTC_COUNT = count; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization after writing value to Count Register */ + } +} + +void RTC_Timer32Compare0Set ( uint32_t compareValue ) +{ + RTC_REGS->MODE0.RTC_COMP[0] = compareValue; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } +} +void RTC_Timer32Compare1Set ( uint32_t compareValue ) +{ + RTC_REGS->MODE0.RTC_COMP[1] = compareValue; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP1_Msk) == RTC_MODE0_SYNCBUSY_COMP1_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } +} +uint32_t RTC_Timer32CounterGet ( void ) +{ + if ((RTC_REGS->MODE0.RTC_CTRLA & RTC_MODE0_CTRLA_COUNTSYNC_Msk) == 0U) + { + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + } + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization before reading value from Count Register */ + } + return(RTC_REGS->MODE0.RTC_COUNT); +} + +uint32_t RTC_Timer32PeriodGet ( void ) +{ + /* Get 32Bit Compare Value */ + /*lint -e{9048} PC lint incorrectly reports a missing 'U' Suffix */ + return (RTC_MODE0_COUNT_COUNT_Msk); +} + +uint32_t RTC_Timer32FrequencyGet ( void ) +{ + /* Return Frequency of RTC Clock */ + return RTC_COUNTER_CLOCK_FREQUENCY; +} + +void RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENSET = (uint16_t)interruptMask; +} + +void RTC_Timer32InterruptDisable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENCLR = (uint16_t)interruptMask; +} + +void RTC_BackupRegisterSet( BACKUP_REGISTER reg, uint32_t value ) +{ + RTC_REGS->MODE0.RTC_BKUP[reg] = value; +} + +uint32_t RTC_BackupRegisterGet( BACKUP_REGISTER reg ) +{ + return(RTC_REGS->MODE0.RTC_BKUP[reg]); +} + TAMPER_CHANNEL RTC_TamperSourceGet( void ) +{ + return((TAMPER_CHANNEL) ((RTC_REGS->MODE0.RTC_TAMPID) & (0xFFU))); +} + +uint32_t RTC_Timer32TimeStampGet( void ) +{ + return(RTC_REGS->MODE0.RTC_TIMESTAMP); +} + +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ) +{ + rtcObj.timer32BitCallback = callback; + rtcObj.context = context; +} + +void RTC_InterruptHandler( void ) +{ + rtcObj.timer32intCause = (RTC_TIMER32_INT_MASK) RTC_REGS->MODE0.RTC_INTFLAG; + RTC_REGS->MODE0.RTC_INTFLAG = (uint16_t)RTC_MODE0_INTFLAG_Msk; + (void)RTC_REGS->MODE0.RTC_INTFLAG; + + /* Invoke registered Callback function */ + if(rtcObj.timer32BitCallback != NULL) + { + rtcObj.timer32BitCallback( rtcObj.timer32intCause, rtcObj.context ); + } +} diff --git a/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c new file mode 100644 index 0000000..ccb496c --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c @@ -0,0 +1,588 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.c + + Summary: + SERCOM I2C PLIB Implementation file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. + This library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "interrupts.h" +#include "plib_sercom1_i2c_master.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + + +#define SERCOM1_I2CM_SPEED_HZ 100000 + +/* SERCOM1 I2C baud value */ +#define SERCOM1_I2CM_BAUD_VALUE (0x22U) + + +static SERCOM_I2C_OBJ sercom1I2CObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM1 I2C Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM1_I2C_Initialize(void) +{ + /* Reset the module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable smart mode */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = SERCOM1_I2CM_BAUD_VALUE; + + /* Set Operation Mode (Master), SDA Hold time, run in stand by and i2c master enable */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | SERCOM_I2CM_CTRLA_SDAHOLD_75NS | SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE | SERCOM_I2CM_CTRLA_SCLSM(0UL) | SERCOM_I2CM_CTRLA_ENABLE_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initial Bus State: IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize the SERCOM1 PLib Object */ + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Enable all Interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; +} + +static bool SERCOM1_I2C_CalculateBaudValue(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t* baudVal) +{ + uint32_t baudValue = 0U; + float fSrcClkFreq = (float)srcClkFreq; + float fI2cClkSpeed = (float)i2cClkSpeed; + float fBaudValue = 0.0f; + + /* Reference clock frequency must be atleast two times the baud rate */ + if (srcClkFreq < (2U * i2cClkSpeed)) + { + return false; + } + + if (i2cClkSpeed <= 1000000U) + { + /* Standard, FM and FM+ baud calculation */ + fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); + baudValue = (uint32_t)fBaudValue; + } + else + { + return false; + } + if (i2cClkSpeed <= 400000U) + { + /* For I2C clock speed upto 400 kHz, the value of BAUD<7:0> determines both SCL_L and SCL_H with SCL_L = SCL_H */ + if (baudValue > (0xFFU * 2U)) + { + /* Set baud rate to the minimum possible value */ + baudValue = 0xFFU; + } + else if (baudValue <= 1U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value */ + baudValue = 1U; + } + else + { + baudValue /= 2U; + } + } + else + { + /* To maintain the ratio of SCL_L:SCL_H to 2:1, the max value of BAUD_LOW<15:8>:BAUD<7:0> can be 0xFF:0x7F. Hence BAUD_LOW + BAUD can not exceed 255+127 = 382 */ + if (baudValue >= 382U) + { + /* Set baud rate to the minimum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (0xFFUL << 8U) | (0x7FU); + } + else if (baudValue <= 3U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (2UL << 8U) | 1U; + } + else + { + /* For Fm+ mode, I2C SCL_L:SCL_H to 2:1 */ + baudValue = ((((baudValue * 2U)/3U) << 8U) | (baudValue/3U)); + } + } + *baudVal = baudValue; + return true; +} + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ) +{ + uint32_t baudValue; + uint32_t i2cClkSpeed; + uint32_t i2cSpeedMode = 0; + + if (setup == NULL) + { + return false; + } + + i2cClkSpeed = setup->clkSpeed; + + if( srcClkFreq == 0U) + { + srcClkFreq = 8000000UL; + } + + if (SERCOM1_I2C_CalculateBaudValue(srcClkFreq, i2cClkSpeed, &baudValue) == false) + { + return false; + } + + if (i2cClkSpeed > 400000U) + { + i2cSpeedMode = 1U; + } + + /* Disable the I2C before changing the I2C clock speed */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = baudValue; + + SERCOM1_REGS->I2CM.SERCOM_CTRLA = ((SERCOM1_REGS->I2CM.SERCOM_CTRLA & ~SERCOM_I2CM_CTRLA_SPEED_Msk) | (SERCOM_I2CM_CTRLA_SPEED(i2cSpeedMode))); + + /* Re-enable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return true; +} + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle) +{ + sercom1I2CObj.callback = callback; + + sercom1I2CObj.context = contextHandle; +} + + +static void SERCOM1_I2C_SendAddress(uint16_t address, bool dir) +{ + /* If operation is I2C read */ + if(dir) + { + /*

*/ + + /* Next state will be to read data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + } + else + { + /*

*/ + + /* Next state will be to write data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_WRITE; + } + + + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)address << 1U) | (dir ? 1UL :0UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + +} + +static void SERCOM1_I2C_InitiateTransfer(uint16_t address, bool dir) +{ + sercom1I2CObj.writeCount = 0U; + sercom1I2CObj.readCount = 0U; + + /* Clear all flags */ + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Smart mode enabled with SCLSM = 0, - ACK is set to send while receiving the data */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB &= ~SERCOM_I2CM_CTRLB_ACKACT_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_I2C_SendAddress(address, dir); +} + +static bool SERCOM1_I2C_XferSetup( + uint16_t address, + uint8_t* wrData, + uint32_t wrLength, + uint8_t* rdData, + uint32_t rdLength, + bool dir, + bool isHighSpeed +) +{ + /* Check for ongoing transfer */ + if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) + { + return false; + } + + sercom1I2CObj.address = address; + sercom1I2CObj.readBuffer = rdData; + sercom1I2CObj.readSize = rdLength; + sercom1I2CObj.writeBuffer = wrData; + sercom1I2CObj.writeSize = wrLength; + sercom1I2CObj.transferDir = dir; + sercom1I2CObj.isHighSpeed = isHighSpeed; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + + SERCOM1_I2C_InitiateTransfer(address, dir); + + return true; +} + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, NULL, 0, rdData, rdLength, true, false); +} + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, NULL, 0, false, false); +} + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, rdData, rdLength, false, false); +} + + +bool SERCOM1_I2C_IsBusy(void) +{ + bool isBusy = true; + if((sercom1I2CObj.state == SERCOM_I2C_STATE_IDLE)) + { + if(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01UL))) + { + isBusy = false; + } + } + return isBusy; +} + +bool SERCOM1_I2C_send_done(void) +{ + bool ret = 0; + + if((sercom1I2CObj.writeCount==sercom1I2CObj.writeSize) && (sercom1I2CObj.readSize == 0)) + { + ret =1; + } + + return ret; +} + + +bool SERCOM1_I2C_rx_done(void) +{ + bool ret = 0; + + if((sercom1I2CObj.writeCount==sercom1I2CObj.writeSize) && (sercom1I2CObj.readSize == sercom1I2CObj.readCount)) + { + ret =1; + } + + + return ret; +} + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void) +{ + return sercom1I2CObj.error; +} + +void SERCOM1_I2C_InterruptHandler(void) +{ + if(SERCOM1_REGS->I2CM.SERCOM_INTENSET != 0U) + { + /* Checks if the arbitration lost in multi-master scenario */ + if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_ARBLOST_Msk) == SERCOM_I2CM_STATUS_ARBLOST_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + + } + /* Check for Bus Error during transmission */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSERR_Msk) == SERCOM_I2CM_STATUS_BUSERR_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + } + /* Checks slave acknowledge for address or data */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_RXNACK_Msk) == SERCOM_I2CM_STATUS_RXNACK_Msk) + { + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NAK; + } + else + { + switch(sercom1I2CObj.state) + { + case SERCOM_I2C_REINITIATE_TRANSFER: + + if (sercom1I2CObj.writeSize != 0U) + { + /* Initiate Write transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, false); + } + else + { + /* Initiate Read transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, true); + } + + break; + + + case SERCOM_I2C_STATE_IDLE: + + break; + + + + case SERCOM_I2C_STATE_TRANSFER_WRITE: + + if (sercom1I2CObj.writeCount == (sercom1I2CObj.writeSize)) + { + if(sercom1I2CObj.readSize != 0U) + { + + /* Write 7bit address with direction (ADDR.ADDR[0]) equal to 1*/ + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)(sercom1I2CObj.address) << 1U) | (uint32_t)I2C_TRANSFER_READ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + + } + else + { + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + } + /* Write next byte */ + else + { + SERCOM1_REGS->I2CM.SERCOM_DATA = sercom1I2CObj.writeBuffer[sercom1I2CObj.writeCount++]; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } + + break; + + case SERCOM_I2C_STATE_TRANSFER_READ: + + if(sercom1I2CObj.readCount == (sercom1I2CObj.readSize - 1U)) + { + /* Set NACK and send stop condition to the slave from master */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Read the received data */ + sercom1I2CObj.readBuffer[sercom1I2CObj.readCount++] = SERCOM1_REGS->I2CM.SERCOM_DATA; + + + break; + + default: + + /* Do nothing */ + break; + } + } + + /* Error Status */ + if(sercom1I2CObj.state == SERCOM_I2C_STATE_ERROR) + { + /* Reset the PLib objects and Interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Generate STOP condition */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + if (sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(sercom1I2CObj.context); + } + } + /* Transfer Complete */ + else if(sercom1I2CObj.state == SERCOM_I2C_STATE_TRANSFER_DONE) + { + /* Reset the PLib objects and interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Wait for the NAK and STOP bit to be transmitted out and I2C state machine to rest in IDLE state */ + //while((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01UL)) + { + /* Do nothing */ + } + + if(sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(sercom1I2CObj.context); + } + + } + else + { + /* Do nothing */ + } + } + + return; +} \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h new file mode 100644 index 0000000..60dab1e --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h @@ -0,0 +1,102 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.h + + Summary: + SERCOM I2C PLIB Header file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM1_I2C_H +#define PLIB_SERCOM1_I2C_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_i2c_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* + * The following functions make up the methods (set of possible operations) of + * this interface. + */ + +void SERCOM1_I2C_Initialize(void); + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength); + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_IsBusy(void); + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void); + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle); + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ); + +bool SERCOM1_I2C_send_done(void); + +bool SERCOM1_I2C_rx_done(void); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM1_I2C_H */ diff --git a/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h new file mode 100644 index 0000000..13a73f5 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h @@ -0,0 +1,260 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company + Microchip Technology Inc. + + File Name + plib_sercom_i2c_master.h + + Summary + SERCOM I2C peripheral library interface. + + Description + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_I2C_MASTER_H +#define PLIB_SERCOM_I2C_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SERCOM I2C Transfer type + + Summary: + List of transfer direction. + + Description: + This enum defines the I2C transfer direction. + + Remarks: + None. +*/ + +enum +{ + I2C_TRANSFER_WRITE = 0, + I2C_TRANSFER_READ = 1, +}; + +// ***************************************************************************** +/* SERCOM I2C Error. + + Summary: + Defines the possible errors that the SERCOM I2C peripheral can generate. + + Description: + This enum defines the possible error the SERCOM I2C peripheral can generate. + An error of this type is returned by the SERCOMx_I2C_ErrorGet() function. + + Remarks: + None. +*/ + +typedef enum +{ + /* No error has occurred. */ + SERCOM_I2C_ERROR_NONE, + + /* A bus transaction was NAK'ed */ + SERCOM_I2C_ERROR_NAK, + + /* A bus error has occurred. */ + SERCOM_I2C_ERROR_BUS, + +} SERCOM_I2C_ERROR; + +// ***************************************************************************** +/* SERCOM I2C State. + + Summary: + SERCOM I2C PLib Task State. + + Description: + This data type defines the SERCOM I2C PLib Task State. + + Remarks: + None. +*/ + +typedef enum +{ + /* SERCOM PLib Task Error State */ + SERCOM_I2C_STATE_ERROR = -1, + + /* SERCOM PLib Task Idle State */ + SERCOM_I2C_STATE_IDLE, + + /* SERCOM PLib Task Address Send State */ + SERCOM_I2C_STATE_ADDR_SEND, + + SERCOM_I2C_REINITIATE_TRANSFER, + /* SERCOM PLib Task Read Transfer State */ + SERCOM_I2C_STATE_TRANSFER_READ, + + /* SERCOM PLib Task Write Transfer State */ + SERCOM_I2C_STATE_TRANSFER_WRITE, + + /* SERCOM PLib Task High Speed Slave Address Send State */ + SERCOM_I2C_STATE_TRANSFER_ADDR_HS, + + /* SERCOM PLib Task Transfer Done State */ + SERCOM_I2C_STATE_TRANSFER_DONE, + +} SERCOM_I2C_STATE; + +// ***************************************************************************** +/* SERCOM I2C Callback + + Summary: + SERCOM I2C Callback Function Pointer. + + Description: + This data type defines the SERCOM I2C Callback Function Pointer. + + Remarks: + None. +*/ + +typedef void (*SERCOM_I2C_CALLBACK) +( + /*Transfer context*/ + uintptr_t contextHandle + +); + +// ***************************************************************************** +/* SERCOM I2C PLib Instance Object + + Summary: + SERCOM I2C PLib Object structure. + + Description: + This data structure defines the SERCOM I2C PLib Instance Object. + + Remarks: + None. +*/ + +typedef struct +{ + bool isHighSpeed; + + bool txMasterCode; + + bool transferDir; + + uint16_t address; + + uint8_t masterCode; + + uint8_t* writeBuffer; + + uint8_t* readBuffer; + + size_t writeSize; + + size_t readSize; + + size_t writeCount; + + size_t readCount; + + /* State */ + volatile SERCOM_I2C_STATE state; + + /* Transfer status */ + volatile SERCOM_I2C_ERROR error; + + /* Transfer Event Callback */ + SERCOM_I2C_CALLBACK callback; + + /* Transfer context */ + uintptr_t context; + +} SERCOM_I2C_OBJ; + +// ***************************************************************************** +/* Transaction Request Block + + Summary: + Transaction Request Block Structure. + + Description: + This data structure defines the Transaction Request Block. + + Remarks: + None. +*/ + +typedef struct +{ + /* SERCOM I2C Clock Speed */ + uint32_t clkSpeed; + +} SERCOM_I2C_TRANSFER_SETUP; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM_I2C_MASTER_H */ \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c new file mode 100644 index 0000000..a7022d5 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.c @@ -0,0 +1,595 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE(SERCOM0_SPI) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.c + + Summary + SERCOM0_SPI Master PLIB Implementation File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_sercom0_spi_master.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: MACROS Definitions +// ***************************************************************************** +// ***************************************************************************** + + +/* SERCOM0 clk freq value for the baud calculation */ +#define SERCOM0_Frequency (8000000UL) + +/* SERCOM0 SPI baud value for 1000000 Hz baud rate */ +#define SERCOM0_SPIM_BAUD_VALUE (3UL) + +/*Global object to save SPI Exchange related data */ +static SPI_OBJECT sercom0SPIObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM0_SPI Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize(void); + + Summary: + Initializes instance SERCOM0 of the SERCOM module operating in SPI mode. + + Description: + This function initializes instance SERCOM0 of SERCOM module operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_Initialize(void) +{ + /* Instantiate the SERCOM0 SPI object */ + sercom0SPIObj.callback = NULL ; + sercom0SPIObj.transferIsBusy = false ; + sercom0SPIObj.txSize = 0U; + sercom0SPIObj.rxSize = 0U; + + /* Selection of the Character Size and Receiver Enable */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT | SERCOM_SPIM_CTRLB_RXEN_Msk ; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)SERCOM_SPIM_BAUD_BAUD(SERCOM0_SPIM_BAUD_VALUE); + + /* Configure Data Out Pin Out , Master Mode, + * Data In and Pin Out,Data Order and Standby mode if configured + * and Selection of the Clock Phase and Polarity and Enable the SPI Module + */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD0 | SERCOM_SPIM_CTRLA_DIPO_PAD3 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE | SERCOM_SPIM_CTRLA_DORD_LSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; + + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation parameters, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock) +{ + uint32_t baudValue = 0U; + + bool statusValue = false; + + if(spiSourceClock == 0U) + { + /* Fetch Master Clock Frequency directly */ + spiSourceClock = SERCOM0_Frequency; + } + + /* Disable the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_ENABLE_Msk); + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + if(setup != NULL) + { + if (setup->clockFrequency <= spiSourceClock/2U) + { + baudValue = (spiSourceClock/(2U*(setup->clockFrequency))) - 1U; + + /* Set the lowest possible baud */ + if (baudValue >= 255U) + { + baudValue = 255U; + } + + /* Selection of the Clock Polarity and Clock Phase */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_CPOL_Msk | SERCOM_SPIM_CTRLA_CPHA_Msk); + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= (uint32_t)setup->clockPolarity | (uint32_t)setup->clockPhase; + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)baudValue; + + /* Selection of the Character Size */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB &= ~SERCOM_SPIM_CTRLB_CHSIZE_Msk; + SERCOM0_REGS->SPIM.SERCOM_CTRLB |= (uint32_t)setup->dataBits; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + statusValue = true; + } + } + + /* Enabling the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= SERCOM_SPIM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return statusValue; +} + + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context ) +{ + sercom0SPIObj.callback = callBack; + + sercom0SPIObj.context = context; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy(void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_IsBusy(void) +{ + bool isBusy = false; + if ((sercom0SPIObj.txSize == 0U) && (sercom0SPIObj.rxSize == 0U)) + { + /* This means no transfer has been requested yet; hence SPI is not busy. */ + isBusy = false; + } + else + { + /* if transmit is not complete or if the state flag is not set, SPI is busy */ + isBusy = (((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U) || sercom0SPIObj.transferIsBusy); + } + return isBusy; +} + +bool SERCOM0_SPI_IsTransmitterBusy(void) +{ + return ((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U)? true : false; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize) +{ + bool isRequestAccepted = false; + uint32_t dummyData = 0U; + + /* Verify the request */ + if((((txSize > 0U) && (pTransmitData != NULL)) || ((rxSize > 0U) && (pReceiveData != NULL))) && (sercom0SPIObj.transferIsBusy == false)) + { + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_9) + { + /* For 9-bit transmission, the txSize and rxSize must be an even number. */ + if(((txSize > 0U) && ((txSize & 0x01U) != 0U)) || ((rxSize > 0U) && ((rxSize & 0x01U) != 0U))) + { + return isRequestAccepted; + } + } + + isRequestAccepted = true; + sercom0SPIObj.txBuffer = pTransmitData; + sercom0SPIObj.rxBuffer = pReceiveData; + sercom0SPIObj.rxCount = 0U; + sercom0SPIObj.txCount = 0U; + sercom0SPIObj.dummySize = 0U; + + if(pTransmitData != NULL) + { + sercom0SPIObj.txSize = txSize; + } + else + { + sercom0SPIObj.txSize = 0U; + } + + if(pReceiveData != NULL) + { + sercom0SPIObj.rxSize = rxSize; + } + else + { + sercom0SPIObj.rxSize = 0U; + } + + sercom0SPIObj.transferIsBusy = true; + + /* Flush out any unread data in SPI read buffer */ + while((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + dummyData = SERCOM0_REGS->SPIM.SERCOM_DATA; + (void)dummyData; + } + + SERCOM0_REGS->SPIM.SERCOM_STATUS |= SERCOM_SPIM_STATUS_BUFOVF_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTFLAG |= (uint8_t)SERCOM_SPIM_INTFLAG_ERROR_Msk; + + if(sercom0SPIObj.rxSize > sercom0SPIObj.txSize) + { + sercom0SPIObj.dummySize = sercom0SPIObj.rxSize - sercom0SPIObj.txSize; + } + + /* Start the first write here itself, rest will happen in ISR context */ + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_8) + { + if(sercom0SPIObj.txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint8_t*)sercom0SPIObj.txBuffer); + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + sercom0SPIObj.txSize >>= 1U; + sercom0SPIObj.dummySize >>= 1U; + sercom0SPIObj.rxSize >>= 1U; + + if(sercom0SPIObj.txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint16_t*)sercom0SPIObj.txBuffer) & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if(rxSize > 0U) + { + /* Enable ReceiveComplete */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_RXC_Msk; + } + else + { + /* Enable the DataRegisterEmpty */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + } + } + + return isRequestAccepted; +} + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize) +{ + return SERCOM0_SPI_WriteRead(pTransmitData, txSize, NULL, 0U); +} + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize) +{ + return SERCOM0_SPI_WriteRead(NULL, 0U, pReceiveData, rxSize); +} + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_InterruptHandler(void); + + Summary: + Handler that handles the SPI interrupts + + Description: + This Function is called from the handler to handle the exchange based on the + Interrupts. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_InterruptHandler(void) +{ + uint32_t dataBits = 0U; + uint32_t receivedData = 0U; + static bool isLastByteTransferInProgress = false; + + if(SERCOM0_REGS->SPIM.SERCOM_INTENSET != 0U) + { + dataBits = SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk; + + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + receivedData = SERCOM0_REGS->SPIM.SERCOM_DATA; + + if(sercom0SPIObj.rxCount < sercom0SPIObj.rxSize) + { + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + ((uint8_t*)sercom0SPIObj.rxBuffer)[sercom0SPIObj.rxCount] = (uint8_t)receivedData; + sercom0SPIObj.rxCount++; + } + else + { + ((uint16_t*)sercom0SPIObj.rxBuffer)[sercom0SPIObj.rxCount] = (uint16_t)receivedData; + sercom0SPIObj.rxCount++; + } + } + } + + /* If there are more words to be transmitted, then transmit them here and keep track of the count */ + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_DRE_Msk) == SERCOM_SPIM_INTFLAG_DRE_Msk) + { + /* Disable the DRE interrupt. This will be enabled back if more than + * one byte is pending to be transmitted */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_DRE_Msk; + + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + if(sercom0SPIObj.txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint8_t*)sercom0SPIObj.txBuffer)[sercom0SPIObj.txCount]; + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + if(sercom0SPIObj.txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint16_t*)sercom0SPIObj.txBuffer)[sercom0SPIObj.txCount]; + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if((sercom0SPIObj.txCount == sercom0SPIObj.txSize) && (sercom0SPIObj.dummySize == 0U)) + { + /* At higher baud rates, the data in the shift register can be + * shifted out and TXC flag can get set resulting in a + * callback been given to the application with the SPI interrupt + * pending with the application. This will then result in the + * interrupt handler being called again with nothing to transmit. + * To avoid this, a software flag is set, but + * the TXC interrupt is not enabled until the very end. + */ + + isLastByteTransferInProgress = true; + } + else if(sercom0SPIObj.rxCount == sercom0SPIObj.rxSize) + { + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_RXC_Msk; + } + else + { + /* Do nothing */ + } + } + + if(((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == SERCOM_SPIM_INTFLAG_TXC_Msk) && (isLastByteTransferInProgress == true)) + { + if(sercom0SPIObj.rxCount == sercom0SPIObj.rxSize) + { + sercom0SPIObj.transferIsBusy = false; + + /* Disable the Data Register empty and Receive Complete Interrupt flags */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)(SERCOM_SPIM_INTENCLR_DRE_Msk | SERCOM_SPIM_INTENCLR_RXC_Msk | SERCOM_SPIM_INTENSET_TXC_Msk); + + isLastByteTransferInProgress = false; + + if(sercom0SPIObj.callback != NULL) + { + sercom0SPIObj.callback(sercom0SPIObj.context); + } + } + } + + if(isLastByteTransferInProgress == true) + { + /* For the last byte transfer, the DRE interrupt is already disabled. + * Enable TXC interrupt to ensure no data is present in the shift + * register before application callback is called. + */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_TXC_Msk; + } + } +} diff --git a/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.h b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.h new file mode 100644 index 0000000..16b5016 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom0_spi_master.h @@ -0,0 +1,624 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE (SERCOM0_SPI ) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.h + + Summary + SERCOM0_SPI Master PLIB Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM0_SPI_MASTER_H // Guards against multiple inclusion +#define PLIB_SERCOM0_SPI_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_spi_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize (void); + + Summary: + Initializes instance SERCOM0 operating in SPI mode. + + Description: + This function initializes instance SERCOM0 operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Precondition: + MCC GUI should be configured with the right values. The Generic Clock + configuration and the SERCOM Peripheral Clock channel should have been + configured in the clock manager GUI.The function will itself enable the + required peripheral clock channel and main clock. + + Parameters: + None. + + Returns: + None. + + Example: + + SERCOM0_SPI_Initialize(); + + + Remarks: + This function must be called once before any other SPI function is called. +*/ + +void SERCOM0_SPI_Initialize (void); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation paramertes, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Precondition: + SERCOM SERCOM0 SPI must first be initialized using SERCOM0_SPI_Initialize(). + + Parameters : + setup - pointer to the data structure of type SPI_TRANSFER_SETUP containing + the operation parameters. Each operation parameter must be specified even if + the parameter does not need to change. + + spiSourceClock - Current value of GCLK frequency feeding the SERCOM0 core. + + Returns: + true - setup was successful. + + false - if spiSourceClock and spi clock frequencies are such that resultant + baud value is out of the possible range. + + Example: Assuming 20 MHz as peripheral Master clock frequency + + SPI_TRANSFER_SETUP setup; + setup.clockFrequency = 1000000; + setup.clockPhase = SPI_CLOCK_PHASE_TRAILING_EDGE; + setup.clockPolarity = SPI_CLOCK_POLARITY_IDLE_LOW; + setup.dataBits = SPI_DATA_BITS_8; + + if (SERCOM0_SPI_TransferSetup (&setup, 20000000) == false) + { + this means setup could not be done, debug the reason. + } + + + + Remarks: + The application would need to call this function only if the operational + parameter need to be different than the ones configured in MHC. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. If the + peripheral instance has been configured for Interrupt mode and transfer + completion status needs to be communicated back to application via callback, + a callback should have been registered using SERCOM0_SPI_CallbackRegister() + function. + + Parameters: + pTransmitData - Pointer to the data which has to be transmitted. In a case + where only data reception is required, this pointer can be set to NULL. If + the module is configured for 9 bit data length, the data should be right + aligned in a 16 bit memory location. The size of this buffer should be + txSize. + + txSize - Number of bytes to be transmitted. For 9 but data length, a count + of 1 counts 2 bytes. This value can be different from rxSize. + + pReceiveData - Pointer to the location where the received data has to be + stored. It is user's responsibility to ensure that this location has + sufficient memory to store rxSize amount of data. In a case where only data + transmission is required, this pointer can be set to NULL. If the module is + configured for 9 bit data length, received data will be right aligned and + will be stored in a 16 bit memory location. + + rxSize - Number of bytes to be received. This value can be different from + txSize. For 9 bit data length, a size count of 1 indicates 2 bytes required + to store 9 bits of data. + + Returns: + true - If configured for Non-interrupt mode, the function has recevied and + transmitted the requested number of bytes. If configured for Interrupt mode, + the request was accepted successfully and will be processed in the + interrupt. + + false - If both pTransmitData and pReceiveData are NULL, or if both txSize + and rxSize are 0 or if txSize is non-zero but the pTransmitData is set to + NULL or rxSize is non-zero but pReceiveData is NULL. In Interrupt mode, the + function returns false if there is an on-going data transfer at the time of + calling the function. + + Example: + + + The following code snippet shows an example using the + SERCOM0_SPI_WriteRead() function in interrupt mode operation using the + callback function. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + The following code snippet shows non-interrupt or blocking mode + operation. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + This function call will block. + SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize); + + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + + Summary: + Writes data to SERCOM SERCOM0 SPI peripheral. + + Description: + This function writes "txSize" number of bytes on SERCOM SERCOM0 SPI module. Data + pointed by pTransmitData is transmitted. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pTransmitData - Pointer to the buffer containing the data which has to be + transmitted. For 9 bit mode, data should be right aligned in the 16 bit + memory location. In "Interrupt Mode", this buffer should not be modified + after calling the function and before the callback function has been called + or the SERCOM0_SPI_IsBusy() function returns false. + + txSize - Number of bytes to be transmitted. For 9 bit mode, 2 bytes make up + a count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has transmitted + the requested number of bytes. If configured for Interrupt mode, the request + was accepted successfully and will be processed in the interrupt. + + false - If pTransmitData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t txBuffer[4]; + size_t txSize = 4; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Write(&txBuffer, txSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + + Remarks: + None. + +*/ + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + + Summary: + Reads data on the SERCOM SERCOM0 SPI peripheral. + + Description: + This function reads "rxSize" number of bytes on SERCOM SERCOM0 SPI module. The + received data is stored in the buffer pointed by pReceiveData. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + receiving "rxSize" number of bytes. This indicates that the operation has + been completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + receive buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pReceiveData - Pointer to the buffer where the received data will be stored. + For 9 bit mode, data should be right aligned in the 16 bit memory location. + In "Interrupt Mode", this buffer should not be modified after calling the + function and before the callback function has been called or the + SERCOM0_SPI_IsBusy() function returns false. + + rxSize - Number of bytes to be received. For 9 bit mode, 2 bytes make up a + count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has received the + requested number of bytes. If configured for Interrupt mode, the request was + accepted successfully and will be processed in the interrupt. + + false - If pReceiveData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t rxBuffer[10]; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Read(&rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Parameters: + callBack - Pointer to the event handler function implemented by the + user . + + context - The value of parameter will be passed back to the application + unchanged, when the callBack function is called. It can + be used to identify any application specific data object that + identifies the instance of the client module (for example, + it may be a pointer to the client module's state structure). + + Returns: + None. + + Example: + + uint8_t txBuffer[10]; + uint8_t rxBuffer[10]; + size_t txSize = 10; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + SERCOM0_SPI_CallbackRegister(&APP_SPICallBack, (uintptr_t)NULL); + + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize )) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + void APP_SPICallBack(uintptr_t contextHandle) + { + Exchange was completed without error, do something else. + } + + + Remarks: + If the client does not want to be notified when the queued operation + has completed, it does not need to register a callback. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy (void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. This function returns true when the SPI PLIB software state machine is idle and + all the bytes are transmitted out on the bus (shift register is empty). + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. The module should + have been configured for interrupt mode operation in MHC. + + Parameters: + None. + + Returns: + true - Transfer is still in progress + false - Transfer is completed or no transfer is currently in progress. + + Example: + + The following code example demonstrates the use of the + SERCOM0_SPI_IsBusy() function. This example shows a blocking while + loop. The function can also be called periodically. + + uint8_t dataBuffer[20]; + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_Write(dataBuffer, 20); + + while (SERCOM0_SPI_IsBusy() == true) + { + Wait here till the transfer is done. + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_IsBusy (void); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsTransmitterBusy (void); + + Summary: + Returns hardware transfer status of the SPI transmit shift register + + Description: + This function returns the hardware status of the transmit shift register. + The status is returned true after all the bytes have been shifted out on the + SPI bus. This function should be used when using DMA with SPI PLIB to make + sure that all the bytes have been transmitted out on the bus. For SPI + transfers without DMA, the SERCOM0_SPI_IsBusy() API must be used. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. + + Parameters: + None. + + Returns: + true - Data is being shifted out on the SPI bus + false - All the data bytes have been shifted out on the SPI bus + + Example: + + + + + Remarks: + None. +*/ +bool SERCOM0_SPI_IsTransmitterBusy(void); + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_SERCOM0_SPI_MASTER_H */ \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h new file mode 100644 index 0000000..f358529 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h @@ -0,0 +1,304 @@ +/******************************************************************************* + SERCOM_SPI(SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_spi_master_common.h + + Summary + SERCOM_SPI PLIB Master Local Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_SPI_MASTER_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_SPI_MASTER_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Clock Phase + + Summary: + Identifies SPI Clock Phase Options + + Description: + This enumeration identifies possible SPI Clock Phase Options. + + Remarks: + None. +*/ + +typedef enum +{ + /* Input data is sampled on clock trailing edge and changed on + leading edge */ + SPI_CLOCK_PHASE_TRAILING_EDGE = SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE, + + /* Input data is sampled on clock leading edge and changed on + trailing edge */ + SPI_CLOCK_PHASE_LEADING_EDGE = SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE, + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_PHASE_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_PHASE; + +// ***************************************************************************** +/* SPI Clock Polarity + + Summary: + Identifies SPI Clock Polarity Options + + Description: + This enumeration identifies possible SPI Clock Polarity Options. + + Remarks: + None. +*/ + +typedef enum +{ + /* The inactive state value of clock is logic level zero */ + SPI_CLOCK_POLARITY_IDLE_LOW = SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW, + + /* The inactive state value of clock is logic level one */ + SPI_CLOCK_POLARITY_IDLE_HIGH = SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH, + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_POLARITY_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_POLARITY; + +// ***************************************************************************** +/* SPI Data Bits + + Summary: + Identifies SPI bits per transfer + + Description: + This enumeration identifies number of bits per SPI transfer. + + Remarks: + For 9 bit mode, data should be right aligned in the 16 bit + memory location. +*/ + +typedef enum +{ + /* 8 bits per transfer */ + SPI_DATA_BITS_8 = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT, + + /* 9 bits per transfer */ + SPI_DATA_BITS_9 = SERCOM_SPIM_CTRLB_CHSIZE_9_BIT, + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_DATA_BITS_INVALID = 0xFFFFFFFFU + +} SPI_DATA_BITS; + +// ***************************************************************************** +/* SPI Transfer Setup Parameters + + Summary: + Identifies the setup parameters which can be changed dynamically. + + Description + This structure identifies the possible setup parameters for SPI + which can be changed dynamically if needed. + + Remarks: + None. +*/ + +typedef struct +{ + /* Baud Rate or clock frequency */ + uint32_t clockFrequency; + + /* Clock Phase */ + SPI_CLOCK_PHASE clockPhase; + + /* Clock Polarity */ + SPI_CLOCK_POLARITY clockPolarity; + + /* Number of bits per transfer */ + SPI_DATA_BITS dataBits; + +} SPI_TRANSFER_SETUP; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI CallBack Function Pointer + + Summary: + Pointer to a SPI Call back function. + + Description: + This data type defines the required function signature for the + SPI event handling callback function. Application must register + a pointer to an event handling function whose function signature (parameter + and return value types) match the types specified by this function pointer + in order to receive event calls back from the PLIB. + + The parameters and return values are described here and a partial example + implementation is provided. + + Parameters: + context - Value identifying the context of the application that + registered the event handling function + + Returns: + None. + + Example: + + + SPI1_CallbackRegister(&APP_SPICallBack, NULL); + void APP_SPICallBack(uintptr_t contextHandle) + { + if( SPI_ERROR_NONE == SPI1_ErrorGet()) + { + Exchange was completed without error, do something else now. + } + } + + + Remarks: + The context parameter contains the a handle to the client context, + provided at the time the event handling function was registered using the + SPIx_CallbackRegister function. This context handle value is + passed back to the client as the "context" parameter. It can be any value + (such as a pointer to the client's data) necessary to identify the client + context or instance of the client that made the data exchange + request. + + The event handler function executes in the PLIB's interrupt context. It is + recommended of the application to not perform process intensive or blocking + operations with in this function. +*/ + +typedef void (*SERCOM_SPI_CALLBACK)(uintptr_t context); + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local: **** Local SPI Object**** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Object + + Summary: + Defines the data type for the data structures used for peripheral + operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + /* Pointer to the transmitter buffer */ + void * txBuffer; + + /* Pointer to the received buffer */ + void * rxBuffer; + + size_t txSize; + + size_t rxSize; + + size_t dummySize; + + /* Size of the receive processed exchange size */ + size_t rxCount; + + /* Size of the transmit processed exchange size */ + size_t txCount; + + /* Exchange busy status of the SPI */ + bool transferIsBusy; + + /* SPI Event handler */ + SERCOM_SPI_CALLBACK callback; + + /* Context */ + uintptr_t context; + + uint32_t status; + +} SPI_OBJECT; + +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif + +#endif //PLIB_SERCOM_SPI_MASTER_COMMON_H \ No newline at end of file diff --git a/firmware/src/config/mcal/peripheral/systick/plib_systick.c b/firmware/src/config/mcal/peripheral/systick/plib_systick.c new file mode 100644 index 0000000..1c99f7f --- /dev/null +++ b/firmware/src/config/mcal/peripheral/systick/plib_systick.c @@ -0,0 +1,212 @@ +/******************************************************************************* + SysTick Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_systick.c + + Summary: + Systick Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "interrupts.h" +#include "plib_systick.h" + +static SYSTICK_OBJECT systick; +uint8_t systick_1_5_s_flag = SYSTICK_1_5_S_UNINITIALIZE; + +void SYSTICK_TimerInitialize ( void ) +{ + SysTick->CTRL = 0U; + SysTick->VAL = 0U; + SysTick->LOAD = 0x1D4C0U - 1U; + SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + systick.tickCounter = 0U; + systick.callback = NULL; +} + +void SYSTICK_TimerRestart ( void ) +{ + SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); + SysTick->VAL = 0U; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +void SYSTICK_TimerStart ( void ) +{ + SysTick->VAL = 0U; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +void SYSTICK_TimerStop ( void ) +{ + SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); +} + +void SYSTICK_TimerPeriodSet ( uint32_t period ) +{ + SysTick->LOAD = period - 1U; +} + +uint32_t SYSTICK_TimerPeriodGet ( void ) +{ + return(SysTick->LOAD); +} + +uint32_t SYSTICK_TimerCounterGet ( void ) +{ + return (SysTick->VAL); +} + +uint32_t SYSTICK_TimerFrequencyGet ( void ) +{ + return (SYSTICK_FREQ); +} + +void SYSTICK_DelayMs ( uint32_t delay_ms) +{ + uint32_t elapsedCount=0U, delayCount; + uint32_t deltaCount, oldCount, newCount, period; + + period = SysTick->LOAD + 1U; + + /* Calculate the count for the given delay */ + delayCount=(SYSTICK_FREQ/1000U)*delay_ms; + + if((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) == SysTick_CTRL_ENABLE_Msk) + { + oldCount = SysTick->VAL; + + while (elapsedCount < delayCount) + { + newCount = SysTick->VAL; + deltaCount = oldCount - newCount; + + if(newCount > oldCount) + { + deltaCount = period - newCount + oldCount; + } + + oldCount = newCount; + elapsedCount = elapsedCount + deltaCount; + } + } +} + +void SYSTICK_DelayUs ( uint32_t delay_us) +{ + uint32_t elapsedCount=0U, delayCount; + uint32_t deltaCount, oldCount, newCount, period; + + period = SysTick->LOAD + 1U; + + /* Calculate the count for the given delay */ + delayCount=(SYSTICK_FREQ/1000000U)*delay_us; + + if((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) == SysTick_CTRL_ENABLE_Msk) + { + oldCount = SysTick->VAL; + + while (elapsedCount < delayCount) + { + newCount = SysTick->VAL; + deltaCount = oldCount - newCount; + + if(newCount > oldCount) + { + deltaCount = period - newCount + oldCount; + } + + oldCount = newCount; + elapsedCount = elapsedCount + deltaCount; + } + } +} + + + +uint32_t SYSTICK_GetTickCounter(void) +{ + return systick.tickCounter; +} + +void SYSTICK_StartTimeOut (SYSTICK_TIMEOUT* timeout, uint32_t delay_ms) +{ + timeout->start = SYSTICK_GetTickCounter(); + timeout->count = (delay_ms*1000U)/SYSTICK_INTERRUPT_PERIOD_IN_US; +} + +void SYSTICK_ResetTimeOut (SYSTICK_TIMEOUT* timeout) +{ + timeout->start = SYSTICK_GetTickCounter(); +} + +bool SYSTICK_IsTimeoutReached (SYSTICK_TIMEOUT* timeout) +{ + bool valTimeout = true; + if ((SYSTICK_GetTickCounter() - timeout->start) < timeout->count) + { + valTimeout = false; + } + + return valTimeout; + +} +void SYSTICK_TimerCallbackSet ( SYSTICK_CALLBACK callback, uintptr_t context ) +{ + systick.callback = callback; + systick.context = context; +} + +uint8_t SYSTICK_Get1_5_S_Flag(void) +{ + return systick_1_5_s_flag; +} + +void SysTick_Handler(void) +{ + /* Reading control register clears the count flag */ + uint32_t sysCtrl = SysTick->CTRL; + systick.tickCounter++; + + if(systick.tickCounter > SYSTICK_1_5_S_TIMEOUT){ + systick_1_5_s_flag = SYSTICK_1_5_S_INITIALIZE; + } + + if(systick.callback != NULL) + { + systick.callback(systick.context); + } + (void)sysCtrl; +} diff --git a/firmware/src/config/mcal/peripheral/systick/plib_systick.h b/firmware/src/config/mcal/peripheral/systick/plib_systick.h new file mode 100644 index 0000000..cfd2ba7 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/systick/plib_systick.h @@ -0,0 +1,105 @@ +/******************************************************************************* + Interface definition of SYSTICK PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_systick.h + + Summary: + Interface definition of the System Timer Plib (SYSTICK). + + Description: + This file defines the interface for the SYSTICK Plib. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SYSTICK_H // Guards against multiple inclusion +#define PLIB_SYSTICK_H + +#include +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + +#define SYSTICK_FREQ 120000000U + +#define SYSTICK_INTERRUPT_PERIOD_IN_US (1000U) + +#define SYSTICK_1_5_S_UNINITIALIZE (0) +#define SYSTICK_1_5_S_INITIALIZE (1) +#define SYSTICK_1_5_S_TIMEOUT (1500) + +typedef void (*SYSTICK_CALLBACK)(uintptr_t context); + + +typedef struct +{ + uint32_t start; + uint32_t count; +}SYSTICK_TIMEOUT; + +typedef struct +{ + SYSTICK_CALLBACK callback; + uintptr_t context; + volatile uint32_t tickCounter; +} SYSTICK_OBJECT ; + +/***************************** SYSTICK API *******************************/ +void SYSTICK_TimerInitialize ( void ); +void SYSTICK_TimerRestart ( void ); +void SYSTICK_TimerStart ( void ); +void SYSTICK_TimerStop ( void ); +void SYSTICK_TimerPeriodSet ( uint32_t period ); +uint32_t SYSTICK_TimerPeriodGet ( void ); +uint32_t SYSTICK_TimerCounterGet ( void ); +uint32_t SYSTICK_TimerFrequencyGet ( void ); +void SYSTICK_DelayMs ( uint32_t delay_ms ); +void SYSTICK_DelayUs ( uint32_t delay_us ); + +void SYSTICK_TimerCallbackSet ( SYSTICK_CALLBACK callback, uintptr_t context ); +uint32_t SYSTICK_GetTickCounter(void); +void SYSTICK_StartTimeOut (SYSTICK_TIMEOUT* timeout, uint32_t delay_ms); +void SYSTICK_ResetTimeOut (SYSTICK_TIMEOUT* timeout); +bool SYSTICK_IsTimeoutReached (SYSTICK_TIMEOUT* timeout); +uint8_t SYSTICK_Get1_5_S_Flag(void); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif diff --git a/firmware/src/config/mcal/peripheral/tc/plib_tc0.c b/firmware/src/config/mcal/peripheral/tc/plib_tc0.c new file mode 100644 index 0000000..6af71ef --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tc/plib_tc0.c @@ -0,0 +1,214 @@ +/******************************************************************************* + Timer/Counter(TC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_tc0.c + + Summary + TC0 PLIB Implementation File. + + Description + This file defines the interface to the TC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "interrupts.h" +#include "plib_tc0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +static TC_TIMER_CALLBACK_OBJ TC0_CallbackObject; + +// ***************************************************************************** +// ***************************************************************************** +// Section: TC0 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize the TC module in Timer mode */ +void TC0_TimerInitialize( void ) +{ + /* Reset TC */ + TC0_REGS->COUNT16.TC_CTRLA = TC_CTRLA_SWRST_Msk; + + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_SWRST_Msk) == TC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Write Synchronization */ + } + + /* Configure counter mode & prescaler */ + TC0_REGS->COUNT16.TC_CTRLA = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV1 | TC_CTRLA_PRESCSYNC_PRESC ; + + /* Configure in Match Frequency Mode */ + TC0_REGS->COUNT16.TC_WAVE = (uint8_t)TC_WAVE_WAVEGEN_MPWM; + + /* Configure timer period */ + TC0_REGS->COUNT16.TC_CC[0U] = 80U; + + /* Clear all interrupt flags */ + TC0_REGS->COUNT16.TC_INTFLAG = (uint8_t)TC_INTFLAG_Msk; + + TC0_CallbackObject.callback = NULL; + /* Enable interrupt*/ + TC0_REGS->COUNT16.TC_INTENSET = (uint8_t)(TC_INTENSET_OVF_Msk); + + + while((TC0_REGS->COUNT16.TC_SYNCBUSY) != 0U) + { + /* Wait for Write Synchronization */ + } +} + +/* Enable the TC counter */ +void TC0_TimerStart( void ) +{ + TC0_REGS->COUNT16.TC_CTRLA |= TC_CTRLA_ENABLE_Msk; + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_ENABLE_Msk) == TC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Write Synchronization */ + } +} + +/* Disable the TC counter */ +void TC0_TimerStop( void ) +{ + TC0_REGS->COUNT16.TC_CTRLA &= ~TC_CTRLA_ENABLE_Msk; + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_ENABLE_Msk) == TC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Write Synchronization */ + } +} + +uint32_t TC0_TimerFrequencyGet( void ) +{ + return (uint32_t)(1000000U); +} + +void TC0_TimerCommandSet(TC_COMMAND command) +{ + TC0_REGS->COUNT16.TC_CTRLBSET = (uint8_t)((uint32_t)command << TC_CTRLBSET_CMD_Pos); + while((TC0_REGS->COUNT16.TC_SYNCBUSY) != 0U) + { + /* Wait for Write Synchronization */ + } +} + +/* Get the current timer counter value */ +uint16_t TC0_Timer16bitCounterGet( void ) +{ + /* Write command to force COUNT register read synchronization */ + TC0_REGS->COUNT16.TC_CTRLBSET |= (uint8_t)TC_CTRLBSET_CMD_READSYNC; + + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_CTRLB_Msk) == TC_SYNCBUSY_CTRLB_Msk) + { + /* Wait for Write Synchronization */ + } + + while((TC0_REGS->COUNT16.TC_CTRLBSET & TC_CTRLBSET_CMD_Msk) != 0U) + { + /* Wait for CMD to become zero */ + } + + /* Read current count value */ + return (uint16_t)TC0_REGS->COUNT16.TC_COUNT; +} + +/* Configure timer counter value */ +void TC0_Timer16bitCounterSet( uint16_t count ) +{ + TC0_REGS->COUNT16.TC_COUNT = count; + + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_COUNT_Msk) == TC_SYNCBUSY_COUNT_Msk) + { + /* Wait for Write Synchronization */ + } +} + +/* Configure timer period */ +void TC0_Timer16bitPeriodSet( uint16_t period ) +{ + TC0_REGS->COUNT16.TC_CC[0] = period; + while((TC0_REGS->COUNT16.TC_SYNCBUSY & TC_SYNCBUSY_CC0_Msk) == TC_SYNCBUSY_CC0_Msk) + { + /* Wait for Write Synchronization */ + } +} + +/* Read the timer period value */ +uint16_t TC0_Timer16bitPeriodGet( void ) +{ + return (uint16_t)TC0_REGS->COUNT16.TC_CC[0]; +} + + + +/* Register callback function */ +void TC0_TimerCallbackRegister( TC_TIMER_CALLBACK callback, uintptr_t context ) +{ + TC0_CallbackObject.callback = callback; + + TC0_CallbackObject.context = context; +} + +/* Timer Interrupt handler */ +void TC0_TimerInterruptHandler( void ) +{ + if (TC0_REGS->COUNT16.TC_INTENSET != 0U) + { + TC_TIMER_STATUS status; + status = (TC_TIMER_STATUS) TC0_REGS->COUNT16.TC_INTFLAG; + /* Clear interrupt flags */ + TC0_REGS->COUNT16.TC_INTFLAG = (uint8_t)TC_INTFLAG_Msk; + if((status != TC_TIMER_STATUS_NONE) && (TC0_CallbackObject.callback != NULL)) + { + TC0_CallbackObject.callback(status, TC0_CallbackObject.context); + } + } +} + diff --git a/firmware/src/config/mcal/peripheral/tc/plib_tc0.h b/firmware/src/config/mcal/peripheral/tc/plib_tc0.h new file mode 100644 index 0000000..d441034 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tc/plib_tc0.h @@ -0,0 +1,124 @@ +/******************************************************************************* + Timer/Counter(TC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_tc0.h + + Summary + TC0 PLIB Header File. + + Description + This file defines the interface to the TC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_TC0_H // Guards against multiple inclusion +#define PLIB_TC0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_tc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +// ***************************************************************************** + +void TC0_TimerInitialize( void ); + +void TC0_TimerStart( void ); + +void TC0_TimerStop( void ); + +uint32_t TC0_TimerFrequencyGet( void ); + + +void TC0_Timer16bitPeriodSet( uint16_t period ); + +uint16_t TC0_Timer16bitPeriodGet( void ); + +uint16_t TC0_Timer16bitCounterGet( void ); + +void TC0_Timer16bitCounterSet( uint16_t count ); + + + + +void TC0_TimerCallbackRegister( TC_TIMER_CALLBACK callback, uintptr_t context ); + + +void TC0_TimerCommandSet(TC_COMMAND command); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_TC0_H */ diff --git a/firmware/src/config/mcal/peripheral/tc/plib_tc_common.h b/firmware/src/config/mcal/peripheral/tc/plib_tc_common.h new file mode 100644 index 0000000..fb7784c --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tc/plib_tc_common.h @@ -0,0 +1,193 @@ +/******************************************************************************* + Timer/Counter(TC) Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_tc_common.h + + Summary + TC peripheral library interface. + + Description + This file defines the interface to the TC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_TC_COMMON_H // Guards against multiple inclusion +#define PLIB_TC_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Convenience macros for TC capture status */ +// ***************************************************************************** + +#define TC_CAPTURE_STATUS_NONE 0U + +/* Capture status overflow */ +#define TC_CAPTURE_STATUS_OVERFLOW TC_INTFLAG_OVF_Msk + +/* Capture status error */ +#define TC_CAPTURE_STATUS_ERROR TC_INTFLAG_ERR_Msk + +/* Capture status ready for channel 0 */ +#define TC_CAPTURE_STATUS_CAPTURE0_READY TC_INTFLAG_MC0_Msk + +/* Capture status ready for channel 1 */ +#define TC_CAPTURE_STATUS_CAPTURE1_READY TC_INTFLAG_MC1_Msk + +#define TC_CAPTURE_STATUS_MSK (TC_CAPTURE_STATUS_OVERFLOW | TC_CAPTURE_STATUS_ERROR | TC_CAPTURE_STATUS_CAPTURE0_READY | TC_CAPTURE_STATUS_CAPTURE1_READY) + +/* Invalid compare status */ +#define TC_CAPTURE_STATUS_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +/* Convenience macros for TC compare status */ +// ***************************************************************************** + +#define TC_COMPARE_STATUS_NONE 0U +/* overflow */ +#define TC_COMPARE_STATUS_OVERFLOW TC_INTFLAG_OVF_Msk +/* match compare 0 */ +#define TC_COMPARE_STATUS_MATCH0 TC_INTFLAG_MC0_Msk +/* match compare 1 */ +#define TC_COMPARE_STATUS_MATCH1 TC_INTFLAG_MC1_Msk + +#define TC_COMPARE_STATUS_MSK (TC_COMPARE_STATUS_OVERFLOW | TC_COMPARE_STATUS_MATCH0 | TC_COMPARE_STATUS_MATCH1) + +/* Invalid capture status */ +#define TC_COMPARE_STATUS_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +/* Convenience macros for TC timer status */ +// ***************************************************************************** + +#define TC_TIMER_STATUS_NONE 0U +/* overflow */ +#define TC_TIMER_STATUS_OVERFLOW TC_INTFLAG_OVF_Msk + +/* match compare 1 */ +#define TC_TIMER_STATUS_MATCH1 TC_INTFLAG_MC1_Msk + +#define TC_TIMER_STATUS_MSK (TC_TIMER_STATUS_OVERFLOW | TC_TIMER_STATUS_MATCH1) + +/* Invalid timer status */ +#define TC_TIMER_STATUS_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + +typedef uint32_t TC_CAPTURE_STATUS; + +typedef uint32_t TC_COMPARE_STATUS; + +typedef uint32_t TC_TIMER_STATUS; + +typedef enum +{ + TC_COMMAND_NONE, + TC_COMMAND_START_RETRIGGER, + TC_COMMAND_STOP, + TC_COMMAND_FORCE_UPDATE, + TC_COMMAND_READ_SYNC +}TC_COMMAND; + +// ***************************************************************************** + +typedef void (*TC_TIMER_CALLBACK) (TC_TIMER_STATUS status, uintptr_t context); + +typedef void (*TC_COMPARE_CALLBACK) (TC_COMPARE_STATUS status, uintptr_t context); + +typedef void (*TC_CAPTURE_CALLBACK) (TC_CAPTURE_STATUS status, uintptr_t context); + +// ***************************************************************************** +typedef struct +{ + TC_TIMER_CALLBACK callback; + + uintptr_t context; + +} TC_TIMER_CALLBACK_OBJ; + +typedef struct +{ + TC_COMPARE_CALLBACK callback; + uintptr_t context; +}TC_COMPARE_CALLBACK_OBJ; + +typedef struct +{ + TC_CAPTURE_CALLBACK callback; + uintptr_t context; +}TC_CAPTURE_CALLBACK_OBJ; + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_TC_COMMON_H */ diff --git a/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.c b/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.c new file mode 100644 index 0000000..6e97a35 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.c @@ -0,0 +1,236 @@ +/******************************************************************************* + TCC Peripheral Library Interface Source File + + Company + Microchip Technology Inc. + + File Name + plib_tcc0.c + + Summary + TCC0 peripheral library source file. + + Description + This file implements the interface to the TCC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* This section lists the other files that are included in this file. +*/ +#include "interrupts.h" +#include "plib_tcc0.h" + + +/* Object to hold callback function and context */ +static TCC_CALLBACK_OBJECT TCC0_CallbackObj; + +/* Initialize TCC module */ +void TCC0_PWMInitialize(void) +{ + /* Reset TCC */ + TCC0_REGS->TCC_CTRLA = TCC_CTRLA_SWRST_Msk; + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_SWRST_Msk) != 0U) + { + /* Wait for sync */ + } + /* Clock prescaler */ + TCC0_REGS->TCC_CTRLA = TCC_CTRLA_PRESCALER_DIV8 ; + TCC0_REGS->TCC_WEXCTRL = TCC_WEXCTRL_OTMX(2UL); + /* Dead time configurations */ + TCC0_REGS->TCC_WEXCTRL |= TCC_WEXCTRL_DTIEN1_Msk | TCC_WEXCTRL_DTIEN2_Msk | TCC_WEXCTRL_DTIEN3_Msk + | TCC_WEXCTRL_DTLS(64UL) | TCC_WEXCTRL_DTHS(64UL); + + TCC0_REGS->TCC_WAVE = TCC_WAVE_WAVEGEN_NPWM; + + /* Configure duty cycle values */ + TCC0_REGS->TCC_CC[0] = 0U; + TCC0_REGS->TCC_CC[1] = 0U; + TCC0_REGS->TCC_CC[2] = 0U; + TCC0_REGS->TCC_CC[3] = 0U; + TCC0_REGS->TCC_CC[4] = 0U; + TCC0_REGS->TCC_CC[5] = 0U; + TCC0_REGS->TCC_PER = 8000U; + + + TCC0_REGS->TCC_INTENSET = TCC_INTENSET_MC0_Msk + | TCC_INTENSET_OVF_Msk; + + while (TCC0_REGS->TCC_SYNCBUSY != 0U) + { + /* Wait for sync */ + } +} + + +/* Start the PWM generation */ +void TCC0_PWMStart(void) +{ + TCC0_REGS->TCC_CTRLA |= TCC_CTRLA_ENABLE_Msk; + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_ENABLE_Msk) != 0U) + { + /* Wait for sync */ + } +} + +/* Stop the PWM generation */ +void TCC0_PWMStop (void) +{ + TCC0_REGS->TCC_CTRLA &= ~TCC_CTRLA_ENABLE_Msk; + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_ENABLE_Msk) != 0U) + { + /* Wait for sync */ + } +} + +/* Configure PWM period */ +bool TCC0_PWM24bitPeriodSet (uint32_t period) +{ + bool status = false; + if ((TCC0_REGS->TCC_STATUS & (TCC_STATUS_PERBUFV_Msk)) == 0U) + { + TCC0_REGS->TCC_PERBUF = period & 0xFFFFFFU; + status = true; + } + return status; +} + + +/* Read TCC period */ +uint32_t TCC0_PWM24bitPeriodGet (void) +{ + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_PER_Msk) != 0U) + { + /* Wait for sync */ + } + return (TCC0_REGS->TCC_PER & 0xFFFFFFU); +} + +/* Configure dead time */ +void TCC0_PWMDeadTimeSet (uint8_t deadtime_high, uint8_t deadtime_low) +{ + TCC0_REGS->TCC_WEXCTRL &= ~(TCC_WEXCTRL_DTHS_Msk | TCC_WEXCTRL_DTLS_Msk); + TCC0_REGS->TCC_WEXCTRL |= TCC_WEXCTRL_DTHS((uint32_t)deadtime_high) | TCC_WEXCTRL_DTLS((uint32_t)deadtime_low); +} + +bool TCC0_PWMPatternSet(uint8_t pattern_enable, uint8_t pattern_output) +{ + bool status = false; + if ((TCC0_REGS->TCC_STATUS & (TCC_STATUS_PATTBUFV_Msk)) == 0U) + { + TCC0_REGS->TCC_PATTBUF = (uint16_t)(pattern_enable | ((uint32_t)pattern_output << 8U)); + status = true; + } + return status; +} + + +/* Set the counter*/ +void TCC0_PWM24bitCounterSet (uint32_t count) +{ + TCC0_REGS->TCC_COUNT = count & 0xFFFFFFU; + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_COUNT_Msk) != 0U) + { + /* Wait for sync */ + } +} + +/* Enable forced synchronous update */ +void TCC0_PWMForceUpdate(void) +{ + TCC0_REGS->TCC_CTRLBSET |= (uint8_t)TCC_CTRLBCLR_CMD_UPDATE; + while ((TCC0_REGS->TCC_SYNCBUSY & TCC_SYNCBUSY_CTRLB_Msk) != 0U) + { + /* Wait for sync */ + } +} + +/* Enable the period interrupt - overflow or underflow interrupt */ +void TCC0_PWMPeriodInterruptEnable(void) +{ + TCC0_REGS->TCC_INTENSET = TCC_INTENSET_OVF_Msk; +} + +/* Disable the period interrupt - overflow or underflow interrupt */ +void TCC0_PWMPeriodInterruptDisable(void) +{ + TCC0_REGS->TCC_INTENCLR = TCC_INTENCLR_OVF_Msk; +} + + /* Register callback function */ +void TCC0_PWMCallbackRegister(TCC_CALLBACK callback, uintptr_t context) +{ + TCC0_CallbackObj.callback_fn = callback; + TCC0_CallbackObj.context = context; +} + +/* Interrupt Handler */ +void TCC0_OTHER_InterruptHandler(void) +{ + uint32_t status; + status = (TCC0_REGS->TCC_INTFLAG & 0xFFFFU); + /* Clear interrupt flags */ + TCC0_REGS->TCC_INTFLAG = 0xFFFFU; + (void)TCC0_REGS->TCC_INTFLAG; + if (TCC0_CallbackObj.callback_fn != NULL) + { + TCC0_CallbackObj.callback_fn(status, TCC0_CallbackObj.context); + } + +} + +/* Interrupt Handler */ +void TCC0_MC0_InterruptHandler(void) +{ + uint32_t status; + status = TCC_INTFLAG_MC0_Msk; + /* Clear interrupt flags */ + TCC0_REGS->TCC_INTFLAG = TCC_INTFLAG_MC0_Msk; + (void)TCC0_REGS->TCC_INTFLAG; + if (TCC0_CallbackObj.callback_fn != NULL) + { + TCC0_CallbackObj.callback_fn(status, TCC0_CallbackObj.context); + } + +} + + + + + +/** + End of File +*/ diff --git a/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.h b/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.h new file mode 100644 index 0000000..db7cce8 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tcc/plib_tcc0.h @@ -0,0 +1,170 @@ +/******************************************************************************* + Data Type definition of Timer/Counter(TCC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_tcc0.h + + Summary: + Data Type definition of the TCC Peripheral Interface Plib. + + Description: + This file defines the Data Types for the TCC Plib. + + Remarks: + None. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_TCC0_H +#define PLIB_TCC0_H + +#include "device.h" +#include "plib_tcc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +/* Total number of TCC channels in a module */ +#define TCC0_NUM_CHANNELS (6U) + +/* TCC Channel numbers + + Summary: + Identifies channel number within TCC module + + Description: + This enumeration identifies TCC channel number. + + Remarks: + None. +*/ +typedef enum +{ + TCC0_CHANNEL0, + TCC0_CHANNEL1, + TCC0_CHANNEL2, + TCC0_CHANNEL3, + TCC0_CHANNEL4, + TCC0_CHANNEL5, +}TCC0_CHANNEL_NUM; + +// ***************************************************************************** + +/* TCC Channel interrupt status + + Summary: + Identifies TCC PWM interrupt status flags + + Description: + This enumeration identifies TCC PWM interrupt status falgs + + Remarks: + None. +*/ +typedef enum +{ + TCC0_PWM_STATUS_OVF = TCC_INTFLAG_OVF_Msk, + TCC0_PWM_STATUS_FAULT_0 = TCC_INTFLAG_FAULT0_Msk, + TCC0_PWM_STATUS_FAULT_1 = TCC_INTFLAG_FAULT1_Msk, + TCC0_PWM_STATUS_MC_0 = TCC_INTFLAG_MC0_Msk, + TCC0_PWM_STATUS_MC_1 = TCC_INTFLAG_MC1_Msk, + TCC0_PWM_STATUS_MC_2 = TCC_INTFLAG_MC2_Msk, + TCC0_PWM_STATUS_MC_3 = TCC_INTFLAG_MC3_Msk, + TCC0_PWM_STATUS_MC_4 = TCC_INTFLAG_MC4_Msk, + TCC0_PWM_STATUS_MC_5 = TCC_INTFLAG_MC5_Msk, +}TCC0_PWM_STATUS; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +// ***************************************************************************** +void TCC0_PWMInitialize(void); + +void TCC0_PWMStart(void); + +void TCC0_PWMStop(void); + +void TCC0_PWMDeadTimeSet(uint8_t deadtime_high, uint8_t deadtime_low); + +void TCC0_PWMForceUpdate(void); + +bool TCC0_PWMPatternSet(uint8_t pattern_enable, uint8_t pattern_output); + + +void TCC0_PWMPeriodInterruptEnable(void); + +void TCC0_PWMPeriodInterruptDisable(void); + +void TCC0_PWMCallbackRegister(TCC_CALLBACK callback, uintptr_t context); + +bool TCC0_PWM24bitPeriodSet(uint32_t period); + +uint32_t TCC0_PWM24bitPeriodGet(void); + +void TCC0_PWM24bitCounterSet(uint32_t count); + +__STATIC_INLINE bool TCC0_PWM24bitDutySet(TCC0_CHANNEL_NUM channel, uint32_t duty) +{ + bool status = false; + if ((TCC0_REGS->TCC_STATUS & (1UL << (TCC_STATUS_CCBUFV0_Pos + (uint32_t)channel))) == 0U) + { + TCC0_REGS->TCC_CCBUF[channel] = duty & 0xFFFFFFU; + status = true; + } + return status; +} + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } +#endif +// DOM-IGNORE-END + +#endif /* PLIB_TCC0_H */ diff --git a/firmware/src/config/mcal/peripheral/tcc/plib_tcc_common.h b/firmware/src/config/mcal/peripheral/tcc/plib_tcc_common.h new file mode 100644 index 0000000..378f5c4 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/tcc/plib_tcc_common.h @@ -0,0 +1,107 @@ +/******************************************************************************* + Timer/Counter for Control(TCC) Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_tcc_common.h + + Summary + TCC peripheral library interface. + + Description + This file defines the interface to the TCC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_TCC_COMMON_H // Guards against multiple inclusion +#define PLIB_TCC_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ +// ***************************************************************************** + +typedef void (*TCC_CALLBACK)( uint32_t status, uintptr_t context ); +// ***************************************************************************** + +typedef struct +{ + TCC_CALLBACK callback_fn; + uintptr_t context; +}TCC_CALLBACK_OBJECT; + +typedef enum +{ + TCC_COMMAND_NONE, + TCC_COMMAND_START_RETRIGGER, + TCC_COMMAND_STOP, + TCC_COMMAND_FORCE_UPDATE, + TCC_COMMAND_READ_SYNC +}TCC_COMMAND; + + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_TCC_COMMON_H */ diff --git a/firmware/src/config/mcal/peripheral/wdt/plib_wdt.c b/firmware/src/config/mcal/peripheral/wdt/plib_wdt.c new file mode 100644 index 0000000..32eaa4d --- /dev/null +++ b/firmware/src/config/mcal/peripheral/wdt/plib_wdt.c @@ -0,0 +1,215 @@ +/******************************************************************************* + Watchdog Timer PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_wdt.c + + Summary: + Interface definition of WDT PLIB. + + Description: + This file defines the interface for the WDT Plib. + It allows user to setup timeout duration and restart watch dog timer. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "interrupts.h" +#include "plib_wdt.h" + +static WDT_CALLBACK_OBJECT wdtCallbackObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: WDT Interface Implementations +// ***************************************************************************** +// ***************************************************************************** + +void WDT_Enable( void ) +{ + /* Checking if Always On Bit is Enabled */ + if((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ALWAYSON_Msk) != WDT_CTRLA_ALWAYSON_Msk) + { + /* Enable Watchdog Timer */ + WDT_REGS->WDT_CTRLA |= (uint8_t)WDT_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + } + + /* Enable early warning interrupt */ + WDT_REGS->WDT_INTENSET = (uint8_t)WDT_INTENSET_EW_Msk; +} + +/* This function is used to disable the Watchdog Timer */ +void WDT_Disable( void ) +{ + /* Wait for synchronization */ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + + /* Disable Watchdog Timer */ + WDT_REGS->WDT_CTRLA &= (uint8_t)(~WDT_CTRLA_ENABLE_Msk); + + /* Wait for synchronization */ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + + /* Disable Early Watchdog Interrupt */ + WDT_REGS->WDT_INTENCLR = (uint8_t)WDT_INTENCLR_EW_Msk; +} + +void WDT_EnableWindowMode( void ) +{ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + + /* Window mode can be changed only if peripheral is disabled or ALWAYS ON bit is set */ + if(((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ENABLE_Msk) == 0U) || ((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ALWAYSON_Msk) != 0U)) + { + /* Enable window mode */ + WDT_REGS->WDT_CTRLA |= (uint8_t)WDT_CTRLA_WEN_Msk; + } + + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } +} + +void WDT_DisableWindowMode( void ) +{ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + + /* Window mode can be changed only if peripheral is disabled or ALWAYS ON bit is set */ + if(((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ENABLE_Msk) == 0U) || ((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ALWAYSON_Msk) != 0U)) + { + /* Disable window mode */ + WDT_REGS->WDT_CTRLA &= (uint8_t)(~WDT_CTRLA_WEN_Msk); + } + + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } +} + +bool WDT_IsEnabled(void) +{ + return ((WDT_REGS->WDT_CTRLA & (WDT_CTRLA_ALWAYSON_Msk | WDT_CTRLA_ENABLE_Msk)) != 0U); +} + +bool WDT_IsAlwaysOn(void) +{ + return ((WDT_REGS->WDT_CTRLA & WDT_CTRLA_ALWAYSON_Msk) != 0U); +} + +bool WDT_IsWindowModeEnabled(void) +{ + return ((WDT_REGS->WDT_CTRLA & WDT_CTRLA_WEN_Msk) != 0U); +} + + +void WDT_TimeoutPeriodSet(uint8_t TimeoutPeriod) +{ + /* Set WDT timeout period */ + WDT_REGS->WDT_CONFIG = (WDT_REGS->WDT_CONFIG & (uint8_t)~WDT_CONFIG_PER_Msk) | (TimeoutPeriod & (uint8_t)WDT_CONFIG_PER_Msk); +} + +/* If application intends to stay in active mode after clearing WDT, then use WDT_Clear API to clear the WDT. This avoids CPU from waiting or stalling for Synchronization. + * If application intends to enter low power mode after clearing WDT, then use the WDT_ClearWithSync API to clear the WDT. + */ +void WDT_Clear( void ) +{ + if ((WDT_REGS->WDT_SYNCBUSY & WDT_SYNCBUSY_CLEAR_Msk) != WDT_SYNCBUSY_CLEAR_Msk) + { + /* Clear WDT and reset the WDT timer before the + timeout occurs */ + WDT_REGS->WDT_CLEAR = (uint8_t)WDT_CLEAR_CLEAR_KEY; + } +} + +/* This API must be used if application intends to enter low power mode after clearing WDT. + * It waits for write synchronization to complete as the device must not enter low power mode + * while write sync is in progress. + */ +void WDT_ClearWithSync( void ) +{ + /* Wait for synchronization */ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } + + /* Clear WDT and reset the WDT timer before the + timeout occurs */ + WDT_REGS->WDT_CLEAR = (uint8_t)WDT_CLEAR_CLEAR_KEY; + + /* Wait for synchronization */ + while(WDT_REGS->WDT_SYNCBUSY != 0U) + { + + } +} + +void WDT_CallbackRegister( WDT_CALLBACK callback, uintptr_t context) +{ + wdtCallbackObj.callback = callback; + + wdtCallbackObj.context = context; +} + +void WDT_InterruptHandler( void ) +{ + /* Clear Early Watchdog Interrupt */ + WDT_REGS->WDT_INTFLAG = (uint8_t)WDT_INTFLAG_EW_Msk; + + if( wdtCallbackObj.callback != NULL ) + { + wdtCallbackObj.callback(wdtCallbackObj.context); + } +} diff --git a/firmware/src/config/mcal/peripheral/wdt/plib_wdt.h b/firmware/src/config/mcal/peripheral/wdt/plib_wdt.h new file mode 100644 index 0000000..4e29749 --- /dev/null +++ b/firmware/src/config/mcal/peripheral/wdt/plib_wdt.h @@ -0,0 +1,117 @@ +/******************************************************************************* + Watch Dog Timer PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_wdt.h + + Summary: + Interface definition of WDT PLIB. + + Description: + This file defines the interface for the WDT Plib. + It allows user to setup timeout duration and restart watch dog timer. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_WDT_H // Guards against multiple inclusion +#define PLIB_WDT_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +typedef void (*WDT_CALLBACK)(uintptr_t context); + +typedef struct +{ + WDT_CALLBACK callback; + + uintptr_t context; + +} WDT_CALLBACK_OBJECT; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void WDT_Enable( void ); + +void WDT_Disable( void ); + +void WDT_EnableWindowMode( void ); + +void WDT_DisableWindowMode( void ); + +bool WDT_IsEnabled(void); + +bool WDT_IsAlwaysOn(void); + +bool WDT_IsWindowModeEnabled(void); + +void WDT_TimeoutPeriodSet(uint8_t TimeoutPeriod); + +void WDT_Clear( void ); + +void WDT_ClearWithSync( void ); + +void WDT_CallbackRegister( WDT_CALLBACK callback, uintptr_t context ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_WDT_H */ diff --git a/firmware/src/config/mcal/pin_configurations.csv b/firmware/src/config/mcal/pin_configurations.csv new file mode 100644 index 0000000..3b27c4c --- /dev/null +++ b/firmware/src/config/mcal/pin_configurations.csv @@ -0,0 +1,52 @@ +"Pin Number","Pin ID","Custom Name","Function","Mode", "Direction","Latch","Pull Up","Pull Down","Drive Strength" +1,PA00,SDA,SERCOM1_PAD0,Digital,High Impedance,n/a,No,No,NORMAL +2,PA01,SCL,SERCOM1_PAD1,Digital,High Impedance,n/a,No,No,NORMAL +3,PA02,INP,DAC_VOUT0,Analog,Out,Low,,,NORMAL +4,PA03,,Available,,,,,,NORMAL +5,PB04,AD_LDO,ADC1_AIN6,Analog,High Impedance,n/a,,,NORMAL +6,PB05,LD_OUT,ADC1_AIN7,Analog,High Impedance,n/a,,,NORMAL +9,PB06,Y1_SNS,ADC0_X24/Y24,Analog,High Impedance,n/a,,,NORMAL +10,PB07,Y2_SNS,ADC0_X25/Y25,Analog,High Impedance,n/a,,,NORMAL +11,PB08,Y3_SNS,ADC0_AIN2/X1/Y1,Analog,High Impedance,n/a,,,NORMAL +12,PB09,Y4_SNS,ADC0_AIN3/X2/Y2,Analog,High Impedance,n/a,,,NORMAL +13,PA04,Y5_SNS,ADC0_AIN4/X3/Y3/VREFB,Analog,High Impedance,n/a,,,NORMAL +14,PA05,,Available,,,,,,NORMAL +15,PA06,,Available,,,,,,NORMAL +16,PA07,,Available,,,,,,NORMAL +17,PA08,MOSI,SERCOM0_PAD0,Digital,High Impedance,n/a,No,No,NORMAL +18,PA09,CLK,SERCOM0_PAD1,Digital,High Impedance,n/a,No,No,NORMAL +19,PA10,Spi_Software_Trigger,GPIO,Digital,Out,High,,,NORMAL +20,PA11,MISO,SERCOM0_PAD3,Digital,High Impedance,n/a,No,No,NORMAL +23,PB10,BL_PWM,TCC0_WO4,Digital,High Impedance,n/a,No,No,NORMAL +24,PB11,,Available,,,,,,NORMAL +25,PB12,CAN_TXD,CAN1_TX,Digital,High Impedance,n/a,No,No,NORMAL +26,PB13,CAN_RXD,CAN1_RX,Digital,High Impedance,n/a,No,No,NORMAL +27,PB14,Gain1,GPIO,Digital,Out,Low,,,NORMAL +28,PB15,Gain0,GPIO,Digital,Out,Low,,,NORMAL +29,PA12,FAULT_OUT,EIC_EXTINT12,Digital,In,n/a,No,No,NORMAL +30,PA13,SDZ,GPIO,Digital,Out,Low,,,NORMAL +31,PA14,,Available,,,,,,NORMAL +32,PA15,,Available,,,,,,NORMAL +35,PA16,X1_SNS,ADC0_X10/Y10,Analog,High Impedance,n/a,,,NORMAL +36,PA17,X2_SNS,ADC0_X11/Y11,Analog,High Impedance,n/a,,,NORMAL +37,PA18,X3_SNS,ADC0_X12/Y12,Analog,High Impedance,n/a,,,NORMAL +38,PA19,X4_SNS,ADC0_X13/Y13,Analog,High Impedance,n/a,,,NORMAL +39,PB16,,Available,,,,,,NORMAL +40,PB17,,Available,,,,,,NORMAL +41,PA20,X5_SNS,ADC0_X14/Y14,Analog,High Impedance,n/a,,,NORMAL +42,PA21,CAP_RES1_SNS,ADC0_X15/Y15,Analog,High Impedance,n/a,,,NORMAL +43,PA22,CAP_CANCEL2_SNS,ADC0_X16/Y16,Analog,High Impedance,n/a,,,NORMAL +44,PA23,CAP_CANCEL1_SNS,ADC0_X17/Y17,Analog,High Impedance,n/a,,,NORMAL +45,PA24,,Available,,,,,,NORMAL +46,PA25,INP_0_EN,GPIO,Digital,Out,High,,,NORMAL +49,PB22,,Available,,,,,,NORMAL +50,PB23,,Available,,,,,,NORMAL +51,PA27,,Available,,,,,,NORMAL +57,PA30,,Available,,,,,,NORMAL +58,PA31,,Available,,,,,,NORMAL +59,PB30,SBC_INT,EIC_EXTINT14,Digital,In/Out,Low,,,NORMAL +60,PB31,INTB_PRSS,EIC_EXTINT15,Digital,In,n/a,No,No,NORMAL +61,PB00,CAP_TJP2_SNS,ADC0_AIN12/X30/Y30,Analog,In,n/a,,,NORMAL +62,PB01,CAP_TJP1_SNS,ADC0_AIN13/X31/Y31,Analog,High Impedance,n/a,,,NORMAL +63,PB02,Power_AD_Ctrl,GPIO,Digital,Out,Low,,,NORMAL +64,PB03,CAP_RES2_SNS,ADC0_AIN15/X21/Y21,Analog,In,n/a,,,NORMAL diff --git a/firmware/src/config/mcal/startup_xc32.c b/firmware/src/config/mcal/startup_xc32.c new file mode 100644 index 0000000..776a83e --- /dev/null +++ b/firmware/src/config/mcal/startup_xc32.c @@ -0,0 +1,179 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include "device.h" +#include "interrupts.h" + +/* + * The MPLAB X Simulator does not yet support simulation of programming the + * GPNVM bits yet. We can remove this once it supports the FRDY bit. + */ + /* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.1 deviated 1 time. Deviation record ID - H3_MISRAC_2012_R_21_1_DR_1 */ +#ifdef __MPLAB_DEBUGGER_SIMULATOR +#define __XC32_SKIP_STARTUP_GPNVM_WAIT +#endif +/* MISRAC 2012 deviation block end */ + +/* + * This startup code relies on features that are specific to the MPLAB XC32 + * toolchain. Do not use it with other toolchains. + */ +#ifndef __XC32 +#warning This startup code is intended for use with the MPLAB XC32 Compiler only. +#endif + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated 5 times. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 6 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ + +/* array initialization function */ +extern void __attribute__((long_call)) __libc_init_array(void); + +/* Optional application-provided functions */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_bootstrap(void); + +/* Reserved for use by the MPLAB XC32 Compiler */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_bootstrap(void); + +/* Linker defined variables */ +extern uint32_t __svectors; + +/* MISRAC 2012 deviation block end */ + + +extern int main(void); + +__STATIC_INLINE void CMCC_Configure(void) +{ + CMCC_REGS->CMCC_CTRL &= ~(CMCC_CTRL_CEN_Msk); + while((CMCC_REGS->CMCC_SR & CMCC_SR_CSTS_Msk) == CMCC_SR_CSTS_Msk) + { + /*Wait for the operation to complete*/ + } + CMCC_REGS->CMCC_CFG = CMCC_CFG_CSIZESW(2U)| CMCC_CFG_DCDIS_Msk; + CMCC_REGS->CMCC_CTRL = (CMCC_CTRL_CEN_Msk); +} + + +#if (__ARM_FP==14) || (__ARM_FP==4) + +/* Enable FPU */ +__STATIC_INLINE void FPU_Enable(void) +{ + uint32_t primask = __get_PRIMASK(); + __disable_irq(); + SCB->CPACR |= (((uint32_t)0xFU) << 20); + __DSB(); + __ISB(); + + if (primask == 0U) + { + __enable_irq(); + } +} +#endif /* (__ARM_FP==14) || (__ARM_FP==4) */ + + +/* Brief default application function used as a weak reference */ +extern void Dummy_App_Func(void); +void __attribute__((optimize("-O1"),long_call))Dummy_App_Func(void) +{ + /* Do nothing */ + return; +} + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void __attribute__((optimize("-O1"), section(".text.Reset_Handler"), long_call, noreturn)) Reset_Handler(void) +{ +#ifdef SCB_VTOR_TBLOFF_Msk + uint32_t *pSrc; +#endif + +#if defined (__REINIT_STACK_POINTER) + /* Initialize SP from linker-defined _stack symbol. */ + __asm__ volatile ("ldr sp, =_stack" : : : "sp"); + +#ifdef SCB_VTOR_TBLOFF_Msk + /* Buy stack for locals */ + __asm__ volatile ("sub sp, sp, #8" : : : "sp"); +#endif + __asm__ volatile ("add r7, sp, #0" : : : "r7"); +#endif + + /* Call the optional application-provided _on_reset() function. */ + _on_reset(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_reset(); + +#if (__ARM_FP==14) || (__ARM_FP==4) + /* Enable the FPU if the application is built with -mfloat-abi=softfp or -mfloat-abi=hard */ + FPU_Enable(); +#endif + + /* Configure CMCC */ + CMCC_Configure(); + + /* Initialize data after TCM is enabled. + * Data initialization from the XC32 .dinit template */ + __pic32c_data_initialization(); + + +# ifdef SCB_VTOR_TBLOFF_Msk + /* Set the vector-table base address in FLASH */ + pSrc = (uint32_t *) & __svectors; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); +# endif /* SCB_VTOR_TBLOFF_Msk */ + + /* Initialize the C library */ + __libc_init_array(); + + /* Call the optional application-provided _on_bootstrap() function. */ + _on_bootstrap(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_bootstrap(); + + /* Branch to application's main function */ + (void)main(); + +#if (defined(__DEBUG) || defined(__DEBUG_D)) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + + while (true) + { + /* Infinite loop */ + } +} diff --git a/firmware/src/config/mcal/stdio/xc32_monitor.c b/firmware/src/config/mcal/stdio/xc32_monitor.c new file mode 100644 index 0000000..97a5aea --- /dev/null +++ b/firmware/src/config/mcal/stdio/xc32_monitor.c @@ -0,0 +1,54 @@ +/******************************************************************************* + Debug Console Source file + + Company: + Microchip Technology Inc. + + File Name: + xc32_monitor.c + + Summary: + debug console Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +#include + +extern int read(int handle, void *buffer, unsigned int len); +extern int write(int handle, void * buffer, size_t count); + + +int read(int handle, void *buffer, unsigned int len) +{ + return -1; +} + +int write(int handle, void * buffer, size_t count) +{ + return -1; +} \ No newline at end of file diff --git a/firmware/src/config/mcal/toolchain_specifics.h b/firmware/src/config/mcal/toolchain_specifics.h new file mode 100644 index 0000000..2359136 --- /dev/null +++ b/firmware/src/config/mcal/toolchain_specifics.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef TOOLCHAIN_SPECIFICS_H +#define TOOLCHAIN_SPECIFICS_H + +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +#pragma GCC diagnostic push +#ifndef __cplusplus + #pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#include "cmsis_compiler.h" +#pragma GCC diagnostic pop + +#include + +#define NO_INIT __attribute__((section(".no_init"))) +#define SECTION(a) __attribute__((__section__(a))) + +#define CACHE_LINE_SIZE (16u) +#define CACHE_ALIGN __ALIGNED(CACHE_LINE_SIZE) + +#define CACHE_ALIGNED_SIZE_GET(size) (size + ((size % CACHE_LINE_SIZE)? (CACHE_LINE_SIZE - (size % CACHE_LINE_SIZE)) : 0)) + +#ifndef FORMAT_ATTRIBUTE + #define FORMAT_ATTRIBUTE(archetype, string_index, first_to_check) __attribute__ ((format (archetype, string_index, first_to_check))) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // end of header + diff --git a/firmware/src/config/mcal/touch/lib.7z b/firmware/src/config/mcal/touch/lib.7z new file mode 100644 index 0000000..f4738b5 Binary files /dev/null and b/firmware/src/config/mcal/touch/lib.7z differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a b/firmware/src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a new file mode 100644 index 0000000..657e847 Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_acq_same51_0x000f.X.a differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a b/firmware/src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a new file mode 100644 index 0000000..6f1469f Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_freq_hop_cm4_0x0006.X.a differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a b/firmware/src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a new file mode 100644 index 0000000..392e0a9 Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_scroller_cm4_0x000b.X.a differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a b/firmware/src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a new file mode 100644 index 0000000..1bd6542 Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_surface_cs_cm4_0x0021.X.a differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_surface_gestures_cm4_0x0023.X.a b/firmware/src/config/mcal/touch/lib/qtm_surface_gestures_cm4_0x0023.X.a new file mode 100644 index 0000000..1733ca8 Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_surface_gestures_cm4_0x0023.X.a differ diff --git a/firmware/src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a b/firmware/src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a new file mode 100644 index 0000000..39d3bdb Binary files /dev/null and b/firmware/src/config/mcal/touch/lib/qtm_touch_key_cm4_0x0002.X.a differ diff --git a/firmware/src/config/mcal/touch/qtm_acq_same51_0x000f_api.h b/firmware/src/config/mcal/touch/qtm_acq_same51_0x000f_api.h new file mode 100644 index 0000000..1b08c71 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_acq_same51_0x000f_api.h @@ -0,0 +1,66 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_acq_same51_0x000f_api.h + + Summary: + QTouch Modular Library + + Description: + API for Acquisition module - SAME51/PTC + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/*============================================================================ +Filename : qtm_acq_same51_0x000f_api.h +Project : QTouch Modular Library +Purpose : API for Acquisition module - SAME51/PTC +------------------------------------------------------------------------------ +Copyright (c) Microchip Inc. All rights reserved. +------------------------------------------------------------------------------ +============================================================================*/ + +#ifndef TOUCH_API_SAME51_ACQ_MODULE_H +#define TOUCH_API_SAME51_ACQ_MODULE_H + +/* Include base API file */ +#include "qtm_acq_same54_0x000f_api.h" + +/* Definition of node config structure based on base API file */ +#define qtm_acq_same51_node_config_t qtm_acq_same54_node_config_t + +/* Definitions of derived API functions based on base API file */ +#define qtm_same51_acq_module_get_id qtm_same54_acq_module_get_id +#define qtm_same51_acq_module_get_version qtm_same54_acq_module_get_version +#define qtm_same51_ptc_handler qtm_same54_ptc_handler + +#endif /* TOUCH_API_SAME51_ACQ_MODULE_H */ + diff --git a/firmware/src/config/mcal/touch/qtm_acq_same54_0x000f_api.h b/firmware/src/config/mcal/touch/qtm_acq_same54_0x000f_api.h new file mode 100644 index 0000000..a9d8225 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_acq_same54_0x000f_api.h @@ -0,0 +1,458 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_acq_same54_0x000f_api.h + + Summary: + QTouch Modular Library + + Description: + API for Acquisition module - SAME54/PTC + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/*============================================================================ +Filename : qtm_acq_same54_0x000f_api.h +Project : QTouch Modular Library +Purpose : API for Acquisition module - SAME54/PTC +------------------------------------------------------------------------------ +Version Number : 0.7 +------------------------------------------------------------------------------ +Copyright (c) Microchip Inc. All rights reserved. +------------------------------------------------------------------------------ +============================================================================*/ + +#ifndef TOUCH_API_SAME54_ACQ_MODULE_H +#define TOUCH_API_SAME54_ACQ_MODULE_H + +#include "qtm_common_components_api.h" + +/* Calibration auto-tuning options */ +#define CAL_OPTION_MASK 0x03u + +#define CAL_AUTO_TUNE_NONE 0u +#define CAL_AUTO_TUNE_RSEL 1u +#define CAL_AUTO_TUNE_PRSC 2u +#define CAL_AUTO_TUNE_CSD 3u + +/* Timing auto-cal target */ +#define CAL_CHRG_TIME_MASK 0x30u +#define CAL_CHRG_TIME_POS 4u + +#define CAL_CHRG_2TAU 0u +#define CAL_CHRG_3TAU 1u +#define CAL_CHRG_4TAU 2u +#define CAL_CHRG_5TAU 3u + +#define RSEL_MAX_OPTION RSEL_VAL_200 +#define PRSC_MAX_OPTION PRSC_DIV_SEL_256 + +#define NUM_PTC_XY_LINES 32u + +/* X line bit position */ +#define X_NONE 0u +#define X(n) ((uint32_t)(1u << (n))) + +/* Y line bit position */ +#define Y(n) ((uint32_t)(1u << (n))) + +/* Extract Analog / Digital Gain */ +#define NODE_GAIN_ANA(m) (uint8_t)(((m) & 0xF0u) >> 4u) +#define NODE_GAIN_DIG(m) (uint8_t)((m) & 0x0Fu) + +/* Combine Analog / Digital Gain */ +#define NODE_GAIN(a,d) (uint8_t)(((a) << 4u)|(d)) + +/* Extract Resistor / Prescaler */ +#define NODE_RSEL(m) (uint8_t)(((m) & 0xF0u) >> 4u) +#define NODE_PRSC(m) (uint8_t)((m) & 0x0Fu) + +/* Combine Resistor / Prescaler */ +#define NODE_RSEL_PRSC(r,p) (uint8_t)(((r) << 4u)|(p)) + +typedef enum tag_filter_level_t { + FILTER_LEVEL_1, + FILTER_LEVEL_2, + FILTER_LEVEL_4, + FILTER_LEVEL_8, + FILTER_LEVEL_16, + FILTER_LEVEL_32, + FILTER_LEVEL_64, + FILTER_LEVEL_128, + FILTER_LEVEL_256, + FILTER_LEVEL_512, + FILTER_LEVEL_1024 +} +filter_level_t; + +/* Touch library GAIN setting */ +typedef enum tag_gain_t +{ + GAIN_1, + GAIN_2, + GAIN_4, + GAIN_8, + GAIN_16 +} +gain_t; +/* PTC clock prescale setting. +* For Example: if Generic clock input to PTC = 4MHz, then: +* PRSC_DIV_SEL_2 sets PTC Clock to 2MHz +* PRSC_DIV_SEL_4 sets PTC Clock to 1MHz +* +*/ +typedef enum tag_prsc_div_sel_t +{ + PRSC_DIV_SEL_2, + PRSC_DIV_SEL_4, + PRSC_DIV_SEL_8, + PRSC_DIV_SEL_16, + PRSC_DIV_SEL_32, + PRSC_DIV_SEL_64, + PRSC_DIV_SEL_128, + PRSC_DIV_SEL_256 +} +prsc_div_sel_t; + +/** +* PTC series resistor setting. For Mutual cap mode, this series +* resistor is switched internally on the Y-pin. For Self cap mode, +* thes series resistor is switched internally on the Sensor pin. +* +* Example: +* RSEL_VAL_0 sets internal series resistor to 0ohms. +* RSEL_VAL_20 sets internal series resistor to 20Kohms. +* RSEL_VAL_50 sets internal series resistor to 50Kohms. +* RSEL_VAL_100 sets internal series resistor to 100Kohms. +*/ +typedef enum tag_rsel_val_t +{ + RSEL_VAL_0, + RSEL_VAL_3, + RSEL_VAL_6, + RSEL_VAL_20, + RSEL_VAL_50, + RSEL_VAL_75, + RSEL_VAL_100, + RSEL_VAL_200 +} +rsel_val_t; + + +/** +* PTC acquisition frequency delay setting. +* +* The PTC acquisition frequency is dependent on the Generic clock +* input to PTC and PTC clock prescaler setting. This delay setting +* inserts "n" PTC clock cycles between consecutive measurements on +* a given sensor, thereby changing the PTC acquisition frequency. +* FREQ_HOP_SEL_1 setting inserts 1 PTC clock cycle between consecutive +* measurements. FREQ_HOP_SEL_14 setting inserts 14 PTC clock cycles. +* Hence, higher delay setting will increase the total time taken for +* capacitance measurement on a given sensor as compared to a lower +* delay setting. +* +* A desired setting can be used to avoid noise around the same frequency +* as the acquisition frequency. +* +*/ +typedef enum tag_freq_config_sel_t +{ + FREQ_SEL_0, + FREQ_SEL_1, + FREQ_SEL_2, + FREQ_SEL_3, + FREQ_SEL_4, + FREQ_SEL_5, + FREQ_SEL_6, + FREQ_SEL_7, + FREQ_SEL_8, + FREQ_SEL_9, + FREQ_SEL_10, + FREQ_SEL_11, + FREQ_SEL_12, + FREQ_SEL_13, + FREQ_SEL_14, + FREQ_SEL_15, + FREQ_SEL_SPREAD +} +freq_config_sel_t; + +/*---------------------------------------------------------------------------- +* Structure Declarations +*----------------------------------------------------------------------------*/ + +/* Node configuration +- v1: +- v2: Mega328PB => CSD, Up to 8 X lines, up to 32 Y lines +- v3: Tiny817 => 8PTC pins (Selectable X or Y), Driven shield +*/ +typedef struct +{ + uint32_t node_xmask; /* Selects the X Pins for this node */ + uint32_t node_ymask; /* Selects the Y Pins for this node */ + uint8_t node_csd; /* Charge Share Delay */ + uint8_t node_rsel_prsc; /* Bits 7:4 = Resistor, Bits 3:0 Prescaler */ + uint8_t node_gain; /* Bits 7:4 = Analog gain, Bits 3:0 = Digital gain */ + uint8_t node_oversampling; /* Accumulator setting */ +}qtm_acq_same54_node_config_t; + +/* Node run-time data - Defined in common api as it will be used with all acquisition modules */ + +/* Node group configuration */ +typedef struct +{ + uint16_t num_sensor_nodes; /* Number of sensor nodes */ + uint8_t acq_sensor_type; /* Self or mutual sensors */ + uint8_t calib_option_select; /* Hardware tuning: XX | TT 3/4/5 Tau | X | XX None/RSEL/PRSC/CSD */ + uint8_t freq_option_select; /* SDS or ASDV setting */ + uint8_t ptc_interrupt_priority; +} qtm_acq_node_group_config_t; + +/* Container structure for sensor group */ +typedef struct +{ + qtm_acq_node_group_config_t* qtm_acq_node_group_config; + qtm_acq_same54_node_config_t* qtm_acq_node_config; + qtm_acq_node_data_t* qtm_acq_node_data; +} qtm_acquisition_control_t; + +typedef struct +{ + qtm_acquisition_control_t* qtm_acq_control; + uint16_t auto_scan_node_number; + uint8_t auto_scan_node_threshold; + uint8_t auto_scan_trigger; +}qtm_auto_scan_config_t; + + + +#define DRIVEN_SHIELD_DUMMY_ACQ 3u + +typedef void (*qtm_drivenshield_callback_t)(uint8_t csd, uint8_t sds, uint8_t prescaler, uint8_t volatile * ptr, uint8_t value); + +/* Drivenshield status flag */ +typedef struct qtm_drivenshield_config_tag +{ + uint8_t flags; +}qtm_drivenshield_config_t; + +/*============================================================================ +touch_ret_t qtm_drivenshield_setup(qtm_drivenshield_config_t* config); +------------------------------------------------------------------------------ +Purpose: Setup the drivenshield with settings from the user +Input : drivenshield_config_t setup in touch.c and touch.h +Output : touch_ret_t +Notes : Called by application to load the drivenshield operating parameters + +============================================================================*/ +touch_ret_t qtm_drivenshield_setup(qtm_drivenshield_config_t* config); + +/*============================================================================ +void qtm_drivenshield_register_start_callback(qtm_drivenshield_callback_t callback); +------------------------------------------------------------------------------ +Purpose: Register the drivenshield Start callback with the touch library +Input : Pointer to the application function to start the event system +Output : touch_ret_t +Notes : The library initialises this with a null, if this remains the + library will function as normal, if this is not null then the + application will start the event system and call this callback before + start of touch measurement + +============================================================================*/ +touch_ret_t qtm_drivenshield_register_start_callback(qtm_drivenshield_callback_t callback); + +/*============================================================================ +touch_ret_t qtm_drivenshield_deregister_start_callback(void); +------------------------------------------------------------------------------ +Purpose: De-register the drivenshield Start callback with the touch library +Input : None +Output : touch_ret_t +Notes : When this function is called driven shield functionality will stop + +============================================================================*/ +touch_ret_t qtm_drivenshield_deregister_start_callback(void); + +/*---------------------------------------------------------------------------- +* prototypes +*----------------------------------------------------------------------------*/ + +/* Library prototypes */ +/*============================================================================ +touch_ret_t qtm_acquisition_process(void) +------------------------------------------------------------------------------ +Purpose: Signal capture and processing +Input : (Measured signals, config) +Output : TOUCH_SUCCESS or TOUCH_CAL_ERROR +Notes : none +============================================================================*/ +touch_ret_t qtm_acquisition_process(void); + +/*============================================================================ +touch_ret_t ptc_init_acquisition_module(qtm_acquisition_control_t* qtm_acq_control_ptr); +------------------------------------------------------------------------------ +Purpose: Initialize the PTC & Assign pins +Input : pointer to acquisition set +Output : touch_ret_t: TOUCH_SUCCESS or INVALID_PARAM +Notes : ptc_init_acquisition module must be called ONLY once with a pointer to each config set +============================================================================*/ +touch_ret_t qtm_ptc_init_acquisition_module(qtm_acquisition_control_t* qtm_acq_control_ptr); + +/*============================================================================ +touch_ret_t ptc_qtlib_assign_signal_memory(uint16_t* qtm_signal_raw_data_ptr); +------------------------------------------------------------------------------ +Purpose: Assign raw signals pointer to array defined in application code +Input : pointer to raw data array +Output : touch_ret_t: TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_ptc_qtlib_assign_signal_memory(uint16_t* qtm_signal_raw_data_ptr); + +/* Scan configuration */ + +/*============================================================================ +touch_ret_t enable_sensor_node(qtm_acquisition_control_t* qtm_acq_control_ptr, uint16_t qtm_which_node_number) +------------------------------------------------------------------------------ +Purpose: Enables a sensor node for measurement +Input : Node configurations pointer, node (channel) number +Output : touch_ret_t: +Notes : +============================================================================*/ +touch_ret_t qtm_enable_sensor_node(qtm_acquisition_control_t* qtm_acq_control_ptr, uint16_t qtm_which_node_number); + +/*============================================================================ +touch_ret_t calibrate_sensor_node(qtm_acquisition_control_t* qtm_acq_control_ptr, uint16_t qtm_which_node_number) +------------------------------------------------------------------------------ +Purpose: Marks a sensor node for calibration +Input : Node configurations pointer, node (channel) number +Output : touch_ret_t: +Notes : +============================================================================*/ +touch_ret_t qtm_calibrate_sensor_node(qtm_acquisition_control_t* qtm_acq_control_ptr, uint16_t qtm_which_node_number); + +/* Measurement start - sequence or windowcomp */ + +/*============================================================================ +touch_ret_t ptc_start_measurement_seq(qtm_acquisition_control_t* qtm_acq_control_pointer, void (*measure_complete_callback) (void)); +------------------------------------------------------------------------------ +Purpose: Loads touch configurations for first channel and start, +Input : Node configurations pointer, measure complete callback pointer +Output : touch_ret_t: +Notes : +============================================================================*/ +touch_ret_t qtm_ptc_start_measurement_seq(qtm_acquisition_control_t* qtm_acq_control_pointer, void (*measure_complete_callback) (void)); + +/*============================================================================ +touch_ret_t autoscan_sensor_node(qtm_auto_scan_config_t* qtm_auto_scan_config_ptr, void (*auto_scan_callback)(void)) +------------------------------------------------------------------------------ +Purpose: Configures the PTC for sleep mode measurement of a single node, with window comparator wake +Input : Acquisition set, channel number, threshold, scan trigger +Output : touch_ret_t +Notes : none +============================================================================*/ +touch_ret_t qtm_autoscan_sensor_node(qtm_auto_scan_config_t* qtm_auto_scan_config_ptr, void (*auto_scan_callback)(void)); + +/*============================================================================ +touch_ret_t autoscan_node_cancel(void) +------------------------------------------------------------------------------ +Purpose: Cancel auto-scan config +Input : None +Output : touch_ret_t +Notes : none +============================================================================*/ +touch_ret_t qtm_autoscan_node_cancel(void); + +/*============================================================================ +void qtm_autoscan_trigger(void); +------------------------------------------------------------------------------ +Purpose: Trigger a single-sensor LP measurement +Input : None +Output : touch_ret_t +Notes : none +============================================================================*/ +void qtm_autoscan_trigger(void); + +/*============================================================================ +void qtm_ptc_de_init(void) +------------------------------------------------------------------------------ +Purpose: Clear PTC Pin registers, set TOUCH_STATE_NULL +Input : none +Output : none +Notes : none +============================================================================*/ +void qtm_ptc_de_init(void); + +/*============================================================================ +uint16_t same54_acq_module_get_id(void); +------------------------------------------------------------------------------ +Purpose: Check module ID +Input : +Output : 16-bit ID for the module +Notes : none +============================================================================*/ +uint16_t qtm_same54_acq_module_get_id(void); + + + +/*============================================================================ +uint8_t same54_acq_module_get_version(void); +------------------------------------------------------------------------------ +Purpose: Check module verison +Input : +Output : 8-bit Firmware version (4-bit Major / 4-bit Minor) for the module +Notes : none +============================================================================*/ +uint8_t qtm_same54_acq_module_get_version(void); + + + +/*============================================================================ +void qtm_same54_ptc_handler(void) +------------------------------------------------------------------------------ +Purpose: Captures the measurement, starts the next or End Of Sequence handler +Input : none +Output : none +Notes : none +============================================================================*/ +void qtm_same54_ptc_handler(void); + +/*============================================================================ +void qtm_ptc_clear_interrupt(void) +------------------------------------------------------------------------------ +Purpose: Clears the eoc/wcomp interrupt bits +Input : none +Output : none +Notes : none +============================================================================*/ +void qtm_ptc_clear_interrupt(void); + +#endif /* TOUCH_API_PTC_H */ + diff --git a/firmware/src/config/mcal/touch/qtm_common_components_api.h b/firmware/src/config/mcal/touch/qtm_common_components_api.h new file mode 100644 index 0000000..5fcb022 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_common_components_api.h @@ -0,0 +1,202 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_common_components_api.h + + Summary: + QTouch Modular Library + + Description: + Common API across modules + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +#ifndef __QTM_API_COMMON_INC__ +#define __QTM_API_COMMON_INC__ + +#include +#include + +/* Acquisition type */ +/* Acquisition set config */ +#define NODE_SELFCAP 0x80u +#define NODE_SELFCAP_SHIELD 0x81u +#define NODE_MUTUAL 0x40u +#define NODE_MUTUAL_4P 0x41u + +/* ---------------------------------------------------------------------------------------- */ +/* Touch Library functions return a touch_ret_t */ +/* ---------------------------------------------------------------------------------------- */ +typedef enum tag_touch_ret_t { + /* Successful completion of operation. */ + TOUCH_SUCCESS = 0u, + + /* Touch Library is busy with pending previous Touch measurement. */ + TOUCH_ACQ_INCOMPLETE = 1u, + + /* Invalid input parameter. */ + TOUCH_INVALID_INPUT_PARAM = 2u, + + /* Operation not allowed in the current state of the library module. */ + TOUCH_INVALID_LIB_STATE = 3u, + + /* Successful completion of FMEA.*/ + TOUCH_FMEA_SUCCESS = 4u, + + /* Operation not allowed in the current state of the library module. */ + TOUCH_FMEA_ERROR = 5u, + + /* MAGIC number used to Program Counter checking. */ + TOUCH_PC_FUNC_MAGIC_NO_1 = 6u, + + /* MAGIC number used to Program Counter checking. */ + TOUCH_PC_FUNC_MAGIC_NO_2 = 7u, + + /* Error in Logical Program Flow. */ + TOUCH_LOGICAL_PROGRAM_FLOW_ERROR = 8u, + + /* CRC on Touch Configuration failure. */ + TOUCH_LIB_CRC_FAIL = 9u, + + /* Double inverse failure. */ + TOUCH_LIB_DI_FAIL = 10u, + + /* Invalid Pointer argument */ + TOUCH_INVALID_POINTER = 11u, + + /* MAGIC number used to Program Counter checking. */ + TOUCH_PC_FUNC_MAGIC_NO_3 = 12u, + + /* Library Is Unsafe to Use */ + TOUCH_LIB_UNSAFE = 13u, + + /* Library Is Unable t Calibrate Node */ + TOUCH_LIB_NODE_CAL_ERROR = 14u + +} touch_ret_t; + +/* Touch library state */ +typedef enum tag_touch_lib_state_t { + /* Null - Not initialized */ + TOUCH_STATE_NULL = 0u, + + /* Initialized, no measurements yet */ + TOUCH_STATE_INIT = 1u, + + /* Ready to take a measurement */ + TOUCH_STATE_READY = 2u, + + /* Calibration set for some nodes */ + TOUCH_STATE_CALIBRATE = 3u, + + /* Measurement sequence in progress */ + TOUCH_STATE_BUSY = 4u +} touch_lib_state_t; + +/* ---------------------------------------------------------------------------------------- */ +/* Acquisition node status byte */ +/* ---------------------------------------------------------------------------------------- */ +/* + Bit(s) + 0 Node enabled for measurement (1) / Disabled (0) + 1 Request hardware calibration (1) + 4:2 Node state - 0 = Measure + 1 = CC Calibration + 2 = Prescaler calibration + 3 = Series R calibration + 4 = Charge Share Delay calibration + 5 Reserved + 6 TAU_CAL_DONE (1) - Flag for 3-stage hardware cal + 7 CAL ERROR - Max comp cap +*/ + +#define NODE_STATUS_MASK 0x1Cu +#define NODE_STATUS_POS 0x02u + +#define NODE_ENABLED 0x01u +#define NODE_CAL_REQ 0x02u +#define CAL_STATE_SET 0x20u +#define TAU_CAL_DONE 0x40u +#define NODE_CAL_ERROR 0x80u + +/* Node state - 3 bits */ +#define NODE_MEASURE 0u +#define NODE_CC_CAL 1u +#define NODE_PRSC_CAL 2u +#define NODE_RSEL_CAL 3u +#define NODE_CSD_CAL 4u + +/* Any CAL bit */ +#define NODE_CAL_MASK 0x1Eu + +/* ---------------------------------------------------------------------------------------- */ +/* Acquisition Node run-time data */ +/* ---------------------------------------------------------------------------------------- */ +typedef struct { + uint8_t node_acq_status; + uint16_t node_acq_signals; + uint16_t node_comp_caps; +} qtm_acq_node_data_t; + +/* ---------------------------------------------------------------------------------------- */ +/* Key sensor status byte */ +/* ---------------------------------------------------------------------------------------- */ +/* Note: Bit 7 indicates logical 'In Detect' (States 'Detect' and 'Filter Out') */ + +#define QTM_KEY_STATE_DISABLE 0x00u +#define QTM_KEY_STATE_INIT 0x01u +#define QTM_KEY_STATE_CAL 0x02u +#define QTM_KEY_STATE_NO_DET 0x03u +#define QTM_KEY_STATE_FILT_IN 0x04u +#define QTM_KEY_STATE_DETECT 0x85u +#define QTM_KEY_STATE_FILT_OUT 0x86u +#define QTM_KEY_STATE_ANTI_TCH 0x07u +#define QTM_KEY_STATE_SUSPEND 0x08u +#define QTM_KEY_STATE_CAL_ERR 0x09u +#define KEY_TOUCHED_MASK 0x80u +/* ---------------------------------------------------------------------------------------- */ +/* Key sensor run-time data */ +/* ---------------------------------------------------------------------------------------- */ +typedef struct { + uint8_t sensor_state; /* Disabled, Off, On, Filter, Cal... */ + uint8_t sensor_state_counter; /* State counter */ + qtm_acq_node_data_t *node_data_struct_ptr; /* Pointer to node data structure */ + uint16_t channel_reference; /* Reference signal */ +} qtm_touch_key_data_t; + +/* ---------------------------------------------------------------------------------------- */ +/* Scroller physical / layout types */ +/* ---------------------------------------------------------------------------------------- */ +#define SCROLLER_TYPE_SLIDER 0u +#define SCROLLER_TYPE_WHEEL 1u +#define SCROLLER_TYPE_WRAPAROUND 2u + +#endif /* __QTM_QPI_COMMON_*/ diff --git a/firmware/src/config/mcal/touch/qtm_freq_hop_0x0006_api.h b/firmware/src/config/mcal/touch/qtm_freq_hop_0x0006_api.h new file mode 100644 index 0000000..1e31ef6 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_freq_hop_0x0006_api.h @@ -0,0 +1,120 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_freq_hop_0x0006_api.h + + Summary: + QTouch Modular Library + + Description: + API for Frequnecy Hop module + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/* QTouch Modular Library Configuration */ + +#ifndef TOUCH_API_FREQ_HOP_H +#define TOUCH_API_FREQ_HOP_H + + +/* Include files */ +#include +#include "qtm_common_components_api.h" + +/*---------------------------------------------------------------------------- + * Structure Declarations + *----------------------------------------------------------------------------*/ + +/* Frequency HOP Module */ +/* Configuration */ +typedef struct +{ + uint16_t num_sensors; + uint8_t num_freqs; + uint8_t *freq_option_select; + uint8_t *median_filter_freq; /* PTC frequencies to be used on the median filter samples */ + +}qtm_freq_hop_config_t; + +/* Status data */ +typedef struct +{ + uint8_t module_status; /* Obligatory status byte: Bit 7 = Reburst... */ + uint8_t current_freq; /* PTC Sampling Delay Selection - 0 to 15 PTC CLK cycles */ + uint16_t *filter_buffer; /* Filter buffer used to store past cycle signal values of sensor */ + qtm_acq_node_data_t *qtm_acq_node_data; + +}qtm_freq_hop_data_t; + +/* Container */ +typedef struct +{ + qtm_freq_hop_data_t (*qtm_freq_hop_data); + qtm_freq_hop_config_t (*qtm_freq_hop_config); +} qtm_freq_hop_control_t; + + +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ +/*============================================================================ +touch_ret_t qtm_freq_hop(qtm_freq_hop_control_t *qtm_freq_hop_control); +------------------------------------------------------------------------------ +Purpose: Runs freq hop process +Input : Pointer to container structure +Output : touch_ret_t +Notes : none +============================================================================*/ +touch_ret_t qtm_freq_hop(qtm_freq_hop_control_t *qtm_freq_hop_control); + +/*============================================================================ +uint16_t qtm_get_freq_hop_module_id(void) +------------------------------------------------------------------------------ +Purpose: Returns the module ID +Input : none +Output : Module ID +Notes : none +============================================================================*/ +uint16_t qtm_get_freq_hop_module_id(void); + + +/*============================================================================ +uint8_t qtm_get_freq_hop_module_ver(void) +------------------------------------------------------------------------------ +Purpose: Returns the module Firmware version +Input : none +Output : Module ID - Upper nibble major / Lower nibble minor +Notes : none +============================================================================*/ +uint8_t qtm_get_freq_hop_module_ver(void); + + +#endif /* TOUCH_API_FREQ_HOP_H */ diff --git a/firmware/src/config/mcal/touch/qtm_gestures_2d_0x0023_api.h b/firmware/src/config/mcal/touch/qtm_gestures_2d_0x0023_api.h new file mode 100644 index 0000000..4b7b161 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_gestures_2d_0x0023_api.h @@ -0,0 +1,217 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_gestures_2d_0x0023_api.h + + Summary: + QTouch Modular Library + + Description: + API for Gesture Module + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/*============================================================================ +Filename : qtm_gestures_api.h +Project : QTouch Modular Library +Purpose : Structs and definitions for use within modules +------------------------------------------------------------------------------ +Copyright (C) 2019 Microchip. All rights reserved. +------------------------------------------------------------------------------ +============================================================================*/ + +#ifndef TOUCH_API_GESTURE_2D_H +#define TOUCH_API_GESTURE_2D_H + +/* Include files */ +#include +#include "qtm_common_components_api.h" + +/* Timebase */ +#define GESTURE_TIMEBASE_DEFAULT 10u + +/* gesture IDs */ +#define NO_GESTURE 0x00u +#define RIGHT_SWIPE 0x10u +#define RIGHT_SWIPE_HOLD 0x12u +#define RIGHT_EDGE_SWIPE 0x11u +#define RIGHT_EDGE_SWIPE_HOLD 0x13u +#define RIGHT_SWIPE_DUAL 0x14u +#define RIGHT_SWIPE_HOLD_DUAL 0x16u +#define RIGHT_EDGE_SWIPE_DUAL 0x15u +#define RIGHT_EDGE_SWIPE_HOLD_DUAL 0x17u + +#define LEFT_SWIPE 0x20u +#define LEFT_SWIPE_HOLD 0x22u +#define LEFT_EDGE_SWIPE 0x21u +#define LEFT_EDGE_SWIPE_HOLD 0x23u +#define LEFT_SWIPE_DUAL 0x24u +#define LEFT_SWIPE_HOLD_DUAL 0x26u +#define LEFT_EDGE_SWIPE_DUAL 0x25u +#define LEFT_EDGE_SWIPE_HOLD_DUAL 0x27u + +#define UP_SWIPE 0x30u +#define UP_SWIPE_HOLD 0x32u +#define UP_EDGE_SWIPE 0x31u +#define UP_EDGE_SWIPE_HOLD 0x33u +#define UP_SWIPE_DUAL 0x34u +#define UP_SWIPE_HOLD_DUAL 0x36u +#define UP_EDGE_SWIPE_DUAL 0x35u +#define UP_EDGE_SWIPE_HOLD_DUAL 0x37u + +#define DOWN_SWIPE 0x40u +#define DOWN_SWIPE_HOLD 0x42u +#define DOWN_EDGE_SWIPE 0x41u +#define DOWN_EDGE_SWIPE_HOLD 0x43u +#define DOWN_SWIPE_DUAL 0x44u +#define DOWN_SWIPE_HOLD_DUAL 0x46u +#define DOWN_EDGE_SWIPE_DUAL 0x45u +#define DOWN_EDGE_SWIPE_HOLD_DUAL 0x47u + +#define HOLD_TAP 0xd0u +#define HOLD_TAP_DUAL 0xd4u +#define PRE_TAP 0x8fu +#define TAP 0x90u +#define DOUBLE_TAP 0x92u +#define TAP_DUAL 0xa0u +#define PALM 0xb0u + +#define PINCH 0xc0u +#define ZOOM 0xc1u + + +#define GESTURE_RELEASED 0xA8u + +#define CW_WHEEL 0xf0u +#define CCW_WHEEL 0xf1u +#define CW_WHEEL_DUAL 0xf4u +#define CCW_WHEEL_DUAL 0xf5u + +/*---------------------------------------------------------------------------- +* Structure Declarations +*----------------------------------------------------------------------------*/ + +/* Gestures 2D Configuration */ +typedef struct +{ + uint16_t *horiz_position0; + uint16_t *vertical_position0; + uint8_t *surface_status0; + uint16_t *horiz_position1; + uint16_t *vertical_position1; + uint8_t *surface_status1; + uint8_t surface_resolution; + uint8_t tapReleaseTimeout; + uint8_t tapHoldTimeout; + uint8_t swipeTimeout; + uint8_t xSwipeDistanceThreshold; + uint8_t ySwipeDistanceThreshold; + uint8_t edgeSwipeDistanceThreshold; + uint8_t tapDistanceThreshold; + uint8_t seqTapDistanceThreshold; + uint8_t edgeBoundary; + int8_t wheelPostscaler; + int8_t wheelStartQuadrantCount; + int8_t wheelReverseQuadrantCount; + uint8_t pinchZoomThreshold; +}qtm_gestures_2d_config_t; + +/* Surface CS Data */ +typedef struct +{ + uint8_t gestures_status; + uint8_t gestures_which_gesture; + uint8_t gestures_info; +}qtm_gestures_2d_data_t; + +/* Container */ +typedef struct +{ + qtm_gestures_2d_data_t *qtm_gestures_2d_data; + qtm_gestures_2d_config_t *qtm_gestures_2d_config; +} qtm_gestures_2d_control_t; + +/*---------------------------------------------------------------------------- +* prototypes +*----------------------------------------------------------------------------*/ +void qtm_gestures_2d_clearGesture(void); + +/*============================================================================ +touch_ret_t qtm_init_gestures_2d(void); +------------------------------------------------------------------------------ +Purpose: Initialize gesture tracking variables +Input : - +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_init_gestures_2d(void); + +/*============================================================================ +touch_ret_t qtm_gestures_2d_process(qtm_gestures_2d_control_t *qtm_gestures_2d_control); +------------------------------------------------------------------------------ +Purpose: Gesture engine processes updated touch info +Input : Gesture control struct pointer +Output : ?TOUCH_SUCCESS? +Notes : none +============================================================================*/ +touch_ret_t qtm_gestures_2d_process(qtm_gestures_2d_control_t *qtm_gestures_2d_control); + +/*============================================================================ +void qtm_update_gesture_2d_timer(uint16_t time_elapsed_since_update); +------------------------------------------------------------------------------ +Purpose: Updates local variable with time period +Input : Number of ms since last update +Output : none +Notes : none +============================================================================*/ +void qtm_update_gesture_2d_timer(uint16_t time_elapsed_since_update); + +/*============================================================================ +uint16_t qtm_get_gesture_2d_module_id(void); +------------------------------------------------------------------------------ +Purpose: Returns the module ID +Input : none +Output : Module ID +Notes : none +============================================================================*/ +uint16_t qtm_get_gesture_2d_module_id(void); + +/*============================================================================ +uint8_t qtm_get_gesture_2d_module_ver(void); +------------------------------------------------------------------------------ +Purpose: Returns the module Firmware version +Input : none +Output : Module ID - Upper nibble major / Lower nibble minor +Notes : none +============================================================================*/ +uint8_t qtm_get_gesture_2d_module_ver(void); + +#endif /* TOUCH_API_GESTURE_2D_H */ diff --git a/firmware/src/config/mcal/touch/qtm_scroller_0x000b_api.h b/firmware/src/config/mcal/touch/qtm_scroller_0x000b_api.h new file mode 100644 index 0000000..3eba0b5 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_scroller_0x000b_api.h @@ -0,0 +1,197 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_scroller_0x000b_api.h + + Summary: + QTouch Modular Library + + Description: + API for scroller module + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/* QTouch Modular Library */ +/* API Header file - qtm_scroller_0x000b */ + +#ifndef TOUCH_API_SCROLLER_H +#define TOUCH_API_SCROLLER_H + +/* Include files */ +#include +#include "qtm_common_components_api.h" + +/* Scroller status bits */ +#define SCROLLER_TOUCH_ACTIVE (uint8_t)((uint8_t)1<<0u) /* Bit 0 */ +#define SCROLLER_POSITION_CHANGE (uint8_t)((uint8_t)1<<1u) /* Bit 1 */ +#define SCROLLER_REBURST (uint8_t)((uint8_t)1<<7u) /* Bit 7 */ + +/* Extract Resolution / Deadband */ +#define SCROLLER_RESOLUTION(m) (uint8_t)(((m) & 0xF0u) >> 4u) +#define SCROLLER_DEADBAND(m) (uint8_t)((m) & 0x0Fu) + +/* Combine Resolution / Deadband */ +#define SCROLLER_RESOL_DEADBAND(r,p) (uint8_t)(((r) << 4u)|(p)) + +/* scroller resolution setting */ +typedef enum tag_scroller_resolution_t +{ + SCR_RESOL_2_BIT = 2, + SCR_RESOL_3_BIT, + SCR_RESOL_4_BIT, + SCR_RESOL_5_BIT, + SCR_RESOL_6_BIT, + SCR_RESOL_7_BIT, + SCR_RESOL_8_BIT, + SCR_RESOL_9_BIT, + SCR_RESOL_10_BIT, + SCR_RESOL_11_BIT, + SCR_RESOL_12_BIT +} +scroller_resolution_t; + + +/* scroller deadband percentage setting */ +typedef enum tag_scroller_deadband_t +{ + SCR_DB_NONE, + SCR_DB_1_PERCENT, + SCR_DB_2_PERCENT, + SCR_DB_3_PERCENT, + SCR_DB_4_PERCENT, + SCR_DB_5_PERCENT, + SCR_DB_6_PERCENT, + SCR_DB_7_PERCENT, + SCR_DB_8_PERCENT, + SCR_DB_9_PERCENT, + SCR_DB_10_PERCENT, + SCR_DB_11_PERCENT, + SCR_DB_12_PERCENT, + SCR_DB_13_PERCENT, + SCR_DB_14_PERCENT, + SCR_DB_15_PERCENT +} +scroller_deadband_t; + +/*---------------------------------------------------------------------------- + * Structure Declarations + *----------------------------------------------------------------------------*/ + +/* Configuration - Group of scrollers */ +typedef struct +{ + qtm_touch_key_data_t *qtm_touch_key_data; + uint8_t num_scrollers; +}qtm_scroller_group_config_t; + +/* Data - Group of scrollers */ +typedef struct +{ + uint8_t scroller_group_status; +}qtm_scroller_group_data_t; + +/* Configuration - Each slider / wheel */ +typedef struct +{ + uint8_t type; + uint16_t start_key; + uint8_t number_of_keys; + uint8_t resol_deadband; + uint8_t position_hysteresis; + uint16_t contact_min_threshold; +}qtm_scroller_config_t; + +/* Data Each - slider / wheel */ +typedef struct +{ + uint8_t scroller_status; + uint8_t right_hyst; + uint8_t left_hyst; + uint16_t raw_position; + uint16_t position; + uint16_t contact_size; +}qtm_scroller_data_t; + +/* Container */ +typedef struct +{ + qtm_scroller_group_data_t *qtm_scroller_group_data; + qtm_scroller_group_config_t *qtm_scroller_group_config; + qtm_scroller_data_t *qtm_scroller_data; + qtm_scroller_config_t *qtm_scroller_config; +} qtm_scroller_control_t; + + +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ + +/*============================================================================ +touch_ret_t qtm_init_scroller_module(qtm_scroller_control_t *qtm_scroller_control) +------------------------------------------------------------------------------ +Purpose: Initialize a scroller +Input : Pointer to scroller group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_init_scroller_module(qtm_scroller_control_t *qtm_scroller_control); + +/*============================================================================ +touch_ret_t qtm_scroller_process(qtm_scroller_control_t *qtm_scroller_control) +------------------------------------------------------------------------------ +Purpose: Scroller position calculation and filtering +Input : Pointer to scroller group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_scroller_process(qtm_scroller_control_t *qtm_scroller_control); + +/*============================================================================ +uint16_t qtm_get_scroller_module_id(void) +------------------------------------------------------------------------------ +Purpose: Returns the module ID +Input : none +Output : Module ID +Notes : none +============================================================================*/ +uint16_t qtm_get_scroller_module_id(void); + +/*============================================================================ +uint8_t qtm_get_scroller_module_ver(void) +------------------------------------------------------------------------------ +Purpose: Returns the module Firmware version +Input : none +Output : Module ID - Upper nibble major / Lower nibble minor +Notes : none +============================================================================*/ +uint8_t qtm_get_scroller_module_ver(void); + +#endif /* TOUCH_API_SCROLLER_H */ diff --git a/firmware/src/config/mcal/touch/qtm_surface_cs_0x0021_api.h b/firmware/src/config/mcal/touch/qtm_surface_cs_0x0021_api.h new file mode 100644 index 0000000..53de796 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_surface_cs_0x0021_api.h @@ -0,0 +1,199 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_surface_cs_0x0021_api.h + + Summary: + QTouch Modular Library + + Description: + API for surface single-touch + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/*============================================================================ +Filename : qtm_surface_1finger_touch_api.h +Project : QTouch Modular Library +Purpose : Structs and definitions for use within modules +------------------------------------------------------------------------------ +Copyright (C) 2019 Microchip. All rights reserved. +------------------------------------------------------------------------------ +============================================================================*/ + +#ifndef TOUCH_API_SURFACE_CS_H +#define TOUCH_API_SURFACE_CS_H + +/* Include files */ +#include +#include "qtm_common_components_api.h" + +/* Axis status bits */ +#define TOUCH_ACTIVE (uint8_t)((uint8_t)1u<<0u) /* Bit 0 */ +#define POSITION_CHANGE (uint8_t)((uint8_t)1u<<1u) /* Bit 1 */ +#define POSITION_H_INC (uint8_t)((uint8_t)1u<<2u) /* Bit 2 */ +#define POSITION_H_DEC (uint8_t)((uint8_t)1u<<3u) /* Bit 3 */ +#define POSITION_V_INC (uint8_t)((uint8_t)1u<<4u) /* Bit 4 */ +#define POSITION_V_DEC (uint8_t)((uint8_t)1u<<5u) /* Bit 5 */ +#define SURFACE_REBURST (uint8_t)((uint8_t)1u<<7u) /* Bit 7 */ + +/* Extract Resolution / Deadband */ +#define SCR_RESOLUTION(m) ((uint8_t)(((m) & 0xF0u) >> 4u)) +#define SCR_DEADBAND(m) ((uint8_t)((m) & 0x0Fu)) + +/* Combine Resolution / Deadband */ +#define SCR_RESOL_DEADBAND(r,p) ((uint8_t)(((r) << 4u)|(p))) + +/* Position filtering */ +#define POSITION_IIR_MASK 0x03u +#define POSITION_MEDIAN_ENABLE 0x10u +#define SCR_MEDIAN_IIR(r,p) ((uint8_t)(((r) << 4u)|(p))) + +/* scroller resolution setting */ +typedef enum tag_resolution_t +{ + RESOL_2_BIT = 2, + RESOL_3_BIT, + RESOL_4_BIT, + RESOL_5_BIT, + RESOL_6_BIT, + RESOL_7_BIT, + RESOL_8_BIT, + RESOL_9_BIT, + RESOL_10_BIT, + RESOL_11_BIT, + RESOL_12_BIT +} +scr_resolution_t; + + +/* scroller deadband percentage setting */ +typedef enum tag_deadband_t +{ + DB_NONE, + DB_1_PERCENT, + DB_2_PERCENT, + DB_3_PERCENT, + DB_4_PERCENT, + DB_5_PERCENT, + DB_6_PERCENT, + DB_7_PERCENT, + DB_8_PERCENT, + DB_9_PERCENT, + DB_10_PERCENT, + DB_11_PERCENT, + DB_12_PERCENT, + DB_13_PERCENT, + DB_14_PERCENT, + DB_15_PERCENT +} +scr_deadband_t; + +/*---------------------------------------------------------------------------- + * Structure Declarations + *----------------------------------------------------------------------------*/ + +/* Surface CS Configuration */ +typedef struct +{ + uint16_t start_key_h; /* Start key of horizontal axis */ + uint8_t number_of_keys_h; /* Number of keys in horizontal axis */ + uint16_t start_key_v; /* Start key of vertical axis */ + uint8_t number_of_keys_v; /* Number of keys in vertical axis */ + uint8_t resol_deadband; /* Resolution 2 to 12 bits | Deadband 0% to 15% */ + uint8_t position_hysteresis; /* Distance threshold for initial move or direction change */ + uint8_t position_filter; /* Bits 1:0 = IIR (0% / 25% / 50% / 75%), Bit 4 = Enable Median Filter (3-point) */ + uint16_t contact_min_threshold; /* Contact threshold / Sum of 4 deltas */ + qtm_touch_key_data_t *qtm_touch_key_data; /* Pointer to touch key data */ +}qtm_surface_cs_config_t; + +/* Surface CS Data */ +typedef struct +{ + uint8_t qt_surface_status; + uint16_t h_position_abs; + uint16_t h_position; + uint16_t v_position_abs; + uint16_t v_position; + uint16_t contact_size; +}qtm_surface_contact_data_t; + +/* Container */ +typedef struct +{ + qtm_surface_contact_data_t *qtm_surface_contact_data; + qtm_surface_cs_config_t *qtm_surface_cs_config; +} qtm_surface_cs_control_t; + +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ + +/*============================================================================ +touch_ret_t qtm_init_surface_cs(qtm_surface_cs_control_t *qtm_surface_cs_control); +------------------------------------------------------------------------------ +Purpose: Initialize a scroller +Input : Pointer to scroller group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_init_surface_cs(qtm_surface_cs_control_t *qtm_surface_cs_control); + +/*============================================================================ +touch_ret_t qtm_surface_cs_process(qtm_surface_cs_control_t *qtm_surface_cs_control); +------------------------------------------------------------------------------ +Purpose: Scroller position calculation and filtering +Input : Pointer to scroller group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_surface_cs_process(qtm_surface_cs_control_t *qtm_surface_cs_control); + +/*============================================================================ +uint16_t qtm_get_scroller_module_id(void) +------------------------------------------------------------------------------ +Purpose: Returns the module ID +Input : none +Output : Module ID +Notes : none +============================================================================*/ +uint16_t qtm_get_surface_cs_module_id(void); + +/*============================================================================ +uint8_t qtm_get_scroller_module_ver(void) +------------------------------------------------------------------------------ +Purpose: Returns the module Firmware version +Input : none +Output : Module ID - Upper nibble major / Lower nibble minor +Notes : none +============================================================================*/ +uint8_t qtm_get_surface_cs_module_ver(void); + +#endif /* TOUCH_API_SCROLLER_H */ diff --git a/firmware/src/config/mcal/touch/qtm_touch_key_0x0002_api.h b/firmware/src/config/mcal/touch/qtm_touch_key_0x0002_api.h new file mode 100644 index 0000000..7eea9e5 --- /dev/null +++ b/firmware/src/config/mcal/touch/qtm_touch_key_0x0002_api.h @@ -0,0 +1,237 @@ + +/******************************************************************************* + Touch Library + + Company: + Microchip Technology Inc. + + File Name: + qtm_touch_key_0x0002_api.h + + Summary: + QTouch Modular Library + + Description: + API for Keys module + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +/*============================================================================ +Filename : qtm_touch_key_api.h +Project : QTouch Modular Library +Purpose : Structs and definitions for use within modules +------------------------------------------------------------------------------ +Copyright (c) Microchip. All rights reserved. +------------------------------------------------------------------------------ +============================================================================*/ + +#ifndef TOUCH_API_KEYS_H +#define TOUCH_API_KEYS_H + +/* Include files */ +#include +#include "qtm_common_components_api.h" + +/* Keys status dlags */ +#define QTM_KEY_REBURST 0x80u +#define QTM_KEY_DETECT 0x01u + +/* QTLib Timebase */ +#define QTLIB_TIMEBASE 200u + +/*---------------------------------------------------------------------------- + * type definitions + *----------------------------------------------------------------------------*/ + +/* ! An unsigned 8-bit number setting a sensor detection threshold. */ +typedef uint8_t threshold_t; + +/* ! Sensor number type. */ +typedef uint16_t sensor_id_t; + +/* ! Current time type. */ +typedef uint16_t touch_current_time_t; + +/* ! Touch sensor delta value type. */ +typedef int16_t touch_delta_t; + +/* ! Status of Touch measurement. */ +typedef uint16_t touch_acq_status_t; + +typedef enum tag_hysteresis_t { HYST_50, HYST_25, HYST_12_5, HYST_6_25, MAX_HYST } QTM_hysteresis_t; + +typedef enum tag_aks_group_t { + NO_AKS_GROUP, + AKS_GROUP_1, + AKS_GROUP_2, + AKS_GROUP_3, + AKS_GROUP_4, + AKS_GROUP_5, + AKS_GROUP_6, + AKS_GROUP_7, + MAX_AKS_GROUP +} QTM_aks_group_t; + +typedef enum tag_recal_threshold_t { + RECAL_100, + RECAL_50, + RECAL_25, + RECAL_12_5, + RECAL_6_25, + MAX_RECAL +} recal_threshold_t; + +/* Reburst mode: +0 = none (application calls only) +1 = Unresolved - i.e. sensors in process of calibration / filter in / filter out and AKS groups +2 = All keys +*/ +typedef enum { REBURST_NONE, REBURST_UNRESOLVED, REBURST_ALL } reburst_mode_t; +/*---------------------------------------------------------------------------- + * Structure Declarations + *----------------------------------------------------------------------------*/ + +/* Key process module */ +/* Sensor group config */ +typedef struct { + uint16_t num_key_sensors; /* Number of sensors */ + uint8_t sensor_touch_di; /* Count in to Detect */ + uint8_t sensor_max_on_time; /* Max on duration x 200ms */ + uint8_t sensor_anti_touch_di; /* Count in to Anti-touch recal */ + uint8_t sensor_anti_touch_recal_thr; /* Anti-touch recal threshold % */ + uint8_t sensor_touch_drift_rate; /* One count per <200> ms */ + uint8_t sensor_anti_touch_drift_rate; /* One count per <200> ms */ + uint8_t sensor_drift_hold_time; /* Drift hold time */ + uint8_t sensor_reburst_mode; /* None / Unresolved / All */ +} qtm_touch_key_group_config_t; + +/* Sensor group data */ +typedef struct { + uint8_t qtm_keys_status; /* Status byte - bitfield: Bit 7 = REBURST_REQ, Bits 6:1 = Reserved, Bit 0 = Detect */ + uint16_t acq_group_timestamp; /* For tracking this group drift etc */ + uint8_t dht_count_in; /* Count of drift hold time */ + uint8_t tch_drift_count_in; /* Count of towards touch drift */ + uint8_t antitch_drift_count_in; /* Count of away from touch drift */ +} qtm_touch_key_group_data_t; + +/* Sensor keys config */ +typedef struct { + uint8_t channel_threshold; /* Touch detection threshold */ + uint8_t channel_hysteresis; /* Percentage of threshold reduction to exit detect state */ + uint8_t channel_aks_group; /* 0 = None, 1-255 = group number */ +} qtm_touch_key_config_t; + +/* ---------------------------------------------------------------------------------------- */ +/* Key sensor run-time data - api common */ +/* ---------------------------------------------------------------------------------------- */ + +/* Container */ +typedef struct { + qtm_touch_key_group_data_t(*qtm_touch_key_group_data); + qtm_touch_key_group_config_t(*qtm_touch_key_group_config); + qtm_touch_key_data_t(*qtm_touch_key_data); + qtm_touch_key_config_t(*qtm_touch_key_config); +} qtm_touch_key_control_t; + +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ + +/* Key Process Library Prototypes */ + +/*============================================================================ +touch_ret_t qtm_init_sensor_key(qtm_touch_key_control_t* qtm_lib_key_group_ptr, uint8_t which_sensor_key, +qtm_acq_node_data_t* acq_lib_node_ptr) +------------------------------------------------------------------------------ +Purpose: Initialize a touch key sensor +Input : Pointer to key group control data, key number, pointers to sensor node status and signal +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_init_sensor_key(qtm_touch_key_control_t *qtm_lib_key_group_ptr, uint8_t which_sensor_key, + qtm_acq_node_data_t *acq_lib_node_ptr); + +/*============================================================================ +touch_ret_t qtm_key_sensors_process(qtm_touch_key_control_t* qtm_lib_key_group_ptr) +------------------------------------------------------------------------------ +Purpose: Sensor key post-processing (touch detect state machine) +Input : Pointer to key group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_key_sensors_process(qtm_touch_key_control_t *qtm_lib_key_group_ptr); + +/*============================================================================ +touch_ret_t qtm_key_suspend(uint16_t which_sensor_key, qtm_touch_key_control_t* qtm_lib_key_group_ptr) +------------------------------------------------------------------------------ +Purpose: Suspends acquisition measurements for the key +Input : Key number, Pointer to key group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_key_suspend(uint16_t which_sensor_key, qtm_touch_key_control_t *qtm_lib_key_group_ptr); + +/*============================================================================ +touch_ret_t qtm_key_resume(uint16_t which_sensor_key, qtm_touch_key_control_t* qtm_lib_key_group_ptr) +------------------------------------------------------------------------------ +Purpose: Resumes acquisition measurements for the key +Input : Key number, Pointer to key group control data +Output : TOUCH_SUCCESS +Notes : none +============================================================================*/ +touch_ret_t qtm_key_resume(uint16_t which_sensor_key, qtm_touch_key_control_t *qtm_lib_key_group_ptr); + +/*============================================================================ +void update_qtlib_timer(uint16_t time_elapsed_since_update) +------------------------------------------------------------------------------ +Purpose: Updates local variable with time period +Input : Number of ms since last update +Output : none +Notes : none +============================================================================*/ +void qtm_update_qtlib_timer(uint16_t time_elapsed_since_update); + +/*============================================================================ +uint16_t qtm_get_touch_keys_module_id(void) +------------------------------------------------------------------------------ +Purpose: Returns the module ID +Input : none +Output : Module ID +Notes : none +============================================================================*/ +uint16_t qtm_get_touch_keys_module_id(void); + +/*============================================================================ +uint8_t qtm_get_touch_keys_module_ver(void) +------------------------------------------------------------------------------ +Purpose: Returns the module Firmware version +Input : none +Output : Module ID - Upper nibble major / Lower nibble minor +Notes : none +============================================================================*/ +uint8_t qtm_get_touch_keys_module_ver(void); + +#endif /* TOUCH_API_PTC_H */ diff --git a/firmware/src/config/mcal/touch/touch.c b/firmware/src/config/mcal/touch/touch.c new file mode 100644 index 0000000..23fce1f --- /dev/null +++ b/firmware/src/config/mcal/touch/touch.c @@ -0,0 +1,485 @@ +/******************************************************************************* + Touch Library v3.12.1 Release + + Company: + Microchip Technology Inc. + + File Name: + touch.c + + Summary: + QTouch Modular Library + + Description: + Provides Initialization, Processing and ISR handler of touch library, + Simple API functions to get/set the key touch parameters from/to the + touch library data structures +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) 2022 released Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + + +/*---------------------------------------------------------------------------- + * include files + *----------------------------------------------------------------------------*/ +#include "definitions.h" +#include "touch/touch.h" + +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ + +/*! \brief configure keys, wheels and sliders. + */ +static touch_ret_t touch_sensors_config(void); + +/*! \brief Touch measure complete callback function example prototype. + */ +static void qtm_measure_complete_callback(void); + +/*! \brief Touch Error callback function prototype. + */ +static void qtm_error_callback(uint8_t error); + + +/*---------------------------------------------------------------------------- + * Global Variables + *----------------------------------------------------------------------------*/ + +/* Flag to indicate time for touch measurement */ +volatile uint8_t time_to_measure_touch_var = 0; +/* post-process request flag */ +volatile uint8_t touch_postprocess_request = 0; + +/* Measurement Done Touch Flag */ +volatile uint8_t measurement_done_touch = 0; + +volatile uint8_t k_voice_touch_Sts = 0,k_menu_touch_Sts=0,k_vol_touch_Sts=0; +/* Error Handling */ +uint8_t module_error_code = 0; + + + +/* Acquisition module internal data - Size to largest acquisition set */ +uint16_t touch_acq_signals_raw[DEF_NUM_CHANNELS]; +/* Acquisition set 1 - General settings */ +qtm_acq_node_group_config_t ptc_qtlib_acq_gen1 + = {DEF_NUM_CHANNELS, DEF_SENSOR_TYPE, DEF_PTC_CAL_AUTO_TUNE, DEF_SEL_FREQ_INIT, DEF_PTC_INTERRUPT_PRIORITY}; + +/* Node status, signal, calibration values */ +qtm_acq_node_data_t ptc_qtlib_node_stat1[DEF_NUM_CHANNELS]; + +/* Node configurations */ +qtm_acq_same51_node_config_t ptc_seq_node_cfg1[DEF_NUM_CHANNELS] = {NODE_0_PARAMS,NODE_1_PARAMS,NODE_2_PARAMS,NODE_3_PARAMS,NODE_4_PARAMS,NODE_5_PARAMS,NODE_6_PARAMS,NODE_7_PARAMS,NODE_8_PARAMS,NODE_9_PARAMS,NODE_10_PARAMS,NODE_11_PARAMS,NODE_12_PARAMS,NODE_13_PARAMS,NODE_14_PARAMS}; + +/* Container */ +qtm_acquisition_control_t qtlib_acq_set1 = {&ptc_qtlib_acq_gen1, &ptc_seq_node_cfg1[0], &ptc_qtlib_node_stat1[0]}; + +/**********************************************************/ +/*********** Frequency Hop Module **********************/ +/**********************************************************/ + +/* Buffer used with various noise filtering functions */ +uint16_t noise_filter_buffer[DEF_NUM_CHANNELS * NUM_FREQ_STEPS]; +uint8_t freq_hop_delay_selection[NUM_FREQ_STEPS] = {DEF_MEDIAN_FILTER_FREQUENCIES}; + +/* Configuration */ +qtm_freq_hop_config_t qtm_freq_hop_config1 = { + DEF_NUM_CHANNELS, + NUM_FREQ_STEPS, + &ptc_qtlib_acq_gen1.freq_option_select, + &freq_hop_delay_selection[0], +}; + +/* Data */ +qtm_freq_hop_data_t qtm_freq_hop_data1 = {0, 0, &noise_filter_buffer[0], &ptc_qtlib_node_stat1[0]}; + +/* Container */ +qtm_freq_hop_control_t qtm_freq_hop_control1 = {&qtm_freq_hop_data1, &qtm_freq_hop_config1}; + +/**********************************************************/ +/*********************** Keys Module **********************/ +/**********************************************************/ + +/* Keys set 1 - General settings */ +qtm_touch_key_group_config_t qtlib_key_grp_config_set1 = {DEF_NUM_SENSORS, + DEF_TOUCH_DET_INT, + DEF_MAX_ON_DURATION, + DEF_ANTI_TCH_DET_INT, + DEF_ANTI_TCH_RECAL_THRSHLD, + DEF_TCH_DRIFT_RATE, + DEF_ANTI_TCH_DRIFT_RATE, + DEF_DRIFT_HOLD_TIME, + DEF_REBURST_MODE}; + +qtm_touch_key_group_data_t qtlib_key_grp_data_set1; + +/* Key data */ +qtm_touch_key_data_t qtlib_key_data_set1[DEF_NUM_SENSORS]; + +/* Key Configurations */ +qtm_touch_key_config_t qtlib_key_configs_set1[DEF_NUM_SENSORS] = { KEY_0_PARAMS, KEY_1_PARAMS, KEY_2_PARAMS, KEY_3_PARAMS, KEY_4_PARAMS, KEY_5_PARAMS, KEY_6_PARAMS, KEY_7_PARAMS, KEY_8_PARAMS, KEY_9_PARAMS, KEY_10_PARAMS, KEY_11_PARAMS, KEY_12_PARAMS, KEY_13_PARAMS,KEY_14_PARAMS}; +/* Container */ +qtm_touch_key_control_t qtlib_key_set1 + = {&qtlib_key_grp_data_set1, &qtlib_key_grp_config_set1, &qtlib_key_data_set1[0], &qtlib_key_configs_set1[0]}; + +/**********************************************************/ +/***************** Scroller Module ********************/ +/**********************************************************/ + +/* Individual and Group Data */ +qtm_scroller_data_t qtm_scroller_data1[DEF_NUM_SCROLLERS]; +qtm_scroller_group_data_t qtm_scroller_group_data1 = {0}; + +/* Group Configuration */ +qtm_scroller_group_config_t qtm_scroller_group_config1 = {&qtlib_key_data_set1[0], DEF_NUM_SCROLLERS}; + +/* Scroller Configurations */ +qtm_scroller_config_t qtm_scroller_config1[DEF_NUM_SCROLLERS] = {SCROLLER_0_PARAMS}; + +/* Container */ +qtm_scroller_control_t qtm_scroller_control1 + = {&qtm_scroller_group_data1, &qtm_scroller_group_config1, &qtm_scroller_data1[0], &qtm_scroller_config1[0]}; +/**********************************************************/ +/***************** Surface 1t Module ********************/ +/**********************************************************/ + +qtm_surface_cs_config_t qtm_surface_cs_config1 = { + /* Config: */ + SURFACE_CS_START_KEY_H, + SURFACE_CS_NUM_KEYS_H, + SURFACE_CS_START_KEY_V, + SURFACE_CS_NUM_KEYS_V, + SURFACE_CS_RESOL_DB, + SURFACE_CS_POS_HYST, + SURFACE_CS_FILT_CFG, + SURFACE_CS_MIN_CONTACT, + &qtlib_key_data_set1[0]}; + +/* Surface Data */ +qtm_surface_contact_data_t qtm_surface_cs_data1; + +/* Container */ +qtm_surface_cs_control_t qtm_surface_cs_control1 = {&qtm_surface_cs_data1, &qtm_surface_cs_config1}; + + + +/*---------------------------------------------------------------------------- + * function definitions + *----------------------------------------------------------------------------*/ + + +/*============================================================================ +static touch_ret_t touch_sensors_config(void) +------------------------------------------------------------------------------ +Purpose: Initialization of touch key sensors +Input : none +Output : none +Notes : +============================================================================*/ +/* Touch sensors config - assign nodes to buttons / wheels / sliders / surfaces / water level / etc */ +static touch_ret_t touch_sensors_config(void) +{ + uint16_t sensor_nodes; + touch_ret_t touch_ret = TOUCH_SUCCESS; + + /* Init acquisition module */ + qtm_ptc_init_acquisition_module(&qtlib_acq_set1); + qtm_ptc_qtlib_assign_signal_memory(&touch_acq_signals_raw[0]); + + /* Initialize sensor nodes */ + for (sensor_nodes = 0u; sensor_nodes < DEF_NUM_CHANNELS; sensor_nodes++) { + /* Enable each node for measurement and mark for calibration */ + qtm_enable_sensor_node(&qtlib_acq_set1, sensor_nodes); + qtm_calibrate_sensor_node(&qtlib_acq_set1, sensor_nodes); + } + + + /* Enable sensor keys and assign nodes */ + for (sensor_nodes = 0u; sensor_nodes < DEF_NUM_SENSORS; sensor_nodes++) { + qtm_init_sensor_key(&qtlib_key_set1, sensor_nodes, &ptc_qtlib_node_stat1[sensor_nodes]); + } + + /* scroller init */ + touch_ret |= qtm_init_scroller_module(&qtm_scroller_control1); + + touch_ret |= qtm_init_surface_cs(&qtm_surface_cs_control1); + + return (touch_ret); +} + +/*============================================================================ +static void qtm_measure_complete_callback( void ) +------------------------------------------------------------------------------ +Purpose: Callback function called after the completion of + measurement cycle. This function sets the post processing request + flag to trigger the post processing. +Input : none +Output : none +Notes : +============================================================================*/ +static void qtm_measure_complete_callback(void) +{ + touch_postprocess_request = 1u; +} + +/*============================================================================ +static void qtm_error_callback(uint8_t error) +------------------------------------------------------------------------------ +Purpose: Callback function called after the completion of + post processing. This function is called only when there is error. +Input : error code +Output : decoded module error code +Notes : +Derived Module_error_codes: + Acquisition module error =1 + post processing module1 error = 2 + post processing module2 error = 3 + ... and so on + +============================================================================*/ +static void qtm_error_callback(uint8_t error) +{ + module_error_code = error + 1u; + +} + +/*============================================================================ +void touch_init(void) +------------------------------------------------------------------------------ +Purpose: Initialization of touch library. PTC, timer, and + datastreamer modules are initialized in this function. +Input : none +Output : none +Notes : +============================================================================*/ +void touch_init(void) +{ + touch_timer_config(); + + /* Configure touch sensors with Application specific settings */ + touch_sensors_config(); + + + +} + +/*============================================================================ +void touch_process(void) +------------------------------------------------------------------------------ +Purpose: Main processing function of touch library. This function initiates the + acquisition, calls post processing after the acquistion complete and + sets the flag for next measurement based on the sensor status. +Input : none +Output : none +Notes : +============================================================================*/ +void touch_process(void) +{ + touch_ret_t touch_ret; + + /* check the time_to_measure_touch for Touch Acquisition */ + if (time_to_measure_touch_var == 1u) { + + /* Do the acquisition */ + touch_ret = qtm_ptc_start_measurement_seq(&qtlib_acq_set1, qtm_measure_complete_callback); + + /* if the Acquistion request was successful then clear the request flag */ + if (TOUCH_SUCCESS == touch_ret) { + /* Clear the Measure request flag */ + time_to_measure_touch_var = 0; + } + } + /* check the flag for node level post processing */ + if (touch_postprocess_request == 1u){ + /* Reset the flags for node_level_post_processing */ + touch_postprocess_request = 0u; + /* Run Acquisition module level post processing*/ + touch_ret = qtm_acquisition_process(); + /* Check the return value */ + if (TOUCH_SUCCESS == touch_ret) { + /* Returned with success: Start module level post processing */ + touch_ret = qtm_freq_hop(&qtm_freq_hop_control1); + if (TOUCH_SUCCESS != touch_ret) { + qtm_error_callback(1); + } + touch_ret = qtm_key_sensors_process(&qtlib_key_set1); + if (TOUCH_SUCCESS != touch_ret) { + qtm_error_callback(2); + } + touch_ret = qtm_scroller_process(&qtm_scroller_control1); + if (TOUCH_SUCCESS != touch_ret) { + qtm_error_callback(3); + } + touch_ret = qtm_surface_cs_process(&qtm_surface_cs_control1); + if (TOUCH_SUCCESS != touch_ret) { + qtm_error_callback(4); + } + }else { + /* Acq module Error Detected: Issue an Acq module common error code 0x80 */ + qtm_error_callback(0); + } + + + + if (0u != (qtlib_key_set1.qtm_touch_key_group_data->qtm_keys_status & QTM_KEY_REBURST)) { + time_to_measure_touch_var = 1u; + } else { + measurement_done_touch =1u; + } + } + +} +uint8_t interrupt_cnt; +uint8_t touch_gesture_time_cnt; + +/*============================================================================ +void touch_timer_handler(void) +------------------------------------------------------------------------------ +Purpose: This function updates the time elapsed to the touch key module to + synchronize the internal time counts used by the module. +Input : none +Output : none +Notes : +============================================================================*/ +void touch_timer_handler(void) +{ + + + time_to_measure_touch_var = 1u; + qtm_update_qtlib_timer(DEF_TOUCH_MEASUREMENT_PERIOD_MS); + } + +void rtc_cb( RTC_TIMER32_INT_MASK intCause, uintptr_t context ) +{ + touch_timer_handler(); +} +uintptr_t rtc_context; + +void touch_timer_config(void) +{ + RTC_Timer32CallbackRegister(rtc_cb, rtc_context); + + /* Wait for Synchronization after writing value to Count Register */ + RTC_Timer32Stop(); + RTC_Timer32CounterSet(0u); + + RTC_Timer32Compare0Set((uint32_t) DEF_TOUCH_MEASUREMENT_PERIOD_MS); + RTC_Timer32Start(); +} + +uint16_t get_sensor_node_signal(uint16_t sensor_node) +{ + return (ptc_qtlib_node_stat1[sensor_node].node_acq_signals); +} + +void update_sensor_node_signal(uint16_t sensor_node, uint16_t new_signal) +{ + ptc_qtlib_node_stat1[sensor_node].node_acq_signals = new_signal; +} + +uint16_t get_sensor_node_reference(uint16_t sensor_node) +{ + return (qtlib_key_data_set1[sensor_node].channel_reference); +} + +void update_sensor_node_reference(uint16_t sensor_node, uint16_t new_reference) +{ + qtlib_key_data_set1[sensor_node].channel_reference = new_reference; +} + +uint16_t get_sensor_cc_val(uint16_t sensor_node) +{ + return (ptc_qtlib_node_stat1[sensor_node].node_comp_caps); +} + +void update_sensor_cc_val(uint16_t sensor_node, uint16_t new_cc_value) +{ + ptc_qtlib_node_stat1[sensor_node].node_comp_caps = new_cc_value; +} + +uint8_t get_sensor_state(uint16_t sensor_node) +{ + return (qtlib_key_set1.qtm_touch_key_data[sensor_node].sensor_state); +} + +void update_sensor_state(uint16_t sensor_node, uint8_t new_state) +{ + qtlib_key_set1.qtm_touch_key_data[sensor_node].sensor_state = new_state; +} + +void calibrate_node(uint16_t sensor_node) +{ + /* Calibrate Node */ + qtm_calibrate_sensor_node(&qtlib_acq_set1, sensor_node); + /* Initialize key */ + qtm_init_sensor_key(&qtlib_key_set1, sensor_node, &ptc_qtlib_node_stat1[sensor_node]); +} + +uint8_t get_scroller_state(uint16_t sensor_node) +{ + return (qtm_scroller_control1.qtm_scroller_data[sensor_node].scroller_status); +} + +uint16_t get_scroller_position(uint16_t sensor_node) +{ + return (qtm_scroller_control1.qtm_scroller_data[sensor_node].position); +} + +uint8_t get_surface_status(void) +{ + return (qtm_surface_cs_control1.qtm_surface_contact_data->qt_surface_status); +} + +uint8_t get_surface_position(uint8_t ver_or_hor) +{ + uint8_t temp_pos = 0; +/* +* ver_or_hor, 0 = hor, 1 = ver +*/ + if(ver_or_hor == VER_POS) + { + temp_pos = qtm_surface_cs_control1.qtm_surface_contact_data->v_position; + } + else + { + temp_pos = qtm_surface_cs_control1.qtm_surface_contact_data->h_position; + } + return temp_pos; +} + + +/*============================================================================ +void PTC_Handler_EOC(void) +------------------------------------------------------------------------------ +Purpose: Interrupt service handler for PTC EOC interrupt +Input : none +Output : none +Notes : none +============================================================================*/ +void ADC0_1_Handler(void) +{ + ADC0_REGS->ADC_INTFLAG |=1u; + qtm_same54_ptc_handler(); +} diff --git a/firmware/src/config/mcal/touch/touch.h b/firmware/src/config/mcal/touch/touch.h new file mode 100644 index 0000000..8b2cf30 --- /dev/null +++ b/firmware/src/config/mcal/touch/touch.h @@ -0,0 +1,447 @@ +/******************************************************************************* + Touch Library v3.12.1 Release + + Company: + Microchip Technology Inc. + + File Name: + touch.h + + Summary: + QTouch Modular Library + + Description: + Configuration macros for touch library + +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) 2022 released Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ +#ifndef TOUCH_H +#define TOUCH_H +#include "device.h" + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END +//SAME51 + +/*---------------------------------------------------------------------------- + * include files + *----------------------------------------------------------------------------*/ + +#include "touch_api_ptc.h" + +/**********************************************************/ +/******************* Acquisition controls *****************/ +/**********************************************************/ +/* Defines the Measurement Time in milli seconds. + * Range: 1 to 255. + * Default value: 20. + */ +#define DEF_TOUCH_MEASUREMENT_PERIOD_MS 4 + +/* Defines the Type of sensor + * Default value: NODE_MUTUAL. + */ +#define DEF_SENSOR_TYPE NODE_SELFCAP + + +/* Set sensor calibration mode for charge share delay ,Prescaler or series resistor. + * Range: CAL_AUTO_TUNE_NONE / CAL_AUTO_TUNE_RSEL / CAL_AUTO_TUNE_PRSC / CAL_AUTO_TUNE_CSD + * Default value: CAL_AUTO_TUNE_NONE. + */ + +#define DEF_PTC_CAL_OPTION CAL_AUTO_TUNE_NONE + +/* Defines the interrupt priority for the PTC. Set low priority to PTC interrupt for applications having interrupt time + * constraints. + */ +#define DEF_PTC_INTERRUPT_PRIORITY 7 + +/* Calibration option to ensure full charge transfer */ +/* Bits 7:0 = XX | TT SELECT_TAU | X | CAL_OPTION */ +#define DEF_PTC_TAU_TARGET CAL_CHRG_5TAU +#define DEF_PTC_CAL_AUTO_TUNE (uint8_t)((DEF_PTC_TAU_TARGET << CAL_CHRG_TIME_POS) | DEF_PTC_CAL_OPTION) + +/* Set default bootup acquisition frequency. + * Range: FREQ_SEL_0 - FREQ_SEL_15 , FREQ_SEL_SPREAD + * Default value: FREQ_SEL_0. + */ +#define DEF_SEL_FREQ_INIT FREQ_SEL_0 + +/*---------------------------------------------------------------------------- + * defines + *----------------------------------------------------------------------------*/ + +/**********************************************************/ +/***************** Node Params ******************/ +/**********************************************************/ +/* Acquisition Set 1 */ +/* Defines the number of sensor nodes in the acquisition set + * Range: 1 to 65535. + * Default value: 1 + */ +#define DEF_NUM_CHANNELS (15) + + +/* Defines node parameter setting + * {X-line, Y-line, Charge Share Delay, NODE_RSEL_PRSC(series resistor, prescaler), NODE_G(Analog Gain , Digital Gain), + * filter level} + */ + + +#define NODE_0_PARAMS \ +{ \ + X_NONE, Y(15), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_1_PARAMS \ +{ \ + X_NONE, Y(16), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_2_PARAMS \ +{ \ + X_NONE, Y(17), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_3_PARAMS \ +{ \ + X_NONE, Y(30), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_4_PARAMS \ +{ \ + X_NONE, Y(31), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_5_PARAMS \ +{ \ + X_NONE, Y(24), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_6_PARAMS \ +{ \ + X_NONE, Y(25), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_7_PARAMS \ +{ \ + X_NONE, Y(1), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_8_PARAMS \ +{ \ + X_NONE, Y(2), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_9_PARAMS \ +{ \ + X_NONE, Y(3), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_10_PARAMS \ +{ \ + X_NONE, Y(10), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_11_PARAMS \ +{ \ + X_NONE, Y(11), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_12_PARAMS \ +{ \ + X_NONE, Y(12), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_13_PARAMS \ +{ \ + X_NONE, Y(13), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} +#define NODE_14_PARAMS \ +{ \ + X_NONE, Y(14), 10,PRSC_DIV_SEL_8, NODE_GAIN(GAIN_1, GAIN_4), FILTER_LEVEL_64 \ +} + +/**********************************************************/ +/***************** Key Params ******************/ +/**********************************************************/ +/* Defines the number of key sensors + * Range: 1 to 65535. + * Default value: 1 + */ +#define DEF_NUM_SENSORS (15) + +/* Defines Key Sensor setting + * {Sensor Threshold, Sensor Hysterisis, Sensor AKS} + */ + +#define KEY_0_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_2 \ +} + + +#define KEY_1_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_2 \ +} + + +#define KEY_2_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_2 \ +} + + +#define KEY_3_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_2 \ +} + + +#define KEY_4_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_2 \ +} + + +#define KEY_5_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_6_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_7_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_8_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_9_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_10_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_11_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_12_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_13_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +#define KEY_14_PARAMS \ +{ \ + 50, HYST_12_5, AKS_GROUP_1 \ +} + + +/* De-bounce counter for additional measurements to confirm touch detection + * Range: 0 to 255. + * Default value: 4. + */ +#define DEF_TOUCH_DET_INT 4 + +/* De-bounce counter for additional measurements to confirm away from touch signal + * to initiate Away from touch re-calibration. + * Range: 0 to 255. + * Default value: 5. + */ +#define DEF_ANTI_TCH_DET_INT 5 + +/* Threshold beyond with automatic sensor recalibration is initiated. + * Range: RECAL_100/ RECAL_50 / RECAL_25 / RECAL_12_5 / RECAL_6_25 / MAX_RECAL + * Default value: RECAL_100. + */ +#define DEF_ANTI_TCH_RECAL_THRSHLD RECAL_50 + +/* Rate at which sensor reference value is adjusted towards sensor signal value + * when signal value is greater than reference. + * Units: 200ms + * Range: 0-255 + * Default value: 20u = 4 seconds. + */ +#define DEF_TCH_DRIFT_RATE 1 + +/* Rate at which sensor reference value is adjusted towards sensor signal value + * when signal value is less than reference. + * Units: 200ms + * Range: 0-255 + * Default value: 5u = 1 second. + */ +#define DEF_ANTI_TCH_DRIFT_RATE 5 + +/* Time to restrict drift on all sensor when one or more sensors are activated. + * Units: 200ms + * Range: 0-255 + * Default value: 20u = 4 seconds. + */ +#define DEF_DRIFT_HOLD_TIME 20 + +/* Set mode for additional sensor measurements based on touch activity. + * Range: REBURST_NONE / REBURST_UNRESOLVED / REBURST_ALL + * Default value: REBURST_UNRESOLVED + */ +#define DEF_REBURST_MODE REBURST_UNRESOLVED + +/* Sensor maximum ON duration upon touch. + * Range: 0-255 + * Default value: 0 + */ +#define DEF_MAX_ON_DURATION 0 + +/**********************************************************/ +/***************** Slider/Wheel Parameters ****************/ +/**********************************************************/ +/* Defines the number of scrollers (sliders or wheels) + */ +#define DEF_NUM_SCROLLERS 1 + +/* Defines scroller parameter setting + * {touch_scroller_type, touch_start_key, touch_scroller_size, + * SCROLLER_RESOL_DEADBAND(touch_scroller_resolution,touch_scroller_deadband), touch_scroller_hysterisis, + * touch_scr_detect_threshold} + * Configuring scr_detect_threshold: By default, scr_detect_threshold parameter should be + * set equal to threshold value of the underlying keys. Then the parameter has to be tuned based on the actual contact + * size of the touch when moved over the scroller. The contact size of the moving touch can be observed from + * "contact_size" parameter on scroller runtime data structure. + */ +#define SCROLLER_0_PARAMS \ +{ \ + SCROLLER_TYPE_SLIDER, 0, 5, \ + SCROLLER_RESOL_DEADBAND(SCR_RESOL_8_BIT, DB_NONE),8,20\ +} + +/**********************************************************/ +/***************** Surface Parameters ****************/ +/**********************************************************/ + +/* Horizontal Start Key <0-65534> + * Start key of horizontal axis + * Range: 0 to 65534 + */ +#define SURFACE_CS_START_KEY_H 10 +/* Horizontal Number of Channel <0-255> + * Number of Channels forming horizontal axis + * Range: 0 to 255 + */ +#define SURFACE_CS_NUM_KEYS_H 5 +/* Vertical Start Key <0-65534> + * Start key of vertical axis + * Range: 0 to 65534 + */ +#define SURFACE_CS_START_KEY_V 5 +/* Vertical Number of Channel <0-255> + * Number of Channels forming vertical axis + * Range: 0 to 255 + */ +#define SURFACE_CS_NUM_KEYS_V 5 +/* Position Resolution and Deadband Percentage + * Full scale position resolution reported for the axis and the deadband Percentage + * RESOL_2_BIT - RESOL_12_BIT + * DB_NONE - DB_15_PERCENT + */ +#define SURFACE_CS_RESOL_DB SCR_RESOL_DEADBAND(RESOL_8_BIT, DB_1_PERCENT) +/* Median filter enable and IIR filter Config + * Median Filter <0-1> + * Enable or Disable Median Filter + * enable - 1 + * disable - 0 + * IIR filter <0-3> + * Configure IIR filter + * 0 - None + * 1 - 25% + * 2 - 50% + * 3 - 75% + */ +#define SURFACE_CS_FILT_CFG SCR_MEDIAN_IIR(1, 3) +/* Position Hystersis <0-255> + * The minimum travel distance to be reported after contact or direction change + * Applicable to Horizontal and Vertical directions + */ +#define SURFACE_CS_POS_HYST 3 +/* Minimum Contact <0-65534> + * The minimum contact size measurement for persistent contact tracking. + * Contact size is the sum of neighbouring keys' touch deltas forming the touch contact. + */ +#define SURFACE_CS_MIN_CONTACT 60 + + +/**********************************************************/ +/********* Frequency Hop Module ****************/ +/**********************************************************/ + +/* sets the frequency steps for hop. + * Range: 3 to 7. + * Default value: 3 + */ +#define NUM_FREQ_STEPS 3 + +/* PTC Sampling Delay Selection - 0 to 15 PTC CLK cycles */ + +#define DEF_MEDIAN_FILTER_FREQUENCIES FREQ_SEL_0,FREQ_SEL_1,FREQ_SEL_2 + + +/**********************************************************/ +/***************** Communication - Data Streamer ******************/ +/**********************************************************/ +#define DEF_TOUCH_DATA_STREAMER_ENABLE 0u + + + +/**********************************************************/ + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END +#endif // TOUCH_H diff --git a/firmware/src/config/mcal/touch/touch_api_ptc.h b/firmware/src/config/mcal/touch/touch_api_ptc.h new file mode 100644 index 0000000..308143d --- /dev/null +++ b/firmware/src/config/mcal/touch/touch_api_ptc.h @@ -0,0 +1,89 @@ + +/******************************************************************************* + Touch Library v3.12.1 Release + + Company: + Microchip Technology Inc. + + File Name: + touch_api_ptc.h + + Summary: + QTouch Modular Library + + Description: + Includes the Module API header files based on the configured modules, + prototypes for touch.c file and Application helper API functions +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) 2022 released Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + +#ifndef TOUCH_API_PTC_H +#define TOUCH_API_PTC_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * include files + *----------------------------------------------------------------------------*/ + +#include "qtm_common_components_api.h" +#include "qtm_acq_same51_0x000f_api.h" +#include "qtm_touch_key_0x0002_api.h" +#include "qtm_freq_hop_0x0006_api.h" +#include "qtm_scroller_0x000b_api.h" +#include "qtm_surface_cs_0x0021_api.h" +/*---------------------------------------------------------------------------- + * prototypes + *----------------------------------------------------------------------------*/ +/* Application Helper API's */ +uint16_t get_sensor_node_signal(uint16_t sensor_node); +void update_sensor_node_signal(uint16_t sensor_node, uint16_t new_signal); +uint16_t get_sensor_node_reference(uint16_t sensor_node); +void update_sensor_node_reference(uint16_t sensor_node, uint16_t new_reference); +uint16_t get_sensor_cc_val(uint16_t sensor_node); +void update_sensor_cc_val(uint16_t sensor_node, uint16_t new_cc_value); +uint8_t get_sensor_state(uint16_t sensor_node); +void update_sensor_state(uint16_t sensor_node, uint8_t new_state); +void calibrate_node(uint16_t sensor_node); +uint8_t get_scroller_state(uint16_t sensor_node); +uint16_t get_scroller_position(uint16_t sensor_node); +#define HOR_POS 0u +#define VER_POS 1u +uint8_t get_surface_status(void); +uint8_t get_surface_position(uint8_t ver_or_hor); + +void touch_timer_handler(void); +void touch_init(void); +void touch_process(void); + +void touch_timer_config(void); + +#ifdef __cplusplus +} +#endif + +#endif /* TOUCH_API_PTC_H */ diff --git a/firmware/src/config/mcal/touch/touch_example.c b/firmware/src/config/mcal/touch/touch_example.c new file mode 100644 index 0000000..717a355 --- /dev/null +++ b/firmware/src/config/mcal/touch/touch_example.c @@ -0,0 +1,189 @@ +/******************************************************************************* + Touch Library v3.12.1 Release + + Company: + Microchip Technology Inc. + + File Name: + touch_example.c + + Summary: + QTouch Modular Library + + Description: + Provides Initialization, Processing and ISR handler of touch library, + Simple API functions to get/set the key touch parameters from/to the + touch library data structures +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) 2022 released Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + + +#include "touch_example.h" + +void touch_mainloop_example(void){ + + /* call touch process function */ + touch_process(); + + if(measurement_done_touch == 1) + { + measurement_done_touch = 0; + // process touch data + } + +} + +/*============================================================================ +void touch_status_display(void) +------------------------------------------------------------------------------ +Purpose: Sample code snippet to demonstrate how to check the status of the + sensors +Input : none +Output : none +Notes : none +============================================================================*/ +bool CAP_TJP_SNS[2]; +bool CAP_RES_SNS[2]; +bool CAP_CANCEL_SNS[2]; + +void touch_status_display(void) +{ +uint8_t key_status = 0u; + key_status = get_sensor_state(0) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_TJP_SNS[0] = true; + } else { + CAP_TJP_SNS[0] = false; + } + + key_status = get_sensor_state(1) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_TJP_SNS[1] = true; + } else { + CAP_TJP_SNS[1] = false; + } + + key_status = get_sensor_state(2) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_RES_SNS[0] = true; + } else { + CAP_RES_SNS[0] = false; + } + + key_status = get_sensor_state(3) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_RES_SNS[1] = true; + } else { + CAP_RES_SNS[1] = false; + } + + key_status = get_sensor_state(4) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_CANCEL_SNS[0] = true; + } else { + CAP_CANCEL_SNS[0] = false; + } + + key_status = get_sensor_state(5) & KEY_TOUCHED_MASK; + if (0u != key_status) { + CAP_CANCEL_SNS[1] = true; + } else { + CAP_CANCEL_SNS[1] = false; + } + + key_status = get_sensor_state(6) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(7) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(8) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(9) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(10) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(11) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(12) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(13) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(14) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + key_status = get_sensor_state(15) & KEY_TOUCHED_MASK; + if (0u != key_status) { + //Touch detect + } else { + //Touch No detect + } + + +} + + diff --git a/firmware/src/config/mcal/touch/touch_example.h b/firmware/src/config/mcal/touch/touch_example.h new file mode 100644 index 0000000..7634062 --- /dev/null +++ b/firmware/src/config/mcal/touch/touch_example.h @@ -0,0 +1,54 @@ +/******************************************************************************* + Touch Library v3.12.1 Release + + Company: + Microchip Technology Inc. + + File Name: + touch_example.h + + Summary: + QTouch Modular Library + + Description: + Provides Initialization, Processing and ISR handler of touch library, + Simple API functions to get/set the key touch parameters from/to the + touch library data structures +*******************************************************************************/ + +/******************************************************************************* +Copyright (c) 2022 released Microchip Technology Inc. All rights reserved. + +Microchip licenses to you the right to use, modify, copy and distribute +Software only when embedded on a Microchip microcontroller or digital signal +controller that is integrated into your product or third party product +(pursuant to the sublicense terms in the accompanying license agreement). + +You should refer to the license agreement accompanying this Software for +additional information regarding your rights and obligations. + +SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF +MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. +IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER +CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR +OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES +INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR +CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF +SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES +(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. +*******************************************************************************/ + + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "touch.h" + + + +extern volatile uint8_t measurement_done_touch; + +void touch_mainloop_example(void); +void touch_status_display(void); diff --git a/firmware/src/forceSnsr/forceSnsr.c b/firmware/src/forceSnsr/forceSnsr.c new file mode 100644 index 0000000..ad77217 --- /dev/null +++ b/firmware/src/forceSnsr/forceSnsr.c @@ -0,0 +1,586 @@ +#include "forceSnsr.h" +#include "forceSnsr_Cfg.h" +#include + + + +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + + +/***************************************************************/ + +extern forcesnsr_RxReg_un_type forcesnsr_reg_state_un_bak; +extern forcesnsr_RxReg_un_type forcesnsr_reg_state_un; + + +forcesnsrMain_State_e forcesnsr_mainctrl_status[forcesnsrMax_CH ]; +forcesnsrMain_State_e forcesnsr_lastmainctrl_status[forcesnsrMax_CH ]; +STATE_UINT8 forcesnsr_data_tbl[32]; +STATE_UINT8 forcesnsr_i2c_process_state_u8; +forcesnsr_RxReg_un_type forcesnsr_reg_state_grp; + + uint8_t force_button_state_u8 = 0; + +/***************************************************************/ + + +/***************************static function statement begin************************************/ +static void forcesnsr_I2c_End_Callback(uintptr_t contextHandle); +static STATE_UINT8 forcesnsr_I2c_send(STATE_UINT8 regid,STATE_UINT8 len,STATE_UINT8 * data); +static STATE_UINT8 forcesnsr_I2c_recive(STATE_UINT8 regid,STATE_UINT8 len,STATE_UINT8 * data); +static void forcesnsr_I2c_init(void); +static STATE_UINT8 forcesnsr_id_I2c_send(STATE_UINT8 index); +static STATE_UINT8 forcesnsr_id_I2c_recive(STATE_UINT8 index); +static STATE_UINT8 Get_Reg_Ckc_is_Ok(void); + + +static forcesnsrMain_State_e forcesnsr_handle_entry_init(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_during_init(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_exit_init(STATE_UINT8 channel); + + +static forcesnsrMain_State_e forcesnsr_handle_entry_state1(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_during_state1(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_exit_state1(STATE_UINT8 channel); + + +static forcesnsrMain_State_e forcesnsr_handle_entry_state2(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_during_state2(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_exit_state2(STATE_UINT8 channel); + + +static forcesnsrMain_State_e forcesnsr_handle_entry_state3(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_during_state3(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_exit_state3(STATE_UINT8 channel); + + +static forcesnsrMain_State_e forcesnsr_handle_entry_state4(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_during_state4(STATE_UINT8 channel); +static forcesnsrMain_State_e forcesnsr_handle_exit_state4(STATE_UINT8 channel); + + +/***************************static function statement end ************************************/ + + + + +/***************************table begin************************************/ +const forcesnsrState_Handle_Ptr forcesnsr_handle_func_tbl[5][3] = +{ + {(forcesnsrState_Handle_Ptr) forcesnsr_handle_entry_init, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_during_init, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_exit_init}, + + {(forcesnsrState_Handle_Ptr) forcesnsr_handle_entry_state1, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_during_state1, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_exit_state1}, + + {(forcesnsrState_Handle_Ptr) forcesnsr_handle_entry_state2, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_during_state2, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_exit_state2}, + + {(forcesnsrState_Handle_Ptr) forcesnsr_handle_entry_state3, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_during_state3, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_exit_state3}, + + {(forcesnsrState_Handle_Ptr) forcesnsr_handle_entry_state4, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_during_state4, + (forcesnsrState_Handle_Ptr) forcesnsr_handle_exit_state4} +}; + +/***************************table end ************************************/ + + + + +/***************************static function define begin************************************/ + + + +/***************************init_entry***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_entry_init(STATE_UINT8 channel) +{ +/*please fill your code*/ + return init_STATE_E_0; +} + + +/***************************init_during***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_during_init(STATE_UINT8 channel) +{ +/*please fill your code*/ + STATE_UINT8 ret = FALSE; + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_NOT_PROCESS) + { + ret = forcesnsr_id_I2c_send(forcesnsr_REG_ID_MAIN_CFG_INDEX); + if(ret == TRUE) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESSING; + } + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_FAIL) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_SUCESS) + { + return state1_STATE_E_1; + } + + return init_STATE_E_0; +} + + +/***************************init_exit***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_exit_init(STATE_UINT8 channel) +{ +/*please fill your code*/ + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + return init_STATE_E_0; +} + + +/***************************state1_entry***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_entry_state1(STATE_UINT8 channel) +{ +/*please fill your code*/ + + return init_STATE_E_0; +} + + +/***************************state1_during***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_during_state1(STATE_UINT8 channel) +{ +/*please fill your code*/ + STATE_UINT8 ret = FALSE; + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_NOT_PROCESS) + { + ret = forcesnsr_id_I2c_send(forcesnsr_REG_ID_CAL_BASELINE_INT_CFG_INDEX); + if(ret == TRUE) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESSING; + } + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_FAIL) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_SUCESS) + { + return state2_STATE_E_2; + } + + return state1_STATE_E_1; +} + + +/***************************state1_exit***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_exit_state1(STATE_UINT8 channel) +{ +/*please fill your code*/ + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + return init_STATE_E_0; +} + + +/***************************state2_entry***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_entry_state2(STATE_UINT8 channel) +{ +/*please fill your code*/ + return init_STATE_E_0; +} + + +/***************************state2_during***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_during_state2(STATE_UINT8 channel) +{ +/*please fill your code*/ + STATE_UINT8 ret = FALSE; + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_NOT_PROCESS) + { + ret = forcesnsr_id_I2c_send(forcesnsr_REG_ID_FALLING_CFG_INDEX); + if(ret == TRUE) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESSING; + } + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_FAIL) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_SUCESS) + { + return state3_STATE_E_3; + } + + return state2_STATE_E_2; +} + + +/***************************state2_exit***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_exit_state2(STATE_UINT8 channel) +{ +/*please fill your code*/ + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + return init_STATE_E_0; +} + + +/***************************state3_entry***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_entry_state3(STATE_UINT8 channel) +{ +/*please fill your code*/ + return init_STATE_E_0; +} + + +/***************************state3_during***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_during_state3(STATE_UINT8 channel) +{ +/*please fill your code*/ + STATE_UINT8 ret = FALSE; + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_NOT_PROCESS) + { + ret = forcesnsr_id_I2c_recive(forcesnsr_REG_ID_AD_TEMP_INDEX); + if(ret == TRUE) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESSING; + } + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_FAIL) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_SUCESS) + { + memcpy(&forcesnsr_reg_state_un_bak,&forcesnsr_reg_state_un,sizeof(forcesnsr_reg_state_un_bak)); + return state4_STATE_E_4; + } + return state3_STATE_E_3; +} + + +/***************************state3_exit***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_exit_state3(STATE_UINT8 channel) +{ +/*please fill your code*/ + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + return init_STATE_E_0; +} + + +/***************************state4_entry***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_entry_state4(STATE_UINT8 channel) +{ +/*please fill your code*/ + return init_STATE_E_0; +} + + +/***************************state4_during***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_during_state4(STATE_UINT8 channel) +{ +/*please fill your code*/ + STATE_UINT8 ret = FALSE; + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_NOT_PROCESS) + { + ret = forcesnsr_id_I2c_recive(forcesnsr_REG_ID_BASELINE_INDEX); + if(ret == TRUE) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESSING; + } + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_FAIL) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + } + + if(forcesnsr_i2c_process_state_u8 == forcesnsr_CALLBACK_PROCESS_SUCESS) + { + memcpy(&forcesnsr_reg_state_un_bak,&forcesnsr_reg_state_un,sizeof(forcesnsr_reg_state_un_bak)); + if(TRUE == Get_Reg_Ckc_is_Ok()) + { + return state3_STATE_E_3; + } + else + { + return init_STATE_E_0; + } + } + + return state4_STATE_E_4; +} + + +/***************************state4_exit***********************************/ +static forcesnsrMain_State_e forcesnsr_handle_exit_state4(STATE_UINT8 channel) +{ +/*please fill your code*/ + + return init_STATE_E_0; +} + + + + +/***************************static function define end ************************************/ + + + + +/***************************init function define begin************************************/ +void forcesnsr_Init(void) +{ + STATE_UINT32 fl_index_u32 = 0; + + for(fl_index_u32 = 0 ; fl_index_u32 < forcesnsrMax_CH ; fl_index_u32++) + { + forcesnsr_mainctrl_status[fl_index_u32]=init_STATE_E_0; + forcesnsr_lastmainctrl_status[fl_index_u32]=init_STATE_E_0; + } + + forcesnsr_I2c_init(); +} +/***************************init function define end ************************************/ + + + + +/***************************main function define begin************************************/ +void forcesnsr_MainTask(void) +{ + STATE_UINT32 fl_index_u32 = 0; + + for(fl_index_u32 = 0 ; fl_index_u32 < forcesnsrMax_CH ; fl_index_u32++) + { + + if(forcesnsr_mainctrl_status[fl_index_u32] <= state4_STATE_E_4) + { + forcesnsr_mainctrl_status[fl_index_u32]=forcesnsr_handle_func_tbl[forcesnsr_mainctrl_status[fl_index_u32]][1](fl_index_u32); + } + else + { + forcesnsr_mainctrl_status[fl_index_u32]=init_STATE_E_0; + } + + + if(forcesnsr_mainctrl_status[fl_index_u32] <= state4_STATE_E_4) + { + if(forcesnsr_lastmainctrl_status[fl_index_u32] != forcesnsr_mainctrl_status[fl_index_u32]) + { + (void)forcesnsr_handle_func_tbl[forcesnsr_lastmainctrl_status[fl_index_u32]][2](fl_index_u32); + } + } + else + { + forcesnsr_mainctrl_status[fl_index_u32]=init_STATE_E_0; + } + + + if(forcesnsr_mainctrl_status[fl_index_u32] <= state4_STATE_E_4) + { + if(forcesnsr_lastmainctrl_status[fl_index_u32] != forcesnsr_mainctrl_status[fl_index_u32]) + { + (void)forcesnsr_handle_func_tbl[forcesnsr_mainctrl_status[fl_index_u32]][0](fl_index_u32); + } + } + else + { + forcesnsr_mainctrl_status[fl_index_u32]=init_STATE_E_0; + } + forcesnsr_lastmainctrl_status[fl_index_u32]=forcesnsr_mainctrl_status[fl_index_u32]; + } + + +} +/***************************main function define end ************************************/ + + +/* +i2c initial +*/ + +static void forcesnsr_I2c_init(void) +{ + PORT_PinPeripheralFunctionConfig(PORT_PIN_PA00,PERIPHERAL_FUNCTION_D); + PORT_PinPeripheralFunctionConfig(PORT_PIN_PA01,PERIPHERAL_FUNCTION_D); + + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_NOT_PROCESS; + + SERCOM1_I2C_Initialize(); + SERCOM1_I2C_CallbackRegister(forcesnsr_I2c_End_Callback,0); +} + + +/* +i2c rx or tx process sucess callback +*/ + +static void forcesnsr_I2c_End_Callback(uintptr_t contextHandle) +{ + + if(SERCOM_I2C_ERROR_NONE == SERCOM1_I2C_ErrorGet()) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESS_SUCESS; + } + else if((SERCOM1_I2C_send_done()) && (SERCOM_I2C_ERROR_NAK == SERCOM1_I2C_ErrorGet())) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESS_SUCESS; + } + else if((SERCOM1_I2C_rx_done()) && (SERCOM_I2C_ERROR_NAK == SERCOM1_I2C_ErrorGet())) + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESS_SUCESS; + } + else + { + forcesnsr_i2c_process_state_u8 = forcesnsr_CALLBACK_PROCESS_FAIL; + } + + + SERCOM1_I2C_Initialize(); +} + + +/* +i2c tx process ,ansync process +*/ +static STATE_UINT8 forcesnsr_I2c_send(STATE_UINT8 regid,STATE_UINT8 len,STATE_UINT8 * data) +{ + STATE_UINT8 index = 0; + STATE_UINT8 num = 0; + STATE_UINT8 ret = 0; + + if(len > sizeof(forcesnsr_data_tbl)) + { + return FALSE; + } + + forcesnsr_data_tbl[index++] = regid; + + if(len < ((sizeof(forcesnsr_data_tbl))/(sizeof(forcesnsr_data_tbl[0])) - 3)) + { + for(num = 0 ; num < len ; num ++) + { + forcesnsr_data_tbl[index++] = data[num]; + } + + /*i2c send interface*/ + ret = SERCOM1_I2C_Write(forcesnsr_BIT7_ADDR,forcesnsr_data_tbl,index); + } + + return ret; +} + +static STATE_UINT8 forcesnsr_id_I2c_send(STATE_UINT8 index) +{ + STATE_UINT8 ret = FALSE; + + ret = forcesnsr_I2c_send(forcesnsr_Main_Cfg_Tbl[index].cmd_id,\ + forcesnsr_Main_Cfg_Tbl[index].cmd_len,\ + (STATE_UINT8 *)forcesnsr_Main_Cfg_Tbl[index].default_state); + + return ret; +} + + +/* +i2c rx process ,ansync process +*/ +static STATE_UINT8 forcesnsr_I2c_recive(STATE_UINT8 regid,STATE_UINT8 len,STATE_UINT8 * data) +{ + STATE_UINT8 ret = FALSE; + forcesnsr_data_tbl[0] = regid; + + if((len + regid <= forcesnsr_Max_reg_num) && (data != 0)) + { + /*i2c send and recive interface*/ + ret = SERCOM1_I2C_WriteRead(forcesnsr_BIT7_ADDR,forcesnsr_data_tbl,1,data,len); + } + + return ret; +} + +static STATE_UINT8 forcesnsr_id_I2c_recive(STATE_UINT8 index) +{ + STATE_UINT8 ret = FALSE; + + ret = forcesnsr_I2c_recive(forcesnsr_Main_Cfg_Tbl[index].cmd_id,\ + forcesnsr_Main_Cfg_Tbl[index].cmd_len,\ + (STATE_UINT8 *)forcesnsr_Main_Cfg_Tbl[index].cmd_data); + + return ret; +} + +/* +return: ture is button pressed +*/ +STATE_UINT8 Get_force_btn_is_press_state(void) +{ + if(FALSE == PORT_PinRead(PORT_PIN_PB31)) + { + force_button_state_u8 = TRUE; + } + else + { + force_button_state_u8 = FALSE; + } + + return force_button_state_u8; +} + +/* +compare key register value +return true is force sensor chip register value match with expect +*/ +STATE_UINT8 Get_Reg_Ckc_is_Ok(void) +{ + STATE_UINT8 ret = TRUE; + + if(forcesnsr_reg_state_un_bak.reg_grp[0] != forcesnsr_Main_Cfg_Tbl[0].default_state[0]) + { + ret = FALSE; + } + if(forcesnsr_reg_state_un_bak.reg_grp[1] != forcesnsr_Main_Cfg_Tbl[0].default_state[1]) + { + ret = FALSE; + } + if(forcesnsr_reg_state_un_bak.reg_grp[0xE] != forcesnsr_Main_Cfg_Tbl[1].default_state[7]) + { + ret = FALSE; + } + if(forcesnsr_reg_state_un_bak.reg_grp[0x09] != forcesnsr_Main_Cfg_Tbl[1].default_state[2]) + { + ret = FALSE; + } + if(forcesnsr_reg_state_un_bak.reg_grp[0x0A] != forcesnsr_Main_Cfg_Tbl[1].default_state[3]) + { + ret = FALSE; + } + if(forcesnsr_reg_state_un_bak.reg_grp[0x0B] != forcesnsr_Main_Cfg_Tbl[1].default_state[4]) + { + ret = FALSE; + } + return ret; +} + + + diff --git a/firmware/src/forceSnsr/forceSnsr.h b/firmware/src/forceSnsr/forceSnsr.h new file mode 100644 index 0000000..bf957ae --- /dev/null +++ b/firmware/src/forceSnsr/forceSnsr.h @@ -0,0 +1,68 @@ +#ifndef __forcesnsr_H__ +#define __forcesnsr_H__ +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + +#ifndef TRUE +#define TRUE true +#endif + +#ifndef FALSE +#define FALSE false +#endif + + + +typedef enum +{ + forcesnsr_CALLBACK_PROCESS_SUCESS = 0x00, + forcesnsr_CALLBACK_PROCESS_FAIL , + forcesnsr_CALLBACK_PROCESSING , + forcesnsr_CALLBACK_NOT_PROCESS , + +}forcesnsr_callback_process_state_e_typ; + + + +#define forcesnsrMax_CH 1 + + +/***************************datatype define begin************************************/ +#define STATE_UINT8 unsigned char +#define STATE_SINT8 char +#define STATE_UINT16 unsigned short +#define STATE_SINT16 short +#define STATE_UINT32 unsigned int +#define STATE_SINT32 int +/***************************datatype define end************************************/ + +extern STATE_UINT8 forcesnsr_i2c_process_state_u8; + + +/***************************enum define begin************************************/ +typedef enum{ + init_STATE_E_0, + state1_STATE_E_1, + state2_STATE_E_2, + state3_STATE_E_3, + state4_STATE_E_4, +}forcesnsrMain_State_e; +/***************************enum define end************************************/ + + +/*****************************main control function begin**********************************/ +typedef forcesnsrMain_State_e ( * forcesnsrState_Handle_Ptr)(STATE_UINT8 channel); +/*********************************main control function end*******************************/ + + +/***************************extern function begin************************************/ +extern void forcesnsr_Init(void); +extern void forcesnsr_MainTask(void); +extern STATE_UINT8 Get_force_btn_is_press_state(void); +/***************************extern function end************************************/ + + +#endif diff --git a/firmware/src/forceSnsr/forceSnsr_Cfg.c b/firmware/src/forceSnsr/forceSnsr_Cfg.c new file mode 100644 index 0000000..e1140b6 --- /dev/null +++ b/firmware/src/forceSnsr/forceSnsr_Cfg.c @@ -0,0 +1,62 @@ +#include "forceSnsr_Cfg.h" +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + + +forcesnsr_RxReg_un_type forcesnsr_reg_state_un; +forcesnsr_RxReg_un_type forcesnsr_reg_state_un_bak; + +/* +forcesnsr main contorl stuct + +all tx register default initial configration define in this table + +all rx register attribute define in this table +*/ + +const forcesnsr_Reg_Cfg_Main_Str_typ forcesnsr_Main_Cfg_Tbl[] = +{ + /*tx register default initial value define */ + { + forcesnsr_Tx_CMD,0x00,2, (STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0]), + { + 0xB5,0x37, + forcesnsr_REG_FILL8_VAL,forcesnsr_REG_FILL6_VAL + } + }, + { + forcesnsr_Tx_CMD,0x07,8,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[8]), + { + 0x02,0x02,0x30,0x30,0x03,0x2D,0x60,0x93, + forcesnsr_REG_FILL8_VAL + } + }, + { + forcesnsr_Tx_CMD,0x16,2,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0x16]), + { + 0x0c,0x80, + forcesnsr_REG_FILL8_VAL,forcesnsr_REG_FILL6_VAL + } + }, + { + forcesnsr_Rx_CMD,0x00,15,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[0]), + { + forcesnsr_REG_FILL16_VAL + } + }, + { + forcesnsr_Rx_CMD,0xF,9,(STATE_UINT8 *)&(forcesnsr_reg_state_un.reg_grp[15]), + { + forcesnsr_REG_FILL16_VAL + } + } +}; + + + +/***************************main function define end ************************************/ + + diff --git a/firmware/src/forceSnsr/forceSnsr_Cfg.h b/firmware/src/forceSnsr/forceSnsr_Cfg.h new file mode 100644 index 0000000..ae94534 --- /dev/null +++ b/firmware/src/forceSnsr/forceSnsr_Cfg.h @@ -0,0 +1,209 @@ +#ifndef __forcesnsr_CFG_H__ +#define __forcesnsr_CFG_H__ + +#include "forceSnsr.h" +#include "../config/mcal/peripheral/port/plib_port.h" +#include "../config/mcal/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + + +/*************************************************************** +Macro Definition and enum define +***************************************************************/ + +typedef enum +{ + forcesnsr_REG_ID_MAIN_CFG_INDEX = 0x00, + forcesnsr_REG_ID_CAL_BASELINE_INT_CFG_INDEX , + forcesnsr_REG_ID_FALLING_CFG_INDEX , + forcesnsr_REG_ID_AD_TEMP_INDEX , + forcesnsr_REG_ID_BASELINE_INDEX , +}forcesnsr_Reg_Id_e_index_typ; + + + + + +typedef enum +{ + forcesnsr_Tx_CMD = 0x00, + forcesnsr_Rx_CMD = 0x01, +}forcesnsr_Direction_e_typ; + +#define forcesnsr_Max_reg_num 26 + +/*forcesnsr register default initial value*/ +#define forcesnsr_REG_FILL1_VAL ((STATE_UINT8)0x00) +#define forcesnsr_REG_FILL2_VAL forcesnsr_REG_FILL1_VAL,forcesnsr_REG_FILL1_VAL +#define forcesnsr_REG_FILL4_VAL forcesnsr_REG_FILL2_VAL,forcesnsr_REG_FILL2_VAL +#define forcesnsr_REG_FILL6_VAL forcesnsr_REG_FILL2_VAL,forcesnsr_REG_FILL2_VAL,forcesnsr_REG_FILL2_VAL +#define forcesnsr_REG_FILL8_VAL forcesnsr_REG_FILL4_VAL,forcesnsr_REG_FILL4_VAL +#define forcesnsr_REG_FILL16_VAL forcesnsr_REG_FILL8_VAL,forcesnsr_REG_FILL8_VAL + +#define forcesnsr_BIT7_ADDR 0x46 + + +/*************************************************************** +extern function interface +***************************************************************/ + + +#define forcesnsr_Get_INT_PORT() PORT_PinRead(PORT_PIN_PB31) + +/*************************************************************** +struct type define +***************************************************************/ + + + +/* APP mssage ID 45B tx */ +typedef struct { + /* Byte0 */ + STATE_UINT8 EN: 1;/*byte0 - bit0*/ + STATE_UINT8 TEMPWAIT: 2; + STATE_UINT8 ADCRAW: 1; + STATE_UINT8 WAIT: 3; + STATE_UINT8 TOEN: 1; /*byte0 - bit7*/ + + /* Byte1 */ + STATE_UINT8 PRECHARGE: 3;/*byte1- bit0*/ + STATE_UINT8 RESERVED_BYTE1_BIT3: 1; + STATE_UINT8 INAGAIN: 3; + STATE_UINT8 RESERVED_BYTE1_BIT7: 1; + + /* Byte2 */ + STATE_UINT8 INTR: 1;/*byte2- bit0*/ + STATE_UINT8 SNSERR: 1; + STATE_UINT8 OVRACALTH: 1; + STATE_UINT8 OVRINTRTH: 1; + STATE_UINT8 RESERVED_BYTE2_BIT4_6:3; + STATE_UINT8 BUSY: 1; + + + /* Byte3 */ + STATE_UINT8 ADCOUT_H: 8;/*byte3- bit0*/ + + /* Byte4 */ + STATE_UINT8 SCOUNT :4; + STATE_UINT8 ADCOUT_L :4;/*byte4- bit0*/ + + /* Byte5 */ + STATE_UINT8 TEMP_H: 8;/*byte5- bit0*/ + + /* Byte6 */ + STATE_UINT8 RESERVED_BYTE6_BIT0_3:4; + STATE_UINT8 TEMP_L: 4; + + /* Byte7 */ + STATE_UINT8 AUTOCAL_H: 8; + + /* Byte8 */ + STATE_UINT8 RESERVED_BYTE7_BIT0: 1; + STATE_UINT8 AUTOPRELDAD: 1; + STATE_UINT8 RESERVED_BYTE7_BIT2_3: 2; + STATE_UINT8 AUTOCAL_L: 4; + + /* Byte9 */ + STATE_UINT8 CALPERIOD: 3; + STATE_UINT8 INTRPOL: 1; + STATE_UINT8 CALRESET: 3; + STATE_UINT8 ENCALMODE: 1; + + /* ByteA */ + STATE_UINT8 LIFTDELAY: 3; + STATE_UINT8 RESERVED_BYTEA_BIT3: 1; + STATE_UINT8 RISEBLWGT: 3; + STATE_UINT8 RESERVED_BYTEA_BIT7: 1; + + /* ByteB */ + STATE_UINT8 FALLBLWGT: 3; + STATE_UINT8 PRELDADJ: 5; + + /* ByteC */ + STATE_UINT8 INTRTHR_H: 8; + + /* ByteD */ + STATE_UINT8 FALLTHRSEL: 3; + STATE_UINT8 RESERVED_BYTED_BIT3: 1; + STATE_UINT8 INTRTHR_L: 4; + + /* ByteE */ + STATE_UINT8 INTRSAMPLE: 3; + STATE_UINT8 RESERVED_BYTEE_BIT3: 1; + STATE_UINT8 BTNMODE: 1; + STATE_UINT8 INTRPERSIST: 1; + STATE_UINT8 INTRMODE: 1; + STATE_UINT8 INTREN: 1; + + /* ByteF */ + STATE_UINT8 FORCEBL: 1; + STATE_UINT8 RESERVED_BYTEF_BIT1_3: 3; + STATE_UINT8 PWRMODE: 4; + + /* Byte0x10 */ + STATE_UINT8 ADCMAX_H: 8; + + /* Byte0x11 */ + STATE_UINT8 RESERVED_BYTE11_BIT0_3: 4; + STATE_UINT8 ADCMAX_L: 4; + + /* Byte0x12 */ + STATE_UINT8 BASELINE_H: 8; + + /* Byte0x13 */ + STATE_UINT8 RESERVED_BYTE13_BIT0_3: 4; + STATE_UINT8 BASELINE_L: 4; + + + /* Byte0x14 */ + STATE_UINT8 ADCFIFO_H: 8; + + /* Byte0x15 */ + STATE_UINT8 FCOUNT: 4; + STATE_UINT8 ADCFIFO_L: 4; + + /* Byte0x16 */ + STATE_UINT8 FALLTHR_H: 8; + + /* Byte0x17 */ + STATE_UINT8 RESERVED_BYTE17_BIT0_3: 4; + STATE_UINT8 FALLTHR_L: 4; + + /* Byte0x18 */ + STATE_UINT8 VERSION: 8; + + /* Byte0x19 */ + STATE_UINT8 TEMPSNSBL: 8; + +}_forcesnsr_RxReg_Str_Type; + +typedef union { + STATE_UINT8 reg_grp[forcesnsr_Max_reg_num]; + _forcesnsr_RxReg_Str_Type forcesnsr_RxReg; +}forcesnsr_RxReg_un_type; + + +typedef struct +{ + STATE_UINT8 cmd_direction; + STATE_UINT8 cmd_id; + STATE_UINT8 cmd_len; + STATE_UINT8 * cmd_data; + STATE_UINT8 default_state[16]; +}forcesnsr_Reg_Cfg_Main_Str_typ; + + +/*************************************************************** +extern variable +***************************************************************/ + +extern forcesnsr_RxReg_un_type forcesnsr_reg_state_grp; +extern const forcesnsr_Reg_Cfg_Main_Str_typ forcesnsr_Main_Cfg_Tbl[]; + + + +#endif diff --git a/firmware/src/forceSnsr/forcedetect.c b/firmware/src/forceSnsr/forcedetect.c new file mode 100644 index 0000000..74b71d1 --- /dev/null +++ b/firmware/src/forceSnsr/forcedetect.c @@ -0,0 +1,112 @@ +#include "forceSnsr.h" +#include "forceSnsr_Cfg.h" +#include "forcedetect.h" +#include + + + +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ + +extern forcesnsr_RxReg_un_type forcesnsr_reg_state_un_bak; +static volatile STATE_UINT8 forcedetect_btn_val; +detectforce_Reg_Cfg_Main_Str_typ detectforce_Reg_Str; + + +/***************************static function define end ************************************/ +/*combind 8bit and 4bit data to uint16 +*/ +static inline STATE_UINT16 forcedetect_combind_data(STATE_UINT8 H_byte_8bit,STATE_UINT8 L_byte_4bit) +{ + uint16_t temp1=0,temp2=0; + temp1 = H_byte_8bit; + temp2 = L_byte_4bit; + temp1 <<= 4; + temp1 += temp2; + + return temp1; +} + + +/***************************init function define begin************************************/ +void forcedetect_Init(void) +{ + forcesnsr_Init(); + detectforce_Reg_Str.btn_state = FALSE; +} +/***************************init function define end ************************************/ + + + + +/***************************main function define begin************************************/ +void forcedetect_MainTask(void) +{ + STATE_UINT8 adc_cnt=0; + forcesnsr_MainTask(); + + adc_cnt = forcesnsr_reg_state_un_bak.forcesnsr_RxReg.SCOUNT; + + if(detectforce_Reg_Str.Adc_cnt != adc_cnt) + { + detectforce_Reg_Str.raw = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.ADCOUT_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.ADCOUT_L); + detectforce_Reg_Str.baseline = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.BASELINE_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.BASELINE_L); + detectforce_Reg_Str.force_snserr = forcesnsr_reg_state_un_bak.forcesnsr_RxReg.SNSERR; + detectforce_Reg_Str.autocal = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.AUTOCAL_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.AUTOCAL_L); + detectforce_Reg_Str.int_theshold = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.INTRTHR_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.INTRTHR_L); + detectforce_Reg_Str.adc_max = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.ADCOUT_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.ADCOUT_L); + detectforce_Reg_Str.fallthr = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.FALLTHR_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.FALLTHR_L); + detectforce_Reg_Str.temp = forcedetect_combind_data(forcesnsr_reg_state_un_bak.forcesnsr_RxReg.TEMP_H,forcesnsr_reg_state_un_bak.forcesnsr_RxReg.TEMP_L); + detectforce_Reg_Str.preload = forcesnsr_reg_state_un_bak.forcesnsr_RxReg.PRELDADJ; + detectforce_Reg_Str.Adc_cnt = adc_cnt; + } + + if(TRUE == Get_force_btn_is_press_state()) + { + detectforce_Reg_Str.btn_state = TRUE; + } + else + { + detectforce_Reg_Str.btn_state = FALSE; + } + + + } +/***************************main function define end ************************************/ + + +/* +return: ture is button pressed +*/ +STATE_UINT8 Get_forcedetect_btn_is_press_state(void) +{ + return detectforce_Reg_Str.btn_state; +} + +/* +return: force press value, value range 0~ 4095 +*/ +STATE_UINT16 Get_forcedetect_force_value(void) +{ + return detectforce_Reg_Str.raw; +} + + +STATE_UINT16 Get_forcedetect_basline_value(void) +{ + return detectforce_Reg_Str.baseline; +} + +STATE_UINT8 Get_forcedetect_SNSERR_value(void) +{ + return detectforce_Reg_Str.force_snserr;//0 no error 1 sensor error +} + +STATE_UINT8 Get_forcedetect_preload_value(void) +{ + return detectforce_Reg_Str.preload; +} + diff --git a/firmware/src/forceSnsr/forcedetect.h b/firmware/src/forceSnsr/forcedetect.h new file mode 100644 index 0000000..8752e15 --- /dev/null +++ b/firmware/src/forceSnsr/forcedetect.h @@ -0,0 +1,69 @@ +#ifndef __forcedetect_H__ +#define __forcedetect_H__ +/*************************************************************** +copyright from private LiuXiao +if you have any question,you can contact me by email 461445092@qq.com +2022-10-05 17:56:24.020233 +***************************************************************/ +#include "forceSnsr_Cfg.h" + +#ifndef TRUE +#define TRUE true +#endif + +#ifndef FALSE +#define FALSE false +#endif + + + + +/***************************datatype define begin************************************/ + +/***************************datatype define end************************************/ + +typedef struct +{ + STATE_UINT16 raw; + STATE_UINT16 baseline; + STATE_UINT16 autocal; + STATE_UINT16 int_theshold; + STATE_UINT16 adc_max; + STATE_UINT16 fallthr; + STATE_UINT16 temp; + STATE_UINT8 Adc_cnt; + STATE_UINT8 btn_state; + STATE_UINT8 force_snserr; + STATE_UINT8 preload; +}detectforce_Reg_Cfg_Main_Str_typ; + + + +/***************************enum define begin************************************/ + +/***************************enum define end************************************/ + + +/*****************************main control function begin**********************************/ +/*********************************main control function end*******************************/ + + +/***************************extern function begin************************************/ +extern void forcedetect_Init(void); +extern void forcedetect_MainTask(void); +extern STATE_UINT8 Get_forcedetect_btn_is_press_state(void); +/* +return: force press value, value range 0~ 4095 +*/ +extern STATE_UINT16 Get_forcedetect_force_value(void); + +extern STATE_UINT16 Get_forcedetect_basline_value(void); + +extern STATE_UINT8 Get_forcedetect_SNSERR_value(void); + +extern STATE_UINT8 Get_forcedetect_preload_value(void); + +/***************************extern function end************************************/ + + +#endif diff --git a/firmware/src/main.c b/firmware/src/main.c new file mode 100644 index 0000000..8f9e265 --- /dev/null +++ b/firmware/src/main.c @@ -0,0 +1,347 @@ +/******************************************************************************* + Main Source File + + Company: + Microchip Technology Inc. + + File Name: + main.c + + Summary: + This file contains the "main" function for a project. + + Description: + This file contains the "main" function for a project. The + "main" function calls the "SYS_Initialize" function to initialize the state + machines of all modules in the system + *******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "OsekCom/OsekCom.h" +#include "Speaker/Speaker.h" +#include "P417_SWTR_App_ert_rtw/P417_SWTR_App.h" +#include "TouchPanel/TouchPanel.h" +#include "forceSnsr/forcedetect.h" +#include "TLE9263/TLE926x_Main.h" +#include "TLE926x.h" +#include "core_cm4.h" +#include "RTE.h" +#include "DiagnosticR/Comp_ISO_15765_2/TP.h" +#include "DiagnosticR/Comp_ISO_15765_3/Iso15765_3.h" +#include "DiagnosticR/UDS/UDS_Services_Common.h" +#include "DiagnosticR/Dem/Dem.h" + +#include "calib_public.h" +#include "smartee.h" +#include "FunctionState.h" +#include "SysDiagDetect.h" +/* System tick */ +uint32_t SysTick_1ms_Period = 0; +uint32_t SysTick_Cur_Counter = 0; +volatile uint32_t SysTick_Elapse = 0; +uint32_t CyclicTskSchM_CurTime = 0; +uint8_t Test_frame_On = 0; +uint8_t SDZ_init_flag = 0; +uint8_t SDZ_first_delay = 0; + + +void OS_TimerCallback(uintptr_t context) +{ + SysTick_Elapse++; +} + +void CyclicTskSchM_TimerSync (void) +{ + CyclicTskSchM_CurTime+= 1; + + while (SysTick_Elapse < CyclicTskSchM_CurTime) + { + /* TimerSync */ + } + + CyclicTskSchM_CurTime = SysTick_Elapse; +} +/* PWM */ +uint32_t counter = 0; +uint32_t duty = 7999; +uint32_t period = 0; + +/* ADC1 */ +#define ADC1_CH_AD_LDO_SNS 0 +#define ADC1_CH_LD_OUT_SNS 1 +#define ADC1_CH_MAX 2 + +uint8_t adc_ch_sel = 0; +uint16_t adc_result = 0; +uint16_t adc[ADC1_CH_MAX] = {0}; + +void ADC1_ConversionCallback (ADC_STATUS status, uintptr_t context) +{ + if(status == ADC_STATUS_RESRDY) { + adc_result = ADC1_ConversionResultGet(); + //adc[adc_ch_sel - 1] = adc_result & 0xFFF; + adc[adc_ch_sel] = adc_result & 0xFFF; + + switch (adc_ch_sel) + { + case ADC1_CH_AD_LDO_SNS: + ADC1_ChannelSelect(ADC_POSINPUT_AIN6, ADC_NEGINPUT_GND); + adc_ch_sel= ADC1_CH_LD_OUT_SNS; + break; + case ADC1_CH_LD_OUT_SNS: + ADC1_ChannelSelect(ADC_POSINPUT_AIN7, ADC_NEGINPUT_GND); + adc_ch_sel= ADC1_CH_AD_LDO_SNS; + break; + default: + break; + } + //adc_ch_sel++; + //if (adc_ch_sel > ADC1_CH_MAX) { + // adc_ch_sel = ADC1_CH_AD_LDO_SNS + 1; + //} + ADC1_ConversionStart(); + } +} + + +/* CAN1 */ +bool Can1BusErrFlag = false; +uint8_t Can1MessageRAM[CAN1_MESSAGE_RAM_CONFIG_SIZE] __attribute__((aligned (32))); +uint32_t Received_id[8] = {0}; +typedef struct +{ + /* id */ + uint32_t id; + /* Data field */ + uint8_t data[8]; + +} CAN_Received_Buffer; +CAN_Received_Buffer Received_buf[8] = {0}; + +#define WRITE_ID(id) (id << 18) +#define READ_ID(id) (id >> 18) +static uint8_t canTxBuffer[CAN1_TX_FIFO_BUFFER_SIZE]; +static uint8_t canRxBuffer[CAN1_RX_FIFO0_SIZE]; + +CAN_RX_BUFFER *CanRxBuf_t = NULL; +CAN_TX_BUFFER *CanTxBuffer = NULL; + +uint32_t CanBufQueryIdTp(void) +{ + return Received_buf[0].id; +} + +uint32_t CanBufQueryIdTp_Tx(void) +{ + return CanTxBuffer->id; +} + +uint8_t CanBufQueryDataByte(uint8_t hdl, uint8_t index) +{ + uint8_t byte; + + byte = (uint8_t)Received_buf[0].data[index]; + + return byte; +} + +void CAN_Rx_FIFO0_CALLBACK(uint8_t numberOfMessage, uintptr_t context) +{ + uint8_t MessageNumer = 0; + CAN1_MessageReceiveFifo(CAN_RX_FIFO_0, numberOfMessage, (CAN_RX_BUFFER *)canRxBuffer); + CanRxBuf_t = (CAN_RX_BUFFER *)canRxBuffer; + for (;MessageNumer < numberOfMessage; MessageNumer++) + { + Received_buf[MessageNumer].id = READ_ID(CanRxBuf_t[MessageNumer].id); + memcpy(Received_buf[MessageNumer].data, CanRxBuf_t[MessageNumer].data, 8); + } + OsekComRxNotifCallbackSWTR(0); +} + +void CAN_Tx_FIFO0_CALLBACK(uintptr_t context) +{ + OsekComTxNotifCallbackSWTR(0); +} + +/* CAN handlers definition */ +void CanTx(t_can_handler can_handler, bool notif, uint32_t idtp, uint16_t len, t_can_data can_data) +{ + uint8_t loop_count = 0; + + memset(canTxBuffer, 0x00, CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE); + CanTxBuffer = (CAN_TX_BUFFER *)canTxBuffer; + CanTxBuffer->id = WRITE_ID(idtp); + CanTxBuffer->dlc = len; + for (loop_count = 0; loop_count < len; loop_count++){ + CanTxBuffer->data[loop_count] = can_data[loop_count]; + } + if (CAN1_MessageTransmitFifo(1, CanTxBuffer) == true) + { + ; + } + else + { + ; + } +} +void IhuPrivateDHUCanFr01_CALLBACK(void) +{ + ; +} + +void IhuPrivateDHUCanFr01_Timeout_CALLBACK(void) +{ + ; +} + +// ***************************************************************************** +// ***************************************************************************** +// Section: Main Entry Point +// ***************************************************************************** +// ***************************************************************************** +static uint32_t status = 0; + +int main ( void ) +{ + uint32_t loop_counter = 0; + /* Initialize all modules */ + SYS_Initialize ( NULL ); + //Tle9263_Init(); + Calib_Init(); + WDT_TimeoutPeriodSet(1); + SysTick_1ms_Period = SYSTICK_TimerPeriodGet() + 1; + SYSTICK_TimerCallbackSet(OS_TimerCallback, 0); + SYSTICK_TimerStart(); + + TCC0_PWMStart(); + + CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_0, &CAN_Rx_FIFO0_CALLBACK, (uintptr_t)NULL); + CAN1_TxFifoCallbackRegister(&CAN_Tx_FIFO0_CALLBACK, (uintptr_t)NULL); + CAN1_MessageRAMConfigSet(Can1MessageRAM); + StartCom(COM_NORMAL_MODE); + RTE_Set_All_UB(); + StartPeriodic(); + + speaker_Init(); + forcedetect_Init(); + TouchPanel_init(); + Tle9263_Init(); + + ADC1_Enable(); + ADC1_CallbackRegister(ADC1_ConversionCallback, 0); + ADC1_ChannelSelect(ADC_POSINPUT_AIN6, ADC_NEGINPUT_GND); + //adc_ch_sel++; + ADC1_ConversionStart(); + + P417_SWTR_App_initialize(); + + //WDT_Enable(); + InicialitzaTPTask(ISO15765_2_REPROGONCAN_HANDLER); + InicialitzaIso15765_3Task(); + Dem_Init(); + UDS_DID_initNVM(); + PORT_PinWrite(PORT_PIN_PB02,1);//battery voltage detection on + PORT_PinWrite(PORT_PIN_PA13,0);/*init turn off SDZ*/ + SmartEE_Read(0x783, &Test_frame_On , 1); + if (Test_frame_On > 1) + { + Test_frame_On = 1; + } + + + Fuction_State = Function_State_A; + while ( true ) + { + /* Maintain state machines of all polled MPLAB Harmony modules. */ + SYS_Tasks ( ); + ADC1_ChannelSelect(ADC_POSINPUT_AIN6, ADC_NEGINPUT_GND); + + ADC1_ConversionStart(); + + + + + + if (!(loop_counter % 2)) + { + //(void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, duty); + OsekComTask(); + Tle9263_MainTask(); + /* call touch process function */ + if(Fuction_State == Function_State_A) + { + TouchPanel_MainFunction(); + speaker_MainTask(); + forcedetect_MainTask(); + + RTE_Set_All_Test_Value(); + } + else + { + //(void)TCC0_PWM24bitDutySet(TCC0_CHANNEL0, 0);//Turn off LED + } + //TCC0_PWM24bitDutySet(TCC0_CHANNEL0,6999); + if(Fuction_State != Function_State_C) + { + TPTask(ISO15765_2_REPROGONCAN_HANDLER); + Iso15765_3Task(); + Dem_MainFunction(); + } + Calib_Task(); + + //SBC VCC2 always on Setting + sbc_write_reg(SBC_M_S_CTRL,0x18,0); + + } + + if (!(loop_counter % 5)) + { + FunctionState_Task(); + Sys_Diag_Detcet_Task(); + + + } + + + /* Check CAN Status */ + status = CAN1_ErrorGet(); +#if 0 + if (Can1BusErrFlag == false) + { + WDT_Clear(); + } + else + { + Can1BusErrFlag = false; + NVIC_SystemReset(); + while(1); + } +#endif + WDT_Clear(); + //if(Fuction_State == Function_State_A) + //{ + P417_SWTR_App_step(); + // } + CyclicTskSchM_TimerSync(); + loop_counter++; + } + + /* Execution should not come here during normal operation */ + + return ( EXIT_FAILURE ); +} + + +/******************************************************************************* + End of File +*/ + diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/ac.h b/firmware/src/packs/ATSAME51J19A_DFP/component/ac.h new file mode 100644 index 0000000..b2c6412 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/ac.h @@ -0,0 +1,416 @@ +/* + * Component description for AC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_AC_COMPONENT_H_ +#define _SAME51_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AC_CTRLA register */ +#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_CTRLA register */ +#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assigment of value for START0 in the AC_CTRLB register */ +#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assigment of value for START1 in the AC_CTRLB register */ +#define AC_CTRLB_Msk _UINT8_(0x03) /* (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_UINT8_(0x3) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assigment of value for COMPEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assigment of value for COMPEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assigment of value for WINEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assigment of value for COMPEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assigment of value for COMPEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_Msk _UINT16_(0x3313) /* (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0x3) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0x3) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_UINT16_(0x3) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENCLR register */ +#define AC_INTENCLR_Msk _UINT8_(0x13) /* (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_UINT8_(0x3) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENSET register */ +#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENSET register */ +#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENSET register */ +#define AC_INTENSET_Msk _UINT8_(0x13) /* (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_UINT8_(0x3) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_UINT8_(0x1) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTFLAG register */ +#define AC_INTFLAG_Msk _UINT8_(0x13) /* (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_UINT8_(0x3) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assigment of value for STATE0 in the AC_STATUSA register */ +#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assigment of value for STATE1 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assigment of value for WSTATE0 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _UINT8_(0x33) /* (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_UINT8_(0x3) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assigment of value for READY0 in the AC_STATUSB register */ +#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assigment of value for READY1 in the AC_STATUSB register */ +#define AC_STATUSB_Msk _UINT8_(0x03) /* (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_UINT8_(0x3) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AC_DBGCTRL register */ +#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assigment of value for WEN0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assigment of value for WINTSEL0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _UINT8_(0x07) /* (AC_WINCTRL) Register Mask */ + +#define AC_WINCTRL_WEN_Pos _UINT8_(0) /* (AC_WINCTRL Position) Window x Mode Enable */ +#define AC_WINCTRL_WEN_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN_Pos) /* (AC_WINCTRL Mask) WEN */ +#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & (_UINT8_(value) << AC_WINCTRL_WEN_Pos)) + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assigment of value for VALUE in the AC_SCALER register */ +#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assigment of value for SINGLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assigment of value for INTSEL in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assigment of value for SWAP in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assigment of value for SPEED in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assigment of value for HYSTEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_HYST_Pos _UINT32_(20) /* (AC_COMPCTRL) Hysteresis Level Position */ +#define AC_COMPCTRL_HYST_Msk (_UINT32_(0x3) << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) Hysteresis Level Mask */ +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & (_UINT32_(value) << AC_COMPCTRL_HYST_Pos)) /* Assigment of value for HYST in the AC_COMPCTRL register */ +#define AC_COMPCTRL_HYST_HYST25_Val _UINT32_(0x0) /* (AC_COMPCTRL) 25mV */ +#define AC_COMPCTRL_HYST_HYST50_Val _UINT32_(0x1) /* (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST75_Val _UINT32_(0x2) /* (AC_COMPCTRL) 75mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _UINT32_(0x3) /* (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST25 (AC_COMPCTRL_HYST_HYST25_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 25mV Position */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 50mV Position */ +#define AC_COMPCTRL_HYST_HYST75 (AC_COMPCTRL_HYST_HYST75_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 75mV Position */ +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 100mV Position */ +#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assigment of value for FLEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assigment of value for OUT in the AC_COMPCTRL register */ +#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _UINT32_(0x373BF75E) /* (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assigment of value for WINCTRL in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assigment of value for COMPCTRL0 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assigment of value for COMPCTRL1 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_Msk _UINT32_(0x0000001F) /* (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#define AC_CALIB_RESETVALUE _UINT16_(0x101) /* (AC_CALIB) Calibration Reset Value */ + +#define AC_CALIB_BIAS0_Pos _UINT16_(0) /* (AC_CALIB) COMP0/1 Bias Scaling Position */ +#define AC_CALIB_BIAS0_Msk (_UINT16_(0x3) << AC_CALIB_BIAS0_Pos) /* (AC_CALIB) COMP0/1 Bias Scaling Mask */ +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & (_UINT16_(value) << AC_CALIB_BIAS0_Pos)) /* Assigment of value for BIAS0 in the AC_CALIB register */ +#define AC_CALIB_Msk _UINT16_(0x0003) /* (AC_CALIB) Register Mask */ + + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ +#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ +#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ +#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ +#define AC_CALIB_REG_OFST _UINT32_(0x24) /* (AC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint8_t Reserved3[0x08]; + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_AC_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/adc.h b/firmware/src/packs/ATSAME51J19A_DFP/component/adc.h new file mode 100644 index 0000000..c34aa28 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/adc.h @@ -0,0 +1,633 @@ +/* + * Component description for ADC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_ADC_COMPONENT_H_ +#define _SAME51_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _UINT16_(0) /* (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_UINT16_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT16_(value) << ADC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_CTRLA register */ +#define ADC_CTRLA_ENABLE_Pos _UINT16_(1) /* (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_UINT16_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT16_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_CTRLA register */ +#define ADC_CTRLA_DUALSEL_Pos _UINT16_(3) /* (ADC_CTRLA) Dual Mode Trigger Selection Position */ +#define ADC_CTRLA_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLA_DUALSEL_Pos)) /* Assigment of value for DUALSEL in the ADC_CTRLA register */ +#define ADC_CTRLA_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLA_SLAVEEN_Pos _UINT16_(5) /* (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_UINT16_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT16_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assigment of value for SLAVEEN in the ADC_CTRLA register */ +#define ADC_CTRLA_RUNSTDBY_Pos _UINT16_(6) /* (ADC_CTRLA) Run in Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_UINT16_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run in Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT16_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the ADC_CTRLA register */ +#define ADC_CTRLA_ONDEMAND_Pos _UINT16_(7) /* (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_UINT16_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT16_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the ADC_CTRLA register */ +#define ADC_CTRLA_PRESCALER_Pos _UINT16_(8) /* (ADC_CTRLA) Prescaler Configuration Position */ +#define ADC_CTRLA_PRESCALER_Msk (_UINT16_(0x7) << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Prescaler Configuration Mask */ +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & (_UINT16_(value) << ADC_CTRLA_PRESCALER_Pos)) /* Assigment of value for PRESCALER in the ADC_CTRLA register */ +#define ADC_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x0) /* (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x1) /* (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x2) /* (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x3) /* (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x4) /* (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x5) /* (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x6) /* (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x7) /* (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 2 Position */ +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 4 Position */ +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 8 Position */ +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 16 Position */ +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 32 Position */ +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 64 Position */ +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 128 Position */ +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 256 Position */ +#define ADC_CTRLA_R2R_Pos _UINT16_(15) /* (ADC_CTRLA) Rail to Rail Operation Enable Position */ +#define ADC_CTRLA_R2R_Msk (_UINT16_(0x1) << ADC_CTRLA_R2R_Pos) /* (ADC_CTRLA) Rail to Rail Operation Enable Mask */ +#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & (_UINT16_(value) << ADC_CTRLA_R2R_Pos)) /* Assigment of value for R2R in the ADC_CTRLA register */ +#define ADC_CTRLA_Msk _UINT16_(0x87FB) /* (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assigment of value for FLUSHEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assigment of value for FLUSHINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assigment of value for STARTINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assigment of value for RESRDYEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assigment of value for WINMONEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the ADC_DBGCTRL register */ +#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _UINT16_(0xC) /* (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _UINT16_(0xD) /* (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _UINT16_(0xE) /* (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _UINT16_(0xF) /* (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) Temperature Sensor TSENSP */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _UINT16_(0x1D) /* (ADC_INPUTCTRL) Temperature Sensor TSENSC */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1E) /* (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _UINT16_(0x1F) /* (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN12 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN13 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN14 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN15 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */ +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) PTC output (only on ADC0) Position */ +#define ADC_INPUTCTRL_DIFFMODE_Pos _UINT16_(7) /* (ADC_INPUTCTRL) Differential Mode Position */ +#define ADC_INPUTCTRL_DIFFMODE_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /* (ADC_INPUTCTRL) Differential Mode Mask */ +#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DIFFMODE_Pos)) /* Assigment of value for DIFFMODE in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Pos _UINT16_(15) /* (ADC_INPUTCTRL) Stop DMA Sequencing Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /* (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ +#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) /* Assigment of value for DSEQSTOP in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_Msk _UINT16_(0x9F9F) /* (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_LEFTADJ_Pos _UINT16_(0) /* (ADC_CTRLB) Left-Adjusted Result Position */ +#define ADC_CTRLB_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /* (ADC_CTRLB) Left-Adjusted Result Mask */ +#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLB_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the ADC_CTRLB register */ +#define ADC_CTRLB_FREERUN_Pos _UINT16_(1) /* (ADC_CTRLB) Free Running Mode Position */ +#define ADC_CTRLB_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLB_FREERUN_Pos) /* (ADC_CTRLB) Free Running Mode Mask */ +#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLB_FREERUN_Pos)) /* Assigment of value for FREERUN in the ADC_CTRLB register */ +#define ADC_CTRLB_CORREN_Pos _UINT16_(2) /* (ADC_CTRLB) Digital Correction Logic Enable Position */ +#define ADC_CTRLB_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLB_CORREN_Pos) /* (ADC_CTRLB) Digital Correction Logic Enable Mask */ +#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & (_UINT16_(value) << ADC_CTRLB_CORREN_Pos)) /* Assigment of value for CORREN in the ADC_CTRLB register */ +#define ADC_CTRLB_RESSEL_Pos _UINT16_(3) /* (ADC_CTRLB) Conversion Result Resolution Position */ +#define ADC_CTRLB_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) Conversion Result Resolution Mask */ +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLB_RESSEL_Pos)) /* Assigment of value for RESSEL in the ADC_CTRLB register */ +#define ADC_CTRLB_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 12-bit result Position */ +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) For averaging mode output Position */ +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 10-bit result Position */ +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 8-bit result Position */ +#define ADC_CTRLB_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLB) Window Monitor Mode Position */ +#define ADC_CTRLB_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) Window Monitor Mode Mask */ +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLB_WINMODE_Pos)) /* Assigment of value for WINMODE in the ADC_CTRLB register */ +#define ADC_CTRLB_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) No window mode (default) Position */ +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT > WINLT Position */ +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLB_WINSS_Pos _UINT16_(11) /* (ADC_CTRLB) Window Single Sample Position */ +#define ADC_CTRLB_WINSS_Msk (_UINT16_(0x1) << ADC_CTRLB_WINSS_Pos) /* (ADC_CTRLB) Window Single Sample Mask */ +#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & (_UINT16_(value) << ADC_CTRLB_WINSS_Pos)) /* Assigment of value for WINSS in the ADC_CTRLB register */ +#define ADC_CTRLB_Msk _UINT16_(0x0F1F) /* (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assigment of value for REFSEL in the ADC_REFCTRL register */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x3) /* (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x4) /* (ADC_REFCTRL) External Reference A */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _UINT8_(0x5) /* (ADC_REFCTRL) External Reference B */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _UINT8_(0x6) /* (ADC_REFCTRL) External Reference C (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference A Position */ +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference B Position */ +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference C (only on ADC1) Position */ +#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assigment of value for REFCOMP in the ADC_REFCTRL register */ +#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assigment of value for SAMPLENUM in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assigment of value for ADJRES in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assigment of value for SAMPLEN in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assigment of value for OFFCOMP in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_WINLT register */ +#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_WINUT register */ +#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_GAINCORR register */ +#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_OFFSETCORR register */ +#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Conversion Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Conversion Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assigment of value for FLUSH in the ADC_SWTRIG register */ +#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assigment of value for START in the ADC_SWTRIG register */ +#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENCLR register */ +#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENCLR register */ +#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENCLR register */ +#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENSET register */ +#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENSET register */ +#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENSET register */ +#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTFLAG register */ +#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTFLAG register */ +#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTFLAG register */ +#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ +#define ADC_STATUS_RESETVALUE _UINT8_(0x00) /* (ADC_STATUS) Status Reset Value */ + +#define ADC_STATUS_ADCBUSY_Pos _UINT8_(0) /* (ADC_STATUS) ADC Busy Status Position */ +#define ADC_STATUS_ADCBUSY_Msk (_UINT8_(0x1) << ADC_STATUS_ADCBUSY_Pos) /* (ADC_STATUS) ADC Busy Status Mask */ +#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & (_UINT8_(value) << ADC_STATUS_ADCBUSY_Pos)) /* Assigment of value for ADCBUSY in the ADC_STATUS register */ +#define ADC_STATUS_WCC_Pos _UINT8_(2) /* (ADC_STATUS) Window Comparator Counter Position */ +#define ADC_STATUS_WCC_Msk (_UINT8_(0x3F) << ADC_STATUS_WCC_Pos) /* (ADC_STATUS) Window Comparator Counter Mask */ +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & (_UINT8_(value) << ADC_STATUS_WCC_Pos)) /* Assigment of value for WCC in the ADC_STATUS register */ +#define ADC_STATUS_Msk _UINT8_(0xFD) /* (ADC_STATUS) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT32_(2) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_CTRLB_Pos _UINT32_(3) /* (ADC_SYNCBUSY) Control B Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /* (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << ADC_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_REFCTRL_Pos _UINT32_(4) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_REFCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT32_(5) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT32_(6) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINLT_Pos _UINT32_(7) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINUT_Pos _UINT32_(8) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_GAINCORR_Pos _UINT32_(9) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT32_(10) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SWTRIG_Pos _UINT32_(11) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assigment of value for SWTRIG in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_Msk _UINT32_(0x00000FFF) /* (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#define ADC_DSEQDATA_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ + +#define ADC_DSEQDATA_DATA_Pos _UINT32_(0) /* (ADC_DSEQDATA) DMA Sequential Data Position */ +#define ADC_DSEQDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /* (ADC_DSEQDATA) DMA Sequential Data Mask */ +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & (_UINT32_(value) << ADC_DSEQDATA_DATA_Pos)) /* Assigment of value for DATA in the ADC_DSEQDATA register */ +#define ADC_DSEQDATA_Msk _UINT32_(0xFFFFFFFF) /* (ADC_DSEQDATA) Register Mask */ + + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#define ADC_DSEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQCTRL) Input Control Position */ +#define ADC_DSEQCTRL_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /* (ADC_DSEQCTRL) Input Control Mask */ +#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQCTRL) Control B Position */ +#define ADC_DSEQCTRL_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /* (ADC_DSEQCTRL) Control B Mask */ +#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQCTRL_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQCTRL) Reference Control Position */ +#define ADC_DSEQCTRL_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /* (ADC_DSEQCTRL) Reference Control Mask */ +#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQCTRL) Average Control Position */ +#define ADC_DSEQCTRL_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /* (ADC_DSEQCTRL) Average Control Mask */ +#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQCTRL) Sampling Time Control Position */ +#define ADC_DSEQCTRL_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /* (ADC_DSEQCTRL) Sampling Time Control Mask */ +#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_WINLT_Pos _UINT32_(5) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ +#define ADC_DSEQCTRL_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_WINUT_Pos _UINT32_(6) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ +#define ADC_DSEQCTRL_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQCTRL) Gain Correction Position */ +#define ADC_DSEQCTRL_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /* (ADC_DSEQCTRL) Gain Correction Mask */ +#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQCTRL) Offset Correction Position */ +#define ADC_DSEQCTRL_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /* (ADC_DSEQCTRL) Offset Correction Mask */ +#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_AUTOSTART_Pos _UINT32_(31) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ +#define ADC_DSEQCTRL_AUTOSTART_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ +#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AUTOSTART_Pos)) /* Assigment of value for AUTOSTART in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_Msk _UINT32_(0x800001FF) /* (ADC_DSEQCTRL) Register Mask */ + + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ +#define ADC_DSEQSTAT_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQSTAT) Input Control Position */ +#define ADC_DSEQSTAT_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /* (ADC_DSEQSTAT) Input Control Mask */ +#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQSTAT) Control B Position */ +#define ADC_DSEQSTAT_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /* (ADC_DSEQSTAT) Control B Mask */ +#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQSTAT_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQSTAT) Reference Control Position */ +#define ADC_DSEQSTAT_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /* (ADC_DSEQSTAT) Reference Control Mask */ +#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQSTAT) Average Control Position */ +#define ADC_DSEQSTAT_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /* (ADC_DSEQSTAT) Average Control Mask */ +#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQSTAT) Sampling Time Control Position */ +#define ADC_DSEQSTAT_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /* (ADC_DSEQSTAT) Sampling Time Control Mask */ +#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_WINLT_Pos _UINT32_(5) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ +#define ADC_DSEQSTAT_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_WINUT_Pos _UINT32_(6) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ +#define ADC_DSEQSTAT_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQSTAT) Gain Correction Position */ +#define ADC_DSEQSTAT_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /* (ADC_DSEQSTAT) Gain Correction Mask */ +#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQSTAT) Offset Correction Position */ +#define ADC_DSEQSTAT_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /* (ADC_DSEQSTAT) Offset Correction Mask */ +#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_BUSY_Pos _UINT32_(31) /* (ADC_DSEQSTAT) DMA Sequencing Busy Position */ +#define ADC_DSEQSTAT_BUSY_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /* (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ +#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & (_UINT32_(value) << ADC_DSEQSTAT_BUSY_Pos)) /* Assigment of value for BUSY in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_Msk _UINT32_(0x800001FF) /* (ADC_DSEQSTAT) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ +#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Conversion Value Reset Value */ + +#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Conversion Value Position */ +#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Conversion Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the ADC_RESULT register */ +#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ + + +/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ +#define ADC_RESS_RESETVALUE _UINT16_(0x00) /* (ADC_RESS) Last Sample Result Reset Value */ + +#define ADC_RESS_RESS_Pos _UINT16_(0) /* (ADC_RESS) Last ADC conversion result Position */ +#define ADC_RESS_RESS_Msk (_UINT16_(0xFFFF) << ADC_RESS_RESS_Pos) /* (ADC_RESS) Last ADC conversion result Mask */ +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & (_UINT16_(value) << ADC_RESS_RESS_Pos)) /* Assigment of value for RESS in the ADC_RESS register */ +#define ADC_RESS_Msk _UINT16_(0xFFFF) /* (ADC_RESS) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assigment of value for BIASCOMP in the ADC_CALIB register */ +#define ADC_CALIB_BIASR2R_Pos _UINT16_(4) /* (ADC_CALIB) Bias R2R Ampli scaling Position */ +#define ADC_CALIB_BIASR2R_Msk (_UINT16_(0x7) << ADC_CALIB_BIASR2R_Pos) /* (ADC_CALIB) Bias R2R Ampli scaling Mask */ +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & (_UINT16_(value) << ADC_CALIB_BIASR2R_Pos)) /* Assigment of value for BIASR2R in the ADC_CALIB register */ +#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assigment of value for BIASREFBUF in the ADC_CALIB register */ +#define ADC_CALIB_Msk _UINT16_(0x0777) /* (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ +#define ADC_EVCTRL_REG_OFST _UINT32_(0x02) /* (ADC_EVCTRL) Event Control Offset */ +#define ADC_DBGCTRL_REG_OFST _UINT32_(0x03) /* (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x04) /* (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLB_REG_OFST _UINT32_(0x06) /* (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST _UINT32_(0x08) /* (ADC_REFCTRL) Reference Control Offset */ +#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0A) /* (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0B) /* (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST _UINT32_(0x0C) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST _UINT32_(0x0E) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST _UINT32_(0x10) /* (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x12) /* (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST _UINT32_(0x14) /* (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_INTENCLR_REG_OFST _UINT32_(0x2C) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST _UINT32_(0x2D) /* (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST _UINT32_(0x2E) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_STATUS_REG_OFST _UINT32_(0x2F) /* (ADC_STATUS) Status Offset */ +#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x30) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_DSEQDATA_REG_OFST _UINT32_(0x34) /* (ADC_DSEQDATA) DMA Sequencial Data Offset */ +#define ADC_DSEQCTRL_REG_OFST _UINT32_(0x38) /* (ADC_DSEQCTRL) DMA Sequential Control Offset */ +#define ADC_DSEQSTAT_REG_OFST _UINT32_(0x3C) /* (ADC_DSEQSTAT) DMA Sequencial Status Offset */ +#define ADC_RESULT_REG_OFST _UINT32_(0x40) /* (ADC_RESULT) Result Conversion Value Offset */ +#define ADC_RESS_REG_OFST _UINT32_(0x44) /* (ADC_RESS) Last Sample Result Offset */ +#define ADC_CALIB_REG_OFST _UINT32_(0x48) /* (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */ + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x17]; + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */ + __I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */ + __O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */ + __I uint8_t Reserved3[0x02]; + __I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */ + __I uint8_t Reserved4[0x02]; + __IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_ADC_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/aes.h b/firmware/src/packs/ATSAME51J19A_DFP/component/aes.h new file mode 100644 index 0000000..dc867bb --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/aes.h @@ -0,0 +1,317 @@ +/* + * Component description for AES + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_AES_COMPONENT_H_ +#define _SAME51_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#define AES_CTRLA_RESETVALUE _UINT32_(0x00) /* (AES_CTRLA) Control A Reset Value */ + +#define AES_CTRLA_SWRST_Pos _UINT32_(0) /* (AES_CTRLA) Software Reset Position */ +#define AES_CTRLA_SWRST_Msk (_UINT32_(0x1) << AES_CTRLA_SWRST_Pos) /* (AES_CTRLA) Software Reset Mask */ +#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & (_UINT32_(value) << AES_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AES_CTRLA register */ +#define AES_CTRLA_ENABLE_Pos _UINT32_(1) /* (AES_CTRLA) Enable Position */ +#define AES_CTRLA_ENABLE_Msk (_UINT32_(0x1) << AES_CTRLA_ENABLE_Pos) /* (AES_CTRLA) Enable Mask */ +#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & (_UINT32_(value) << AES_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AES_CTRLA register */ +#define AES_CTRLA_AESMODE_Pos _UINT32_(2) /* (AES_CTRLA) AES Modes of operation Position */ +#define AES_CTRLA_AESMODE_Msk (_UINT32_(0x7) << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) AES Modes of operation Mask */ +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & (_UINT32_(value) << AES_CTRLA_AESMODE_Pos)) /* Assigment of value for AESMODE in the AES_CTRLA register */ +#define AES_CTRLA_AESMODE_ECB_Val _UINT32_(0x0) /* (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _UINT32_(0x1) /* (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _UINT32_(0x2) /* (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _UINT32_(0x3) /* (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _UINT32_(0x4) /* (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _UINT32_(0x5) /* (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _UINT32_(0x6) /* (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Electronic code book mode Position */ +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher block chaining mode Position */ +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Output feedback mode Position */ +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher feedback mode Position */ +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Counter mode Position */ +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) CCM mode Position */ +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Galois counter mode Position */ +#define AES_CTRLA_CFBS_Pos _UINT32_(5) /* (AES_CTRLA) Cipher Feedback Block Size Position */ +#define AES_CTRLA_CFBS_Msk (_UINT32_(0x7) << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) Cipher Feedback Block Size Mask */ +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & (_UINT32_(value) << AES_CTRLA_CFBS_Pos)) /* Assigment of value for CFBS in the AES_CTRLA register */ +#define AES_CTRLA_CFBS_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _UINT32_(0x3) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _UINT32_(0x4) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_KEYSIZE_Pos _UINT32_(8) /* (AES_CTRLA) Encryption Key Size Position */ +#define AES_CTRLA_KEYSIZE_Msk (_UINT32_(0x3) << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) Encryption Key Size Mask */ +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & (_UINT32_(value) << AES_CTRLA_KEYSIZE_Pos)) /* Assigment of value for KEYSIZE in the AES_CTRLA register */ +#define AES_CTRLA_KEYSIZE_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_CIPHER_Pos _UINT32_(10) /* (AES_CTRLA) Cipher Mode Position */ +#define AES_CTRLA_CIPHER_Msk (_UINT32_(0x1) << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Cipher Mode Mask */ +#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & (_UINT32_(value) << AES_CTRLA_CIPHER_Pos)) /* Assigment of value for CIPHER in the AES_CTRLA register */ +#define AES_CTRLA_CIPHER_DEC_Val _UINT32_(0x0) /* (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _UINT32_(0x1) /* (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Decryption Position */ +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Encryption Position */ +#define AES_CTRLA_STARTMODE_Pos _UINT32_(11) /* (AES_CTRLA) Start Mode Select Position */ +#define AES_CTRLA_STARTMODE_Msk (_UINT32_(0x1) << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Mode Select Mask */ +#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & (_UINT32_(value) << AES_CTRLA_STARTMODE_Pos)) /* Assigment of value for STARTMODE in the AES_CTRLA register */ +#define AES_CTRLA_STARTMODE_MANUAL_Val _UINT32_(0x0) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _UINT32_(0x1) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ +#define AES_CTRLA_LOD_Pos _UINT32_(12) /* (AES_CTRLA) Last Output Data Mode Position */ +#define AES_CTRLA_LOD_Msk (_UINT32_(0x1) << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Last Output Data Mode Mask */ +#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & (_UINT32_(value) << AES_CTRLA_LOD_Pos)) /* Assigment of value for LOD in the AES_CTRLA register */ +#define AES_CTRLA_LOD_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Start encryption in Last Output Data mode Position */ +#define AES_CTRLA_KEYGEN_Pos _UINT32_(13) /* (AES_CTRLA) Last Key Generation Position */ +#define AES_CTRLA_KEYGEN_Msk (_UINT32_(0x1) << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Last Key Generation Mask */ +#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & (_UINT32_(value) << AES_CTRLA_KEYGEN_Pos)) /* Assigment of value for KEYGEN in the AES_CTRLA register */ +#define AES_CTRLA_KEYGEN_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ +#define AES_CTRLA_XORKEY_Pos _UINT32_(14) /* (AES_CTRLA) XOR Key Operation Position */ +#define AES_CTRLA_XORKEY_Msk (_UINT32_(0x1) << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) XOR Key Operation Mask */ +#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & (_UINT32_(value) << AES_CTRLA_XORKEY_Pos)) /* Assigment of value for XORKEY in the AES_CTRLA register */ +#define AES_CTRLA_XORKEY_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _UINT32_(0x1) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ +#define AES_CTRLA_CTYPE_Pos _UINT32_(16) /* (AES_CTRLA) Counter Measure Type Position */ +#define AES_CTRLA_CTYPE_Msk (_UINT32_(0xF) << AES_CTRLA_CTYPE_Pos) /* (AES_CTRLA) Counter Measure Type Mask */ +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & (_UINT32_(value) << AES_CTRLA_CTYPE_Pos)) /* Assigment of value for CTYPE in the AES_CTRLA register */ +#define AES_CTRLA_Msk _UINT32_(0x000F7FFF) /* (AES_CTRLA) Register Mask */ + + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#define AES_CTRLB_RESETVALUE _UINT8_(0x00) /* (AES_CTRLB) Control B Reset Value */ + +#define AES_CTRLB_START_Pos _UINT8_(0) /* (AES_CTRLB) Start Encryption/Decryption Position */ +#define AES_CTRLB_START_Msk (_UINT8_(0x1) << AES_CTRLB_START_Pos) /* (AES_CTRLB) Start Encryption/Decryption Mask */ +#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & (_UINT8_(value) << AES_CTRLB_START_Pos)) /* Assigment of value for START in the AES_CTRLB register */ +#define AES_CTRLB_NEWMSG_Pos _UINT8_(1) /* (AES_CTRLB) New message Position */ +#define AES_CTRLB_NEWMSG_Msk (_UINT8_(0x1) << AES_CTRLB_NEWMSG_Pos) /* (AES_CTRLB) New message Mask */ +#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & (_UINT8_(value) << AES_CTRLB_NEWMSG_Pos)) /* Assigment of value for NEWMSG in the AES_CTRLB register */ +#define AES_CTRLB_EOM_Pos _UINT8_(2) /* (AES_CTRLB) End of message Position */ +#define AES_CTRLB_EOM_Msk (_UINT8_(0x1) << AES_CTRLB_EOM_Pos) /* (AES_CTRLB) End of message Mask */ +#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & (_UINT8_(value) << AES_CTRLB_EOM_Pos)) /* Assigment of value for EOM in the AES_CTRLB register */ +#define AES_CTRLB_GFMUL_Pos _UINT8_(3) /* (AES_CTRLB) GF Multiplication Position */ +#define AES_CTRLB_GFMUL_Msk (_UINT8_(0x1) << AES_CTRLB_GFMUL_Pos) /* (AES_CTRLB) GF Multiplication Mask */ +#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & (_UINT8_(value) << AES_CTRLB_GFMUL_Pos)) /* Assigment of value for GFMUL in the AES_CTRLB register */ +#define AES_CTRLB_Msk _UINT8_(0x0F) /* (AES_CTRLB) Register Mask */ + + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#define AES_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AES_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AES_INTENCLR_ENCCMP_Pos _UINT8_(0) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ +#define AES_INTENCLR_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_ENCCMP_Pos) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & (_UINT8_(value) << AES_INTENCLR_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENCLR register */ +#define AES_INTENCLR_GFMCMP_Pos _UINT8_(1) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENCLR_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_GFMCMP_Pos) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & (_UINT8_(value) << AES_INTENCLR_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENCLR register */ +#define AES_INTENCLR_Msk _UINT8_(0x03) /* (AES_INTENCLR) Register Mask */ + + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#define AES_INTENSET_RESETVALUE _UINT8_(0x00) /* (AES_INTENSET) Interrupt Enable Set Reset Value */ + +#define AES_INTENSET_ENCCMP_Pos _UINT8_(0) /* (AES_INTENSET) Encryption Complete Interrupt Enable Position */ +#define AES_INTENSET_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENSET_ENCCMP_Pos) /* (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & (_UINT8_(value) << AES_INTENSET_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENSET register */ +#define AES_INTENSET_GFMCMP_Pos _UINT8_(1) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENSET_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENSET_GFMCMP_Pos) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & (_UINT8_(value) << AES_INTENSET_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENSET register */ +#define AES_INTENSET_Msk _UINT8_(0x03) /* (AES_INTENSET) Register Mask */ + + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#define AES_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AES_INTFLAG) Interrupt Flag Status Reset Value */ + +#define AES_INTFLAG_ENCCMP_Pos _UINT8_(0) /* (AES_INTFLAG) Encryption Complete Position */ +#define AES_INTFLAG_ENCCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_ENCCMP_Pos) /* (AES_INTFLAG) Encryption Complete Mask */ +#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & (_UINT8_(value) << AES_INTFLAG_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTFLAG register */ +#define AES_INTFLAG_GFMCMP_Pos _UINT8_(1) /* (AES_INTFLAG) GF Multiplication Complete Position */ +#define AES_INTFLAG_GFMCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_GFMCMP_Pos) /* (AES_INTFLAG) GF Multiplication Complete Mask */ +#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & (_UINT8_(value) << AES_INTFLAG_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTFLAG register */ +#define AES_INTFLAG_Msk _UINT8_(0x03) /* (AES_INTFLAG) Register Mask */ + + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#define AES_DATABUFPTR_RESETVALUE _UINT8_(0x00) /* (AES_DATABUFPTR) Data buffer pointer Reset Value */ + +#define AES_DATABUFPTR_INDATAPTR_Pos _UINT8_(0) /* (AES_DATABUFPTR) Input Data Pointer Position */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_UINT8_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /* (AES_DATABUFPTR) Input Data Pointer Mask */ +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & (_UINT8_(value) << AES_DATABUFPTR_INDATAPTR_Pos)) /* Assigment of value for INDATAPTR in the AES_DATABUFPTR register */ +#define AES_DATABUFPTR_Msk _UINT8_(0x03) /* (AES_DATABUFPTR) Register Mask */ + + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#define AES_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AES_DBGCTRL) Debug control Reset Value */ + +#define AES_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AES_DBGCTRL) Debug Run Position */ +#define AES_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /* (AES_DBGCTRL) Debug Run Mask */ +#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AES_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AES_DBGCTRL register */ +#define AES_DBGCTRL_Msk _UINT8_(0x01) /* (AES_DBGCTRL) Register Mask */ + + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#define AES_KEYWORD_RESETVALUE _UINT32_(0x00) /* (AES_KEYWORD) Keyword n Reset Value */ + +#define AES_KEYWORD_KEYWORD_Pos _UINT32_(0) /* (AES_KEYWORD) Key Word Value Position */ +#define AES_KEYWORD_KEYWORD_Msk (_UINT32_(0xFFFFFFFF) << AES_KEYWORD_KEYWORD_Pos) /* (AES_KEYWORD) Key Word Value Mask */ +#define AES_KEYWORD_KEYWORD(value) (AES_KEYWORD_KEYWORD_Msk & (_UINT32_(value) << AES_KEYWORD_KEYWORD_Pos)) /* Assigment of value for KEYWORD in the AES_KEYWORD register */ +#define AES_KEYWORD_Msk _UINT32_(0xFFFFFFFF) /* (AES_KEYWORD) Register Mask */ + + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#define AES_INDATA_RESETVALUE _UINT32_(0x00) /* (AES_INDATA) Indata Reset Value */ + +#define AES_INDATA_INDATA_Pos _UINT32_(0) /* (AES_INDATA) Data Value Position */ +#define AES_INDATA_INDATA_Msk (_UINT32_(0xFFFFFFFF) << AES_INDATA_INDATA_Pos) /* (AES_INDATA) Data Value Mask */ +#define AES_INDATA_INDATA(value) (AES_INDATA_INDATA_Msk & (_UINT32_(value) << AES_INDATA_INDATA_Pos)) /* Assigment of value for INDATA in the AES_INDATA register */ +#define AES_INDATA_Msk _UINT32_(0xFFFFFFFF) /* (AES_INDATA) Register Mask */ + + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#define AES_INTVECTV_RESETVALUE _UINT32_(0x00) /* (AES_INTVECTV) Initialisation Vector n Reset Value */ + +#define AES_INTVECTV_INTVECTV_Pos _UINT32_(0) /* (AES_INTVECTV) Initialization Vector Value Position */ +#define AES_INTVECTV_INTVECTV_Msk (_UINT32_(0xFFFFFFFF) << AES_INTVECTV_INTVECTV_Pos) /* (AES_INTVECTV) Initialization Vector Value Mask */ +#define AES_INTVECTV_INTVECTV(value) (AES_INTVECTV_INTVECTV_Msk & (_UINT32_(value) << AES_INTVECTV_INTVECTV_Pos)) /* Assigment of value for INTVECTV in the AES_INTVECTV register */ +#define AES_INTVECTV_Msk _UINT32_(0xFFFFFFFF) /* (AES_INTVECTV) Register Mask */ + + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#define AES_HASHKEY_RESETVALUE _UINT32_(0x00) /* (AES_HASHKEY) Hash key n Reset Value */ + +#define AES_HASHKEY_HASHKEY_Pos _UINT32_(0) /* (AES_HASHKEY) Hash Key Value Position */ +#define AES_HASHKEY_HASHKEY_Msk (_UINT32_(0xFFFFFFFF) << AES_HASHKEY_HASHKEY_Pos) /* (AES_HASHKEY) Hash Key Value Mask */ +#define AES_HASHKEY_HASHKEY(value) (AES_HASHKEY_HASHKEY_Msk & (_UINT32_(value) << AES_HASHKEY_HASHKEY_Pos)) /* Assigment of value for HASHKEY in the AES_HASHKEY register */ +#define AES_HASHKEY_Msk _UINT32_(0xFFFFFFFF) /* (AES_HASHKEY) Register Mask */ + + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#define AES_GHASH_RESETVALUE _UINT32_(0x00) /* (AES_GHASH) Galois Hash n Reset Value */ + +#define AES_GHASH_GHASH_Pos _UINT32_(0) /* (AES_GHASH) Galois Hash Value Position */ +#define AES_GHASH_GHASH_Msk (_UINT32_(0xFFFFFFFF) << AES_GHASH_GHASH_Pos) /* (AES_GHASH) Galois Hash Value Mask */ +#define AES_GHASH_GHASH(value) (AES_GHASH_GHASH_Msk & (_UINT32_(value) << AES_GHASH_GHASH_Pos)) /* Assigment of value for GHASH in the AES_GHASH register */ +#define AES_GHASH_Msk _UINT32_(0xFFFFFFFF) /* (AES_GHASH) Register Mask */ + + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#define AES_CIPLEN_RESETVALUE _UINT32_(0x00) /* (AES_CIPLEN) Cipher Length Reset Value */ + +#define AES_CIPLEN_CIPLEN_Pos _UINT32_(0) /* (AES_CIPLEN) Cipher Length Position */ +#define AES_CIPLEN_CIPLEN_Msk (_UINT32_(0xFFFFFFFF) << AES_CIPLEN_CIPLEN_Pos) /* (AES_CIPLEN) Cipher Length Mask */ +#define AES_CIPLEN_CIPLEN(value) (AES_CIPLEN_CIPLEN_Msk & (_UINT32_(value) << AES_CIPLEN_CIPLEN_Pos)) /* Assigment of value for CIPLEN in the AES_CIPLEN register */ +#define AES_CIPLEN_Msk _UINT32_(0xFFFFFFFF) /* (AES_CIPLEN) Register Mask */ + + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#define AES_RANDSEED_RESETVALUE _UINT32_(0x00) /* (AES_RANDSEED) Random Seed Reset Value */ + +#define AES_RANDSEED_RANDSEED_Pos _UINT32_(0) /* (AES_RANDSEED) Random Seed Position */ +#define AES_RANDSEED_RANDSEED_Msk (_UINT32_(0xFFFFFFFF) << AES_RANDSEED_RANDSEED_Pos) /* (AES_RANDSEED) Random Seed Mask */ +#define AES_RANDSEED_RANDSEED(value) (AES_RANDSEED_RANDSEED_Msk & (_UINT32_(value) << AES_RANDSEED_RANDSEED_Pos)) /* Assigment of value for RANDSEED in the AES_RANDSEED register */ +#define AES_RANDSEED_Msk _UINT32_(0xFFFFFFFF) /* (AES_RANDSEED) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CTRLA_REG_OFST _UINT32_(0x00) /* (AES_CTRLA) Control A Offset */ +#define AES_CTRLB_REG_OFST _UINT32_(0x04) /* (AES_CTRLB) Control B Offset */ +#define AES_INTENCLR_REG_OFST _UINT32_(0x05) /* (AES_INTENCLR) Interrupt Enable Clear Offset */ +#define AES_INTENSET_REG_OFST _UINT32_(0x06) /* (AES_INTENSET) Interrupt Enable Set Offset */ +#define AES_INTFLAG_REG_OFST _UINT32_(0x07) /* (AES_INTFLAG) Interrupt Flag Status Offset */ +#define AES_DATABUFPTR_REG_OFST _UINT32_(0x08) /* (AES_DATABUFPTR) Data buffer pointer Offset */ +#define AES_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AES_DBGCTRL) Debug control Offset */ +#define AES_KEYWORD_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD) Keyword n Offset */ +#define AES_KEYWORD0_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD0) Keyword n Offset */ +#define AES_KEYWORD1_REG_OFST _UINT32_(0x10) /* (AES_KEYWORD1) Keyword n Offset */ +#define AES_KEYWORD2_REG_OFST _UINT32_(0x14) /* (AES_KEYWORD2) Keyword n Offset */ +#define AES_KEYWORD3_REG_OFST _UINT32_(0x18) /* (AES_KEYWORD3) Keyword n Offset */ +#define AES_KEYWORD4_REG_OFST _UINT32_(0x1C) /* (AES_KEYWORD4) Keyword n Offset */ +#define AES_KEYWORD5_REG_OFST _UINT32_(0x20) /* (AES_KEYWORD5) Keyword n Offset */ +#define AES_KEYWORD6_REG_OFST _UINT32_(0x24) /* (AES_KEYWORD6) Keyword n Offset */ +#define AES_KEYWORD7_REG_OFST _UINT32_(0x28) /* (AES_KEYWORD7) Keyword n Offset */ +#define AES_INDATA_REG_OFST _UINT32_(0x38) /* (AES_INDATA) Indata Offset */ +#define AES_INTVECTV_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV) Initialisation Vector n Offset */ +#define AES_INTVECTV0_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV0) Initialisation Vector n Offset */ +#define AES_INTVECTV1_REG_OFST _UINT32_(0x40) /* (AES_INTVECTV1) Initialisation Vector n Offset */ +#define AES_INTVECTV2_REG_OFST _UINT32_(0x44) /* (AES_INTVECTV2) Initialisation Vector n Offset */ +#define AES_INTVECTV3_REG_OFST _UINT32_(0x48) /* (AES_INTVECTV3) Initialisation Vector n Offset */ +#define AES_HASHKEY_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY) Hash key n Offset */ +#define AES_HASHKEY0_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY0) Hash key n Offset */ +#define AES_HASHKEY1_REG_OFST _UINT32_(0x60) /* (AES_HASHKEY1) Hash key n Offset */ +#define AES_HASHKEY2_REG_OFST _UINT32_(0x64) /* (AES_HASHKEY2) Hash key n Offset */ +#define AES_HASHKEY3_REG_OFST _UINT32_(0x68) /* (AES_HASHKEY3) Hash key n Offset */ +#define AES_GHASH_REG_OFST _UINT32_(0x6C) /* (AES_GHASH) Galois Hash n Offset */ +#define AES_GHASH0_REG_OFST _UINT32_(0x6C) /* (AES_GHASH0) Galois Hash n Offset */ +#define AES_GHASH1_REG_OFST _UINT32_(0x70) /* (AES_GHASH1) Galois Hash n Offset */ +#define AES_GHASH2_REG_OFST _UINT32_(0x74) /* (AES_GHASH2) Galois Hash n Offset */ +#define AES_GHASH3_REG_OFST _UINT32_(0x78) /* (AES_GHASH3) Galois Hash n Offset */ +#define AES_CIPLEN_REG_OFST _UINT32_(0x80) /* (AES_CIPLEN) Cipher Length Offset */ +#define AES_RANDSEED_REG_OFST _UINT32_(0x84) /* (AES_RANDSEED) Random Seed Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ /* Advanced Encryption Standard */ + __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ + __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ + __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ + __I uint8_t Reserved1[0x02]; + __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ + __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ + __I uint8_t Reserved3[0x10]; + __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ + __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ + __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_AES_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/can.h b/firmware/src/packs/ATSAME51J19A_DFP/component/can.h new file mode 100644 index 0000000..59a6956 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/can.h @@ -0,0 +1,2522 @@ +/* + * Component description for CAN + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_CAN_COMPONENT_H_ +#define _SAME51_CAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assigment of value for EFC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assigment of value for TXTS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assigment of value for ET in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assigment of value for SFID2 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assigment of value for SFID1 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assigment of value for SFEC in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assigment of value for SFT in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assigment of value for EFID1 in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assigment of value for EFEC in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assigment of value for EFID2 in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assigment of value for EFT in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assigment of value for SUBSTEP in the CAN_CREL register */ +#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assigment of value for STEP in the CAN_CREL register */ +#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assigment of value for REL in the CAN_CREL register */ +#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assigment of value for ETV in the CAN_ENDN register */ +#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assigment of value for QOS in the CAN_MRCFG register */ +#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assigment of value for DSJW in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assigment of value for DTSEG2 in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assigment of value for DTSEG1 in the CAN_DBTP register */ +#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assigment of value for DBRP in the CAN_DBTP register */ +#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assigment of value for TDC in the CAN_DBTP register */ +#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assigment of value for LBCK in the CAN_TEST register */ +#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assigment of value for TX in the CAN_TEST register */ +#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assigment of value for RX in the CAN_TEST register */ +#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assigment of value for WDC in the CAN_RWD register */ +#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assigment of value for WDV in the CAN_RWD register */ +#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assigment of value for INIT in the CAN_CCCR register */ +#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assigment of value for CCE in the CAN_CCCR register */ +#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assigment of value for ASM in the CAN_CCCR register */ +#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assigment of value for CSA in the CAN_CCCR register */ +#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assigment of value for CSR in the CAN_CCCR register */ +#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assigment of value for MON in the CAN_CCCR register */ +#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assigment of value for DAR in the CAN_CCCR register */ +#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assigment of value for TEST in the CAN_CCCR register */ +#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assigment of value for FDOE in the CAN_CCCR register */ +#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assigment of value for BRSE in the CAN_CCCR register */ +#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assigment of value for PXHD in the CAN_CCCR register */ +#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assigment of value for EFBI in the CAN_CCCR register */ +#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assigment of value for TXP in the CAN_CCCR register */ +#define CAN_CCCR_Msk _UINT32_(0x000073FF) /* (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assigment of value for NTSEG2 in the CAN_NBTP register */ +#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assigment of value for NTSEG1 in the CAN_NBTP register */ +#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assigment of value for NBRP in the CAN_NBTP register */ +#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assigment of value for NSJW in the CAN_NBTP register */ +#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assigment of value for TSS in the CAN_TSCC register */ +#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assigment of value for TCP in the CAN_TSCC register */ +#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assigment of value for TSC in the CAN_TSCV register */ +#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assigment of value for ETOC in the CAN_TOCC register */ +#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assigment of value for TOS in the CAN_TOCC register */ +#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assigment of value for TOP in the CAN_TOCC register */ +#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assigment of value for TOC in the CAN_TOCV register */ +#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assigment of value for TEC in the CAN_ECR register */ +#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assigment of value for REC in the CAN_ECR register */ +#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assigment of value for RP in the CAN_ECR register */ +#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assigment of value for CEL in the CAN_ECR register */ +#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assigment of value for LEC in the CAN_PSR register */ +#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assigment of value for ACT in the CAN_PSR register */ +#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assigment of value for EP in the CAN_PSR register */ +#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assigment of value for EW in the CAN_PSR register */ +#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assigment of value for BO in the CAN_PSR register */ +#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assigment of value for DLEC in the CAN_PSR register */ +#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assigment of value for RESI in the CAN_PSR register */ +#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assigment of value for RBRS in the CAN_PSR register */ +#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assigment of value for RFDF in the CAN_PSR register */ +#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assigment of value for PXE in the CAN_PSR register */ +#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assigment of value for TDCV in the CAN_PSR register */ +#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assigment of value for TDCF in the CAN_TDCR register */ +#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assigment of value for TDCO in the CAN_TDCR register */ +#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assigment of value for RF0N in the CAN_IR register */ +#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assigment of value for RF0W in the CAN_IR register */ +#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assigment of value for RF0F in the CAN_IR register */ +#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_IR register */ +#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assigment of value for RF1N in the CAN_IR register */ +#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assigment of value for RF1W in the CAN_IR register */ +#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assigment of value for RF1F in the CAN_IR register */ +#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_IR register */ +#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assigment of value for HPM in the CAN_IR register */ +#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assigment of value for TC in the CAN_IR register */ +#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assigment of value for TCF in the CAN_IR register */ +#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assigment of value for TFE in the CAN_IR register */ +#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assigment of value for TEFN in the CAN_IR register */ +#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assigment of value for TEFW in the CAN_IR register */ +#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assigment of value for TEFF in the CAN_IR register */ +#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_IR register */ +#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assigment of value for TSW in the CAN_IR register */ +#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assigment of value for MRAF in the CAN_IR register */ +#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assigment of value for TOO in the CAN_IR register */ +#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assigment of value for DRX in the CAN_IR register */ +#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assigment of value for BEC in the CAN_IR register */ +#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assigment of value for BEU in the CAN_IR register */ +#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assigment of value for ELO in the CAN_IR register */ +#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assigment of value for EP in the CAN_IR register */ +#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assigment of value for EW in the CAN_IR register */ +#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assigment of value for BO in the CAN_IR register */ +#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assigment of value for WDI in the CAN_IR register */ +#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assigment of value for PEA in the CAN_IR register */ +#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assigment of value for PED in the CAN_IR register */ +#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assigment of value for ARA in the CAN_IR register */ +#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assigment of value for RF0NE in the CAN_IE register */ +#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assigment of value for RF0WE in the CAN_IE register */ +#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assigment of value for RF0FE in the CAN_IE register */ +#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assigment of value for RF0LE in the CAN_IE register */ +#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assigment of value for RF1NE in the CAN_IE register */ +#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assigment of value for RF1WE in the CAN_IE register */ +#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assigment of value for RF1FE in the CAN_IE register */ +#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assigment of value for RF1LE in the CAN_IE register */ +#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assigment of value for HPME in the CAN_IE register */ +#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assigment of value for TCE in the CAN_IE register */ +#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assigment of value for TCFE in the CAN_IE register */ +#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assigment of value for TFEE in the CAN_IE register */ +#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assigment of value for TEFNE in the CAN_IE register */ +#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assigment of value for TEFWE in the CAN_IE register */ +#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assigment of value for TEFFE in the CAN_IE register */ +#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assigment of value for TEFLE in the CAN_IE register */ +#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assigment of value for TSWE in the CAN_IE register */ +#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assigment of value for MRAFE in the CAN_IE register */ +#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assigment of value for TOOE in the CAN_IE register */ +#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assigment of value for DRXE in the CAN_IE register */ +#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assigment of value for BECE in the CAN_IE register */ +#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assigment of value for BEUE in the CAN_IE register */ +#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assigment of value for ELOE in the CAN_IE register */ +#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assigment of value for EPE in the CAN_IE register */ +#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assigment of value for EWE in the CAN_IE register */ +#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assigment of value for BOE in the CAN_IE register */ +#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assigment of value for WDIE in the CAN_IE register */ +#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assigment of value for PEAE in the CAN_IE register */ +#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assigment of value for PEDE in the CAN_IE register */ +#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assigment of value for ARAE in the CAN_IE register */ +#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assigment of value for RF0NL in the CAN_ILS register */ +#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assigment of value for RF0WL in the CAN_ILS register */ +#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assigment of value for RF0FL in the CAN_ILS register */ +#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assigment of value for RF0LL in the CAN_ILS register */ +#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assigment of value for RF1NL in the CAN_ILS register */ +#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assigment of value for RF1WL in the CAN_ILS register */ +#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assigment of value for RF1FL in the CAN_ILS register */ +#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assigment of value for RF1LL in the CAN_ILS register */ +#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assigment of value for HPML in the CAN_ILS register */ +#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assigment of value for TCL in the CAN_ILS register */ +#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assigment of value for TCFL in the CAN_ILS register */ +#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assigment of value for TFEL in the CAN_ILS register */ +#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assigment of value for TEFNL in the CAN_ILS register */ +#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assigment of value for TEFWL in the CAN_ILS register */ +#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assigment of value for TEFFL in the CAN_ILS register */ +#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assigment of value for TEFLL in the CAN_ILS register */ +#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assigment of value for TSWL in the CAN_ILS register */ +#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assigment of value for MRAFL in the CAN_ILS register */ +#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assigment of value for TOOL in the CAN_ILS register */ +#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assigment of value for DRXL in the CAN_ILS register */ +#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assigment of value for BECL in the CAN_ILS register */ +#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assigment of value for BEUL in the CAN_ILS register */ +#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assigment of value for ELOL in the CAN_ILS register */ +#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assigment of value for EPL in the CAN_ILS register */ +#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assigment of value for EWL in the CAN_ILS register */ +#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assigment of value for BOL in the CAN_ILS register */ +#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assigment of value for WDIL in the CAN_ILS register */ +#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assigment of value for PEAL in the CAN_ILS register */ +#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assigment of value for PEDL in the CAN_ILS register */ +#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assigment of value for ARAL in the CAN_ILS register */ +#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assigment of value for EINT0 in the CAN_ILE register */ +#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assigment of value for EINT1 in the CAN_ILE register */ +#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assigment of value for RRFE in the CAN_GFC register */ +#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assigment of value for RRFS in the CAN_GFC register */ +#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assigment of value for ANFE in the CAN_GFC register */ +#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assigment of value for ANFS in the CAN_GFC register */ +#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assigment of value for FLSSA in the CAN_SIDFC register */ +#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assigment of value for LSS in the CAN_SIDFC register */ +#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assigment of value for FLESA in the CAN_XIDFC register */ +#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assigment of value for LSE in the CAN_XIDFC register */ +#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assigment of value for EIDM in the CAN_XIDAM register */ +#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assigment of value for BIDX in the CAN_HPMS register */ +#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assigment of value for MSI in the CAN_HPMS register */ +#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_HPMS register */ +#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assigment of value for FLST in the CAN_HPMS register */ +#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assigment of value for ND0 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assigment of value for ND1 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assigment of value for ND2 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assigment of value for ND3 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assigment of value for ND4 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assigment of value for ND5 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assigment of value for ND6 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assigment of value for ND7 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assigment of value for ND8 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assigment of value for ND9 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assigment of value for ND10 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assigment of value for ND11 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assigment of value for ND12 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assigment of value for ND13 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assigment of value for ND14 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assigment of value for ND15 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assigment of value for ND16 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assigment of value for ND17 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assigment of value for ND18 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assigment of value for ND19 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assigment of value for ND20 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assigment of value for ND21 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assigment of value for ND22 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assigment of value for ND23 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assigment of value for ND24 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assigment of value for ND25 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assigment of value for ND26 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assigment of value for ND27 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assigment of value for ND28 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assigment of value for ND29 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assigment of value for ND30 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assigment of value for ND31 in the CAN_NDAT1 register */ +#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assigment of value for ND32 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assigment of value for ND33 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assigment of value for ND34 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assigment of value for ND35 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assigment of value for ND36 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assigment of value for ND37 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assigment of value for ND38 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assigment of value for ND39 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assigment of value for ND40 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assigment of value for ND41 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assigment of value for ND42 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assigment of value for ND43 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assigment of value for ND44 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assigment of value for ND45 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assigment of value for ND46 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assigment of value for ND47 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assigment of value for ND48 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assigment of value for ND49 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assigment of value for ND50 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assigment of value for ND51 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assigment of value for ND52 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assigment of value for ND53 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assigment of value for ND54 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assigment of value for ND55 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assigment of value for ND56 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assigment of value for ND57 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assigment of value for ND58 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assigment of value for ND59 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assigment of value for ND60 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assigment of value for ND61 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assigment of value for ND62 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assigment of value for ND63 in the CAN_NDAT2 register */ +#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assigment of value for F0SA in the CAN_RXF0C register */ +#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assigment of value for F0S in the CAN_RXF0C register */ +#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assigment of value for F0WM in the CAN_RXF0C register */ +#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assigment of value for F0OM in the CAN_RXF0C register */ +#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assigment of value for F0FL in the CAN_RXF0S register */ +#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assigment of value for F0GI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assigment of value for F0PI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assigment of value for F0F in the CAN_RXF0S register */ +#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_RXF0S register */ +#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assigment of value for F0AI in the CAN_RXF0A register */ +#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assigment of value for RBSA in the CAN_RXBC register */ +#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assigment of value for F1SA in the CAN_RXF1C register */ +#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assigment of value for F1S in the CAN_RXF1C register */ +#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assigment of value for F1WM in the CAN_RXF1C register */ +#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assigment of value for F1OM in the CAN_RXF1C register */ +#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assigment of value for F1FL in the CAN_RXF1S register */ +#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assigment of value for F1GI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assigment of value for F1PI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assigment of value for F1F in the CAN_RXF1S register */ +#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assigment of value for DMS in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assigment of value for F1AI in the CAN_RXF1A register */ +#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assigment of value for F0DS in the CAN_RXESC register */ +#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assigment of value for F1DS in the CAN_RXESC register */ +#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assigment of value for RBDS in the CAN_RXESC register */ +#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assigment of value for TBSA in the CAN_TXBC register */ +#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assigment of value for NDTB in the CAN_TXBC register */ +#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assigment of value for TFQS in the CAN_TXBC register */ +#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assigment of value for TFQM in the CAN_TXBC register */ +#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assigment of value for TFFL in the CAN_TXFQS register */ +#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assigment of value for TFGI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assigment of value for TFQPI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assigment of value for TFQF in the CAN_TXFQS register */ +#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assigment of value for TBDS in the CAN_TXESC register */ +#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assigment of value for TRP0 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assigment of value for TRP1 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assigment of value for TRP2 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assigment of value for TRP3 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assigment of value for TRP4 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assigment of value for TRP5 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assigment of value for TRP6 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assigment of value for TRP7 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assigment of value for TRP8 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assigment of value for TRP9 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assigment of value for TRP10 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assigment of value for TRP11 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assigment of value for TRP12 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assigment of value for TRP13 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assigment of value for TRP14 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assigment of value for TRP15 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assigment of value for TRP16 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assigment of value for TRP17 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assigment of value for TRP18 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assigment of value for TRP19 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assigment of value for TRP20 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assigment of value for TRP21 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assigment of value for TRP22 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assigment of value for TRP23 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assigment of value for TRP24 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assigment of value for TRP25 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assigment of value for TRP26 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assigment of value for TRP27 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assigment of value for TRP28 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assigment of value for TRP29 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assigment of value for TRP30 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assigment of value for TRP31 in the CAN_TXBRP register */ +#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assigment of value for AR0 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assigment of value for AR1 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assigment of value for AR2 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assigment of value for AR3 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assigment of value for AR4 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assigment of value for AR5 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assigment of value for AR6 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assigment of value for AR7 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assigment of value for AR8 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assigment of value for AR9 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assigment of value for AR10 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assigment of value for AR11 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assigment of value for AR12 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assigment of value for AR13 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assigment of value for AR14 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assigment of value for AR15 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assigment of value for AR16 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assigment of value for AR17 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assigment of value for AR18 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assigment of value for AR19 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assigment of value for AR20 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assigment of value for AR21 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assigment of value for AR22 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assigment of value for AR23 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assigment of value for AR24 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assigment of value for AR25 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assigment of value for AR26 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assigment of value for AR27 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assigment of value for AR28 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assigment of value for AR29 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assigment of value for AR30 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assigment of value for AR31 in the CAN_TXBAR register */ +#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assigment of value for CR0 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assigment of value for CR1 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assigment of value for CR2 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assigment of value for CR3 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assigment of value for CR4 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assigment of value for CR5 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assigment of value for CR6 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assigment of value for CR7 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assigment of value for CR8 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assigment of value for CR9 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assigment of value for CR10 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assigment of value for CR11 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assigment of value for CR12 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assigment of value for CR13 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assigment of value for CR14 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assigment of value for CR15 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assigment of value for CR16 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assigment of value for CR17 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assigment of value for CR18 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assigment of value for CR19 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assigment of value for CR20 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assigment of value for CR21 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assigment of value for CR22 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assigment of value for CR23 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assigment of value for CR24 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assigment of value for CR25 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assigment of value for CR26 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assigment of value for CR27 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assigment of value for CR28 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assigment of value for CR29 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assigment of value for CR30 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assigment of value for CR31 in the CAN_TXBCR register */ +#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assigment of value for TO0 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assigment of value for TO1 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assigment of value for TO2 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assigment of value for TO3 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assigment of value for TO4 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assigment of value for TO5 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assigment of value for TO6 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assigment of value for TO7 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assigment of value for TO8 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assigment of value for TO9 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assigment of value for TO10 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assigment of value for TO11 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assigment of value for TO12 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assigment of value for TO13 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assigment of value for TO14 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assigment of value for TO15 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assigment of value for TO16 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assigment of value for TO17 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assigment of value for TO18 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assigment of value for TO19 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assigment of value for TO20 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assigment of value for TO21 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assigment of value for TO22 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assigment of value for TO23 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assigment of value for TO24 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assigment of value for TO25 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assigment of value for TO26 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assigment of value for TO27 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assigment of value for TO28 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assigment of value for TO29 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assigment of value for TO30 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assigment of value for TO31 in the CAN_TXBTO register */ +#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assigment of value for CF0 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assigment of value for CF1 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assigment of value for CF2 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assigment of value for CF3 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assigment of value for CF4 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assigment of value for CF5 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assigment of value for CF6 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assigment of value for CF7 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assigment of value for CF8 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assigment of value for CF9 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assigment of value for CF10 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assigment of value for CF11 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assigment of value for CF12 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assigment of value for CF13 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assigment of value for CF14 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assigment of value for CF15 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assigment of value for CF16 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assigment of value for CF17 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assigment of value for CF18 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assigment of value for CF19 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assigment of value for CF20 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assigment of value for CF21 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assigment of value for CF22 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assigment of value for CF23 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assigment of value for CF24 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assigment of value for CF25 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assigment of value for CF26 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assigment of value for CF27 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assigment of value for CF28 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assigment of value for CF29 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assigment of value for CF30 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assigment of value for CF31 in the CAN_TXBCF register */ +#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assigment of value for TIE0 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assigment of value for TIE1 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assigment of value for TIE2 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assigment of value for TIE3 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assigment of value for TIE4 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assigment of value for TIE5 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assigment of value for TIE6 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assigment of value for TIE7 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assigment of value for TIE8 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assigment of value for TIE9 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assigment of value for TIE10 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assigment of value for TIE11 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assigment of value for TIE12 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assigment of value for TIE13 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assigment of value for TIE14 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assigment of value for TIE15 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assigment of value for TIE16 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assigment of value for TIE17 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assigment of value for TIE18 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assigment of value for TIE19 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assigment of value for TIE20 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assigment of value for TIE21 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assigment of value for TIE22 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assigment of value for TIE23 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assigment of value for TIE24 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assigment of value for TIE25 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assigment of value for TIE26 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assigment of value for TIE27 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assigment of value for TIE28 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assigment of value for TIE29 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assigment of value for TIE30 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assigment of value for TIE31 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assigment of value for CFIE0 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assigment of value for CFIE1 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assigment of value for CFIE2 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assigment of value for CFIE3 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assigment of value for CFIE4 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assigment of value for CFIE5 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assigment of value for CFIE6 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assigment of value for CFIE7 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assigment of value for CFIE8 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assigment of value for CFIE9 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assigment of value for CFIE10 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assigment of value for CFIE11 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assigment of value for CFIE12 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assigment of value for CFIE13 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assigment of value for CFIE14 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assigment of value for CFIE15 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assigment of value for CFIE16 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assigment of value for CFIE17 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assigment of value for CFIE18 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assigment of value for CFIE19 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assigment of value for CFIE20 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assigment of value for CFIE21 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assigment of value for CFIE22 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assigment of value for CFIE23 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assigment of value for CFIE24 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assigment of value for CFIE25 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assigment of value for CFIE26 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assigment of value for CFIE27 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assigment of value for CFIE28 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assigment of value for CFIE29 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assigment of value for CFIE30 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assigment of value for CFIE31 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assigment of value for EFSA in the CAN_TXEFC register */ +#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assigment of value for EFS in the CAN_TXEFC register */ +#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assigment of value for EFWM in the CAN_TXEFC register */ +#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assigment of value for EFFL in the CAN_TXEFS register */ +#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assigment of value for EFGI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assigment of value for EFPI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assigment of value for EFF in the CAN_TXEFS register */ +#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_TXEFS register */ +#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assigment of value for EFAI in the CAN_TXEFA register */ +#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ + + +/** \brief CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_CAN_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/ccl.h b/firmware/src/packs/ATSAME51J19A_DFP/component/ccl.h new file mode 100644 index 0000000..d337e2d --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/ccl.h @@ -0,0 +1,223 @@ +/* + * Component description for CCL + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_CCL_COMPONENT_H_ +#define _SAME51_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CCL_CTRL register */ +#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_CTRL register */ +#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the CCL_CTRL register */ +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assigment of value for SEQSEL in the CCL_SEQCTRL register */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assigment of value for FILTSEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assigment of value for EDGESEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assigment of value for INSEL0 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assigment of value for INSEL1 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assigment of value for INSEL2 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assigment of value for LUTEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assigment of value for LUTEO in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assigment of value for TRUTH in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ +#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ +#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ +#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ +#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ +#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_CCL_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/cmcc.h b/firmware/src/packs/ATSAME51J19A_DFP/component/cmcc.h new file mode 100644 index 0000000..a92afd9 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/cmcc.h @@ -0,0 +1,217 @@ +/* + * Component description for CMCC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_CMCC_COMPONENT_H_ +#define _SAME51_CMCC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CMCC */ +/* ************************************************************************** */ + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ +#define CMCC_TYPE_RESETVALUE _UINT32_(0x12D2) /* (CMCC_TYPE) Cache Type Register Reset Value */ + +#define CMCC_TYPE_GCLK_Pos _UINT32_(1) /* (CMCC_TYPE) dynamic Clock Gating supported Position */ +#define CMCC_TYPE_GCLK_Msk (_UINT32_(0x1) << CMCC_TYPE_GCLK_Pos) /* (CMCC_TYPE) dynamic Clock Gating supported Mask */ +#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & (_UINT32_(value) << CMCC_TYPE_GCLK_Pos)) /* Assigment of value for GCLK in the CMCC_TYPE register */ +#define CMCC_TYPE_RRP_Pos _UINT32_(4) /* (CMCC_TYPE) Round Robin Policy supported Position */ +#define CMCC_TYPE_RRP_Msk (_UINT32_(0x1) << CMCC_TYPE_RRP_Pos) /* (CMCC_TYPE) Round Robin Policy supported Mask */ +#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & (_UINT32_(value) << CMCC_TYPE_RRP_Pos)) /* Assigment of value for RRP in the CMCC_TYPE register */ +#define CMCC_TYPE_WAYNUM_Pos _UINT32_(5) /* (CMCC_TYPE) Number of Way Position */ +#define CMCC_TYPE_WAYNUM_Msk (_UINT32_(0x3) << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) Number of Way Mask */ +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & (_UINT32_(value) << CMCC_TYPE_WAYNUM_Pos)) /* Assigment of value for WAYNUM in the CMCC_TYPE register */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _UINT32_(0x2) /* (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) 4-WAY set associative Position */ +#define CMCC_TYPE_LCKDOWN_Pos _UINT32_(7) /* (CMCC_TYPE) Lock Down supported Position */ +#define CMCC_TYPE_LCKDOWN_Msk (_UINT32_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /* (CMCC_TYPE) Lock Down supported Mask */ +#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & (_UINT32_(value) << CMCC_TYPE_LCKDOWN_Pos)) /* Assigment of value for LCKDOWN in the CMCC_TYPE register */ +#define CMCC_TYPE_CSIZE_Pos _UINT32_(8) /* (CMCC_TYPE) Cache Size Position */ +#define CMCC_TYPE_CSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size Mask */ +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CSIZE_Pos)) /* Assigment of value for CSIZE in the CMCC_TYPE register */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 1 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 2 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 4 KB Position */ +#define CMCC_TYPE_CLSIZE_Pos _UINT32_(11) /* (CMCC_TYPE) Cache Line Size Position */ +#define CMCC_TYPE_CLSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size Mask */ +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CLSIZE_Pos)) /* Assigment of value for CLSIZE in the CMCC_TYPE register */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size is 16 bytes Position */ +#define CMCC_TYPE_Msk _UINT32_(0x00003FF2) /* (CMCC_TYPE) Register Mask */ + + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#define CMCC_CFG_RESETVALUE _UINT32_(0x20) /* (CMCC_CFG) Cache Configuration Register Reset Value */ + +#define CMCC_CFG_ICDIS_Pos _UINT32_(1) /* (CMCC_CFG) Instruction Cache Disable Position */ +#define CMCC_CFG_ICDIS_Msk (_UINT32_(0x1) << CMCC_CFG_ICDIS_Pos) /* (CMCC_CFG) Instruction Cache Disable Mask */ +#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & (_UINT32_(value) << CMCC_CFG_ICDIS_Pos)) /* Assigment of value for ICDIS in the CMCC_CFG register */ +#define CMCC_CFG_DCDIS_Pos _UINT32_(2) /* (CMCC_CFG) Data Cache Disable Position */ +#define CMCC_CFG_DCDIS_Msk (_UINT32_(0x1) << CMCC_CFG_DCDIS_Pos) /* (CMCC_CFG) Data Cache Disable Mask */ +#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & (_UINT32_(value) << CMCC_CFG_DCDIS_Pos)) /* Assigment of value for DCDIS in the CMCC_CFG register */ +#define CMCC_CFG_CSIZESW_Pos _UINT32_(4) /* (CMCC_CFG) Cache size configured by software Position */ +#define CMCC_CFG_CSIZESW_Msk (_UINT32_(0x7) << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) Cache size configured by software Mask */ +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & (_UINT32_(value) << CMCC_CFG_CSIZESW_Pos)) /* Assigment of value for CSIZESW in the CMCC_CFG register */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_CFG) The Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_CFG) The Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_CFG) The Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 1KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 2KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 4KB Position */ +#define CMCC_CFG_Msk _UINT32_(0x00000076) /* (CMCC_CFG) Register Mask */ + + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#define CMCC_CTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_CTRL) Cache Control Register Reset Value */ + +#define CMCC_CTRL_CEN_Pos _UINT32_(0) /* (CMCC_CTRL) Cache Controller Enable Position */ +#define CMCC_CTRL_CEN_Msk (_UINT32_(0x1) << CMCC_CTRL_CEN_Pos) /* (CMCC_CTRL) Cache Controller Enable Mask */ +#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & (_UINT32_(value) << CMCC_CTRL_CEN_Pos)) /* Assigment of value for CEN in the CMCC_CTRL register */ +#define CMCC_CTRL_Msk _UINT32_(0x00000001) /* (CMCC_CTRL) Register Mask */ + + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ +#define CMCC_SR_RESETVALUE _UINT32_(0x00) /* (CMCC_SR) Cache Status Register Reset Value */ + +#define CMCC_SR_CSTS_Pos _UINT32_(0) /* (CMCC_SR) Cache Controller Status Position */ +#define CMCC_SR_CSTS_Msk (_UINT32_(0x1) << CMCC_SR_CSTS_Pos) /* (CMCC_SR) Cache Controller Status Mask */ +#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & (_UINT32_(value) << CMCC_SR_CSTS_Pos)) /* Assigment of value for CSTS in the CMCC_SR register */ +#define CMCC_SR_Msk _UINT32_(0x00000001) /* (CMCC_SR) Register Mask */ + + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#define CMCC_LCKWAY_RESETVALUE _UINT32_(0x00) /* (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ + +#define CMCC_LCKWAY_LCKWAY_Pos _UINT32_(0) /* (CMCC_LCKWAY) Lockdown way Register Position */ +#define CMCC_LCKWAY_LCKWAY_Msk (_UINT32_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /* (CMCC_LCKWAY) Lockdown way Register Mask */ +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & (_UINT32_(value) << CMCC_LCKWAY_LCKWAY_Pos)) /* Assigment of value for LCKWAY in the CMCC_LCKWAY register */ +#define CMCC_LCKWAY_Msk _UINT32_(0x0000000F) /* (CMCC_LCKWAY) Register Mask */ + + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#define CMCC_MAINT0_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ + +#define CMCC_MAINT0_INVALL_Pos _UINT32_(0) /* (CMCC_MAINT0) Cache Controller invalidate All Position */ +#define CMCC_MAINT0_INVALL_Msk (_UINT32_(0x1) << CMCC_MAINT0_INVALL_Pos) /* (CMCC_MAINT0) Cache Controller invalidate All Mask */ +#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & (_UINT32_(value) << CMCC_MAINT0_INVALL_Pos)) /* Assigment of value for INVALL in the CMCC_MAINT0 register */ +#define CMCC_MAINT0_Msk _UINT32_(0x00000001) /* (CMCC_MAINT0) Register Mask */ + + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#define CMCC_MAINT1_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ + +#define CMCC_MAINT1_INDEX_Pos _UINT32_(4) /* (CMCC_MAINT1) Invalidate Index Position */ +#define CMCC_MAINT1_INDEX_Msk (_UINT32_(0xFF) << CMCC_MAINT1_INDEX_Pos) /* (CMCC_MAINT1) Invalidate Index Mask */ +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & (_UINT32_(value) << CMCC_MAINT1_INDEX_Pos)) /* Assigment of value for INDEX in the CMCC_MAINT1 register */ +#define CMCC_MAINT1_WAY_Pos _UINT32_(28) /* (CMCC_MAINT1) Invalidate Way Position */ +#define CMCC_MAINT1_WAY_Msk (_UINT32_(0xF) << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Invalidate Way Mask */ +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & (_UINT32_(value) << CMCC_MAINT1_WAY_Pos)) /* Assigment of value for WAY in the CMCC_MAINT1 register */ +#define CMCC_MAINT1_WAY_WAY0_Val _UINT32_(0x0) /* (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _UINT32_(0x1) /* (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _UINT32_(0x2) /* (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _UINT32_(0x3) /* (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ +#define CMCC_MAINT1_Msk _UINT32_(0xF0000FF0) /* (CMCC_MAINT1) Register Mask */ + + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#define CMCC_MCFG_RESETVALUE _UINT32_(0x00) /* (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ + +#define CMCC_MCFG_MODE_Pos _UINT32_(0) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ +#define CMCC_MCFG_MODE_Msk (_UINT32_(0x3) << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & (_UINT32_(value) << CMCC_MCFG_MODE_Pos)) /* Assigment of value for MODE in the CMCC_MCFG register */ +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _UINT32_(0x0) /* (CMCC_MCFG) Cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _UINT32_(0x1) /* (CMCC_MCFG) Instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _UINT32_(0x2) /* (CMCC_MCFG) Data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cycle counter Position */ +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Instruction hit counter Position */ +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Data hit counter Position */ +#define CMCC_MCFG_Msk _UINT32_(0x00000003) /* (CMCC_MCFG) Register Mask */ + + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#define CMCC_MEN_RESETVALUE _UINT32_(0x00) /* (CMCC_MEN) Cache Monitor Enable Register Reset Value */ + +#define CMCC_MEN_MENABLE_Pos _UINT32_(0) /* (CMCC_MEN) Cache Controller Monitor Enable Position */ +#define CMCC_MEN_MENABLE_Msk (_UINT32_(0x1) << CMCC_MEN_MENABLE_Pos) /* (CMCC_MEN) Cache Controller Monitor Enable Mask */ +#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & (_UINT32_(value) << CMCC_MEN_MENABLE_Pos)) /* Assigment of value for MENABLE in the CMCC_MEN register */ +#define CMCC_MEN_Msk _UINT32_(0x00000001) /* (CMCC_MEN) Register Mask */ + + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#define CMCC_MCTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ + +#define CMCC_MCTRL_SWRST_Pos _UINT32_(0) /* (CMCC_MCTRL) Cache Controller Software Reset Position */ +#define CMCC_MCTRL_SWRST_Msk (_UINT32_(0x1) << CMCC_MCTRL_SWRST_Pos) /* (CMCC_MCTRL) Cache Controller Software Reset Mask */ +#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & (_UINT32_(value) << CMCC_MCTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CMCC_MCTRL register */ +#define CMCC_MCTRL_Msk _UINT32_(0x00000001) /* (CMCC_MCTRL) Register Mask */ + + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ +#define CMCC_MSR_RESETVALUE _UINT32_(0x00) /* (CMCC_MSR) Cache Monitor Status Register Reset Value */ + +#define CMCC_MSR_EVENT_CNT_Pos _UINT32_(0) /* (CMCC_MSR) Monitor Event Counter Position */ +#define CMCC_MSR_EVENT_CNT_Msk (_UINT32_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /* (CMCC_MSR) Monitor Event Counter Mask */ +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & (_UINT32_(value) << CMCC_MSR_EVENT_CNT_Pos)) /* Assigment of value for EVENT_CNT in the CMCC_MSR register */ +#define CMCC_MSR_Msk _UINT32_(0xFFFFFFFF) /* (CMCC_MSR) Register Mask */ + + +/** \brief CMCC register offsets definitions */ +#define CMCC_TYPE_REG_OFST _UINT32_(0x00) /* (CMCC_TYPE) Cache Type Register Offset */ +#define CMCC_CFG_REG_OFST _UINT32_(0x04) /* (CMCC_CFG) Cache Configuration Register Offset */ +#define CMCC_CTRL_REG_OFST _UINT32_(0x08) /* (CMCC_CTRL) Cache Control Register Offset */ +#define CMCC_SR_REG_OFST _UINT32_(0x0C) /* (CMCC_SR) Cache Status Register Offset */ +#define CMCC_LCKWAY_REG_OFST _UINT32_(0x10) /* (CMCC_LCKWAY) Cache Lock per Way Register Offset */ +#define CMCC_MAINT0_REG_OFST _UINT32_(0x20) /* (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ +#define CMCC_MAINT1_REG_OFST _UINT32_(0x24) /* (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ +#define CMCC_MCFG_REG_OFST _UINT32_(0x28) /* (CMCC_MCFG) Cache Monitor Configuration Register Offset */ +#define CMCC_MEN_REG_OFST _UINT32_(0x2C) /* (CMCC_MEN) Cache Monitor Enable Register Offset */ +#define CMCC_MCTRL_REG_OFST _UINT32_(0x30) /* (CMCC_MCTRL) Cache Monitor Control Register Offset */ +#define CMCC_MSR_REG_OFST _UINT32_(0x34) /* (CMCC_MSR) Cache Monitor Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CMCC register API structure */ +typedef struct +{ /* Cortex M Cache Controller */ + __I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */ + __IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */ + __I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */ + __IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} cmcc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_CMCC_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/dac.h b/firmware/src/packs/ATSAME51J19A_DFP/component/dac.h new file mode 100644 index 0000000..9cb1824 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/dac.h @@ -0,0 +1,447 @@ +/* + * Component description for DAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_DAC_COMPONENT_H_ +#define _SAME51_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_CTRLA register */ +#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable DAC Controller Position */ +#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable DAC Controller Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_CTRLA register */ +#define DAC_CTRLA_Msk _UINT8_(0x03) /* (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _UINT8_(0x02) /* (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_DIFF_Pos _UINT8_(0) /* (DAC_CTRLB) Differential mode enable Position */ +#define DAC_CTRLB_DIFF_Msk (_UINT8_(0x1) << DAC_CTRLB_DIFF_Pos) /* (DAC_CTRLB) Differential mode enable Mask */ +#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & (_UINT8_(value) << DAC_CTRLB_DIFF_Pos)) /* Assigment of value for DIFF in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_Pos _UINT8_(1) /* (DAC_CTRLB) Reference Selection for DAC0/1 Position */ +#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assigment of value for REFSEL in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_VREFPU_Val _UINT8_(0x0) /* (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _UINT8_(0x1) /* (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _UINT8_(0x3) /* (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference unbuffered Position */ +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Analog supply Position */ +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference buffered Position */ +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal bandgap reference Position */ +#define DAC_CTRLB_Msk _UINT8_(0x07) /* (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI0_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ +#define DAC_EVCTRL_STARTEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ +#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI0_Pos)) /* Assigment of value for STARTEI0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_STARTEI1_Pos _UINT8_(1) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ +#define DAC_EVCTRL_STARTEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ +#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI1_Pos)) /* Assigment of value for STARTEI1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO0_Pos _UINT8_(2) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ +#define DAC_EVCTRL_EMPTYEO0_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ +#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO0_Pos)) /* Assigment of value for EMPTYEO0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO1_Pos _UINT8_(3) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ +#define DAC_EVCTRL_EMPTYEO1_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ +#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO1_Pos)) /* Assigment of value for EMPTYEO1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI0_Pos _UINT8_(4) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ +#define DAC_EVCTRL_INVEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI0_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ +#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI1_Pos _UINT8_(5) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ +#define DAC_EVCTRL_INVEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI1_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ +#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_RESRDYEO0_Pos _UINT8_(6) /* (DAC_EVCTRL) Result Ready Event Output 0 Position */ +#define DAC_EVCTRL_RESRDYEO0_Msk (_UINT8_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /* (DAC_EVCTRL) Result Ready Event Output 0 Mask */ +#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO0_Pos)) /* Assigment of value for RESRDYEO0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_RESRDYEO1_Pos _UINT8_(7) /* (DAC_EVCTRL) Result Ready Event Output 1 Position */ +#define DAC_EVCTRL_RESRDYEO1_Msk (_UINT8_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /* (DAC_EVCTRL) Result Ready Event Output 1 Mask */ +#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO1_Pos)) /* Assigment of value for RESRDYEO1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_Msk _UINT8_(0xFF) /* (DAC_EVCTRL) Register Mask */ + +#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL Mask) STARTEI */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(2) /* (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL Mask) EMPTYEO */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI_Pos _UINT8_(4) /* (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL Mask) INVEI */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO_Pos _UINT8_(6) /* (DAC_EVCTRL Position) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /* (DAC_EVCTRL Mask) RESRDYEO */ +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO_Pos)) + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_RESRDY0_Pos _UINT8_(4) /* (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /* (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_RESRDY1_Pos _UINT8_(5) /* (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /* (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /* (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /* (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_Msk _UINT8_(0xFF) /* (DAC_INTENCLR) Register Mask */ + +#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR Position) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR Mask) UNDERRUN */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY_Pos _UINT8_(2) /* (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR Mask) EMPTY */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY_Pos _UINT8_(4) /* (DAC_INTENCLR Position) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_UINT8_(0x3) << DAC_INTENCLR_RESRDY_Pos) /* (DAC_INTENCLR Mask) RESRDY */ +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN_Pos _UINT8_(6) /* (DAC_INTENCLR Position) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /* (DAC_INTENCLR Mask) OVERRUN */ +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN_Pos)) + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTENSET register */ +#define DAC_INTENSET_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY0_Pos) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY1_Pos) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTENSET register */ +#define DAC_INTENSET_RESRDY0_Pos _UINT8_(4) /* (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTENSET_RESRDY0_Pos) /* (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTENSET register */ +#define DAC_INTENSET_RESRDY1_Pos _UINT8_(5) /* (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTENSET_RESRDY1_Pos) /* (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTENSET register */ +#define DAC_INTENSET_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTENSET) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /* (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTENSET register */ +#define DAC_INTENSET_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTENSET) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /* (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTENSET register */ +#define DAC_INTENSET_Msk _UINT8_(0xFF) /* (DAC_INTENSET) Register Mask */ + +#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET Position) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET Mask) UNDERRUN */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY_Pos _UINT8_(2) /* (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET Mask) EMPTY */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY_Pos _UINT8_(4) /* (DAC_INTENSET Position) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_UINT8_(0x3) << DAC_INTENSET_RESRDY_Pos) /* (DAC_INTENSET Mask) RESRDY */ +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN_Pos _UINT8_(6) /* (DAC_INTENSET Position) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTENSET_OVERRUN_Pos) /* (DAC_INTENSET Mask) OVERRUN */ +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN_Pos)) + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTFLAG) Result 0 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /* (DAC_INTFLAG) Result 0 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTFLAG) Result 1 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /* (DAC_INTFLAG) Result 1 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY0_Pos _UINT8_(2) /* (DAC_INTFLAG) Data Buffer 0 Empty Position */ +#define DAC_INTFLAG_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /* (DAC_INTFLAG) Data Buffer 0 Empty Mask */ +#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY1_Pos _UINT8_(3) /* (DAC_INTFLAG) Data Buffer 1 Empty Position */ +#define DAC_INTFLAG_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /* (DAC_INTFLAG) Data Buffer 1 Empty Mask */ +#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_RESRDY0_Pos _UINT8_(4) /* (DAC_INTFLAG) Result 0 Ready Position */ +#define DAC_INTFLAG_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /* (DAC_INTFLAG) Result 0 Ready Mask */ +#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_RESRDY1_Pos _UINT8_(5) /* (DAC_INTFLAG) Result 1 Ready Position */ +#define DAC_INTFLAG_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /* (DAC_INTFLAG) Result 1 Ready Mask */ +#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTFLAG) Result 0 Overrun Position */ +#define DAC_INTFLAG_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /* (DAC_INTFLAG) Result 0 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTFLAG) Result 1 Overrun Position */ +#define DAC_INTFLAG_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /* (DAC_INTFLAG) Result 1 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_Msk _UINT8_(0xFF) /* (DAC_INTFLAG) Register Mask */ + +#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG Position) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG Mask) UNDERRUN */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY_Pos _UINT8_(2) /* (DAC_INTFLAG Position) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x3) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG Mask) EMPTY */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY_Pos _UINT8_(4) /* (DAC_INTFLAG Position) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_UINT8_(0x3) << DAC_INTFLAG_RESRDY_Pos) /* (DAC_INTFLAG Mask) RESRDY */ +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN_Pos _UINT8_(6) /* (DAC_INTFLAG Position) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /* (DAC_INTFLAG Mask) OVERRUN */ +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN_Pos)) + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY0_Pos _UINT8_(0) /* (DAC_STATUS) DAC 0 Startup Ready Position */ +#define DAC_STATUS_READY0_Msk (_UINT8_(0x1) << DAC_STATUS_READY0_Pos) /* (DAC_STATUS) DAC 0 Startup Ready Mask */ +#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & (_UINT8_(value) << DAC_STATUS_READY0_Pos)) /* Assigment of value for READY0 in the DAC_STATUS register */ +#define DAC_STATUS_READY1_Pos _UINT8_(1) /* (DAC_STATUS) DAC 1 Startup Ready Position */ +#define DAC_STATUS_READY1_Msk (_UINT8_(0x1) << DAC_STATUS_READY1_Pos) /* (DAC_STATUS) DAC 1 Startup Ready Mask */ +#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & (_UINT8_(value) << DAC_STATUS_READY1_Pos)) /* Assigment of value for READY1 in the DAC_STATUS register */ +#define DAC_STATUS_EOC0_Pos _UINT8_(2) /* (DAC_STATUS) DAC 0 End of Conversion Position */ +#define DAC_STATUS_EOC0_Msk (_UINT8_(0x1) << DAC_STATUS_EOC0_Pos) /* (DAC_STATUS) DAC 0 End of Conversion Mask */ +#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & (_UINT8_(value) << DAC_STATUS_EOC0_Pos)) /* Assigment of value for EOC0 in the DAC_STATUS register */ +#define DAC_STATUS_EOC1_Pos _UINT8_(3) /* (DAC_STATUS) DAC 1 End of Conversion Position */ +#define DAC_STATUS_EOC1_Msk (_UINT8_(0x1) << DAC_STATUS_EOC1_Pos) /* (DAC_STATUS) DAC 1 End of Conversion Mask */ +#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & (_UINT8_(value) << DAC_STATUS_EOC1_Pos)) /* Assigment of value for EOC1 in the DAC_STATUS register */ +#define DAC_STATUS_Msk _UINT8_(0x0F) /* (DAC_STATUS) Register Mask */ + +#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS Position) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_UINT8_(0x3) << DAC_STATUS_READY_Pos) /* (DAC_STATUS Mask) READY */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC_Pos _UINT8_(2) /* (DAC_STATUS Position) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_UINT8_(0x3) << DAC_STATUS_EOC_Pos) /* (DAC_STATUS Mask) EOC */ +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & (_UINT8_(value) << DAC_STATUS_EOC_Pos)) + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) DAC Enable Status Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) DAC Enable Status Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA0_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data DAC 0 Position */ +#define DAC_SYNCBUSY_DATA0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /* (DAC_SYNCBUSY) Data DAC 0 Mask */ +#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA0_Pos)) /* Assigment of value for DATA0 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA1_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data DAC 1 Position */ +#define DAC_SYNCBUSY_DATA1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /* (DAC_SYNCBUSY) Data DAC 1 Mask */ +#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA1_Pos)) /* Assigment of value for DATA1 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF0_Pos _UINT32_(4) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ +#define DAC_SYNCBUSY_DATABUF0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ +#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF0_Pos)) /* Assigment of value for DATABUF0 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF1_Pos _UINT32_(5) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ +#define DAC_SYNCBUSY_DATABUF1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ +#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF1_Pos)) /* Assigment of value for DATABUF1 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_Msk _UINT32_(0x0000003F) /* (DAC_SYNCBUSY) Register Mask */ + +#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY Position) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY Mask) DATA */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(4) /* (DAC_SYNCBUSY Position) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY Mask) DATABUF */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#define DAC_DACCTRL_RESETVALUE _UINT16_(0x00) /* (DAC_DACCTRL) DAC n Control Reset Value */ + +#define DAC_DACCTRL_LEFTADJ_Pos _UINT16_(0) /* (DAC_DACCTRL) Left Adjusted Data Position */ +#define DAC_DACCTRL_LEFTADJ_Msk (_UINT16_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /* (DAC_DACCTRL) Left Adjusted Data Mask */ +#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & (_UINT16_(value) << DAC_DACCTRL_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the DAC_DACCTRL register */ +#define DAC_DACCTRL_ENABLE_Pos _UINT16_(1) /* (DAC_DACCTRL) Enable DAC0 Position */ +#define DAC_DACCTRL_ENABLE_Msk (_UINT16_(0x1) << DAC_DACCTRL_ENABLE_Pos) /* (DAC_DACCTRL) Enable DAC0 Mask */ +#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & (_UINT16_(value) << DAC_DACCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_DACCTRL register */ +#define DAC_DACCTRL_CCTRL_Pos _UINT16_(2) /* (DAC_DACCTRL) Current Control Position */ +#define DAC_DACCTRL_CCTRL_Msk (_UINT16_(0x3) << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) Current Control Mask */ +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & (_UINT16_(value) << DAC_DACCTRL_CCTRL_Pos)) /* Assigment of value for CCTRL in the DAC_DACCTRL register */ +#define DAC_DACCTRL_CCTRL_CC100K_Val _UINT16_(0x0) /* (DAC_DACCTRL) 100kSPS */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _UINT16_(0x1) /* (DAC_DACCTRL) 500kSPS */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _UINT16_(0x2) /* (DAC_DACCTRL) 1MSPS */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 100kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 500kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 1MSPS Position */ +#define DAC_DACCTRL_FEXT_Pos _UINT16_(5) /* (DAC_DACCTRL) Standalone Filter Position */ +#define DAC_DACCTRL_FEXT_Msk (_UINT16_(0x1) << DAC_DACCTRL_FEXT_Pos) /* (DAC_DACCTRL) Standalone Filter Mask */ +#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & (_UINT16_(value) << DAC_DACCTRL_FEXT_Pos)) /* Assigment of value for FEXT in the DAC_DACCTRL register */ +#define DAC_DACCTRL_RUNSTDBY_Pos _UINT16_(6) /* (DAC_DACCTRL) Run in Standby Position */ +#define DAC_DACCTRL_RUNSTDBY_Msk (_UINT16_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /* (DAC_DACCTRL) Run in Standby Mask */ +#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & (_UINT16_(value) << DAC_DACCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the DAC_DACCTRL register */ +#define DAC_DACCTRL_DITHER_Pos _UINT16_(7) /* (DAC_DACCTRL) Dithering Mode Position */ +#define DAC_DACCTRL_DITHER_Msk (_UINT16_(0x1) << DAC_DACCTRL_DITHER_Pos) /* (DAC_DACCTRL) Dithering Mode Mask */ +#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & (_UINT16_(value) << DAC_DACCTRL_DITHER_Pos)) /* Assigment of value for DITHER in the DAC_DACCTRL register */ +#define DAC_DACCTRL_REFRESH_Pos _UINT16_(8) /* (DAC_DACCTRL) Refresh period Position */ +#define DAC_DACCTRL_REFRESH_Msk (_UINT16_(0xF) << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh period Mask */ +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & (_UINT16_(value) << DAC_DACCTRL_REFRESH_Pos)) /* Assigment of value for REFRESH in the DAC_DACCTRL register */ +#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _UINT16_(0x0) /* (DAC_DACCTRL) Do not Refresh */ +#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _UINT16_(0x1) /* (DAC_DACCTRL) Refresh every 30 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _UINT16_(0x2) /* (DAC_DACCTRL) Refresh every 60 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _UINT16_(0x3) /* (DAC_DACCTRL) Refresh every 90 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _UINT16_(0x4) /* (DAC_DACCTRL) Refresh every 120 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _UINT16_(0x5) /* (DAC_DACCTRL) Refresh every 150 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _UINT16_(0x6) /* (DAC_DACCTRL) Refresh every 180 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _UINT16_(0x7) /* (DAC_DACCTRL) Refresh every 210 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _UINT16_(0x8) /* (DAC_DACCTRL) Refresh every 240 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _UINT16_(0x9) /* (DAC_DACCTRL) Refresh every 270 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _UINT16_(0xA) /* (DAC_DACCTRL) Refresh every 300 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _UINT16_(0xB) /* (DAC_DACCTRL) Refresh every 330 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _UINT16_(0xC) /* (DAC_DACCTRL) Refresh every 360 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _UINT16_(0xD) /* (DAC_DACCTRL) Refresh every 390 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _UINT16_(0xE) /* (DAC_DACCTRL) Refresh every 420 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _UINT16_(0xF) /* (DAC_DACCTRL) Refresh every 450 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Do not Refresh Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 30 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 60 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 90 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 120 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 150 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 180 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 210 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 240 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 270 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 300 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 330 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 360 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 390 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 420 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 450 us Position */ +#define DAC_DACCTRL_OSR_Pos _UINT16_(13) /* (DAC_DACCTRL) Sampling Rate Position */ +#define DAC_DACCTRL_OSR_Msk (_UINT16_(0x7) << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) Sampling Rate Mask */ +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & (_UINT16_(value) << DAC_DACCTRL_OSR_Pos)) /* Assigment of value for OSR in the DAC_DACCTRL register */ +#define DAC_DACCTRL_OSR_OSR_1_Val _UINT16_(0x0) /* (DAC_DACCTRL) No Over Sampling */ +#define DAC_DACCTRL_OSR_OSR_2_Val _UINT16_(0x1) /* (DAC_DACCTRL) 2x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_4_Val _UINT16_(0x2) /* (DAC_DACCTRL) 4x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_8_Val _UINT16_(0x3) /* (DAC_DACCTRL) 8x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_16_Val _UINT16_(0x4) /* (DAC_DACCTRL) 16x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_32_Val _UINT16_(0x5) /* (DAC_DACCTRL) 32x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) No Over Sampling Position */ +#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 2x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 4x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 8x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 16x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 32x Over Sampling Ratio Position */ +#define DAC_DACCTRL_Msk _UINT16_(0xEFEF) /* (DAC_DACCTRL) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) DAC n Data Reset Value */ + +#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) DAC0 Data Position */ +#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) DAC0 Data Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assigment of value for DATA in the DAC_DATA register */ +#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) DAC n Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) DAC0 Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) DAC0 Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_DATABUF register */ +#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the DAC_DBGCTRL register */ +#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ + + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */ +#define DAC_RESULT_RESETVALUE _UINT16_(0x00) /* (DAC_RESULT) Filter Result Reset Value */ + +#define DAC_RESULT_RESULT_Pos _UINT16_(0) /* (DAC_RESULT) Filter Result Position */ +#define DAC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << DAC_RESULT_RESULT_Pos) /* (DAC_RESULT) Filter Result Mask */ +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & (_UINT16_(value) << DAC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the DAC_RESULT register */ +#define DAC_RESULT_Msk _UINT16_(0xFFFF) /* (DAC_RESULT) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ +#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x08) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DACCTRL_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL) DAC n Control Offset */ +#define DAC_DACCTRL0_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL0) DAC n Control Offset */ +#define DAC_DACCTRL1_REG_OFST _UINT32_(0x0E) /* (DAC_DACCTRL1) DAC n Control Offset */ +#define DAC_DATA_REG_OFST _UINT32_(0x10) /* (DAC_DATA) DAC n Data Offset */ +#define DAC_DATA0_REG_OFST _UINT32_(0x10) /* (DAC_DATA0) DAC n Data Offset */ +#define DAC_DATA1_REG_OFST _UINT32_(0x12) /* (DAC_DATA1) DAC n Data Offset */ +#define DAC_DATABUF_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF) DAC n Data Buffer Offset */ +#define DAC_DATABUF0_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF0) DAC n Data Buffer Offset */ +#define DAC_DATABUF1_REG_OFST _UINT32_(0x16) /* (DAC_DATABUF1) DAC n Data Buffer Offset */ +#define DAC_DBGCTRL_REG_OFST _UINT32_(0x18) /* (DAC_DBGCTRL) Debug Control Offset */ +#define DAC_RESULT_REG_OFST _UINT32_(0x1C) /* (DAC_RESULT) Filter Result Offset */ +#define DAC_RESULT0_REG_OFST _UINT32_(0x1C) /* (DAC_RESULT0) Filter Result Offset */ +#define DAC_RESULT1_REG_OFST _UINT32_(0x1E) /* (DAC_RESULT1) Filter Result Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital-to-Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */ + __O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */ + __O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */ + __I uint8_t Reserved2[0x03]; + __I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME51_DAC_COMPONENT_H_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/component/dmac.h b/firmware/src/packs/ATSAME51J19A_DFP/component/dmac.h new file mode 100644 index 0000000..6803153 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/component/dmac.h @@ -0,0 +1,1189 @@ +/* + * Component description for DMAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_DMAC_COMPONENT_H_ +#define _SAME51_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assigment of value for VALID in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Block Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Block Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assigment of value for EVOSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Block event strobe Position */ +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Burst event strobe Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assigment of value for BLOCKACT in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assigment of value for BEATSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assigment of value for SRCINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assigment of value for DSTINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assigment of value for STEPSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assigment of value for STEPSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits */ +#define USB_EPNUM (8) /* parameter for rtl : max of ENDPOINT and PIPE NUM */ +#define USB_EPT_NUM (8) /* Number of USB end points */ +#define USB_GCLK_ID (10) /* Index of Generic Clock */ +#define USB_INITIAL_CONTROL_QOS (3) /* CONTROL QOS RESET value */ +#define USB_INITIAL_DATA_QOS (3) /* DATA QOS RESET value */ +#define USB_MISSING_SOF_DET_IMPLEMENTED (1) /* 48 mHz xPLL feature implemented */ +#define USB_PIPE_NUM (8) /* Number of USB pipes */ +#define USB_SYSTEM_CLOCK_IS_CKUSB (0) /* Dual (1'b0) or Single (1'b1) clock system */ +#define USB_2_AHB_FIFO_DEPTH (4) /* bytes number, should be at least 2, and 2^n (4,8,16 ...) */ +#define USB_2_AHB_RD_DATA_BITS (16) /* 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode */ +#define USB_2_AHB_RD_THRESHOLD (2) /* as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested */ +#define USB_2_AHB_WR_DATA_BITS (8) /* 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode */ +#define USB_INSTANCE_ID (32) /* Instance index for USB */ + +#endif /* _SAME51_USB_INSTANCE_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/instance/wdt.h b/firmware/src/packs/ATSAME51J19A_DFP/instance/wdt.h new file mode 100644 index 0000000..7e32341 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/instance/wdt.h @@ -0,0 +1,31 @@ +/* + * Instance header file for ATSAME51N20A + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:15Z */ +#ifndef _SAME51_WDT_INSTANCE_ +#define _SAME51_WDT_INSTANCE_ + + +/* ========== Instance Parameter definitions for WDT peripheral ========== */ +#define WDT_INSTANCE_ID (8) /* Instance index for WDT */ + +#endif /* _SAME51_WDT_INSTANCE_ */ diff --git a/firmware/src/packs/ATSAME51J19A_DFP/pio/same51j19a.h b/firmware/src/packs/ATSAME51J19A_DFP/pio/same51j19a.h new file mode 100644 index 0000000..df7d3ce --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/pio/same51j19a.h @@ -0,0 +1,2298 @@ +/* + * Peripheral I/O description for SAME51J19A + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-02-14T14:27:08Z */ +#ifndef _SAME51J19A_GPIO_H_ +#define _SAME51J19A_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA00 ( 0) /**< Pin Number for PA00 */ +#define PIN_PA01 ( 1) /**< Pin Number for PA01 */ +#define PIN_PA02 ( 2) /**< Pin Number for PA02 */ +#define PIN_PA03 ( 3) /**< Pin Number for PA03 */ +#define PIN_PA04 ( 4) /**< Pin Number for PA04 */ +#define PIN_PA05 ( 5) /**< Pin Number for PA05 */ +#define PIN_PA06 ( 6) /**< Pin Number for PA06 */ +#define PIN_PA07 ( 7) /**< Pin Number for PA07 */ +#define PIN_PA08 ( 8) /**< Pin Number for PA08 */ +#define PIN_PA09 ( 9) /**< Pin Number for PA09 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB00 ( 32) /**< Pin Number for PB00 */ +#define PIN_PB01 ( 33) /**< Pin Number for PB01 */ +#define PIN_PB02 ( 34) /**< Pin Number for PB02 */ +#define PIN_PB03 ( 35) /**< Pin Number for PB03 */ +#define PIN_PB04 ( 36) /**< Pin Number for PB04 */ +#define PIN_PB05 ( 37) /**< Pin Number for PB05 */ +#define PIN_PB06 ( 38) /**< Pin Number for PB06 */ +#define PIN_PB07 ( 39) /**< Pin Number for PB07 */ +#define PIN_PB08 ( 40) /**< Pin Number for PB08 */ +#define PIN_PB09 ( 41) /**< Pin Number for PB09 */ +#define PIN_PB10 ( 42) /**< Pin Number for PB10 */ +#define PIN_PB11 ( 43) /**< Pin Number for PB11 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PB14 ( 46) /**< Pin Number for PB14 */ +#define PIN_PB15 ( 47) /**< Pin Number for PB15 */ +#define PIN_PB16 ( 48) /**< Pin Number for PB16 */ +#define PIN_PB17 ( 49) /**< Pin Number for PB17 */ +#define PIN_PB22 ( 54) /**< Pin Number for PB22 */ +#define PIN_PB23 ( 55) /**< Pin Number for PB23 */ +#define PIN_PB30 ( 62) /**< Pin Number for PB30 */ +#define PIN_PB31 ( 63) /**< Pin Number for PB31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */ +#define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */ +#define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */ +#define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */ +#define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */ +#define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */ +#define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */ +#define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */ +#define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */ +#define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */ +#define PORT_PA10 (_UINT32_(1) << 10) /**< PORT mask for PA10 */ +#define PORT_PA11 (_UINT32_(1) << 11) /**< PORT mask for PA11 */ +#define PORT_PA12 (_UINT32_(1) << 12) /**< PORT mask for PA12 */ +#define PORT_PA13 (_UINT32_(1) << 13) /**< PORT mask for PA13 */ +#define PORT_PA14 (_UINT32_(1) << 14) /**< PORT mask for PA14 */ +#define PORT_PA15 (_UINT32_(1) << 15) /**< PORT mask for PA15 */ +#define PORT_PA16 (_UINT32_(1) << 16) /**< PORT mask for PA16 */ +#define PORT_PA17 (_UINT32_(1) << 17) /**< PORT mask for PA17 */ +#define PORT_PA18 (_UINT32_(1) << 18) /**< PORT mask for PA18 */ +#define PORT_PA19 (_UINT32_(1) << 19) /**< PORT mask for PA19 */ +#define PORT_PA20 (_UINT32_(1) << 20) /**< PORT mask for PA20 */ +#define PORT_PA21 (_UINT32_(1) << 21) /**< PORT mask for PA21 */ +#define PORT_PA22 (_UINT32_(1) << 22) /**< PORT mask for PA22 */ +#define PORT_PA23 (_UINT32_(1) << 23) /**< PORT mask for PA23 */ +#define PORT_PA24 (_UINT32_(1) << 24) /**< PORT mask for PA24 */ +#define PORT_PA25 (_UINT32_(1) << 25) /**< PORT mask for PA25 */ +#define PORT_PA27 (_UINT32_(1) << 27) /**< PORT mask for PA27 */ +#define PORT_PA30 (_UINT32_(1) << 30) /**< PORT mask for PA30 */ +#define PORT_PA31 (_UINT32_(1) << 31) /**< PORT mask for PA31 */ +#define PORT_PB00 (_UINT32_(1) << 0) /**< PORT mask for PB00 */ +#define PORT_PB01 (_UINT32_(1) << 1) /**< PORT mask for PB01 */ +#define PORT_PB02 (_UINT32_(1) << 2) /**< PORT mask for PB02 */ +#define PORT_PB03 (_UINT32_(1) << 3) /**< PORT mask for PB03 */ +#define PORT_PB04 (_UINT32_(1) << 4) /**< PORT mask for PB04 */ +#define PORT_PB05 (_UINT32_(1) << 5) /**< PORT mask for PB05 */ +#define PORT_PB06 (_UINT32_(1) << 6) /**< PORT mask for PB06 */ +#define PORT_PB07 (_UINT32_(1) << 7) /**< PORT mask for PB07 */ +#define PORT_PB08 (_UINT32_(1) << 8) /**< PORT mask for PB08 */ +#define PORT_PB09 (_UINT32_(1) << 9) /**< PORT mask for PB09 */ +#define PORT_PB10 (_UINT32_(1) << 10) /**< PORT mask for PB10 */ +#define PORT_PB11 (_UINT32_(1) << 11) /**< PORT mask for PB11 */ +#define PORT_PB12 (_UINT32_(1) << 12) /**< PORT mask for PB12 */ +#define PORT_PB13 (_UINT32_(1) << 13) /**< PORT mask for PB13 */ +#define PORT_PB14 (_UINT32_(1) << 14) /**< PORT mask for PB14 */ +#define PORT_PB15 (_UINT32_(1) << 15) /**< PORT mask for PB15 */ +#define PORT_PB16 (_UINT32_(1) << 16) /**< PORT mask for PB16 */ +#define PORT_PB17 (_UINT32_(1) << 17) /**< PORT mask for PB17 */ +#define PORT_PB22 (_UINT32_(1) << 22) /**< PORT mask for PB22 */ +#define PORT_PB23 (_UINT32_(1) << 23) /**< PORT mask for PB23 */ +#define PORT_PB30 (_UINT32_(1) << 30) /**< PORT mask for PB30 */ +#define PORT_PB31 (_UINT32_(1) << 31) /**< PORT mask for PB31 */ + +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _UINT32_(4) +#define MUX_PA04B_AC_AIN0 _UINT32_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) + +#define PIN_PA05B_AC_AIN1 _UINT32_(5) +#define MUX_PA05B_AC_AIN1 _UINT32_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) + +#define PIN_PA06B_AC_AIN2 _UINT32_(6) +#define MUX_PA06B_AC_AIN2 _UINT32_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) + +#define PIN_PA07B_AC_AIN3 _UINT32_(7) +#define MUX_PA07B_AC_AIN3 _UINT32_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) + +#define PIN_PA12M_AC_CMP0 _UINT32_(12) +#define MUX_PA12M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) + +#define PIN_PA18M_AC_CMP0 _UINT32_(18) +#define MUX_PA18M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) + +#define PIN_PA13M_AC_CMP1 _UINT32_(13) +#define MUX_PA13M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) + +#define PIN_PA19M_AC_CMP1 _UINT32_(19) +#define MUX_PA19M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) + +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _UINT32_(2) +#define MUX_PA02B_ADC0_AIN0 _UINT32_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) + +#define PIN_PA03B_ADC0_AIN1 _UINT32_(3) +#define MUX_PA03B_ADC0_AIN1 _UINT32_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_AIN2 _UINT32_(40) +#define MUX_PB08B_ADC0_AIN2 _UINT32_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_AIN3 _UINT32_(41) +#define MUX_PB09B_ADC0_AIN3 _UINT32_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_AIN4 _UINT32_(4) +#define MUX_PA04B_ADC0_AIN4 _UINT32_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) + +#define PIN_PA05B_ADC0_AIN5 _UINT32_(5) +#define MUX_PA05B_ADC0_AIN5 _UINT32_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) + +#define PIN_PA06B_ADC0_AIN6 _UINT32_(6) +#define MUX_PA06B_ADC0_AIN6 _UINT32_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_AIN7 _UINT32_(7) +#define MUX_PA07B_ADC0_AIN7 _UINT32_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_AIN8 _UINT32_(8) +#define MUX_PA08B_ADC0_AIN8 _UINT32_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_AIN9 _UINT32_(9) +#define MUX_PA09B_ADC0_AIN9 _UINT32_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_AIN10 _UINT32_(10) +#define MUX_PA10B_ADC0_AIN10 _UINT32_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_AIN11 _UINT32_(11) +#define MUX_PA11B_ADC0_AIN11 _UINT32_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) + +#define PIN_PB00B_ADC0_AIN12 _UINT32_(32) +#define MUX_PB00B_ADC0_AIN12 _UINT32_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_AIN13 _UINT32_(33) +#define MUX_PB01B_ADC0_AIN13 _UINT32_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) + +#define PIN_PB02B_ADC0_AIN14 _UINT32_(34) +#define MUX_PB02B_ADC0_AIN14 _UINT32_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_AIN15 _UINT32_(35) +#define MUX_PB03B_ADC0_AIN15 _UINT32_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) + +#define PIN_PA03B_ADC0_VREFA _UINT32_(3) +#define MUX_PA03B_ADC0_VREFA _UINT32_(1) +#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) +#define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) + +#define PIN_PA04B_ADC0_VREFB _UINT32_(4) +#define MUX_PA04B_ADC0_VREFB _UINT32_(1) +#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) +#define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_VREFC _UINT32_(6) +#define MUX_PA06B_ADC0_VREFC _UINT32_(1) +#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) +#define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) + +#define PIN_PA03B_ADC0_X0 _UINT32_(3) +#define MUX_PA03B_ADC0_X0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) +#define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_X1 _UINT32_(40) +#define MUX_PB08B_ADC0_X1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) +#define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_X2 _UINT32_(41) +#define MUX_PB09B_ADC0_X2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) +#define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_X3 _UINT32_(4) +#define MUX_PA04B_ADC0_X3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) +#define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_X4 _UINT32_(6) +#define MUX_PA06B_ADC0_X4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) +#define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_X5 _UINT32_(7) +#define MUX_PA07B_ADC0_X5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) +#define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_X6 _UINT32_(8) +#define MUX_PA08B_ADC0_X6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) +#define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_X7 _UINT32_(9) +#define MUX_PA09B_ADC0_X7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) +#define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_X8 _UINT32_(10) +#define MUX_PA10B_ADC0_X8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) +#define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_X9 _UINT32_(11) +#define MUX_PA11B_ADC0_X9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) +#define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_X10 _UINT32_(16) +#define MUX_PA16B_ADC0_X10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) +#define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_X11 _UINT32_(17) +#define MUX_PA17B_ADC0_X11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) +#define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_X12 _UINT32_(18) +#define MUX_PA18B_ADC0_X12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) +#define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_X13 _UINT32_(19) +#define MUX_PA19B_ADC0_X13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) +#define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_X14 _UINT32_(20) +#define MUX_PA20B_ADC0_X14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) +#define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_X15 _UINT32_(21) +#define MUX_PA21B_ADC0_X15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) +#define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_X16 _UINT32_(22) +#define MUX_PA22B_ADC0_X16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) +#define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_X17 _UINT32_(23) +#define MUX_PA23B_ADC0_X17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) +#define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_X18 _UINT32_(27) +#define MUX_PA27B_ADC0_X18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) +#define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_X19 _UINT32_(30) +#define MUX_PA30B_ADC0_X19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) +#define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_X20 _UINT32_(34) +#define MUX_PB02B_ADC0_X20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) +#define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_X21 _UINT32_(35) +#define MUX_PB03B_ADC0_X21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) +#define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_X22 _UINT32_(36) +#define MUX_PB04B_ADC0_X22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) +#define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_X23 _UINT32_(37) +#define MUX_PB05B_ADC0_X23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) +#define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_X24 _UINT32_(38) +#define MUX_PB06B_ADC0_X24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) +#define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_X25 _UINT32_(39) +#define MUX_PB07B_ADC0_X25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) +#define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_X26 _UINT32_(44) +#define MUX_PB12B_ADC0_X26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) +#define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_X27 _UINT32_(45) +#define MUX_PB13B_ADC0_X27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) +#define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_X28 _UINT32_(46) +#define MUX_PB14B_ADC0_X28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) +#define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_X29 _UINT32_(47) +#define MUX_PB15B_ADC0_X29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) +#define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_X30 _UINT32_(32) +#define MUX_PB00B_ADC0_X30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) +#define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_X31 _UINT32_(33) +#define MUX_PB01B_ADC0_X31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) +#define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) + +#define PIN_PA03B_ADC0_Y0 _UINT32_(3) +#define MUX_PA03B_ADC0_Y0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) +#define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_Y1 _UINT32_(40) +#define MUX_PB08B_ADC0_Y1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) +#define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_Y2 _UINT32_(41) +#define MUX_PB09B_ADC0_Y2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) +#define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_Y3 _UINT32_(4) +#define MUX_PA04B_ADC0_Y3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) +#define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_Y4 _UINT32_(6) +#define MUX_PA06B_ADC0_Y4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) +#define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_Y5 _UINT32_(7) +#define MUX_PA07B_ADC0_Y5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) +#define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_Y6 _UINT32_(8) +#define MUX_PA08B_ADC0_Y6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) +#define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_Y7 _UINT32_(9) +#define MUX_PA09B_ADC0_Y7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) +#define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_Y8 _UINT32_(10) +#define MUX_PA10B_ADC0_Y8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) +#define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_Y9 _UINT32_(11) +#define MUX_PA11B_ADC0_Y9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) +#define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_Y10 _UINT32_(16) +#define MUX_PA16B_ADC0_Y10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) +#define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_Y11 _UINT32_(17) +#define MUX_PA17B_ADC0_Y11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) +#define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_Y12 _UINT32_(18) +#define MUX_PA18B_ADC0_Y12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) +#define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_Y13 _UINT32_(19) +#define MUX_PA19B_ADC0_Y13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) +#define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_Y14 _UINT32_(20) +#define MUX_PA20B_ADC0_Y14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) +#define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_Y15 _UINT32_(21) +#define MUX_PA21B_ADC0_Y15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) +#define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_Y16 _UINT32_(22) +#define MUX_PA22B_ADC0_Y16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) +#define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_Y17 _UINT32_(23) +#define MUX_PA23B_ADC0_Y17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) +#define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_Y18 _UINT32_(27) +#define MUX_PA27B_ADC0_Y18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) +#define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_Y19 _UINT32_(30) +#define MUX_PA30B_ADC0_Y19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) +#define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_Y20 _UINT32_(34) +#define MUX_PB02B_ADC0_Y20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) +#define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_Y21 _UINT32_(35) +#define MUX_PB03B_ADC0_Y21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) +#define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_Y22 _UINT32_(36) +#define MUX_PB04B_ADC0_Y22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) +#define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_Y23 _UINT32_(37) +#define MUX_PB05B_ADC0_Y23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) +#define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_Y24 _UINT32_(38) +#define MUX_PB06B_ADC0_Y24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) +#define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_Y25 _UINT32_(39) +#define MUX_PB07B_ADC0_Y25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) +#define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_Y26 _UINT32_(44) +#define MUX_PB12B_ADC0_Y26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) +#define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_Y27 _UINT32_(45) +#define MUX_PB13B_ADC0_Y27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) +#define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_Y28 _UINT32_(46) +#define MUX_PB14B_ADC0_Y28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) +#define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_Y29 _UINT32_(47) +#define MUX_PB15B_ADC0_Y29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) +#define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_Y30 _UINT32_(32) +#define MUX_PB00B_ADC0_Y30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) +#define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_Y31 _UINT32_(33) +#define MUX_PB01B_ADC0_Y31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) +#define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) + +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _UINT32_(40) +#define MUX_PB08B_ADC1_AIN0 _UINT32_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC1_AIN1 _UINT32_(41) +#define MUX_PB09B_ADC1_AIN1 _UINT32_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) + +#define PIN_PA08B_ADC1_AIN2 _UINT32_(8) +#define MUX_PA08B_ADC1_AIN2 _UINT32_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC1_AIN3 _UINT32_(9) +#define MUX_PA09B_ADC1_AIN3 _UINT32_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) + +#define PIN_PB04B_ADC1_AIN6 _UINT32_(36) +#define MUX_PB04B_ADC1_AIN6 _UINT32_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC1_AIN7 _UINT32_(37) +#define MUX_PB05B_ADC1_AIN7 _UINT32_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC1_AIN8 _UINT32_(38) +#define MUX_PB06B_ADC1_AIN8 _UINT32_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC1_AIN9 _UINT32_(39) +#define MUX_PB07B_ADC1_AIN9 _UINT32_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) + +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _UINT32_(23) +#define MUX_PA23I_CAN0_RX _UINT32_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) + +#define PIN_PA25I_CAN0_RX _UINT32_(25) +#define MUX_PA25I_CAN0_RX _UINT32_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) + +#define PIN_PA22I_CAN0_TX _UINT32_(22) +#define MUX_PA22I_CAN0_TX _UINT32_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) + +#define PIN_PA24I_CAN0_TX _UINT32_(24) +#define MUX_PA24I_CAN0_TX _UINT32_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) + +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _UINT32_(45) +#define MUX_PB13H_CAN1_RX _UINT32_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) + +#define PIN_PB15H_CAN1_RX _UINT32_(47) +#define MUX_PB15H_CAN1_RX _UINT32_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) + +#define PIN_PB12H_CAN1_TX _UINT32_(44) +#define MUX_PB12H_CAN1_TX _UINT32_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) + +#define PIN_PB14H_CAN1_TX _UINT32_(46) +#define MUX_PB14H_CAN1_TX _UINT32_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) + +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _UINT32_(4) +#define MUX_PA04N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) + +#define PIN_PA16N_CCL_IN0 _UINT32_(16) +#define MUX_PA16N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) + +#define PIN_PB22N_CCL_IN0 _UINT32_(54) +#define MUX_PB22N_CCL_IN0 _UINT32_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) + +#define PIN_PA05N_CCL_IN1 _UINT32_(5) +#define MUX_PA05N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) + +#define PIN_PA17N_CCL_IN1 _UINT32_(17) +#define MUX_PA17N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) + +#define PIN_PB00N_CCL_IN1 _UINT32_(32) +#define MUX_PB00N_CCL_IN1 _UINT32_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) + +#define PIN_PA06N_CCL_IN2 _UINT32_(6) +#define MUX_PA06N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) + +#define PIN_PA18N_CCL_IN2 _UINT32_(18) +#define MUX_PA18N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) + +#define PIN_PB01N_CCL_IN2 _UINT32_(33) +#define MUX_PB01N_CCL_IN2 _UINT32_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) + +#define PIN_PA08N_CCL_IN3 _UINT32_(8) +#define MUX_PA08N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) + +#define PIN_PA30N_CCL_IN3 _UINT32_(30) +#define MUX_PA30N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) + +#define PIN_PA09N_CCL_IN4 _UINT32_(9) +#define MUX_PA09N_CCL_IN4 _UINT32_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) + +#define PIN_PA10N_CCL_IN5 _UINT32_(10) +#define MUX_PA10N_CCL_IN5 _UINT32_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) + +#define PIN_PA22N_CCL_IN6 _UINT32_(22) +#define MUX_PA22N_CCL_IN6 _UINT32_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) + +#define PIN_PB06N_CCL_IN6 _UINT32_(38) +#define MUX_PB06N_CCL_IN6 _UINT32_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) + +#define PIN_PA23N_CCL_IN7 _UINT32_(23) +#define MUX_PA23N_CCL_IN7 _UINT32_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) + +#define PIN_PB07N_CCL_IN7 _UINT32_(39) +#define MUX_PB07N_CCL_IN7 _UINT32_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) + +#define PIN_PA24N_CCL_IN8 _UINT32_(24) +#define MUX_PA24N_CCL_IN8 _UINT32_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) + +#define PIN_PB08N_CCL_IN8 _UINT32_(40) +#define MUX_PB08N_CCL_IN8 _UINT32_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) + +#define PIN_PB14N_CCL_IN9 _UINT32_(46) +#define MUX_PB14N_CCL_IN9 _UINT32_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) + +#define PIN_PB15N_CCL_IN10 _UINT32_(47) +#define MUX_PB15N_CCL_IN10 _UINT32_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) + +#define PIN_PB10N_CCL_IN11 _UINT32_(42) +#define MUX_PB10N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) + +#define PIN_PB16N_CCL_IN11 _UINT32_(48) +#define MUX_PB16N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) + +#define PIN_PA07N_CCL_OUT0 _UINT32_(7) +#define MUX_PA07N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) + +#define PIN_PA19N_CCL_OUT0 _UINT32_(19) +#define MUX_PA19N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) + +#define PIN_PB02N_CCL_OUT0 _UINT32_(34) +#define MUX_PB02N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) + +#define PIN_PB23N_CCL_OUT0 _UINT32_(55) +#define MUX_PB23N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) + +#define PIN_PA11N_CCL_OUT1 _UINT32_(11) +#define MUX_PA11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA31N_CCL_OUT1 _UINT32_(31) +#define MUX_PA31N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) + +#define PIN_PB11N_CCL_OUT1 _UINT32_(43) +#define MUX_PB11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA25N_CCL_OUT2 _UINT32_(25) +#define MUX_PA25N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) + +#define PIN_PB09N_CCL_OUT2 _UINT32_(41) +#define MUX_PB09N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) + +#define PIN_PB17N_CCL_OUT3 _UINT32_(49) +#define MUX_PB17N_CCL_OUT3 _UINT32_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) + +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _UINT32_(2) +#define MUX_PA02B_DAC_VOUT0 _UINT32_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) + +#define PIN_PA05B_DAC_VOUT1 _UINT32_(5) +#define MUX_PA05B_DAC_VOUT1 _UINT32_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) + +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) +#define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ + +#define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) +#define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ + +#define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) +#define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ + +#define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) +#define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ + +#define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) +#define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ + +#define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) +#define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ + +#define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) +#define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ + +#define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) +#define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ + +#define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) +#define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ + +#define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) +#define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ + +#define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) +#define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ + +#define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) +#define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ + +#define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) +#define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ + +#define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) +#define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ + +#define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) +#define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ + +#define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) +#define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ + +#define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) +#define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ + +#define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) +#define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ + +#define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) +#define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ + +#define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) +#define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ + +#define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) +#define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ + +#define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) +#define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ + +#define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) +#define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ + +#define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) +#define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ + +#define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) +#define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ + +#define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) +#define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ + +#define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) +#define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ + +#define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) +#define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ + +#define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) +#define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ + +#define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) +#define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ + +#define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) +#define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ + +#define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) +#define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ + +#define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) +#define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ + +#define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) +#define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ + +#define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) +#define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ + +#define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) +#define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ + +#define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) +#define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ + +#define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) +#define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ + +#define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) +#define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ + +#define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) +#define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ + +#define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) +#define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ + +#define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) +#define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ + +#define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) +#define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ + +#define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) +#define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ + +#define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) +#define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ + +#define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) +#define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ + +#define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) +#define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ + +#define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) +#define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ + +#define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) +#define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ + +#define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) +#define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ + +#define PIN_PA08A_EIC_NMI _UINT32_(8) +#define MUX_PA08A_EIC_NMI _UINT32_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) + +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _UINT32_(30) +#define MUX_PA30M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) + +#define PIN_PB14M_GCLK_IO0 _UINT32_(46) +#define MUX_PB14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PA14M_GCLK_IO0 _UINT32_(14) +#define MUX_PA14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PB22M_GCLK_IO0 _UINT32_(54) +#define MUX_PB22M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) + +#define PIN_PB15M_GCLK_IO1 _UINT32_(47) +#define MUX_PB15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PA15M_GCLK_IO1 _UINT32_(15) +#define MUX_PA15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PB23M_GCLK_IO1 _UINT32_(55) +#define MUX_PB23M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) + +#define PIN_PA27M_GCLK_IO1 _UINT32_(27) +#define MUX_PA27M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) + +#define PIN_PA16M_GCLK_IO2 _UINT32_(16) +#define MUX_PA16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PB16M_GCLK_IO2 _UINT32_(48) +#define MUX_PB16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PA17M_GCLK_IO3 _UINT32_(17) +#define MUX_PA17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PB17M_GCLK_IO3 _UINT32_(49) +#define MUX_PB17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PA10M_GCLK_IO4 _UINT32_(10) +#define MUX_PA10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB10M_GCLK_IO4 _UINT32_(42) +#define MUX_PB10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PA11M_GCLK_IO5 _UINT32_(11) +#define MUX_PA11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB11M_GCLK_IO5 _UINT32_(43) +#define MUX_PB11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB12M_GCLK_IO6 _UINT32_(44) +#define MUX_PB12M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) + +#define PIN_PB13M_GCLK_IO7 _UINT32_(45) +#define MUX_PB13M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) + +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _UINT32_(9) +#define MUX_PA09J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) + +#define PIN_PA20J_I2S_FS0 _UINT32_(20) +#define MUX_PA20J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) + +#define PIN_PA23J_I2S_FS1 _UINT32_(23) +#define MUX_PA23J_I2S_FS1 _UINT32_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) + +#define PIN_PB11J_I2S_FS1 _UINT32_(43) +#define MUX_PB11J_I2S_FS1 _UINT32_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) + +#define PIN_PA08J_I2S_MCK0 _UINT32_(8) +#define MUX_PA08J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) + +#define PIN_PB17J_I2S_MCK0 _UINT32_(49) +#define MUX_PB17J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) + +#define PIN_PB13J_I2S_MCK1 _UINT32_(45) +#define MUX_PB13J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) + +#define PIN_PA10J_I2S_SCK0 _UINT32_(10) +#define MUX_PA10J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) + +#define PIN_PB16J_I2S_SCK0 _UINT32_(48) +#define MUX_PB16J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) + +#define PIN_PB12J_I2S_SCK1 _UINT32_(44) +#define MUX_PB12J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) + +#define PIN_PA22J_I2S_SDI _UINT32_(22) +#define MUX_PA22J_I2S_SDI _UINT32_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) + +#define PIN_PB10J_I2S_SDI _UINT32_(42) +#define MUX_PB10J_I2S_SDI _UINT32_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) + +#define PIN_PA11J_I2S_SDO _UINT32_(11) +#define MUX_PA11J_I2S_SDO _UINT32_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) + +#define PIN_PA21J_I2S_SDO _UINT32_(21) +#define MUX_PA21J_I2S_SDO _UINT32_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) + +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _UINT32_(14) +#define MUX_PA14K_PCC_CLK _UINT32_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) + +#define PIN_PA16K_PCC_DATA0 _UINT32_(16) +#define MUX_PA16K_PCC_DATA0 _UINT32_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) + +#define PIN_PA17K_PCC_DATA1 _UINT32_(17) +#define MUX_PA17K_PCC_DATA1 _UINT32_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) + +#define PIN_PA18K_PCC_DATA2 _UINT32_(18) +#define MUX_PA18K_PCC_DATA2 _UINT32_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) + +#define PIN_PA19K_PCC_DATA3 _UINT32_(19) +#define MUX_PA19K_PCC_DATA3 _UINT32_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) + +#define PIN_PA20K_PCC_DATA4 _UINT32_(20) +#define MUX_PA20K_PCC_DATA4 _UINT32_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) + +#define PIN_PA21K_PCC_DATA5 _UINT32_(21) +#define MUX_PA21K_PCC_DATA5 _UINT32_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) + +#define PIN_PA22K_PCC_DATA6 _UINT32_(22) +#define MUX_PA22K_PCC_DATA6 _UINT32_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) + +#define PIN_PA23K_PCC_DATA7 _UINT32_(23) +#define MUX_PA23K_PCC_DATA7 _UINT32_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) + +#define PIN_PB14K_PCC_DATA8 _UINT32_(46) +#define MUX_PB14K_PCC_DATA8 _UINT32_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) + +#define PIN_PB15K_PCC_DATA9 _UINT32_(47) +#define MUX_PB15K_PCC_DATA9 _UINT32_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) + +#define PIN_PA12K_PCC_DEN1 _UINT32_(12) +#define MUX_PA12K_PCC_DEN1 _UINT32_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) + +#define PIN_PA13K_PCC_DEN2 _UINT32_(13) +#define MUX_PA13K_PCC_DEN2 _UINT32_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) + +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _UINT32_(55) +#define MUX_PB23G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) + +#define PIN_PA24G_PDEC_QDI0 _UINT32_(24) +#define MUX_PA24G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) + +#define PIN_PA25G_PDEC_QDI1 _UINT32_(25) +#define MUX_PA25G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) + +#define PIN_PB22G_PDEC_QDI2 _UINT32_(54) +#define MUX_PB22G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) + +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _UINT32_(43) +#define MUX_PB11H_QSPI_CS _UINT32_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) + +#define PIN_PA08H_QSPI_DATA0 _UINT32_(8) +#define MUX_PA08H_QSPI_DATA0 _UINT32_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) + +#define PIN_PA09H_QSPI_DATA1 _UINT32_(9) +#define MUX_PA09H_QSPI_DATA1 _UINT32_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) + +#define PIN_PA10H_QSPI_DATA2 _UINT32_(10) +#define MUX_PA10H_QSPI_DATA2 _UINT32_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) + +#define PIN_PA11H_QSPI_DATA3 _UINT32_(11) +#define MUX_PA11H_QSPI_DATA3 _UINT32_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) + +#define PIN_PB10H_QSPI_SCK _UINT32_(42) +#define MUX_PB10H_QSPI_SCK _UINT32_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) + +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _UINT32_(6) +#define MUX_PA06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PA12I_SDHC0_SDCD _UINT32_(12) +#define MUX_PA12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB12I_SDHC0_SDCD _UINT32_(44) +#define MUX_PB12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB11I_SDHC0_SDCK _UINT32_(43) +#define MUX_PB11I_SDHC0_SDCK _UINT32_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) + +#define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) +#define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) + +#define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) +#define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) + +#define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) +#define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) + +#define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) +#define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) + +#define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) +#define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) + +#define PIN_PA07I_SDHC0_SDWP _UINT32_(7) +#define MUX_PA07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) + +#define PIN_PA13I_SDHC0_SDWP _UINT32_(13) +#define MUX_PA13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PB13I_SDHC0_SDWP _UINT32_(45) +#define MUX_PB13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) + +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) +#define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) + +#define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) +#define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) + +#define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) +#define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) + +#define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) +#define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) + +#define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) +#define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) + +#define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) +#define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) + +#define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) +#define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) + +#define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) +#define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) + +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) +#define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) + +#define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) +#define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) +#define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) + +#define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) +#define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) +#define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) + +#define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) +#define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) + +#define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) +#define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) +#define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) + +#define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) +#define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) + +#define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) +#define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) + +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) +#define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) + +#define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) +#define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) +#define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) + +#define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) +#define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) +#define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) + +#define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) +#define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) +#define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) +#define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) +#define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) +#define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) + +#define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) +#define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) +#define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) + +#define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) +#define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) +#define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) +#define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) +#define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) +#define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) +#define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) +#define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) + +#define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) +#define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) +#define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) +#define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) + +#define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) +#define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) +#define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) +#define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) +#define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) + +#define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) +#define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) +#define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) +#define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) + +#define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) +#define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) +#define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) + +#define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) +#define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) + +#define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) +#define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) + +#define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) +#define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) +#define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) + +#define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) +#define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) + +#define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) +#define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) + +#define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) +#define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) +#define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) +#define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) + +#define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) +#define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) +#define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) +#define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) +#define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) + +#define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) +#define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) + +#define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) +#define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) + +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _UINT32_(4) +#define MUX_PA04E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PA08E_TC0_WO0 _UINT32_(8) +#define MUX_PA08E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PB30E_TC0_WO0 _UINT32_(62) +#define MUX_PB30E_TC0_WO0 _UINT32_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) + +#define PIN_PA05E_TC0_WO1 _UINT32_(5) +#define MUX_PA05E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) + +#define PIN_PA09E_TC0_WO1 _UINT32_(9) +#define MUX_PA09E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PB31E_TC0_WO1 _UINT32_(63) +#define MUX_PB31E_TC0_WO1 _UINT32_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _UINT32_(6) +#define MUX_PA06E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) + +#define PIN_PA10E_TC1_WO0 _UINT32_(10) +#define MUX_PA10E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA07E_TC1_WO1 _UINT32_(7) +#define MUX_PA07E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) + +#define PIN_PA11E_TC1_WO1 _UINT32_(11) +#define MUX_PA11E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) + +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _UINT32_(12) +#define MUX_PA12E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) + +#define PIN_PA16E_TC2_WO0 _UINT32_(16) +#define MUX_PA16E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) + +#define PIN_PA00E_TC2_WO0 _UINT32_(0) +#define MUX_PA00E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) + +#define PIN_PA01E_TC2_WO1 _UINT32_(1) +#define MUX_PA01E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) + +#define PIN_PA13E_TC2_WO1 _UINT32_(13) +#define MUX_PA13E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) + +#define PIN_PA17E_TC2_WO1 _UINT32_(17) +#define MUX_PA17E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _UINT32_(18) +#define MUX_PA18E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) + +#define PIN_PA14E_TC3_WO0 _UINT32_(14) +#define MUX_PA14E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) + +#define PIN_PA15E_TC3_WO1 _UINT32_(15) +#define MUX_PA15E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) + +#define PIN_PA19E_TC3_WO1 _UINT32_(19) +#define MUX_PA19E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) + +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _UINT32_(22) +#define MUX_PA22E_TC4_WO0 _UINT32_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) + +#define PIN_PB08E_TC4_WO0 _UINT32_(40) +#define MUX_PB08E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) + +#define PIN_PB12E_TC4_WO0 _UINT32_(44) +#define MUX_PB12E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) + +#define PIN_PA23E_TC4_WO1 _UINT32_(23) +#define MUX_PA23E_TC4_WO1 _UINT32_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) + +#define PIN_PB09E_TC4_WO1 _UINT32_(41) +#define MUX_PB09E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) + +#define PIN_PB13E_TC4_WO1 _UINT32_(45) +#define MUX_PB13E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) + +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _UINT32_(24) +#define MUX_PA24E_TC5_WO0 _UINT32_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) + +#define PIN_PB10E_TC5_WO0 _UINT32_(42) +#define MUX_PB10E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) + +#define PIN_PB14E_TC5_WO0 _UINT32_(46) +#define MUX_PB14E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) + +#define PIN_PA25E_TC5_WO1 _UINT32_(25) +#define MUX_PA25E_TC5_WO1 _UINT32_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) + +#define PIN_PB11E_TC5_WO1 _UINT32_(43) +#define MUX_PB11E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) + +#define PIN_PB15E_TC5_WO1 _UINT32_(47) +#define MUX_PB15E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) + +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _UINT32_(20) +#define MUX_PA20G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) + +#define PIN_PB12G_TCC0_WO0 _UINT32_(44) +#define MUX_PB12G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) + +#define PIN_PA08F_TCC0_WO0 _UINT32_(8) +#define MUX_PA08F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PA21G_TCC0_WO1 _UINT32_(21) +#define MUX_PA21G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) + +#define PIN_PB13G_TCC0_WO1 _UINT32_(45) +#define MUX_PB13G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) + +#define PIN_PA09F_TCC0_WO1 _UINT32_(9) +#define MUX_PA09F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PA22G_TCC0_WO2 _UINT32_(22) +#define MUX_PA22G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) + +#define PIN_PB14G_TCC0_WO2 _UINT32_(46) +#define MUX_PB14G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) + +#define PIN_PA10F_TCC0_WO2 _UINT32_(10) +#define MUX_PA10F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) + +#define PIN_PA23G_TCC0_WO3 _UINT32_(23) +#define MUX_PA23G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) + +#define PIN_PB15G_TCC0_WO3 _UINT32_(47) +#define MUX_PB15G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) + +#define PIN_PA11F_TCC0_WO3 _UINT32_(11) +#define MUX_PA11F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) + +#define PIN_PA16G_TCC0_WO4 _UINT32_(16) +#define MUX_PA16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB16G_TCC0_WO4 _UINT32_(48) +#define MUX_PB16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB10F_TCC0_WO4 _UINT32_(42) +#define MUX_PB10F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) + +#define PIN_PA17G_TCC0_WO5 _UINT32_(17) +#define MUX_PA17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB17G_TCC0_WO5 _UINT32_(49) +#define MUX_PB17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB11F_TCC0_WO5 _UINT32_(43) +#define MUX_PB11F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) + +#define PIN_PA18G_TCC0_WO6 _UINT32_(18) +#define MUX_PA18G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) + +#define PIN_PB30G_TCC0_WO6 _UINT32_(62) +#define MUX_PB30G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) + +#define PIN_PA12F_TCC0_WO6 _UINT32_(12) +#define MUX_PA12F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) + +#define PIN_PA19G_TCC0_WO7 _UINT32_(19) +#define MUX_PA19G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) + +#define PIN_PB31G_TCC0_WO7 _UINT32_(63) +#define MUX_PB31G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) + +#define PIN_PA13F_TCC0_WO7 _UINT32_(13) +#define MUX_PA13F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) + +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _UINT32_(42) +#define MUX_PB10G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA16F_TCC1_WO0 _UINT32_(16) +#define MUX_PA16F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) + +#define PIN_PB11G_TCC1_WO1 _UINT32_(43) +#define MUX_PB11G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) + +#define PIN_PA17F_TCC1_WO1 _UINT32_(17) +#define MUX_PA17F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) + +#define PIN_PA12G_TCC1_WO2 _UINT32_(12) +#define MUX_PA12G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) + +#define PIN_PA14G_TCC1_WO2 _UINT32_(14) +#define MUX_PA14G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) + +#define PIN_PA18F_TCC1_WO2 _UINT32_(18) +#define MUX_PA18F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) + +#define PIN_PA13G_TCC1_WO3 _UINT32_(13) +#define MUX_PA13G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) + +#define PIN_PA15G_TCC1_WO3 _UINT32_(15) +#define MUX_PA15G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) + +#define PIN_PA19F_TCC1_WO3 _UINT32_(19) +#define MUX_PA19F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) + +#define PIN_PA08G_TCC1_WO4 _UINT32_(8) +#define MUX_PA08G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) + +#define PIN_PA20F_TCC1_WO4 _UINT32_(20) +#define MUX_PA20F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) + +#define PIN_PA09G_TCC1_WO5 _UINT32_(9) +#define MUX_PA09G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) + +#define PIN_PA21F_TCC1_WO5 _UINT32_(21) +#define MUX_PA21F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) + +#define PIN_PA10G_TCC1_WO6 _UINT32_(10) +#define MUX_PA10G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) + +#define PIN_PA22F_TCC1_WO6 _UINT32_(22) +#define MUX_PA22F_TCC1_WO6 _UINT32_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) + +#define PIN_PA11G_TCC1_WO7 _UINT32_(11) +#define MUX_PA11G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) + +#define PIN_PA23F_TCC1_WO7 _UINT32_(23) +#define MUX_PA23F_TCC1_WO7 _UINT32_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _UINT32_(14) +#define MUX_PA14F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) + +#define PIN_PA30F_TCC2_WO0 _UINT32_(30) +#define MUX_PA30F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) + +#define PIN_PA15F_TCC2_WO1 _UINT32_(15) +#define MUX_PA15F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) + +#define PIN_PA31F_TCC2_WO1 _UINT32_(31) +#define MUX_PA31F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) + +#define PIN_PA24F_TCC2_WO2 _UINT32_(24) +#define MUX_PA24F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) + +#define PIN_PB02F_TCC2_WO2 _UINT32_(34) +#define MUX_PB02F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) + +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _UINT32_(44) +#define MUX_PB12F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) + +#define PIN_PB16F_TCC3_WO0 _UINT32_(48) +#define MUX_PB16F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) + +#define PIN_PB13F_TCC3_WO1 _UINT32_(45) +#define MUX_PB13F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) + +#define PIN_PB17F_TCC3_WO1 _UINT32_(49) +#define MUX_PB17F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _UINT32_(46) +#define MUX_PB14F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) + +#define PIN_PB30F_TCC4_WO0 _UINT32_(62) +#define MUX_PB30F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) + +#define PIN_PB15F_TCC4_WO1 _UINT32_(47) +#define MUX_PB15F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) + +#define PIN_PB31F_TCC4_WO1 _UINT32_(63) +#define MUX_PB31F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _UINT32_(24) +#define MUX_PA24H_USB_DM _UINT32_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UINT32_(1) << 24) + +#define PIN_PA25H_USB_DP _UINT32_(25) +#define MUX_PA25H_USB_DP _UINT32_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UINT32_(1) << 25) + +#define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) +#define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) + +#define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) +#define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) + + + +#endif /* _SAME51J19A_GPIO_H_ */ + diff --git a/firmware/src/packs/ATSAME51J19A_DFP/same51j19a.h b/firmware/src/packs/ATSAME51J19A_DFP/same51j19a.h new file mode 100644 index 0000000..36a1eb3 --- /dev/null +++ b/firmware/src/packs/ATSAME51J19A_DFP/same51j19a.h @@ -0,0 +1,1078 @@ +/* + * Header file for ATSAME51J19A + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* File generated from device description version 2022-02-14T14:27:08Z */ +#ifndef _SAME51J19A_H_ +#define _SAME51J19A_H_ + +/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ +#define HEADER_FORMAT_VERSION "2.1.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (1) +#define HEADER_FORMAT_VERSION_PATCH (0) + +/* SAME51J19A definitions + This file defines all structures and symbols for SAME51J19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAME51J19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /* 0 Power Manager (PM) */ + MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ + CAN0_IRQn = 78, /* 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /* 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ + PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /* 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /* 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /* 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /* Debug Level */ +#define __FPU_PRESENT 1 /* FPU present or not */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /* Trace Level */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same51.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAME51J19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/i2s.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Instance index for PAC (PAC) */ +#define ID_PM ( 1) /* Instance index for PM (PM) */ +#define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ +#define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ +#define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ +#define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ +#define ID_WDT ( 8) /* Instance index for WDT (WDT) */ +#define ID_RTC ( 9) /* Instance index for RTC (RTC) */ +#define ID_EIC ( 10) /* Instance index for EIC (EIC) */ +#define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ +#define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ +#define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ +#define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ +#define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ +#define ID_USB ( 32) /* Instance index for USB (USB) */ +#define ID_DSU ( 33) /* Instance index for DSU (DSU) */ +#define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ +#define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ +#define ID_PORT ( 36) /* Instance index for PORT (PORT) */ +#define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ +#define ID_HMATRIX ( 38) /* HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ +#define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ +#define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ +#define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ +#define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ +#define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ +#define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ +#define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ +#define ID_CAN0 ( 64) /* Control Area Network (CAN0) */ +#define ID_CAN1 ( 65) /* Control Area Network (CAN1) */ +#define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ +#define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ +#define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ +#define ID_TC5 ( 70) /* Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ +#define ID_AC ( 72) /* Instance index for AC (AC) */ +#define ID_AES ( 73) /* Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ +#define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ +#define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ +#define ID_CCL ( 78) /* Instance index for CCL (CCL) */ +#define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ +#define ID_SERCOM5 ( 97) /* Serial Communication Interface (SERCOM5) */ +#define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ +#define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ +#define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ +#define ID_DAC (105) /* Instance index for DAC (DAC) */ +#define ID_I2S (106) /* Instance index for I2S (I2S) */ +#define ID_PCC (107) /* Instance index for PCC (PCC) */ + +#define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00800100) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ +#define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42000000) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42000400) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ +#define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ +#define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00800100) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ +#define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ +#define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ +#define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ +#define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#include "pio/same51j19a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 512) +#define FLASH_NB_OF_PAGES _UINT32_( 1024) + +#define SW0_SIZE _UINT32_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UINT32_( 512) +#define TEMP_LOG_NB_OF_PAGES _UINT32_( 1) + +#define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 512) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 1) + +#define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UINT32_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00800100) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAME51J19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X61810302) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME51J19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAME51J19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /* ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /* ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/* Event User IDs for SAME51J19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAME51J19A_H_ */ + diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000..abebc95 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..a955d47 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1e255d5 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..2f048e4 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/core_cm4.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..e21cd14 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h b/firmware/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/firmware/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/firmware/src/smartEE/smartee.c b/firmware/src/smartEE/smartee.c new file mode 100644 index 0000000..6e68343 --- /dev/null +++ b/firmware/src/smartEE/smartee.c @@ -0,0 +1,81 @@ +#include "smartee.h" + +uint8_t SmartEEflag = ENABLE; + + +int8_t SmartEE_CheckConfig(void) +{ + int8_t ret = 0; + + uint32_t NVMCTRL_SEESBLK = ((*(uint32_t *)(USER_PAGE_ADDR + 4)) >> 0) & NVMCTRL_SEESBLK_MASK_BITS; + uint32_t NVMCTRL_SEEPSZ = ((*(uint32_t *)(USER_PAGE_ADDR + 4)) >> 4) & NVMCTRL_SEEPSZ_MASK_BITS; + + if (NVMCTRL_SEESBLK != NVMCTRL_SEESBLK_CONFIG || (NVMCTRL_SEEPSZ != NVMCTRL_SEEPSZ_CONFIG)) + { + ret = -1; + SmartEEflag = DISABLE; + } + + return ret; +} + + +int8_t SmartEE_Read(uint16_t address, uint8_t *data, uint8_t len) +{ + int8_t ret = 0; + uint8_t i = 0; + uint8_t len2read = 0; + + if(SmartEEflag == DISABLE) + { + ret = -1; + }else + { + if(address + len > SMARTEEPROM_SIZE) + { + len2read = SMARTEEPROM_SIZE - address; + }else{ + len2read = len; + } + + for(i=0; i SMARTEEPROM_SIZE) + { + len2write = SMARTEEPROM_SIZE - address; + }else{ + len2write = len; + } + + while (NVMCTRL_SmartEEPROM_IsBusy()); + + for(i=0; i