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This commit is contained in:
sunbeam 2024-05-14 16:05:43 +08:00
parent acac69d9a8
commit 9264a68c73
18 changed files with 1077 additions and 611 deletions
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4
CAN_Bootloader/main.aardio
View File

@ -14,7 +14,6 @@ btnReadF199={cls="button";text="读取F199";left=149;top=415;right=248;bottom=44
btnReadHw={cls="button";text="读取硬件版本号";left=149;top=381;right=248;bottom=409;z=12}; btnReadHw={cls="button";text="读取硬件版本号";left=149;top=381;right=248;bottom=409;z=12};
btnReadSw={cls="button";text="读取软件版本号";left=37;top=382;right=136;bottom=410;z=10}; btnReadSw={cls="button";text="读取软件版本号";left=37;top=382;right=136;bottom=410;z=10};
btnTest={cls="button";text="停止";left=149;top=316;right=248;bottom=344;z=11}; btnTest={cls="button";text="停止";left=149;top=316;right=248;bottom=344;z=11};
button={cls="button";text="Button";left=248;top=445;right=278;bottom=459;z=26};
cbbChannel={cls="combobox";left=58;top=64;right=191;bottom=90;edge=1;items={};mode="dropdown";z=3}; cbbChannel={cls="combobox";left=58;top=64;right=191;bottom=90;edge=1;items={};mode="dropdown";z=3};
cbbDev={cls="combobox";left=58;top=27;right=191;bottom=53;edge=1;items={};mode="dropdown";z=1}; cbbDev={cls="combobox";left=58;top=27;right=191;bottom=53;edge=1;items={};mode="dropdown";z=1};
checkbox={cls="checkbox";text="CANFD设备";left=151;top=101;right=248;bottom=120;checked=1;z=21}; checkbox={cls="checkbox";text="CANFD设备";left=151;top=101;right=248;bottom=120;checked=1;z=21};
@ -256,9 +255,6 @@ mainForm.onClose = function(hwnd,message,wParam,lParam){
} }
mainForm.button.oncommand = function(id,event){
DiagReadDID(0xF191);
}
mainForm.show(); mainForm.show();
return win.loopMessage(); return win.loopMessage();

41
CAN_Bootloader/user/DiagBootcode.aardio
View File

@ -405,17 +405,6 @@ FuncBootSeq = function(){
} }
} }
case 19 { case 19 {
if(sendstate == 0){//复位
FuncClearState();
FuncReq11(0x03);
}
else {
var ret = FuncWait(0x11);
nextstate(ret);
}
}
case 20 {
if(sendstate == 0){//等待复位完成 if(sendstate == 0){//等待复位完成
delaycount = 0; delaycount = 0;
FuncClearState(); FuncClearState();
@ -428,8 +417,32 @@ FuncBootSeq = function(){
} }
} }
case 20 {
if(sendstate == 0){//复位
FuncClearState();
FuncReq11(0x03);
}
else {
var ret = FuncWait(0x11);
nextstate(ret);
}
}
case 21 { case 21 {
if(sendstate == 0){//等待复位完成
delaycount = 0;
FuncClearState();
}
else {
delaycount += 1;
if(delaycount > 200){
nextstate(0);//延时1S
}
}
}
case 22 {
if(sendstate == 0){ if(sendstate == 0){
FuncReq10(true,0x03);//进入扩展会话 FuncReq10(true,0x03);//进入扩展会话
FuncClearState(); FuncClearState();
@ -439,7 +452,7 @@ FuncBootSeq = function(){
nextstate(ret); nextstate(ret);
} }
} }
case 22 { case 23 {
if(sendstate == 0){ if(sendstate == 0){
FuncReq28(0x00,0x01);//开启发送 FuncReq28(0x00,0x01);//开启发送
FuncClearState(); FuncClearState();
@ -449,7 +462,7 @@ FuncBootSeq = function(){
nextstate(ret); nextstate(ret);
} }
} }
case 23 { case 24 {
if(sendstate == 0){ if(sendstate == 0){
FuncReq85(0x01);//开启DTC FuncReq85(0x01);//开启DTC
FuncClearState(); FuncClearState();
@ -459,7 +472,7 @@ FuncBootSeq = function(){
nextstate(ret); nextstate(ret);
} }
} }
case 24 { case 25 {
if(sendstate == 0){ if(sendstate == 0){
FuncReq10(true,0x01);//进入默认会话 FuncReq10(true,0x01);//进入默认会话
FuncClearState(); FuncClearState();

21
cva_asw_m0146/.vscode/c_cpp_properties.json vendored Normal file
View File

@ -0,0 +1,21 @@
{
"configurations": [
{
"name": "Win32",
"includePath": [
"${workspaceFolder}/**",
"E:\\Program Files\\IAR Systems\\Embedded Workbench 9.2\\arm\\inc\\c\\"
],
"defines": [
"MCU_CVM0144FMLH",
"__INT32_T_TYPE__=signed long",
"__UINT32_T_TYPE__=unsigned long",
"__INT8_T_TYPE__=signed char",
"__UINT8_T_TYPE__=unsigned char",
"__INT16_T_TYPE__=signed int",
"__UINT16_T_TYPE__=unsigned int"
]
}
],
"version": 4
}

17
cva_asw_m0146/.vscode/settings.json vendored
View File

@ -1,6 +1,19 @@
{ {
"files.associations": { "files.associations": {
"mcu.h": "c", "mcu.h": "c",
"segger_rtt.h": "c" "segger_rtt.h": "c",
} "apptask.h": "c",
"uds_user.h": "c",
"uds.h": "c",
"stimer.h": "c",
"ycheck.h": "c",
"yvals.h": "c",
"stddef.h": "c",
"stdint.h": "c",
"hwctrl.h": "c",
"cvm014x_features.h": "c",
"clock_drv.h": "c",
"irq_drv.h": "c"
},
"C_Cpp.default.compilerPath": ""
} }

19
cva_asw_m0146/cva_asw_m0146.ewp
View File

@ -359,6 +359,8 @@
<state>$PROJ_DIR$\SDK\platform\devices\CVM014x\drivers</state> <state>$PROJ_DIR$\SDK\platform\devices\CVM014x\drivers</state>
<state>$PROJ_DIR$\src\TLE9461</state> <state>$PROJ_DIR$\src\TLE9461</state>
<state>$PROJ_DIR$\src\RTT</state> <state>$PROJ_DIR$\src\RTT</state>
<state>$PROJ_DIR$\SDK\platform\devices\CVM014x\drivers\clock</state>
<state>$PROJ_DIR$\SDK\platform\devices\CVM014x\drivers\cpu\irq</state>
</option> </option>
<option> <option>
<name>CCStdIncCheck</name> <name>CCStdIncCheck</name>
@ -444,19 +446,19 @@
</option> </option>
<option> <option>
<name>CCEncSource</name> <name>CCEncSource</name>
<state>0</state> <state>2</state>
</option> </option>
<option> <option>
<name>CCEncOutput</name> <name>CCEncOutput</name>
<state>0</state> <state>2</state>
</option> </option>
<option> <option>
<name>CCEncOutputBom</name> <name>CCEncOutputBom</name>
<state>1</state> <state>0</state>
</option> </option>
<option> <option>
<name>CCEncInput</name> <name>CCEncInput</name>
<state>0</state> <state>1</state>
</option> </option>
<option> <option>
<name>IccExceptions2</name> <name>IccExceptions2</name>
@ -2959,11 +2961,20 @@
<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name> <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
</file> </file>
</group> </group>
<file>
<name>$PROJ_DIR$\src\appTask.c</name>
</file>
<file> <file>
<name>$PROJ_DIR$\src\extern.c</name> <name>$PROJ_DIR$\src\extern.c</name>
</file> </file>
<file>
<name>$PROJ_DIR$\src\hwctrl.c</name>
</file>
<file> <file>
<name>$PROJ_DIR$\src\main.c</name> <name>$PROJ_DIR$\src\main.c</name>
</file> </file>
<file>
<name>$PROJ_DIR$\src\MotorCtrl.c</name>
</file>
</group> </group>
</project> </project>

9
cva_asw_m0146/cva_asw_m0146.ewt
View File

@ -3600,11 +3600,20 @@
<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name> <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
</file> </file>
</group> </group>
<file>
<name>$PROJ_DIR$\src\appTask.c</name>
</file>
<file> <file>
<name>$PROJ_DIR$\src\extern.c</name> <name>$PROJ_DIR$\src\extern.c</name>
</file> </file>
<file>
<name>$PROJ_DIR$\src\hwctrl.c</name>
</file>
<file> <file>
<name>$PROJ_DIR$\src\main.c</name> <name>$PROJ_DIR$\src\main.c</name>
</file> </file>
<file>
<name>$PROJ_DIR$\src\MotorCtrl.c</name>
</file>
</group> </group>
</project> </project>

2
cva_asw_m0146/settings/cva_asw_m0146.dnx
View File

@ -25,8 +25,8 @@
<MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue> <MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
</PlDriver> </PlDriver>
<ArmDriver> <ArmDriver>
<EnableCache>0</EnableCache>
<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration> <EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
<EnableCache>0</EnableCache>
</ArmDriver> </ArmDriver>
<DebugChecksum> <DebugChecksum>
<Checksum>3190234441</Checksum> <Checksum>3190234441</Checksum>

28
cva_asw_m0146/settings/cva_asw_m0146.wsdt
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File diff suppressed because one or more lines are too long

29
cva_asw_m0146/src/MotorCtrl.c Normal file
View File

@ -0,0 +1,29 @@
#include "MotorCtrl.h"
#include "hwctrl.h"
void MotorCtrl_Init(McuType *obj)
{
for (uint8_t i = 0; i < 6; i++)
{
hw_MotorCtrl(obj, i, Motor_ACT_NOACT);
}
}
void MotorCtrl_Maintask(McuType *obj)//10ms task
{
static uint8_t motor_cnt = 0,motor_act=0,run_count=0;
run_count++;
if (run_count > 100)
{
run_count = 0;
}
}

12
cva_asw_m0146/src/MotorCtrl.h Normal file
View File

@ -0,0 +1,12 @@
#ifndef __MOTORCTRL_H
#define __MOTORCTRL_H
#include "Mcu.h"
void MotorCtrl_Init(McuType *obj);
void MotorCtrl_Maintask(McuType *obj);
#endif

182
cva_asw_m0146/src/TLE9461/TLE94x1_DEFINES.h
View File

@ -2477,7 +2477,7 @@ typedef enum
SBC_MODE_SLEEP, SBC_MODE_SLEEP,
SBC_MODE_STOP, SBC_MODE_STOP,
SBC_MODE_RESET SBC_MODE_RESET
}; }SBC_MODE_ENUM;
typedef enum typedef enum
{ {
@ -2485,13 +2485,13 @@ typedef enum
SBC_VCC2_ON_NORMAL, SBC_VCC2_ON_NORMAL,
SBC_VCC2_ON_NORMAL_STOP, SBC_VCC2_ON_NORMAL_STOP,
SBC_VCC2_ON_ALWAYS SBC_VCC2_ON_ALWAYS
}; }SBC_VCC2_ENUM;
typedef enum typedef enum
{ {
SBC_VCC1_OV_RST_NOACTION = 0x00U, SBC_VCC1_OV_RST_NOACTION = 0x00U,
SBC_VCC1_OV_RST_RESTART_FAILSAFE SBC_VCC1_OV_RST_RESTART_FAILSAFE
}; }SBC_VCC1_OV_RST_ENUM;
typedef enum typedef enum
{ {
@ -2499,7 +2499,7 @@ typedef enum
SBC_VCC1_RT_VRT2, SBC_VCC1_RT_VRT2,
SBC_VCC1_RT_VRT3, SBC_VCC1_RT_VRT3,
SBC_VCC1_RT_VRT4 SBC_VCC1_RT_VRT4
}; }SBC_VCC1_RT_ENUM;
/* -------------------------------- HW_CTRL_0 ----------------------------------- */ /* -------------------------------- HW_CTRL_0 ----------------------------------- */
@ -2508,25 +2508,25 @@ typedef enum
{ {
SBC_SOFT_RESET_RST_TRIGGER_SOFTRST = 0x00U, SBC_SOFT_RESET_RST_TRIGGER_SOFTRST = 0x00U,
SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST
}; }SBC_SOFT_RESET_RST_ENUM;
typedef enum typedef enum
{ {
SBC_FO_ON_NOT_ACTIVE = 0x00U, SBC_FO_ON_NOT_ACTIVE = 0x00U,
SBC_FO_ON_ACTIVE SBC_FO_ON_ACTIVE
}; }SBC_FO_ON_ENUM;
typedef enum typedef enum
{ {
SBC_CP_EN_OFF = 0x00U, SBC_CP_EN_OFF = 0x00U,
SBC_CP_EN_ON SBC_CP_EN_ON
}; }SBC_CP_EN_ENUM;
typedef enum typedef enum
{ {
SBC_CFG1_RESTART_FAILSAFE_2WDFAIL = 0x00U, SBC_CFG1_RESTART_FAILSAFE_2WDFAIL = 0x00U,
SBC_CFG1_RESTART_FAILSAFE_1WDFAIL SBC_CFG1_RESTART_FAILSAFE_1WDFAIL
}; }SBC_CFG1_RESTART_FAILSAFE_ENUM;
/* -------------------------------- WD_CTRL ------------------------------------- */ /* -------------------------------- WD_CTRL ------------------------------------- */
@ -2535,25 +2535,25 @@ typedef enum
{ {
SBC_CHECKSUM_0 = 0x00U, SBC_CHECKSUM_0 = 0x00U,
SBC_CHECKSUM_1 SBC_CHECKSUM_1
}; }SBC_CHECKSUM_ENUM;
typedef enum typedef enum
{ {
SBC_WD_STM_EN_0_ACTIVE_STOPMODE = 0x00U, SBC_WD_STM_EN_0_ACTIVE_STOPMODE = 0x00U,
SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE
}; }SBC_WD_STM_EN_0_ENUM;
typedef enum typedef enum
{ {
SBC_WD_WIN_TIMEOUT_WD = 0x00U, SBC_WD_WIN_TIMEOUT_WD = 0x00U,
SBC_WD_WIN_WINDOW_WD SBC_WD_WIN_WINDOW_WD
}; }SBC_WD_WIN_ENUM;
typedef enum typedef enum
{ {
SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE = 0x00U, SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE = 0x00U,
SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE
}; }SBC_WD_EN_WK_BUS_ENUM;
typedef enum typedef enum
{ {
@ -2565,7 +2565,7 @@ typedef enum
SBC_WD_TIMER_500MS, SBC_WD_TIMER_500MS,
SBC_WD_TIMER_1000MS, SBC_WD_TIMER_1000MS,
SBC_WD_TIMER_10000MS SBC_WD_TIMER_10000MS
}; }SBC_WD_TIMER_ENUM;
/* -------------------------------- BUS_CTRL_0 ---------------------------------- */ /* -------------------------------- BUS_CTRL_0 ---------------------------------- */
@ -2579,7 +2579,7 @@ typedef enum
SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK, SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK,
SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK, SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK,
SBC_BUS_CTRL_0_CAN_NORMAL_SWK SBC_BUS_CTRL_0_CAN_NORMAL_SWK
}; }SBC_BUS_CTRL_0_CAN_ENUM;
/* -------------------------------- WK_CTRL_0 ----------------------------------- */ /* -------------------------------- WK_CTRL_0 ----------------------------------- */
@ -2588,13 +2588,13 @@ typedef enum
{ {
WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED = 0x00U, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED = 0x00U,
WK_CTRL_0_TIMER_WK_EN_WAKESOURCE WK_CTRL_0_TIMER_WK_EN_WAKESOURCE
}; }WK_CTRL_0_TIMER_WK_EN_ENUM;
typedef enum typedef enum
{ {
SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE = 0x00U, SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE = 0x00U,
SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE
}; }SBC_WD_STM_EN_1_ENUM;
/* -------------------------------- WK_CTRL_1 ----------------------------------- */ /* -------------------------------- WK_CTRL_1 ----------------------------------- */
@ -2603,19 +2603,19 @@ typedef enum
{ {
SBC_INT_GLOBAL_WAKESOURCES_ONLY = 0x00U, SBC_INT_GLOBAL_WAKESOURCES_ONLY = 0x00U,
SBC_INT_GLOBAL_ALLINFORMATIONBITS SBC_INT_GLOBAL_ALLINFORMATIONBITS
}; }SBC_INT_GLOBAL_ENUM;
typedef enum typedef enum
{ {
SBC_WK_MEAS_WK_AS_WAKEUP = 0x00U, SBC_WK_MEAS_WK_AS_WAKEUP = 0x00U,
SBC_WK_MEAS_WK_AS_VOLTAGESENSING SBC_WK_MEAS_WK_AS_VOLTAGESENSING
}; }SBC_WK_MEAS_ENUM;
typedef enum typedef enum
{ {
SBC_WK_EN_WAKEUP_DISABLED = 0x00U, SBC_WK_EN_WAKEUP_DISABLED = 0x00U,
SBC_WK_EN_WAKEUP_ENABLED SBC_WK_EN_WAKEUP_ENABLED
}; }SBC_WK_EN_ENUM;
/* -------------------------------- WK_PUPD_CTRL -------------------------------- */ /* -------------------------------- WK_PUPD_CTRL -------------------------------- */
@ -2626,7 +2626,7 @@ typedef enum
SBC_GPIO_WK_PUPD_PULLDOWN, SBC_GPIO_WK_PUPD_PULLDOWN,
SBC_GPIO_WK_PUPD_PULLUP, SBC_GPIO_WK_PUPD_PULLUP,
SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING
}; }SBC_GPIO_WK_PUPD_ENUM;
typedef enum typedef enum
{ {
@ -2634,7 +2634,7 @@ typedef enum
SBC_WK_PUPD_PULLDOWN, SBC_WK_PUPD_PULLDOWN,
SBC_WK_PUPD_PULLUP, SBC_WK_PUPD_PULLUP,
SBC_WK_PUPD_AUTOMATIC_PULLING SBC_WK_PUPD_AUTOMATIC_PULLING
}; }SBC_WK_PUPD_ENUM;
/* -------------------------------- BUS_CTRL_3 ---------------------------------- */ /* -------------------------------- BUS_CTRL_3 ---------------------------------- */
@ -2643,7 +2643,7 @@ typedef enum
{ {
SBC_CAN_FLASH_DISABLED = 0x00U, SBC_CAN_FLASH_DISABLED = 0x00U,
SBC_CAN_FLASH_ENABLED SBC_CAN_FLASH_ENABLED
}; }SBC_CAN_FLASH_ENUM;
/* -------------------------------- TIMER_CTRL ---------------------------------- */ /* -------------------------------- TIMER_CTRL ---------------------------------- */
@ -2657,7 +2657,7 @@ typedef enum
SBC_TIMER_ON_10MS, SBC_TIMER_ON_10MS,
SBC_TIMER_ON_20MS, SBC_TIMER_ON_20MS,
SBC_TIMER_ON_TIMEROFF_HSX_HIGH SBC_TIMER_ON_TIMEROFF_HSX_HIGH
}; }SBC_TIMER_ON_ENUM;
typedef enum typedef enum
{ {
@ -2677,7 +2677,7 @@ typedef enum
SBC_TIMER_PER_200S, SBC_TIMER_PER_200S,
SBC_TIMER_PER_500S, SBC_TIMER_PER_500S,
SBC_TIMER_PER_1000S SBC_TIMER_PER_1000S
}; }SBC_TIMER_PER_ENUM;
/* -------------------------------- HW_CTRL_1 ----------------------------------- */ /* -------------------------------- HW_CTRL_1 ----------------------------------- */
@ -2686,25 +2686,25 @@ typedef enum
{ {
SBC_RSTN_HYS_DEFAULT = 0x00U, SBC_RSTN_HYS_DEFAULT = 0x00U,
SBC_RSTN_HYS_HIGHEST_VRT SBC_RSTN_HYS_HIGHEST_VRT
}; }SBC_RSTN_HYS_ENUM;
typedef enum typedef enum
{ {
SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION = 0x00U, SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION = 0x00U,
SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS
}; }SBC_TSD2_DEL_ENUM;
typedef enum typedef enum
{ {
SBC_RSTN_DEL_TRD1 = 0x00U, SBC_RSTN_DEL_TRD1 = 0x00U,
SBC_RSTN_DEL_TRD2 SBC_RSTN_DEL_TRD2
}; }SBC_RSTN_DEL_ENUM;
typedef enum typedef enum
{ {
SBC_CFG_LOCK_0_NOTLOCKED = 0x00U, SBC_CFG_LOCK_0_NOTLOCKED = 0x00U,
SBC_CFG_LOCK_0_LOCKED SBC_CFG_LOCK_0_LOCKED
}; }SBC_CFG_LOCK_0_ENUM;
/* -------------------------------- HW_CTRL_2 ----------------------------------- */ /* -------------------------------- HW_CTRL_2 ----------------------------------- */
@ -2715,13 +2715,13 @@ typedef enum
SBC_2MHZ_FREQ_2_0_MHZ, SBC_2MHZ_FREQ_2_0_MHZ,
SBC_2MHZ_FREQ_2_2_MHZ, SBC_2MHZ_FREQ_2_2_MHZ,
SBC_2MHZ_FREQ_2_4_MHZ SBC_2MHZ_FREQ_2_4_MHZ
}; }SBC_2MHZ_FREQ_ENUM;
typedef enum typedef enum
{ {
SBC_I_PEAK_TH_LOW = 0x00U, SBC_I_PEAK_TH_LOW = 0x00U,
SBC_I_PEAK_TH_HIGH SBC_I_PEAK_TH_HIGH
}; }SBC_I_PEAK_TH_ENUM;
typedef enum typedef enum
{ {
@ -2729,13 +2729,13 @@ typedef enum
SBC_SS_MOD_FR_15_6KHZ, SBC_SS_MOD_FR_15_6KHZ,
SBC_SS_MOD_FR_31_2KHZ, SBC_SS_MOD_FR_31_2KHZ,
SBC_SS_MOD_FR_62_5KHZ SBC_SS_MOD_FR_62_5KHZ
}; }SBC_SS_MOD_FR_ENUM;
typedef enum typedef enum
{ {
SBC_CFG_LOCK_1_NOTLOCKED = 0x00U, SBC_CFG_LOCK_1_NOTLOCKED = 0x00U,
SBC_CFG_LOCK_1_LOCKED SBC_CFG_LOCK_1_LOCKED
}; }SBC_CFG_LOCK_ENUM;
/* -------------------------------- GPIO_CTRL ----------------------------------- */ /* -------------------------------- GPIO_CTRL ----------------------------------- */
@ -2748,7 +2748,7 @@ typedef enum
SBC_GPIO_WAKE_INPUT, SBC_GPIO_WAKE_INPUT,
SBC_GPIO_LSS_PWM, SBC_GPIO_LSS_PWM,
SBC_GPIO_HSS_PWM SBC_GPIO_HSS_PWM
}; }SBC_GPIO_ENUM;
/* -------------------------------- PWM_CTRL ------------------------------------ */ /* -------------------------------- PWM_CTRL ------------------------------------ */
@ -2766,7 +2766,7 @@ typedef enum
SBC_PWM_DC_80 = 0xCCU, SBC_PWM_DC_80 = 0xCCU,
SBC_PWM_DC_90 = 0xE6U, SBC_PWM_DC_90 = 0xE6U,
SBC_PWM_DC_100 = 0xFFU SBC_PWM_DC_100 = 0xFFU
}; }SBC_PWM_DC_ENUM;
/* -------------------------------- PWM_FREQ_CTRL ------------------------------- */ /* -------------------------------- PWM_FREQ_CTRL ------------------------------- */
@ -2777,7 +2777,7 @@ typedef enum
SBC_PWM_FREQ_200HZ, SBC_PWM_FREQ_200HZ,
SBC_PWM_FREQ_325HZ, SBC_PWM_FREQ_325HZ,
SBC_PWM_FREQ_400HZ SBC_PWM_FREQ_400HZ
}; }SBC_PWM_FREQ_ENUM;
/* -------------------------------- HW_CTRL_3 ----------------------------------- */ /* -------------------------------- HW_CTRL_3 ----------------------------------- */
@ -2786,7 +2786,7 @@ typedef enum
{ {
SBC_TSD_THR_DEFAULT = 0x00U, SBC_TSD_THR_DEFAULT = 0x00U,
SBC_TSD_THR_HIGHER SBC_TSD_THR_HIGHER
}; }SBC_TSD_THR_ENUM;
typedef enum typedef enum
{ {
@ -2794,7 +2794,7 @@ typedef enum
SBC_ICC1_LIM_ADJ_1000MA, SBC_ICC1_LIM_ADJ_1000MA,
SBC_ICC1_LIM_ADJ_1200MA, SBC_ICC1_LIM_ADJ_1200MA,
SBC_ICC1_LIM_ADJ_1500MA SBC_ICC1_LIM_ADJ_1500MA
}; }SBC_ICC1_LIM_ADJ_ENUM;
@ -2813,25 +2813,25 @@ typedef enum
{ {
SBC_OSC_CAL_DISABLED = 0x00U, SBC_OSC_CAL_DISABLED = 0x00U,
SBC_OSC_CAL_ENABLED SBC_OSC_CAL_ENABLED
}; }SBC_OSC_CAL_ENUM;
typedef enum typedef enum
{ {
SBC_TRIM_EN_LOCKED = 0x00U, SBC_TRIM_EN_LOCKED = 0x00U,
SBC_TRIM_EN_UNLOCKED = 0x03U SBC_TRIM_EN_UNLOCKED = 0x03U
}; }SBC_TRIM_EN_ENUM;
typedef enum typedef enum
{ {
SBC_CANTO_MASK_NOINT = 0x00U, SBC_CANTO_MASK_NOINT = 0x00U,
SBC_CANTO_MASK_INT_ON_TO SBC_CANTO_MASK_INT_ON_TO
}; }SBC_CANTO_MASK_ENUM;
typedef enum typedef enum
{ {
SBC_CFG_VAL_NOTVALID = 0x00U, SBC_CFG_VAL_NOTVALID = 0x00U,
SBC_CFG_VAL_VALID SBC_CFG_VAL_VALID
}; }SBC_CFG_VAL_ENUM;
/* -------------------------------- SWK_ID0_CTRL --------------------------------- */ /* -------------------------------- SWK_ID0_CTRL --------------------------------- */
@ -2840,13 +2840,13 @@ typedef enum
{ {
SBC_RTR_NORMAL_DATA_FRAME = 0x00U, SBC_RTR_NORMAL_DATA_FRAME = 0x00U,
SBC_RTR_REMOTE_TRANSMIT_REQUEST SBC_RTR_REMOTE_TRANSMIT_REQUEST
}; }SBC_RTR_ENUM;
typedef enum typedef enum
{ {
SBC_IDE_STANDARD = 0x00U, SBC_IDE_STANDARD = 0x00U,
SBC_IDE_EXTENDED SBC_IDE_EXTENDED
}; }SBC_IDE_ENUM;
/* -------------------------------- SWK_DLC_CTRL --------------------------------- */ /* -------------------------------- SWK_DLC_CTRL --------------------------------- */
@ -2862,7 +2862,7 @@ typedef enum
SBC_DLC_6BYTES, SBC_DLC_6BYTES,
SBC_DLC_7BYTES, SBC_DLC_7BYTES,
SBC_DLC_8BYTES SBC_DLC_8BYTES
}; }SBC_DLC_ENUM;
/* -------------------------------- SWK_CAN_FD_CTRL ------------------------------ */ /* -------------------------------- SWK_CAN_FD_CTRL ------------------------------ */
@ -2871,13 +2871,13 @@ typedef enum
{ {
SBC_DIS_ERR_CNT_ENABLED = 0x00U, SBC_DIS_ERR_CNT_ENABLED = 0x00U,
SBC_DIS_ERR_CNT_DISABLED SBC_DIS_ERR_CNT_DISABLED
}; }SBC_DIS_ERR_CNT_ENUM;
typedef enum typedef enum
{ {
SBC_RX_FILT_BYP_NOTBYPASSED = 0x00U, SBC_RX_FILT_BYP_NOTBYPASSED = 0x00U,
SBC_RX_FILT_BYP_BYPASSED SBC_RX_FILT_BYP_BYPASSED
}; }SBC_RX_FILT_BYP_ENUM;
typedef enum typedef enum
{ {
@ -2889,13 +2889,13 @@ typedef enum
SBC_FD_FILTER_300NS, SBC_FD_FILTER_300NS,
SBC_FD_FILTER_350NS, SBC_FD_FILTER_350NS,
SBC_FD_FILTER_700NS SBC_FD_FILTER_700NS
}; }SBC_FD_FILTER_ENUM;
typedef enum typedef enum
{ {
SBC_CAN_FD_EN_DISABLED = 0x00U, SBC_CAN_FD_EN_DISABLED = 0x00U,
SBC_CAN_FD_EN_ENABLED SBC_CAN_FD_EN_ENABLED
}; }SBC_CAN_FD_EN_ENUM;
/* -------------------------------- SWK_OPT_CTRL --------------------------------- */ /* -------------------------------- SWK_OPT_CTRL --------------------------------- */
@ -2904,7 +2904,7 @@ typedef enum
{ {
SBC_RX_WK_SEL_LOWPOWER = 0x00U, SBC_RX_WK_SEL_LOWPOWER = 0x00U,
SBC_RX_WK_SEL_STANDARD SBC_RX_WK_SEL_STANDARD
}; }SBC_RX_WK_SEL_ENUM;
/* -------------------------------- SWK_CDR_CTRL1 -------------------------------- */ /* -------------------------------- SWK_CDR_CTRL1 -------------------------------- */
@ -2915,13 +2915,13 @@ typedef enum
SBC_SEL_FILT_TC16, SBC_SEL_FILT_TC16,
SBC_SEL_FILT_TC32, SBC_SEL_FILT_TC32,
SBC_SEL_FILT_ADAPT SBC_SEL_FILT_ADAPT
}; }SBC_SEL_FILT_ENUM;
typedef enum typedef enum
{ {
SBC_CDR_EN_DISABLED = 0x00U, SBC_CDR_EN_DISABLED = 0x00U,
SBC_CDR_EN_ENABLED SBC_CDR_EN_ENABLED
}; }SBC_CDR_EN_ENUM;
/* -------------------------------- SWK_CDR_CTRL2 -------------------------------- */ /* -------------------------------- SWK_CDR_CTRL2 -------------------------------- */
@ -2932,7 +2932,7 @@ typedef enum
SBC_SEL_OSC_CLK_40MHZ, SBC_SEL_OSC_CLK_40MHZ,
SBC_SEL_OSC_CLK_20MHZ, SBC_SEL_OSC_CLK_20MHZ,
SBC_SEL_OSC_CLK_10MHZ SBC_SEL_OSC_CLK_10MHZ
}; }SBC_SEL_OSC_CLK_ENUM;
@ -2951,25 +2951,25 @@ typedef enum
{ {
SBC_VS_UV_NOEVENT = 0x00U, SBC_VS_UV_NOEVENT = 0x00U,
SBC_VS_UV_EVENT SBC_VS_UV_EVENT
}; }SBC_VS_UV_ENUM;
typedef enum typedef enum
{ {
SBC_VS_OV_NOEVENT = 0x00U, SBC_VS_OV_NOEVENT = 0x00U,
SBC_VS_OV_EVENT SBC_VS_OV_EVENT
}; }SBC_VS_OV_ENUM;
typedef enum typedef enum
{ {
SBC_VCC1_OV_NOEVENT = 0x00U, SBC_VCC1_OV_NOEVENT = 0x00U,
SBC_VCC1_OV_EVENT SBC_VCC1_OV_EVENT
}; }SBC_VCC1_OV_ENUM;
typedef enum typedef enum
{ {
SBC_VCC1_UV_PREWARN_NOEVENT = 0x00U, SBC_VCC1_UV_PREWARN_NOEVENT = 0x00U,
SBC_VCC1_UV_PREWARN_EVENT SBC_VCC1_UV_PREWARN_EVENT
}; }SBC_VCC1_UV_PREWARN_ENUM;
/* -------------------------------- SUP_STAT_0 ----------------------------------- */ /* -------------------------------- SUP_STAT_0 ----------------------------------- */
@ -2978,31 +2978,31 @@ typedef enum
{ {
SBC_POR_NOEVENT = 0x00U, SBC_POR_NOEVENT = 0x00U,
SBC_POR_EVENT SBC_POR_EVENT
}; }SBC_POR_ENUM;
typedef enum typedef enum
{ {
SBC_VCC2_OT_NOEVENT = 0x00U, SBC_VCC2_OT_NOEVENT = 0x00U,
SBC_VCC2_OT_EVENT SBC_VCC2_OT_EVENT
}; }SBC_VCC2_OT_ENUM;
typedef enum typedef enum
{ {
SBC_VCC2_UV_NOEVENT = 0x00U, SBC_VCC2_UV_NOEVENT = 0x00U,
SBC_VCC2_UV_EVENT SBC_VCC2_UV_EVENT
}; }SBC_VCC2_UV_ENUM;
typedef enum typedef enum
{ {
SBC_VCC1_SC_NOEVENT = 0x00U, SBC_VCC1_SC_NOEVENT = 0x00U,
SBC_VCC1_SC_TO_GND_EVENT SBC_VCC1_SC_TO_GND_EVENT
}; }SBC_VCC1_SC_ENUM;
typedef enum typedef enum
{ {
SBC_VCC1_UV_NOEVENT = 0x00U, SBC_VCC1_UV_NOEVENT = 0x00U,
SBC_VCC1_UV_EVENT SBC_VCC1_UV_EVENT
}; }SBC_VCC1_UV_ENUM;
/* -------------------------------- THERM_STAT ----------------------------------- */ /* -------------------------------- THERM_STAT ----------------------------------- */
@ -3011,25 +3011,25 @@ typedef enum
{ {
SBC_TSD2_SAFE_NOSAFESTATE = 0x00U, SBC_TSD2_SAFE_NOSAFESTATE = 0x00U,
SBC_TSD2_SAFE_SAFESTATE_DETECTED SBC_TSD2_SAFE_SAFESTATE_DETECTED
}; }SBC_TSD2_SAFE_ENUM;
typedef enum typedef enum
{ {
SBC_TSD2_NOEVENT = 0x00U, SBC_TSD2_NOEVENT = 0x00U,
SBC_TSD2_EVENT SBC_TSD2_EVENT
}; }SBC_TSD2_ENUM;
typedef enum typedef enum
{ {
SBC_TSD1_NOEVENT = 0x00U, SBC_TSD1_NOEVENT = 0x00U,
SBC_TSD1_EVENT SBC_TSD1_EVENT
}; }SBC_TSD1_ENUM;
typedef enum typedef enum
{ {
SBC_TPW_NOEVENT = 0x00U, SBC_TPW_NOEVENT = 0x00U,
SBC_TPW_EVENT SBC_TPW_EVENT
}; }SBC_TPW_ENUM;
/* -------------------------------- DEV_STAT ------------------------------------- */ /* -------------------------------- DEV_STAT ------------------------------------- */
@ -3039,26 +3039,26 @@ typedef enum
SBC_DEV_STAT_CLEARED = 0x00U, SBC_DEV_STAT_CLEARED = 0x00U,
SBC_DEV_STAT_RESTART_AFTER_FAIL, SBC_DEV_STAT_RESTART_AFTER_FAIL,
SBC_DEV_STAT_SLEEP_MODE SBC_DEV_STAT_SLEEP_MODE
}; }SBC_DEV_STAT_ENUM;
typedef enum typedef enum
{ {
SBC_WD_FAIL_NOFAIL = 0x00U, SBC_WD_FAIL_NOFAIL = 0x00U,
SBC_WD_FAIL_1FAIL, SBC_WD_FAIL_1FAIL,
SBC_WD_FAIL_2FAIL SBC_WD_FAIL_2FAIL
}; }SBC_WD_FAIL_ENUM;
typedef enum typedef enum
{ {
SBC_SPI_FAIL_NOEVENT = 0x00U, SBC_SPI_FAIL_NOEVENT = 0x00U,
SBC_SPI_FAIL_EVENT SBC_SPI_FAIL_EVENT
}; }SBC_SPI_FAIL_ENUM;
typedef enum typedef enum
{ {
SBC_FAILURE_NOEVENT = 0x00U, SBC_FAILURE_NOEVENT = 0x00U,
SBC_FAILURE_EVENT SBC_FAILURE_EVENT
}; }SBC_FAILURE_ENUM;
/* -------------------------------- BUS_STAT ------------------------------------- */ /* -------------------------------- BUS_STAT ------------------------------------- */
@ -3067,13 +3067,13 @@ typedef enum
{ {
SBC_CANTO_NORMAL = 0x00U, SBC_CANTO_NORMAL = 0x00U,
SBC_CANTO_TIMEOUT SBC_CANTO_TIMEOUT
}; }SBC_CANTO_ENUM;
typedef enum typedef enum
{ {
SBC_SYSERR_NOEVENT = 0x00U, SBC_SYSERR_NOEVENT = 0x00U,
SBC_SYSERR_DETECTED SBC_SYSERR_DETECTED
}; }SBC_SYSERR_ENUM;
typedef enum typedef enum
{ {
@ -3081,13 +3081,13 @@ typedef enum
SBC_CAN_FAIL_TSD, SBC_CAN_FAIL_TSD,
SBC_CAN_FAIL_TXD_DOM_TO, SBC_CAN_FAIL_TXD_DOM_TO,
SBC_CAN_FAIL_BUS_DOM_TO SBC_CAN_FAIL_BUS_DOM_TO
}; }SBC_CAN_FAIL_ENUM;
typedef enum typedef enum
{ {
SBC_VCAN_UV_NOEVENT = 0x00U, SBC_VCAN_UV_NOEVENT = 0x00U,
SBC_VCAN_UV_EVENT SBC_VCAN_UV_EVENT
}; }SBC_VCAN_UV_ENUM;
/* -------------------------------- WK_STAT_0 ------------------------------------ */ /* -------------------------------- WK_STAT_0 ------------------------------------ */
@ -3096,19 +3096,19 @@ typedef enum
{ {
SBC_CAN_WU_NOEVENT = 0x00U, SBC_CAN_WU_NOEVENT = 0x00U,
SBC_CAN_WU_EVENT SBC_CAN_WU_EVENT
}; }SBC_CAN_WU_ENUM;
typedef enum typedef enum
{ {
SBC_TIMER_WU_NOEVENT = 0x00U, SBC_TIMER_WU_NOEVENT = 0x00U,
SBC_TIMER_WU_EVENT SBC_TIMER_WU_EVENT
}; }SBC_TIMER_WU_ENUM;
typedef enum typedef enum
{ {
SBC_WK_WU_NOEVENT = 0x00U, SBC_WK_WU_NOEVENT = 0x00U,
SBC_WK_WU_EVENT SBC_WK_WU_EVENT
}; }SBC_WK_WU_ENUM;
/* -------------------------------- WK_STAT_1 ------------------------------------ */ /* -------------------------------- WK_STAT_1 ------------------------------------ */
@ -3117,7 +3117,7 @@ typedef enum
{ {
SBC_GPIO_WK_WU_NOEVENT = 0x00U, SBC_GPIO_WK_WU_NOEVENT = 0x00U,
SBC_GPIO_WK_WU_EVENT SBC_GPIO_WK_WU_EVENT
}; }SBC_GPIO_WK_WU_ENUM;
/* -------------------------------- WK_LVL_STAT ---------------------------------- */ /* -------------------------------- WK_LVL_STAT ---------------------------------- */
@ -3126,25 +3126,25 @@ typedef enum
{ {
SBC_DEV_LVL_NORMAL = 0x00U, SBC_DEV_LVL_NORMAL = 0x00U,
SBC_DEV_LVL_DEVELOPMENT_MODE SBC_DEV_LVL_DEVELOPMENT_MODE
}; }SBC_DEV_LVL_ENUM;
typedef enum typedef enum
{ {
SBC_CFG0_STATE_CONFIG_2_4 = 0x00U, SBC_CFG0_STATE_CONFIG_2_4 = 0x00U,
SBC_CFG0_STATE_CONFIG_1_3 SBC_CFG0_STATE_CONFIG_1_3
}; }SBC_CFG0_STATE_CONFIG_ENUM;
typedef enum typedef enum
{ {
SBC_GPIO_LVL_LOW = 0x00U, SBC_GPIO_LVL_LOW = 0x00U,
SBC_GPIO_LVL_HIGH SBC_GPIO_LVL_HIGH
}; }SBC_GPIO_LVL_ENUM;
typedef enum typedef enum
{ {
SBC_WK_LVL_LOW = 0x00U, SBC_WK_LVL_LOW = 0x00U,
SBC_WK_LVL_HIGH SBC_WK_LVL_HIGH
}; }SBC_WK_LVL_ENUM;
/* -------------------------------- GPIO_OC_STAT --------------------------------- */ /* -------------------------------- GPIO_OC_STAT --------------------------------- */
@ -3153,7 +3153,7 @@ typedef enum
{ {
SBC_GPIO_OC_NOEVENT = 0x00U, SBC_GPIO_OC_NOEVENT = 0x00U,
SBC_GPIO_OC_EVENT SBC_GPIO_OC_EVENT
}; }SBC_GPIO_OC_ENUM;
/* -------------------------------- GPIO_OL_STAT --------------------------------- */ /* -------------------------------- GPIO_OL_STAT --------------------------------- */
@ -3162,7 +3162,7 @@ typedef enum
{ {
SBC_GPIO_OL_NOEVENT = 0x00U, SBC_GPIO_OL_NOEVENT = 0x00U,
SBC_GPIO_OL_EVENT SBC_GPIO_OL_EVENT
}; }SBC_GPIO_OL_ENUM;
@ -3181,31 +3181,31 @@ typedef enum
{ {
SBC_SYNC_NOT_SYNCHRONOUS = 0x00U, SBC_SYNC_NOT_SYNCHRONOUS = 0x00U,
SBC_SYNC_VALID_FRAME_RECEIVED SBC_SYNC_VALID_FRAME_RECEIVED
}; }SBC_SYNC_ENUM;
typedef enum typedef enum
{ {
SBC_CANSIL_NOT_EXCEEDED = 0x00U, SBC_CANSIL_NOT_EXCEEDED = 0x00U,
SBC_CANSIL_EXCEEDED SBC_CANSIL_EXCEEDED
}; }SBC_CANSIL_ENUM;
typedef enum typedef enum
{ {
SBC_SWK_SET_SWK_NOT_ACTIVE = 0x00U, SBC_SWK_SET_SWK_NOT_ACTIVE = 0x00U,
SBC_SWK_SET_SWK_ACTIVE SBC_SWK_SET_SWK_ACTIVE
}; }SBC_SWK_SET_SWK_ENUM;
typedef enum typedef enum
{ {
SBC_WUP_NO_WUP = 0x00U, SBC_WUP_NO_WUP = 0x00U,
SBC_WUP_DETECTED SBC_WUP_DETECTED
}; }SBC_WUP;
typedef enum typedef enum
{ {
SBC_WUF_NO_WUF = 0x00U, SBC_WUF_NO_WUF = 0x00U,
SBC_WUF_DETECTED SBC_WUF_DETECTED
}; }SBC_WUF_ENUM;
/* -------------------------------- SWK_ECNT_STAT ------------------------------ */ /* -------------------------------- SWK_ECNT_STAT ------------------------------ */
@ -3215,7 +3215,7 @@ typedef enum
SBC_ECNT_NOEVENT = 0x00U, SBC_ECNT_NOEVENT = 0x00U,
SBC_ECNT_31_FRAME_ERRORS = 0x1FU, SBC_ECNT_31_FRAME_ERRORS = 0x1FU,
SBC_ECNT_ERROR_OVERFLOW = 0x20U SBC_ECNT_ERROR_OVERFLOW = 0x20U
}; }SBC_ECNT_ENUM;
/* ================================================================================ */ /* ================================================================================ */
@ -3234,7 +3234,7 @@ typedef enum
SBC_FAM_MULTICAN, SBC_FAM_MULTICAN,
SBC_FAM_LITE, SBC_FAM_LITE,
SBC_FAM_MIDRANGEPLUS = 0x07U SBC_FAM_MIDRANGEPLUS = 0x07U
}; }SBC_FAM_ENUM;
typedef enum typedef enum
{ {
@ -3242,7 +3242,7 @@ typedef enum
SBC_PROD_TLE9461V33, SBC_PROD_TLE9461V33,
SBC_PROD_TLE9471 = 0x0EU, SBC_PROD_TLE9471 = 0x0EU,
SBC_PROD_TLE9471V33 SBC_PROD_TLE9471V33
}; }SBC_PROD_ENUM;
#endif /* TLE94x1_DEFINES_H */ #endif /* TLE94x1_DEFINES_H */

147
cva_asw_m0146/src/appTask.c Normal file
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@ -0,0 +1,147 @@
#include "appTask.h"
#include "uds.h"
#include "uds_user.h"
#include "stdint.h"
#include "drivers/flexcan/flexcan_drv.h"
#include "hwctrl.h"
#include "TLE94x1.h"
#include "string.h"
#include "SEGGER_RTT.h"
#include "MotorCtrl.h"
/*******************************************************************************
* the defines
******************************************************************************/
#define UDS_RECV_BUF (2056)
#define UDS_SEND_BUF (512)
/* Indication value with boot loader request from asw */
#define ASW_BOOT_REQ_ACTIVE (0x55AAAA55ul)
uint8_t txMsgBuf[8] = {0};
uint8_t udsSendBuf[UDS_SEND_BUF] = {0};
uint8_t udsRecvBuf[UDS_RECV_BUF] = {0};
UdsType udsObj;
int64_t Get_Cur_Time_Stamp(void);
Uds_ParamsType udsParam = {
.isotpParams.framePadding = true,
.isotpParams.blockSize = 0,
.isotpParams.recvPhysId = UDS_PHYS_RECV_MSG_ID,
.isotpParams.recvFuncId = UDS_FUNC_RECV_MSG_ID,
.isotpParams.sendid = UDS_PHYS_RESP_MSG_ID,
.isotpParams.sendBuf = udsSendBuf,
.isotpParams.sendBufSize = UDS_SEND_BUF,
.isotpParams.recvBuf = udsRecvBuf,
.isotpParams.recvBufSize = UDS_RECV_BUF,
.isotpParams.debug = NULL,
.isotpParams.sendCanMsg = FlexCanBoot_TxMessage,
.isotpParams.getTimeMs = Get_Cur_Time_Stamp,
.p2Server_ms = 50,
.p2xServer_10ms = 500,
.s3Server_ms = 5000,
};
int64_t timer_1ms = 0;
volatile uint32_t gSystick1msEvent = 0, gSystick1msCnt = 0, gTestRunCnt = 0, gTestIoEn = 0, gSysTick1sCnt = 0;
#pragma location = ".bss.no_init"
static uint32_t sAswBoot_Req;
//
int64_t Get_Cur_Time_Stamp(void)
{
return timer_1ms;
}
void Asw_SetBootloaderRequest(void)
{
sAswBoot_Req = ASW_BOOT_REQ_ACTIVE;
}
void SysTick_Handler(void)
{
gSystick1msEvent++;
timer_1ms++;
Uds_Tick(&udsObj);
}
void appTask(McuType *obj)
{
FlexCan_FrameStructureType rxMsg;
if(gSystick1msEvent > 0u)
{
if(udsObj.session == UDS_SESSION_PROGRAMMING)
{
Asw_SetBootloaderRequest();
ResetDrv_SoftwareResetModule(&obj->resetDrv, RESETDRV_SWRESET_SYS);
}
gSystick1msEvent--;
gSystick1msCnt++;
gSysTick1sCnt++;
if (gSystick1msCnt % 10 == 0)
{
MotorCtrl_Maintask(obj);
}
if (gSystick1msCnt % 50 == 0)
{
SBC_WD_Trigger();
}
if(gSystick1msCnt % 200 == 0)
{
uint8_t txMsgBuf[8]={0};
txMsgBuf[3] = gSysTick1sCnt & 0xFF;
FlexCanBoot_TxMessage(APP_TX_TEST1_MSG_ID, txMsgBuf, 8);
}
if (gSystick1msCnt >= 10000)
{
gSystick1msCnt = 0;
SEGGER_RTT_printf(0,"app running\n");
}
/* Handler user routine */
if(FlexCanBoot_ReadoutMsg(&rxMsg) == true)
{
if((rxMsg.id == UDS_PHYS_RECV_MSG_ID) || (rxMsg.id == UDS_FUNC_RECV_MSG_ID))
{
IsoTp_HandleIncomingCanMsg(&udsObj.isotp, rxMsg.id, rxMsg.data, rxMsg.len);
}
else
{
}
}
Uds_Run(&udsObj);
}
}
void appTaskInit(McuType *obj)
{
/* UDS init */
Uds_UserInit(&udsObj, &udsParam);
MotorCtrl_Init(obj);
}

10
cva_asw_m0146/src/appTask.h Normal file
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@ -0,0 +1,10 @@
#ifndef __APPTASK_H__
#define __APPTASK_H__
#include "Mcu.h"
void appTask(McuType *obj);
void appTaskInit(McuType *obj);
#endif

609
cva_asw_m0146/src/hwctrl.c Normal file
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@ -0,0 +1,609 @@
#include "hwctrl.h"
#include "clock_drv.h"
#include "SEGGER_RTT.h"
#include "appTask.h"
#include "TLE94x1.h"
#include "string.h"
#include "irq_drv.h"
/*******************************************************************************
* the defines
******************************************************************************/
/*******************************************************************************
* the typedefs
******************************************************************************/
typedef enum
{
UDS_MSG_IDX_STD_RX_PHYS,
UDS_MSG_IDX_STD_RX_FUNC,
UDS_MSG_IDX_STD_RX_TEST1,
UDS_MSG_IDX_STD_RX_TEST2,
UDS_MSG_IDX_STD_TX_TEST1,
UDS_MSG_IDX_STD_TX,
UDS_MSG_IDX_STD_TEST1,
UDS_MSG_IDX_STD_TEST2,
UDS_MSG_IDX_NUM
} Uds_MsgIdIdxType;
typedef struct
{
FlexCan_FrameStructureType rxMsg[CAN_BUFFER_FIFO_SIZE];
FlexCan_FrameStructureType txMsg[CAN_BUFFER_FIFO_SIZE];
uint8_t wrIdx;
uint8_t rdIdx;
} FlexCan_DataInfoType;
/*******************************************************************************
* the globals
******************************************************************************/
FlexCanDrv_ControllerCfgType flexCanCfg;
FlexCan_DataInfoType flexCan_DataInfo;
FlexCanDrvType* flexCanDrv_DemoObj;
/*******************************************************************************
* the const
******************************************************************************/
const FlexCanDrv_MsgCfgType msgCfgObj[UDS_MSG_IDX_NUM] = {
{UDS_MSG_IDX_STD_RX_PHYS, 1, UDS_PHYS_RECV_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_PHYS */
{UDS_MSG_IDX_STD_RX_FUNC, 1, UDS_FUNC_RECV_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_RX_TEST1, 1, APP_RX_TEST1_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_RX_TEST2, 1, APP_RX_TEST2_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_TX, 1, UDS_PHYS_RESP_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
{UDS_MSG_IDX_STD_TEST1, 1, APP_TX_TEST1_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
{UDS_MSG_IDX_STD_TEST2, 1, APP_TX_TEST2_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
};
/*******************************************************************************
* the function prototypes
******************************************************************************/
static void FlexCanBoot_Init(McuType *obj);
static void hw_IO_Init(McuType *obj);
static void hw_clock_init(McuType *obj)
{
/* Setup the clock */
ClockDrv_ModuleClkConfigType clockConfig;
uint32_t tTcr = 0;
WdgDrv_Disable(&(obj->wdgDrv));
SEGGER_RTT_printf(0,"-----clock_INIT-----\n");
/* Enable the clock for all ports */
clockConfig.gating = true;
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PORTA, &clockConfig);
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PORTB, &clockConfig);
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PORTC, &clockConfig);
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PORTD, &clockConfig);
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PORTE, &clockConfig);
/* Setup the Pll div2 clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_PLL;
clockConfig.div = 1;
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
/* Setup the FIRC2 div2 clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_FIRC;
clockConfig.div = 1;
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_FIRC_DIV2, &clockConfig);
/* Setup the SPI clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_PLL_DIV2;
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_SPI2, &clockConfig);
tTcr = SpiReg_GetTcr((const SpiRegType *)&obj->spiDrv2.reg);
SpiDrv_SetPrescaler(&tTcr,0x03);
}
void hw_init(McuType *obj)
{
uint32_t gCpuClockFrequency = 0;
hw_clock_init(obj);
SEGGER_RTT_printf(0,"-----SPI_INIT-----\n");
SBC_SPI_INIT();
/* CAN init */
memset(&flexCan_DataInfo, 0, sizeof(flexCan_DataInfo));
memset(&flexCanCfg, 0, sizeof(flexCanCfg));
SEGGER_RTT_printf(0,"-----FlexCanDrv_INIT-----\n");
/* get CAN controller default configuration */
FlexCanDrv_GetDefaultCfg(&flexCanCfg);
flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
flexCanCfg.msgCfg = msgCfgObj;
FlexCanBoot_Init(obj);
hw_IO_Init(obj);
/* Set system tick clock, 1ms event */
ClockDrv_GetFreq(&obj->clockDrv, CLOCKDRV_CORE, &gCpuClockFrequency);
SysTick_Config(gCpuClockFrequency / 1000u);
IrqDrv_EnableIrq(SysTick_IRQn);
SBC_Init();
}
#define PINSDRV_DIR_OUTPUT 1
#define PINSDRV_DIR_INPUT 0
static void hw_IO_Init(McuType *obj)
{
//1
PinsDrv_SetMuxModeSel(&obj->ptd, 1, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 1, 1);
PortReg_SetPcrSr(obj->ptd.port, 1, 1);
PinsDrv_SetPinDirection(&obj->ptd, 1, PINSDRV_DIR_OUTPUT);
//2
PinsDrv_SetMuxModeSel(&obj->ptd, 0, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 0, 1);
PortReg_SetPcrSr(obj->ptd.port, 0, 1);
PinsDrv_SetPinDirection(&obj->ptd, 0, PINSDRV_DIR_OUTPUT);
//3
PinsDrv_SetMuxModeSel(&obj->pte, 11, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 11, 1);
PortReg_SetPcrSr(obj->pte.port, 11, 1);
PinsDrv_SetPinDirection(&obj->pte, 11, PINSDRV_DIR_OUTPUT);
//4
PinsDrv_SetMuxModeSel(&obj->pte, 10, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 10, 1);
PortReg_SetPcrSr(obj->pte.port, 10, 1);
PinsDrv_SetPinDirection(&obj->pte, 10, PINSDRV_DIR_OUTPUT);
//5
PinsDrv_SetMuxModeSel(&obj->pte, 5, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 5, 1);
PortReg_SetPcrSr(obj->pte.port, 5, 1);
PinsDrv_SetPinDirection(&obj->pte, 5, PINSDRV_DIR_OUTPUT);
//6
PinsDrv_SetMuxModeSel(&obj->pte, 4, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 4, 1);
PortReg_SetPcrSr(obj->pte.port, 4, 1);
PinsDrv_SetPinDirection(&obj->pte, 4, PINSDRV_DIR_OUTPUT);
//7-12电源
//13
PinsDrv_SetMuxModeSel(&obj->pte, 3, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 3, 1);
PortReg_SetPcrSr(obj->pte.port, 3, 1);
PinsDrv_SetPinDirection(&obj->pte, 3, PINSDRV_DIR_OUTPUT);
//14
PinsDrv_SetMuxModeSel(&obj->ptd, 16, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 16, 1);
PortReg_SetPcrSr(obj->ptd.port, 16, 1);
PinsDrv_SetPinDirection(&obj->ptd, 16, PINSDRV_DIR_OUTPUT);
//15
PinsDrv_SetMuxModeSel(&obj->ptd, 15, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 15, 1);
PortReg_SetPcrSr(obj->ptd.port, 15, 1);
PinsDrv_SetPinDirection(&obj->ptd, 15, PINSDRV_DIR_OUTPUT);
//16
PinsDrv_SetMuxModeSel(&obj->pte, 9, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 9, 1);
PortReg_SetPcrSr(obj->pte.port, 9, 1);
PinsDrv_SetPinDirection(&obj->pte, 9, PINSDRV_DIR_OUTPUT);
//17
PinsDrv_SetMuxModeSel(&obj->pte, 8, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 8, 1);
PortReg_SetPcrSr(obj->pte.port, 8, 1);
PinsDrv_SetPinDirection(&obj->pte, 8, PINSDRV_DIR_OUTPUT);
//18
PinsDrv_SetMuxModeSel(&obj->ptb, 5, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptb.port, 5, 1);
PortReg_SetPcrSr(obj->ptb.port, 5, 1);
PinsDrv_SetPinDirection(&obj->ptb, 5, PINSDRV_DIR_OUTPUT);
//19
PinsDrv_SetMuxModeSel(&obj->ptb, 4, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptb.port, 4, 1);
PortReg_SetPcrSr(obj->ptb.port, 4, 1);
PinsDrv_SetPinDirection(&obj->ptb, 4, PINSDRV_DIR_OUTPUT);
//20-22预留
//23
PinsDrv_SetMuxModeSel(&obj->ptd, 6, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 6, 1);
PortReg_SetPcrSr(obj->ptd.port, 6, 1);
PinsDrv_SetPinDirection(&obj->ptd, 6, PINSDRV_DIR_OUTPUT);
//24
PinsDrv_SetMuxModeSel(&obj->ptd, 5, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 5, 1);
PortReg_SetPcrSr(obj->ptd.port, 5, 1);
PinsDrv_SetPinDirection(&obj->ptd, 5, PINSDRV_DIR_OUTPUT);
//25-26 SPI
//27
PinsDrv_SetMuxModeSel(&obj->ptc, 17, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->ptc.port, 17, 1);
PortReg_SetPcrSr(obj->ptc.port, 17, 1);
//28
PinsDrv_SetMuxModeSel(&obj->ptc, 16, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptc.port, 16, 1);
PortReg_SetPcrSr(obj->ptc.port, 16, 1);
PinsDrv_SetPinDirection(&obj->ptc, 16,PINSDRV_DIR_OUTPUT);
//29 30 SPI
//31
PinsDrv_SetMuxModeSel(&obj->ptb, 3, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->ptb.port, 3, 1);
PortReg_SetPcrSr(obj->ptb.port, 3, 1);
//32
PinsDrv_SetMuxModeSel(&obj->ptb, 2, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptb.port, 2, 1);
PortReg_SetPcrSr(obj->ptb.port, 2, 1);
//33 34 CAN
//35
PinsDrv_SetMuxModeSel(&obj->ptc, 9, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptc.port, 9, 1);
PortReg_SetPcrSr(obj->ptc.port, 9, 1);
PinsDrv_SetPinDirection(&obj->ptc, 9,PINSDRV_DIR_OUTPUT);
//36
PinsDrv_SetMuxModeSel(&obj->ptc, 8, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptc.port, 8, 1);
PortReg_SetPcrSr(obj->ptc.port, 8, 1);
//37
PinsDrv_SetMuxModeSel(&obj->pta, 7, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->pta.port, 7, 1);
PortReg_SetPcrSr(obj->pta.port, 7, 1);
//38
PinsDrv_SetMuxModeSel(&obj->pta, 6, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 6, 1);
PortReg_SetPcrSr(obj->pta.port, 6, 1);
//39
PinsDrv_SetMuxModeSel(&obj->pte, 7, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 7, 1);
PortReg_SetPcrSr(obj->pte.port, 7, 1);
//40 41 VDD
//42 NC
//43
PinsDrv_SetMuxModeSel(&obj->ptb, 12, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->ptb.port, 12, 1);
PortReg_SetPcrSr(obj->ptb.port, 12, 1);
//44
PinsDrv_SetMuxModeSel(&obj->ptd, 4, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 4, 1);
PortReg_SetPcrSr(obj->ptd.port, 4, 1);
//45
PinsDrv_SetMuxModeSel(&obj->ptd, 3, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptd.port, 3, 1);
PortReg_SetPcrSr(obj->ptd.port, 3, 1);
//46
PinsDrv_SetMuxModeSel(&obj->ptd, 2, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->ptd.port, 2, 1);
PortReg_SetPcrSr(obj->ptd.port, 2, 1);
//47
PinsDrv_SetMuxModeSel(&obj->pta, 3, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 3, 1);
PortReg_SetPcrSr(obj->pta.port, 3, 1);
PinsDrv_SetPinDirection(&obj->pta, 3, PINSDRV_DIR_OUTPUT);
//48
PinsDrv_SetMuxModeSel(&obj->pta, 2, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 2, 1);
PortReg_SetPcrSr(obj->pta.port, 2, 1);
PinsDrv_SetPinDirection(&obj->pta, 2, PINSDRV_DIR_OUTPUT);
//49
PinsDrv_SetMuxModeSel(&obj->pta, 1, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->pta.port, 1, 1);
PortReg_SetPcrSr(obj->pta.port, 1, 1);
//50
PinsDrv_SetMuxModeSel(&obj->pta, 0, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->pta.port, 0, 1);
PortReg_SetPcrSr(obj->pta.port, 0, 1);
//51
PinsDrv_SetMuxModeSel(&obj->ptc, 7, PINSDRV_PIN_DISABLED);
PortReg_SetPcrDrvStr(obj->ptc.port, 7, 1);
PortReg_SetPcrSr(obj->ptc.port, 7, 1);
//52
PinsDrv_SetMuxModeSel(&obj->ptc, 6, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->ptc.port, 6, 1);
PortReg_SetPcrSr(obj->ptc.port, 6, 1);
PinsDrv_SetPinDirection(&obj->ptc, 6, PINSDRV_DIR_OUTPUT);
//53
PinsDrv_SetMuxModeSel(&obj->pte, 6, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 6, 1);
PortReg_SetPcrSr(obj->pte.port, 6, 1);
PinsDrv_SetPinDirection(&obj->pte, 6, PINSDRV_DIR_OUTPUT);
//54
PinsDrv_SetMuxModeSel(&obj->pte, 2, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 2, 1);
PortReg_SetPcrSr(obj->pte.port, 2, 1);
PinsDrv_SetPinDirection(&obj->pte, 2, PINSDRV_DIR_OUTPUT);
//55
PinsDrv_SetMuxModeSel(&obj->pta, 13, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 13, 1);
PortReg_SetPcrSr(obj->pta.port, 13, 1);
PinsDrv_SetPinDirection(&obj->pta, 12, PINSDRV_DIR_OUTPUT);
//56
PinsDrv_SetMuxModeSel(&obj->pta, 12, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 12, 1);
PortReg_SetPcrSr(obj->pta.port, 12, 1);
PinsDrv_SetPinDirection(&obj->pta, 11, PINSDRV_DIR_OUTPUT);
//57
PinsDrv_SetMuxModeSel(&obj->pta, 11, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 11, 1);
PortReg_SetPcrSr(obj->pta.port, 11, 1);
//58
PinsDrv_SetMuxModeSel(&obj->pta, 10, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pta.port, 10, 1);
PortReg_SetPcrSr(obj->pta.port, 10, 1);
PinsDrv_SetPinDirection(&obj->pta, 10, PINSDRV_DIR_OUTPUT);
//59
PinsDrv_SetMuxModeSel(&obj->pte, 1, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 1, 1);
PortReg_SetPcrSr(obj->pte.port, 1, 1);
PinsDrv_SetPinDirection(&obj->pte, 1, PINSDRV_DIR_OUTPUT);
//60
PinsDrv_SetMuxModeSel(&obj->pte, 0, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 0, 1);
PortReg_SetPcrSr(obj->pte.port, 0, 1);
PinsDrv_SetPinDirection(&obj->pte, 0, PINSDRV_DIR_OUTPUT);
//61
PinsDrv_SetMuxModeSel(&obj->pte, 5, PINSDRV_MUX_AS_GPIO);
PortReg_SetPcrDrvStr(obj->pte.port, 5, 1);
PortReg_SetPcrSr(obj->pte.port, 5, 1);
//62-64 SWD
}
/*************************************motor driver *****************************************/
void hw_MotorCtrl(McuType *obj,Motor_ID_Type motorid,Motor_ACT_Type dir)
{
switch(motorid)
{
case Motor1:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->ptd, 0);
PinsDrv_ClearPin(&obj->ptd, 1);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->ptd, 0);
PinsDrv_ClearPin(&obj->ptd, 1);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->ptd, 1);
PinsDrv_ClearPin(&obj->ptd, 0);
break;
}
break;
case Motor2:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->pte, 10);
PinsDrv_ClearPin(&obj->pte, 11);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->pte, 10);
PinsDrv_ClearPin(&obj->pte, 11);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->pte, 11);
PinsDrv_ClearPin(&obj->pte, 10);
break;
}
break;
case Motor3:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->pte, 4);
PinsDrv_ClearPin(&obj->pte, 5);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->pte, 4);
PinsDrv_ClearPin(&obj->pte, 5);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->pte, 5);
PinsDrv_ClearPin(&obj->pte, 4);
break;
}
break;
case Motor4:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->pte, 3);
PinsDrv_ClearPin(&obj->ptd, 16);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->pte, 3);
PinsDrv_ClearPin(&obj->ptd, 16);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->ptd, 16);
PinsDrv_ClearPin(&obj->pte, 3);
break;
}
break;
case Motor5:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->pte, 9);
PinsDrv_ClearPin(&obj->ptd, 15);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->pte, 9);
PinsDrv_ClearPin(&obj->ptd, 15);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->ptd, 15);
PinsDrv_ClearPin(&obj->pte, 9);
break;
}
break;
case Motor6:
switch(dir)
{
case Motor_ACT_NOACT:
PinsDrv_ClearPin(&obj->ptd, 0);
PinsDrv_ClearPin(&obj->ptd, 1);
break;
case Motor_ACT_CW:
PinsDrv_SetPin(&obj->ptd, 0);
PinsDrv_ClearPin(&obj->ptd, 1);
break;
case Motor_ACT_CCW:
PinsDrv_SetPin(&obj->ptd, 1);
PinsDrv_ClearPin(&obj->ptd, 0);
break;
}
break;
}
}
/************************************* CAN *****************************************/
int8_t FlexCanBoot_TxMessage(uint32_t msgId, const uint8_t* pData, uint8_t size)
{
FlexCanDrv_MsgObjType txMsgObj;
uint8_t msgIdx = 0, i = 0;
for(i = 0; i < flexCanCfg.msgNum; i++)
{
if(msgId == flexCanCfg.msgCfg[i].msgId)
{
msgIdx = i;
break;
}
}
txMsgObj.msgBufId = flexCanCfg.msgCfg[msgIdx].msgBufId;
txMsgObj.dlc = size;
txMsgObj.msgId = flexCanCfg.msgCfg[msgIdx].msgId;
memcpy(&txMsgObj.data[0], pData, size);
FlexCanDrv_SetTxMsg(flexCanDrv_DemoObj, &txMsgObj);
/* transmit standard CAN Tx message */
FlexCanDrv_TransmitMsg(flexCanDrv_DemoObj, &txMsgObj);
return 0;
}
static void FlexCanBoot_Init(McuType *obj)
{
uint32_t busClockFreq = 0;
flexCanDrv_DemoObj = &obj->flexCanDrv0;
/* set PTE4 as MUX 5 - CAN0.RX */
PinsDrv_SetMuxModeSel(&obj->ptb, 0, PINSDRV_MUX_ALT5);
/* set PTE5 as MUX 5 - CAN0.TX */
PinsDrv_SetMuxModeSel(&obj->ptb, 1, PINSDRV_MUX_ALT5);
flexCanCfg.clkSrc = FLEXCANDRV_CLKSRC_CHICLK;
flexCanCfg.fdEnable = false;
flexCanCfg.fdISOEnable = false;
flexCanCfg.enhancefifoEnable = true;
flexCanCfg.msgBufDataLenSel = FLEXCANDRV_MB_SIZE_BYTE_8;
flexCanCfg.individualMaskEnable = true;
if(flexCanCfg.clkSrc == FLEXCANDRV_CLKSRC_CHICLK)
{
ClockDrv_GetFreq(&obj->clockDrv, CLOCKDRV_APB, &busClockFreq);
}
else
{
ClockDrv_GetFreq(&obj->clockDrv, CLOCKDRV_SOSC_DIV2, &busClockFreq);
}
if(flexCanCfg.fdEnable == true)
{
FlexCanDrv_BitTimingCalc(&flexCanCfg.fdBitTiming,
busClockFreq, /* module clock source: 16M */
2000000, /* baudrate: 2M */
7500, /* sample point: 75% */
2000, /* SJW: 20% */
1); /* FD bit timing */
}
FlexCanDrv_BitTimingCalc(&flexCanCfg.bitTiming,
busClockFreq, /* module clock source: 16M */
500000, /* baudrate: 500K */
7500, /* sample point: 75% */
2500, /* SJW: 20% */
0); /* classic CAN bit timing */
/* initialize CAN module */
FlexCanDrv_Configure(flexCanDrv_DemoObj, &flexCanCfg);
/* enable enhance rx fifo interrupt */
FlexCanDrv_SetEnhanceRxFFIsr(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE, true);
IrqDrv_EnableIrq(CAN0_ERxFIFO_IRQn);
}
bool FlexCanBoot_ReadoutMsg(FlexCan_FrameStructureType* pRxMsgObj)
{
bool ret = false;
if(flexCan_DataInfo.wrIdx != flexCan_DataInfo.rdIdx)
{
memcpy(pRxMsgObj, &flexCan_DataInfo.rxMsg[flexCan_DataInfo.rdIdx], sizeof(FlexCan_FrameStructureType));
flexCan_DataInfo.rdIdx++;
if(flexCan_DataInfo.rdIdx >= CAN_BUFFER_FIFO_SIZE)
{
flexCan_DataInfo.rdIdx = 0;
}
ret = true;
}
return ret;
}
uint8_t flexCanBoot_EnhanceRxFFCnt = 0;
void CAN0_ERxFIFO_Handler(void)
{
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE) == true)
{
if(FlexCanDrv_GetEnhanceRxFFIsFull(flexCanDrv_DemoObj) == false)
{
}
if(FlexCanDrv_GetEnhanceRxFFIsEmpty(flexCanDrv_DemoObj) == false)
{
FlexCanDrv_MsgObjType rxMsgObj;
flexCanBoot_EnhanceRxFFCnt = FlexCanDrv_GetEnhanceRxFFMsgNums(flexCanDrv_DemoObj);
if(flexCanBoot_EnhanceRxFFCnt > 0)
{
FlexCanDrv_GetEnhanceRxFifoMsg(flexCanDrv_DemoObj, &rxMsgObj);
memcpy(flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].data, rxMsgObj.data, rxMsgObj.dlc);
flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].id = rxMsgObj.msgId;
flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].len = rxMsgObj.dlc;
flexCan_DataInfo.wrIdx++;
if(flexCan_DataInfo.wrIdx >= CAN_BUFFER_FIFO_SIZE)
{
flexCan_DataInfo.wrIdx = 0;
}
}
}
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_WMMIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_WMMIE);
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_OVFIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_OVFIE);
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_UFWIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_UFWIE);
}
}

64
cva_asw_m0146/src/hwctrl.h Normal file
View File

@ -0,0 +1,64 @@
#ifndef __HWCTRL_H__
#define __HWCTRL_H__
#include "mcu.h"
/*******************************************************************************
* the defines
******************************************************************************/
#define UDS_PHYS_RECV_MSG_ID (0x732)
#define UDS_FUNC_RECV_MSG_ID (0x7DF)
#define UDS_PHYS_RESP_MSG_ID (0x7B2)
#define APP_TX_TEST1_MSG_ID (0x111)
#define APP_TX_TEST2_MSG_ID (0x222)
#define APP_RX_TEST1_MSG_ID (0x444)
#define APP_RX_TEST2_MSG_ID (0x555)
#define CAN_DATA_BUFFER_SIZE (64u)
#define CAN_BUFFER_FIFO_SIZE (32u)
/*******************************************************************************
* the typedefs
******************************************************************************/
typedef struct
{
uint32_t id;
uint8_t data[CAN_DATA_BUFFER_SIZE];
uint8_t len;
uint16_t timeStamp;
uint32_t hrTimeStamp;
} FlexCan_FrameStructureType;
typedef enum
{
Motor_ACT_NOACT,//停止
Motor_ACT_CW,//正转
Motor_ACT_CCW,//反转
} Motor_ACT_Type;
typedef enum
{
Motor1,//
Motor2,//
Motor3,//
Motor4,//
Motor5,//
Motor6,//
} Motor_ID_Type;
/*******************************************************************************
* the function prototypes
******************************************************************************/
void hw_init(McuType *obj);
int8_t FlexCanBoot_TxMessage(uint32_t msgId, const uint8_t* pData, uint8_t size);
bool FlexCanBoot_ReadoutMsg(FlexCan_FrameStructureType* pRxMsgObj);
void hw_MotorCtrl(McuType *obj,Motor_ID_Type motorid,Motor_ACT_Type dir);
#endif

366
cva_asw_m0146/src/main.c
View File

@ -22,36 +22,18 @@
******************************************************************************/ ******************************************************************************/
#include <stdint.h> #include <stdint.h>
#include <string.h>
#include "mcu.h" #include "mcu.h"
#include "uds_user.h"
#include "TLE94x1.h"
#include "SEGGER_RTT.h" #include "SEGGER_RTT.h"
#include "appTask.h"
#include "hwctrl.h"
/******************************************************************************* /*******************************************************************************
* the defines * the defines
******************************************************************************/ ******************************************************************************/
#define UDS_PHYS_RECV_MSG_ID (0x732)
#define UDS_FUNC_RECV_MSG_ID (0x7DF)
#define UDS_PHYS_RESP_MSG_ID (0x7B2)
#define APP_TX_TEST1_MSG_ID (0x111)
#define APP_TX_TEST2_MSG_ID (0x222)
#define APP_RX_TEST1_MSG_ID (0x444)
#define APP_RX_TEST2_MSG_ID (0x555)
#define UDS_RECV_BUF (2056)
#define UDS_SEND_BUF (512)
#define CAN_BUFF_MAX_NUM (32) #define CAN_BUFF_MAX_NUM (32)
#define CAN_DATA_BUFFER_SIZE (64u)
#define CAN_BUFFER_FIFO_SIZE (32u)
int64_t Get_Cur_Time_Stamp(void);
static int8_t FlexCanBoot_TxMessage(uint32_t msgId, const uint8_t* pData, uint8_t size);
/* Indication value with boot loader request from asw */
#define ASW_BOOT_REQ_ACTIVE (0x55AAAA55ul)
/* Asw code head id to show asw is not empty */ /* Asw code head id to show asw is not empty */
#define ASW_HEAD_MASK (0xAABBCCDDul) #define ASW_HEAD_MASK (0xAABBCCDDul)
@ -60,36 +42,6 @@ static int8_t FlexCanBoot_TxMessage(uint32_t msgId, const uint8_t* pData, uint8_
/******************************************************************************* /*******************************************************************************
* the typedefs * the typedefs
******************************************************************************/ ******************************************************************************/
typedef enum
{
UDS_MSG_IDX_STD_RX_PHYS,
UDS_MSG_IDX_STD_RX_FUNC,
UDS_MSG_IDX_STD_RX_TEST1,
UDS_MSG_IDX_STD_RX_TEST2,
UDS_MSG_IDX_STD_TX_TEST1,
UDS_MSG_IDX_STD_TX,
UDS_MSG_IDX_STD_TEST1,
UDS_MSG_IDX_STD_TEST2,
UDS_MSG_IDX_NUM
} Uds_MsgIdIdxType;
typedef struct
{
uint32_t id;
uint8_t data[CAN_DATA_BUFFER_SIZE];
uint8_t len;
uint16_t timeStamp;
uint32_t hrTimeStamp;
} FlexCan_FrameStructureType;
typedef struct
{
FlexCan_FrameStructureType rxMsg[CAN_BUFFER_FIFO_SIZE];
FlexCan_FrameStructureType txMsg[CAN_BUFFER_FIFO_SIZE];
uint8_t wrIdx;
uint8_t rdIdx;
} FlexCan_DataInfoType;
typedef struct typedef struct
{ {
@ -102,49 +54,11 @@ typedef struct
* the globals * the globals
******************************************************************************/ ******************************************************************************/
McuType mcu; McuType mcu;
volatile uint32_t gSystick1msEvent = 0, gSystick1msCnt = 0, gTestRunCnt = 0, gTestIoEn = 0, gSysTick1sCnt = 0;
uint32_t gCpuClockFrequency = 0;
int64_t timer_1ms = 0;
uint8_t udsSendBuf[UDS_SEND_BUF] = {0};
uint8_t udsRecvBuf[UDS_RECV_BUF] = {0};
UdsType udsObj;
FlexCan_DataInfoType flexCan_DataInfo;
FlexCanDrv_ControllerCfgType flexCanCfg;
FlexCanDrvType* flexCanDrv_DemoObj;
uint8_t flexCanBoot_EnhanceRxFFCnt = 0;
uint8_t txMsgBuf[8] = {0};
uint8_t aswVersion = 1;
Uds_ParamsType udsParam = {
.isotpParams.framePadding = true,
.isotpParams.blockSize = 0,
.isotpParams.recvPhysId = UDS_PHYS_RECV_MSG_ID,
.isotpParams.recvFuncId = UDS_FUNC_RECV_MSG_ID,
.isotpParams.sendid = UDS_PHYS_RESP_MSG_ID,
.isotpParams.sendBuf = udsSendBuf,
.isotpParams.sendBufSize = UDS_SEND_BUF,
.isotpParams.recvBuf = udsRecvBuf,
.isotpParams.recvBufSize = UDS_RECV_BUF,
.isotpParams.debug = NULL,
.isotpParams.sendCanMsg = FlexCanBoot_TxMessage,
.isotpParams.getTimeMs = Get_Cur_Time_Stamp,
.p2Server_ms = 50,
.p2xServer_10ms = 500,
.s3Server_ms = 5000,
};
const FlexCanDrv_MsgCfgType msgCfgObj[UDS_MSG_IDX_NUM] = {
{UDS_MSG_IDX_STD_RX_PHYS, 1, UDS_PHYS_RECV_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_PHYS */
{UDS_MSG_IDX_STD_RX_FUNC, 1, UDS_FUNC_RECV_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_RX_TEST1, 1, APP_RX_TEST1_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_RX_TEST2, 1, APP_RX_TEST2_MSG_ID, false, FLEXCANDRV_MSGTYPE_RX, DLC_BYTE_8, false, true, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_RX_FUNC */
{UDS_MSG_IDX_STD_TX, 1, UDS_PHYS_RESP_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
{UDS_MSG_IDX_STD_TEST1, 1, APP_TX_TEST1_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
{UDS_MSG_IDX_STD_TEST2, 1, APP_TX_TEST2_MSG_ID, false, FLEXCANDRV_MSGTYPE_TX, DLC_BYTE_8, false, false, 0xFFFFFFFF}, /* CAN_MSGOBJ_STD_TX */
};
#pragma location = ".bss.no_init"
static uint32_t sAswBoot_Req;
#pragma location = ".asw_header" #pragma location = ".asw_header"
__root const app_CfgInfoType app_inif = { __root const app_CfgInfoType app_inif = {
@ -159,291 +73,33 @@ __root const app_CfgInfoType app_inif = {
* the functions * the functions
******************************************************************************/ ******************************************************************************/
void Asw_SetBootloaderRequest(void)
{
sAswBoot_Req = ASW_BOOT_REQ_ACTIVE;
}
int64_t Get_Cur_Time_Stamp(void)
{
return timer_1ms;
}
void SysTick_Handler(void)
{
gSystick1msEvent++;
timer_1ms++;
Uds_Tick(&udsObj);
}
void CAN0_ERxFIFO_Handler(void)
{
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE) == true)
{
if(FlexCanDrv_GetEnhanceRxFFIsFull(flexCanDrv_DemoObj) == false)
{
}
if(FlexCanDrv_GetEnhanceRxFFIsEmpty(flexCanDrv_DemoObj) == false)
{
FlexCanDrv_MsgObjType rxMsgObj;
flexCanBoot_EnhanceRxFFCnt = FlexCanDrv_GetEnhanceRxFFMsgNums(flexCanDrv_DemoObj);
if(flexCanBoot_EnhanceRxFFCnt > 0)
{
FlexCanDrv_GetEnhanceRxFifoMsg(flexCanDrv_DemoObj, &rxMsgObj);
memcpy(flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].data, rxMsgObj.data, rxMsgObj.dlc);
flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].id = rxMsgObj.msgId;
flexCan_DataInfo.rxMsg[flexCan_DataInfo.wrIdx].len = rxMsgObj.dlc;
flexCan_DataInfo.wrIdx++;
if(flexCan_DataInfo.wrIdx >= CAN_BUFFER_FIFO_SIZE)
{
flexCan_DataInfo.wrIdx = 0;
}
}
}
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_WMMIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_WMMIE);
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_OVFIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_OVFIE);
}
if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_UFWIE) == true)
{
FlexCanDrv_ClearEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_UFWIE);
}
}
bool FlexCanBoot_ReadoutMsg(FlexCan_FrameStructureType* pRxMsgObj)
{
bool ret = false;
if(flexCan_DataInfo.wrIdx != flexCan_DataInfo.rdIdx)
{
memcpy(pRxMsgObj, &flexCan_DataInfo.rxMsg[flexCan_DataInfo.rdIdx], sizeof(FlexCan_FrameStructureType));
flexCan_DataInfo.rdIdx++;
if(flexCan_DataInfo.rdIdx >= CAN_BUFFER_FIFO_SIZE)
{
flexCan_DataInfo.rdIdx = 0;
}
ret = true;
}
return ret;
}
static int8_t FlexCanBoot_TxMessage(uint32_t msgId, const uint8_t* pData, uint8_t size)
{
FlexCanDrv_MsgObjType txMsgObj;
uint8_t msgIdx = 0, i = 0;
for(i = 0; i < flexCanCfg.msgNum; i++)
{
if(msgId == flexCanCfg.msgCfg[i].msgId)
{
msgIdx = i;
break;
}
}
txMsgObj.msgBufId = flexCanCfg.msgCfg[msgIdx].msgBufId;
txMsgObj.dlc = size;
txMsgObj.msgId = flexCanCfg.msgCfg[msgIdx].msgId;
memcpy(&txMsgObj.data[0], pData, size);
FlexCanDrv_SetTxMsg(flexCanDrv_DemoObj, &txMsgObj);
/* transmit standard CAN Tx message */
FlexCanDrv_TransmitMsg(flexCanDrv_DemoObj, &txMsgObj);
return 0;
}
void FlexCanBoot_Init(void)
{
uint32_t busClockFreq = 0;
flexCanDrv_DemoObj = &mcu.flexCanDrv0;
/* set PTE4 as MUX 5 - CAN0.RX */
PinsDrv_SetMuxModeSel(&mcu.ptb, 0, PINSDRV_MUX_ALT5);
/* set PTE5 as MUX 5 - CAN0.TX */
PinsDrv_SetMuxModeSel(&mcu.ptb, 1, PINSDRV_MUX_ALT5);
flexCanCfg.clkSrc = FLEXCANDRV_CLKSRC_CHICLK;
flexCanCfg.fdEnable = false;
flexCanCfg.fdISOEnable = false;
flexCanCfg.enhancefifoEnable = true;
flexCanCfg.msgBufDataLenSel = FLEXCANDRV_MB_SIZE_BYTE_8;
flexCanCfg.individualMaskEnable = true;
if(flexCanCfg.clkSrc == FLEXCANDRV_CLKSRC_CHICLK)
{
ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_APB, &busClockFreq);
}
else
{
ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SOSC_DIV2, &busClockFreq);
}
if(flexCanCfg.fdEnable == true)
{
FlexCanDrv_BitTimingCalc(&flexCanCfg.fdBitTiming,
busClockFreq, /* module clock source: 16M */
2000000, /* baudrate: 2M */
7500, /* sample point: 75% */
2000, /* SJW: 20% */
1); /* FD bit timing */
}
FlexCanDrv_BitTimingCalc(&flexCanCfg.bitTiming,
busClockFreq, /* module clock source: 16M */
500000, /* baudrate: 500K */
7500, /* sample point: 75% */
2500, /* SJW: 20% */
0); /* classic CAN bit timing */
/* initialize CAN module */
FlexCanDrv_Configure(flexCanDrv_DemoObj, &flexCanCfg);
/* enable enhance rx fifo interrupt */
FlexCanDrv_SetEnhanceRxFFIsr(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE, true);
IrqDrv_EnableIrq(CAN0_ERxFIFO_IRQn);
}
int main(void) int main(void)
{ {
uint32_t tTcr = 0;
FlexCan_FrameStructureType rxMsg;
IrqDrv_DisableGlobalInterrupt(); IrqDrv_DisableGlobalInterrupt();
/* Setup the clock */
ClockDrv_ModuleClkConfigType clockConfig;
/* Initialize all MCU drivers: flash drv included */ /* Initialize all MCU drivers: flash drv included */
Mcu_Init(&mcu); Mcu_Init(&mcu);
SEGGER_RTT_Init(); SEGGER_RTT_Init();
SEGGER_RTT_printf(0,"sAswBoot_Req = %x\n",sAswBoot_Req);
SEGGER_RTT_printf(0,"-----clock_INIT-----\n");
WdgDrv_Disable(&mcu.wdgDrv); hw_init(&mcu);
/* Enable the clock for all ports */ appTaskInit(&mcu);
clockConfig.gating = true;
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTA, &clockConfig);
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTB, &clockConfig);
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTC, &clockConfig);
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig);
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig);
/* Setup the Pll div2 clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_PLL;
clockConfig.div = 1;
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
/* Setup the FIRC2 div2 clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_FIRC;
clockConfig.div = 1;
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_FIRC_DIV2, &clockConfig);
ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_CORE, &gCpuClockFrequency);
/* Setup the SPI clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_PLL_DIV2;
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI2, &clockConfig);
tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv2.reg);
SpiDrv_SetPrescaler(&tTcr,0x03);
SEGGER_RTT_printf(0,"-----SPI_INIT-----\n");
SBC_SPI_INIT();
/* CAN init */
memset(&flexCan_DataInfo, 0, sizeof(flexCan_DataInfo));
memset(&flexCanCfg, 0, sizeof(flexCanCfg));
SEGGER_RTT_printf(0,"-----FlexCanDrv_INIT-----\n");
/* get CAN controller default configuration */
FlexCanDrv_GetDefaultCfg(&flexCanCfg);
flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
flexCanCfg.msgCfg = msgCfgObj;
FlexCanBoot_Init();
/* UDS init */
Uds_UserInit(&udsObj, &udsParam);
/* Set system tick clock, 1ms event */
SysTick_Config(gCpuClockFrequency / 1000u);
IrqDrv_EnableIrq(SysTick_IRQn);
PinsDrv_WritePin(&mcu.ptd, 3, 0);
PinsDrv_WritePin(&mcu.pta, 17, 0);
IrqDrv_EnableGlobalInterrupt(); IrqDrv_EnableGlobalInterrupt();
SEGGER_RTT_printf(0,"-----init success-----\n"); SEGGER_RTT_printf(0,"-----init success-----\n");
while(1) while(1)
{ {
if(gSystick1msEvent > 0u) appTask(&mcu);
{
if(udsObj.session == UDS_SESSION_PROGRAMMING)
{
Asw_SetBootloaderRequest();
ResetDrv_SoftwareResetModule(&mcu.resetDrv, RESETDRV_SWRESET_SYS);
}
gSystick1msEvent--;
gSystick1msCnt++;
gSysTick1sCnt++;
if (gSystick1msCnt % 10 == 0)
{
SBC_WD_Trigger();
}
if(gSystick1msCnt % 200 == 0)
{
uint8_t txMsgBuf[8]={0};
txMsgBuf[0] = aswVersion;
txMsgBuf[3] = gSysTick1sCnt & 0xFF;
FlexCanBoot_TxMessage(APP_TX_TEST1_MSG_ID, txMsgBuf, 8);
}
if (gSystick1msCnt >= 5000)
{
gSystick1msCnt = 0;
SEGGER_RTT_printf(0,"app running\n");
}
/* Handler user routine */
if(FlexCanBoot_ReadoutMsg(&rxMsg) == true)
{
if((rxMsg.id == UDS_PHYS_RECV_MSG_ID) || (rxMsg.id == UDS_FUNC_RECV_MSG_ID))
{
IsoTp_HandleIncomingCanMsg(&udsObj.isotp, rxMsg.id, rxMsg.data, rxMsg.len);
}
else
{
}
}
Uds_Run(&udsObj);
}
} }
} }

125
cva_asw_m0146/src/private_driver/drivers/cpu/startup/app_system_M014x.c
View File

@ -38,131 +38,6 @@
* the functions * the functions
******************************************************************************/ ******************************************************************************/
static void userSystemInit(void)
{
/* Enable cache */
CACHE->CTRL = 0x1C7;
/* Enable PFLASH prefetch */
SimReg_SetFlashPFlsPfbEn(SIM, 1);
/* Setup the clock */
AcgReg_SetLockKey(ACG, 0xFA8623E4); /* Unlock ACG */
ScgReg_SetLockKey(SCG, 0x53436D65); /* Unlock SCG */
#if defined (_USE_EXT_OSC_)
/* Use External oscillator */
AcgReg_SetOscRange(ACG, 3); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */
AcgReg_SetEnSosc(ACG, 1); /* enable SOSC */
while(AcgReg_GetStSoscRdy(ACG) == 0); /* wait until SOSC is ready */
/* Configure PLL */
AcgReg_SetEnPll(ACG, 0); /* Disable PLL first */
/* PLL configuration:
* - PLL input clock source : SOSC
* - PLL pre-divider : 1
* - feedback divider : 45
* - PLL Feedback clock divider pre-scaler : 1
* - PLL post-divider setting : 3
* Final PLL output frequency is 16M(SOSC) * 45 / 3 / 2 = 120M
*/
AcgReg_SetPllClkIn(ACG, 2);
AcgReg_SetPllPreDiv(ACG, 0);
AcgReg_SetPllM(ACG, 45);
AcgReg_SetPllFbkSel(ACG, 0);
AcgReg_SetPllPosDiv(ACG, 3);
/* SCG PLL configuration:
* - PLL DIV1 clock divider : 1
* - PLL DIV2 clock divider : 1
*/
ScgReg_SetPllCfgDiv1(SCG, 0);
ScgReg_SetPllCfgDiv2(SCG, 0);
/* Enable PLL */
AcgReg_SetEnPll(ACG, 1);
/* delay before check PLL locked flag */
SysTick->LOAD = 48000U;
SysTick->VAL = 0U;
SysTick->CTRL = 5U; /* SysTick uses the processor clock and enable sysTick */
while(SysTick->CTRL < 0x10000){
;/* wait for COUNTFLAG setting*/
}
/*recover sysTick register*/
SysTick->CTRL = 4U;
SysTick->LOAD = 0U;
SysTick->VAL = 0U;
while(AcgReg_GetStPllLock(ACG) == 0); /* Wait until PLL is locked */
/* Set Core and APB clock source divider */
AcgReg_SetSysDivCore(ACG, 0); /* Divide-by-1 */
ScgReg_SetCsrDivApb(SCG, 1); /* Divide-by-2 */
/* Flash frequency MUST be 8M */
ScgReg_SetCsrDivCntFls(SCG, 14); /* Divide-by-15 */
/* Flash AHB bus read access time configure */
FtfcReg_SetFcnfgBusReadTm(FTFC, 2); /* 160M->3, 120M->2, 80M->1, 48M->0 */
/* Set Core clock source to PLL */
AcgReg_SetSysSrcSys(ACG, 2); /* select pll as clock source */
#else
/* Use on-chip internal clock */
/* Configure PLL */
AcgReg_SetEnPll(ACG, 0); /* Disable PLL first */
/* PLL configuration:
* - PLL input clock source : FIRC
* - PLL pre-divider : 1
* - feedback divider : 15
* - PLL Feedback clock divider pre-scaler : 1
* - PLL post-divider setting : 3
* Final PLL output frequency is 48M(FIRC) * 15 / 3 / 2 = 120M
*/
AcgReg_SetPllClkIn(ACG, 0);
AcgReg_SetPllPreDiv(ACG, 0);
AcgReg_SetPllM(ACG, 15);
AcgReg_SetPllFbkSel(ACG, 0);
AcgReg_SetPllPosDiv(ACG, 3);
/* SCG PLL configuration:
* - PLL DIV1 clock divider : 1
* - PLL DIV2 clock divider : 1
*/
ScgReg_SetPllCfgDiv1(SCG, 0);
ScgReg_SetPllCfgDiv2(SCG, 0);
/* Enable PLL */
AcgReg_SetEnPll(ACG, 1);
while(AcgReg_GetStPllLock(ACG) == 0); /* Wait until PLL is locked */
/* Set Core and APB clock source divider */
AcgReg_SetSysDivCore(ACG, 0); /* Divide-by-1 */
ScgReg_SetCsrDivApb(SCG, 1); /* Divide-by-2 */
/* Flash frequency MUST be 8M */
ScgReg_SetCsrDivCntFls(SCG, 14); /* Divide-by-15 */
/* Flash AHB bus read access time configure */
FtfcReg_SetFcnfgBusReadTm(FTFC, 2); /* 160M->3, 120M->2, 80M->1, 48M->0 */
/* Set Core clock source to PLL */
AcgReg_SetSysSrcSys(ACG, 2); /* select pll as clock source */
#endif
/* Finish setting up the clock */
AcgReg_SetLockKey(ACG, 0); /* Lock ACG again */
ScgReg_SetLockKey(SCG, 0); /* Lock SCG again */
/* Enable FPU */
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
/*Release of all peripheral interview access*/
AIPS->PACRA = 0;
AIPS->PACRB = 0;
AIPS->PACRC = 0;
AIPS->PACRD = 0;
AIPS->PACRE = 0;
AIPS->PACRF = 0;
AIPS->PACRG = 0;
AIPS->PACRH = 0;
}
void SystemInit(void) void SystemInit(void)
{ {
#if 0 #if 0

3
cva_bootloader_m0146/.vscode/settings.json vendored
View File

@ -7,5 +7,6 @@
"tle94x1_spi.h": "c", "tle94x1_spi.h": "c",
"cpu_drv.h": "c", "cpu_drv.h": "c",
"segger_rtt.h": "c" "segger_rtt.h": "c"
} },
"C_Cpp.default.compilerPath": ""
} }