From ffedf209af875e039b5e5f57a5e6c615937c0ddf Mon Sep 17 00:00:00 2001
From: sunbeam <fcb1995@163.com>
Date: Tue, 7 May 2024 08:14:06 +0800
Subject: [PATCH] =?UTF-8?q?=E9=80=9A=E8=AE=AFOK?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 cva_bootloader_m0146/.vscode/settings.json    |    4 +-
 cva_bootloader_m0146/cva_bootloader_m0146.ewd |  364 +-
 cva_bootloader_m0146/cva_bootloader_m0146.ewp |  373 +-
 cva_bootloader_m0146/cva_bootloader_m0146.ewt |  558 ++-
 .../cva_bootloader_m0146.Debug.cspy.bat       |    4 +-
 .../cva_bootloader_m0146.Debug.cspy.ps1       |    4 +-
 .../cva_bootloader_m0146.Debug.driver.xcl     |    2 +-
 .../cva_bootloader_m0146.Debug.general.xcl    |    6 +-
 .../settings/cva_bootloader_m0146.dbgdt       |  156 +-
 .../settings/cva_bootloader_m0146.dnx         |   89 +-
 .../settings/cva_bootloader_m0146.wsdt        |  288 +-
 .../cva_bootloader_m0146_EditorBookmarks.xml  |    2 +
 cva_bootloader_m0146/src/RTT/README.txt       |   23 +
 cva_bootloader_m0146/src/RTT/SEGGER_RTT.c     | 2078 +++++++++++
 cva_bootloader_m0146/src/RTT/SEGGER_RTT.h     |  419 +++
 .../src/RTT/SEGGER_RTT_ASM_ARMv7M.S           |  242 ++
 .../src/RTT/SEGGER_RTT_Conf.h                 |  429 +++
 .../src/RTT/SEGGER_RTT_Syscalls_GCC.c         |  125 +
 .../src/RTT/SEGGER_RTT_printf.c               |  505 +++
 .../src/TLE9461/SBC_TLE94x1.h                 |  101 +
 cva_bootloader_m0146/src/TLE9461/TLE9461.icwp |  233 ++
 cva_bootloader_m0146/src/TLE9461/TLE94x1.c    |  591 +++
 cva_bootloader_m0146/src/TLE9461/TLE94x1.h    |  393 ++
 .../src/TLE9461/TLE94x1_DEFINES.h             | 3248 +++++++++++++++++
 .../src/TLE9461/TLE94x1_ISR.h                 |  127 +
 .../src/TLE9461/TLE94x1_SPI.c                 |  156 +
 .../src/TLE9461/TLE94x1_SPI.h                 |   95 +
 cva_bootloader_m0146/src/main.c               |   78 +-
 .../private_driver/drivers/clock/clock_drv.c  |    3 +-
 .../private_driver/drivers/clock/clock_drv.h  |    3 +-
 cva_bootloader_m0146/src/private_driver/mcu.c |    4 +
 31 files changed, 10364 insertions(+), 339 deletions(-)
 create mode 100644 cva_bootloader_m0146/settings/cva_bootloader_m0146_EditorBookmarks.xml
 create mode 100644 cva_bootloader_m0146/src/RTT/README.txt
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT.c
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT.h
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT_ASM_ARMv7M.S
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT_Conf.h
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT_Syscalls_GCC.c
 create mode 100644 cva_bootloader_m0146/src/RTT/SEGGER_RTT_printf.c
 create mode 100644 cva_bootloader_m0146/src/TLE9461/SBC_TLE94x1.h
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE9461.icwp
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1.c
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1.h
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1_DEFINES.h
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1_ISR.h
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.c
 create mode 100644 cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.h

diff --git a/cva_bootloader_m0146/.vscode/settings.json b/cva_bootloader_m0146/.vscode/settings.json
index f60e6d9..2a4ee3d 100644
--- a/cva_bootloader_m0146/.vscode/settings.json
+++ b/cva_bootloader_m0146/.vscode/settings.json
@@ -2,6 +2,8 @@
     "files.associations": {
         "uds_service27.h": "c",
         "uds.h": "c",
-        "uds_user.h": "c"
+        "uds_user.h": "c",
+        "tle94x1.h": "c",
+        "tle94x1_spi.h": "c"
     }
 }
\ No newline at end of file
diff --git a/cva_bootloader_m0146/cva_bootloader_m0146.ewd b/cva_bootloader_m0146/cva_bootloader_m0146.ewd
index a583e0c..048f643 100644
--- a/cva_bootloader_m0146/cva_bootloader_m0146.ewd
+++ b/cva_bootloader_m0146/cva_bootloader_m0146.ewd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project>
-    <fileVersion>3</fileVersion>
+    <fileVersion>4</fileVersion>
     <configuration>
         <name>Debug</name>
         <toolchain>
@@ -11,7 +11,7 @@
             <name>C-SPY</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>31</version>
+                <version>33</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -44,7 +44,7 @@
                 </option>
                 <option>
                     <name>MemFile</name>
-                    <state>$TOOLKIT_DIR$\CONFIG\debugger\CVAChip\CVM0146.ddf</state>
+                    <state></state>
                 </option>
                 <option>
                     <name>RunToEnable</name>
@@ -88,7 +88,7 @@
                 </option>
                 <option>
                     <name>OCLastSavedByProductVersion</name>
-                    <state>8.40.1.21529</state>
+                    <state>9.40.2.67586</state>
                 </option>
                 <option>
                     <name>UseFlashLoader</name>
@@ -218,6 +218,42 @@
                     <name>OCMulticoreSessionFile</name>
                     <state></state>
                 </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -453,6 +489,39 @@
                 </option>
             </data>
         </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
         <settings>
             <name>GDBSERVER_ID</name>
             <archiveVersion>2</archiveVersion>
@@ -494,7 +563,7 @@
             <name>IJET_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>8</version>
+                <version>9</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -718,6 +787,58 @@
                     <name>CCIjetUsbSerialNoSelect</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -831,7 +952,7 @@
                 <option>
                     <name>CCJLinkResetList</name>
                     <version>6</version>
-                    <state>7</state>
+                    <state>5</state>
                 </option>
                 <option>
                     <name>CCJLinkInterfaceCmdLine</name>
@@ -924,7 +1045,7 @@
             <name>LMIFTDI_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>2</version>
+                <version>3</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -951,6 +1072,19 @@
                     <name>CCLmiFtdiInterfaceCmdLine</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1003,7 +1137,7 @@
             <name>STLINK_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>6</version>
+                <version>8</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -1118,9 +1252,17 @@
                 </option>
                 <option>
                     <name>CCSTLinkProbeList</name>
-                    <version>0</version>
+                    <version>2</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1223,7 +1365,7 @@
             <name>XDS100_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>8</version>
+                <version>9</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -1348,7 +1490,7 @@
                 </option>
                 <option>
                     <name>CCXds100ResetList</name>
-                    <version>0</version>
+                    <version>1</version>
                     <state>0</state>
                 </option>
                 <option>
@@ -1397,6 +1539,10 @@
                     <name>OCXDSDigitalStatesConfigFile</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <debuggerPlugins>
@@ -1416,10 +1562,6 @@
                 <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
@@ -1432,30 +1574,18 @@
                 <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
             <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
                 <loadFlag>0</loadFlag>
@@ -1492,7 +1622,7 @@
             <name>C-SPY</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>31</version>
+                <version>33</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -1699,6 +1829,42 @@
                     <name>OCMulticoreSessionFile</name>
                     <state></state>
                 </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1934,6 +2100,39 @@
                 </option>
             </data>
         </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
         <settings>
             <name>GDBSERVER_ID</name>
             <archiveVersion>2</archiveVersion>
@@ -1975,7 +2174,7 @@
             <name>IJET_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>8</version>
+                <version>9</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -2199,6 +2398,58 @@
                     <name>CCIjetUsbSerialNoSelect</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -2405,7 +2656,7 @@
             <name>LMIFTDI_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>2</version>
+                <version>3</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -2432,6 +2683,19 @@
                     <name>CCLmiFtdiInterfaceCmdLine</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -2484,7 +2748,7 @@
             <name>STLINK_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>6</version>
+                <version>8</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -2599,9 +2863,17 @@
                 </option>
                 <option>
                     <name>CCSTLinkProbeList</name>
-                    <version>0</version>
+                    <version>2</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -2704,7 +2976,7 @@
             <name>XDS100_ID</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>8</version>
+                <version>9</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -2829,7 +3101,7 @@
                 </option>
                 <option>
                     <name>CCXds100ResetList</name>
-                    <version>0</version>
+                    <version>1</version>
                     <state>0</state>
                 </option>
                 <option>
@@ -2878,6 +3150,10 @@
                     <name>OCXDSDigitalStatesConfigFile</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <debuggerPlugins>
@@ -2897,10 +3173,6 @@
                 <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
@@ -2913,30 +3185,18 @@
                 <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
             <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
                 <loadFlag>0</loadFlag>
             </plugin>
-            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-                <loadFlag>0</loadFlag>
-            </plugin>
             <plugin>
                 <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
                 <loadFlag>0</loadFlag>
diff --git a/cva_bootloader_m0146/cva_bootloader_m0146.ewp b/cva_bootloader_m0146/cva_bootloader_m0146.ewp
index db02d20..0343525 100644
--- a/cva_bootloader_m0146/cva_bootloader_m0146.ewp
+++ b/cva_bootloader_m0146/cva_bootloader_m0146.ewp
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project>
-    <fileVersion>3</fileVersion>
+    <fileVersion>4</fileVersion>
     <configuration>
         <name>Debug</name>
         <toolchain>
@@ -11,9 +11,13 @@
             <name>General</name>
             <archiveVersion>3</archiveVersion>
             <data>
-                <version>31</version>
+                <version>36</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Debug\BrowseInfo</state>
+                </option>
                 <option>
                     <name>ExePath</name>
                     <state>Debug_FLASH\Exe</state>
@@ -58,7 +62,7 @@
                 </option>
                 <option>
                     <name>RTDescription</name>
-                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                    <state>A complete configuration of the C/C++14 runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
                 </option>
                 <option>
                     <name>OGProductVersion</name>
@@ -66,15 +70,7 @@
                 </option>
                 <option>
                     <name>OGLastSavedByProductVersion</name>
-                    <state>8.40.1.21529</state>
-                </option>
-                <option>
-                    <name>GeneralEnableMisra</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GeneralMisraVerbose</name>
-                    <state>0</state>
+                    <state>9.40.2.67586</state>
                 </option>
                 <option>
                     <name>OGChipSelectEditMenu</name>
@@ -96,27 +92,13 @@
                     <name>GenStdoutInterface</name>
                     <state>0</state>
                 </option>
-                <option>
-                    <name>GeneralMisraRules98</name>
-                    <version>0</version>
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-                </option>
-                <option>
-                    <name>GeneralMisraVer</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GeneralMisraRules04</name>
-                    <version>0</version>
-                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-                </option>
                 <option>
                     <name>RTConfigPath2</name>
                     <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
                 </option>
                 <option>
                     <name>GBECoreSlave</name>
-                    <version>27</version>
+                    <version>33</version>
                     <state>39</state>
                 </option>
                 <option>
@@ -133,7 +115,7 @@
                 </option>
                 <option>
                     <name>CoreVariant</name>
-                    <version>27</version>
+                    <version>33</version>
                     <state>39</state>
                 </option>
                 <option>
@@ -156,7 +138,7 @@
                 </option>
                 <option>
                     <name>GFPUCoreSlave2</name>
-                    <version>27</version>
+                    <version>33</version>
                     <state>39</state>
                 </option>
                 <option>
@@ -209,13 +191,38 @@
                     <version>0</version>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>Debug</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OG_32_64DeviceCoreSlave</name>
+                    <version>33</version>
+                    <state>39</state>
+                </option>
             </data>
         </settings>
         <settings>
             <name>ICCARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>35</version>
+                <version>38</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -339,10 +346,6 @@
                     <name>PreInclude</name>
                     <state></state>
                 </option>
-                <option>
-                    <name>CompilerMisraOverride</name>
-                    <state>0</state>
-                </option>
                 <option>
                     <name>CCIncludePath2</name>
                     <state>$PROJ_DIR$\src\bootloader</state>
@@ -357,6 +360,8 @@
                     <state>$PROJ_DIR$\src\private_driver</state>
                     <state>$PROJ_DIR$\SDK\platform\devices\CVM014x</state>
                     <state>$PROJ_DIR$\src\private_driver\drivers\clock</state>
+                    <state>$PROJ_DIR$\src\RTT</state>
+                    <state>$PROJ_DIR$\src\TLE9461</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>
@@ -383,16 +388,6 @@
                     <name>CCOptLevelSlave</name>
                     <state>0</state>
                 </option>
-                <option>
-                    <name>CompilerMisraRules98</name>
-                    <version>0</version>
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-                </option>
-                <option>
-                    <name>CompilerMisraRules04</name>
-                    <version>0</version>
-                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-                </option>
                 <option>
                     <name>CCPosIndRopi</name>
                     <state>0</state>
@@ -478,13 +473,25 @@
                     <name>OICompilerExtraOption</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPointerAutentiction</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCBranchTargetIdentification</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
             <name>AARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>10</version>
+                <version>12</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -641,6 +648,14 @@
                     <name>AsmNoLiteralPool</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>A_32_64Device</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -680,36 +695,20 @@
                 <extensions></extensions>
                 <cmdline></cmdline>
                 <hasPrio>0</hasPrio>
-            </data>
-        </settings>
-        <settings>
-            <name>BICOMP</name>
-            <archiveVersion>0</archiveVersion>
-            <data />
-        </settings>
-        <settings>
-            <name>BUILDACTION</name>
-            <archiveVersion>1</archiveVersion>
-            <data>
-                <prebuild></prebuild>
-                <postbuild></postbuild>
+                <buildSequence>inputOutputBased</buildSequence>
             </data>
         </settings>
         <settings>
             <name>ILINK</name>
             <archiveVersion>0</archiveVersion>
             <data>
-                <version>23</version>
+                <version>27</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
                     <name>IlinkLibIOConfig</name>
                     <state>1</state>
                 </option>
-                <option>
-                    <name>XLinkMisraHandler</name>
-                    <state>0</state>
-                </option>
                 <option>
                     <name>IlinkInputFileSlave</name>
                     <state>0</state>
@@ -1035,6 +1034,42 @@
                     <name>IlinkRawBinaryAlign2</name>
                     <state></state>
                 </option>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1059,8 +1094,8 @@
             </data>
         </settings>
         <settings>
-            <name>BILINK</name>
-            <archiveVersion>0</archiveVersion>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
             <data />
         </settings>
     </configuration>
@@ -1074,9 +1109,13 @@
             <name>General</name>
             <archiveVersion>3</archiveVersion>
             <data>
-                <version>31</version>
+                <version>36</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Release\BrowseInfo</state>
+                </option>
                 <option>
                     <name>ExePath</name>
                     <state>Release\Exe</state>
@@ -1129,19 +1168,11 @@
                 </option>
                 <option>
                     <name>OGLastSavedByProductVersion</name>
-                    <state>8.11.3.13977</state>
-                </option>
-                <option>
-                    <name>GeneralEnableMisra</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GeneralMisraVerbose</name>
-                    <state>0</state>
+                    <state>9.40.2.67586</state>
                 </option>
                 <option>
                     <name>OGChipSelectEditMenu</name>
-                    <state>CVM0146	CVM0146</state>
+                    <state>Default	None</state>
                 </option>
                 <option>
                     <name>GenLowLevelInterface</name>
@@ -1159,27 +1190,13 @@
                     <name>GenStdoutInterface</name>
                     <state>0</state>
                 </option>
-                <option>
-                    <name>GeneralMisraRules98</name>
-                    <version>0</version>
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-                </option>
-                <option>
-                    <name>GeneralMisraVer</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GeneralMisraRules04</name>
-                    <version>0</version>
-                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-                </option>
                 <option>
                     <name>RTConfigPath2</name>
                     <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
                 </option>
                 <option>
                     <name>GBECoreSlave</name>
-                    <version>27</version>
+                    <version>33</version>
                     <state>39</state>
                 </option>
                 <option>
@@ -1196,8 +1213,8 @@
                 </option>
                 <option>
                     <name>CoreVariant</name>
-                    <version>27</version>
-                    <state>39</state>
+                    <version>33</version>
+                    <state>0</state>
                 </option>
                 <option>
                     <name>GFPUDeviceSlave</name>
@@ -1219,7 +1236,7 @@
                 </option>
                 <option>
                     <name>GFPUCoreSlave2</name>
-                    <version>27</version>
+                    <version>33</version>
                     <state>39</state>
                 </option>
                 <option>
@@ -1272,13 +1289,38 @@
                     <version>0</version>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>Release</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OG_32_64DeviceCoreSlave</name>
+                    <version>33</version>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
             <name>ICCARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>35</version>
+                <version>38</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -1402,10 +1444,6 @@
                     <name>PreInclude</name>
                     <state></state>
                 </option>
-                <option>
-                    <name>CompilerMisraOverride</name>
-                    <state>0</state>
-                </option>
                 <option>
                     <name>CCIncludePath2</name>
                     <state>$PROJ_DIR$\src\bootloader</state>
@@ -1446,16 +1484,6 @@
                     <name>CCOptLevelSlave</name>
                     <state>3</state>
                 </option>
-                <option>
-                    <name>CompilerMisraRules98</name>
-                    <version>0</version>
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-                </option>
-                <option>
-                    <name>CompilerMisraRules04</name>
-                    <version>0</version>
-                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-                </option>
                 <option>
                     <name>CCPosIndRopi</name>
                     <state>0</state>
@@ -1541,13 +1569,25 @@
                     <name>OICompilerExtraOption</name>
                     <state>1</state>
                 </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPointerAutentiction</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCBranchTargetIdentification</name>
+                    <state>0</state>
+                </option>
             </data>
         </settings>
         <settings>
             <name>AARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>10</version>
+                <version>12</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -1704,6 +1744,14 @@
                     <name>AsmNoLiteralPool</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>A_32_64Device</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1743,36 +1791,20 @@
                 <extensions></extensions>
                 <cmdline></cmdline>
                 <hasPrio>0</hasPrio>
-            </data>
-        </settings>
-        <settings>
-            <name>BICOMP</name>
-            <archiveVersion>0</archiveVersion>
-            <data />
-        </settings>
-        <settings>
-            <name>BUILDACTION</name>
-            <archiveVersion>1</archiveVersion>
-            <data>
-                <prebuild></prebuild>
-                <postbuild>$PROJ_DIR$\bat_complier_object\convert_hex.bat</postbuild>
+                <buildSequence>inputOutputBased</buildSequence>
             </data>
         </settings>
         <settings>
             <name>ILINK</name>
             <archiveVersion>0</archiveVersion>
             <data>
-                <version>23</version>
+                <version>27</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
                     <name>IlinkLibIOConfig</name>
                     <state>1</state>
                 </option>
-                <option>
-                    <name>XLinkMisraHandler</name>
-                    <state>0</state>
-                </option>
                 <option>
                     <name>IlinkInputFileSlave</name>
                     <state>0</state>
@@ -2098,6 +2130,42 @@
                     <name>IlinkRawBinaryAlign2</name>
                     <state></state>
                 </option>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -2122,9 +2190,22 @@
             </data>
         </settings>
         <settings>
-            <name>BILINK</name>
-            <archiveVersion>0</archiveVersion>
-            <data />
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <buildActions>
+                    <buildAction>
+                        <cmdline>$PROJ_DIR$\bat_complier_object\convert_hex.bat &amp;&amp; echo &gt; "$BUILD_FILES_DIR$/.postbuild"</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>postLink</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$BUILD_FILES_DIR$/.postbuild</name>
+                            </file>
+                        </outputs>
+                    </buildAction>
+                </buildActions>
+            </data>
         </settings>
     </configuration>
     <group>
@@ -2863,6 +2944,36 @@
                 <name>$PROJ_DIR$\SDK\platform\devices\CVM014x\reg\wdg_reg.h</name>
             </file>
         </group>
+        <group>
+            <name>RTT</name>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_ASM_ARMv7M.S</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_printf.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
+            </file>
+        </group>
+        <group>
+            <name>TLE9461</name>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
+            </file>
+        </group>
         <file>
             <name>$PROJ_DIR$\src\main.c</name>
         </file>
diff --git a/cva_bootloader_m0146/cva_bootloader_m0146.ewt b/cva_bootloader_m0146/cva_bootloader_m0146.ewt
index 63c7a40..ab24dfb 100644
--- a/cva_bootloader_m0146/cva_bootloader_m0146.ewt
+++ b/cva_bootloader_m0146/cva_bootloader_m0146.ewt
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project>
-    <fileVersion>3</fileVersion>
+    <fileVersion>4</fileVersion>
     <configuration>
         <name>Debug</name>
         <toolchain>
@@ -9,9 +9,9 @@
         <debug>1</debug>
         <settings>
             <name>C-STAT</name>
-            <archiveVersion>261</archiveVersion>
+            <archiveVersion>517</archiveVersion>
             <data>
-                <version>261</version>
+                <version>517</version>
                 <cstatargs>
                     <useExtraArgs>0</useExtraArgs>
                     <extraArgs></extraArgs>
@@ -22,9 +22,10 @@
                     <enableFalsePositives>0</enableFalsePositives>
                     <messagesLimitEnabled>1</messagesLimitEnabled>
                     <messagesLimit>100</messagesLimit>
+                    <outputDir>Debug/C-STAT</outputDir>
                 </cstatargs>
                 <cstat_settings>
-                    <cstat_version>1.5.5</cstat_version>
+                    <cstat_version>2.5.2</cstat_version>
                     <checks_tree>
                         <package enabled="true" name="STDCHECKS">
                             <group enabled="true" name="ARR">
@@ -304,15 +305,215 @@
                             </group>
                         </package>
                         <package enabled="false" name="CERT">
+                            <group enabled="true" name="CERT-ARR">
+                                <check enabled="true" name="CERT-ARR30-C_a" />
+                                <check enabled="true" name="CERT-ARR30-C_b" />
+                                <check enabled="true" name="CERT-ARR30-C_c" />
+                                <check enabled="true" name="CERT-ARR30-C_d" />
+                                <check enabled="true" name="CERT-ARR30-C_e" />
+                                <check enabled="true" name="CERT-ARR30-C_f" />
+                                <check enabled="true" name="CERT-ARR30-C_g" />
+                                <check enabled="true" name="CERT-ARR30-C_h" />
+                                <check enabled="true" name="CERT-ARR30-C_i" />
+                                <check enabled="true" name="CERT-ARR30-C_j" />
+                                <check enabled="true" name="CERT-ARR32-C" />
+                                <check enabled="true" name="CERT-ARR36-C_a" />
+                                <check enabled="true" name="CERT-ARR36-C_b" />
+                                <check enabled="true" name="CERT-ARR37-C" />
+                                <check enabled="true" name="CERT-ARR38-C_a" />
+                                <check enabled="true" name="CERT-ARR38-C_b" />
+                                <check enabled="true" name="CERT-ARR38-C_c" />
+                                <check enabled="true" name="CERT-ARR38-C_d" />
+                                <check enabled="true" name="CERT-ARR38-C_e" />
+                                <check enabled="true" name="CERT-ARR38-C_f" />
+                                <check enabled="true" name="CERT-ARR39-C" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check enabled="true" name="CERT-DCL30-C_a" />
+                                <check enabled="true" name="CERT-DCL30-C_b" />
+                                <check enabled="true" name="CERT-DCL30-C_c" />
+                                <check enabled="true" name="CERT-DCL30-C_d" />
+                                <check enabled="true" name="CERT-DCL30-C_e" />
+                                <check enabled="true" name="CERT-DCL31-C" />
+                                <check enabled="true" name="CERT-DCL36-C" />
+                                <check enabled="true" name="CERT-DCL37-C_a" />
+                                <check enabled="true" name="CERT-DCL37-C_b" />
+                                <check enabled="false" name="CERT-DCL37-C_c" />
+                                <check enabled="true" name="CERT-DCL38-C" />
+                                <check enabled="true" name="CERT-DCL39-C" />
+                                <check enabled="true" name="CERT-DCL40-C" />
+                                <check enabled="true" name="CERT-DCL41-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check enabled="true" name="CERT-ENV30-C" />
+                                <check enabled="true" name="CERT-ENV31-C" />
+                                <check enabled="true" name="CERT-ENV32-C" />
+                                <check enabled="true" name="CERT-ENV33-C" />
+                                <check enabled="true" name="CERT-ENV34-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check enabled="true" name="CERT-ERR30-C_a" />
+                                <check enabled="true" name="CERT-ERR30-C_b" />
+                                <check enabled="true" name="CERT-ERR30-C_c" />
+                                <check enabled="true" name="CERT-ERR30-C_d" />
+                                <check enabled="true" name="CERT-ERR30-C_e" />
+                                <check enabled="true" name="CERT-ERR32-C" />
+                                <check enabled="true" name="CERT-ERR33-C_a" />
+                                <check enabled="true" name="CERT-ERR33-C_b" />
+                                <check enabled="true" name="CERT-ERR33-C_c" />
+                                <check enabled="true" name="CERT-ERR33-C_d" />
+                                <check enabled="true" name="CERT-ERR34-C_a" />
+                                <check enabled="true" name="CERT-ERR34-C_b" />
+                            </group>
                             <group enabled="true" name="CERT-EXP">
                                 <check enabled="true" name="CERT-EXP19-C" />
+                                <check enabled="true" name="CERT-EXP30-C_a" />
+                                <check enabled="true" name="CERT-EXP30-C_b" />
+                                <check enabled="true" name="CERT-EXP32-C" />
+                                <check enabled="true" name="CERT-EXP33-C_a" />
+                                <check enabled="true" name="CERT-EXP33-C_b" />
+                                <check enabled="true" name="CERT-EXP33-C_c" />
+                                <check enabled="true" name="CERT-EXP33-C_d" />
+                                <check enabled="true" name="CERT-EXP33-C_e" />
+                                <check enabled="true" name="CERT-EXP33-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_a" />
+                                <check enabled="true" name="CERT-EXP34-C_b" />
+                                <check enabled="true" name="CERT-EXP34-C_c" />
+                                <check enabled="true" name="CERT-EXP34-C_d" />
+                                <check enabled="true" name="CERT-EXP34-C_e" />
+                                <check enabled="true" name="CERT-EXP34-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_g" />
+                                <check enabled="true" name="CERT-EXP35-C" />
+                                <check enabled="true" name="CERT-EXP36-C_a" />
+                                <check enabled="true" name="CERT-EXP36-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_a" />
+                                <check enabled="true" name="CERT-EXP37-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_a" />
+                                <check enabled="true" name="CERT-EXP39-C_b" />
+                                <check enabled="true" name="CERT-EXP39-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_d" />
+                                <check enabled="true" name="CERT-EXP39-C_e" />
+                                <check enabled="true" name="CERT-EXP40-C_a" />
+                                <check enabled="true" name="CERT-EXP40-C_b" />
+                                <check enabled="true" name="CERT-EXP42-C" />
+                                <check enabled="true" name="CERT-EXP43-C_a" />
+                                <check enabled="true" name="CERT-EXP43-C_b" />
+                                <check enabled="true" name="CERT-EXP43-C_c" />
+                                <check enabled="true" name="CERT-EXP43-C_d" />
+                                <check enabled="true" name="CERT-EXP44-C" />
+                                <check enabled="true" name="CERT-EXP45-C" />
+                                <check enabled="true" name="CERT-EXP46-C" />
+                                <check enabled="true" name="CERT-EXP47-C_a" />
+                                <check enabled="true" name="CERT-EXP47-C_b" />
                             </group>
                             <group enabled="true" name="CERT-FIO">
+                                <check enabled="true" name="CERT-FIO30-C" />
+                                <check enabled="true" name="CERT-FIO32-C" />
+                                <check enabled="true" name="CERT-FIO34-C" />
                                 <check enabled="true" name="CERT-FIO37-C" />
                                 <check enabled="true" name="CERT-FIO38-C" />
+                                <check enabled="true" name="CERT-FIO39-C" />
+                                <check enabled="true" name="CERT-FIO40-C" />
+                                <check enabled="true" name="CERT-FIO41-C" />
+                                <check enabled="true" name="CERT-FIO42-C_a" />
+                                <check enabled="false" name="CERT-FIO42-C_b" />
+                                <check enabled="true" name="CERT-FIO44-C" />
+                                <check enabled="true" name="CERT-FIO45-C" />
+                                <check enabled="true" name="CERT-FIO46-C_a" />
+                                <check enabled="true" name="CERT-FIO46-C_b" />
+                                <check enabled="true" name="CERT-FIO46-C_c" />
+                                <check enabled="true" name="CERT-FIO47-C_a" />
+                                <check enabled="true" name="CERT-FIO47-C_b" />
+                                <check enabled="true" name="CERT-FIO47-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check enabled="true" name="CERT-FLP30-C_a" />
+                                <check enabled="true" name="CERT-FLP30-C_b" />
+                                <check enabled="true" name="CERT-FLP32-C_a" />
+                                <check enabled="true" name="CERT-FLP32-C_b" />
+                                <check enabled="true" name="CERT-FLP34-C" />
+                                <check enabled="true" name="CERT-FLP36-C" />
+                                <check enabled="true" name="CERT-FLP37-C" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check enabled="true" name="CERT-INT30-C_a" />
+                                <check enabled="false" name="CERT-INT30-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_a" />
+                                <check enabled="true" name="CERT-INT31-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_c" />
+                                <check enabled="true" name="CERT-INT32-C_a" />
+                                <check enabled="false" name="CERT-INT32-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_a" />
+                                <check enabled="true" name="CERT-INT33-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_c" />
+                                <check enabled="true" name="CERT-INT33-C_d" />
+                                <check enabled="true" name="CERT-INT33-C_e" />
+                                <check enabled="true" name="CERT-INT33-C_f" />
+                                <check enabled="true" name="CERT-INT33-C_g" />
+                                <check enabled="true" name="CERT-INT33-C_h" />
+                                <check enabled="true" name="CERT-INT33-C_i" />
+                                <check enabled="true" name="CERT-INT34-C_a" />
+                                <check enabled="true" name="CERT-INT34-C_b" />
+                                <check enabled="true" name="CERT-INT34-C_c" />
+                                <check enabled="true" name="CERT-INT35-C" />
+                                <check enabled="true" name="CERT-INT36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check enabled="true" name="CERT-MEM30-C_a" />
+                                <check enabled="true" name="CERT-MEM30-C_b" />
+                                <check enabled="true" name="CERT-MEM30-C_c" />
+                                <check enabled="true" name="CERT-MEM31-C" />
+                                <check enabled="true" name="CERT-MEM33-C_a" />
+                                <check enabled="true" name="CERT-MEM33-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_a" />
+                                <check enabled="true" name="CERT-MEM34-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_c" />
+                                <check enabled="true" name="CERT-MEM35-C_a" />
+                                <check enabled="true" name="CERT-MEM35-C_b" />
+                                <check enabled="true" name="CERT-MEM35-C_c" />
+                                <check enabled="true" name="CERT-MEM36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check enabled="true" name="CERT-MSC30-C" />
+                                <check enabled="true" name="CERT-MSC32-C" />
+                                <check enabled="false" name="CERT-MSC33-C" />
+                                <check enabled="true" name="CERT-MSC37-C" />
+                                <check enabled="true" name="CERT-MSC38-C" />
+                                <check enabled="true" name="CERT-MSC39-C" />
+                                <check enabled="true" name="CERT-MSC40-C_a" />
+                                <check enabled="true" name="CERT-MSC40-C_b" />
+                                <check enabled="true" name="CERT-MSC40-C_c" />
+                                <check enabled="true" name="CERT-MSC40-C_d" />
+                                <check enabled="false" name="CERT-MSC40-C_e" />
+                                <check enabled="true" name="CERT-MSC41-C_a" />
+                                <check enabled="true" name="CERT-MSC41-C_b" />
+                                <check enabled="true" name="CERT-MSC41-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check enabled="true" name="CERT-PRE31-C" />
+                                <check enabled="true" name="CERT-PRE32-C_a" />
+                                <check enabled="true" name="CERT-PRE32-C_b" />
                             </group>
                             <group enabled="true" name="CERT-SIG">
+                                <check enabled="true" name="CERT-SIG30-C" />
                                 <check enabled="true" name="CERT-SIG31-C" />
+                                <check enabled="true" name="CERT-SIG34-C" />
+                                <check enabled="true" name="CERT-SIG35-C" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check enabled="true" name="CERT-STR30-C" />
+                                <check enabled="true" name="CERT-STR31-C_a" />
+                                <check enabled="true" name="CERT-STR31-C_b" />
+                                <check enabled="true" name="CERT-STR31-C_c" />
+                                <check enabled="true" name="CERT-STR31-C_d" />
+                                <check enabled="true" name="CERT-STR31-C_e" />
+                                <check enabled="true" name="CERT-STR31-C_f" />
+                                <check enabled="true" name="CERT-STR31-C_g" />
+                                <check enabled="true" name="CERT-STR31-C_h" />
+                                <check enabled="true" name="CERT-STR32-C" />
+                                <check enabled="true" name="CERT-STR34-C" />
+                                <check enabled="true" name="CERT-STR37-C" />
                             </group>
                         </package>
                         <package enabled="false" name="SECURITY">
@@ -395,6 +596,7 @@
                                 <check enabled="false" name="MISRAC2004-2.4" />
                             </group>
                             <group enabled="true" name="MISRAC2004-5">
+                                <check enabled="true" name="MISRAC2004-5.1" />
                                 <check enabled="true" name="MISRAC2004-5.2" />
                                 <check enabled="true" name="MISRAC2004-5.3" />
                                 <check enabled="true" name="MISRAC2004-5.4" />
@@ -422,11 +624,8 @@
                                 <check enabled="true" name="MISRAC2004-8.7" />
                                 <check enabled="true" name="MISRAC2004-8.8_a" />
                                 <check enabled="true" name="MISRAC2004-8.8_b" />
-                                <check enabled="false" name="MISRAC2004-8.9" />
-                                <check enabled="true" name="MISRAC2004-8.12" />
-                            </group>
-                            <group enabled="true" name="MISRAC2004-8 10">
                                 <check enabled="true" name="MISRAC2004-8.10" />
+                                <check enabled="true" name="MISRAC2004-8.12" />
                             </group>
                             <group enabled="true" name="MISRAC2004-9">
                                 <check enabled="true" name="MISRAC2004-9.1_a" />
@@ -600,6 +799,7 @@
                                 <check enabled="false" name="MISRAC2012-Dir-4.11_h" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.11_i" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.12" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.13_a" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_b" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_c" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_d" />
@@ -607,6 +807,18 @@
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_f" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_g" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.13_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_a" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_b" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_c" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_d" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_e" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_f" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_g" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_i" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_j" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_l" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_m" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-1">
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_a" />
@@ -620,6 +832,7 @@
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_i" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_j" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_k" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_l" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_m" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_n" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_o" />
@@ -630,7 +843,8 @@
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_t" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_u" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_v" />
-                                <check enabled="true" name="MISRAC2012-Rule-1.3_w" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.4_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.4_b" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-2">
                                 <check enabled="true" name="MISRAC2012-Rule-2.1_a" />
@@ -678,11 +892,10 @@
                                 <check enabled="true" name="MISRAC2012-Rule-8.1" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.2_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.2_b" />
-                                <check enabled="true" name="MISRAC2012-Rule-8.3_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.3" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.4" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.5_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.5_b" />
-                                <check enabled="true" name="MISRAC2012-Rule-8.6" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.7" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.9_a" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.9_b" />
@@ -737,6 +950,8 @@
                                 <check enabled="false" name="MISRAC2012-Rule-12.1" />
                                 <check enabled="true" name="MISRAC2012-Rule-12.2" />
                                 <check enabled="false" name="MISRAC2012-Rule-12.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-12.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-12.5" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-13">
                                 <check enabled="true" name="MISRAC2012-Rule-13.1" />
@@ -819,6 +1034,8 @@
                                 <check enabled="true" name="MISRAC2012-Rule-20.4_c89" />
                                 <check enabled="true" name="MISRAC2012-Rule-20.4_c99" />
                                 <check enabled="false" name="MISRAC2012-Rule-20.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_b" />
                                 <check enabled="true" name="MISRAC2012-Rule-20.7" />
                                 <check enabled="false" name="MISRAC2012-Rule-20.10" />
                             </group>
@@ -836,6 +1053,22 @@
                                 <check enabled="true" name="MISRAC2012-Rule-21.11" />
                                 <check enabled="false" name="MISRAC2012-Rule-21.12_a" />
                                 <check enabled="false" name="MISRAC2012-Rule-21.12_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.13" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.14" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.15" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.16" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_f" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.20" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.21" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-22">
                                 <check enabled="true" name="MISRAC2012-Rule-22.1_a" />
@@ -848,6 +1081,11 @@
                                 <check enabled="true" name="MISRAC2012-Rule-22.5_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-22.5_b" />
                                 <check enabled="true" name="MISRAC2012-Rule-22.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.8" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.9" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.10" />
                             </group>
                         </package>
                         <package enabled="false" name="MISRAC++2008">
@@ -944,8 +1182,7 @@
                             </group>
                             <group enabled="true" name="MISRAC++2008-5-3">
                                 <check enabled="true" name="MISRAC++2008-5-3-1" />
-                                <check enabled="true" name="MISRAC++2008-5-3-2_a" />
-                                <check enabled="true" name="MISRAC++2008-5-3-2_b" />
+                                <check enabled="true" name="MISRAC++2008-5-3-2" />
                                 <check enabled="true" name="MISRAC++2008-5-3-3" />
                                 <check enabled="true" name="MISRAC++2008-5-3-4" />
                             </group>
@@ -984,9 +1221,11 @@
                             </group>
                             <group enabled="true" name="MISRAC++2008-6-5">
                                 <check enabled="true" name="MISRAC++2008-6-5-1_a" />
+                                <check enabled="true" name="MISRAC++2008-6-5-1_b" />
                                 <check enabled="true" name="MISRAC++2008-6-5-2" />
                                 <check enabled="true" name="MISRAC++2008-6-5-3" />
                                 <check enabled="true" name="MISRAC++2008-6-5-4" />
+                                <check enabled="true" name="MISRAC++2008-6-5-5" />
                                 <check enabled="true" name="MISRAC++2008-6-5-6" />
                             </group>
                             <group enabled="true" name="MISRAC++2008-6-6">
@@ -1195,9 +1434,9 @@
         <debug>0</debug>
         <settings>
             <name>C-STAT</name>
-            <archiveVersion>261</archiveVersion>
+            <archiveVersion>517</archiveVersion>
             <data>
-                <version>261</version>
+                <version>517</version>
                 <cstatargs>
                     <useExtraArgs>0</useExtraArgs>
                     <extraArgs></extraArgs>
@@ -1208,9 +1447,10 @@
                     <enableFalsePositives>0</enableFalsePositives>
                     <messagesLimitEnabled>1</messagesLimitEnabled>
                     <messagesLimit>100</messagesLimit>
+                    <outputDir>Release/C-STAT</outputDir>
                 </cstatargs>
                 <cstat_settings>
-                    <cstat_version>1.5.5</cstat_version>
+                    <cstat_version>2.5.2</cstat_version>
                     <checks_tree>
                         <package enabled="true" name="STDCHECKS">
                             <group enabled="true" name="ARR">
@@ -1490,15 +1730,215 @@
                             </group>
                         </package>
                         <package enabled="false" name="CERT">
+                            <group enabled="true" name="CERT-ARR">
+                                <check enabled="true" name="CERT-ARR30-C_a" />
+                                <check enabled="true" name="CERT-ARR30-C_b" />
+                                <check enabled="true" name="CERT-ARR30-C_c" />
+                                <check enabled="true" name="CERT-ARR30-C_d" />
+                                <check enabled="true" name="CERT-ARR30-C_e" />
+                                <check enabled="true" name="CERT-ARR30-C_f" />
+                                <check enabled="true" name="CERT-ARR30-C_g" />
+                                <check enabled="true" name="CERT-ARR30-C_h" />
+                                <check enabled="true" name="CERT-ARR30-C_i" />
+                                <check enabled="true" name="CERT-ARR30-C_j" />
+                                <check enabled="true" name="CERT-ARR32-C" />
+                                <check enabled="true" name="CERT-ARR36-C_a" />
+                                <check enabled="true" name="CERT-ARR36-C_b" />
+                                <check enabled="true" name="CERT-ARR37-C" />
+                                <check enabled="true" name="CERT-ARR38-C_a" />
+                                <check enabled="true" name="CERT-ARR38-C_b" />
+                                <check enabled="true" name="CERT-ARR38-C_c" />
+                                <check enabled="true" name="CERT-ARR38-C_d" />
+                                <check enabled="true" name="CERT-ARR38-C_e" />
+                                <check enabled="true" name="CERT-ARR38-C_f" />
+                                <check enabled="true" name="CERT-ARR39-C" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check enabled="true" name="CERT-DCL30-C_a" />
+                                <check enabled="true" name="CERT-DCL30-C_b" />
+                                <check enabled="true" name="CERT-DCL30-C_c" />
+                                <check enabled="true" name="CERT-DCL30-C_d" />
+                                <check enabled="true" name="CERT-DCL30-C_e" />
+                                <check enabled="true" name="CERT-DCL31-C" />
+                                <check enabled="true" name="CERT-DCL36-C" />
+                                <check enabled="true" name="CERT-DCL37-C_a" />
+                                <check enabled="true" name="CERT-DCL37-C_b" />
+                                <check enabled="false" name="CERT-DCL37-C_c" />
+                                <check enabled="true" name="CERT-DCL38-C" />
+                                <check enabled="true" name="CERT-DCL39-C" />
+                                <check enabled="true" name="CERT-DCL40-C" />
+                                <check enabled="true" name="CERT-DCL41-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check enabled="true" name="CERT-ENV30-C" />
+                                <check enabled="true" name="CERT-ENV31-C" />
+                                <check enabled="true" name="CERT-ENV32-C" />
+                                <check enabled="true" name="CERT-ENV33-C" />
+                                <check enabled="true" name="CERT-ENV34-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check enabled="true" name="CERT-ERR30-C_a" />
+                                <check enabled="true" name="CERT-ERR30-C_b" />
+                                <check enabled="true" name="CERT-ERR30-C_c" />
+                                <check enabled="true" name="CERT-ERR30-C_d" />
+                                <check enabled="true" name="CERT-ERR30-C_e" />
+                                <check enabled="true" name="CERT-ERR32-C" />
+                                <check enabled="true" name="CERT-ERR33-C_a" />
+                                <check enabled="true" name="CERT-ERR33-C_b" />
+                                <check enabled="true" name="CERT-ERR33-C_c" />
+                                <check enabled="true" name="CERT-ERR33-C_d" />
+                                <check enabled="true" name="CERT-ERR34-C_a" />
+                                <check enabled="true" name="CERT-ERR34-C_b" />
+                            </group>
                             <group enabled="true" name="CERT-EXP">
                                 <check enabled="true" name="CERT-EXP19-C" />
+                                <check enabled="true" name="CERT-EXP30-C_a" />
+                                <check enabled="true" name="CERT-EXP30-C_b" />
+                                <check enabled="true" name="CERT-EXP32-C" />
+                                <check enabled="true" name="CERT-EXP33-C_a" />
+                                <check enabled="true" name="CERT-EXP33-C_b" />
+                                <check enabled="true" name="CERT-EXP33-C_c" />
+                                <check enabled="true" name="CERT-EXP33-C_d" />
+                                <check enabled="true" name="CERT-EXP33-C_e" />
+                                <check enabled="true" name="CERT-EXP33-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_a" />
+                                <check enabled="true" name="CERT-EXP34-C_b" />
+                                <check enabled="true" name="CERT-EXP34-C_c" />
+                                <check enabled="true" name="CERT-EXP34-C_d" />
+                                <check enabled="true" name="CERT-EXP34-C_e" />
+                                <check enabled="true" name="CERT-EXP34-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_g" />
+                                <check enabled="true" name="CERT-EXP35-C" />
+                                <check enabled="true" name="CERT-EXP36-C_a" />
+                                <check enabled="true" name="CERT-EXP36-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_a" />
+                                <check enabled="true" name="CERT-EXP37-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_a" />
+                                <check enabled="true" name="CERT-EXP39-C_b" />
+                                <check enabled="true" name="CERT-EXP39-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_d" />
+                                <check enabled="true" name="CERT-EXP39-C_e" />
+                                <check enabled="true" name="CERT-EXP40-C_a" />
+                                <check enabled="true" name="CERT-EXP40-C_b" />
+                                <check enabled="true" name="CERT-EXP42-C" />
+                                <check enabled="true" name="CERT-EXP43-C_a" />
+                                <check enabled="true" name="CERT-EXP43-C_b" />
+                                <check enabled="true" name="CERT-EXP43-C_c" />
+                                <check enabled="true" name="CERT-EXP43-C_d" />
+                                <check enabled="true" name="CERT-EXP44-C" />
+                                <check enabled="true" name="CERT-EXP45-C" />
+                                <check enabled="true" name="CERT-EXP46-C" />
+                                <check enabled="true" name="CERT-EXP47-C_a" />
+                                <check enabled="true" name="CERT-EXP47-C_b" />
                             </group>
                             <group enabled="true" name="CERT-FIO">
+                                <check enabled="true" name="CERT-FIO30-C" />
+                                <check enabled="true" name="CERT-FIO32-C" />
+                                <check enabled="true" name="CERT-FIO34-C" />
                                 <check enabled="true" name="CERT-FIO37-C" />
                                 <check enabled="true" name="CERT-FIO38-C" />
+                                <check enabled="true" name="CERT-FIO39-C" />
+                                <check enabled="true" name="CERT-FIO40-C" />
+                                <check enabled="true" name="CERT-FIO41-C" />
+                                <check enabled="true" name="CERT-FIO42-C_a" />
+                                <check enabled="false" name="CERT-FIO42-C_b" />
+                                <check enabled="true" name="CERT-FIO44-C" />
+                                <check enabled="true" name="CERT-FIO45-C" />
+                                <check enabled="true" name="CERT-FIO46-C_a" />
+                                <check enabled="true" name="CERT-FIO46-C_b" />
+                                <check enabled="true" name="CERT-FIO46-C_c" />
+                                <check enabled="true" name="CERT-FIO47-C_a" />
+                                <check enabled="true" name="CERT-FIO47-C_b" />
+                                <check enabled="true" name="CERT-FIO47-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check enabled="true" name="CERT-FLP30-C_a" />
+                                <check enabled="true" name="CERT-FLP30-C_b" />
+                                <check enabled="true" name="CERT-FLP32-C_a" />
+                                <check enabled="true" name="CERT-FLP32-C_b" />
+                                <check enabled="true" name="CERT-FLP34-C" />
+                                <check enabled="true" name="CERT-FLP36-C" />
+                                <check enabled="true" name="CERT-FLP37-C" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check enabled="true" name="CERT-INT30-C_a" />
+                                <check enabled="false" name="CERT-INT30-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_a" />
+                                <check enabled="true" name="CERT-INT31-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_c" />
+                                <check enabled="true" name="CERT-INT32-C_a" />
+                                <check enabled="false" name="CERT-INT32-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_a" />
+                                <check enabled="true" name="CERT-INT33-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_c" />
+                                <check enabled="true" name="CERT-INT33-C_d" />
+                                <check enabled="true" name="CERT-INT33-C_e" />
+                                <check enabled="true" name="CERT-INT33-C_f" />
+                                <check enabled="true" name="CERT-INT33-C_g" />
+                                <check enabled="true" name="CERT-INT33-C_h" />
+                                <check enabled="true" name="CERT-INT33-C_i" />
+                                <check enabled="true" name="CERT-INT34-C_a" />
+                                <check enabled="true" name="CERT-INT34-C_b" />
+                                <check enabled="true" name="CERT-INT34-C_c" />
+                                <check enabled="true" name="CERT-INT35-C" />
+                                <check enabled="true" name="CERT-INT36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check enabled="true" name="CERT-MEM30-C_a" />
+                                <check enabled="true" name="CERT-MEM30-C_b" />
+                                <check enabled="true" name="CERT-MEM30-C_c" />
+                                <check enabled="true" name="CERT-MEM31-C" />
+                                <check enabled="true" name="CERT-MEM33-C_a" />
+                                <check enabled="true" name="CERT-MEM33-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_a" />
+                                <check enabled="true" name="CERT-MEM34-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_c" />
+                                <check enabled="true" name="CERT-MEM35-C_a" />
+                                <check enabled="true" name="CERT-MEM35-C_b" />
+                                <check enabled="true" name="CERT-MEM35-C_c" />
+                                <check enabled="true" name="CERT-MEM36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check enabled="true" name="CERT-MSC30-C" />
+                                <check enabled="true" name="CERT-MSC32-C" />
+                                <check enabled="false" name="CERT-MSC33-C" />
+                                <check enabled="true" name="CERT-MSC37-C" />
+                                <check enabled="true" name="CERT-MSC38-C" />
+                                <check enabled="true" name="CERT-MSC39-C" />
+                                <check enabled="true" name="CERT-MSC40-C_a" />
+                                <check enabled="true" name="CERT-MSC40-C_b" />
+                                <check enabled="true" name="CERT-MSC40-C_c" />
+                                <check enabled="true" name="CERT-MSC40-C_d" />
+                                <check enabled="false" name="CERT-MSC40-C_e" />
+                                <check enabled="true" name="CERT-MSC41-C_a" />
+                                <check enabled="true" name="CERT-MSC41-C_b" />
+                                <check enabled="true" name="CERT-MSC41-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check enabled="true" name="CERT-PRE31-C" />
+                                <check enabled="true" name="CERT-PRE32-C_a" />
+                                <check enabled="true" name="CERT-PRE32-C_b" />
                             </group>
                             <group enabled="true" name="CERT-SIG">
+                                <check enabled="true" name="CERT-SIG30-C" />
                                 <check enabled="true" name="CERT-SIG31-C" />
+                                <check enabled="true" name="CERT-SIG34-C" />
+                                <check enabled="true" name="CERT-SIG35-C" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check enabled="true" name="CERT-STR30-C" />
+                                <check enabled="true" name="CERT-STR31-C_a" />
+                                <check enabled="true" name="CERT-STR31-C_b" />
+                                <check enabled="true" name="CERT-STR31-C_c" />
+                                <check enabled="true" name="CERT-STR31-C_d" />
+                                <check enabled="true" name="CERT-STR31-C_e" />
+                                <check enabled="true" name="CERT-STR31-C_f" />
+                                <check enabled="true" name="CERT-STR31-C_g" />
+                                <check enabled="true" name="CERT-STR31-C_h" />
+                                <check enabled="true" name="CERT-STR32-C" />
+                                <check enabled="true" name="CERT-STR34-C" />
+                                <check enabled="true" name="CERT-STR37-C" />
                             </group>
                         </package>
                         <package enabled="false" name="SECURITY">
@@ -1581,6 +2021,7 @@
                                 <check enabled="false" name="MISRAC2004-2.4" />
                             </group>
                             <group enabled="true" name="MISRAC2004-5">
+                                <check enabled="true" name="MISRAC2004-5.1" />
                                 <check enabled="true" name="MISRAC2004-5.2" />
                                 <check enabled="true" name="MISRAC2004-5.3" />
                                 <check enabled="true" name="MISRAC2004-5.4" />
@@ -1608,11 +2049,8 @@
                                 <check enabled="true" name="MISRAC2004-8.7" />
                                 <check enabled="true" name="MISRAC2004-8.8_a" />
                                 <check enabled="true" name="MISRAC2004-8.8_b" />
-                                <check enabled="false" name="MISRAC2004-8.9" />
-                                <check enabled="true" name="MISRAC2004-8.12" />
-                            </group>
-                            <group enabled="true" name="MISRAC2004-8 10">
                                 <check enabled="true" name="MISRAC2004-8.10" />
+                                <check enabled="true" name="MISRAC2004-8.12" />
                             </group>
                             <group enabled="true" name="MISRAC2004-9">
                                 <check enabled="true" name="MISRAC2004-9.1_a" />
@@ -1786,6 +2224,7 @@
                                 <check enabled="false" name="MISRAC2012-Dir-4.11_h" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.11_i" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.12" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.13_a" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_b" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_c" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_d" />
@@ -1793,6 +2232,18 @@
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_f" />
                                 <check enabled="true" name="MISRAC2012-Dir-4.13_g" />
                                 <check enabled="false" name="MISRAC2012-Dir-4.13_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_a" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_b" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_c" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_d" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_e" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_f" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_g" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_i" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_j" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_l" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_m" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-1">
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_a" />
@@ -1806,6 +2257,7 @@
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_i" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_j" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_k" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_l" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_m" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_n" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_o" />
@@ -1816,7 +2268,8 @@
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_t" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_u" />
                                 <check enabled="true" name="MISRAC2012-Rule-1.3_v" />
-                                <check enabled="true" name="MISRAC2012-Rule-1.3_w" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.4_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.4_b" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-2">
                                 <check enabled="true" name="MISRAC2012-Rule-2.1_a" />
@@ -1864,11 +2317,10 @@
                                 <check enabled="true" name="MISRAC2012-Rule-8.1" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.2_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.2_b" />
-                                <check enabled="true" name="MISRAC2012-Rule-8.3_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.3" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.4" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.5_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-8.5_b" />
-                                <check enabled="true" name="MISRAC2012-Rule-8.6" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.7" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.9_a" />
                                 <check enabled="false" name="MISRAC2012-Rule-8.9_b" />
@@ -1923,6 +2375,8 @@
                                 <check enabled="false" name="MISRAC2012-Rule-12.1" />
                                 <check enabled="true" name="MISRAC2012-Rule-12.2" />
                                 <check enabled="false" name="MISRAC2012-Rule-12.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-12.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-12.5" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-13">
                                 <check enabled="true" name="MISRAC2012-Rule-13.1" />
@@ -2005,6 +2459,8 @@
                                 <check enabled="true" name="MISRAC2012-Rule-20.4_c89" />
                                 <check enabled="true" name="MISRAC2012-Rule-20.4_c99" />
                                 <check enabled="false" name="MISRAC2012-Rule-20.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_b" />
                                 <check enabled="true" name="MISRAC2012-Rule-20.7" />
                                 <check enabled="false" name="MISRAC2012-Rule-20.10" />
                             </group>
@@ -2022,6 +2478,22 @@
                                 <check enabled="true" name="MISRAC2012-Rule-21.11" />
                                 <check enabled="false" name="MISRAC2012-Rule-21.12_a" />
                                 <check enabled="false" name="MISRAC2012-Rule-21.12_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.13" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.14" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.15" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.16" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_f" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.20" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.21" />
                             </group>
                             <group enabled="true" name="MISRAC2012-Rule-22">
                                 <check enabled="true" name="MISRAC2012-Rule-22.1_a" />
@@ -2034,6 +2506,11 @@
                                 <check enabled="true" name="MISRAC2012-Rule-22.5_a" />
                                 <check enabled="true" name="MISRAC2012-Rule-22.5_b" />
                                 <check enabled="true" name="MISRAC2012-Rule-22.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.8" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.9" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.10" />
                             </group>
                         </package>
                         <package enabled="false" name="MISRAC++2008">
@@ -2130,8 +2607,7 @@
                             </group>
                             <group enabled="true" name="MISRAC++2008-5-3">
                                 <check enabled="true" name="MISRAC++2008-5-3-1" />
-                                <check enabled="true" name="MISRAC++2008-5-3-2_a" />
-                                <check enabled="true" name="MISRAC++2008-5-3-2_b" />
+                                <check enabled="true" name="MISRAC++2008-5-3-2" />
                                 <check enabled="true" name="MISRAC++2008-5-3-3" />
                                 <check enabled="true" name="MISRAC++2008-5-3-4" />
                             </group>
@@ -2170,9 +2646,11 @@
                             </group>
                             <group enabled="true" name="MISRAC++2008-6-5">
                                 <check enabled="true" name="MISRAC++2008-6-5-1_a" />
+                                <check enabled="true" name="MISRAC++2008-6-5-1_b" />
                                 <check enabled="true" name="MISRAC++2008-6-5-2" />
                                 <check enabled="true" name="MISRAC++2008-6-5-3" />
                                 <check enabled="true" name="MISRAC++2008-6-5-4" />
+                                <check enabled="true" name="MISRAC++2008-6-5-5" />
                                 <check enabled="true" name="MISRAC++2008-6-5-6" />
                             </group>
                             <group enabled="true" name="MISRAC++2008-6-6">
@@ -3101,6 +3579,36 @@
                 <name>$PROJ_DIR$\SDK\platform\devices\CVM014x\reg\wdg_reg.h</name>
             </file>
         </group>
+        <group>
+            <name>RTT</name>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_ASM_ARMv7M.S</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_printf.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
+            </file>
+        </group>
+        <group>
+            <name>TLE9461</name>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
+            </file>
+        </group>
         <file>
             <name>$PROJ_DIR$\src\main.c</name>
         </file>
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.bat b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.bat
index a48d290..14ee629 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.bat
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.bat
@@ -25,7 +25,7 @@ if not "%~1" == "" goto debugFile
 
 @echo on 
 
-"E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
+"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
 
 @echo off 
 goto end 
@@ -34,7 +34,7 @@ goto end
 
 @echo on 
 
-"E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" "--debug_file=%~1" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
+"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" "--debug_file=%~1" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
 
 @echo off 
 :end
\ No newline at end of file
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.ps1 b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.ps1
index 0cbd03f..f14ba67 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.ps1
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.cspy.ps1
@@ -23,9 +23,9 @@
 
 if ($debugfile -eq "")
 {
-& "E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
+& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
 }
 else
 {
-& "E:\IAR Systems\Embedded Workbench 8.3\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --debug_file=$debugfile --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
+& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.general.xcl" --debug_file=$debugfile --backend -f "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\settings\cva_bootloader_m0146.Debug.driver.xcl" 
 }
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.driver.xcl b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.driver.xcl
index 53e3f4d..ffd29cb 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.driver.xcl
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.driver.xcl
@@ -6,7 +6,7 @@
 
 "-p" 
 
-"E:\IAR Systems\Embedded Workbench 8.3\arm\CONFIG\debugger\CVAChip\CVM0144.ddf" 
+"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf" 
 
 "--semihosting" 
 
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.general.xcl b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.general.xcl
index 7d22687..e936804 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.general.xcl
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.Debug.general.xcl
@@ -1,10 +1,10 @@
-"E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armproc.dll" 
+"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll" 
 
-"E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armjlink2.dll" 
+"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armJLINK.dll" 
 
 "F:\FCB_project\RP-01\CODE\cva_bootloader_m0146\Debug_FLASH\Exe\bootloader_m146.out" 
 
---plugin="E:\IAR Systems\Embedded Workbench 8.3\arm\bin\armbat.dll" 
+--plugin="E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armbat.dll" 
 
 
 
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.dbgdt b/cva_bootloader_m0146/settings/cva_bootloader_m0146.dbgdt
index 6525d78..2f5c855 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.dbgdt
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.dbgdt
@@ -69,6 +69,10 @@
             <WIN_WATCH_3>34112</WIN_WATCH_3>
             <WIN_WATCH_4>34113</WIN_WATCH_4>
             <WIN_WORKSPACE>34114</WIN_WORKSPACE>
+            <TB_MAIN2>34115</TB_MAIN2>
+            <WIN_SLIDING_DATA_LOG>34116</WIN_SLIDING_DATA_LOG>
+            <WIN_SLIDING_FUNCTION_TRACE2>34117</WIN_SLIDING_FUNCTION_TRACE2>
+            <WIN_SLIDING_POWER_LOG>34118</WIN_SLIDING_POWER_LOG>
         </ChildIdMap>
         <Desktop>
             <IarPane-34048>
@@ -147,6 +151,7 @@
                     <item>0x24be</item>
                     <item>24be</item>
                 </DisasmHistory>
+                <kDisasmGotoHistoryKey />
                 <ShowCodeCoverage>1</ShowCodeCoverage>
                 <ShowInstrProfiling>1</ShowInstrProfiling>
             </IarPane-34065>
@@ -162,16 +167,16 @@
                 <RecentlyUsedMenus>1</RecentlyUsedMenus>
                 <MenuShadows>1</MenuShadows>
                 <ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
-                <CommandsUsage>2C0000000A00108600000B0000000C81000009000000568600000800000055840000010000000E810000010000005E860000010000001486000002000000058100000100000011860000060000004681000006000000</CommandsUsage>
+                <CommandsUsage>360000000F00108600000C00000026810000020000000D800000010000000C81000009000000568600000F000000148100000100000055840000010000000E810000010000005E860000010000000B8100000100000014860000020000000581000001000000118600000600000046810000080000000D81000002000000</CommandsUsage>
             </MFCToolBarParameters>
             <CommandManager>
                 <CommandsWithoutImages>0600008800000188000002880000038800000488000005880000</CommandsWithoutImages>
-                <MenuUserImages>0000</MenuUserImages>
+                <MenuUserImages>2D00048400004D000000048100009E000000268100002C000000158100001A000000239200000000000007E1000030000000318400005400000020810000AD0000000F810000A500000004E100002E00000000900000CA0000000C810000A20000000D8000000C00000001E100002B0000000981000067000000068400004F000000178100001C000000038400004C000000008400000B000000148100001900000030840000530000000E840000510000004492000096000000008100000E0000001F810000AC0000000E810000A40000001F9200009300000003E100002D0000002D920000950000000B810000A100000000E100002A000000D18400009200000041E100003A000000058400004E000000058100009F000000168100001B000000028400004B0000003284000055000000108400005200000005E100002F00000035E100008F00000002E10000850000000D810000A30000000A840000500000002C92000094000000</MenuUserImages>
             </CommandManager>
             <Pane-59393>
                 <ID>0</ID>
                 <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
-                <RectRecentDocked>0000000018030000000600002B030000</RectRecentDocked>
+                <RectRecentDocked>000000001A030000000600002B030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -210,8 +215,8 @@
             </BasePane-34053>
             <Pane--1>
                 <ID>4294967295</ID>
-                <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
-                <RectRecentDocked>EE010000320000002103000063020000</RectRecentDocked>
+                <RectRecentFloat>EE01000049000000210300007C020000</RectRecentFloat>
+                <RectRecentDocked>AB03000032000000DE04000065020000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -224,7 +229,7 @@
             <Pane-34054>
                 <ID>34054</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -237,7 +242,7 @@
             <Pane-34064>
                 <ID>34064</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -250,7 +255,7 @@
             <Pane-34070>
                 <ID>34070</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -263,7 +268,7 @@
             <Pane-34071>
                 <ID>34071</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -276,7 +281,7 @@
             <Pane-34072>
                 <ID>34072</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -289,7 +294,7 @@
             <Pane-34096>
                 <ID>34096</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -302,7 +307,7 @@
             <Pane-34109>
                 <ID>34109</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -328,7 +333,7 @@
             <Pane-34056>
                 <ID>34056</ID>
                 <RectRecentFloat>8D0300004D010000D90400007E030000</RectRecentFloat>
-                <RectRecentDocked>F20100004A0000001D03000049020000</RectRecentDocked>
+                <RectRecentDocked>AF0300004A000000DA0400004B020000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -336,7 +341,7 @@
                 <PinState>0</PinState>
             </Pane-34056>
             <BasePane-34056>
-                <IsVisible>1</IsVisible>
+                <IsVisible>0</IsVisible>
             </BasePane-34056>
             <IarPane-34056>
                 <col-names>
@@ -447,7 +452,7 @@
             <Pane-34065>
                 <ID>34065</ID>
                 <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
-                <RectRecentDocked>25030000320000000006000063020000</RectRecentDocked>
+                <RectRecentDocked>E2040000320000000006000065020000</RectRecentDocked>
                 <RecentFrameAlignment>16384</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -488,7 +493,7 @@
             <Pane-34068>
                 <ID>34068</ID>
                 <RectRecentFloat>A2020000C1020000A803000022040000</RectRecentFloat>
-                <RectRecentDocked>040000007F020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000081020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>16384</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -500,7 +505,7 @@
             </BasePane-34068>
             <IarPane-34068>
                 <col-names>
-                    <item>HardFault exception.</item>
+                    <item>_I0</item>
                 </col-names>
                 <col-widths>
                     <item>800</item>
@@ -760,7 +765,7 @@
             <Pane-34090>
                 <ID>34090</ID>
                 <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
-                <RectRecentDocked>F20100004A0000001D03000049020000</RectRecentDocked>
+                <RectRecentDocked>AF0300004A000000DA0400004B020000</RectRecentDocked>
                 <RecentFrameAlignment>16384</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -788,6 +793,8 @@
                     <item>udsObj</item>
                     <item>udsRecvBuf</item>
                 </QWatchHistory>
+                <right_justify>0</right_justify>
+                <kQExprHistoryKey />
             </IarPane-34090>
             <Pane-34091>
                 <ID>34091</ID>
@@ -1084,7 +1091,7 @@
             <Pane-34114>
                 <ID>34114</ID>
                 <RectRecentFloat>8D0300004D010000D90400007E030000</RectRecentFloat>
-                <RectRecentDocked>F20100004A0000001D03000049020000</RectRecentDocked>
+                <RectRecentDocked>AF0300004A000000DA0400004B020000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -1095,16 +1102,16 @@
                 <IsVisible>1</IsVisible>
             </BasePane-34114>
             <DockingManager-256>
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+                <RectRecentDocked>0000000000000000510300001A000000</RectRecentDocked>
+                <RecentFrameAlignment>8192</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>827</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34115>
+            <BasePane-34115>
+                <IsVisible>1</IsVisible>
+            </BasePane-34115>
         </Desktop>
     </WindowStorage>
 </Project>
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.dnx b/cva_bootloader_m0146/settings/cva_bootloader_m0146.dnx
index f7de347..8ca883a 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.dnx
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.dnx
@@ -15,19 +15,24 @@
         <WatchCond>_ 0</WatchCond>
         <Watch0>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch0>
         <Watch1>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch1>
-        <CStepIntDis>_ 0</CStepIntDis>
+        <jlinkResetStyle>12</jlinkResetStyle>
+        <jlinkResetStrategy>0</jlinkResetStrategy>
+        <TraceBufferSize>0x10000</TraceBufferSize>
+        <TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
+        <TracePortSize>0x4</TracePortSize>
         <LeaveTargetRunning>_ 0</LeaveTargetRunning>
+        <CStepIntDis>_ 0</CStepIntDis>
     </JLinkDriver>
     <DebugChecksum>
-        <Checksum>2109377255</Checksum>
+        <Checksum>3292783323</Checksum>
     </DebugChecksum>
     <Trace1>
         <Enabled>0</Enabled>
         <ShowSource>1</ShowSource>
     </Trace1>
     <Disassembly>
-        <InstrCount>0</InstrCount>
         <MixedMode>1</MixedMode>
+        <InstrCount>0</InstrCount>
     </Disassembly>
     <CodeCoverage>
         <Enabled>0</Enabled>
@@ -59,9 +64,43 @@
         <ITMportsLogFile>0</ITMportsLogFile>
         <ITMlogFile>$PROJ_DIR$\ITM.log</ITMlogFile>
     </SWOTraceHWSettings>
+    <LogFile>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+        <Category>_ 0</Category>
+    </LogFile>
+    <CallStackLog>
+        <Enabled>0</Enabled>
+    </CallStackLog>
+    <CallStackStripe>
+        <ShowTiming>1</ShowTiming>
+    </CallStackStripe>
+    <PlDriver>
+        <FirstRun>0</FirstRun>
+        <MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
+    </PlDriver>
+    <ArmDriver>
+        <EnableCache>0</EnableCache>
+        <EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
+    </ArmDriver>
+    <TerminalIO>
+        <InputSource>1</InputSource>
+        <InputMode>10</InputMode>
+        <Filename>$PROJ_DIR$\TermIOInput.txt</Filename>
+        <InputEcho>1</InputEcho>
+        <ShowReset>0</ShowReset>
+        <InputEncoding>2</InputEncoding>
+        <OutputEncoding>2</OutputEncoding>
+    </TerminalIO>
     <array_types>
         <Fmt0>uint8_t[2056]	4	0</Fmt0>
     </array_types>
+    <DriverProfiling>
+        <Enabled>0</Enabled>
+        <Mode>1</Mode>
+        <Graph>0</Graph>
+        <Symbiont>0</Symbiont>
+    </DriverProfiling>
     <Trace2>
         <Enabled>0</Enabled>
         <ShowSource>0</ShowSource>
@@ -77,30 +116,33 @@
         <EventSLEEP>0</EventSLEEP>
     </SWOTraceWindow>
     <PowerLog>
+        <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
         <Title_0>I0</Title_0>
         <Symbol_0>0 4 0</Symbol_0>
-        <LogEnabled>0</LogEnabled>
-        <GraphEnabled>0</GraphEnabled>
-        <ShowTimeLog>1</ShowTimeLog>
         <LiveEnabled>0</LiveEnabled>
         <LiveFile>PowerLogLive.log</LiveFile>
     </PowerLog>
     <DataLog>
-        <LogEnabled>0</LogEnabled>
         <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
         <ShowTimeLog>1</ShowTimeLog>
         <SumEnabled>0</SumEnabled>
         <ShowTimeSum>1</ShowTimeSum>
     </DataLog>
     <InterruptLog>
-        <LogEnabled>0</LogEnabled>
         <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
         <ShowTimeLog>1</ShowTimeLog>
         <SumEnabled>0</SumEnabled>
         <ShowTimeSum>1</ShowTimeSum>
         <SumSortOrder>0</SumSortOrder>
     </InterruptLog>
     <EventLog>
+        <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
         <Title_0>Ch3</Title_0>
         <Symbol_0>0 0 1</Symbol_0>
         <Title_1>Ch2</Title_1>
@@ -109,45 +151,26 @@
         <Symbol_2>0 0 1</Symbol_2>
         <Title_3>Ch0</Title_3>
         <Symbol_3>0 0 1</Symbol_3>
-        <LogEnabled>0</LogEnabled>
-        <GraphEnabled>0</GraphEnabled>
-        <ShowTimeLog>1</ShowTimeLog>
         <SumEnabled>0</SumEnabled>
         <ShowTimeSum>1</ShowTimeSum>
         <SumSortOrder>0</SumSortOrder>
     </EventLog>
-    <TermIOLog>
-        <LoggingEnabled>_ 0</LoggingEnabled>
-        <LogFile>_ ""</LogFile>
-    </TermIOLog>
-    <LogFile>
-        <LoggingEnabled>_ 0</LoggingEnabled>
-        <LogFile>_ ""</LogFile>
-        <Category>_ 0</Category>
-    </LogFile>
-    <DriverProfiling>
-        <Enabled>0</Enabled>
-        <Mode>1</Mode>
-        <Graph>0</Graph>
-        <Symbiont>0</Symbiont>
-    </DriverProfiling>
-    <CallStackLog>
-        <Enabled>0</Enabled>
-    </CallStackLog>
-    <CallStackStripe>
-        <ShowTiming>1</ShowTiming>
-    </CallStackStripe>
     <PowerProbe>
         <Frequency>10000</Frequency>
         <Probe0>I0</Probe0>
         <ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
     </PowerProbe>
+    <TermIOLog>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+    </TermIOLog>
     <DisassembleMode>
         <mode>0</mode>
     </DisassembleMode>
     <Breakpoints2>
         <Bp0>_ 0 "EMUL_CODE" "0x00002C66" 0 0 1 "" 0 "" 0</Bp0>
-        <Count>1</Count>
+        <Bp1>_ 1 "EMUL_CODE" "{$PROJ_DIR$\src\private_driver\drivers\clock\clock_drv.c}.2474.10" 0 0 1 "" 0 "" 0</Bp1>
+        <Count>2</Count>
     </Breakpoints2>
     <Aliases>
         <Count>0</Count>
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146.wsdt b/cva_bootloader_m0146/settings/cva_bootloader_m0146.wsdt
index ef94109..a9be1ef 100644
--- a/cva_bootloader_m0146/settings/cva_bootloader_m0146.wsdt
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146.wsdt
@@ -1,7 +1,9 @@
 <?xml version="1.0"?>
 <Workspace>
     <ConfigDictionary>
-        <CurrentConfigs />
+        <CurrentConfigs>
+            <Project>cva_bootloader_m0146/Debug</Project>
+        </CurrentConfigs>
     </ConfigDictionary>
     <WindowStorage>
         <Desktop>
@@ -9,7 +11,16 @@
                 <ColumnWidth0>19</ColumnWidth0>
                 <ColumnWidth1>1484</ColumnWidth1>
                 <FilterLevel>2</FilterLevel>
-                <LiveFile></LiveFile>
+                <col-names>
+                    <item>Log</item>
+                    <item>_I0</item>
+                </col-names>
+                <col-widths>
+                    <item>1503</item>
+                    <item>20</item>
+                </col-widths>
+                <DebugLogLevel>2</DebugLogLevel>
+                <LiveFile />
                 <LiveLogEnabled>0</LiveLogEnabled>
                 <LiveFilterLevel>-1</LiveFilterLevel>
             </IarPane-34048>
@@ -63,7 +74,10 @@
                     <Column2>30</Column2>
                     <Column3>30</Column3>
                 </ColumnWidths>
-                <NodeDict />
+                <NodeDict>
+                    <ExpandedNode>cva_bootloader_m0146</ExpandedNode>
+                    <ExpandedNode>cva_bootloader_m0146/src</ExpandedNode>
+                </NodeDict>
             </IarPane-34063>
             <ControlBarVersion>
                 <Major>14</Major>
@@ -77,16 +91,16 @@
                 <RecentlyUsedMenus>1</RecentlyUsedMenus>
                 <MenuShadows>1</MenuShadows>
                 <ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
-                <CommandsUsage>480000000C0010860000010000000D800000010000000C8100003C0000005686000008000000148100000100000055840000010000000E810000070000005E860000010000001486000002000000058100000200000011860000020000004681000001000000</CommandsUsage>
+                <CommandsUsage>900000001400268100000500000010860000010000000F8100000100000001E10000010000000C810000730000000D80000001000000038400000100000017810000010000005686000008000000558400000200000014810000010000005E860000010000000E8100000B000000E9800000010000000B8100000200000014860000020000001186000002000000058100000300000046810000010000000D81000002000000</CommandsUsage>
             </MFCToolBarParameters>
             <CommandManager>
-                <CommandsWithoutImages>56000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400003C8400003D840000408400004C8400003E8400004B8400004D8400003F8400003A8400003B8400005A8400005B840000D6840000D7840000D8840000D9840000DA840000DB840000DC840000DD840000DE840000DF840000E0840000E1840000E2840000EA840000248100000C84000033840000788400001184000020DE000021DE000026DE000028DE000023DE000022DE000024DE000027DE000025DE000020920000289200002992000037920000389200003492000033920000259200001E9200001D92000045DE000008800000098000000A8000000B8000000C800000158000000A81000001E800007784000007840000808C000044D5000055840000568400005984000012810000D284000053840000818400007D840000828400008384000084840000E88000000E8400003084000051840000</CommandsWithoutImages>
-                <MenuUserImages>2A00048400004C00000004810000180000002681000029000000158100001A000000239200000000000007E10000300000003184000053000000208100002B0000000F8100002300000004E100002E0000000C810000200000000D8000000C00000001E100002B000000098100001A000000068400004E000000178100001C000000038400004B000000008400000B00000014810000190000004492000010000000008100000E0000001F8100002A0000000E810000220000001F9200000D00000003E100002D0000002D9200000F0000000B8100001400000000E100002A000000D18400000C00000041E100003A000000058400004D0000000581000019000000168100001B000000028400004A0000003284000054000000108400005100000005E100002F00000035E100004000000002E100002C0000000D810000160000000A8400004F0000002C9200000E000000</MenuUserImages>
+                <CommandsWithoutImages>59000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400003C8400003D840000408400004C8400003E8400004B8400004D8400003F8400003A8400003B8400005A8400005B840000D6840000D7840000D8840000D9840000DA840000DB840000DC840000DD840000DE840000DF840000E0840000E1840000E2840000EA840000248100000C84000033840000788400001184000020DE000021DE000026DE000028DE000023DE000022DE000024DE000027DE000025DE000020920000289200002992000037920000389200003492000033920000259200001E9200001D92000045DE000008800000098000000A8000000B8000000C800000158000000A81000001E800007784000007840000808C000044D5000055840000568400005984000012810000D284000053840000818400007D840000828400008384000084840000E8800000E98400002DDE00001FDE00002CDE0000868400004D970000</CommandsWithoutImages>
+                <MenuUserImages>2E00048400004D00000015810000240000002681000076000000048100009E000000318400005400000007E100003F000000239200000000000000900000CA00000004E100003D0000000F81000022000000208100002A00000001E100003A0000000D800000180000000C8100001F000000068400004F0000000981000067000000038400004C000000178100002600000014810000230000000084000049000000008100001900000044920000960000000E84000051000000308400005300000003E100003C0000001F920000930000000E810000210000001F8100002900000000E10000390000000B8100001E0000002D92000095000000058400004E00000041E1000046000000D184000008000000028400004B0000001681000025000000058100009F00000010840000520000003284000055000000518400005700000005E100003E0000000A840000500000000D8100002000000002E100003B00000035E100008F0000002C92000094000000</MenuUserImages>
             </CommandManager>
             <Pane-59393>
                 <ID>0</ID>
                 <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
-                <RectRecentDocked>0000000018030000000600002B030000</RectRecentDocked>
+                <RectRecentDocked>000000001A030000000600002B030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -102,7 +116,7 @@
                 <RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked>
                 <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
-                <IsFloating>0</IsFloating>
+                <IsFloating>1</IsFloating>
                 <MRUWidth>32767</MRUWidth>
                 <PinState>0</PinState>
             </Pane-34051>
@@ -112,8 +126,8 @@
             <IarPane-34051 />
             <Pane--1>
                 <ID>4294967295</ID>
-                <RectRecentFloat>000000001D020000000600002F030000</RectRecentFloat>
-                <RectRecentDocked>00000000060200000006000018030000</RectRecentDocked>
+                <RectRecentFloat>000000001F0200000006000031030000</RectRecentFloat>
+                <RectRecentDocked>0000000008020000000600001A030000</RectRecentDocked>
                 <RecentFrameAlignment>4096</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -126,7 +140,7 @@
             <Pane-34052>
                 <ID>34052</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
                 <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
@@ -137,20 +151,33 @@
                 <IsVisible>1</IsVisible>
             </BasePane-34052>
             <IarPane-34052>
+                <col-names>
+                    <item>File</item>
+                    <item>Line</item>
+                    <item>Messages</item>
+                    <item>_I0</item>
+                </col-names>
+                <col-widths>
+                    <item>449</item>
+                    <item>40</item>
+                    <item>996</item>
+                    <item>20</item>
+                </col-widths>
                 <ColumnWidth0>24</ColumnWidth0>
                 <ColumnWidth1>1112</ColumnWidth1>
                 <ColumnWidth2>296</ColumnWidth2>
                 <ColumnWidth3>74</ColumnWidth3>
                 <FilterLevel>2</FilterLevel>
+                <BuildLogLevel>2</BuildLogLevel>
                 <LiveFile>F:\FCB_project\RP-01\REF\can_bootloader\cva_bootloader_m0146\BuildLog.log</LiveFile>
                 <LiveLogEnabled>0</LiveLogEnabled>
                 <LiveFilterLevel>-1</LiveFilterLevel>
             </IarPane-34052>
             <Pane-34048>
                 <ID>34048</ID>
-                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentFloat>E7020000A2020000E708000053030000</RectRecentFloat>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -162,8 +189,8 @@
             <Pane-34056>
                 <ID>34056</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -172,12 +199,20 @@
             <BasePane-34056>
                 <IsVisible>0</IsVisible>
             </BasePane-34056>
-            <IarPane-34056 />
+            <IarPane-34056>
+                <ColumnWidth0>533</ColumnWidth0>
+                <ColumnWidth1>76</ColumnWidth1>
+                <ColumnWidth2>914</ColumnWidth2>
+                <FilterLevel>2</FilterLevel>
+                <LiveFile />
+                <LiveLogEnabled>0</LiveLogEnabled>
+                <LiveFilterLevel>-1</LiveFilterLevel>
+            </IarPane-34056>
             <Pane-34057>
                 <ID>34057</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -186,12 +221,20 @@
             <BasePane-34057>
                 <IsVisible>0</IsVisible>
             </BasePane-34057>
-            <IarPane-34057 />
+            <IarPane-34057>
+                <ColumnWidth0>533</ColumnWidth0>
+                <ColumnWidth1>76</ColumnWidth1>
+                <ColumnWidth2>914</ColumnWidth2>
+                <FilterLevel>2</FilterLevel>
+                <LiveFile />
+                <LiveLogEnabled>0</LiveLogEnabled>
+                <LiveFilterLevel>-1</LiveFilterLevel>
+            </IarPane-34057>
             <Pane-34058>
                 <ID>34058</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -204,8 +247,8 @@
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                 <ID>34059</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -214,12 +257,20 @@
             <BasePane-34059>
                 <IsVisible>0</IsVisible>
             </BasePane-34059>
-            <IarPane-34059 />
+            <IarPane-34059>
+                <ColumnWidth0>533</ColumnWidth0>
+                <ColumnWidth1>76</ColumnWidth1>
+                <ColumnWidth2>914</ColumnWidth2>
+                <FilterLevel>2</FilterLevel>
+                <LiveFile />
+                <LiveLogEnabled>0</LiveLogEnabled>
+                <LiveFilterLevel>-1</LiveFilterLevel>
+            </IarPane-34059>
             <Pane-34062>
                 <ID>34062</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
-                <RectRecentDocked>040000001E020000FC050000FE020000</RectRecentDocked>
-                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RectRecentDocked>0400000020020000FC05000000030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
                 <RecentRowIndex>0</RecentRowIndex>
                 <IsFloating>0</IsFloating>
                 <MRUWidth>32767</MRUWidth>
@@ -228,7 +279,12 @@
             <BasePane-34062>
                 <IsVisible>0</IsVisible>
             </BasePane-34062>
-            <IarPane-34062 />
+            <IarPane-34062>
+                <FilterLevel>2</FilterLevel>
+                <LiveFile />
+                <LiveLogEnabled>0</LiveLogEnabled>
+                <LiveFilterLevel>-1</LiveFilterLevel>
+            </IarPane-34062>
             <Pane-34053>
                 <ID>34053</ID>
                 <RectRecentFloat>000000001700000080020000A8000000</RectRecentFloat>
@@ -242,14 +298,55 @@
             <BasePane-34053>
                 <IsVisible>0</IsVisible>
             </BasePane-34053>
-            <IarPane-34053 />
+            <IarPane-34053>
+                <cg_type>
+                    <item>2</item>
+                </cg_type>
+                <cg_symbol>
+                    <item />
+                </cg_symbol>
+                <cg_user>
+                    <item />
+                </cg_user>
+                <cg_display>
+                    <item>&lt;Right-click on a symbol in the editor to show a call graph&gt;</item>
+                </cg_display>
+                <cg_def_file>
+                    <item />
+                </cg_def_file>
+                <cg_def_line>
+                    <item>0</item>
+                </cg_def_line>
+                <cg_def_col>
+                    <item>0</item>
+                </cg_def_col>
+                <cg_call_file>
+                    <item />
+                </cg_call_file>
+                <cg_call_line>
+                    <item>0</item>
+                </cg_call_line>
+                <cg_call_col>
+                    <item>0</item>
+                </cg_call_col>
+                <col-names>
+                    <item>File</item>
+                    <item>Function</item>
+                    <item>Line</item>
+                </col-names>
+                <col-widths>
+                    <item>200</item>
+                    <item>700</item>
+                    <item>100</item>
+                </col-widths>
+            </IarPane-34053>
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+                <IsFloating>1</IsFloating>
                 <MRUWidth>32767</MRUWidth>
                 <PinState>0</PinState>
             </Pane-34054>
@@ -270,11 +367,27 @@
             <BasePane-34055>
                 <IsVisible>0</IsVisible>
             </BasePane-34055>
-            <IarPane-34055 />
+            <IarPane-34055>
+                <kCStatFilterHistoryKey />
+                <col-names>
+                    <item>Check</item>
+                    <item>File</item>
+                    <item>Line</item>
+                    <item>Message</item>
+                    <item>Severity</item>
+                </col-names>
+                <col-widths>
+                    <item>200</item>
+                    <item>200</item>
+                    <item>100</item>
+                    <item>500</item>
+                    <item>100</item>
+                </col-widths>
+            </IarPane-34055>
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                 <ID>34060</ID>
                 <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
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     </WindowStorage>
diff --git a/cva_bootloader_m0146/settings/cva_bootloader_m0146_EditorBookmarks.xml b/cva_bootloader_m0146/settings/cva_bootloader_m0146_EditorBookmarks.xml
new file mode 100644
index 0000000..38c3485
--- /dev/null
+++ b/cva_bootloader_m0146/settings/cva_bootloader_m0146_EditorBookmarks.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<userBookmarks />
diff --git a/cva_bootloader_m0146/src/RTT/README.txt b/cva_bootloader_m0146/src/RTT/README.txt
new file mode 100644
index 0000000..6ca82ce
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/README.txt
@@ -0,0 +1,23 @@
+README.txt for the SEGGER RTT Implementation Pack.
+
+MDK-ARM specifics:
+https://wiki.segger.com/Keil_MDK-ARM#RTT_in_uVision
+
+Included files:
+===============
+Root Directory
+  - Examples
+    - Main_RTT_InputEchoApp.c    - Sample application which echoes input on Channel 0.
+    - Main_RTT_MenuApp.c         - Sample application to demonstrate RTT bi-directional functionality.
+    - Main_RTT_PrintfTest.c      - Sample application to test RTT small printf implementation.
+    - Main_RTT_SpeedTestApp.c    - Sample application for measuring RTT performance. embOS needed.
+  - RTT
+    - SEGGER_RTT.c                - The RTT implementation.
+    - SEGGER_RTT.h                - Header for RTT implementation.
+    - SEGGER_RTT_Conf.h           - Pre-processor configuration for the RTT implementation.
+    - SEGGER_RTT_Printf.c         - Simple implementation of printf to write formatted strings via RTT.
+  - Syscalls
+    - RTT_Syscalls_GCC.c          - Low-level syscalls to retarget printf() to RTT with GCC / Newlib.
+    - RTT_Syscalls_IAR.c          - Low-level syscalls to retarget printf() to RTT with IAR compiler.
+    - RTT_Syscalls_KEIL.c         - Low-level syscalls to retarget printf() to RTT with KEIL/uVision compiler.
+    - RTT_Syscalls_SES.c          - Low-level syscalls to retarget printf() to RTT with SEGGER Embedded Studio.
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT.c b/cva_bootloader_m0146/src/RTT/SEGGER_RTT.c
new file mode 100644
index 0000000..baa496f
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT.c
@@ -0,0 +1,2078 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 7.22b                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT.c
+Purpose : Implementation of SEGGER real-time transfer (RTT) which
+          allows real-time communication on targets which support
+          debugger memory accesses while the CPU is running.
+Revision: $Rev: 22333 $
+
+Additional information:
+          Type "int" is assumed to be 32-bits in size
+          H->T    Host to target communication
+          T->H    Target to host communication
+
+          RTT channel 0 is always present and reserved for Terminal usage.
+          Name is fixed to "Terminal"
+
+          Effective buffer size: SizeOfBuffer - 1
+
+          WrOff == RdOff:       Buffer is empty
+          WrOff == (RdOff - 1): Buffer is full
+          WrOff >  RdOff:       Free space includes wrap-around
+          WrOff <  RdOff:       Used space includes wrap-around
+          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):  
+                                Buffer full and wrap-around after next byte
+
+
+----------------------------------------------------------------------
+*/
+
+#include "SEGGER_RTT.h"
+
+#include <string.h>                 // for memcpy
+
+/*********************************************************************
+*
+*       Configuration, default values
+*
+**********************************************************************
+*/
+
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #ifdef SEGGER_RTT_CB_ALIGN
+    #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGN
+    #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_CB_SECTION
+    #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_BUFFER_SECTION
+    #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGNMENT
+    #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_ALIGNMENT
+    #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
+#ifndef   BUFFER_SIZE_UP
+  #define BUFFER_SIZE_UP                                  1024  // Size of the buffer for terminal output of target, up to host
+#endif
+
+#ifndef   BUFFER_SIZE_DOWN
+  #define BUFFER_SIZE_DOWN                                16    // Size of the buffer for terminal input to target from host (Usually keyboard input)
+#endif
+
+#ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS                    2    // Number of up-buffers (T->H) available on this target
+#endif
+
+#ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS                  2    // Number of down-buffers (H->T) available on this target
+#endif
+
+#ifndef SEGGER_RTT_BUFFER_SECTION
+  #if defined(SEGGER_RTT_SECTION)
+    #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION
+  #endif
+#endif
+
+#ifndef   SEGGER_RTT_ALIGNMENT
+  #define SEGGER_RTT_ALIGNMENT                            SEGGER_RTT_CPU_CACHE_LINE_SIZE
+#endif
+
+#ifndef   SEGGER_RTT_BUFFER_ALIGNMENT
+  #define SEGGER_RTT_BUFFER_ALIGNMENT                     SEGGER_RTT_CPU_CACHE_LINE_SIZE
+#endif
+
+#ifndef   SEGGER_RTT_MODE_DEFAULT
+  #define SEGGER_RTT_MODE_DEFAULT                         SEGGER_RTT_MODE_NO_BLOCK_SKIP
+#endif
+
+#ifndef   SEGGER_RTT_LOCK
+  #define SEGGER_RTT_LOCK()
+#endif
+
+#ifndef   SEGGER_RTT_UNLOCK
+  #define SEGGER_RTT_UNLOCK()
+#endif
+
+#ifndef   STRLEN
+  #define STRLEN(a)                                       strlen((a))
+#endif
+
+#ifndef   STRCPY
+  #define STRCPY(pDest, pSrc)                             strcpy((pDest), (pSrc))
+#endif
+
+#ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
+  #define SEGGER_RTT_MEMCPY_USE_BYTELOOP                  0
+#endif
+
+#ifndef   SEGGER_RTT_MEMCPY
+  #ifdef  MEMCPY
+    #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      MEMCPY((pDest), (pSrc), (NumBytes))
+  #else
+    #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      memcpy((pDest), (pSrc), (NumBytes))
+  #endif
+#endif
+
+#ifndef   MIN
+  #define MIN(a, b)         (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef   MAX
+  #define MAX(a, b)         (((a) > (b)) ? (a) : (b))
+#endif
+//
+// For some environments, NULL may not be defined until certain headers are included
+//
+#ifndef NULL
+  #define NULL 0
+#endif
+
+/*********************************************************************
+*
+*       Defines, fixed
+*
+**********************************************************************
+*/
+#if (defined __ICCARM__) || (defined __ICCRX__)
+  #define RTT_PRAGMA(P) _Pragma(#P)
+#endif
+
+#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT
+  #if (defined __GNUC__)
+    #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment)))
+  #elif (defined __ICCARM__) || (defined __ICCRX__)
+    #define PRAGMA(A) _Pragma(#A)
+#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \
+                                  Var
+  #elif (defined __CC_ARM)
+    #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment)))
+  #else
+    #error "Alignment not supported for this compiler."
+  #endif
+#else
+  #define SEGGER_RTT_ALIGN(Var, Alignment) Var
+#endif
+
+#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION)
+  #if (defined __GNUC__)
+    #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var
+  #elif (defined __ICCARM__) || (defined __ICCRX__)
+#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \
+                                        Var
+  #elif (defined __CC_ARM)
+    #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init))  Var
+  #else
+    #error "Section placement not supported for this compiler."
+  #endif
+#else
+  #define SEGGER_RTT_PUT_SECTION(Var, Section) Var
+#endif
+
+#if SEGGER_RTT_ALIGNMENT
+  #define SEGGER_RTT_CB_ALIGN(Var)  SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT)
+#else
+  #define SEGGER_RTT_CB_ALIGN(Var)  Var
+#endif
+
+#if SEGGER_RTT_BUFFER_ALIGNMENT
+  #define SEGGER_RTT_BUFFER_ALIGN(Var)  SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT)
+#else
+  #define SEGGER_RTT_BUFFER_ALIGN(Var)  Var
+#endif
+
+
+#if defined(SEGGER_RTT_SECTION)
+  #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION)
+#else
+  #define SEGGER_RTT_PUT_CB_SECTION(Var) Var
+#endif
+
+#if defined(SEGGER_RTT_BUFFER_SECTION)
+  #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION)
+#else
+  #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var
+#endif
+
+/*********************************************************************
+*
+*       Static const data
+*
+**********************************************************************
+*/
+
+static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+//
+// RTT Control Block and allocate buffers for channel 0
+//
+SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT));
+SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer  [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]));
+SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)]));
+
+static unsigned char _ActiveTerminal;
+
+/*********************************************************************
+*
+*       Static functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _DoInit()
+*
+*  Function description
+*    Initializes the control block an buffers.
+*    May only be called via INIT() to avoid overriding settings.
+*
+*/
+#define INIT()  {                                                                                    \
+                  volatile SEGGER_RTT_CB* pRTTCBInit;                                                \
+                  pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \
+                  do {                                                                               \
+                    if (pRTTCBInit->acID[0] == '\0') {                                               \
+                      _DoInit();                                                                     \
+                    }                                                                                \
+                  } while (0);                                                                       \
+                }
+
+static void _DoInit(void) {
+  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
+  //
+  // Initialize control block
+  //
+  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
+  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
+  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
+  //
+  // Initialize up buffer 0
+  //
+  p->aUp[0].sName         = "Terminal";
+  p->aUp[0].pBuffer       = _acUpBuffer;
+  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
+  p->aUp[0].RdOff         = 0u;
+  p->aUp[0].WrOff         = 0u;
+  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
+  //
+  // Initialize down buffer 0
+  //
+  p->aDown[0].sName         = "Terminal";
+  p->aDown[0].pBuffer       = _acDownBuffer;
+  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
+  p->aDown[0].RdOff         = 0u;
+  p->aDown[0].WrOff         = 0u;
+  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
+  //
+  // Finish initialization of the control block.
+  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
+  // in initializer memory (usually flash) by J-Link
+  //
+  STRCPY((char*)&p->acID[7], "RTT");
+  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
+  STRCPY((char*)&p->acID[0], "SEGGER");
+  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
+  p->acID[6] = ' ';
+  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
+}
+
+/*********************************************************************
+*
+*       _WriteBlocking()
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT ring buffer
+*    and updates the associated write pointer which is periodically
+*    read by the host.
+*    The caller is responsible for managing the write chunk sizes as
+*    _WriteBlocking() will block until all data has been posted successfully.
+*
+*  Parameters
+*    pRing        Ring buffer to post to.
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Return value
+*    >= 0 - Number of bytes written into buffer.
+*/
+static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
+  unsigned NumBytesToWrite;
+  unsigned NumBytesWritten;
+  unsigned RdOff;
+  unsigned WrOff;
+  volatile char* pDst;
+  //
+  // Write data to buffer and handle wrap-around if necessary
+  //
+  NumBytesWritten = 0u;
+  WrOff = pRing->WrOff;
+  do {
+    RdOff = pRing->RdOff;                         // May be changed by host (debug probe) in the meantime
+    if (RdOff > WrOff) {
+      NumBytesToWrite = RdOff - WrOff - 1u;
+    } else {
+      NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u);
+    }
+    NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
+    NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    NumBytesWritten += NumBytesToWrite;
+    NumBytes        -= NumBytesToWrite;
+    WrOff           += NumBytesToWrite;
+    while (NumBytesToWrite--) {
+      *pDst++ = *pBuffer++;
+    };
+#else
+    SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite);
+    NumBytesWritten += NumBytesToWrite;
+    pBuffer         += NumBytesToWrite;
+    NumBytes        -= NumBytesToWrite;
+    WrOff           += NumBytesToWrite;
+#endif
+    if (WrOff == pRing->SizeOfBuffer) {
+      WrOff = 0u;
+    }
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff;
+  } while (NumBytes);
+  return NumBytesWritten;
+}
+
+/*********************************************************************
+*
+*       _WriteNoCheck()
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT ring buffer
+*    and updates the associated write pointer which is periodically
+*    read by the host.
+*    It is callers responsibility to make sure data actually fits in buffer.
+*
+*  Parameters
+*    pRing        Ring buffer to post to.
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Notes
+*    (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking
+*/
+static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
+  unsigned NumBytesAtOnce;
+  unsigned WrOff;
+  unsigned Rem;
+  volatile char* pDst;
+
+  WrOff = pRing->WrOff;
+  Rem = pRing->SizeOfBuffer - WrOff;
+  if (Rem > NumBytes) {
+    //
+    // All data fits before wrap around
+    //
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    WrOff += NumBytes;
+    while (NumBytes--) {
+      *pDst++ = *pData++;
+    };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff;
+#else
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff + NumBytes;
+#endif
+  } else {
+    //
+    // We reach the end of the buffer, so need to wrap around
+    //
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    NumBytesAtOnce = Rem;
+    while (NumBytesAtOnce--) {
+      *pDst++ = *pData++;
+    };
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+    NumBytesAtOnce = NumBytes - Rem;
+    while (NumBytesAtOnce--) {
+      *pDst++ = *pData++;
+    };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = NumBytes - Rem;
+#else
+    NumBytesAtOnce = Rem;
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
+    NumBytesAtOnce = NumBytes - Rem;
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = NumBytesAtOnce;
+#endif
+  }
+}
+
+/*********************************************************************
+*
+*       _PostTerminalSwitch()
+*
+*  Function description
+*    Switch terminal to the given terminal ID.  It is the caller's
+*    responsibility to ensure the terminal ID is correct and there is
+*    enough space in the buffer for this to complete successfully.
+*
+*  Parameters
+*    pRing        Ring buffer to post to.
+*    TerminalId   Terminal ID to switch to.
+*/
+static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) {
+  unsigned char ac[2];
+
+  ac[0] = 0xFFu;
+  ac[1] = _aTerminalId[TerminalId];  // Caller made already sure that TerminalId does not exceed our terminal limit
+  _WriteBlocking(pRing, (const char*)ac, 2u);
+}
+
+/*********************************************************************
+*
+*       _GetAvailWriteSpace()
+*
+*  Function description
+*    Returns the number of bytes that can be written to the ring
+*    buffer without blocking.
+*
+*  Parameters
+*    pRing        Ring buffer to check.
+*
+*  Return value
+*    Number of bytes that are free in the buffer.
+*/
+static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
+  unsigned RdOff;
+  unsigned WrOff;
+  unsigned r;
+  //
+  // Avoid warnings regarding volatile access order.  It's not a problem
+  // in this case, but dampen compiler enthusiasm.
+  //
+  RdOff = pRing->RdOff;
+  WrOff = pRing->WrOff;
+  if (RdOff <= WrOff) {
+    r = pRing->SizeOfBuffer - 1u - WrOff + RdOff;
+  } else {
+    r = RdOff - WrOff - 1u;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       Public code
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       SEGGER_RTT_ReadUpBufferNoLock()
+*
+*  Function description
+*    Reads characters from SEGGER real-time-terminal control block
+*    which have been previously stored by the application.
+*    Do not lock against interrupts and multiple access.
+*    Used to do the same operation that J-Link does, to transfer 
+*    RTT data via other channels, such as TCP/IP or UART.
+*
+*  Parameters
+*    BufferIndex  Index of Up-buffer to be used.
+*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to.
+*    BufferSize   Size of the target application buffer.
+*
+*  Return value
+*    Number of bytes that have been read.
+*
+*  Additional information
+*    This function must not be called when J-Link might also do RTT.
+*/
+unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) {
+  unsigned                NumBytesRem;
+  unsigned                NumBytesRead;
+  unsigned                RdOff;
+  unsigned                WrOff;
+  unsigned char*          pBuffer;
+  SEGGER_RTT_BUFFER_UP*   pRing;
+  volatile char*          pSrc;
+
+  INIT();
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pBuffer = (unsigned char*)pData;
+  RdOff = pRing->RdOff;
+  WrOff = pRing->WrOff;
+  NumBytesRead = 0u;
+  //
+  // Read from current read position to wrap-around of buffer, first
+  //
+  if (RdOff > WrOff) {
+    NumBytesRem = pRing->SizeOfBuffer - RdOff;
+    NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    NumBytesRead += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+    while (NumBytesRem--) {
+      *pBuffer++ = *pSrc++;
+    };
+#else
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
+    NumBytesRead += NumBytesRem;
+    pBuffer      += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+#endif
+    //
+    // Handle wrap-around of buffer
+    //
+    if (RdOff == pRing->SizeOfBuffer) {
+      RdOff = 0u;
+    }
+  }
+  //
+  // Read remaining items of buffer
+  //
+  NumBytesRem = WrOff - RdOff;
+  NumBytesRem = MIN(NumBytesRem, BufferSize);
+  if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    NumBytesRead += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+    while (NumBytesRem--) {
+      *pBuffer++ = *pSrc++;
+    };
+#else
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
+    NumBytesRead += NumBytesRem;
+    pBuffer      += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+#endif
+  }
+  //
+  // Update read offset of buffer
+  //
+  if (NumBytesRead) {
+    pRing->RdOff = RdOff;
+  }
+  //
+  return NumBytesRead;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_ReadNoLock()
+*
+*  Function description
+*    Reads characters from SEGGER real-time-terminal control block
+*    which have been previously stored by the host.
+*    Do not lock against interrupts and multiple access.
+*
+*  Parameters
+*    BufferIndex  Index of Down-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to.
+*    BufferSize   Size of the target application buffer.
+*
+*  Return value
+*    Number of bytes that have been read.
+*/
+unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) {
+  unsigned                NumBytesRem;
+  unsigned                NumBytesRead;
+  unsigned                RdOff;
+  unsigned                WrOff;
+  unsigned char*          pBuffer;
+  SEGGER_RTT_BUFFER_DOWN* pRing;
+  volatile char*          pSrc;
+  //
+  INIT();
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pBuffer = (unsigned char*)pData;
+  RdOff = pRing->RdOff;
+  WrOff = pRing->WrOff;
+  NumBytesRead = 0u;
+  //
+  // Read from current read position to wrap-around of buffer, first
+  //
+  if (RdOff > WrOff) {
+    NumBytesRem = pRing->SizeOfBuffer - RdOff;
+    NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    NumBytesRead += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+    while (NumBytesRem--) {
+      *pBuffer++ = *pSrc++;
+    };
+#else
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
+    NumBytesRead += NumBytesRem;
+    pBuffer      += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+#endif
+    //
+    // Handle wrap-around of buffer
+    //
+    if (RdOff == pRing->SizeOfBuffer) {
+      RdOff = 0u;
+    }
+  }
+  //
+  // Read remaining items of buffer
+  //
+  NumBytesRem = WrOff - RdOff;
+  NumBytesRem = MIN(NumBytesRem, BufferSize);
+  if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+    NumBytesRead += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+    while (NumBytesRem--) {
+      *pBuffer++ = *pSrc++;
+    };
+#else
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
+    NumBytesRead += NumBytesRem;
+    pBuffer      += NumBytesRem;
+    BufferSize   -= NumBytesRem;
+    RdOff        += NumBytesRem;
+#endif
+  }
+  if (NumBytesRead) {
+    pRing->RdOff = RdOff;
+  }
+  //
+  return NumBytesRead;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_ReadUpBuffer
+*
+*  Function description
+*    Reads characters from SEGGER real-time-terminal control block
+*    which have been previously stored by the application.
+*    Used to do the same operation that J-Link does, to transfer 
+*    RTT data via other channels, such as TCP/IP or UART.
+*
+*  Parameters
+*    BufferIndex  Index of Up-buffer to be used.
+*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to.
+*    BufferSize   Size of the target application buffer.
+*
+*  Return value
+*    Number of bytes that have been read.
+*
+*  Additional information
+*    This function must not be called when J-Link might also do RTT.
+*    This function locks against all other RTT operations. I.e. during
+*    the read operation, writing is also locked.
+*    If only one consumer reads from the up buffer, 
+*    call sEGGER_RTT_ReadUpBufferNoLock() instead.
+*/
+unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
+  unsigned NumBytesRead;
+
+  SEGGER_RTT_LOCK();
+  //
+  // Call the non-locking read function
+  //
+  NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize);
+  //
+  // Finish up.
+  //
+  SEGGER_RTT_UNLOCK();
+  //
+  return NumBytesRead;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_Read
+*
+*  Function description
+*    Reads characters from SEGGER real-time-terminal control block
+*    which have been previously stored by the host.
+*
+*  Parameters
+*    BufferIndex  Index of Down-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to.
+*    BufferSize   Size of the target application buffer.
+*
+*  Return value
+*    Number of bytes that have been read.
+*/
+unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
+  unsigned NumBytesRead;
+
+  SEGGER_RTT_LOCK();
+  //
+  // Call the non-locking read function
+  //
+  NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize);
+  //
+  // Finish up.
+  //
+  SEGGER_RTT_UNLOCK();
+  //
+  return NumBytesRead;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteWithOverwriteNoLock
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block.
+*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application 
+*    and overwrites data if the data does not fit into the buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Notes
+*    (1) If there is not enough space in the "Up"-buffer, data is overwritten.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link 
+*        connection reads RTT data.
+*/
+void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  const char*           pData;
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned              Avail;
+  volatile char*        pDst;
+  //
+  // Get "to-host" ring buffer and copy some elements into local variables.
+  //
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // Check if we will overwrite data and need to adjust the RdOff.
+  //
+  if (pRing->WrOff == pRing->RdOff) {
+    Avail = pRing->SizeOfBuffer - 1u;
+  } else if ( pRing->WrOff < pRing->RdOff) {
+    Avail = pRing->RdOff - pRing->WrOff - 1u;
+  } else {
+    Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer;
+  }
+  if (NumBytes > Avail) {
+    pRing->RdOff += (NumBytes - Avail);
+    while (pRing->RdOff >= pRing->SizeOfBuffer) {
+      pRing->RdOff -= pRing->SizeOfBuffer;
+    }
+  }
+  //
+  // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds
+  //
+  Avail = pRing->SizeOfBuffer - pRing->WrOff;
+  do {
+    if (Avail > NumBytes) {
+      //
+      // Last round
+      //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+      Avail = NumBytes;
+      while (NumBytes--) {
+        *pDst++ = *pData++;
+      };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff += Avail;
+#else
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff += NumBytes;
+#endif
+      break;
+    } else {
+      //
+      //  Wrap-around necessary, write until wrap-around and reset WrOff
+      //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
+      NumBytes -= Avail;
+      while (Avail--) {
+        *pDst++ = *pData++;
+      };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = 0;
+#else
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail);
+      pData += Avail;
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = 0;
+      NumBytes -= Avail;
+#endif
+      Avail = (pRing->SizeOfBuffer - 1);
+    }
+  } while (NumBytes);
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteSkipNoLock
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block which is then read by the host.
+*    SEGGER_RTT_WriteSkipNoLock does not lock the application and
+*    skips all data, if the data does not fit into the buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*                 MUST be > 0!!!
+*                 This is done for performance reasons, so no initial check has do be done.
+*
+*  Return value
+*    1: Data has been copied
+*    0: No space, data has not been copied
+*
+*  Notes
+*    (1) If there is not enough space in the "Up"-buffer, all data is dropped.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*/
+#if (RTT_USE_ASM == 0)
+unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  const char*           pData;
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned              Avail;
+  unsigned              RdOff;
+  unsigned              WrOff;
+  unsigned              Rem;
+  volatile char*        pDst;
+  //
+  // Cases:
+  //   1) RdOff <= WrOff => Space until wrap-around is sufficient
+  //   2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks)
+  //   3) RdOff <  WrOff => No space in buf
+  //   4) RdOff >  WrOff => Space is sufficient
+  //   5) RdOff >  WrOff => No space in buf
+  //
+  // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
+  //
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRing->RdOff;
+  WrOff = pRing->WrOff;
+  if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
+    Avail = pRing->SizeOfBuffer - WrOff - 1u;           // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
+    if (Avail >= NumBytes) {                            // Case 1)?
+CopyStraight:
+      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+      memcpy((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = WrOff + NumBytes;
+      return 1;
+    }
+    Avail += RdOff;                                     // Space incl. wrap-around
+    if (Avail >= NumBytes) {                            // Case 2? => If not, we have case 3) (does not fit)
+      Rem = pRing->SizeOfBuffer - WrOff;                // Space until end of buffer
+      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+      memcpy((void*)pDst, pData, Rem);                  // Copy 1st chunk
+      NumBytes -= Rem;
+      //
+      // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
+      // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element
+      // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks
+      // Therefore, check if 2nd memcpy is necessary at all
+      //
+      if (NumBytes) {
+        pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+        memcpy((void*)pDst, pData + Rem, NumBytes);
+      }
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = NumBytes;
+      return 1;
+    }
+  } else {                                             // Potential case 4)
+    Avail = RdOff - WrOff - 1u;
+    if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
+      goto CopyStraight;
+    }
+  }
+  return 0;     // No space in buffer
+}
+#endif
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteDownBufferNoLock
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block inside a <Down> buffer.
+*    SEGGER_RTT_WriteDownBufferNoLock does not lock the application.
+*    Used to do the same operation that J-Link does, to transfer 
+*    RTT data from other channels, such as TCP/IP or UART.
+*
+*  Parameters
+*    BufferIndex  Index of "Down"-buffer to be used.
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Down"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*
+*  Additional information
+*    This function must not be called when J-Link might also do RTT.
+*/
+unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  unsigned                Status;
+  unsigned                Avail;
+  const char*             pData;
+  SEGGER_RTT_BUFFER_UP*   pRing;
+  //
+  // Get "to-target" ring buffer.
+  // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link.
+  //
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // How we output depends upon the mode...
+  //
+  switch (pRing->Flags) {
+  case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
+    //
+    // If we are in skip mode and there is no space for the whole
+    // of this output, don't bother.
+    //
+    Avail = _GetAvailWriteSpace(pRing);
+    if (Avail < NumBytes) {
+      Status = 0u;
+    } else {
+      Status = NumBytes;
+      _WriteNoCheck(pRing, pData, NumBytes);
+    }
+    break;
+  case SEGGER_RTT_MODE_NO_BLOCK_TRIM:
+    //
+    // If we are in trim mode, trim to what we can output without blocking.
+    //
+    Avail = _GetAvailWriteSpace(pRing);
+    Status = Avail < NumBytes ? Avail : NumBytes;
+    _WriteNoCheck(pRing, pData, Status);
+    break;
+  case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL:
+    //
+    // If we are in blocking mode, output everything.
+    //
+    Status = _WriteBlocking(pRing, pData, NumBytes);
+    break;
+  default:
+    Status = 0u;
+    break;
+  }
+  //
+  // Finish up.
+  //
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteNoLock
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block which is then read by the host.
+*    SEGGER_RTT_WriteNoLock does not lock the application.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*/
+unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  unsigned              Status;
+  unsigned              Avail;
+  const char*           pData;
+  SEGGER_RTT_BUFFER_UP* pRing;
+  //
+  // Get "to-host" ring buffer.
+  //
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // How we output depends upon the mode...
+  //
+  switch (pRing->Flags) {
+  case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
+    //
+    // If we are in skip mode and there is no space for the whole
+    // of this output, don't bother.
+    //
+    Avail = _GetAvailWriteSpace(pRing);
+    if (Avail < NumBytes) {
+      Status = 0u;
+    } else {
+      Status = NumBytes;
+      _WriteNoCheck(pRing, pData, NumBytes);
+    }
+    break;
+  case SEGGER_RTT_MODE_NO_BLOCK_TRIM:
+    //
+    // If we are in trim mode, trim to what we can output without blocking.
+    //
+    Avail = _GetAvailWriteSpace(pRing);
+    Status = Avail < NumBytes ? Avail : NumBytes;
+    _WriteNoCheck(pRing, pData, Status);
+    break;
+  case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL:
+    //
+    // If we are in blocking mode, output everything.
+    //
+    Status = _WriteBlocking(pRing, pData, NumBytes);
+    break;
+  default:
+    Status = 0u;
+    break;
+  }
+  //
+  // Finish up.
+  //
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteDownBuffer
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT control block in a <Down> buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Down"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*
+*  Additional information
+*    This function must not be called when J-Link might also do RTT.
+*    This function locks against all other RTT operations. I.e. during
+*    the write operation, writing from the application is also locked.
+*    If only one consumer writes to the down buffer, 
+*    call SEGGER_RTT_WriteDownBufferNoLock() instead.
+*/
+unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  unsigned Status;
+
+  INIT();
+  SEGGER_RTT_LOCK();
+  Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
+  SEGGER_RTT_UNLOCK();
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_Write
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block which is then read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*/
+unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
+  unsigned Status;
+
+  INIT();
+  SEGGER_RTT_LOCK();
+  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
+  SEGGER_RTT_UNLOCK();
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteString
+*
+*  Function description
+*    Stores string in SEGGER RTT control block.
+*    This data is read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    s            Pointer to string.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*    (2) String passed to this function has to be \0 terminated
+*    (3) \0 termination character is *not* stored in RTT buffer
+*/
+unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) {
+  unsigned Len;
+
+  Len = STRLEN(s);
+  return SEGGER_RTT_Write(BufferIndex, s, Len);
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_PutCharSkipNoLock
+*
+*  Function description
+*    Stores a single character/byte in SEGGER RTT buffer.
+*    SEGGER_RTT_PutCharSkipNoLock does not lock the application and
+*    skips the byte, if it does not fit into the buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    c            Byte to be stored.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) If there is not enough space in the "Up"-buffer, the character is dropped.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*/
+
+unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned              WrOff;
+  unsigned              Status;
+  volatile char*        pDst;
+  //
+  // Get "to-host" ring buffer.
+  //
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // Get write position and handle wrap-around if necessary
+  //
+  WrOff = pRing->WrOff + 1;
+  if (WrOff == pRing->SizeOfBuffer) {
+    WrOff = 0;
+  }
+  //
+  // Output byte if free space is available
+  //
+  if (WrOff != pRing->RdOff) {
+    pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff;
+    Status = 1;
+  } else {
+    Status = 0;
+  }
+  //
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_PutCharSkip
+*
+*  Function description
+*    Stores a single character/byte in SEGGER RTT buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    c            Byte to be stored.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) If there is not enough space in the "Up"-buffer, the character is dropped.
+*/
+
+unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned              WrOff;
+  unsigned              Status;
+  volatile char*        pDst;
+  //
+  // Prepare
+  //
+  INIT();
+  SEGGER_RTT_LOCK();
+  //
+  // Get "to-host" ring buffer.
+  //
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // Get write position and handle wrap-around if necessary
+  //
+  WrOff = pRing->WrOff + 1;
+  if (WrOff == pRing->SizeOfBuffer) {
+    WrOff = 0;
+  }
+  //
+  // Output byte if free space is available
+  //
+  if (WrOff != pRing->RdOff) {
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff;
+    Status = 1;
+  } else {
+    Status = 0;
+  }
+  //
+  // Finish up.
+  //
+  SEGGER_RTT_UNLOCK();
+  //
+  return Status;
+}
+
+ /*********************************************************************
+*
+*       SEGGER_RTT_PutChar
+*
+*  Function description
+*    Stores a single character/byte in SEGGER RTT buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    c            Byte to be stored.
+*
+*  Return value
+*    Number of bytes which have been stored in the "Up"-buffer.
+*
+*  Notes
+*    (1) Data is stored according to buffer flags.
+*/
+
+unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned              WrOff;
+  unsigned              Status;
+  volatile char*        pDst;
+  //
+  // Prepare
+  //
+  INIT();
+  SEGGER_RTT_LOCK();
+  //
+  // Get "to-host" ring buffer.
+  //
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  //
+  // Get write position and handle wrap-around if necessary
+  //
+  WrOff = pRing->WrOff + 1;
+  if (WrOff == pRing->SizeOfBuffer) {
+    WrOff = 0;
+  }
+  //
+  // Wait for free space if mode is set to blocking
+  //
+  if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
+    while (WrOff == pRing->RdOff) {
+      ;
+    }
+  }
+  //
+  // Output byte if free space is available
+  //
+  if (WrOff != pRing->RdOff) {
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    pRing->WrOff = WrOff;
+    Status = 1;
+  } else {
+    Status = 0;
+  }
+  //
+  // Finish up.
+  //
+  SEGGER_RTT_UNLOCK();
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_GetKey
+*
+*  Function description
+*    Reads one character from the SEGGER RTT buffer.
+*    Host has previously stored data there.
+*
+*  Return value
+*    <  0 -   No character available (buffer empty).
+*    >= 0 -   Character which has been read. (Possible values: 0 - 255)
+*
+*  Notes
+*    (1) This function is only specified for accesses to RTT buffer 0.
+*/
+int SEGGER_RTT_GetKey(void) {
+  char c;
+  int r;
+
+  r = (int)SEGGER_RTT_Read(0u, &c, 1u);
+  if (r == 1) {
+    r = (int)(unsigned char)c;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WaitKey
+*
+*  Function description
+*    Waits until at least one character is avaible in the SEGGER RTT buffer.
+*    Once a character is available, it is read and this function returns.
+*
+*  Return value
+*    >=0 -   Character which has been read.
+*
+*  Notes
+*    (1) This function is only specified for accesses to RTT buffer 0
+*    (2) This function is blocking if no character is present in RTT buffer
+*/
+int SEGGER_RTT_WaitKey(void) {
+  int r;
+
+  do {
+    r = SEGGER_RTT_GetKey();
+  } while (r < 0);
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_HasKey
+*
+*  Function description
+*    Checks if at least one character for reading is available in the SEGGER RTT buffer.
+*
+*  Return value
+*    == 0 -     No characters are available to read.
+*    == 1 -     At least one character is available.
+*
+*  Notes
+*    (1) This function is only specified for accesses to RTT buffer 0
+*/
+int SEGGER_RTT_HasKey(void) {
+  SEGGER_RTT_BUFFER_DOWN* pRing;
+  unsigned RdOff;
+  int r;
+
+  INIT();
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRing->RdOff;
+  if (RdOff != pRing->WrOff) {
+    r = 1;
+  } else {
+    r = 0;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_HasData
+*
+*  Function description
+*    Check if there is data from the host in the given buffer.
+*
+*  Return value:
+*  ==0:  No data
+*  !=0:  Data in buffer
+*
+*/
+unsigned SEGGER_RTT_HasData(unsigned BufferIndex) {
+  SEGGER_RTT_BUFFER_DOWN* pRing;
+  unsigned                v;
+
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  v = pRing->WrOff;
+  return v - pRing->RdOff;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_HasDataUp
+*
+*  Function description
+*    Check if there is data remaining to be sent in the given buffer.
+*
+*  Return value:
+*  ==0:  No data
+*  !=0:  Data in buffer
+*
+*/
+unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned                v;
+
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  v = pRing->RdOff;
+  return pRing->WrOff - v;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_AllocDownBuffer
+*
+*  Function description
+*    Run-time configuration of the next down-buffer (H->T).
+*    The next buffer, which is not used yet is configured.
+*    This includes: Buffer address, size, name, flags, ...
+*
+*  Parameters
+*    sName        Pointer to a constant name string.
+*    pBuffer      Pointer to a buffer to be used.
+*    BufferSize   Size of the buffer.
+*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*
+*  Return value
+*    >= 0 - O.K. Buffer Index
+*     < 0 - Error
+*/
+int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
+  int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
+
+  INIT();
+  SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  BufferIndex = 0;
+  do {
+    if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) {
+      break;
+    }
+    BufferIndex++;
+  } while (BufferIndex < pRTTCB->MaxNumDownBuffers);
+  if (BufferIndex < pRTTCB->MaxNumDownBuffers) {
+    pRTTCB->aDown[BufferIndex].sName        = sName;
+    pRTTCB->aDown[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aDown[BufferIndex].RdOff        = 0u;
+    pRTTCB->aDown[BufferIndex].WrOff        = 0u;
+    pRTTCB->aDown[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+  } else {
+    BufferIndex = -1;
+  }
+  SEGGER_RTT_UNLOCK();
+  return BufferIndex;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_AllocUpBuffer
+*
+*  Function description
+*    Run-time configuration of the next up-buffer (T->H).
+*    The next buffer, which is not used yet is configured.
+*    This includes: Buffer address, size, name, flags, ...
+*
+*  Parameters
+*    sName        Pointer to a constant name string.
+*    pBuffer      Pointer to a buffer to be used.
+*    BufferSize   Size of the buffer.
+*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*
+*  Return value
+*    >= 0 - O.K. Buffer Index
+*     < 0 - Error
+*/
+int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
+  int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
+
+  INIT();
+  SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  BufferIndex = 0;
+  do {
+    if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) {
+      break;
+    }
+    BufferIndex++;
+  } while (BufferIndex < pRTTCB->MaxNumUpBuffers);
+  if (BufferIndex < pRTTCB->MaxNumUpBuffers) {
+    pRTTCB->aUp[BufferIndex].sName        = sName;
+    pRTTCB->aUp[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aUp[BufferIndex].RdOff        = 0u;
+    pRTTCB->aUp[BufferIndex].WrOff        = 0u;
+    pRTTCB->aUp[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+  } else {
+    BufferIndex = -1;
+  }
+  SEGGER_RTT_UNLOCK();
+  return BufferIndex;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_ConfigUpBuffer
+*
+*  Function description
+*    Run-time configuration of a specific up-buffer (T->H).
+*    Buffer to be configured is specified by index.
+*    This includes: Buffer address, size, name, flags, ...
+*
+*  Parameters
+*    BufferIndex  Index of the buffer to configure.
+*    sName        Pointer to a constant name string.
+*    pBuffer      Pointer to a buffer to be used.
+*    BufferSize   Size of the buffer.
+*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*
+*  Return value
+*    >= 0 - O.K.
+*     < 0 - Error
+*
+*  Additional information
+*    Buffer 0 is configured on compile-time.
+*    May only be called once per buffer.
+*    Buffer name and flags can be reconfigured using the appropriate functions.
+*/
+int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pUp = &pRTTCB->aUp[BufferIndex];
+    if (BufferIndex) {
+      pUp->sName        = sName;
+      pUp->pBuffer      = (char*)pBuffer;
+      pUp->SizeOfBuffer = BufferSize;
+      pUp->RdOff        = 0u;
+      pUp->WrOff        = 0u;
+    }
+    pUp->Flags          = Flags;
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_ConfigDownBuffer
+*
+*  Function description
+*    Run-time configuration of a specific down-buffer (H->T).
+*    Buffer to be configured is specified by index.
+*    This includes: Buffer address, size, name, flags, ...
+*
+*  Parameters
+*    BufferIndex  Index of the buffer to configure.
+*    sName        Pointer to a constant name string.
+*    pBuffer      Pointer to a buffer to be used.
+*    BufferSize   Size of the buffer.
+*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error
+*
+*  Additional information
+*    Buffer 0 is configured on compile-time.
+*    May only be called once per buffer.
+*    Buffer name and flags can be reconfigured using the appropriate functions.
+*/
+int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pDown = &pRTTCB->aDown[BufferIndex];
+    if (BufferIndex) {
+      pDown->sName        = sName;
+      pDown->pBuffer      = (char*)pBuffer;
+      pDown->SizeOfBuffer = BufferSize;
+      pDown->RdOff        = 0u;
+      pDown->WrOff        = 0u;
+    }
+    pDown->Flags          = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_SetNameUpBuffer
+*
+*  Function description
+*    Run-time configuration of a specific up-buffer name (T->H).
+*    Buffer to be configured is specified by index.
+*
+*  Parameters
+*    BufferIndex  Index of the buffer to renamed.
+*    sName        Pointer to a constant name string.
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error
+*/
+int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->sName = sName;
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_SetNameDownBuffer
+*
+*  Function description
+*    Run-time configuration of a specific Down-buffer name (T->H).
+*    Buffer to be configured is specified by index.
+*
+*  Parameters
+*    BufferIndex  Index of the buffer to renamed.
+*    sName        Pointer to a constant name string.
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error
+*/
+int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->sName = sName;
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_SetFlagsUpBuffer
+*
+*  Function description
+*    Run-time configuration of specific up-buffer flags (T->H).
+*    Buffer to be configured is specified by index.
+*
+*  Parameters
+*    BufferIndex  Index of the buffer.
+*    Flags        Flags to set for the buffer.
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error
+*/
+int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->Flags = Flags;
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_SetFlagsDownBuffer
+*
+*  Function description
+*    Run-time configuration of specific Down-buffer flags (T->H).
+*    Buffer to be configured is specified by index.
+*
+*  Parameters
+*    BufferIndex  Index of the buffer to renamed.
+*    Flags        Flags to set for the buffer.
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error
+*/
+int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) {
+  int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
+
+  INIT();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
+    SEGGER_RTT_LOCK();
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->Flags = Flags;
+    SEGGER_RTT_UNLOCK();
+    r =  0;
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_Init
+*
+*  Function description
+*    Initializes the RTT Control Block.
+*    Should be used in RAM targets, at start of the application.
+*
+*/
+void SEGGER_RTT_Init (void) {
+  _DoInit();
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_SetTerminal
+*
+*  Function description
+*    Sets the terminal to be used for output on channel 0.
+*
+*  Parameters
+*    TerminalId  Index of the terminal.
+*
+*  Return value
+*    >= 0  O.K.
+*     < 0  Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id)
+*
+*  Notes
+*    (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
+*/
+int SEGGER_RTT_SetTerminal (unsigned char TerminalId) {
+  unsigned char         ac[2];
+  SEGGER_RTT_BUFFER_UP* pRing;
+  unsigned Avail;
+  int r;
+
+  INIT();
+  r = 0;
+  ac[0] = 0xFFu;
+  if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels
+    ac[1] = _aTerminalId[TerminalId];
+    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    SEGGER_RTT_LOCK();                     // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
+    if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
+      _ActiveTerminal = TerminalId;
+      _WriteBlocking(pRing, (const char*)ac, 2u);
+    } else {                                                                            // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes
+      Avail = _GetAvailWriteSpace(pRing);
+      if (Avail >= 2) {
+        _ActiveTerminal = TerminalId;    // Only change active terminal in case of success
+        _WriteNoCheck(pRing, (const char*)ac, 2u);
+      } else {
+        r = -1;
+      }
+    }
+    SEGGER_RTT_UNLOCK();
+  } else {
+    r = -1;
+  }
+  return r;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_TerminalOut
+*
+*  Function description
+*    Writes a string to the given terminal
+*     without changing the terminal for channel 0.
+*
+*  Parameters
+*    TerminalId   Index of the terminal.
+*    s            String to be printed on the terminal.
+*
+*  Return value
+*    >= 0 - Number of bytes written.
+*     < 0 - Error.
+*
+*/
+int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
+  int                   Status;
+  unsigned              FragLen;
+  unsigned              Avail;
+  SEGGER_RTT_BUFFER_UP* pRing;
+  //
+  INIT();
+  //
+  // Validate terminal ID.
+  //
+  if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels
+    //
+    // Get "to-host" ring buffer.
+    //
+    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    //
+    // Need to be able to change terminal, write data, change back.
+    // Compute the fixed and variable sizes.
+    //
+    FragLen = STRLEN(s);
+    //
+    // How we output depends upon the mode...
+    //
+    SEGGER_RTT_LOCK();
+    Avail = _GetAvailWriteSpace(pRing);
+    switch (pRing->Flags & SEGGER_RTT_MODE_MASK) {
+    case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
+      //
+      // If we are in skip mode and there is no space for the whole
+      // of this output, don't bother switching terminals at all.
+      //
+      if (Avail < (FragLen + 4u)) {
+        Status = 0;
+      } else {
+        _PostTerminalSwitch(pRing, TerminalId);
+        Status = (int)_WriteBlocking(pRing, s, FragLen);
+        _PostTerminalSwitch(pRing, _ActiveTerminal);
+      }
+      break;
+    case SEGGER_RTT_MODE_NO_BLOCK_TRIM:
+      //
+      // If we are in trim mode and there is not enough space for everything,
+      // trim the output but always include the terminal switch.  If no room
+      // for terminal switch, skip that totally.
+      //
+      if (Avail < 4u) {
+        Status = -1;
+      } else {
+        _PostTerminalSwitch(pRing, TerminalId);
+        Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u));
+        _PostTerminalSwitch(pRing, _ActiveTerminal);
+      }
+      break;
+    case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL:
+      //
+      // If we are in blocking mode, output everything.
+      //
+      _PostTerminalSwitch(pRing, TerminalId);
+      Status = (int)_WriteBlocking(pRing, s, FragLen);
+      _PostTerminalSwitch(pRing, _ActiveTerminal);
+      break;
+    default:
+      Status = -1;
+      break;
+    }
+    //
+    // Finish up.
+    //
+    SEGGER_RTT_UNLOCK();
+  } else {
+    Status = -1;
+  }
+  return Status;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_GetAvailWriteSpace
+*
+*  Function description
+*    Returns the number of bytes available in the ring buffer.
+*
+*  Parameters
+*    BufferIndex  Index of the up buffer.
+*
+*  Return value
+*    Number of bytes that are free in the selected up buffer.
+*/
+unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  return _GetAvailWriteSpace(pRing);
+}
+
+
+/*********************************************************************
+*
+*       SEGGER_RTT_GetBytesInBuffer()
+*
+*  Function description
+*    Returns the number of bytes currently used in the up buffer.
+*
+*  Parameters
+*    BufferIndex  Index of the up buffer.
+*
+*  Return value
+*    Number of bytes that are used in the buffer.
+*/
+unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) {
+  unsigned RdOff;
+  unsigned WrOff;
+  unsigned r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  //
+  // Avoid warnings regarding volatile access order.  It's not a problem
+  // in this case, but dampen compiler enthusiasm.
+  //
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRTTCB->aUp[BufferIndex].RdOff;
+  WrOff = pRTTCB->aUp[BufferIndex].WrOff;
+  if (RdOff <= WrOff) {
+    r = WrOff - RdOff;
+  } else {
+    r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff);
+  }
+  return r;
+}
+
+/*************************** End of file ****************************/
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT.h b/cva_bootloader_m0146/src/RTT/SEGGER_RTT.h
new file mode 100644
index 0000000..f0eaa42
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT.h
@@ -0,0 +1,419 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 7.22b                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT.h
+Purpose : Implementation of SEGGER real-time transfer which allows
+          real-time communication on targets which support debugger 
+          memory accesses while the CPU is running.
+Revision: $Rev: 20869 $
+----------------------------------------------------------------------
+*/
+
+#ifndef SEGGER_RTT_H
+#define SEGGER_RTT_H
+
+#include "SEGGER_RTT_Conf.h"
+
+/*********************************************************************
+*
+*       Defines, defaults
+*
+**********************************************************************
+*/
+#ifndef RTT_USE_ASM
+  #if (defined __SES_ARM)                       // SEGGER Embedded Studio
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+  #elif (defined __CROSSWORKS_ARM)              // Rowley Crossworks
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+  #elif (defined __ARMCC_VERSION)               // ARM compiler
+		#if (__ARMCC_VERSION >= 6000000)						// ARM compiler V6.0 and later is clang based
+      #define _CC_HAS_RTT_ASM_SUPPORT 1
+		#else
+      #define _CC_HAS_RTT_ASM_SUPPORT 0
+		#endif
+  #elif (defined __GNUC__)                      // GCC
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+  #elif (defined __clang__)                     // Clang compiler
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+  #elif ((defined __IASMARM__) || (defined __ICCARM__))  // IAR assembler/compiler
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+  #else
+    #define _CC_HAS_RTT_ASM_SUPPORT 0
+  #endif
+  #if ((defined __IASMARM__) || (defined __ICCARM__))  // IAR assembler/compiler
+    //
+    // IAR assembler / compiler
+    //
+    #if (__VER__ < 6300000)
+      #define VOLATILE
+    #else
+      #define VOLATILE volatile
+    #endif
+    #if (defined __ARM7M__)                            // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM7M__)                      // Cortex-M3
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #endif
+    #endif
+    #if (defined __ARM7EM__)                           // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM7EM__)                     // Cortex-M4/M7
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_BASELINE__)                   // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM8M_BASELINE__)             // Cortex-M23
+        #define _CORE_HAS_RTT_ASM_SUPPORT 0
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_MAINLINE__)                   // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM8M_MAINLINE__)             // Cortex-M33
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+  #else
+    //
+    // GCC / Clang
+    //
+    #if (defined __ARM_ARCH_7M__)                 // Cortex-M3
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #else
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+    #endif
+  #endif
+  //
+  // If IDE and core support the ASM version, enable ASM version by default
+  //
+  #ifndef _CORE_HAS_RTT_ASM_SUPPORT
+    #define _CORE_HAS_RTT_ASM_SUPPORT 0              // Default for unknown cores
+  #endif
+  #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT)
+    #define RTT_USE_ASM                           (1)
+  #else
+    #define RTT_USE_ASM                           (0)
+  #endif
+#endif
+
+//
+// We need to know if a DMB is needed to make sure that on Cortex-M7 etc.
+// the order of accesses to the ring buffers is guaranteed
+// Needed for: Cortex-M7, Cortex-M23, Cortex-M33
+//
+#ifndef _CORE_NEEDS_DMB
+  #define _CORE_NEEDS_DMB 0
+#endif
+
+#ifndef RTT__DMB
+  #if _CORE_NEEDS_DMB
+    #error "Don't know how to place inline assembly for DMB"
+  #else
+    #define RTT__DMB()
+  #endif
+#endif
+
+#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0)   // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here
+#endif
+
+#ifndef SEGGER_RTT_UNCACHED_OFF
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #else
+    #define SEGGER_RTT_UNCACHED_OFF (0)
+  #endif
+#endif
+#if RTT_USE_ASM
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
+#ifndef SEGGER_RTT_ASM  // defined when SEGGER_RTT.h is included from assembly file
+#include <stdlib.h>
+#include <stdarg.h>
+
+/*********************************************************************
+*
+*       Defines, fixed
+*
+**********************************************************************
+*/
+
+//
+// Determine how much we must pad the control block to make it a multiple of a cache line in size
+// Assuming: U8 = 1B
+//           U16 = 2B
+//           U32 = 4B
+//           U8/U16/U32* = 4B
+//
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE    // Avoid division by zero in case we do not have any cache
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE)
+#else
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes)
+#endif
+#define SEGGER_RTT__CB_SIZE                              (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24))
+#define SEGGER_RTT__CB_PADDING                           (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE)
+
+/*********************************************************************
+*
+*       Types
+*
+**********************************************************************
+*/
+
+//
+// Description for a circular buffer (also called "ring buffer")
+// which is used as up-buffer (T->H)
+//
+typedef struct {
+  const     char*    sName;         // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
+            char*    pBuffer;       // Pointer to start of buffer
+            unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
+            unsigned WrOff;         // Position of next item to be written by either target.
+  volatile  unsigned RdOff;         // Position of next item to be read by host. Must be volatile since it may be modified by host.
+            unsigned Flags;         // Contains configuration flags
+} SEGGER_RTT_BUFFER_UP;
+
+//
+// Description for a circular buffer (also called "ring buffer")
+// which is used as down-buffer (H->T)
+//
+typedef struct {
+  const     char*    sName;         // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
+            char*    pBuffer;       // Pointer to start of buffer
+            unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
+  volatile  unsigned WrOff;         // Position of next item to be written by host. Must be volatile since it may be modified by host.
+            unsigned RdOff;         // Position of next item to be read by target (down-buffer).
+            unsigned Flags;         // Contains configuration flags
+} SEGGER_RTT_BUFFER_DOWN;
+
+//
+// RTT control block which describes the number of buffers available
+// as well as the configuration for each buffer
+//
+//
+typedef struct {
+  char                    acID[16];                                 // Initialized to "SEGGER RTT"
+  int                     MaxNumUpBuffers;                          // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2)
+  int                     MaxNumDownBuffers;                        // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
+  SEGGER_RTT_BUFFER_UP    aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS];       // Up buffers, transferring information up from target via debug probe to host
+  SEGGER_RTT_BUFFER_DOWN  aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS];   // Down buffers, transferring information down from host via debug probe to target
+#if SEGGER_RTT__CB_PADDING
+  unsigned char           aDummy[SEGGER_RTT__CB_PADDING];
+#endif
+} SEGGER_RTT_CB;
+
+/*********************************************************************
+*
+*       Global data
+*
+**********************************************************************
+*/
+extern SEGGER_RTT_CB _SEGGER_RTT;
+
+/*********************************************************************
+*
+*       RTT API functions
+*
+**********************************************************************
+*/
+#ifdef __cplusplus
+  extern "C" {
+#endif
+int          SEGGER_RTT_AllocDownBuffer         (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
+int          SEGGER_RTT_AllocUpBuffer           (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
+int          SEGGER_RTT_ConfigUpBuffer          (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
+int          SEGGER_RTT_ConfigDownBuffer        (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
+int          SEGGER_RTT_GetKey                  (void);
+unsigned     SEGGER_RTT_HasData                 (unsigned BufferIndex);
+int          SEGGER_RTT_HasKey                  (void);
+unsigned     SEGGER_RTT_HasDataUp               (unsigned BufferIndex);
+void         SEGGER_RTT_Init                    (void);
+unsigned     SEGGER_RTT_Read                    (unsigned BufferIndex,       void* pBuffer, unsigned BufferSize);
+unsigned     SEGGER_RTT_ReadNoLock              (unsigned BufferIndex,       void* pData,   unsigned BufferSize);
+int          SEGGER_RTT_SetNameDownBuffer       (unsigned BufferIndex, const char* sName);
+int          SEGGER_RTT_SetNameUpBuffer         (unsigned BufferIndex, const char* sName);
+int          SEGGER_RTT_SetFlagsDownBuffer      (unsigned BufferIndex, unsigned Flags);
+int          SEGGER_RTT_SetFlagsUpBuffer        (unsigned BufferIndex, unsigned Flags);
+int          SEGGER_RTT_WaitKey                 (void);
+unsigned     SEGGER_RTT_Write                   (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_WriteNoLock             (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_WriteSkipNoLock         (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_ASM_WriteSkipNoLock     (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_WriteString             (unsigned BufferIndex, const char* s);
+void         SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_PutChar                 (unsigned BufferIndex, char c);
+unsigned     SEGGER_RTT_PutCharSkip             (unsigned BufferIndex, char c);
+unsigned     SEGGER_RTT_PutCharSkipNoLock       (unsigned BufferIndex, char c);
+unsigned     SEGGER_RTT_GetAvailWriteSpace      (unsigned BufferIndex);
+unsigned     SEGGER_RTT_GetBytesInBuffer        (unsigned BufferIndex);
+//
+// Function macro for performance optimization
+//
+#define      SEGGER_RTT_HASDATA(n)       (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
+
+#if RTT_USE_ASM
+  #define SEGGER_RTT_WriteSkipNoLock  SEGGER_RTT_ASM_WriteSkipNoLock
+#endif
+
+/*********************************************************************
+*
+*       RTT transfer functions to send RTT data via other channels.
+*
+**********************************************************************
+*/
+unsigned     SEGGER_RTT_ReadUpBuffer            (unsigned BufferIndex, void* pBuffer, unsigned BufferSize);
+unsigned     SEGGER_RTT_ReadUpBufferNoLock      (unsigned BufferIndex, void* pData, unsigned BufferSize);
+unsigned     SEGGER_RTT_WriteDownBuffer         (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+unsigned     SEGGER_RTT_WriteDownBufferNoLock   (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
+
+#define      SEGGER_RTT_HASDATA_UP(n)    (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)   // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+
+/*********************************************************************
+*
+*       RTT "Terminal" API functions
+*
+**********************************************************************
+*/
+int     SEGGER_RTT_SetTerminal        (unsigned char TerminalId);
+int     SEGGER_RTT_TerminalOut        (unsigned char TerminalId, const char* s);
+
+/*********************************************************************
+*
+*       RTT printf functions (require SEGGER_RTT_printf.c)
+*
+**********************************************************************
+*/
+int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...);
+int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif // ifndef(SEGGER_RTT_ASM)
+
+/*********************************************************************
+*
+*       Defines
+*
+**********************************************************************
+*/
+
+//
+// Operating modes. Define behavior if buffer is full (not enough space for entire message)
+//
+#define SEGGER_RTT_MODE_NO_BLOCK_SKIP         (0)     // Skip. Do not block, output nothing. (Default)
+#define SEGGER_RTT_MODE_NO_BLOCK_TRIM         (1)     // Trim: Do not block, output as much as fits.
+#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL    (2)     // Block: Wait until there is space in the buffer.
+#define SEGGER_RTT_MODE_MASK                  (3)
+
+//
+// Control sequences, based on ANSI.
+// Can be used to control color, and clear the screen
+//
+#define RTT_CTRL_RESET                "\x1B[0m"         // Reset to default colors
+#define RTT_CTRL_CLEAR                "\x1B[2J"         // Clear screen, reposition cursor to top left
+
+#define RTT_CTRL_TEXT_BLACK           "\x1B[2;30m"
+#define RTT_CTRL_TEXT_RED             "\x1B[2;31m"
+#define RTT_CTRL_TEXT_GREEN           "\x1B[2;32m"
+#define RTT_CTRL_TEXT_YELLOW          "\x1B[2;33m"
+#define RTT_CTRL_TEXT_BLUE            "\x1B[2;34m"
+#define RTT_CTRL_TEXT_MAGENTA         "\x1B[2;35m"
+#define RTT_CTRL_TEXT_CYAN            "\x1B[2;36m"
+#define RTT_CTRL_TEXT_WHITE           "\x1B[2;37m"
+
+#define RTT_CTRL_TEXT_BRIGHT_BLACK    "\x1B[1;30m"
+#define RTT_CTRL_TEXT_BRIGHT_RED      "\x1B[1;31m"
+#define RTT_CTRL_TEXT_BRIGHT_GREEN    "\x1B[1;32m"
+#define RTT_CTRL_TEXT_BRIGHT_YELLOW   "\x1B[1;33m"
+#define RTT_CTRL_TEXT_BRIGHT_BLUE     "\x1B[1;34m"
+#define RTT_CTRL_TEXT_BRIGHT_MAGENTA  "\x1B[1;35m"
+#define RTT_CTRL_TEXT_BRIGHT_CYAN     "\x1B[1;36m"
+#define RTT_CTRL_TEXT_BRIGHT_WHITE    "\x1B[1;37m"
+
+#define RTT_CTRL_BG_BLACK             "\x1B[24;40m"
+#define RTT_CTRL_BG_RED               "\x1B[24;41m"
+#define RTT_CTRL_BG_GREEN             "\x1B[24;42m"
+#define RTT_CTRL_BG_YELLOW            "\x1B[24;43m"
+#define RTT_CTRL_BG_BLUE              "\x1B[24;44m"
+#define RTT_CTRL_BG_MAGENTA           "\x1B[24;45m"
+#define RTT_CTRL_BG_CYAN              "\x1B[24;46m"
+#define RTT_CTRL_BG_WHITE             "\x1B[24;47m"
+
+#define RTT_CTRL_BG_BRIGHT_BLACK      "\x1B[4;40m"
+#define RTT_CTRL_BG_BRIGHT_RED        "\x1B[4;41m"
+#define RTT_CTRL_BG_BRIGHT_GREEN      "\x1B[4;42m"
+#define RTT_CTRL_BG_BRIGHT_YELLOW     "\x1B[4;43m"
+#define RTT_CTRL_BG_BRIGHT_BLUE       "\x1B[4;44m"
+#define RTT_CTRL_BG_BRIGHT_MAGENTA    "\x1B[4;45m"
+#define RTT_CTRL_BG_BRIGHT_CYAN       "\x1B[4;46m"
+#define RTT_CTRL_BG_BRIGHT_WHITE      "\x1B[4;47m"
+
+
+#endif
+
+/*************************** End of file ****************************/
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT_ASM_ARMv7M.S b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_ASM_ARMv7M.S
new file mode 100644
index 0000000..cbbc52f
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_ASM_ARMv7M.S
@@ -0,0 +1,242 @@
+/*********************************************************************
+*                   (c) SEGGER Microcontroller GmbH                  *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : SEGGER_RTT_ASM_ARMv7M.S
+Purpose : Assembler implementation of RTT functions for ARMv7M
+
+Additional information:
+  This module is written to be assembler-independent and works with
+  GCC and clang (Embedded Studio) and IAR.
+*/
+
+#define SEGGER_RTT_ASM      // Used to control processed input from header file
+#include "SEGGER_RTT.h"
+
+/*********************************************************************
+*
+*       Defines, fixed
+*
+**********************************************************************
+*/
+
+#define _CCIAR   0
+#define _CCCLANG 1
+
+#if (defined __SES_ARM) || (defined __GNUC__) || (defined __clang__)
+  #define _CC_TYPE             _CCCLANG
+  #define _PUB_SYM             .global
+  #define _EXT_SYM             .extern
+  #define _END                 .end
+  #define _WEAK                .weak
+  #define _THUMB_FUNC          .thumb_func
+  #define _THUMB_CODE          .code 16
+  #define _WORD                .word
+  #define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax"
+  #define _ALIGN(Exp)          .align Exp 
+  #define _PLACE_LITS          .ltorg
+  #define _DATA_SECT_START 
+  #define _C_STARTUP           _start
+  #define _STACK_END           __stack_end__
+  #define _RAMFUNC
+  //
+  // .text     => Link to flash
+  // .fast     => Link to RAM
+  // OtherSect => Usually link to RAM
+  // Alignment is 2^x
+  //
+#elif defined (__IASMARM__)
+  #define _CC_TYPE             _CCIAR
+  #define _PUB_SYM             PUBLIC
+  #define _EXT_SYM             EXTERN
+  #define _END                 END
+  #define _WEAK                _WEAK
+  #define _THUMB_FUNC
+  #define _THUMB_CODE          THUMB
+  #define _WORD                DCD
+  #define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp)
+  #define _ALIGN(Exp)          alignrom Exp 
+  #define _PLACE_LITS
+  #define _DATA_SECT_START     DATA
+  #define _C_STARTUP           __iar_program_start
+  #define _STACK_END           sfe(CSTACK)
+  #define _RAMFUNC             SECTION_TYPE SHT_PROGBITS, SHF_WRITE | SHF_EXECINSTR
+  //
+  // .text     => Link to flash
+  // .textrw   => Link to RAM
+  // OtherSect => Usually link to RAM
+  // NOROOT    => Allows linker to throw away the function, if not referenced
+  // Alignment is 2^x
+  //
+#endif
+
+#if (_CC_TYPE == _CCIAR)
+        NAME SEGGER_RTT_ASM_ARMv7M
+#else
+        .syntax unified
+#endif
+
+#if defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
+        #define SHT_PROGBITS 0x1
+
+/*********************************************************************
+*
+*       Public / external symbols
+*
+**********************************************************************
+*/
+
+        _EXT_SYM __aeabi_memcpy
+        _EXT_SYM __aeabi_memcpy4
+        _EXT_SYM _SEGGER_RTT
+
+        _PUB_SYM SEGGER_RTT_ASM_WriteSkipNoLock
+
+/*********************************************************************
+*
+*       SEGGER_RTT_WriteSkipNoLock
+*
+*  Function description
+*    Stores a specified number of characters in SEGGER RTT
+*    control block which is then read by the host.
+*    SEGGER_RTT_WriteSkipNoLock does not lock the application and
+*    skips all data, if the data does not fit into the buffer.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
+*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
+*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
+*                 MUST be > 0!!!
+*                 This is done for performance reasons, so no initial check has do be done.
+*
+*  Return value
+*    1: Data has been copied
+*    0: No space, data has not been copied
+*
+*  Notes
+*    (1) If there is not enough space in the "Up"-buffer, all data is dropped.
+*    (2) For performance reasons this function does not call Init()
+*        and may only be called after RTT has been initialized.
+*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
+*/
+        _SECTION(.text, CODE, 2)
+        _ALIGN(2)
+        _THUMB_FUNC
+SEGGER_RTT_ASM_WriteSkipNoLock:   // unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pData, unsigned NumBytes) {
+        //
+        // Cases:
+        //   1) RdOff <= WrOff => Space until wrap-around is sufficient
+        //   2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks)
+        //   3) RdOff <  WrOff => No space in buf
+        //   4) RdOff >  WrOff => Space is sufficient
+        //   5) RdOff >  WrOff => No space in buf
+        //
+        // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
+        //
+        // Register usage:
+        //   R0 Temporary needed as RdOff, <Tmp> register later on
+        //   R1 pData
+        //   R2 <NumBytes>
+        //   R3 <Tmp> register. Hold free for subroutine calls
+        //   R4 <Rem>
+        //   R5 pRing->pBuffer
+        //   R6 pRing (Points to active struct SEGGER_RTT_BUFFER_DOWN)
+        //   R7 WrOff
+        //
+        PUSH     {R4-R7}
+        ADD      R3,R0,R0, LSL #+1
+        LDR.W    R0,=_SEGGER_RTT                 // pRing = &_SEGGER_RTT.aUp[BufferIndex];
+        ADD      R0,R0,R3, LSL #+3
+        ADD      R6,R0,#+24
+        LDR      R0,[R6, #+16]                   // RdOff = pRing->RdOff;
+        LDR      R7,[R6, #+12]                   // WrOff = pRing->WrOff;
+        LDR      R5,[R6, #+4]                    // pRing->pBuffer
+        CMP      R7,R0
+        BCC.N    _CheckCase4                     // if (RdOff <= WrOff) {                           => Case 1), 2) or 3)
+        //
+        // Handling for case 1, later on identical to case 4
+        //
+        LDR      R3,[R6, #+8]                    //  Avail = pRing->SizeOfBuffer - WrOff - 1u;      => Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
+        SUBS     R4,R3,R7                        // <Rem> (Used in case we jump into case 2 afterwards)
+        SUBS     R3,R4,#+1                       // <Avail>
+        CMP      R3,R2
+        BCC.N    _CheckCase2                     // if (Avail >= NumBytes) {  => Case 1)?
+_Case4:
+        ADDS     R5,R7,R5                        // pBuffer += WrOff
+        ADDS     R0,R2,R7                        // v = WrOff + NumBytes
+        //
+        // 2x unrolling for the copy loop that is used most of the time
+        // This is a special optimization for small SystemView packets and makes them even faster
+        //
+        _ALIGN(2)
+_LoopCopyStraight:                               // memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
+        LDRB     R3,[R1], #+1
+        STRB     R3,[R5], #+1                    // *pDest++ = *pSrc++
+        SUBS     R2,R2,#+1
+        BEQ      _CSDone
+        LDRB     R3,[R1], #+1
+        STRB     R3,[R5], #+1                    // *pDest++ = *pSrc++
+        SUBS     R2,R2,#+1
+        BNE      _LoopCopyStraight
+_CSDone:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
+        STR      R0,[R6, #+12]                   // pRing->WrOff = WrOff + NumBytes;
+        MOVS     R0,#+1
+        POP      {R4-R7}
+        BX       LR                              // Return 1
+_CheckCase2:
+        ADDS     R0,R0,R3                        // Avail += RdOff; => Space incl. wrap-around
+        CMP      R0,R2
+        BCC.N    _Case3                          // if (Avail >= NumBytes) {           => Case 2? => If not, we have case 3) (does not fit)
+        //
+        // Handling for case 2
+        //
+        ADDS     R0,R7,R5                        // v = pRing->pBuffer + WrOff => Do not change pRing->pBuffer here because 2nd chunk needs org. value
+        SUBS     R2,R2,R4                        // NumBytes -= Rem;  (Rem = pRing->SizeOfBuffer - WrOff; => Space until end of buffer)
+_LoopCopyBeforeWrapAround:                       // memcpy(pRing->pBuffer + WrOff, pData, Rem); => Copy 1st chunk
+        LDRB     R3,[R1], #+1
+        STRB     R3,[R0], #+1                    // *pDest++ = *pSrc++
+        SUBS     R4,R4,#+1
+        BNE      _LoopCopyBeforeWrapAround
+        //
+        // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
+        // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element
+        // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks
+        // Therefore, check if 2nd memcpy is necessary at all
+        //
+        ADDS     R4,R2,#+0                       // Save <NumBytes> (needed as counter in loop but must be written to <WrOff> after the loop). Also use this inst to update the flags to skip 2nd loop if possible
+        BEQ.N    _No2ChunkNeeded                 // if (NumBytes) {
+_LoopCopyAfterWrapAround:                        // memcpy(pRing->pBuffer, pData + Rem, NumBytes);
+        LDRB     R3,[R1], #+1                    // pData already points to the next src byte due to copy loop increment before this loop
+        STRB     R3,[R5], #+1                    // *pDest++ = *pSrc++
+        SUBS     R2,R2,#+1
+        BNE      _LoopCopyAfterWrapAround
+_No2ChunkNeeded:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
+        STR      R4,[R6, #+12]                   // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer
+        MOVS     R0,#+1
+        POP      {R4-R7}
+        BX       LR                              // Return 1
+_CheckCase4:
+        SUBS     R0,R0,R7
+        SUBS     R0,R0,#+1                       // Avail = RdOff - WrOff - 1u;
+        CMP      R0,R2
+        BCS.N    _Case4                          // if (Avail >= NumBytes) {      => Case 4) == 1) ? => If not, we have case 5) == 3) (does not fit)
+_Case3:
+        MOVS     R0,#+0
+        POP      {R4-R7}
+        BX       LR                              // Return 0
+        _PLACE_LITS
+
+#endif  // defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
+        _END
+
+/*************************** End of file ****************************/
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Conf.h b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Conf.h
new file mode 100644
index 0000000..f71e227
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Conf.h
@@ -0,0 +1,429 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 7.22b                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT_Conf.h
+Purpose : Implementation of SEGGER real-time transfer (RTT) which
+          allows real-time communication on targets which support
+          debugger memory accesses while the CPU is running.
+Revision: $Rev: 21386 $
+
+*/
+
+#ifndef SEGGER_RTT_CONF_H
+#define SEGGER_RTT_CONF_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+  #include <intrinsics.h>
+#endif
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+//
+// Take in and set to correct values for Cortex-A systems with CPU cache
+//
+//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE            (32)          // Largest cache line size (in bytes) in the current system
+//#define SEGGER_RTT_UNCACHED_OFF                   (0xFB000000)  // Address alias where RTT CB and buffers can be accessed uncached
+//
+// Most common case:
+// Up-channel 0: RTT
+// Up-channel 1: SystemView
+//
+#ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS             (3)     // Max. number of up-buffers (T->H) available on this target    (Default: 3)
+#endif
+//
+// Most common case:
+// Down-channel 0: RTT
+// Down-channel 1: SystemView
+//
+#ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
+  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS           (3)     // Max. number of down-buffers (H->T) available on this target  (Default: 3)
+#endif
+
+#ifndef   BUFFER_SIZE_UP
+  #define BUFFER_SIZE_UP                            (1024)  // Size of the buffer for terminal output of target, up to host (Default: 1k)
+#endif
+
+#ifndef   BUFFER_SIZE_DOWN
+  #define BUFFER_SIZE_DOWN                          (16)    // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
+#endif
+
+#ifndef   SEGGER_RTT_PRINTF_BUFFER_SIZE
+  #define SEGGER_RTT_PRINTF_BUFFER_SIZE             (64u)    // Size of buffer for RTT printf to bulk-send chars via RTT     (Default: 64)
+#endif
+
+#ifndef   SEGGER_RTT_MODE_DEFAULT
+  #define SEGGER_RTT_MODE_DEFAULT                   SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
+#endif
+
+/*********************************************************************
+*
+*       RTT memcpy configuration
+*
+*       memcpy() is good for large amounts of data,
+*       but the overhead is big for small amounts, which are usually stored via RTT.
+*       With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
+*
+*       SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
+*       This is may be required with memory access restrictions,
+*       such as on Cortex-A devices with MMU.
+*/
+#ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
+  #define SEGGER_RTT_MEMCPY_USE_BYTELOOP              0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
+#endif
+//
+// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
+//
+//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
+//  #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      SEGGER_memcpy((pDest), (pSrc), (NumBytes))
+//#endif
+
+//
+// Target is not allowed to perform other RTT operations while string still has not been stored completely.
+// Otherwise we would probably end up with a mixed string in the buffer.
+// If using  RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
+//
+// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
+// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
+// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
+// (Higher priority = lower priority number)
+// Default value for embOS: 128u
+// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
+// or define SEGGER_RTT_LOCK() to completely disable interrupts.
+//
+#ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY         (0x20)   // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for SEGGER Embedded Studio,
+*       Rowley CrossStudio and GCC
+*/
+#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
+  #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
+                                  __asm volatile ("mrs   %0, primask  \n\t"                         \
+                                                  "movs  r1, #1       \n\t"                         \
+                                                  "msr   primask, r1  \n\t"                         \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
+                                                  :                                                 \
+                                                  : "r1", "cc"                                      \
+                                                  );
+
+    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   primask, %0  \n\t"                         \
+                                                  :                                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
+                                                  :                                                 \
+                                                  );                                                \
+                                }
+  #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
+                                  __asm volatile ("mrs   %0, basepri  \n\t"                         \
+                                                  "mov   r1, %1       \n\t"                         \
+                                                  "msr   basepri, r1  \n\t"                         \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
+                                                  : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY)          \
+                                                  : "r1", "cc"                                      \
+                                                  );
+
+    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   basepri, %0  \n\t"                         \
+                                                  :                                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
+                                                  :                                                 \
+                                                  );                                                \
+                                }
+
+  #elif defined(__ARM_ARCH_7A__)
+    #define SEGGER_RTT_LOCK() {                                                \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
+                                 __asm volatile ("mrs r1, CPSR \n\t"           \
+                                                 "mov %0, r1 \n\t"             \
+                                                 "orr r1, r1, #0xC0 \n\t"      \
+                                                 "msr CPSR_c, r1 \n\t"         \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
+                                                 :                             \
+                                                 : "r1", "cc"                  \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"              \
+                                                "mrs r1, CPSR \n\t"            \
+                                                "bic r1, r1, #0xC0 \n\t"       \
+                                                "and r0, r0, #0xC0 \n\t"       \
+                                                "orr r1, r1, r0 \n\t"          \
+                                                "msr CPSR_c, r1 \n\t"          \
+                                                :                              \
+                                                : "r" (_SEGGER_RTT__LockState)              \
+                                                : "r0", "r1", "cc"             \
+                                                );                             \
+                            }
+  #elif defined(__riscv) || defined(__riscv_xlen)
+    #define SEGGER_RTT_LOCK()  {                                               \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
+                                 __asm volatile ("csrr  %0, mstatus  \n\t"     \
+                                                 "csrci mstatus, 8   \n\t"     \
+                                                 "andi  %0, %0,  8   \n\t"     \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
+                                                 :                             \
+                                                 :                             \
+                                                );
+
+  #define SEGGER_RTT_UNLOCK()    __asm volatile ("csrr  a1, mstatus  \n\t"     \
+                                                 "or    %0, %0, a1   \n\t"     \
+                                                 "csrs  mstatus, %0  \n\t"     \
+                                                 :                             \
+                                                 : "r"  (_SEGGER_RTT__LockState)            \
+                                                 : "a1"                        \
+                                                );                             \
+                               }
+  #else
+    #define SEGGER_RTT_LOCK()
+    #define SEGGER_RTT_UNLOCK()
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR EWARM
+*/
+#ifdef __ICCARM__
+  #if (defined (__ARM6M__)          && (__CORE__ == __ARM6M__))             ||                      \
+      (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
+                                  __set_PRIMASK(1);
+
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__ARM7EM__)         && (__CORE__ == __ARM7EM__))          ||                      \
+        (defined (__ARM7M__)          && (__CORE__ == __ARM7M__))           ||                      \
+        (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))  ||                      \
+        (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_BASEPRI();                                      \
+                                  __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+
+    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__))                    ||                      \
+        (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
+    #define SEGGER_RTT_LOCK() {                                                                     \
+                                 unsigned int _SEGGER_RTT__LockState;                                            \
+                                 __asm volatile ("mrs r1, CPSR \n\t"                                \
+                                                 "mov %0, r1 \n\t"                                  \
+                                                 "orr r1, r1, #0xC0 \n\t"                           \
+                                                 "msr CPSR_c, r1 \n\t"                              \
+                                                 : "=r" (_SEGGER_RTT__LockState)                                 \
+                                                 :                                                  \
+                                                 : "r1", "cc"                                       \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"                                   \
+                                                "mrs r1, CPSR \n\t"                                 \
+                                                "bic r1, r1, #0xC0 \n\t"                            \
+                                                "and r0, r0, #0xC0 \n\t"                            \
+                                                "orr r1, r1, r0 \n\t"                               \
+                                                "msr CPSR_c, r1 \n\t"                               \
+                                                :                                                   \
+                                                : "r" (_SEGGER_RTT__LockState)                                   \
+                                                : "r0", "r1", "cc"                                  \
+                                                );                                                  \
+                            }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR RX
+*/
+#ifdef __ICCRX__
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
+                                __disable_interrupt();
+
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for IAR RL78
+*/
+#ifdef __ICCRL78__
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                __istate_t _SEGGER_RTT__LockState;                                               \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
+                                __disable_interrupt();
+
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for KEIL ARM
+*/
+#ifdef __CC_ARM
+  #if (defined __TARGET_ARCH_6S_M)
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask");                 \
+                                  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK;                                              \
+                                  _SEGGER_RTT__PRIMASK = 1u;                                                     \
+                                  __schedule_barrier();
+
+    #define SEGGER_RTT_UNLOCK()   _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState;                                              \
+                                  __schedule_barrier();                                             \
+                                }
+  #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char BASEPRI __asm( "basepri");                 \
+                                  _SEGGER_RTT__LockState = BASEPRI;                                              \
+                                  BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY;                      \
+                                  __schedule_barrier();
+
+    #define SEGGER_RTT_UNLOCK()   BASEPRI = _SEGGER_RTT__LockState;                                              \
+                                  __schedule_barrier();                                             \
+                                }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for TI ARM
+*/
+#ifdef __TI_ARM__
+  #if defined (__TI_ARM_V6M0__)
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
+                                  __set_PRIMASK(1);
+
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
+                                }
+  #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
+    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
+      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
+    #endif
+    #define SEGGER_RTT_LOCK()   {                                                                   \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+
+    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(_SEGGER_RTT__LockState);                               \
+                                }
+  #endif
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for CCRX
+*/
+#ifdef __RX
+  #include <machine.h>
+  #define SEGGER_RTT_LOCK()   {                                                                     \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = get_psw() & 0x010000;                                   \
+                                clrpsw_i();
+
+  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | _SEGGER_RTT__LockState);                                     \
+                              }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration for embOS Simulation on Windows
+*       (Can also be used for generic RTT locking with embOS)
+*/
+#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
+
+void OS_SIM_EnterCriticalSection(void);
+void OS_SIM_LeaveCriticalSection(void);
+
+#define SEGGER_RTT_LOCK()       {                                                                   \
+                                  OS_SIM_EnterCriticalSection();
+
+#define SEGGER_RTT_UNLOCK()       OS_SIM_LeaveCriticalSection();                                    \
+                                }
+#endif
+
+/*********************************************************************
+*
+*       RTT lock configuration fallback
+*/
+#ifndef   SEGGER_RTT_LOCK
+  #define SEGGER_RTT_LOCK()                // Lock RTT (nestable)   (i.e. disable interrupts)
+#endif
+
+#ifndef   SEGGER_RTT_UNLOCK
+  #define SEGGER_RTT_UNLOCK()              // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
+#endif
+
+#endif
+/*************************** End of file ****************************/
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Syscalls_GCC.c b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Syscalls_GCC.c
new file mode 100644
index 0000000..f0688f7
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_Syscalls_GCC.c
@@ -0,0 +1,125 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 7.22b                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT_Syscalls_GCC.c
+Purpose : Low-level functions for using printf() via RTT in GCC.
+          To use RTT for printf output, include this file in your 
+          application.
+Revision: $Rev: 20755 $
+----------------------------------------------------------------------
+*/
+#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) && !(defined __ARMCC_VERSION) && !(defined __CC_ARM)
+
+#include <reent.h>  // required for _write_r
+#include "SEGGER_RTT.h"
+
+
+/*********************************************************************
+*
+*       Types
+*
+**********************************************************************
+*/
+//
+// If necessary define the _reent struct
+// to match the one passed by the used standard library.
+//
+struct _reent;
+
+/*********************************************************************
+*
+*       Function prototypes
+*
+**********************************************************************
+*/
+_ssize_t _write  (int file, const void *ptr, size_t len);
+_ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len);
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _write()
+*
+* Function description
+*   Low-level write function.
+*   libc subroutines will use this system routine for output to all files,
+*   including stdout.
+*   Write data via RTT.
+*/
+_ssize_t _write(int file, const void *ptr, size_t len) {
+  (void) file;  /* Not used, avoid warning */
+  SEGGER_RTT_Write(0, ptr, len);
+  return len;
+}
+
+/*********************************************************************
+*
+*       _write_r()
+*
+* Function description
+*   Low-level reentrant write function.
+*   libc subroutines will use this system routine for output to all files,
+*   including stdout.
+*   Write data via RTT.
+*/
+_ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len) {
+  (void) file;  /* Not used, avoid warning */
+  (void) r;     /* Not used, avoid warning */
+  SEGGER_RTT_Write(0, ptr, len);
+  return len;
+}
+
+#endif
+/****** End Of File *************************************************/
diff --git a/cva_bootloader_m0146/src/RTT/SEGGER_RTT_printf.c b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_printf.c
new file mode 100644
index 0000000..fba41db
--- /dev/null
+++ b/cva_bootloader_m0146/src/RTT/SEGGER_RTT_printf.c
@@ -0,0 +1,505 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2021 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       RTT version: 7.22b                                           *
+*                                                                    *
+**********************************************************************
+
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT_printf.c
+Purpose : Replacement for printf to write formatted data via RTT
+Revision: $Rev: 17697 $
+----------------------------------------------------------------------
+*/
+#include "SEGGER_RTT.h"
+#include "SEGGER_RTT_Conf.h"
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
+  #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64)
+#endif
+
+#include <stdlib.h>
+#include <stdarg.h>
+
+
+#define FORMAT_FLAG_LEFT_JUSTIFY   (1u << 0)
+#define FORMAT_FLAG_PAD_ZERO       (1u << 1)
+#define FORMAT_FLAG_PRINT_SIGN     (1u << 2)
+#define FORMAT_FLAG_ALTERNATE      (1u << 3)
+
+/*********************************************************************
+*
+*       Types
+*
+**********************************************************************
+*/
+
+typedef struct {
+  char*     pBuffer;
+  unsigned  BufferSize;
+  unsigned  Cnt;
+
+  int   ReturnValue;
+
+  unsigned RTTBufferIndex;
+} SEGGER_RTT_PRINTF_DESC;
+
+/*********************************************************************
+*
+*       Function prototypes
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       Static code
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       _StoreChar
+*/
+static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) {
+  unsigned Cnt;
+
+  Cnt = p->Cnt;
+  if ((Cnt + 1u) <= p->BufferSize) {
+    *(p->pBuffer + Cnt) = c;
+    p->Cnt = Cnt + 1u;
+    p->ReturnValue++;
+  }
+  //
+  // Write part of string, when the buffer is full
+  //
+  if (p->Cnt == p->BufferSize) {
+    if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) {
+      p->ReturnValue = -1;
+    } else {
+      p->Cnt = 0u;
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       _PrintUnsigned
+*/
+static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
+  static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+  unsigned Div;
+  unsigned Digit;
+  unsigned Number;
+  unsigned Width;
+  char c;
+
+  Number = v;
+  Digit = 1u;
+  //
+  // Get actual field width
+  //
+  Width = 1u;
+  while (Number >= Base) {
+    Number = (Number / Base);
+    Width++;
+  }
+  if (NumDigits > Width) {
+    Width = NumDigits;
+  }
+  //
+  // Print leading chars if necessary
+  //
+  if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) {
+    if (FieldWidth != 0u) {
+      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) {
+        c = '0';
+      } else {
+        c = ' ';
+      }
+      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+        FieldWidth--;
+        _StoreChar(pBufferDesc, c);
+        if (pBufferDesc->ReturnValue < 0) {
+          break;
+        }
+      }
+    }
+  }
+  if (pBufferDesc->ReturnValue >= 0) {
+    //
+    // Compute Digit.
+    // Loop until Digit has the value of the highest digit required.
+    // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100.
+    //
+    while (1) {
+      if (NumDigits > 1u) {       // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned)
+        NumDigits--;
+      } else {
+        Div = v / Digit;
+        if (Div < Base) {        // Is our divider big enough to extract the highest digit from value? => Done
+          break;
+        }
+      }
+      Digit *= Base;
+    }
+    //
+    // Output digits
+    //
+    do {
+      Div = v / Digit;
+      v -= Div * Digit;
+      _StoreChar(pBufferDesc, _aV2C[Div]);
+      if (pBufferDesc->ReturnValue < 0) {
+        break;
+      }
+      Digit /= Base;
+    } while (Digit);
+    //
+    // Print trailing spaces if necessary
+    //
+    if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) {
+      if (FieldWidth != 0u) {
+        while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+          FieldWidth--;
+          _StoreChar(pBufferDesc, ' ');
+          if (pBufferDesc->ReturnValue < 0) {
+            break;
+          }
+        }
+      }
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       _PrintInt
+*/
+static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
+  unsigned Width;
+  int Number;
+
+  Number = (v < 0) ? -v : v;
+
+  //
+  // Get actual field width
+  //
+  Width = 1u;
+  while (Number >= (int)Base) {
+    Number = (Number / (int)Base);
+    Width++;
+  }
+  if (NumDigits > Width) {
+    Width = NumDigits;
+  }
+  if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) {
+    FieldWidth--;
+  }
+
+  //
+  // Print leading spaces if necessary
+  //
+  if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) {
+    if (FieldWidth != 0u) {
+      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+        FieldWidth--;
+        _StoreChar(pBufferDesc, ' ');
+        if (pBufferDesc->ReturnValue < 0) {
+          break;
+        }
+      }
+    }
+  }
+  //
+  // Print sign if necessary
+  //
+  if (pBufferDesc->ReturnValue >= 0) {
+    if (v < 0) {
+      v = -v;
+      _StoreChar(pBufferDesc, '-');
+    } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) {
+      _StoreChar(pBufferDesc, '+');
+    } else {
+
+    }
+    if (pBufferDesc->ReturnValue >= 0) {
+      //
+      // Print leading zeros if necessary
+      //
+      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) {
+        if (FieldWidth != 0u) {
+          while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+            FieldWidth--;
+            _StoreChar(pBufferDesc, '0');
+            if (pBufferDesc->ReturnValue < 0) {
+              break;
+            }
+          }
+        }
+      }
+      if (pBufferDesc->ReturnValue >= 0) {
+        //
+        // Print number without sign
+        //
+        _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags);
+      }
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       Public code
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       SEGGER_RTT_vprintf
+*
+*  Function description
+*    Stores a formatted string in SEGGER RTT control block.
+*    This data is read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
+*    sFormat      Pointer to format string
+*    pParamList   Pointer to the list of arguments for the format string
+*
+*  Return values
+*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
+*     < 0:  Error
+*/
+int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) {
+  char c;
+  SEGGER_RTT_PRINTF_DESC BufferDesc;
+  int v;
+  unsigned NumDigits;
+  unsigned FormatFlags;
+  unsigned FieldWidth;
+  char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE];
+
+  BufferDesc.pBuffer        = acBuffer;
+  BufferDesc.BufferSize     = SEGGER_RTT_PRINTF_BUFFER_SIZE;
+  BufferDesc.Cnt            = 0u;
+  BufferDesc.RTTBufferIndex = BufferIndex;
+  BufferDesc.ReturnValue    = 0;
+
+  do {
+    c = *sFormat;
+    sFormat++;
+    if (c == 0u) {
+      break;
+    }
+    if (c == '%') {
+      //
+      // Filter out flags
+      //
+      FormatFlags = 0u;
+      v = 1;
+      do {
+        c = *sFormat;
+        switch (c) {
+        case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break;
+        case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO;     sFormat++; break;
+        case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN;   sFormat++; break;
+        case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE;    sFormat++; break;
+        default:  v = 0; break;
+        }
+      } while (v);
+      //
+      // filter out field with
+      //
+      FieldWidth = 0u;
+      do {
+        c = *sFormat;
+        if ((c < '0') || (c > '9')) {
+          break;
+        }
+        sFormat++;
+        FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0');
+      } while (1);
+
+      //
+      // Filter out precision (number of digits to display)
+      //
+      NumDigits = 0u;
+      c = *sFormat;
+      if (c == '.') {
+        sFormat++;
+        do {
+          c = *sFormat;
+          if ((c < '0') || (c > '9')) {
+            break;
+          }
+          sFormat++;
+          NumDigits = NumDigits * 10u + ((unsigned)c - '0');
+        } while (1);
+      }
+      //
+      // Filter out length modifier
+      //
+      c = *sFormat;
+      do {
+        if ((c == 'l') || (c == 'h')) {
+          sFormat++;
+          c = *sFormat;
+        } else {
+          break;
+        }
+      } while (1);
+      //
+      // Handle specifiers
+      //
+      switch (c) {
+      case 'c': {
+        char c0;
+        v = va_arg(*pParamList, int);
+        c0 = (char)v;
+        _StoreChar(&BufferDesc, c0);
+        break;
+      }
+      case 'd':
+        v = va_arg(*pParamList, int);
+        _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 'u':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 'x':
+      case 'X':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 's':
+        {
+          const char * s = va_arg(*pParamList, const char *);
+          do {
+            c = *s;
+            s++;
+            if (c == '\0') {
+              break;
+            }
+           _StoreChar(&BufferDesc, c);
+          } while (BufferDesc.ReturnValue >= 0);
+        }
+        break;
+      case 'p':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u);
+        break;
+      case '%':
+        _StoreChar(&BufferDesc, '%');
+        break;
+      default:
+        break;
+      }
+      sFormat++;
+    } else {
+      _StoreChar(&BufferDesc, c);
+    }
+  } while (BufferDesc.ReturnValue >= 0);
+
+  if (BufferDesc.ReturnValue > 0) {
+    //
+    // Write remaining data, if any
+    //
+    if (BufferDesc.Cnt != 0u) {
+      SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt);
+    }
+    BufferDesc.ReturnValue += (int)BufferDesc.Cnt;
+  }
+  return BufferDesc.ReturnValue;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_printf
+*
+*  Function description
+*    Stores a formatted string in SEGGER RTT control block.
+*    This data is read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
+*    sFormat      Pointer to format string, followed by the arguments for conversion
+*
+*  Return values
+*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Conversion specifications have following syntax:
+*          %[flags][FieldWidth][.Precision]ConversionSpecifier
+*    (2) Supported flags:
+*          -: Left justify within the field width
+*          +: Always print sign extension for signed conversions
+*          0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision
+*        Supported conversion specifiers:
+*          c: Print the argument as one char
+*          d: Print the argument as a signed integer
+*          u: Print the argument as an unsigned integer
+*          x: Print the argument as an hexadecimal integer
+*          s: Print the string pointed to by the argument
+*          p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.)
+*/
+int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) {
+  int r;
+  va_list ParamList;
+
+  va_start(ParamList, sFormat);
+  r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList);
+  va_end(ParamList);
+  return r;
+}
+/*************************** End of file ****************************/
diff --git a/cva_bootloader_m0146/src/TLE9461/SBC_TLE94x1.h b/cva_bootloader_m0146/src/TLE9461/SBC_TLE94x1.h
new file mode 100644
index 0000000..146c2cc
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/SBC_TLE94x1.h
@@ -0,0 +1,101 @@
+/**
+ * @cond
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2018, Infineon Technologies AG
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
+ * following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright notice, this list of conditions and the  following
+ *   disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
+ *   following disclaimer in the documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
+ *   products derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ **********************************************************************************************************************/
+#ifndef SBC_TLE94X1_H
+#define SBC_TLE94X1_H
+
+/* XML Version 0.0.6 */
+#define SBC_XML_VERSION (00006)
+
+#define CTRL_BUS_CTRL_0 (0x3) /*decimal 3*/
+
+#define CTRL_BUS_CTRL_3 (0x0) /*decimal 0*/
+
+#define CTRL_GPIO_CTRL (0x4) /*decimal 4*/
+
+#define CTRL_HW_CTRL_0 (0x40) /*decimal 64*/
+
+#define CTRL_HW_CTRL_1 (0x0) /*decimal 0*/
+
+#define CTRL_HW_CTRL_2 (0x40) /*decimal 64*/
+
+#define CTRL_HW_CTRL_3 (0x1) /*decimal 1*/
+
+#define CTRL_M_S_CTRL (0x13) /*decimal 19*/
+
+#define CTRL_PWM_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_PWM_FREQ_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_BTL0_CTRL (0x50) /*decimal 80*/
+
+#define CTRL_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_CDR_CTRL2 (0x1) /*decimal 1*/
+
+#define CTRL_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/
+
+#define CTRL_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/
+
+#define CTRL_SWK_DATA_H_CTRL 0x00000000
+
+#define CTRL_SWK_DATA_L_CTRL 0x00000000
+
+#define CTRL_SWK_DLC_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_ID0_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_IDx_CTRL 0x00000000
+
+#define CTRL_SWK_MASK_IDx_CTRL 0x00000000
+
+#define CTRL_TIMER_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_WD_CTRL (0x15) /*decimal 21*/
+
+#define CTRL_WK_CTRL_0 (0x0) /*decimal 0*/
+
+#define CTRL_WK_CTRL_1 (0x0) /*decimal 0*/
+
+#define CTRL_WK_PUPD_CTRL (0x0) /*decimal 0*/
+
+#define LED_Math_extendedID (0x1) /*decimal 1*/
+
+#define LED_Math_extendedIDMsk (0x1) /*decimal 1*/
+
+#define MATH_Baudrate (0x2) /*decimal 2*/
+
+#define MATH_CDR_FrequencyMHz (0x28) /*decimal 40*/
+
+#define MATH_DoubleCDRFreq (0x0) /*decimal 0*/
+
+#define MATH_EN_PN (0x1) /*decimal 1*/
+
+#define MATH_PWM_DC (0.0)
+
+#endif /* SBC_TLE94X1_H */
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE9461.icwp b/cva_bootloader_m0146/src/TLE9461/TLE9461.icwp
new file mode 100644
index 0000000..5a043c4
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE9461.icwp
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<icwpxml version="2.6.4">
+    <checksum>9e8e9087eecb39921ec31dfccce96b2a2efec664bafe2827aea4ddb51cb86761</checksum>
+    <XmlFile>TLE94x1_Lib.xml</XmlFile>
+    <XmlVersion>V0.0.6</XmlVersion>
+    <ActiveElements>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_2[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WK_PUPD_CTRL[7:6]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.PWM_FREQ_CTRL[1:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <DoubleSpinBox>
+            <define>MATH.PWM_DC</define>
+            <value>0</value>
+            <dispValue>0.0</dispValue>
+        </DoubleSpinBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[7]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.BUS_CTRL_3[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WK_PUPD_CTRL[1:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_0[6]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.TIMER_CTRL[3:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.TIMER_CTRL[6:4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_3[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ButtonGroup>
+            <define>CTRL.WD_CTRL[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ButtonGroup>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_2[7:5]</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_2[3:2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.SWK_CAN_FD_CTRL[3:1]</define>
+            <value>2</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>MATH.Baudrate</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.SWK_ID0_CTRL[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <LineEdit>
+            <define>CTRL.SWK_MASK_IDx_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0</dispValue>
+        </LineEdit>
+        <ComboBox>
+            <define>CTRL.SWK_DLC_CTRL[3:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <LineEdit>
+            <define>CTRL.SWK_DATA_H_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0x00000000</dispValue>
+        </LineEdit>
+        <LineEdit>
+            <define>CTRL.SWK_DATA_L_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0x00000000</dispValue>
+        </LineEdit>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[3]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_2[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.M_S_CTRL[4:3]</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>MATH.EN_PN</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_3[1:0]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[6]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.SWK_CAN_FD_CTRL[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>MATH.DoubleCDRFreq</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <LineEdit>
+            <define>CTRL.SWK_IDx_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0</dispValue>
+        </LineEdit>
+        <ComboBox>
+            <define>CTRL.GPIO_CTRL[2:0]</define>
+            <value>4</value>
+            <dispValue>4</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_0[2];CTRL.WD_CTRL[6]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WD_CTRL[4]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WD_CTRL[2:0]</define>
+            <value>5</value>
+            <dispValue>5</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.M_S_CTRL[1:0]</define>
+            <value>3</value>
+            <dispValue>3</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[7]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.M_S_CTRL[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.BUS_CTRL_0[2:0]</define>
+            <value>3</value>
+            <dispValue>3</dispValue>
+        </ComboBox>
+    </ActiveElements>
+</icwpxml>
\ No newline at end of file
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1.c b/cva_bootloader_m0146/src/TLE9461/TLE94x1.c
new file mode 100644
index 0000000..73428d2
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1.c
@@ -0,0 +1,591 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file         TLE94x1.c
+ *
+ * @brief        Implementation of main library functions
+ *
+ * @version     V1.0.1
+ * @date        05. October 2020
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ ********************************************************************************************************/
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */
+
+#include "TLE94x1.h"
+#include "SBC_TLE94x1.h"
+#include <stdio.h>
+
+
+/* ================================================================================ */
+/* ==============================   Variables     ================================= */
+/* ================================================================================ */
+
+
+/* --------------------------------  ISR Handling --------------------------------- */
+
+static    SBC_Func_Callback                 SBC_ISR_Callbacks[30];
+static    uint32_t                          SBC_ISR_Vectors[30];
+static    uint8_t                           SBC_ISR_ReadOutRegs[30];
+static    uint8_t                           SBC_ISR_ReadOutVals[30];
+static    uint8_t                           SBC_RegisteredCallbacks = 0;
+static    uint8_t                           SBC_RegisteredRedoutRegs = 0;
+
+
+
+/* ================================================================================ */
+/* ===========================   Library Functions     ============================ */
+/* ================================================================================ */
+
+
+/* --------------------------------  Main Functions ------------------------------- */
+
+
+SBC_ErrorCode SBC_WD_Trigger(void) {
+    /* Read WD config out of SBC and write back to trigger WD */
+    uint8_t WD_Data = (uint8_t)SBC_Read_Command(SBC_WD_CTRL);
+    return SBC_Write_Reg(SBC_WD_CTRL, WD_Data, NULL);
+}
+
+
+uint16_t SBC_Read_Command(uint8_t SBC_Reg) {
+    /* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */
+    return  SBC_SPI_TRANSFER16(SBC_Read_Mask & SBC_Reg, 0x00U);
+}
+
+
+uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos) {
+    uint8_t data = ((uint8_t)SBC_Read_Command(SBC_Reg)) & 0xFFU;
+    return (data & SBC_FieldMsk) >> SBC_FieldPos;
+}
+
+
+SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval) {
+    SBC_ErrorCode errCode;
+    uint16_t returndata = SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, SBC_Val);
+    if(returnval != NULL) {
+        *returnval = returndata;
+    }
+
+    errCode.SBC_Register = SBC_Reg;
+    errCode.flippedBitsMask = ((uint8_t)SBC_Read_Command(SBC_Reg)) ^ SBC_Val;
+    errCode.expectedValue = SBC_Val;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval) {
+    SBC_ErrorCode errCode;
+
+    /* Read data out of register to be manipulated */
+    uint16_t returndata = SBC_Read_Command(SBC_Reg);
+    if(returnval != NULL) {
+        *returnval = returndata;
+    }
+    uint8_t data = (uint8_t)returndata; 
+
+    /* Set the used bit field to all 0 */
+    data &= ~(SBC_FieldMsk);
+
+    /* Configure new data to bit field */
+    data |= (SBC_FieldVal << SBC_FieldPos);
+
+    (void)SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, data);
+
+    errCode.SBC_Register = SBC_Reg;
+    errCode.expectedValue = (SBC_FieldVal << SBC_FieldPos);
+    uint8_t actualValue = ((uint8_t)SBC_Read_Command(SBC_Reg)) & SBC_FieldMsk;
+    errCode.flippedBitsMask = errCode.expectedValue ^ actualValue;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Init(void) {
+    SBC_ErrorCode errCode;
+    uint8_t WD_Checksum = CTRL_WD_CTRL;
+    uint8_t WD_CTRL = CTRL_WD_CTRL;
+    uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL;
+    uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL;
+    uint8_t SWK_CAN_FD_CTRL = CTRL_SWK_CAN_FD_CTRL;
+
+    /* Calculate checksum */
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 4;
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 2;
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 1;
+
+    if((WD_Checksum & 1) > 0) {
+        /* Set parity bit */
+        WD_CTRL = CTRL_WD_CTRL | 0x80U;
+    }
+
+    /* Check if ID is configured to be extended */
+    if((CTRL_SWK_ID0_CTRL & SBC_SWK_ID0_CTRL_IDE_Msk) == SBC_IDE_EXTENDED) {
+        /* extended ID */
+        uint32_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL << 3;
+        uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL << 3;
+
+        SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 24);
+        SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL >> 16);
+        SWK_ID1_CTRL = (uint8_t)(SWK_ID_CTRL >> 8);
+        SWK_ID0_CTRL = (((uint8_t)(SWK_ID_CTRL >> 1)) & SBC_SWK_ID0_CTRL_ID4_0_Msk) | SBC_IDE_EXTENDED;
+        SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 24);
+        SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 16);
+        SWK_MASK_ID1_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 8);
+        SWK_MASK_ID0_CTRL = (((uint8_t)(SWK_MASK_ID_CTRL >> 1)) & SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk);
+    } else {
+        /* Standard length ID */
+        uint16_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL;
+        uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL;
+
+        SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 3);
+        SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL << 5);
+        SWK_ID1_CTRL = 0x00U;
+        SWK_ID0_CTRL = 0x00U;
+        SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 3);
+        SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL << 5);
+        SWK_MASK_ID1_CTRL = 0x00U;
+        SWK_MASK_ID0_CTRL = 0x00U;
+    }
+
+    /* DIS_ERR_CNT is set only when FD Tolerance is set. */
+    if((CTRL_SWK_CAN_FD_CTRL & SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk) == SBC_CAN_FD_EN_ENABLED) {
+        SWK_CAN_FD_CTRL &= SBC_DIS_ERR_CNT_DISABLED << SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos;
+    }
+
+    /* Describes initialization sequence */
+    uint8_t initSequence[39][2] = {
+        {SBC_WD_CTRL, WD_CTRL},
+        {SBC_M_S_CTRL, CTRL_M_S_CTRL},
+        {SBC_HW_CTRL_0, CTRL_HW_CTRL_0},
+        {SBC_HW_CTRL_3, CTRL_HW_CTRL_3},
+        {SBC_BUS_CTRL_3, CTRL_BUS_CTRL_3},
+        {SBC_WK_CTRL_0, CTRL_WK_CTRL_0},
+        {SBC_WK_CTRL_1, CTRL_WK_CTRL_1},
+        {SBC_WK_PUPD_CTRL, CTRL_WK_PUPD_CTRL},
+        {SBC_TIMER_CTRL, CTRL_TIMER_CTRL},
+        {SBC_PWM_FREQ_CTRL, CTRL_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */
+        {SBC_PWM_CTRL, CTRL_PWM_CTRL},
+        {SBC_GPIO_CTRL, CTRL_GPIO_CTRL},
+        {SBC_HW_CTRL_1, CTRL_HW_CTRL_1}, /* May lock configuration (CFG_LOCK_0) */
+        {SBC_HW_CTRL_2, CTRL_HW_CTRL_2}, /* May lock configuration (CFG_LOCK_1) */
+        {SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0},
+
+        /* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */
+
+        /* Configuring CDR */
+        {SBC_SWK_CDR_CTRL2, CTRL_SWK_CDR_CTRL2},
+        {SBC_SWK_BTL0_CTRL, CTRL_SWK_BTL0_CTRL},
+        {SBC_SWK_CDR_LIMIT_HIGH_CTRL, CTRL_SWK_CDR_LIMIT_HIGH_CTRL},
+        {SBC_SWK_CDR_LIMIT_LOW_CTRL, CTRL_SWK_CDR_LIMIT_LOW_CTRL},
+        {SBC_SWK_CDR_CTRL1, (SBC_SEL_FILT_TC16 << SBC_SWK_CDR_CTRL1_SEL_FILT_Pos) | (SBC_CDR_EN_ENABLED << SBC_SWK_CDR_CTRL1_CDR_EN_Pos)},
+
+
+        /* Set ID */
+        {SBC_SWK_ID3_CTRL, SWK_ID3_CTRL},
+        {SBC_SWK_ID2_CTRL, SWK_ID2_CTRL},
+        {SBC_SWK_ID1_CTRL, SWK_ID1_CTRL},
+        {SBC_SWK_ID0_CTRL, SWK_ID0_CTRL},
+
+        /* Set Mask */
+        {SBC_SWK_MASK_ID3_CTRL, SWK_MASK_ID3_CTRL},
+        {SBC_SWK_MASK_ID2_CTRL, SWK_MASK_ID2_CTRL},
+        {SBC_SWK_MASK_ID1_CTRL, SWK_MASK_ID1_CTRL},
+        {SBC_SWK_MASK_ID0_CTRL, SWK_MASK_ID0_CTRL},
+
+        /* Set Data */
+        {SBC_SWK_DATA7_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 24)},
+        {SBC_SWK_DATA6_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 16)},
+        {SBC_SWK_DATA5_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 8)},
+        {SBC_SWK_DATA4_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 0)},
+        {SBC_SWK_DATA3_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 24)},
+        {SBC_SWK_DATA2_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 16)},
+        {SBC_SWK_DATA1_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 8)},
+        {SBC_SWK_DATA0_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 0)},
+
+         /* Set DLC */
+        {SBC_SWK_DLC_CTRL, CTRL_SWK_DLC_CTRL},
+
+        {SBC_SWK_CAN_FD_CTRL, SWK_CAN_FD_CTRL},
+
+        /* End Configuration */
+        {0x00U, 0x00U}
+    };
+
+    /* Call SPI Init */
+    if(SBC_SPI_INIT() != 0) {
+        errCode.SBC_Register = 0x00;
+        errCode.flippedBitsMask = 0xFF;
+        errCode.expectedValue = 0x00;
+        return errCode;
+    };
+
+    uint8_t i = 0;
+
+    /* Write all initialization items to Lite SBC */
+    while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) {
+        errCode = SBC_Write_Reg(initSequence[i][0], initSequence[i][1], NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+        i++;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+
+
+/* --------------------------------  ISR Functions -------------------------------- */
+
+
+void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)) {
+    /* Save callback */
+    SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler;
+
+    /* Save callback vector */
+    SBC_ISR_Vectors[SBC_RegisteredCallbacks] = ISR_Vector;
+
+    /* Check if the register will be readout already to avoid double-readout later */
+    uint8_t RegFound = 0;
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        if (SBC_ISR_ReadOutRegs[i] == (ISR_Vector >> 24)) {
+            RegFound = 1;
+        }
+    }
+
+    /* If readout status-reg was not found, register in the readout list */
+    if (RegFound == 0) {
+        SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)(ISR_Vector >> 24);
+        SBC_RegisteredRedoutRegs++;
+    }
+
+    SBC_RegisteredCallbacks++;
+}
+
+
+SBC_ErrorCode SBC_ISR(void) {
+    SBC_ErrorCode errCode;
+
+    /* Readout all registered status-registers */
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        SBC_ISR_ReadOutVals[i] = (uint8_t) SBC_Read_Command(SBC_ISR_ReadOutRegs[i]);
+    }
+
+    /* Handle all interrupts */
+    for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) {
+        /* Decode ISR Vector */
+        uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i];
+        uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8);
+        uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16);
+        uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24);
+
+        /* Readback of associated status-bit */
+        uint8_t ReadBack = 0;
+        for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) {
+            if (SBC_ISR_ReadOutRegs[j] == RegAddr) {
+                ReadBack = SBC_ISR_ReadOutVals[j];
+                break;
+          }
+        }
+
+        /* If compare-values matched -> proceed callback and clear field */
+        if (((ReadBack & FieldMsk) >> FieldPos) == Compare) {
+            SBC_ISR_Callbacks[i](ReadBack);
+        }
+    }
+
+    /* Clear all ISR related registers */
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        errCode = SBC_Write_Reg(SBC_ISR_ReadOutRegs[i], 0x00U, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+    }
+
+    errCode.SBC_Register = 0x00U;
+    errCode.flippedBitsMask = 0x00U;
+    errCode.expectedValue = 0x00U;
+    return errCode;
+}
+
+
+
+/* --------------------------------  API Calls  ----------------------------------- */
+
+SBC_ErrorCode SBC_Mode_Normal(void) {
+    return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_NORMAL, NULL);
+}
+
+
+SBC_ErrorCode SBC_Mode_Stop(void) {
+    return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_STOP, NULL);
+}
+
+
+SBC_ErrorCode SBC_Mode_Sleep(void) {
+    uint8_t registerReadOut;
+
+    SBC_ErrorCode errCode;
+
+    /* If CAN PN is configured */
+    if(MATH_EN_PN != 0) {
+
+        /* Reading value of SWK_STAT. */
+        registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
+
+        /* CAN Protocol Handler in sync? The selective wake routine should be aborted if sync is not set. Note: for SYNC to be set the transceiver must have been in Normal Mode and a valid CAN communication must have been sent on the bus by any node. */
+        if((registerReadOut & SBC_SWK_STAT_SYNC_Msk) >> SBC_SWK_STAT_SYNC_Pos != SBC_SYNC_VALID_FRAME_RECEIVED) {
+            errCode.SBC_Register = SBC_SWK_STAT;
+            errCode.flippedBitsMask = SBC_SWK_STAT_SYNC_Msk;
+            errCode.expectedValue = SBC_SYNC_VALID_FRAME_RECEIVED << SBC_SWK_STAT_SYNC_Pos;
+            return errCode;
+        }
+
+        /* Set SWK Configuration valid */
+        errCode = SBC_Write_RegField(SBC_SWK_CTRL, SBC_SWK_CTRL_CFG_VAL_Msk, SBC_SWK_CTRL_CFG_VAL_Pos, SBC_CFG_VAL_VALID, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+		
+		
+		/* Clear SYSERR bit */
+        errCode = SBC_Write_RegField(SBC_BUS_STAT, SBC_BUS_STAT_SYSERR_Msk, SBC_BUS_STAT_SYSERR_Pos, 0x00, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }	
+
+        /* Set CAN Mode to off and once again to desired configuration */
+        errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, 0x03, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+		
+        errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+
+		 /* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */
+		registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
+        if(        ((SBC_SWK_STAT_SYNC_Msk & registerReadOut) == SBC_SWK_STAT_SYNC_Msk)
+            && ((SBC_SWK_STAT_SWK_SET_Msk & registerReadOut) == SBC_SWK_STAT_SWK_SET_Msk)
+            && ((SBC_SWK_STAT_WUP_Msk & registerReadOut) != SBC_SWK_STAT_WUP_Msk)
+            && ((SBC_SWK_STAT_WUF_Msk & registerReadOut) != SBC_SWK_STAT_WUF_Msk)) {
+        /* Empty */
+        } else {
+            errCode.SBC_Register = SBC_SWK_STAT;
+            errCode.expectedValue = 0b01000100U;
+            errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut;
+            return errCode;
+        }
+		
+		
+		
+    }
+
+	
+
+    /* Clear Wake Status Registers, so that SBC can sleep. */
+    errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+    errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+	
+    /* Select sleep mode */
+    (void)SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_SLEEP, NULL);
+    registerReadOut = (uint8_t)SBC_Read_Command(SBC_M_S_CTRL);
+
+    /* This piece of code is ideally never reached as the microcontroller should be already turned off then */
+    if(registerReadOut != 0) {
+        errCode.SBC_Register = SBC_M_S_CTRL;
+        errCode.flippedBitsMask = registerReadOut;
+        errCode.expectedValue = 0x00U;
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00U;
+    errCode.flippedBitsMask = 0x00U;
+    errCode.expectedValue = 0x00U;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Set_DutyCycle_PWM (uint8_t PWM_DC) {
+    return SBC_Write_Reg(SBC_PWM_CTRL, PWM_DC, NULL);
+}
+
+
+SBC_ErrorCode SBC_Set_Timer_On (uint8_t OnTime) {
+    return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_ON_Msk, SBC_TIMER_CTRL_TIMER_ON_Pos, OnTime, NULL);
+}
+
+
+SBC_ErrorCode SBC_Set_Timer_Period (uint8_t Period) {
+    return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_PER_Msk, SBC_TIMER_CTRL_TIMER_PER_Pos, Period, NULL);
+}
+
+
+SBC_ErrorCode SBC_FO_Test_On(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_ACTIVE, NULL);
+}
+
+
+SBC_ErrorCode SBC_FO_Test_Off(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_NOT_ACTIVE, NULL);
+}
+
+
+SBC_ErrorCode SBC_CP_On(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_ON, NULL);
+}
+
+
+SBC_ErrorCode SBC_CP_Off(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_OFF, NULL);
+}
+
+
+SBC_ErrorCode SBC_WK_MEAS_On(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_VOLTAGESENSING, NULL);
+}
+
+
+SBC_ErrorCode SBC_WK_MEAS_Off(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_WAKEUP, NULL);
+}
+
+
+SBC_ErrorCode SBC_TIMER_WK_EN_On(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKESOURCE, NULL);
+}
+
+
+SBC_ErrorCode SBC_TIMER_WK_EN_Off(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED, NULL);
+}
+
+
+uint16_t SBC_SYS_STAT_Read(void) {
+    uint16_t systemStatus = 0;
+    uint16_t returndata = SBC_Read_Command(SBC_SYS_STATUS_CTRL_0);
+    systemStatus = returndata & 0x00FFU;
+    systemStatus |= SBC_Read_Command(SBC_SYS_STATUS_CTRL_1) << 8;
+    return systemStatus;
+}
+
+
+SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus) {
+    SBC_ErrorCode errCode;
+
+    /* Write lower bits */
+    errCode = SBC_Write_Reg(SBC_SYS_STATUS_CTRL_0, (uint8_t)SystemStatus, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Write higher bits */
+    return SBC_Write_Reg(SBC_SYS_STATUS_CTRL_1, (uint8_t)(SystemStatus >> 8), NULL);
+}
+
+
+SBC_ErrorCode SBC_Lock_Configuration(void) {
+    SBC_ErrorCode errCode;
+
+    /* Lock CP_EN and GPIO cannot be modified */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_LOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Lock Bits with bit type ‘rwl’ (except CP_EN and GPIO) until next device power-up. */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_LOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Unlock_Configuration(void) {
+    SBC_ErrorCode errCode;
+
+    /* Unlock CP_EN and GPIO configuration. */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_NOTLOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Unlock Bits with bit type ‘rwl’ (except CP_EN and GPIO). */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_NOTLOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+SBC_ErrorCode SBC_Clear_Wake_Status(void) {
+    SBC_ErrorCode errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
+    if(errCode.flippedBitsMask != 0) {
+        return errCode;
+    }
+    errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
+    if(errCode.flippedBitsMask != 0) {
+        return errCode;
+    }
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1.h b/cva_bootloader_m0146/src/TLE9461/TLE94x1.h
new file mode 100644
index 0000000..a434389
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1.h
@@ -0,0 +1,393 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1.h
+ *
+ * @brief       Main header declaration file for TLE94x1 SBC family device
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+ 
+#ifndef TLE94x1_H
+#define TLE94x1_H
+ 
+
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+
+ 
+#include "TLE94x1_DEFINES.h"
+#include "TLE94x1_ISR.h"
+#include "TLE94x1_SPI.h"
+#include <stdint.h>
+
+
+
+
+/* ================================================================================ */
+/* ================================   MACROS     ================================== */
+/* ================================================================================ */ 
+
+
+/**
+ * @def     SBC_Write_Bit
+ * 
+ * @brief   This bit has to be set in order to write to a register.
+ */
+#define SBC_Write_Bit   (0x80U)
+
+/**
+ * @def     SBC_Read_Mask
+ * 
+ * @brief   A mask to prevent the user from accidentally writing to a register.
+ */
+#define SBC_Read_Mask   (0x7FU)
+
+
+
+
+/* ================================================================================ */
+/* ===========================   Library Functions     ============================ */
+/* ================================================================================ */ 
+
+struct __SBC_ErrorCode;
+
+/**
+ * @brief  A structure for simple error readout.
+ * 
+ *         flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue.
+ */
+typedef struct __SBC_ErrorCode {
+    uint8_t SBC_Register;       //!< The register where an error occurred.
+    uint8_t flippedBitsMask;    //!< Masks the bits that differ from the expected value. Is 0 if readout is as expected.
+    uint8_t expectedValue;      //!< Expected readout of the register.
+} SBC_ErrorCode;
+
+/**
+ * @brief   Typedef for interrupt callbacks.
+ */
+typedef void (*SBC_Func_Callback)(uint8_t callbackHandler);
+
+
+
+
+
+
+/* --------------------------------  Main Functions ------------------------------- */
+
+
+/**
+ * @brief   This method will trigger the watchdog.
+ * 
+ *          The function must be called periodically according to the configured watchdog-time.
+ */
+SBC_ErrorCode SBC_WD_Trigger(void);
+
+
+/**
+ * @brief   This method will proceed a readout of a register.
+ * 
+ * @param   SBC_Reg     Address of the register to be read out. See TLE94x1_DEFINES.h for definitions
+ * @retval  A 16 bit value will be returned.
+ *          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the read register-value.
+ *          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ */
+uint16_t SBC_Read_Command(uint8_t SBC_Reg);
+
+
+/**
+ * @brief   This method will proceed a readout of a dedicated bitfield within a register
+ * 
+ * @param   SBC_Reg         Address of the register to be readout. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldMsk    Bit mask of the field to be readout. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldPos    Bit position of the field to be readout. See TLE94x1_DEFINES.h for definitions
+ * 
+ * 
+ * @retval  A 8 bit value will be returned and includes the data of the bitfield to be read out *
+ */
+uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos);
+
+
+
+/**
+ * @brief   Writes a whole byte to a register and verifies it.
+ * 
+ * @param   SBC_Reg         Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_Val         Byte to write to SBC_Reg
+ * @param   *returnval      A 16 bit value will be returned.
+ *                          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
+ *                          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ * 
+ * @retval  See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval);
+
+
+/**
+ * @brief   This method can be used for manipulating a single bit-field in a control-register.
+ *
+ *          It will readout the old value of the registers, manipulate the desired bit-field and keep
+ *          the other bit-configuration as it was.
+ *          For usage examples have a look at the implementations of different API calls below.
+ * 
+ * @param   SBC_Reg         Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldMsk    Bit mask of the field to manipulate. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldPos    Bit position of the field to manipulate. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldVal    New value which will be written to the bit-field. See TLE94x1_DEFINES.h for enumerations
+ * @param   *returnval      A 16 bit value will be returned.
+ *                          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
+ *                          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ * 
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ *
+ */
+SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval);
+
+
+/**
+ * @brief   This method must be called one time at startup of the microcontroller.
+ *
+ *          This method will initialize all registers of the SBC with the configuration-data of SBC_TLE94x1.h.
+ *          After this, the SBC can be used as normal.
+ * 
+ * @retval  SBC_ErrorCode    See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Init(void);
+
+/* --------------------------------  ISR Functions -------------------------------- */
+
+
+/**
+ * @brief   This function can register a self-defined function to a specific interrupt-event of the SBC.
+ * 
+ *          Everytime the SBC_ISR() method is called and the associated status-bit is set, it will consider to
+ *          proceed a callback to this function later.
+ *          See all the possible ISR_Vectors in the TLE94x1_ISR.h
+ *
+ * 
+ * @param   ISR_Vector   Definition of the interrupt event. See all possible events in TLE94x1_ISR.h
+ * 
+ * @param   *Callback_Handler Pointer to the function which will be called back.
+ *          The function must accept a uint8_t as first argument.
+ */
+void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler));
+
+
+/**
+ * @brief   Interrupt Service Routine for handling interrupts.
+ * 
+ *          This method must be called automatically everytime a rising-edge on the INTN pin is recognized.
+ *          In case, the INTN pin is not connected, this method can also be called periodically by the user during runtime.
+ *          The ISR will proceed a readout of all registered interrupts. If a status-bit of a registered interrupt is set,
+ *          it will initiate a callback to the registered function and give the registered function the status-register value
+ *          as a parameter.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_ISR(void);
+
+
+
+/* --------------------------------  API Calls  ----------------------------------- */
+
+/**
+ * @brief   Enters SBC normal mode
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Normal(void);
+
+
+/**
+ * @brief   Enters SBC stop mode
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Stop(void);
+
+
+/**
+ * @brief   Clears all wake status registers and enter SBC sleep mode. Depending on configuration also the selective-wake feature will be initialized
+ *          before entering sleep mode. In case, the SWK option is enabled and the internal CAN protocol handler is not in sync when calling this function,
+ *          the sleep mode will be not entered.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Sleep(void);
+
+
+/**
+ * @brief   Sets the duty-cycle of the internal PWM generator
+ * 
+ * @param   PWM_DC Set the duty-cycle with values of 0-255 for 0% to 100%
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_DutyCycle_PWM(uint8_t PWM_DC);
+
+
+/**
+ * @brief   Sets the OnTime of the internal timer.
+ * 
+ * @param   OnTime	On time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_Timer_On(uint8_t OnTime);
+
+/**
+ * @brief   Sets the Period time of the internal timer
+ * 
+ * @param   Period  Period time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_Timer_Period(uint8_t Period);
+
+
+/**
+ * @brief   FO output activated by software for testing. Only working if FO/GPIO is configured as FO
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_FO_Test_On(void);
+
+
+/**
+ * @brief   FO output deactivated by software for testing. Only working if FO/GPIO is configured as FO
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_FO_Test_Off(void);
+
+
+/**
+ * @brief   Charge-Pump (VCP-Pin) is enabled. See chapter 5.3 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_CP_On(void);
+
+
+/**
+ * @brief   Charge-Pump (VCP-Pin) is disabled. See chapter 5.3 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_CP_Off(void);
+
+
+/**
+ * @brief   Enable Voltage Sensing. No wake-up events are generated. See chapter 9.2.4 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_WK_MEAS_On(void);
+
+
+/**
+ * @brief   Disable Voltage Sensing and enable wake-up functionality. See chapter 9.2.4 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_WK_MEAS_Off(void);
+
+
+/**
+ * @brief   WK is enabled as wake source. See chapter 5.2.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_TIMER_WK_EN_On(void);
+
+
+/**
+ * @brief   WK wake-up disabled. See chapter 5.2.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_TIMER_WK_EN_Off(void);
+
+
+/**
+ * @brief   Reads System Status Control, both lower and higher bits. See page 138 in datasheet.
+ * 
+ * @retval  Upper 8 bit are read from register SBC_SYS_STATUS_CTRL_1 and the lower 8 bit from SBC_SYS_STATUS_CTRL_0
+ */
+uint16_t SBC_SYS_STAT_Read(void);
+
+
+/**
+ * @brief   Writes System Status Control, both lower and higher bits. See page 138 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus);
+
+
+/**
+ * @brief   Locks CP_EN, GPIO configuration and 'rwl'-bits.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Lock_Configuration(void);
+
+
+/**
+ * @brief   Unlocks CP_EN, GPIO configuration and 'rwl'-bits.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Unlock_Configuration(void);
+
+
+/**
+ * @brief   Clears both Wake Status registers.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Clear_Wake_Status(void);
+
+#endif  /*TLE94x1_H*/
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1_DEFINES.h b/cva_bootloader_m0146/src/TLE9461/TLE94x1_DEFINES.h
new file mode 100644
index 0000000..57d8ab2
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1_DEFINES.h
@@ -0,0 +1,3248 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_DEFINES.h
+ *
+ * @brief       Main header declaration file for TLE94x1 SBC family device
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+#ifndef TLE94x1_DEFINES_H
+#define TLE94x1_DEFINES_H
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================           General Control Registers            ================ */
+/* ================================================================================ */
+
+
+
+/**
+ * @def     SBC_M_S_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_M_S_CTRL                            (0b00000001U)
+
+/**
+ * @def     SBC_HW_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_0                           (0b00000010U)
+
+/**
+ * @def     SBC_WD_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WD_CTRL                             (0b00000011U)
+
+/**
+ * @def     SBC_BUS_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_BUS_CTRL_0                          (0b00000100U)
+
+/**
+ * @def     SBC_WK_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_CTRL_0                           (0b00000110U)
+
+/**
+ * @def     SBC_WK_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_CTRL_1                           (0b00000111U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_PUPD_CTRL                        (0b00001000U)
+
+/**
+ * @def     SBC_BUS_CTRL_3
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_BUS_CTRL_3                          (0b00001011U)
+
+/**
+ * @def     SBC_TIMER_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_TIMER_CTRL                          (0b00001100U)
+
+/**
+ * @def     SBC_HW_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_1                           (0b00001110U)
+
+/**
+ * @def     SBC_HW_CTRL_2
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_2                           (0b00001111U)
+
+/**
+ * @def     SBC_GPIO_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_GPIO_CTRL                           (0b00010111U)
+
+/**
+ * @def     SBC_PWM_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_PWM_CTRL                            (0b00011000U)
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_PWM_FREQ_CTRL                       (0b00011100U)
+
+/**
+ * @def     SBC_HW_CTRL_3
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_3                           (0b00011101U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_SYS_STATUS_CTRL_0                   (0b00011110U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_SYS_STATUS_CTRL_1                   (0b00011111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================        Selective Wake Control Registers        ================ */
+/* ================================================================================ */
+
+
+
+/**
+ * @def     SBC_SWK_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CTRL                            (0b00100000U)
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_BTL0_CTRL                       (0b00100001U)
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_BTL1_CTRL                       (0b00100010U)
+
+/**
+ * @def     SBC_SWK_ID3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID3_CTRL                        (0b00100011U)
+
+/**
+ * @def     SBC_SWK_ID2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID2_CTRL                        (0b00100100U)
+
+/**
+ * @def     SBC_SWK_ID1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID1_CTRL                        (0b00100101U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID0_CTRL                        (0b00100110U)
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID3_CTRL                   (0b00100111U)
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID2_CTRL                   (0b00101000U)
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID1_CTRL                   (0b00101001U)
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID0_CTRL                   (0b00101010U)
+
+/**
+ * @def     SBC_SWK_DLC_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DLC_CTRL                        (0b00101011U)
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA7_CTRL                      (0b00101100U)
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA6_CTRL                      (0b00101101U)
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA5_CTRL                      (0b00101110U)
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA4_CTRL                      (0b00101111U)
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA3_CTRL                      (0b00110000U)
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA2_CTRL                      (0b00110001U)
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA1_CTRL                      (0b00110010U)
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA0_CTRL                      (0b00110011U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CAN_FD_CTRL                     (0b00110100U)
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL                   (0b00111000U)
+
+/**
+ * @def     SBC_SWK_OPT_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OPT_CTRL                        (0b00111001U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT                  (0b00111010U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_L_STAT
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_CAL_L_STAT                  (0b00111011U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_CTRL1                       (0b00111100U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_CTRL2                       (0b00111101U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL             (0b00111110U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL 
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL              (0b00111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================            General Status Registers            ================ */
+/* ================================================================================ */
+
+
+
+
+/**
+ * @def     SBC_SUP_STAT_1
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_SUP_STAT_1                          (0b01000000U)
+
+/**
+ * @def     SBC_SUP_STAT_0
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_SUP_STAT_0                          (0b01000001U)
+
+/**
+ * @def     SBC_THERM_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_THERM_STAT                          (0b01000010U)
+
+/**
+ * @def     SBC_DEV_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_DEV_STAT                            (0b01000011U)
+
+/**
+ * @def     SBC_BUS_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_BUS_STAT                            (0b01000100U)
+
+/**
+ * @def     SBC_WK_STAT_0
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_STAT_0                           (0b01000110U)
+
+/**
+ * @def     SBC_WK_STAT_1
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_STAT_1                           (0b01000111U)
+
+/**
+ * @def     SBC_WK_LVL_STAT 
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_LVL_STAT                         (0b01001000U)
+
+/**
+ * @def     SBC_GPIO_OC_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_GPIO_OC_STAT                        (0b01010100U)
+
+/**
+ * @def     SBC_GPIO_OL_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_GPIO_OL_STAT                        (0b01010101U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================        Selective Wake Status Registers         ================ */
+/* ================================================================================ */
+
+
+
+
+/**
+ * @def     SBC_SWK_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_STAT                            (0b01110000U)
+
+/**
+ * @def     SBC_SWK_ECNT_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_ECNT_STAT                       (0b01110001U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT1
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_CDR_STAT1                       (0b01110010U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT2
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_CDR_STAT2                       (0b01110011U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_FAM_PROD_STAT                       (0b01111110U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ============   General Control Registers Position & Mask        ================ */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  M_S_CTRL  ------------------------------------ */
+
+/**
+ * @def     SBC_M_S_CTRL_MODE_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_MODE_Pos                   (6U)
+/**
+ * @def     SBC_M_S_CTRL_MODE_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_MODE_Msk                   (0b11000000U)
+/**
+ * @def     SBC_M_S_CTRL_VCC2_ON_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC2_ON_Pos                (3U)
+/**
+ * @def     SBC_M_S_CTRL_VCC2_ON_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC2_ON_Msk                (0b00011000U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_OV_RST_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC1_OV_RST_Pos            (2U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_OV_RST_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC1_OV_RST_Msk            (0b00000100U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_RT_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC1_RT_Pos                (0U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_RT_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC1_RT_Msk                (0b00000011U)
+
+
+/* --------------------------------  HW_CTRL_0  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_0_SOFT_RESET_RST_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_SOFT_RESET_RST_Pos        (6U)
+
+/**
+ * @def     SBC_HW_CTRL_0_SOFT_RESET_RST_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_SOFT_RESET_RST_Msk        (0b01000000U)
+
+/**
+ * @def     SBC_HW_CTRL_0_FO_ON_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_FO_ON_Pos                 (5U)
+
+/**
+ * @def     SBC_HW_CTRL_0_FO_ON_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_FO_ON_Msk                 (0b00100000U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CP_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_CP_EN_Pos                 (2U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CP_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_CP_EN_Msk                 (0b00000100U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CFG1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_CFG1_Pos                  (0U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CFG1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_CFG1_Msk                  (0b00000001U)
+
+
+/* --------------------------------  WD_CTRL    ----------------------------------- */
+
+
+/**
+ * @def     SBC_WD_CTRL_CHECKSUM_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_CHECKSUM_Pos                (7U)
+
+/**
+ * @def     SBC_WD_CTRL_CHECKSUM_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_CHECKSUM_Msk                (0b10000000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_STM_EN_0_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_STM_EN_0_Pos             (6U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_STM_EN_0_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_STM_EN_0_Msk             (0b01000000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_WIN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_WIN_Pos                  (5U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_WIN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_WIN_Msk                  (0b00100000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_EN_WK_BUS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_EN_WK_BUS_Pos            (4U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_EN_WK_BUS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_EN_WK_BUS_Msk            (0b00010000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_TIMER_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_TIMER_Pos                (0U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_TIMER_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_TIMER_Msk                (0b00000111U)
+
+
+/* --------------------------------  BUS_CTRL_0  ---------------------------------- */
+
+/**
+ * @def     SBC_BUS_CTRL_0_CAN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_BUS_CTRL_0_CAN_Pos                  (0U)
+
+/**
+ * @def     SBC_BUS_CTRL_0_CAN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_BUS_CTRL_0_CAN_Msk                  (0b00000111U)
+
+
+/* --------------------------------  WK_CTRL_0  ----------------------------------- */
+
+/**
+ * @def     SBC_WK_CTRL_0_TIMER_WK_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_0_TIMER_WK_EN_Pos           (6U)
+
+/**
+ * @def     SBC_WK_CTRL_0_TIMER_WK_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_0_TIMER_WK_EN_Msk           (0b01000000U)
+
+/**
+ * @def     SBC_WK_CTRL_0_WD_STM_EN_1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_0_WD_STM_EN_1_Pos           (2U)
+
+/**
+ * @def     SBC_WK_CTRL_0_WD_STM_EN_1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_0_WD_STM_EN_1_Msk           (0b00000100U)
+
+
+/* --------------------------------  WK_CTRL_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_CTRL_1_INT_GLOBAL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_INT_GLOBAL_Pos            (7U)
+
+/**
+ * @def     SBC_WK_CTRL_1_INT_GLOBAL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_INT_GLOBAL_Msk            (0b10000000U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_MEAS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_WK_MEAS_Pos               (5U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_MEAS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_WK_MEAS_Msk               (0b00100000U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_WK_EN_Pos                 (0U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_WK_EN_Msk                 (0b00000001U)
+
+
+/* --------------------------------  WK_PUPD_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos       (6U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk       (0b11000000U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_WK_PUPD_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_PUPD_CTRL_WK_PUPD_Pos            (0U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_WK_PUPD_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_PUPD_CTRL_WK_PUPD_Msk            (0b00000011U)
+
+
+/* -------------------------------   BUS_CTRL_3  ---------------------------------- */
+
+/**
+ * @def     SBC_BUS_CTRL_3_CAN_FLASH_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_BUS_CTRL_3_CAN_FLASH_Pos            (4U)
+
+/**
+ * @def     SBC_BUS_CTRL_3_CAN_FLASH_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_BUS_CTRL_3_CAN_FLASH_Msk            (0b00010000U)
+
+
+/* -------------------------------   TIMER_CTRL  ---------------------------------- */
+
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_ON_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_TIMER_CTRL_TIMER_ON_Pos             (4U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_ON_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_TIMER_CTRL_TIMER_ON_Msk             (0b01110000U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_PER_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_TIMER_CTRL_TIMER_PER_Pos            (0U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_PER_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_TIMER_CTRL_TIMER_PER_Msk            (0b00001111U)
+
+
+/* --------------------------------  HW_CTRL_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_HYS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_RSTN_HYS_Pos              (7U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_HYS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_RSTN_HYS_Msk              (0b10000000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_TSD2_DEL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_TSD2_DEL_Pos              (5U)
+
+/**
+ * @def     SBC_HW_CTRL_1_TSD2_DEL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_TSD2_DEL_Msk              (0b00100000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_DEL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_RSTN_DEL_Pos              (4U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_DEL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_RSTN_DEL_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_CFG_LOCK_0_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_CFG_LOCK_0_Pos            (3U)
+
+/**
+ * @def     SBC_HW_CTRL_1_CFG_LOCK_0_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_CFG_LOCK_0_Msk            (0b00001000U)
+
+
+/* --------------------------------  HW_CTRL_2  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_2_2MHZ_FREQ_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_2MHZ_FREQ_Pos             (5U)
+
+/**
+ * @def     SBC_HW_CTRL_2_2MHZ_FREQ_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_2MHZ_FREQ_Msk             (0b11100000U)
+
+/**
+ * @def     SBC_HW_CTRL_2_I_PEAK_TH_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_I_PEAK_TH_Pos             (4U)
+
+/**
+ * @def     SBC_HW_CTRL_2_I_PEAK_TH_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_I_PEAK_TH_Msk             (0b00010000U)
+
+/**
+ * @def     SBC_HW_CTRL_2_SS_MOD_FR_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_SS_MOD_FR_Pos             (2U)
+
+/**
+ * @def     SBC_HW_CTRL_2_SS_MOD_FR_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_SS_MOD_FR_Msk             (0b00001100U)
+
+/**
+ * @def     SBC_HW_CTRL_2_CFG_LOCK_1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_CFG_LOCK_1_Pos            (0U)
+
+/**
+ * @def     SBC_HW_CTRL_2_CFG_LOCK_1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_CFG_LOCK_1_Msk            (0b00000001U)
+
+
+/* --------------------------------  GPIO_CTRL  ----------------------------------- */
+
+/**
+ * @def     SBC_GPIO_CTRL_GPIO_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_GPIO_CTRL_GPIO_Pos                  (0U)
+
+/**
+ * @def     SBC_GPIO_CTRL_GPIO_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_GPIO_CTRL_GPIO_Msk                  (0b00000111U)
+
+
+/* --------------------------------  PWM_CTRL  -------------------------------------- */
+
+/**
+ * @def     SBC_PWM_DC_PWM_DC_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_PWM_CTRL_PWM_DC_Pos                   (0U)
+
+/**
+ * @def     SBC_PWM_DC_PWM_DC_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_PWM_CTRL_PWM_DC_Msk                   (0b11111111U)
+
+
+/* --------------------------------  PWM_FREQ_CTRL  -------------------------------------- */
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos            (0U)
+
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk            (0b00000011U)
+
+
+/* --------------------------------  HW_CTRL_3  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_3_TSD_THR_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_3_TSD_THR_Pos               (2U)
+
+/**
+ * @def     SBC_HW_CTRL_3_TSD_THR_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_3_TSD_THR_Msk               (0b00000100U)
+
+/**
+ * @def     SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos          (0U)
+
+/**
+ * @def     SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk          (0b00000011U)
+
+
+/* --------------------------------  SYS_STATUS_CTRL_0  --------------------------- */
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos    (0U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk    (0b11111111U)
+
+
+/* --------------------------------  SYS_STATUS_CTRL_1  --------------------------- */
+
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos    (0U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk    (0b11111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ========   Selective Wake Control Registers Position & Mask        ============= */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  SWK_CTRL  ------------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_CTRL_OSC_CAL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_OSC_CAL_Pos                (7U)
+
+/**
+ * @def     SBC_SWK_CTRL_OSC_CAL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_OSC_CAL_Msk                (0b10000000U)
+
+/**
+ * @def     SBC_SWK_CTRL_TRIM_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_TRIM_EN_Pos                (5U)
+
+/**
+ * @def     SBC_SWK_CTRL_TRIM_EN_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_TRIM_EN_Msk                (0b01100000U)
+
+/**
+ * @def     SBC_SWK_CTRL_CANTO_MASK_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_CANTO_MASK_Pos             (4U)
+
+/**
+ * @def     SBC_SWK_CTRL_CANTO_MASK_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_CANTO_MASK_Msk             (0b00010000U)
+
+/**
+ * @def     SBC_SWK_CTRL_CFG_VAL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_CFG_VAL_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_CTRL_CFG_VAL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_CFG_VAL_Msk                (0b00000001U)
+
+
+/* --------------------------------  SWK_BTL0_CTRL  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL_TBIT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_BTL0_CTRL_TBIT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL_TBIT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_BTL0_CTRL_TBIT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_BTL1_CTRL  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL_SP_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_BTL1_CTRL_SP_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL_SP_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_BTL1_CTRL_SP_Msk                (0b00111111U)
+
+
+/* --------------------------------  SWK_ID3_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID3_CTRL_ID28_21_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID3_CTRL_ID28_21_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_ID3_CTRL_ID28_21_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID3_CTRL_ID28_21_Msk            (0b11111111U)
+
+
+/* --------------------------------  SWK_ID2_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID2_CTRL_ID20_13_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID2_CTRL_ID20_13_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_ID2_CTRL_ID20_13_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID2_CTRL_ID20_13_Msk            (0b11111111U)
+
+
+/* --------------------------------  SWK_ID1_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID1_CTRL_ID12_5_Pos
+ * 
+ * @brief   Selective wake register bit position. 
+ */
+#define SBC_SWK_ID1_CTRL_ID12_5_Pos             (0U)
+
+/**
+ * @def     SBC_SWK_ID1_CTRL_ID12_5_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID1_CTRL_ID12_5_Msk             (0b11111111U)
+
+
+/* --------------------------------  SWK_ID0_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_ID4_0_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_ID4_0_Pos              (2U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_ID4_0_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_ID4_0_Msk              (0b01111100U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_RTR_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_RTR_Pos                (1U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_RTR_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_RTR_Msk                (0b00000010U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_IDE_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_IDE_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_IDE_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_IDE_Msk                (0b00000001U)
+
+
+/* --------------------------------  SWK_MASK_ID3_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID3_CTRL_Pos               (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID3_CTRL_Msk               (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID2_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos  (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk  (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID1_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos   (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk   (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID0_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos
+ * 
+ * @brief   Selective wake register bit position. 
+ */
+#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos    (2U)
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk    (0b01111100U)
+
+
+/* --------------------------------  SWK_DLC_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_DLC_CTRL_DLC_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DLC_CTRL_DLC_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_DLC_CTRL_DLC_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DLC_CTRL_DLC_Msk                (0b00001111U)
+
+
+/* --------------------------------  SWK_DATA7_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA7_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA7_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA6_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA6_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA6_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA5_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA5_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA5_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA4_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA4_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA4_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA3_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA3_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA3_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA2_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA2_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA2_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA1_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA1_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA1_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA0_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA0_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA0_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_CAN_FD_CTRL  ----------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos     (5U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk     (0b00100000U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos     (4U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk     (0b00010000U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos       (1U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk       (0b00001110U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos       (0U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk       (0b00000001U)
+
+
+/* --------------------------------  SWK_OSC_TRIM_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL_Pos               (0U)
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL_Msk               (0b01111111U)
+
+
+/* --------------------------------  SWK_OPT_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos          (7U)
+
+/**
+ * @def     SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk          (0b10000000U)
+
+
+/* --------------------------------  SWK_OSC_CAL_H_STAT  -------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_OPT_CAL_L_STAT  -------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OPT_CAL_L_STAT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OPT_CAL_L_STAT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_OPT_CAL_L_STAT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OPT_CAL_L_STAT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_CTRL1  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_SEL_FILT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL1_SEL_FILT_Pos          (2U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_SEL_FILT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL1_SEL_FILT_Msk          (0b00001100U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_CDR_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL1_CDR_EN_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_CDR_EN_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL1_CDR_EN_Msk            (0b00000001U)
+
+
+/* --------------------------------  SWK_CDR_CTRL2  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos       (0U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk       (0b00000011U)
+
+
+/* --------------------------------  SWK_CDR_LIMIT_HIGH_CTRL  --------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos   (0U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk   (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_LIMIT_LOW_CTRL  ---------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos    (0U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk    (0b11111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* =============   General Status Registers Position & Mask        ================ */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  SUP_STAT_1  ---------------------------------- */
+
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VS_UV_Pos                (6U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VS_UV_Msk                (0b01000000U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_OV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VS_OV_Pos                (5U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_OV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VS_OV_Msk                (0b00100000U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_OV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VCC1_OV_Pos              (1U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_OV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VCC1_OV_Msk              (0b00000010U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_WARN_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VCC1_WARN_Pos            (0U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_WARN_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VCC1_WARN_Msk            (0b00000001U)
+
+
+/* --------------------------------  SUP_STAT_0  ---------------------------------- */
+
+
+/**
+ * @def     SBC_SUP_STAT_0_POR_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_POR_Pos                  (7U)
+
+/**
+ * @def     SBC_SUP_STAT_0_POR_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_POR_Msk                  (0b10000000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_OT_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC2_OT_Pos              (4U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_OT_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC2_OT_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC2_UV_Pos              (3U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC2_UV_Msk              (0b00001000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_SC_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC1_SC_Pos              (2U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_SC_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC1_SC_Msk              (0b00000100U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC1_UV_Pos              (0U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC1_UV_Msk              (0b00000001U)
+
+
+/* --------------------------------  THERM_STAT  ---------------------------------- */
+
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_SAFE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD2_SAFE_Pos            (3U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_SAFE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD2_SAFE_Msk            (0b00001000U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD2_Pos                 (2U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD2_Msk                 (0b00000100U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD1_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD1_Pos                 (1U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD1_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD1_Msk                 (0b00000010U)
+
+/**
+ * @def     SBC_THERM_STAT_TPW_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TPW_Pos                  (0U)
+
+/**
+ * @def     SBC_THERM_STAT_TPW_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TPW_Msk                  (0b00000001U)
+
+
+/* --------------------------------  DEV_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_DEV_STAT_DEV_STAT_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_DEV_STAT_Pos               (6U)
+
+/**
+ * @def     SBC_DEV_STAT_DEV_STAT_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_DEV_STAT_Msk               (0b11000000U)
+
+/**
+ * @def     SBC_DEV_STAT_WD_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_WD_FAIL_Pos                (2U)
+
+/**
+ * @def     SBC_DEV_STAT_WD_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_WD_FAIL_Msk                (0b00001100U)
+
+/**
+ * @def     SBC_DEV_STAT_SPI_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_SPI_FAIL_Pos               (1U)
+
+/**
+ * @def     SBC_DEV_STAT_SPI_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_SPI_FAIL_Msk               (0b00000010U)
+
+/**
+ * @def     SBC_DEV_STAT_FAILURE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_FAILURE_Pos                (0U)
+
+/**
+ * @def     SBC_DEV_STAT_FAILURE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_FAILURE_Msk                (0b00000001U)
+
+
+/* --------------------------------  BUS_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_BUS_STAT_CANTO_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_CANTO_Pos                  (4U)
+
+/**
+ * @def     SBC_BUS_STAT_CANTO_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_CANTO_Msk                  (0b00010000U)
+
+/**
+ * @def     SBC_BUS_STAT_SYSERR_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_SYSERR_Pos                 (3U)
+
+/**
+ * @def     SBC_BUS_STAT_SYSERR_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_SYSERR_Msk                 (0b00001000U)
+
+/**
+ * @def     SBC_BUS_STAT_CAN_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_CAN_FAIL_Pos               (1U)
+
+/**
+ * @def     SBC_BUS_STAT_CAN_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_CAN_FAIL_Msk               (0b00000110U)
+
+/**
+ * @def     SBC_BUS_STAT_VCAN_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_VCAN_UV_Pos                (0U)
+
+/**
+ * @def     SBC_BUS_STAT_VCAN_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_VCAN_UV_Msk                (0b00000001U)
+
+
+/* --------------------------------  WK_STAT_0  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_STAT_0_CAN_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_CAN_WU_Pos                (5U)
+
+/**
+ * @def     SBC_WK_STAT_0_CAN_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_CAN_WU_Msk                (0b00100000U)
+
+/**
+ * @def     SBC_WK_STAT_0_TIMER_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_TIMER_WU_Pos              (4U)
+
+/**
+ * @def     SBC_WK_STAT_0_TIMER_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_TIMER_WU_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_WK_STAT_0_WK_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_WK_WU_Pos                 (0U)
+
+/**
+ * @def     SBC_WK_STAT_0_WK_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_WK_WU_Msk                 (0b00000001U)
+
+
+/* --------------------------------  WK_STAT_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_STAT_1_GPIO_WK_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_1_GPIO_WK_WU_Pos            (4U)
+
+/**
+ * @def     SBC_WK_STAT_1_GPIO_WK_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_1_GPIO_WK_WU_Msk            (0b00010000U)
+
+
+/* --------------------------------  WK_LVL_STAT  --------------------------------- */
+
+
+/**
+ * @def     SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos         (7U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk         (0b10000000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_CFG0_STATE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_CFG0_STATE_Pos          (6U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_CFG0_STATE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_CFG0_STATE_Msk          (0b01000000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_GPIO_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_GPIO_LVL_Pos            (4U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_GPIO_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_GPIO_LVL_Msk            (0b00010000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_WK_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_WK_LVL_Pos              (0U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_WK_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_WK_LVL_Msk              (0b00000001U)
+
+
+/* --------------------------------  GPIO_OC_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_GPIO_OC_STAT_GPIO_OC_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_GPIO_OC_STAT_GPIO_OC_Pos            (6U)
+
+/**
+ * @def     SBC_GPIO_OC_STAT_GPIO_OC_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_GPIO_OC_STAT_GPIO_OC_Msk            (0b01000000U)
+
+
+/* --------------------------------  GPIO_OL_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_GPIO_OL_STAT_GPIO_OL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_GPIO_OL_STAT_GPIO_OL_Pos            (6U)
+
+/**
+ * @def     SBC_GPIO_OL_STAT_GPIO_OL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_GPIO_OL_STAT_GPIO_OL_Msk            (0b01000000U)
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* =========   Selective Wake Status Registers Position & Mask        ============= */
+/* ================================================================================ */
+
+
+
+
+/* --------------------------------  SWK_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_STAT_SYNC_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_SYNC_Pos                   (6U)
+
+/**
+ * @def     SBC_SWK_STAT_SYNC_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_SYNC_Msk                   (0b01000000U)
+
+/**
+ * @def     SBC_SWK_STAT_CANSIL_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_CANSIL_Pos                 (3U)
+
+/**
+ * @def     SBC_SWK_STAT_CANSIL_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_CANSIL_Msk                 (0b00001000U)
+
+/**
+ * @def     SBC_SWK_STAT_SWK_SET_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_SWK_SET_Pos                (2U)
+
+/**
+ * @def     SBC_SWK_STAT_SWK_SET_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_SWK_SET_Msk                (0b00000100U)
+
+/**
+ * @def     SBC_SWK_STAT_WUP_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_WUP_Pos                    (1U)
+
+/**
+ * @def     SBC_SWK_STAT_WUP_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_WUP_Msk                    (0b00000010U)
+
+/**
+ * @def     SBC_SWK_STAT_WUF_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_WUF_Pos                    (0U)
+
+/**
+ * @def     SBC_SWK_STAT_WUF_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_WUF_Msk                    (0b00000001U)
+
+
+
+
+
+/* --------------------------------  SWK_ECNT_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ECNT_STAT_ECNT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_ECNT_STAT_ECNT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_ECNT_STAT_ECNT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_ECNT_STAT_ECNT_Msk              (0b00111111U)
+
+
+/* --------------------------------  SWK_CDR_STAT1  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_STAT1_NAVG_SAT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_CDR_STAT1_NAVG_SAT_Pos          (0U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT1_NAVG_SAT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_CDR_STAT1_NAVG_SAT_Msk          (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_STAT2  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_STAT2_NAVG_SAT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_CDR_STAT2_NAVG_SAT_Pos          (4U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT2_NAVG_SAT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_CDR_STAT2_NAVG_SAT_Msk          (0b11110000U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ======   Family and Product Information Register Position & Mask        ======== */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  FAM_PROD_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_FAM_PROD_STAT_FAM_Pos
+ * 
+ * @brief   Family and product register bit position.
+ */
+#define SBC_FAM_PROD_STAT_FAM_Pos               (4U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_FAM_Msk
+ * 
+ * @brief   Family and product register bit mask.
+ */
+#define SBC_FAM_PROD_STAT_FAM_Msk               (0b11110000U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_PROD_Pos
+ * 
+ * @brief   Family and product register bit position.
+ */
+#define SBC_FAM_PROD_STAT_PROD_Pos              (0U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_PROD_Msk
+ * 
+ * @brief   Family and product register bit mask.
+ */
+#define SBC_FAM_PROD_STAT_PROD_Msk              (0b00001111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ===============   General Control Registers Enumerations        ================ */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  M_S_CTRL  ------------------------------------ */
+
+typedef enum
+{
+    SBC_MODE_NORMAL                         = 0x00U,
+    SBC_MODE_SLEEP,
+    SBC_MODE_STOP,
+    SBC_MODE_RESET
+};
+
+typedef enum
+{
+    SBC_VCC2_OFF                            = 0x00U,
+    SBC_VCC2_ON_NORMAL,
+    SBC_VCC2_ON_NORMAL_STOP,
+    SBC_VCC2_ON_ALWAYS
+};
+
+typedef enum
+{
+    SBC_VCC1_OV_RST_NOACTION                = 0x00U,
+    SBC_VCC1_OV_RST_RESTART_FAILSAFE
+};
+
+typedef enum
+{
+    SBC_VCC1_RT_VRT1                        = 0x00U,
+    SBC_VCC1_RT_VRT2,
+    SBC_VCC1_RT_VRT3,
+    SBC_VCC1_RT_VRT4
+};
+
+
+/* --------------------------------  HW_CTRL_0  ----------------------------------- */
+
+typedef enum
+{
+    SBC_SOFT_RESET_RST_TRIGGER_SOFTRST      = 0x00U,
+    SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST
+};
+
+typedef enum
+{
+    SBC_FO_ON_NOT_ACTIVE                    = 0x00U,
+    SBC_FO_ON_ACTIVE
+};
+
+typedef enum
+{
+    SBC_CP_EN_OFF                           = 0x00U,
+    SBC_CP_EN_ON
+};
+
+typedef enum
+{
+    SBC_CFG1_RESTART_FAILSAFE_2WDFAIL       = 0x00U,
+    SBC_CFG1_RESTART_FAILSAFE_1WDFAIL
+};
+
+
+/* --------------------------------  WD_CTRL  ------------------------------------- */
+
+typedef enum
+{
+    SBC_CHECKSUM_0                       = 0x00U,
+    SBC_CHECKSUM_1
+};
+
+typedef enum
+{
+    SBC_WD_STM_EN_0_ACTIVE_STOPMODE         = 0x00U,
+    SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE
+};
+
+typedef enum
+{
+    SBC_WD_WIN_TIMEOUT_WD                   = 0x00U,
+    SBC_WD_WIN_WINDOW_WD
+};
+
+typedef enum
+{
+    SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE  = 0x00U,
+    SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE
+};
+
+typedef enum
+{
+    SBC_WD_TIMER_10MS                       = 0x00U,
+    SBC_WD_TIMER_20MS,
+    SBC_WD_TIMER_50MS,
+    SBC_WD_TIMER_100MS,
+    SBC_WD_TIMER_200MS,
+    SBC_WD_TIMER_500MS,
+    SBC_WD_TIMER_1000MS,
+    SBC_WD_TIMER_10000MS
+};
+
+
+/* --------------------------------  BUS_CTRL_0  ---------------------------------- */
+
+typedef enum
+{
+    SBC_BUS_CTRL_0_CAN_WAKECAPABLE_NOSWK    = 0x01U,
+    SBC_BUS_CTRL_0_CAN_RECEIVEONLY_NOSWK,
+    SBC_BUS_CTRL_0_CAN_NORMAL_NOSWK,
+    SBC_BUS_CTRL_0_CAN_OFF,
+    SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK,
+    SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK,
+    SBC_BUS_CTRL_0_CAN_NORMAL_SWK
+};
+
+
+/* --------------------------------  WK_CTRL_0  ----------------------------------- */
+
+typedef enum
+{
+    WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED   = 0x00U,
+    WK_CTRL_0_TIMER_WK_EN_WAKESOURCE
+};
+
+typedef enum
+{
+    SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE       = 0x00U,
+    SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE
+};
+
+
+/* --------------------------------  WK_CTRL_1  ----------------------------------- */
+
+typedef enum
+{
+    SBC_INT_GLOBAL_WAKESOURCES_ONLY         = 0x00U,
+    SBC_INT_GLOBAL_ALLINFORMATIONBITS
+};
+
+typedef enum
+{
+    SBC_WK_MEAS_WK_AS_WAKEUP                = 0x00U,
+    SBC_WK_MEAS_WK_AS_VOLTAGESENSING
+};
+
+typedef enum
+{
+    SBC_WK_EN_WAKEUP_DISABLED               = 0x00U,
+    SBC_WK_EN_WAKEUP_ENABLED
+};
+
+
+/* --------------------------------  WK_PUPD_CTRL  -------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_WK_PUPD_NOPULLING              = 0x00U,
+    SBC_GPIO_WK_PUPD_PULLDOWN,
+    SBC_GPIO_WK_PUPD_PULLUP,
+    SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING
+};
+
+typedef enum
+{
+    SBC_WK_PUPD_NOPULLING                   = 0x00U,
+    SBC_WK_PUPD_PULLDOWN,
+    SBC_WK_PUPD_PULLUP,
+    SBC_WK_PUPD_AUTOMATIC_PULLING
+};
+
+
+/* --------------------------------  BUS_CTRL_3  ---------------------------------- */
+
+typedef enum
+{
+    SBC_CAN_FLASH_DISABLED                  = 0x00U,
+    SBC_CAN_FLASH_ENABLED
+};
+
+
+/* --------------------------------  TIMER_CTRL  ---------------------------------- */
+
+typedef enum
+{
+    SBC_TIMER_ON_TIMEROFF_HSX_LOW           = 0x00U,
+    SBC_TIMER_ON_100US,
+    SBC_TIMER_ON_300US,
+    SBC_TIMER_ON_1MS,
+    SBC_TIMER_ON_10MS,
+    SBC_TIMER_ON_20MS,
+    SBC_TIMER_ON_TIMEROFF_HSX_HIGH
+};
+
+typedef enum
+{
+    SBC_TIMER_PER_10MS                      = 0x00U,
+    SBC_TIMER_PER_20MS,
+    SBC_TIMER_PER_50MS,
+    SBC_TIMER_PER_100MS,
+    SBC_TIMER_PER_200MS,
+    SBC_TIMER_PER_500MS,
+    SBC_TIMER_PER_1S,
+    SBC_TIMER_PER_2S,
+    SBC_TIMER_PER_5S,
+    SBC_TIMER_PER_10S,
+    SBC_TIMER_PER_20S,
+    SBC_TIMER_PER_50S,
+    SBC_TIMER_PER_100S,
+    SBC_TIMER_PER_200S,
+    SBC_TIMER_PER_500S,
+    SBC_TIMER_PER_1000S
+};
+
+
+/* --------------------------------  HW_CTRL_1  ----------------------------------- */
+
+typedef enum
+{
+    SBC_RSTN_HYS_DEFAULT                    = 0x00U,
+    SBC_RSTN_HYS_HIGHEST_VRT
+};
+
+typedef enum
+{
+    SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION  = 0x00U,
+    SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS
+};
+
+typedef enum
+{
+    SBC_RSTN_DEL_TRD1                       = 0x00U,
+    SBC_RSTN_DEL_TRD2
+};
+
+typedef enum
+{
+    SBC_CFG_LOCK_0_NOTLOCKED                = 0x00U,
+    SBC_CFG_LOCK_0_LOCKED
+};
+
+
+/* --------------------------------  HW_CTRL_2  ----------------------------------- */
+
+typedef enum
+{
+    SBC_2MHZ_FREQ_1_8_MHZ                   = 0x00U,
+    SBC_2MHZ_FREQ_2_0_MHZ,
+    SBC_2MHZ_FREQ_2_2_MHZ,
+    SBC_2MHZ_FREQ_2_4_MHZ
+};
+
+typedef enum
+{
+    SBC_I_PEAK_TH_LOW                       = 0x00U,
+    SBC_I_PEAK_TH_HIGH
+};
+
+typedef enum
+{
+    SBC_SS_MOD_FR_DISABLED                  = 0x00U,
+    SBC_SS_MOD_FR_15_6KHZ,
+    SBC_SS_MOD_FR_31_2KHZ,
+    SBC_SS_MOD_FR_62_5KHZ
+};
+
+typedef enum
+{
+    SBC_CFG_LOCK_1_NOTLOCKED                = 0x00U,
+    SBC_CFG_LOCK_1_LOCKED
+};
+
+
+/* --------------------------------  GPIO_CTRL  ----------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_FO                             = 0x00U,
+    SBC_GPIO_HSS_TIMER                      = 0x03U,
+    SBC_GPIO_OFF,
+    SBC_GPIO_WAKE_INPUT,
+    SBC_GPIO_LSS_PWM,
+    SBC_GPIO_HSS_PWM
+};
+
+
+/* --------------------------------  PWM_CTRL  ------------------------------------ */
+
+typedef enum
+{
+    SBC_PWM_DC_0                            = 0x00U,
+    SBC_PWM_DC_10                           = 0x19U,
+    SBC_PWM_DC_20                           = 0x51U,
+    SBC_PWM_DC_30                           = 0x4DU,
+    SBC_PWM_DC_40                           = 0x66U,
+    SBC_PWM_DC_50                           = 0x80U,
+    SBC_PWM_DC_60                           = 0x99U,
+    SBC_PWM_DC_70                           = 0xB3U,
+    SBC_PWM_DC_80                           = 0xCCU,
+    SBC_PWM_DC_90                           = 0xE6U,
+    SBC_PWM_DC_100                          = 0xFFU
+};
+
+
+/* --------------------------------  PWM_FREQ_CTRL  ------------------------------- */
+
+typedef enum
+{
+    SBC_PWM_FREQ_100HZ                      = 0x00U,
+    SBC_PWM_FREQ_200HZ,
+    SBC_PWM_FREQ_325HZ,
+    SBC_PWM_FREQ_400HZ
+};
+
+
+/* --------------------------------  HW_CTRL_3 ----------------------------------- */
+
+typedef enum
+{
+    SBC_TSD_THR_DEFAULT                     = 0x00U,
+    SBC_TSD_THR_HIGHER
+};
+
+typedef enum
+{
+    SBC_ICC1_LIM_ADJ_750MA                  = 0x00U,
+    SBC_ICC1_LIM_ADJ_1000MA,
+    SBC_ICC1_LIM_ADJ_1200MA,
+    SBC_ICC1_LIM_ADJ_1500MA
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* ==========   Selective Wake Control Registers Enumerations        ============== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SWK_CTRL  ------------------------------------ */
+
+typedef enum
+{ 
+    SBC_OSC_CAL_DISABLED                    = 0x00U,
+    SBC_OSC_CAL_ENABLED
+};
+
+typedef enum
+{
+    SBC_TRIM_EN_LOCKED                      = 0x00U,
+    SBC_TRIM_EN_UNLOCKED                    = 0x03U
+};
+
+typedef enum
+{
+    SBC_CANTO_MASK_NOINT                    = 0x00U,
+    SBC_CANTO_MASK_INT_ON_TO
+};
+
+typedef enum
+{
+    SBC_CFG_VAL_NOTVALID                    = 0x00U,
+    SBC_CFG_VAL_VALID
+};
+
+
+/* --------------------------------  SWK_ID0_CTRL --------------------------------- */
+
+typedef enum
+{
+    SBC_RTR_NORMAL_DATA_FRAME               = 0x00U,
+    SBC_RTR_REMOTE_TRANSMIT_REQUEST
+};
+
+typedef enum
+{
+    SBC_IDE_STANDARD                         = 0x00U,
+    SBC_IDE_EXTENDED
+};
+
+
+/* --------------------------------  SWK_DLC_CTRL --------------------------------- */
+
+typedef enum
+{
+    SBC_DLC_0BYTES                          = 0x00U,
+    SBC_DLC_1BYTES,
+    SBC_DLC_2BYTES,
+    SBC_DLC_3BYTES,
+    SBC_DLC_4BYTES,
+    SBC_DLC_5BYTES,
+    SBC_DLC_6BYTES,
+    SBC_DLC_7BYTES,
+    SBC_DLC_8BYTES
+};
+
+
+/* --------------------------------  SWK_CAN_FD_CTRL ------------------------------ */
+
+typedef enum
+{
+    SBC_DIS_ERR_CNT_ENABLED                 = 0x00U,
+    SBC_DIS_ERR_CNT_DISABLED
+};
+
+typedef enum
+{
+    SBC_RX_FILT_BYP_NOTBYPASSED             = 0x00U,
+    SBC_RX_FILT_BYP_BYPASSED
+};
+
+typedef enum
+{
+    SBC_FD_FILTER_50NS                      = 0x00U,
+    SBC_FD_FILTER_100NS,
+    SBC_FD_FILTER_150NS,
+    SBC_FD_FILTER_200NS,
+    SBC_FD_FILTER_250NS,
+    SBC_FD_FILTER_300NS,
+    SBC_FD_FILTER_350NS,
+    SBC_FD_FILTER_700NS
+};
+
+typedef enum
+{
+    SBC_CAN_FD_EN_DISABLED                  = 0x00U,
+    SBC_CAN_FD_EN_ENABLED
+};
+
+
+/* --------------------------------  SWK_OPT_CTRL --------------------------------- */
+
+typedef enum
+{ 
+    SBC_RX_WK_SEL_LOWPOWER                  = 0x00U,
+    SBC_RX_WK_SEL_STANDARD
+};
+
+
+/* --------------------------------  SWK_CDR_CTRL1 -------------------------------- */
+
+typedef enum
+{ 
+    SBC_SEL_FILT_TC8                        = 0x00U,
+    SBC_SEL_FILT_TC16,
+    SBC_SEL_FILT_TC32,
+    SBC_SEL_FILT_ADAPT
+};
+
+typedef enum
+{
+    SBC_CDR_EN_DISABLED                     = 0x00U,
+    SBC_CDR_EN_ENABLED
+};
+
+
+/* --------------------------------  SWK_CDR_CTRL2 -------------------------------- */
+
+typedef enum
+{
+    SBC_SEL_OSC_CLK_80MHZ                   = 0x00U,
+    SBC_SEL_OSC_CLK_40MHZ,
+    SBC_SEL_OSC_CLK_20MHZ,
+    SBC_SEL_OSC_CLK_10MHZ
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* ==========   General Status Information Registers Enumerations        ========== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SUP_STAT_1  ---------------------------------- */
+
+typedef enum
+{
+    SBC_VS_UV_NOEVENT                       = 0x00U,
+    SBC_VS_UV_EVENT
+};
+
+typedef enum
+{
+    SBC_VS_OV_NOEVENT                       = 0x00U,
+    SBC_VS_OV_EVENT
+};
+
+typedef enum
+{ 
+    SBC_VCC1_OV_NOEVENT                     = 0x00U,
+    SBC_VCC1_OV_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_UV_PREWARN_NOEVENT             = 0x00U,
+    SBC_VCC1_UV_PREWARN_EVENT
+};
+
+
+/* --------------------------------  SUP_STAT_0 ----------------------------------- */
+
+typedef enum
+{
+    SBC_POR_NOEVENT                         = 0x00U,
+    SBC_POR_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC2_OT_NOEVENT                     = 0x00U,
+    SBC_VCC2_OT_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC2_UV_NOEVENT                     = 0x00U,
+    SBC_VCC2_UV_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_SC_NOEVENT                     = 0x00U,
+    SBC_VCC1_SC_TO_GND_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_UV_NOEVENT                     = 0x00U,
+    SBC_VCC1_UV_EVENT
+};
+
+
+/* --------------------------------  THERM_STAT ----------------------------------- */
+
+typedef enum
+{
+    SBC_TSD2_SAFE_NOSAFESTATE               = 0x00U,
+    SBC_TSD2_SAFE_SAFESTATE_DETECTED
+};
+
+typedef enum
+{
+    SBC_TSD2_NOEVENT                        = 0x00U,
+    SBC_TSD2_EVENT
+};
+
+typedef enum
+{
+    SBC_TSD1_NOEVENT                        = 0x00U,
+    SBC_TSD1_EVENT
+};
+
+typedef enum
+{
+    SBC_TPW_NOEVENT                         = 0x00U,
+    SBC_TPW_EVENT
+};
+
+
+/* --------------------------------  DEV_STAT ------------------------------------- */
+
+typedef enum
+{
+    SBC_DEV_STAT_CLEARED                    = 0x00U,
+    SBC_DEV_STAT_RESTART_AFTER_FAIL,
+    SBC_DEV_STAT_SLEEP_MODE
+};
+
+typedef enum
+{
+    SBC_WD_FAIL_NOFAIL                      = 0x00U,
+    SBC_WD_FAIL_1FAIL,
+    SBC_WD_FAIL_2FAIL
+};
+
+typedef enum
+{
+    SBC_SPI_FAIL_NOEVENT                    = 0x00U,
+    SBC_SPI_FAIL_EVENT
+};
+
+typedef enum
+{
+    SBC_FAILURE_NOEVENT                     = 0x00U,
+    SBC_FAILURE_EVENT
+};
+
+
+/* --------------------------------  BUS_STAT ------------------------------------- */
+
+typedef enum
+{
+    SBC_CANTO_NORMAL                        = 0x00U,
+    SBC_CANTO_TIMEOUT
+};
+
+typedef enum
+{
+    SBC_SYSERR_NOEVENT                      = 0x00U,
+    SBC_SYSERR_DETECTED
+};
+
+typedef enum
+{
+    SBC_CAN_FAIL_NO_FAIL                    = 0x00U,
+    SBC_CAN_FAIL_TSD,
+    SBC_CAN_FAIL_TXD_DOM_TO,
+    SBC_CAN_FAIL_BUS_DOM_TO
+};
+
+typedef enum
+{
+    SBC_VCAN_UV_NOEVENT                     = 0x00U,
+    SBC_VCAN_UV_EVENT
+};
+
+
+/* --------------------------------  WK_STAT_0 ------------------------------------ */
+
+typedef enum
+{
+    SBC_CAN_WU_NOEVENT                      = 0x00U,
+    SBC_CAN_WU_EVENT
+};
+
+typedef enum
+{
+    SBC_TIMER_WU_NOEVENT                    = 0x00U,
+    SBC_TIMER_WU_EVENT
+};
+
+typedef enum
+{
+    SBC_WK_WU_NOEVENT                       = 0x00U,
+    SBC_WK_WU_EVENT
+};
+
+
+/* --------------------------------  WK_STAT_1 ------------------------------------ */
+
+typedef enum
+{
+    SBC_GPIO_WK_WU_NOEVENT                  = 0x00U,
+    SBC_GPIO_WK_WU_EVENT
+};
+
+
+/* --------------------------------  WK_LVL_STAT ---------------------------------- */
+
+typedef enum
+{
+    SBC_DEV_LVL_NORMAL                      = 0x00U,
+    SBC_DEV_LVL_DEVELOPMENT_MODE
+};
+
+typedef enum
+{
+    SBC_CFG0_STATE_CONFIG_2_4               = 0x00U,
+    SBC_CFG0_STATE_CONFIG_1_3
+};
+
+typedef enum
+{
+    SBC_GPIO_LVL_LOW                        = 0x00U,
+    SBC_GPIO_LVL_HIGH
+};
+
+typedef enum
+{
+    SBC_WK_LVL_LOW                          = 0x00U,
+    SBC_WK_LVL_HIGH
+};
+
+
+/* --------------------------------  GPIO_OC_STAT --------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_OC_NOEVENT                     = 0x00U,
+    SBC_GPIO_OC_EVENT
+};
+
+
+/* --------------------------------  GPIO_OL_STAT --------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_OL_NOEVENT                     = 0x00U,
+    SBC_GPIO_OL_EVENT
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* =============   Selective Wake Status Registers Enumerations        ============ */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SWK_STAT  ------------------------------------ */
+
+typedef enum
+{
+    SBC_SYNC_NOT_SYNCHRONOUS                = 0x00U,
+    SBC_SYNC_VALID_FRAME_RECEIVED
+};
+
+typedef enum
+{
+    SBC_CANSIL_NOT_EXCEEDED                 = 0x00U,
+    SBC_CANSIL_EXCEEDED
+};
+
+typedef enum
+{
+    SBC_SWK_SET_SWK_NOT_ACTIVE              = 0x00U,
+    SBC_SWK_SET_SWK_ACTIVE
+};
+
+typedef enum
+{
+    SBC_WUP_NO_WUP                          = 0x00U,
+    SBC_WUP_DETECTED
+};
+
+typedef enum
+{
+    SBC_WUF_NO_WUF                          = 0x00U,
+    SBC_WUF_DETECTED
+};
+
+
+/* --------------------------------  SWK_ECNT_STAT  ------------------------------ */
+
+typedef enum
+{
+    SBC_ECNT_NOEVENT                        = 0x00U,
+    SBC_ECNT_31_FRAME_ERRORS                = 0x1FU,
+    SBC_ECNT_ERROR_OVERFLOW                 = 0x20U
+};
+
+
+/* ================================================================================ */
+/* ========   Family and Product Information Registers Enumerations        ======== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  FAM_PROD_STAT  ------------------------------- */
+
+typedef enum
+{
+    SBC_FAM_DRIVER                          = 0x01U,
+    SBC_FAM_DCDC,
+    SBC_FAM_MIDRANGE,
+    SBC_FAM_MULTICAN,
+    SBC_FAM_LITE,
+    SBC_FAM_MIDRANGEPLUS                    = 0x07U
+};
+
+typedef enum
+{
+    SBC_PROD_TLE9461                        = 0x06U,
+    SBC_PROD_TLE9461V33,
+    SBC_PROD_TLE9471                        = 0x0EU,
+    SBC_PROD_TLE9471V33
+};
+
+
+#endif  /* TLE94x1_DEFINES_H */
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1_ISR.h b/cva_bootloader_m0146/src/TLE9461/TLE94x1_ISR.h
new file mode 100644
index 0000000..b40bbbe
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1_ISR.h
@@ -0,0 +1,127 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_ISR.h
+ *
+ * @brief       Declaration file for ISR-Vectors and ISR related functions
+ * 
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+
+#ifndef TLE94x1_ISR_H
+#define TLE94x1_ISR_H
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES   ================================== */
+/* ================================================================================ */ 
+
+#include "TLE94x1_DEFINES.h"
+
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================================   MACROS   ==================================== */
+/* ================================================================================ */ 
+
+
+/**
+ * @def     SBC_ISR_VECTOR
+ *
+ * @brief   Vector defining the handling of interrupts.
+ * 
+ *          Vectors of this type have to be registered by the SBC_Register_Callback method.
+ */
+#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE)    ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE))
+
+
+
+
+
+
+/* ================================================================================ */
+/* =======================   General Interrupt Defines   ========================== */
+/* ================================================================================ */ 
+
+
+
+/* Interrupts based on WK_STAT_0 and WK_STAT_1 register are always available */
+#define SBC_ISR_CAN_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_CAN_WU_Msk,       SBC_WK_STAT_0_CAN_WU_Pos,       SBC_CAN_WU_EVENT)
+#define SBC_ISR_TIMER_WU                        SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_TIMER_WU_Msk,     SBC_WK_STAT_0_TIMER_WU_Pos,     SBC_TIMER_WU_EVENT)
+#define SBC_ISR_WK_WU                           SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_WK_WU_Msk,        SBC_WK_STAT_0_WK_WU_Pos,        SBC_WK_WU_EVENT)
+#define SBC_ISR_GPIO_WK_WU                      SBC_ISR_VECTOR(SBC_WK_STAT_1,       SBC_WK_STAT_1_GPIO_WK_WU_Msk,   SBC_WK_STAT_1_GPIO_WK_WU_Pos,   SBC_GPIO_WK_WU_EVENT)
+
+
+/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */
+#define SBC_ISR_VS_UV                           SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VS_UV_Msk,       SBC_SUP_STAT_1_VS_UV_Pos,       SBC_VS_UV_EVENT)
+#define SBC_ISR_VS_OV                           SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VS_OV_Msk,       SBC_SUP_STAT_1_VS_OV_Pos,       SBC_VS_OV_EVENT)
+#define SBC_ISR_VCC1_OV                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VCC1_OV_Msk,     SBC_SUP_STAT_1_VCC1_OV_Pos,     SBC_VCC1_OV_EVENT)
+#define SBC_ISR_VCC1_UV_PREWARN                 SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VCC1_WARN_Msk,   SBC_SUP_STAT_1_VCC1_WARN_Pos,   SBC_VCC1_UV_PREWARN_EVENT)
+#define SBC_ISR_VCC2_OT                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC2_OT_Msk,     SBC_SUP_STAT_0_VCC2_OT_Pos,     SBC_VCC2_OT_EVENT)
+#define SBC_ISR_VCC2_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC2_UV_Msk,     SBC_SUP_STAT_0_VCC2_UV_Pos,     SBC_VCC2_UV_EVENT)
+#define SBC_ISR_VCC1_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC1_UV_Msk,     SBC_SUP_STAT_0_VCC1_UV_Pos,     SBC_VCC1_UV_EVENT)
+#define SBC_ISR_TSD2_SAFESTATE                  SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TSD2_SAFE_Msk,   SBC_THERM_STAT_TSD2_SAFE_Pos,   SBC_TSD2_SAFE_SAFESTATE_DETECTED)
+#define SBC_ISR_TSD1                            SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TSD1_Msk,        SBC_THERM_STAT_TSD1_Pos,        SBC_TSD1_EVENT)
+#define SBC_ISR_TPW                             SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TPW_Msk,         SBC_THERM_STAT_TPW_Pos,         SBC_TPW_EVENT)
+#define SBC_ISR_RESTART_AFTER_FAIL              SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_DEV_STAT_Msk,      SBC_DEV_STAT_DEV_STAT_Pos,      SBC_DEV_STAT_RESTART_AFTER_FAIL)
+#define SBC_ISR_FROM_SLEEPMODE                  SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_DEV_STAT_Msk,      SBC_DEV_STAT_DEV_STAT_Pos,      SBC_DEV_STAT_SLEEP_MODE)
+#define SBC_ISR_WD_FAIL_1                       SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_WD_FAIL_Msk,       SBC_DEV_STAT_WD_FAIL_Pos,       SBC_WD_FAIL_1FAIL)
+#define SBC_ISR_WD_FAIL_2                       SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_WD_FAIL_Msk,       SBC_DEV_STAT_WD_FAIL_Pos,       SBC_WD_FAIL_2FAIL)
+#define SBC_ISR_FAILURE                         SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_FAILURE_Msk,       SBC_DEV_STAT_FAILURE_Pos,       SBC_FAILURE_EVENT)
+#define SBC_ISR_CAN_TSD                         SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_TSD)
+#define SBC_ISR_CAN_TXD_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_TXD_DOM_TO)
+#define SBC_ISR_CAN_BUS_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_BUS_DOM_TO)
+#define SBC_ISR_VCAN_UV                         SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_VCAN_UV_Msk,       SBC_BUS_STAT_VCAN_UV_Pos,       SBC_VCAN_UV_EVENT)
+#define SBC_ISR_GPIO_OC                         SBC_ISR_VECTOR(SBC_GPIO_OC_STAT,    SBC_GPIO_OC_STAT_GPIO_OC_Msk,   SBC_GPIO_OC_STAT_GPIO_OC_Pos,   SBC_GPIO_OC_EVENT)
+#define SBC_ISR_GPIO_OL                         SBC_ISR_VECTOR(SBC_GPIO_OL_STAT,    SBC_GPIO_OL_STAT_GPIO_OL_Msk,   SBC_GPIO_OL_STAT_GPIO_OL_Pos,   SBC_GPIO_OL_EVENT)
+
+
+#endif  /*TLE94x1_ISR_H*/
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.c b/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.c
new file mode 100644
index 0000000..a6aefc8
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.c
@@ -0,0 +1,156 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_SPI.c
+ *
+ * @brief       Implementation of all SPI related functions
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+#include "TLE94x1_SPI.h"
+#include "mcu.h"
+
+void SPI2_PortInit(void);
+
+
+
+
+/* ================================================================================ */
+/* =======================   SPI communication functions     ====================== */
+/* ================================================================================ */ 
+
+
+uint8_t spitxbuf[10],spirxbuf[10];
+extern McuType mcu;
+uint8_t SBC_SPI_INIT(void) {
+    SpiDrv_InitCfgType masterCfg;
+
+    SPI2_PortInit();
+
+    SpiDrv_GetDefaultConfig(&masterCfg);
+    masterCfg.basicParameters.isMasterNode = true;
+    masterCfg.basicParameters.baudRate     = 1000000ul;
+    //masterCfg.basicParameters.clockPolarity = SPIDRV_CLK_POLARITY_IDLE_IN_HIGH;
+    masterCfg.basicParameters.clockPhase    = SPIDRV_CLK_PHASE_DATA_SAMPLE_ON_TRAILING_EDGE;
+
+    while(ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SPI2, &masterCfg.basicParameters.busClockFreq) == false)
+    {
+        ;
+    }
+    SpiDrv_SetConfig(&mcu.spiDrv2, &masterCfg);
+
+    SpiDrv_SetRxFifoWaterMask(&mcu.spiDrv2, 0);
+    //SpiDrv_SetIsrConfig(&mcu.spiDrv2, SPIDRV_ISR_SRC_RX_DATA, true);
+
+    /* Enable the SPI interrupts */
+    //IrqDrv_EnableIrq(SPI2_IRQn);
+    return 0;
+}
+
+
+
+uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) {
+    uint16_t ret;
+    //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_LOW);
+    spitxbuf[0] = Upper;
+    spitxbuf[1] = Lower;
+    //SpiDrv_AsyncContinueFrameTransfer(&mcu.spiDrv2,2,spitxbuf,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE);
+    SpiDrv_MasterSyncTransfer(&mcu.spiDrv2,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE,2,spitxbuf,spirxbuf);
+    //LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,spitxbuf,spirxbuf,2,10);
+    ret = spirxbuf[0];
+    ret <<= 8;
+    ret |= spirxbuf[1];
+    //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_HIGH);
+    return ret;
+}
+
+
+/********************CVA SPI DRV**********************/
+
+void SPI2_Handler(void)
+{
+    if(SpiDrv_GetStatus(&mcu.spiDrv2, SPIDRV_STATUS_RX_DATA) == true && SpiDrv_GetIsrConfig(&mcu.spiDrv2, SPIDRV_ISR_SRC_RX_DATA) == true)
+    {
+        //spi0IrqCnt++;
+        //uint8_t len = SpiDrv_AsyncReceive(&mcu.spiDrv2, (void *)masterRxBuff, true);
+    }
+}
+
+void SPI2_PortInit(void)
+{
+    /* SPI2 CS */
+    PinsDrv_SetMuxModeSel(&mcu.ptc, 14, PINSDRV_MUX_ALT3);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.ptc.port, 14, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.ptc.port, 14, 1);
+
+    /* SPI2 CLK */
+    PinsDrv_SetMuxModeSel(&mcu.ptc, 15, PINSDRV_MUX_ALT3);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.ptc.port, 15, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.ptc.port, 15, 1);
+
+    /* SPI2 SIN */
+    PinsDrv_SetMuxModeSel(&mcu.ptc, 0, PINSDRV_MUX_ALT3);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.ptc.port, 0, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.ptc.port, 0, 1);
+
+    /* SPI2 SOUT */
+    PinsDrv_SetMuxModeSel(&mcu.ptc, 1, PINSDRV_MUX_ALT3);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.ptc.port, 1, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.ptc.port, 1, 1);
+}
+
+void SPI_TEST_TASK(void)
+{
+    
+}
\ No newline at end of file
diff --git a/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.h b/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.h
new file mode 100644
index 0000000..abf88cc
--- /dev/null
+++ b/cva_bootloader_m0146/src/TLE9461/TLE94x1_SPI.h
@@ -0,0 +1,95 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_SPI.h
+ *
+ * @brief       Declaration file for TLE94x1 SBC family device SPI functions
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+ 
+#ifndef TLE94x1_SPI_H
+#define TLE94x1_SPI_H
+ 
+
+
+
+
+ 
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+#include <stdint.h>
+
+
+
+/* ================================================================================ */
+/* =============================   SPI Functions     ============================== */
+/* ================================================================================ */
+
+/**
+ * @brief   IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
+ * 
+ *          The function has to initialze the SPI of the uC and will be called once during SBC_Init().
+ *          In case, the SPI hardware is already initialized by some other code before, it can be left blank.
+ * 
+ * @retval  Method has to return 0 if initialization was successful.
+ */
+uint8_t SBC_SPI_INIT(void);
+
+/**
+ * @brief   IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
+ * 
+ *          The function will be called by the library everytime when a SPI communication is needed.
+ *          The function proceeds a bidirectional 16-bit transfer to/from the SBC  .
+ *          As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments.
+ *          For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples.
+ * 
+ * @param   Upper   The first 8 bit to transmit to the SBC.
+ * @param   Lower   The second 8 bit to transmit to the SBC.
+ * @retval  The function will return all 16 bits received from the SBC. 
+ *          Bit[15:8] are the first 8 bits received (Status-Information-Field).
+ *          Bit[7:0] is the data-field transmitted of the SBC.
+ */	
+uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower);
+
+#endif /* TLE94x1_SPI_H */
diff --git a/cva_bootloader_m0146/src/main.c b/cva_bootloader_m0146/src/main.c
index fce60ce..4854a96 100644
--- a/cva_bootloader_m0146/src/main.c
+++ b/cva_bootloader_m0146/src/main.c
@@ -28,6 +28,8 @@
 #include "bootloader.h"
 #include "fls.h"
 #include "private_driver/uds/user/uds_user.h"
+#include "SEGGER_RTT.h"
+#include "TLE94x1.h"
 
 /*******************************************************************************
  * the defines
@@ -537,12 +539,7 @@ void FlexCanBoot_Init(void)
 
     flexCanDrv_DemoObj = &mcu.flexCanDrv0;
 
-    /* set PTC1 MUX as GPIO */
-    PinsDrv_SetMuxModeSel(&mcu.ptc, 1, PINSDRV_MUX_AS_GPIO);
-    /* set PTC1 as GPIO output */
-    PinsDrv_SetPinDirection(&mcu.ptc, 1, 1);
-    /* set PTC1 as high to control CAN transceiver STB */
-    PinsDrv_WritePin(&mcu.ptc, 1, 0);
+
 
     /* set PTC1 MUX as GPIO */
     PinsDrv_SetMuxModeSel(&mcu.ptd, 1, PINSDRV_MUX_AS_GPIO);
@@ -559,10 +556,10 @@ void FlexCanBoot_Init(void)
     PinsDrv_WritePin(&mcu.pte, 7, 0);
 
     /* set PTE4 as MUX 5 - CAN0.RX */
-    PinsDrv_SetMuxModeSel(&mcu.pte, 4, PINSDRV_MUX_ALT5);
+    PinsDrv_SetMuxModeSel(&mcu.ptb, 0, PINSDRV_MUX_ALT5);
 
     /* set PTE5 as MUX 5 - CAN0.TX */
-    PinsDrv_SetMuxModeSel(&mcu.pte, 5, PINSDRV_MUX_ALT5);
+    PinsDrv_SetMuxModeSel(&mcu.ptb, 1, PINSDRV_MUX_ALT5);
 
     flexCanCfg.clkSrc               = FLEXCANDRV_CLKSRC_CHICLK;
     flexCanCfg.fdEnable             = false;
@@ -743,6 +740,9 @@ int main(void)
     FlexCan_FrameStructureType rxMsg;
     /* Setup the clock */
     ClockDrv_ModuleClkConfigType clockConfig;
+    uint32_t ret;
+    uint32_t rollingcounter,temp;
+    uint32_t tTcr       = 0;
 
     IrqDrv_DisableGlobalInterrupt();
 
@@ -755,11 +755,7 @@ int main(void)
     memset(&flexCan_DataInfo, 0, sizeof(flexCan_DataInfo));
     memset(&flexCanCfg, 0, sizeof(flexCanCfg));
 
-    /* Setup the Pll div2 clock */
-    clockConfig.gating = true;
-    clockConfig.source = CLOCKDRV_PLL;
-    clockConfig.div    = 1;
-    ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
+    SEGGER_RTT_Init();
 
     /* Enable the clock for all port peripheral */
     clockConfig.gating = true;
@@ -770,15 +766,40 @@ int main(void)
     ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig);
     ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig);
 
+    /* Setup the Pll div2 clock */
+    clockConfig.gating = true;
+    clockConfig.source = CLOCKDRV_PLL;
+    clockConfig.div    = 1;
+    ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
+
+
+    /* Setup the SPI clock */
+    clockConfig.gating = true;
+    clockConfig.source = CLOCKDRV_PLL_DIV2;
+    ret = ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI2, &clockConfig);
+
+    tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv2.reg);
+
+    SpiDrv_SetPrescaler(&tTcr,0x03);
+
+    //SEGGER_RTT_printf(0,"ret = %d\n",ret);
+    //SEGGER_RTT_printf(0,"-----SBC_SPI_INIT-----\n");
+
+    SBC_SPI_INIT();
+
+
+    SBC_Init();
+    //SBC_Mode_Normal();
+
     /* get CAN controller default configuration */
     FlexCanDrv_GetDefaultCfg(&flexCanCfg);
     flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
     flexCanCfg.msgCfg = msgCfgObj;
     FlexCanBoot_Init();
-    PinsDrv_SetMuxModeSel(&mcu.ptd, 1, PINSDRV_MUX_AS_GPIO);
-    PinsDrv_SetPinDirection(&mcu.ptd, 1, 1);
-    PinsDrv_SetPullSel(&mcu.ptd, 1, PINSDRV_INTERNAL_PULL_UP);
-    PinsDrv_WritePin(&mcu.ptd, 1, 0);
+    PinsDrv_SetMuxModeSel(&mcu.ptb, 5, PINSDRV_MUX_AS_GPIO);
+    PinsDrv_SetPinDirection(&mcu.ptb, 5, 1);
+    PinsDrv_SetPullSel(&mcu.ptb, 5, PINSDRV_INTERNAL_PULL_UP);
+    PinsDrv_WritePin(&mcu.ptb, 5, 0);
 
     /* UDS init */
     Uds_UserInit(&udsObj, &udsParam);
@@ -793,28 +814,43 @@ int main(void)
 
     IrqDrv_EnableGlobalInterrupt();
 
+    
+
     while(1)
     {
         if(gSystick1msEvent > 0u)
         {
             gSystick1msEvent = 0;
             gSystick1msCnt++;
+            if (gSystick1msCnt % 10 == 0)
+            {
+                SBC_WD_Trigger();
+            }
 
-            if(gSystick1msCnt >= 500)
+            if (gSystick1msCnt % 500 == 0)
+            {
+                FlexCanBoot_TxMessage(UDS_TEXT_TX_MSG_ID,testdata,8);
+            }
+            
+
+            if(gSystick1msCnt >= 5000)
             {
                 gSystick1msCnt = 0;
                 /* Test Io */
                 if(gTestIoEn == 0)
                 {
                     gTestIoEn = 1;
-                    PinsDrv_WritePin(&mcu.ptd, 1, 1);
+                    //PinsDrv_WritePin(&mcu.ptb, 5, 1);
                 }
                 else
                 {
                     gTestIoEn = 0;
-                    PinsDrv_WritePin(&mcu.ptd, 1, 0);
+                    //PinsDrv_WritePin(&mcu.ptb, 5, 0);
                 }
-                //FlexCanBoot_TxMessage(UDS_TEXT_TX_MSG_ID,testdata,8);
+
+                ret = SBC_Read_Command(SBC_M_S_CTRL);
+                SEGGER_RTT_printf(0,"%04d : FAM_PROD_STAT = %x\n",rollingcounter++,ret);
+                
             }
 
            
diff --git a/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.c b/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.c
index e3566b6..92932a3 100644
--- a/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.c
+++ b/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.c
@@ -305,11 +305,12 @@ const ClockDrv_ModuleClkFuncType c_clockFuncTable[CLOCKDRV_CLOCK_NUM] = {
     {GET_FREQ_FUNC(Cmuf),     CONFIG_CLOCK_FUNC(Cmuf)    }, /* CLOCKDRV_CMUF */
     {GET_FREQ_FUNC(Fccu),     CONFIG_CLOCK_FUNC(Fccu)    }, /* CLOCKDRV_FCCU */
     {GET_FREQ_FUNC(Cmup),     CONFIG_CLOCK_FUNC(Cmup)    }, /* CLOCKDRV_CMUP */
-#if 0
+
     {GET_FREQ_FUNC(I2C),      CONFIG_CLOCK_FUNC(I2C)     }, /* CLOCKDRV_I2C */
     {GET_FREQ_FUNC(Spi0),     CONFIG_CLOCK_FUNC(Spi0)    }, /* CLOCKDRV_SPI0 */
     {GET_FREQ_FUNC(Spi1),     CONFIG_CLOCK_FUNC(Spi1)    }, /* CLOCKDRV_SPI1 */
     {GET_FREQ_FUNC(Spi2),     CONFIG_CLOCK_FUNC(Spi2)    }, /* CLOCKDRV_SPI2 */
+#if 0
     {GET_FREQ_FUNC(Spi3),     CONFIG_CLOCK_FUNC(Spi3)    }, /* CLOCKDRV_SPI3 */
     {GET_FREQ_FUNC(Uart0),    CONFIG_CLOCK_FUNC(Uart0)   }, /* CLOCKDRV_UART0 */
     {GET_FREQ_FUNC(Uart1),    CONFIG_CLOCK_FUNC(Uart1)   }, /* CLOCKDRV_UART1 */
diff --git a/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.h b/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.h
index ae1bff9..679130e 100644
--- a/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.h
+++ b/cva_bootloader_m0146/src/private_driver/drivers/clock/clock_drv.h
@@ -125,11 +125,12 @@ typedef enum
     CLOCKDRV_CMUF,     /* CMUF clock */
     CLOCKDRV_FCCU,     /* FCCU clock */
     CLOCKDRV_CMUP,     /* CMUP clock */
-#if 0    
+  
     CLOCKDRV_I2C,      /* I2C clock */
     CLOCKDRV_SPI0,     /* SPI0 clock */
     CLOCKDRV_SPI1,     /* SPI1 clock */
     CLOCKDRV_SPI2,     /* SPI2 clock */
+    #if 0  
     CLOCKDRV_SPI3,     /* SPI3 clock */
     CLOCKDRV_UART0,    /* UART0 clock */
     CLOCKDRV_UART1,    /* UART1 clock */
diff --git a/cva_bootloader_m0146/src/private_driver/mcu.c b/cva_bootloader_m0146/src/private_driver/mcu.c
index f24b249..5028dc7 100644
--- a/cva_bootloader_m0146/src/private_driver/mcu.c
+++ b/cva_bootloader_m0146/src/private_driver/mcu.c
@@ -83,6 +83,10 @@ void Mcu_Init(McuType *obj)
     /* Initialize reset driver */
     ResetDrv_Init(&obj->resetDrv, RCM, PCC, APC);
 
+    SpiDrv_Init(&obj->spiDrv2, SPI2);
+
     /* Initialize watchdog driver */
     WdgDrv_Init(&obj->wdgDrv, WDG);
+
+    
 }