/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _EIM_REG_H_
#define _EIM_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the EIM Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* CR Bit Fields */
#define EIM_CR_GEIEN_MASK         (0x01u)
#define EIM_CR_GEIEN_SHIFT        (0u)
#define EIM_CR_GEIEN_WIDTH        (1u)

/* CHEN Bit Fields */
#define EIM_CH_EN_CH0_MASK        (0x01u)
#define EIM_CH_EN_CH0_SHIFT       (0u)
#define EIM_CH_EN_CH0_WIDTH       (1u)

/* CH0_DATAH Bit Fields */
#define EIM_CH0_DATAH_DATAH_MASK  (0xFF000000u)
#define EIM_CH0_DATAH_DATAH_SHIFT (24u)
#define EIM_CH0_DATAH_DATAH_WIDTH (8u)

/* CH0_DATAL Bit Fields */
#define EIM_CH0_DATAL_DATAL_MASK  (0xFFFFFFFFu)
#define EIM_CH0_DATAL_DATAL_SHIFT (0u)
#define EIM_CH0_DATAL_DATAL_WIDTH (32u)

/* CH0_DATAM Bit Fields */
#define EIM_CH0_DATAM_DATAM_MASK  (0xFFFFFFFFu)
#define EIM_CH0_DATAM_DATAM_SHIFT (0u)
#define EIM_CH0_DATAM_DATAM_WIDTH (32u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of EIM registers
 */
typedef struct _EimRegType_
{
    volatile uint32_t CR;            /*!< Control, Error in Control Register, offset: 0x0 */
    volatile uint32_t CH_EN;         /*!< Control, Error in channel enable Register, offset: 0x4 */
    uint32_t          RESERVED0[62]; /*!< Reserverd block, offset: 0x8 */
    volatile uint32_t CH0_DATAH;     /*!< CH0 data bits[71:64] error injection enable, offset: 0x100 */
    volatile uint32_t CH0_DATAL;     /*!< CH0 data bits[31:0] error injection enable, offset: 0x0x104 */
    volatile uint32_t CH0_DATAM;     /*!< CH0 data bits[63:32] error injection enable, offset: 0x0x108 */
} EimRegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the Global Error Injection Enable
 *
 * This function gets the current Global Error Injection Enable.
 * This bit globally enables or disables the error injection function of the EIM.
 * This field is initialized by hardware reset.
 *
 * \param[in] obj : pointer to EIM register instance
 * \return Global Error Injection Enable
 *         - 0b : Disabled
 *         - 1b : Enabled
 */
__attribute__((always_inline)) static inline uint8_t EimReg_GetCrGeiEn(const EimRegType *obj)
{
    return ((obj->CR & EIM_CR_GEIEN_MASK) >> EIM_CR_GEIEN_SHIFT);
}

/*! \brief Sets the Global Error Injection Enable
 *
 * This function sets the Global Error Injection Enable.
 * This bit globally enables or disables the error injection function of the EIM.
 * This field is initialized by hardware reset.
 *
 * \param[in] obj : pointer to EIM register instance
 * \param[in] value : the value of Global Error Injection Enable
 *                    - 0b : Disabled
 *                    - 1b : Enabled
 */
__attribute__((always_inline)) static inline void EimReg_SetCrGeiEn(EimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CR;

    tmp &= ~EIM_CR_GEIEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << EIM_CR_GEIEN_SHIFT)) & EIM_CR_GEIEN_MASK);
    obj->CR = tmp;
}

/*! \brief Gets the Error Injection Channel 0 Enable
 *
 * This function gets the current Error Injection Channel 0 Enable.
 * This field enables the corresponding error injection channel.
 * The Global Error Injection Enable (EIMCR[GEIEN]) field must also be asserted to enable error injection.
 * After error injection is enabled, all subsequent read accesses incur one or more bit inversions as defined
 * in the corresponding EIM_CHn_* registers.
 * Error injection remains in effect until the error injection channel is manually disabled via software.
 *
 * \param[in] obj : pointer to EIM register instance
 * \return Error Injection Channel 0 Enable
 *         - 0b : Error injection is disabled on Error Injection Channel 0
 *         - 1b : Error injection is enabled on Error Injection Channel 0
 */
__attribute__((always_inline)) static inline uint8_t EimReg_GetChEnCh0(const EimRegType *obj)
{
    return ((obj->CH_EN & EIM_CH_EN_CH0_MASK) >> EIM_CH_EN_CH0_SHIFT);
}

/*! \brief Sets the Error Injection Channel 0 Enable
 *
 * This function sets the Error Injection Channel 0 Enable.
 * This field enables the corresponding error injection channel.
 * The Global Error Injection Enable (EIMCR[GEIEN]) field must also be asserted to enable error injection.
 * After error injection is enabled, all subsequent read accesses incur one or more bit inversions
 * as defined in the corresponding EIM_CHn_* registers.
 * Error injection remains in effect until the error injection channel is manually disabled via software.
 *
 * \param[in] obj : pointer to EIM register instance
 * \param[in] value : the value of Error Injection Channel 0 Enable
 *                    - 0b : Error injection is disabled on Error Injection Channel 0
 *                    - 1b : Error injection is enabled on Error Injection Channel 0
 */
__attribute__((always_inline)) static inline void EimReg_SetChEnCh0(EimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CH_EN;

    tmp &= ~EIM_CH_EN_CH0_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << EIM_CH_EN_CH0_SHIFT)) & EIM_CH_EN_CH0_MASK);
    obj->CH_EN = tmp;
}

/*! \brief Gets the Data Inversion Enable [71:64]
 *
 * This function gets the current Data Inversion Enable [71:64].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \return Data Inversion Enable [71:64]
 *         - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *         - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline uint8_t EimReg_GetCh0DataH(const EimRegType *obj)
{
    return ((obj->CH0_DATAH & EIM_CH0_DATAH_DATAH_MASK) >> EIM_CH0_DATAH_DATAH_SHIFT);
}

/*! \brief Sets the Data Inversion Enable [71:64]
 *
 * This function sets the Data Inversion Enable [71:64].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \param[in] value : the value of Data Inversion Enable [71:64]
 *                    - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *                    - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline void EimReg_SetCh0DataH(EimRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CH0_DATAH;

    tmp &= ~EIM_CH0_DATAH_DATAH_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << EIM_CH0_DATAH_DATAH_SHIFT)) & EIM_CH0_DATAH_DATAH_MASK);
    obj->CH0_DATAH = tmp;
}

/*! \brief Gets the Data Inversion Enable [31:0]
 *
 * This function gets the current Data Inversion Enable [31:0].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \return Data Inversion Enable [31:0]
 *         - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *         - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline uint32_t EimReg_GetCh0DataL(const EimRegType *obj)
{
    return ((obj->CH0_DATAL & EIM_CH0_DATAL_DATAL_MASK) >> EIM_CH0_DATAL_DATAL_SHIFT);
}

/*! \brief Sets the Data Inversion Enable [31:0]
 *
 * This function sets the Data Inversion Enable [31:0].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \param[in] value : the value of Data Inversion Enable [31:0]
 *                    - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *                    - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline void EimReg_SetCh0DataL(EimRegType *obj, uint32_t value)
{
    uint32_t tmp = obj->CH0_DATAL;

    tmp &= ~EIM_CH0_DATAL_DATAL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << EIM_CH0_DATAL_DATAL_SHIFT)) & EIM_CH0_DATAL_DATAL_MASK);
    obj->CH0_DATAL = tmp;
}

/*! \brief Gets the Data Inversion Enable [63:32]
 *
 * This function gets the current Data Inversion Enable [63:32].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \return Data Inversion Enable [63:32]
 *         - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *         - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline uint32_t EimReg_GetCh0DataM(const EimRegType *obj)
{
    return ((obj->CH0_DATAM & EIM_CH0_DATAM_DATAM_MASK) >> EIM_CH0_DATAM_DATAM_SHIFT);
}

/*! \brief Sets the Data Inversion Enable [63:32]
 *
 * This function sets the Data Inversion Enable [63:32].
 * This field defines a bit-mapped mask that specifies whether the corresponding bit of the read data bus
 * from the target RAM should be inverted or remain unmodified.
 * Writes to unimplemented bits are ignored.
 *
 * \param[in] obj : pointer to EIM register instance
 * \param[in] value : the value of Data Inversion Enable [63:32]
 *                    - 0b  : The corresponding bit of the checkbit bus remains unmodified.
 *                    - 1b  : The corresponding bit of the checkbit bus is inverted.
 */
__attribute__((always_inline)) static inline void EimReg_SetCh0DataM(EimRegType *obj, uint32_t value)
{
    uint32_t tmp = obj->CH0_DATAM;

    tmp &= ~EIM_CH0_DATAM_DATAM_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << EIM_CH0_DATAM_DATAM_SHIFT)) & EIM_CH0_DATAM_DATAM_MASK);
    obj->CH0_DATAM = tmp;
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _EIM_REG_H_ */
