/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _FLEXCAN_REG_H_
#define _FLEXCAN_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the FLEXCAN Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/
#define MESSAGE_BUFFER_ADDR_OFF         (0x80UL)

#define MESSAGE_BUFFER_CS_WORD_NUM      (0)
#define MESSAGE_BUFFER_ID_WORD_NUM      (1)

/* message buffer CS field */
#define MESSAGE_BUFFER_CS_EDL_SHIFT     (31U)
#define MESSAGE_BUFFER_CS_EDL_MASK      (0x1UL << MESSAGE_BUFFER_CS_EDL_SHIFT)
#define MESSAGE_BUFFER_CS_BRS_SHIFT     (30U)
#define MESSAGE_BUFFER_CS_BRS_MASK      (0x1UL << MESSAGE_BUFFER_CS_BRS_SHIFT)
#define MESSAGE_BUFFER_CS_CODE_SHIFT    (24U)
#define MESSAGE_BUFFER_CS_CODE_MASK     (0xFUL << MESSAGE_BUFFER_CS_CODE_SHIFT)
#define MESSAGE_BUFFER_CS_SRR_SHIFT     (22U)
#define MESSAGE_BUFFER_CS_SRR_MASK      (0x1UL << MESSAGE_BUFFER_CS_SRR_SHIFT)
#define MESSAGE_BUFFER_CS_IDE_SHIFT     (21U)
#define MESSAGE_BUFFER_CS_IDE_MASK      (0x1UL << MESSAGE_BUFFER_CS_IDE_SHIFT)
#define MESSAGE_BUFFER_CS_DLC_SHIFT     (16U)
#define MESSAGE_BUFFER_CS_DLC_MASK      (0xFUL << MESSAGE_BUFFER_CS_DLC_SHIFT)

/* message buffer ID field */
#define MESSAGE_BUFFER_ID_EXT_ID_SHIFT  (0U)
#define MESSAGE_BUFFER_ID_EXT_ID_MASK   (0x1FFFFFFFUL << MESSAGE_BUFFER_ID_EXT_ID_SHIFT)
#define MESSAGE_BUFFER_ID_STD_ID_SHIFT  (18U)
#define MESSAGE_BUFFER_ID_STD_ID_MASK   (0x7FFUL << MESSAGE_BUFFER_ID_STD_ID_SHIFT)

/* MCR register */
#define FLEXCAN_MCR_MDIS_SHIFT          (31U)
#define FLEXCAN_MCR_MDIS_MASK           (0x1UL << FLEXCAN_MCR_MDIS_SHIFT)
#define FLEXCAN_MCR_MDIS_WIDTH          (1u)
#define FLEXCAN_MCR_FRZ_SHIFT           (30U)
#define FLEXCAN_MCR_FRZ_MASK            (0x1UL << FLEXCAN_MCR_FRZ_SHIFT)
#define FLEXCAN_MCR_FRZ_WIDTH           (1u)
#define FLEXCAN_MCR_RFEN_SHIFT          (29U)
#define FLEXCAN_MCR_RFEN_MASK           (0x1UL << FLEXCAN_MCR_RFEN_SHIFT)
#define FLEXCAN_MCR_RFEN_WIDTH          (1u)
#define FLEXCAN_MCR_HALT_SHIFT          (28U)
#define FLEXCAN_MCR_HALT_MASK           (0x1UL << FLEXCAN_MCR_HALT_SHIFT)
#define FLEXCAN_MCR_HALT_WIDTH          (1u)
#define FLEXCAN_MCR_NOTRDY_SHIFT        (27U)
#define FLEXCAN_MCR_NOTRDY_MASK         (0x1UL << FLEXCAN_MCR_NOTRDY_SHIFT)
#define FLEXCAN_MCR_WAKMSK_SHIFT        (26U)
#define FLEXCAN_MCR_WAKMSK_MASK         (0x1UL << FLEXCAN_MCR_WAKMSK_SHIFT)
#define FLEXCAN_MCR_SOFTRST_SHIFT       (25U)
#define FLEXCAN_MCR_SOFTRST_MASK        (0x1UL << FLEXCAN_MCR_SOFTRST_SHIFT)
#define FLEXCAN_MCR_SOFTRST_WIDTH       (1u)
#define FLEXCAN_MCR_FRZACK_SHIFT        (24U)
#define FLEXCAN_MCR_FRZACK_MASK         (0x1UL << FLEXCAN_MCR_FRZACK_SHIFT)
#define FLEXCAN_MCR_FRZACK_WIDTH        (1u)
#define FLEXCAN_MCR_SUPV_SHIFT          (23U)
#define FLEXCAN_MCR_SUPV_MASK           (0x1UL << FLEXCAN_MCR_SUPV_SHIFT)
#define FLEXCAN_MCR_SUPV_WIDTH          (1u)
#define FLEXCAN_MCR_SLFWAK_SHIFT        (22U)
#define FLEXCAN_MCR_SLFWAK_MASK         (0x1UL << FLEXCAN_MCR_SLFWAK_SHIFT)
#define FLEXCAN_MCR_SLFWAK_WIDTH        (1u)
#define FLEXCAN_MCR_WRNEN_SHIFT         (21U)
#define FLEXCAN_MCR_WRNEN_MASK          (0x1UL << FLEXCAN_MCR_WRNEN_SHIFT)
#define FLEXCAN_MCR_WRNEN_WIDTH         (1u)
#define FLEXCAN_MCR_LPMACK_SHIFT        (20U)
#define FLEXCAN_MCR_LPMACK_MASK         (0x1UL << FLEXCAN_MCR_LPMACK_SHIFT)
#define FLEXCAN_MCR_LPMACK_WIDTH        (1u)
#define FLEXCAN_MCR_WAKSRC_SHIFT        (19U)
#define FLEXCAN_MCR_WAKSRC_MASK         (0x1UL << FLEXCAN_MCR_WAKSRC_SHIFT)
#define FLEXCAN_MCR_WAKSRC_WIDTH        (1u)
#define FLEXCAN_MCR_DOZE_SHIFT          (18U)
#define FLEXCAN_MCR_DOZE_MASK           (0x1UL << FLEXCAN_MCR_DOZE_SHIFT)
#define FLEXCAN_MCR_DOZE_WIDTH          (1u)
#define FLEXCAN_MCR_SRXDIS_SHIFT        (17U)
#define FLEXCAN_MCR_SRXDIS_MASK         (0x1UL << FLEXCAN_MCR_SRXDIS_SHIFT)
#define FLEXCAN_MCR_SRXDIS_WIDTH        (1u)
#define FLEXCAN_MCR_IRQM_SHIFT          (16U)
#define FLEXCAN_MCR_IRQM_MASK           (0x1UL << FLEXCAN_MCR_IRQM_SHIFT)
#define FLEXCAN_MCR_IRMQ_WIDTH          (1u)
#define FLEXCAN_MCR_DMA_SHIFT           (15U)
#define FLEXCAN_MCR_DMA_MASK            (0x1UL << FLEXCAN_MCR_DMA_SHIFT)
#define FLEXCAN_MCR_DMA_WIDTH           (1u)
#define FLEXCAN_MCR_LPRIOEN_MASK        (0x2000u)
#define FLEXCAN_MCR_LPRIOEN_SHIFT       (13u)
#define FLEXCAN_MCR_LPRIOEN_WIDTH       (1u)
#define FLEXCAN_MCR_AEN_SHIFT           (12U)
#define FLEXCAN_MCR_AEN_MASK            (0x1UL << FLEXCAN_MCR_AEN_SHIFT)
#define FELXCAN_MCR_AEN_WIDTH           (1U)
#define FLEXCAN_MCR_FDEN_SHIFT          (11U)
#define FLEXCAN_MCR_FDEN_MASK           (0x1UL << FLEXCAN_MCR_FDEN_SHIFT)
#define FLEXCAN_MCR_FDEN_WIDTH          (1u)
#define FLEXCAN_MCR_IDAM_SHIFT          (8UL)
#define FLEXCAN_MCR_IDAM_MASK           (0x3UL << FLEXCAN_MCR_IDAM_SHIFT)
#define FLEXCAN_MCR_IDAM_WIDTH          (2U)
#define FLEXCAN_MCR_MAXMB_SHIFT         (0U)
#define FLEXCAN_MCR_MAXMB_MASK          (0x7FUL << FLEXCAN_MCR_MAXMB_SHIFT)
#define FLEXCAN_MCR_MAXMB_WIDTH         (7u)

/* CTRL1 register */
#define FLEXCAN_CTRL1_PRESDIV_MASK      (0xFF000000u)
#define FLEXCAN_CTRL1_PRESDIV_SHIFT     (24u)
#define FLEXCAN_CTRL1_PRESDIV_WIDTH     (8u)
#define FLEXCAN_CTRL1_RJW_MASK          (0xC00000u)
#define FLEXCAN_CTRL1_RJW_SHIFT         (22u)
#define FLEXCAN_CTRL1_RJW_WIDTH         (2u)
#define FLEXCAN_CTRL1_PSEG1_MASK        (0x380000u)
#define FLEXCAN_CTRL1_PSEG1_SHIFT       (19u)
#define FLEXCAN_CTRL1_PSEG1_WIDTH       (3u)
#define FLEXCAN_CTRL1_PSEG2_MASK        (0x70000u)
#define FLEXCAN_CTRL1_PSEG2_SHIFT       (16u)
#define FLEXCAN_CTRL1_PSEG2_WIDTH       (3u)
#define FLEXCAN_CTRL1_BOFFMSK_SHIFT     (15U)
#define FLEXCAN_CTRL1_BOFFMSK_MASK      (0x1UL << FLEXCAN_CTRL1_BOFFMSK_SHIFT)
#define FLEXCAN_CTRL1_BOFFMSK_WIDTH     (1U)
#define FLEXCAN_CTRL1_ERRMSK_SHIFT      (14U)
#define FLEXCAN_CTRL1_ERRMSK_MASK       (0x1UL << FLEXCAN_CTRL1_ERRMSK_SHIFT)
#define FLEXCAN_CTRL1_ERRMSK_WIDTH      (1UL)
#define FLEXCAN_CTRL1_CLKSRC_SHIFT      (13U)
#define FLEXCAN_CTRL1_CLKSRC_MASK       (0x1UL << FLEXCAN_CTRL1_CLKSRC_SHIFT)
#define FLEXCAN_CTRL1_CLKSRC_WIDTH      (1u)
#define FLEXCAN_CTRL1_LPB_SHIFT         (12U)
#define FLEXCAN_CTRL1_LPB_MASK          (0x1UL << FLEXCAN_CTRL1_LPB_SHIFT)
#define FLEXCAN_CTRL1_LPB_WIDTH         (1u)
#define FLEXCAN_CTRL1_TWRNMSK_SHIFT     (11U)
#define FLEXCAN_CTRL1_TWRNMSK_MASK      (0x1UL << FLEXCAN_CTRL1_TWRNMSK_SHIFT)
#define FLEXCAN_CTRL1_TWRNMSK_WIDTH     (1U)
#define FLEXCAN_CTRL1_RWRNMSK_SHIFT     (10U)
#define FLEXCAN_CTRL1_RWRNMSK_MASK      (1UL << FLEXCAN_CTRL1_RWRNMSK_SHIFT)
#define FLEXCAN_CTRL1_RWRNMSK_WIDTH     (1U)
#define FLEXCAN_CTRL1_SMP_SHIFT         (7U)
#define FLEXCAN_CTRL1_SMP_MASK          (1UL << FLEXCAN_CTRL1_SMP_SHIFT)
#define FLEXCAN_CTRL1_SMP_WIDTH         (1U)
#define FLEXCAN_CTRL1_BOFFREC_SHIFT     (6U)
#define FLEXCAN_CTRL1_BOFFREC_MASK      (1UL << FLEXCAN_CTRL1_BOFFREC_SHIFT)
#define FLEXCAN_CTRL1_BOFFREC_WIDTH     (1U)
#define FLEXCAN_CTRL1_TSYN_SHIFT        (5U)
#define FLEXCAN_CTRL1_TSYN_MASK         (0x1UL << FLEXCAN_CTRL1_TSYN_SHIFT)
#define FLEXCAN_CTRL1_TSYN_WIDTH        (1U)
#define FLEXCAN_CTRL1_LBUF_SHIFT        (4U)
#define FLEXCAN_CTRL1_LBUF_MASK         (0x1UL << FLEXCAN_CTRL1_LBUF_SHIFT)
#define FLEXCAN_CTRL1_LBUF_WIDTH        (1U)
#define FLEXCAN_CTRL1_LOM_SHIFT         (3U)
#define FLEXCAN_CTRL1_LOM_MASK          (0x1UL << FLEXCAN_CTRL1_LOM_SHIFT)
#define FLEXCAN_CTRL1_LOM_WIDTH         (1U)
#define FLEXCAN_CTRL1_PROPSEG_MASK      (0x07u)
#define FLEXCAN_CTRL1_PROPSEG_SHIFT     (0u)
#define FLEXCAN_CTRL1_PROPSEG_WIDTH     (3u)

/* TIMER register */
#define FLEXCAN_TIMER_TIMER_MASK        (0xFFFFu)
#define FLEXCAN_TIMER_TIMER_SHIFT       (0u)
#define FLEXCAN_TIMER_TIMER_WIDTH       (16u)

/* RXMGMASK register */
#define FLEXCAN_RXMGMASK_MG_MASK        (0xFFFFFFFFu)
#define FLEXCAN_RXMGMASK_MG_SHIFT       (0u)
#define FLEXCAN_RXMGMASK_MG_WIDTH       (32u)

/* RX14MASK register */
#define FLEXCAN_RX14MASK_RX14M_MASK     (0xFFFFFFFFu)
#define FLEXCAN_RX14MASK_RX14M_SHIFT    (0u)
#define FLEXCAN_RX14MASK_RX14M_WIDTH    (32u)

/* RX15MASK register */
#define FLEXCAN_RX15MASK_RX15M_MASK     (0xFFFFFFFFu)
#define FLEXCAN_RX15MASK_RX15M_SHIFT    (0u)
#define FLEXCAN_RX15MASK_RX15M_WIDTH    (32u)

/* ECR register */
#define FLEXCAN_ECR_RXERRCNTFAST_MASK   (0xFF000000u)
#define FLEXCAN_ECR_RXERRCNTFAST_SHIFT  (24u)
#define FLEXCAN_ECR_RXERRCNTFAST_WIDTH  (8u)
#define FLEXCAN_ECR_TXERRCNTFAST_MASK   (0xFF0000u)
#define FLEXCAN_ECR_TXERRCNTFAST_SHIFT  (16u)
#define FLEXCAN_ECR_TXERRCNTFAST_WIDTH  (8u)
#define FLEXCAN_ECR_RXERRCNT_MASK       (0xFF00u)
#define FLEXCAN_ECR_RXERRCNT_SHIFT      (8u)
#define FLEXCAN_ECR_RXERRCNT_WIDTH      (8u)
#define FLEXCAN_ECR_TXERRCNT_MASK       (0xFFu)
#define FLEXCAN_ECR_TXERRCNT_SHIFT      (0u)
#define FLEXCAN_ECR_TXERRCNT_WIDTH      (8u)

/* ESR1 register */
#define FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
#define FLEXCAN_ESR1_BIT1ERR_FAST_MASK  (1UL << FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT)
#define FLEXCAN_ESR1_BIT1ERR_FAST_WIDTH (1U)
#define FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
#define FLEXCAN_ESR1_BIT0ERR_FAST_MASK  (1UL << FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT)
#define FLEXCAN_ESR1_BIT0ERR_FAST_WIDTH (1U)
#define FLEXCAN_ESR1_CRCERR_FAST_SHIFT  (28U)
#define FLEXCAN_ESR1_CRCERR_FAST_MASK   (1UL << FLEXCAN_ESR1_CRCERR_FAST_SHIFT)
#define FLEXCAN_ESR1_CRCERR_FAST_WIDTH  (1U)
#define FLEXCAN_ESR1_FRMERR_FAST_SHIFT  (27U)
#define FLEXCAN_ESR1_FRMERR_FAST_MASK   (1UL << FLEXCAN_ESR1_FRMERR_FAST_SHIFT)
#define FLEXCAN_ESR1_FRMERR_FAST_WIDTH  (1U)
#define FLEXCAN_ESR1_STFERR_FAST_SHIFT  (26U)
#define FLEXCAN_ESR1_STFERR_FAST_MASK   (1UL << FLEXCAN_ESR1_STFERR_FAST_SHIFT)
#define FLEXCAN_ESR1_STFERR_FAST_WIDTH  (1U)
#define FLEXCAN_ESR1_ERROVR_SHIFT       (21U)
#define FLEXCAN_ESR1_ERROVR_MASK        (1UL << FLEXCAN_ESR1_ERROVR_SHIFT)
#define FLEXCAN_ESR1_ERROVR_WIDTH       (1U)
#define FLEXCAN_ESR1_ERRINT_FAST_SHIFT  (20U)
#define FLEXCAN_ESR1_ERRINT_FAST_MASK   (1UL << FLEXCAN_ESR1_ERRINT_FAST_SHIFT)
#define FLEXCAN_ESR1_ERRINT_FAST_WIDTH  (1U)
#define FLEXCAN_ESR1_BOFFDONEINT_SHIFT  (19U)
#define FLEXCAN_ESR1_BOFFDONEINT_MASK   (1UL << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)
#define FLEXCAN_ESR1_BOFFDONEINT_WIDTH  (1U)
#define FLEXCAN_ESR1_SYNCH_SHIFT        (18U)
#define FLEXCAN_ESR1_SYNCH_MASK         (1UL << FLEXCAN_ESR1_SYNCH_SHIFT)
#define FLEXCAN_ESR1_SYNCH_WIDTH        (1U)
#define FLEXCAN_ESR1_TWRNINT_SHIFT      (17U)
#define FLEXCAN_ESR1_TWRNINT_MASK       (1UL << FLEXCAN_ESR1_TWRNINT_SHIFT)
#define FLEXCAN_ESR1_TWRNINT_WIDTH      (1U)
#define FLEXCAN_ESR1_RWRNINT_SHIFT      (16U)
#define FLEXCAN_ESR1_RWRNINT_MASK       (1UL << FLEXCAN_ESR1_RWRNINT_SHIFT)
#define FLEXCAN_ESR1_RWRNINT_WIDTH      (1U)
#define FLEXCAN_ESR1_BIT1ERR_SHIFT      (15U)
#define FLEXCAN_ESR1_BIT1ERR_MASK       (1UL << FLEXCAN_ESR1_BIT1ERR_SHIFT)
#define FLEXCAN_ESR1_BIT1ERR_WIDTH      (1U)
#define FLEXCAN_ESR1_BIT0ERR_SHIFT      (14U)
#define FLEXCAN_ESR1_BIT0ERR_MASK       (1UL << FLEXCAN_ESR1_BIT0ERR_SHIFT)
#define FLEXCAN_ESR1_BIT0ERR_WIDTH      (1U)
#define FLEXCAN_ESR1_ACKERR_SHIFT       (13U)
#define FLEXCAN_ESR1_ACKERR_MASK        (1UL << FLEXCAN_ESR1_ACKERR_SHIFT)
#define FLEXCAN_ESR1_ACKERR_WIDTH       (1U)
#define FLEXCAN_ESR1_CRCERR_SHIFT       (12U)
#define FLEXCAN_ESR1_CRCERR_MASK        (1UL << FLEXCAN_ESR1_CRCERR_SHIFT)
#define FLEXCAN_ESR1_CRCERR_WIDTH       (1U)
#define FLEXCAN_ESR1_FRMERR_SHIFT       (11U)
#define FLEXCAN_ESR1_FRMERR_MASK        (1UL << FLEXCAN_ESR1_FRMERR_SHIFT)
#define FLEXCAN_ESR1_FRMERR_WIDTH       (1U)
#define FLEXCAN_ESR1_STFERR_SHIFT       (10U)
#define FLEXCAN_ESR1_STFERR_MASK        (1UL << FLEXCAN_ESR1_STFERR_SHIFT)
#define FLEXCAN_ESR1_STFERR_WIDTH       (1U)
#define FLEXCAN_ESR1_TXWRN_SHIFT        (9U)
#define FLEXCAN_ESR1_TXWRN_MASK         (0x1UL << FLEXCAN_ESR1_TXWRN_SHIFT)
#define FLEXCAN_ESR1_TXWRN_WIDTH        (1U)
#define FLEXCAN_ESR1_RXWRN_SHIFT        (8U)
#define FLEXCAN_ESR1_RXWRN_MASK         (0x1UL << FLEXCAN_ESR1_RXWRN_SHIFT)
#define FLEXCAN_ESR1_RXWRN_WIDTH        (1U)
#define FLEXCAN_ESR1_IDLE_SHIFT         (7U)
#define FLEXCAN_ESR1_IDLE_MASK          (1UL << FLEXCAN_ESR1_IDLE_SHIFT)
#define FLEXCAN_ESR1_IDLE_WIDTH         (1U)
#define FLEXCAN_ESR1_TX_SHIFT           (6U)
#define FLEXCAN_ESR1_TX_MASK            (1UL << FLEXCAN_ESR1_TX_SHIFT)
#define FLEXCAN_ESR1_TX_WIDTH           (1U)
#define FLEXCAN_ESR1_FLTCONF_SHIFT      (4U)
#define FLEXCAN_ESR1_FLTCONF_MASK       (3UL << FLEXCAN_ESR1_FLTCONF_SHIFT)
#define FLEXCAN_ESR1_FLTCONF_WIDTH      (2U)
#define FLEXCAN_ESR1_RX_SHIFT           (3U)
#define FLEXCAN_ESR1_RX_MASK            (1UL << FLEXCAN_ESR1_RX_SHIFT)
#define FLEXCAN_ESR1_RX_WIDTH           (1U)
#define FLEXCAN_ESR1_BOFFINT_SHIFT      (2U)
#define FLEXCAN_ESR1_BOFFINT_MASK       (0x1UL << FLEXCAN_ESR1_BOFFINT_SHIFT)
#define FLEXCAN_ESR1_BOFFINT_WIDTH      (1U)
#define FLEXCAN_ESR1_ERRINT_SHIFT       (1U)
#define FLEXCAN_ESR1_ERRINT_MASK        (0x1UL << FLEXCAN_ESR1_ERRINT_SHIFT)
#define FLEXCAN_ESR1_ERRINT_WIDTH       (1U)
#define FLEXCAN_ESR1_WAKINT_SHIFT       (0U)
#define FLEXCAN_ESR1_WAKINT_MASK        (0x1UL << FLEXCAN_ESR1_WAKINT_SHIFT)
#define FLEXCAN_ESR1_WAKINT_WIDTH       (1U)

/* CTRL2 register */
#define FLEXCAN_CTRL2_ERRMSKFAST_MASK   (0x80000000u)
#define FLEXCAN_CTRL2_ERRMSKFAST_SHIFT  (31u)
#define FLEXCAN_CTRL2_ERRMSKFAST_WIDTH  (1u)
#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK  (0x40000000u)
#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30u)
#define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH (1u)
#define FLEXCAN_CTRL2_ECRWRE_SHIFT      (29U)
#define FLEXCAN_CTRL2_ECRWRE_MASK       (0x1UL << FLEXCAN_CTRL2_ECRWRE_SHIFT)
#define FLEXCAN_CTRL2_ECRWRE_WIDTH      (1u)
#define FLEXCAN_CTRL2_WRMFRZ_SHIFT      (28U)
#define FLEXCAN_CTRL2_WRMFRZ_MASK       (0x1UL << FLEXCAN_CTRL2_WRMFRZ_SHIFT)
#define FLEXCAN_CTRL2_WRMFRZ_WIDTH      (1u)
#define FLEXCAN_CTRL2_RFFN_SHIFT        (24U)
#define FLEXCAN_CTRL2_RFFN_MASK         (0xFUL << FLEXCAN_CTRL2_RFFN_SHIFT)
#define FLEXCAN_CTRL2_RFFN_WIDTH        (4U)
#define FLEXCAN_CTRL2_TASD_MASK         (0xF80000u)
#define FLEXCAN_CTRL2_TASD_SHIFT        (19u)
#define FLEXCAN_CTRL2_TASD_WIDTH        (5u)
#define FLEXCAN_CTRL2_MRP_MASK          (0x40000u)
#define FLEXCAN_CTRL2_MRP_SHIFT         (18u)
#define FLEXCAN_CTRL2_MRP_WIDTH         (1u)
#define FLEXCAN_CTRL2_RRS_MASK          (0x20000u)
#define FLEXCAN_CTRL2_RRS_SHIFT         (17u)
#define FLEXCAN_CTRL2_RRS_WIDTH         (1u)
#define FLEXCAN_CTRL2_EACEN_MASK        (0x10000u)
#define FLEXCAN_CTRL2_EACEN_SHIFT       (16u)
#define FLEXCAN_CTRL2_EACEN_WIDTH       (1u)
#define FLEXCAN_CTRL2_TIMERSRC_MASK     (0x8000u)
#define FLEXCAN_CTRL2_TIMERSRC_SHIFT    (15u)
#define FLEXCAN_CTRL2_TIMERSRC_WIDTH    (1u)
#define FLEXCAN_CTRL2_PREXCEN_MASK      (0x4000u)
#define FLEXCAN_CTRL2_PREXCEN_SHIFT     (14u)
#define FLEXCAN_CTRL2_PREXCEN_WIDTH     (1u)
#define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT  (12U)
#define FLEXCAN_CTRL2_ISOCANFDEN_MASK   (0x1UL << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT)
#define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH  (1u)
#define FLEXCAN_CTRL2_EDFLTDIS_MASK     (0x800u)
#define FLEXCAN_CTRL2_EDFLTDIS_SHIFT    (11u)
#define FLEXCAN_CTRL2_EDFLTDIS_WIDTH    (1u)

/* ESR2 register */
#define FLEXCAN_ESR2_LPTM_MASK          (0x7F0000u)
#define FLEXCAN_ESR2_LPTM_SHIFT         (16u)
#define FLEXCAN_ESR2_LPTM_WIDTH         (7u)
#define FLEXCAN_ESR2_VPS_MASK           (0x4000u)
#define FLEXCAN_ESR2_VPS_SHIFT          (14u)
#define FLEXCAN_ESR2_VPS_WIDTH          (1u)
#define FLEXCAN_ESR2_IMB_MASK           (0x2000u)
#define FLEXCAN_ESR2_IMB_SHIFT          (13u)
#define FLEXCAN_ESR2_IMB_WIDTH          (1u)

/* CRCR register */
#define FLEXCAN_CRCR_MBCRC_MASK         (0x7F0000u)
#define FLEXCAN_CRCR_MBCRC_SHIFT        (16u)
#define FLEXCAN_CRCR_MBCRC_WIDTH        (7u)
#define FLEXCAN_CRCR_TXCRC_MASK         (0x7FFFu)
#define FLEXCAN_CRCR_TXCRC_SHIFT        (0u)
#define FLEXCAN_CRCR_TXCRC_WIDTH        (15u)

/* RXFGMASK register */
#define FLEXCAN_RXFGMASK_FGM_MASK       (0xFFFFFFFFu)
#define FLEXCAN_RXFGMASK_FGM_SHIFT      (0u)
#define FLEXCAN_RXFGMASK_FGM_WIDTH      (32u)

/* RXFIR register */
#define FLEXCAN_RXFIR_IDHIT_MASK        (0x1FFu)
#define FLEXCAN_RXFIR_IDHIT_SHIFT       (0u)
#define FLEXCAN_RXFIR_IDHIT_WIDTH       (9u)

/* CBT register */
#define FLEXCAN_CBT_BTF_SHIFT           (31U)
#define FLEXCAN_CBT_BTF_MASK            (0x1UL << FLEXCAN_CBT_BTF_SHIFT)
#define FLEXCAN_CBT_BTF_WIDTH           (1u)
#define FLEXCAN_CBT_EPRESDIV_SHIFT      (21U)
#define FLEXCAN_CBT_EPRESDIV_MASK       (0x3FFUL << FLEXCAN_CBT_EPRESDIV_SHIFT)
#define FLEXCAN_CBT_EPRESDIV_WIDTH      (10u)
#define FLEXCAN_CBT_ERJW_SHIFT          (16U)
#define FLEXCAN_CBT_ERJW_MASK           (0x1FUL << FLEXCAN_CBT_ERJW_SHIFT)
#define FLEXCAN_CBT_ERJW_WIDTH          (5u)
#define FLEXCAN_CBT_EPROPSEG_SHIFT      (10U)
#define FLEXCAN_CBT_EPROPSEG_MASK       (0x3FUL << FLEXCAN_CBT_EPROPSEG_SHIFT)
#define FLEXCAN_CBT_EPROPSEG_WIDTH      (6u)
#define FLEXCAN_CBT_EPSEG1_SHIFT        (5U)
#define FLEXCAN_CBT_EPSEG1_MASK         (0x1FUL << FLEXCAN_CBT_EPSEG1_SHIFT)
#define FLEXCAN_CBT_EPSEG1_WIDTH        (5u)
#define FLEXCAN_CBT_EPSEG2_SHIFT        (0U)
#define FLEXCAN_CBT_EPSEG2_MASK         (0x1FUL << FLEXCAN_CBT_EPSEG2_SHIFT)
#define FLEXCAN_CBT_EPSEG2_WIDTH        (5u)

/* IMASK4 register */
#define FLEXCAN_IMASK4_BUF127TO96M_MASK  (0xFFFFFFFFu)
#define FLEXCAN_IMASK4_BUF127TO96M_SHIFT (0u)
#define FLEXCAN_IMASK4_BUF127TO96M_WIDTH (32u)

/* IMASK3 register */
#define FLEXCAN_IMASK3_BUF95TO64M_MASK   (0xFFFFFFFFu)
#define FLEXCAN_IMASK3_BUF95TO64M_SHIFT  (0u)
#define FLEXCAN_IMASK3_BUF95TO64M_WIDTH  (32u)

/* IFLAG4 register */
#define FLEXCAN_IFLAG4_BUF127TO96_MASK   (0xFFFFFFFFu)
#define FLEXCAN_IFLAG4_BUF127TO96_SHIFT  (0u)
#define FLEXCAN_IFLAG4_BUF127TO96_WIDTH  (32u)

/* IFLAG3 register */
#define FLEXCAN_IFLAG3_BUF95TO64_MASK    (0xFFFFFFFFu)
#define FLEXCAN_IFLAG3_BUF95TO64_SHIFT   (0u)
#define FLEXCAN_IFLAG3_BUF95TO64_WIDTH   (32u)

/* RXIMRN register */
#define FLEXCAN_RXIMRN_MI_MASK           (0xFFFFFFFFu)
#define FLEXCAN_RXIMRN_MI_SHIFT          (0u)
#define FLEXCAN_RXIMRN_MI_WIDTH          (32u)

/* MECR register */
#define FLEXCAN_MECR_ECRWRDIS_SHIFT     (31U)
#define FLEXCAN_MECR_ECRWRDIS_MASK      (0x1UL << FLEXCAN_MECR_ECRWRDIS_SHIFT)
#define FLEXCAN_MECR_ECRWRDIS_WIDTH     (1u)
#define FLEXCAN_MECR_HANCEIMSK_MASK     (0x80000u)
#define FLEXCAN_MECR_HANCEIMSK_SHIFT    (19u)
#define FLEXCAN_MECR_HANCEIMSK_WIDTH    (1u)
#define FLEXCAN_MECR_FANCEIMSK_MASK     (0x40000u)
#define FLEXCAN_MECR_FANCEIMSK_SHIFT    (18u)
#define FLEXCAN_MECR_FANCEIMSK_WIDTH    (1u)
#define FLEXCAN_MECR_CEIMSK_MASK        (0x10000u)
#define FLEXCAN_MECR_CEIMSK_SHIFT       (16u)
#define FLEXCAN_MECR_CEIMSK_WIDTH       (1u)
#define FLEXCAN_MECR_HAERRIE_MASK       (0x8000u)
#define FLEXCAN_MECR_HAERRIE_SHIFT      (15u)
#define FLEXCAN_MECR_HAERRIE_WIDTH      (1u)
#define FLEXCAN_MECR_FAERRIE_MASK       (0x4000u)
#define FLEXCAN_MECR_FAERRIE_SHIFT      (14u)
#define FLEXCAN_MECR_FAERRIE_WIDTH      (1u)
#define FLEXCAN_MECR_EXTERRIE_MASK      (0x2000u)
#define FLEXCAN_MECR_EXTERRIE_SHIFT     (13u)
#define FLEXCAN_MECR_EXTERRIE_WIDTH     (1u)
#define FLEXCAN_MECR_RERRDIS_MASK       (0x200u)
#define FLEXCAN_MECR_RERRDIS_SHIFT      (9u)
#define FLEXCAN_MECR_RERRDIS_WIDTH      (1u)
#define FLEXCAN_MECR_ECCDIS_SHIFT       (8U)
#define FLEXCAN_MECR_ECCDIS_MASK        (0x1UL << FLEXCAN_MECR_ECCDIS_SHIFT)
#define FLEXCAN_MECR_ECCDIS_WIDTH       (1u)
#define FLEXCAN_MECR_NCEFAFRZ_SHIFT     (7U)
#define FLEXCAN_MECR_NCEFAFRZ_MASK      (0x1UL << FLEXCAN_MECR_NCEFAFRZ_SHIFT)
#define FLEXCAN_MECR_NCEFAFRZ_WIDTH     (1u)

/* FDCTRL register */
#define FLEXCAN_FDCTRL_FDRATE_SHIFT     (31U)
#define FLEXCAN_FDCTRL_FDRATE_MASK      (0x1UL << FLEXCAN_FDCTRL_FDRATE_SHIFT)
#define FLEXCAN_FDCTRL_FDRATE_WIDTH     (1u)
#define FLEXCAN_FDCTRL_MBDSR3_SHIFT     (25U)
#define FLEXCAN_FDCTRL_MBDSR3_MASK      (0x3UL << FLEXCAN_FDCTRL_MBDSR3_SHIFT)
#define FLEXCAN_FDCTRL_MBDSR3_WIDTH     (2u)
#define FLEXCAN_FDCTRL_MBDSR2_SHIFT     (22U)
#define FLEXCAN_FDCTRL_MBDSR2_MASK      (0x3UL << FLEXCAN_FDCTRL_MBDSR2_SHIFT)
#define FLEXCAN_FDCTRL_MBDSR2_WIDTH     (2u)
#define FLEXCAN_FDCTRL_MBDSR1_SHIFT     (19U)
#define FLEXCAN_FDCTRL_MBDSR1_MASK      (0x3UL << FLEXCAN_FDCTRL_MBDSR1_SHIFT)
#define FLEXCAN_FDCTRL_MBDSR1_WIDTH     (2u)
#define FLEXCAN_FDCTRL_MBDSR0_SHIFT     (16U)
#define FLEXCAN_FDCTRL_MBDSR0_MASK      (0x3UL << FLEXCAN_FDCTRL_MBDSR0_SHIFT)
#define FLEXCAN_FDCTRL_MBDSR0_WIDTH     (2u)
#define FLEXCAN_FDCTRL_TDCEN_SHIFT      (15U)
#define FLEXCAN_FDCTRL_TDCEN_MASK       (0x1UL << FLEXCAN_FDCTRL_TDCEN_SHIFT)
#define FLEXCAN_FDCTRL_TDCEN_WIDTH      (1u)
#define FLEXCAN_FDCTRL_TDCFAIL_MASK     (0x4000u)
#define FLEXCAN_FDCTRL_TDCFAIL_SHIFT    (14u)
#define FLEXCAN_FDCTRL_TDCFAIL_WIDTH    (1u)
#define FLEXCAN_FDCTRL_TDCOFF_SHIFT     (8U)
#define FLEXCAN_FDCTRL_TDCOFF_MASK      (0x1FUL << FLEXCAN_FDCTRL_TDCOFF_SHIFT)
#define FLEXCAN_FDCTRL_TDCOFF_WIDTH     (5u)
#define FLEXCAN_FDCTRL_TDCVAL_MASK      (0x3Fu)
#define FLEXCAN_FDCTRL_TDCVAL_SHIFT     (0u)
#define FLEXCAN_FDCTRL_TDCVAL_WIDTH     (6u)

/* FDCBT register */
#define FLEXCAN_FDCBT_FPRESDIV_SHIFT    (20U)
#define FLEXCAN_FDCBT_FPRESDIV_MASK     (0x3FFUL << FLEXCAN_FDCBT_FPRESDIV_SHIFT)
#define FLEXCAN_FDCBT_FPRESDIV_WIDTH    (10u)
#define FLEXCAN_FDCBT_FRJW_SHIFT        (16U)
#define FLEXCAN_FDCBT_FRJW_MASK         (0x7UL << FLEXCAN_FDCBT_FRJW_SHIFT)
#define FLEXCAN_FDCBT_FPJW_WIDTH        (3u)
#define FLEXCAN_FDCBT_FPROPSEG_SHIFT    (10U)
#define FLEXCAN_FDCBT_FPROPSEG_MASK     (0x1FUL << FLEXCAN_FDCBT_FPROPSEG_SHIFT)
#define FLEXCAN_FDCBT_FPROPSEG_WIDTH    (5u)
#define FLEXCAN_FDCBT_FPSEG1_SHIFT      (5U)
#define FLEXCAN_FDCBT_FPSEG1_MASK       (0x7UL << FLEXCAN_FDCBT_FPSEG1_SHIFT)
#define FLEXCAN_FDCBT_FPSEG1_WIDTH      (3u)
#define FLEXCAN_FDCBT_FPSEG2_SHIFT      (0U)
#define FLEXCAN_FDCBT_FPSEG2_MASK       (0x7UL << FLEXCAN_FDCBT_FPSEG2_SHIFT)
#define FLEXCAN_FDCBT_FPSEG2_WIDTH      (3u)

/* FDCRC register */
#define CAN_FDCRC_FDMBCRC_MASK          (0x7F000000u)
#define CAN_FDCRC_FDMBCRC_SHIFT         (24u)
#define CAN_FDCRC_FDMBCRC_WIDTH         (7u)
#define CAN_FDCRC_FDTXCRC_MASK          (0x1FFFFFu)
#define CAN_FDCRC_FDTXCRC_SHIFT         (0u)
#define CAN_FDCRC_FDTXCRC_WIDTH         (21u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of FLEXCAN registers
 */
typedef struct _FlexCanRegType_
{
    volatile uint32_t MCR;            /*!< module configuration register, offset: 0000H */
    volatile uint32_t CTRL1;          /*!< control1 register, offset: 0004H */
    volatile uint32_t TIMER;          /*!< free running timer register, offset: 0008H */
    volatile uint32_t REVERSED0;      /*!< resverd register, offset: 000CH */
    volatile uint32_t RXMGMASK;       /*!< rx mailbox global mask register, offset: 0010H */
    volatile uint32_t RX14MASK;       /*!< rx 14 mask register, offset: 0014H */
    volatile uint32_t RX15MASK;       /*!< rx 15 mask register, offset: 0018H */
    volatile uint32_t ECR;            /*!< error countner register, offset: 001CH */
    volatile uint32_t ESR1;           /*!< error and status 1 register, offset: 0020H */
    volatile uint32_t IMASK2;         /*!< interrupt mask 2 register, offset: 0024H */
    volatile uint32_t IMASK1;         /*!< interrupt mask 1 register, offset: 0028H */
    volatile uint32_t IFLAG2;         /*!< interrupt flags 2 register, offset: 002CH */
    volatile uint32_t IFLAG1;         /*!< interrupt flags 1 register, offset: 0030H */
    volatile uint32_t CTRL2;          /*!< control 2 register, offset: 0034H */
    volatile uint32_t ESR2;           /*!< error and status 2 register, offset: 0038H */
    volatile uint32_t REVERSED1[2];   /*!< reversed register, offset: 003CH */
    volatile uint32_t CRCR;           /*!< crc register, offset: 0044H */
    volatile uint32_t RXFGMASK;       /*!< rx fifo global mask register, offset: 0048H */
    volatile uint32_t RXFIR;          /*!< rx fifo information register, offset: 004CH */
    volatile uint32_t CBT;            /*!< CAN bit timing register, offset: 0050H */
    volatile uint32_t REVERSED2[5];   /*!< reversed register, offset: 0054H */
    volatile uint32_t IMASK4;         /*!< interrupt mask 4 register, offset: 0068H */
    volatile uint32_t IMASK3;         /*!< interrupt mask 3 register, offset: 006CH */
    volatile uint32_t IFLAG4;         /*!< interrupt flags 4 register, offset: 0070H */
    volatile uint32_t IFLAG3;         /*!< interrupt flags 3 register, offset: 0074H */
    volatile uint32_t REVERSED3[2];   /*!< reversed registers, offset: 0078H */
    volatile uint32_t MSGBUF[256];    /*!< message buffers, offset: 0080H */
	volatile uint32_t REVERSED4[256];  /*!< Reserved register, offset: 0x480 */
    volatile uint32_t RXIMR[64];      /*!< rx individual mask registers, offset: 0880H */
    volatile uint32_t REVERSED5[88];  /*!< reversed register, offset: 0980H */
    volatile uint32_t MECR;           /*!< memory error control register, offset: 0AE0H */
    volatile uint32_t ERRIAR;         /*!< error injection address register, offset: 0AE4H */
    volatile uint32_t ERRIDPR;        /*!< error injection data pattern register, offset: 0AE8H */
    volatile uint32_t ERRIPPR;        /*!< error injection parity pattern register, offset: 0AECH */
    volatile uint32_t RERRAR;         /*!< error report address register, offset: 0AF0H */
    volatile uint32_t RERRDR;         /*!< error report data register, offset: 0AF4H */
    volatile uint32_t RERRSYNR;       /*!< error report syndrome register, offset: 0AF8H */
    volatile uint32_t ERRSR;          /*!< error status register, offset: 0AFCH */
    volatile uint32_t CTRL1_PN;       /*!< pretended networking control 1 register, offset: 0B00H */
    volatile uint32_t CTRL2_PN;       /*!< pretended networking control 2 register, offset: 0B04H */
    volatile uint32_t WU_MTC;         /*!< pretended networking wake up match register, offset: 0B08H */
    volatile uint32_t FLT_ID1;        /*!< pretended networking ID filter 1 register, offset: 0B0CH */
    volatile uint32_t FLT_DLC;        /*!< pretended networking DLC filter register, offset: 0B10H */
    volatile uint32_t PL1_LO;         /*!< pretended networking payload low filter 1 register, offset: 0B14H */
    volatile uint32_t PL1_HI;         /*!< pretended networking payload high filter 1 register, offset: 0B18H */
    volatile uint32_t FLT_ID2_IDMASK; /*!< pretended networking ID filter 2 register / ID mask register, offset: 0B1CH */
    volatile uint32_t PL2_PLMASK_LO;  /*!< pretended networking payload low filter 2 register / payload low mask register, offset: 0B20H */
    volatile uint32_t PL2_PLMASK_HI;  /*!< pretended networking payload high filter 2 high order bits / payload high mask register, offset: 0B24H */
    volatile uint32_t REVERSED6[6];   /*!< reversed registers, offset: 0B28H */
    volatile uint32_t WMB0_CS;        /*!< wakeup message buffer 0 register for C/S, offset: 0B40H */
    volatile uint32_t WMB0_ID;        /*!< wakeup message buffer 0 register for ID, offset: 0B44H */
    volatile uint32_t WMB0_D03;       /*!< wakeup message buffer 0 register for data 0 - 3, offset: 0B48H */
    volatile uint32_t WMB0_D47;       /*!< wakeup message buffer 0 register for data 4 - 7, offset: 0B4CH */
    volatile uint32_t WMB1_CS;        /*!< wakeup message buffer 1 register for C/S, offset: 0B50H */
    volatile uint32_t WMB1_ID;        /*!< wakeup message buffer 1 register for ID, offset: 0B54H */
    volatile uint32_t WMB1_D03;       /*!< wakeup message buffer 1 register for data 0 - 3, offset: 0B58H */
    volatile uint32_t WMB1_D47;       /*!< wakeup message buffer 1 register for data 4 - 7, offest: 0B5CH */
    volatile uint32_t WMB2_CS;        /*!< wakeup message buffer 2 register for C/S, offset: 0B60H */
    volatile uint32_t WMB2_ID;        /*!< wakeup message buffer 2 register for ID, offset: 0B64H */
    volatile uint32_t WMB2_D03;       /*!< wakeup message buffer 2 register for data 0 - 3, offset: 0B68H */
    volatile uint32_t WMB2_D47;       /*!< wakeup message buffer 2 register for data 4 - 7, offest: 0B6CH */
    volatile uint32_t WMB3_CS;        /*!< wakeup message buffer 3 register for C/S, offset: 0B70H */
    volatile uint32_t WMB3_ID;        /*!< wakeup message buffer 3 register for ID, offset: 0B74H */
    volatile uint32_t WMB3_D03;       /*!< wakeup message buffer 3 register for data 0 - 3, offset: 0B78H */
    volatile uint32_t WMB3_D47;       /*!< wakeup message buffer 3 register for data 4 - 7, offest: 0B7CH */
    volatile uint32_t REVERSED7[32];  /*!< reversed registers, offset: 0B80H */
    volatile uint32_t FDCTRL;         /*!< CAN FD control register, offset: 0C00H */
    volatile uint32_t FDCBT;          /*!< CAN FD bit timing register, offset: 0C04H */
    volatile uint32_t FDCRC;          /*!< CAN FD CRC register, offset: 0C08H */
} FlexCanRegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/
/*! \brief Get FlexCAN module message buffer start address
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return module message buffer start address
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetMsgBufferStartAddr(FlexCanRegType *obj)
{
    return (uint32_t)(&obj->MSGBUF[0]);
}

/*! \brief Get FlexCAN module disable status
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return module disable status
 *              -0b： enable the FlexCAN module
 *              -1b： disable the FlexCAN module
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetModuleDisable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_MDIS_MASK) >> FLEXCAN_MCR_MDIS_SHIFT);
}

/*! \brief Set FlexCAN module enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : module enable
 *              -0b： enable the FlexCAN module
 *              -1b： disable the FlexCAN module
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetModuleDisable(FlexCanRegType *obj, uint8_t isDisable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_MDIS_MASK);
    tempReg |= (((uint32_t)isDisable) << FLEXCAN_MCR_MDIS_SHIFT) & FLEXCAN_MCR_MDIS_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get freeze mode
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return freeze mode
 *              -0b： not enabled to enter freeze mode
 *              -1b： enabled to enter freeze mode
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFreezeMode(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_FRZ_MASK) >> FLEXCAN_MCR_FRZ_SHIFT);
}

/*! \brief Set freeze mode
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] frzModeReq : freeze mode request
 *              -0b： not enabled to enter freeze mode
 *              -1b： enabled to enter freeze mode
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFreezeMode(FlexCanRegType *obj, uint8_t frzModeReq)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_FRZ_MASK);
    tempReg |= (((uint32_t)frzModeReq) << FLEXCAN_MCR_FRZ_SHIFT) & FLEXCAN_MCR_FRZ_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get Rx FIFO enable status
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return freeze mode
 *              -0b： Rx FIFO not enable
 *              -1b： Rx FIFO enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxFIFOEnable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_RFEN_MASK) >> FLEXCAN_MCR_RFEN_SHIFT);
}

/*! \brief Set Rx FIFO enable status
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] fifoEnable : rx FIFO enable status
 *              -0b： Rx FIFO not enable
 *              -1b： Rx FIFO enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxFIFOEnalbe(FlexCanRegType *obj, uint8_t fifoEnable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_RFEN_MASK);
    tempReg |= (((uint32_t)fifoEnable) << FLEXCAN_MCR_RFEN_SHIFT) & FLEXCAN_MCR_RFEN_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get halt mode
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return halt mode
 *              -0b： request halt mode
 *              -1b： no halt mode reuqest
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetHaltMode(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_HALT_MASK) >> FLEXCAN_MCR_HALT_SHIFT);
}

/*! \brief Set halt mode
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] haltModeReq : halt mode request
 *              -0b： request halt mode
 *              -1b： no halt mode reuqest
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetHaltMode(FlexCanRegType *obj, uint8_t haltModeReq)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_HALT_MASK);
    tempReg |= (((uint32_t)haltModeReq) << FLEXCAN_MCR_HALT_SHIFT) & FLEXCAN_MCR_HALT_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get not ready flag
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return not ready flag
 *              -0b： FlexCAN is either in normal, listen-only, or loop-back mode
 *              -1b： FlexCAN is either in module disable, doze, stop, or freeze mode
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetNotReadyFlag(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT);
}

/*! \brief Get wakeup interrupt mask
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return wakeup interrupt mask
 *              -0b： disable wakeup interrupt
 *              -1b： enable wakeup interrupt
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetWakupIntMask(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_WAKMSK_MASK) >> FLEXCAN_MCR_WAKMSK_SHIFT);
}

/*! \brief Set wakeup interrupt mask
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : wakeup interrupt mask enable
 *              -0b： disable wakeup interrupt
 *              -1b： enable wakeup interrupt
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetWakeupIntMask(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_WAKMSK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_WAKMSK_SHIFT) & FLEXCAN_MCR_WAKMSK_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get soft reset request
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return soft reset request
 *              -0b： reset the registers affected by soft reset
 *              -1b： no reset request
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetSoftResetRequest(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_SOFTRST_MASK) >> FLEXCAN_MCR_SOFTRST_SHIFT);
}

/*! \brief Set soft reset request
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : soft reset request
 *              -0b : reset the registers affected by soft reset
 *              -1b : no reset request
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetSoftResetRequest(FlexCanRegType *obj, uint8_t softRstReq)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_SOFTRST_MASK);
    tempReg |= (((uint32_t)softRstReq) << FLEXCAN_MCR_SOFTRST_SHIFT) & FLEXCAN_MCR_SOFTRST_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get freeze mode acknowledge
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return freeze mode acknowledge
 *              -0b : FlexCAN not in freeze mode, prescaler running
 *              -1b : FlexCAN in freeze mode, prescaler stopped
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFreezeAck(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT);
}

/*! \brief Get FlexCAN access mode
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return access mode
 *              -0b : FlexCAN is in user mode, affected registers allow both
 *                    supervisor and unrestricted access
 *              -1b : FlexCAN is in supervisor mode. Affected registers allow
 *                    only supervisor access. Unrestricted access behaves as
 *                    though the access was done to an unnimplemented register
 *                    location.
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetAccessMode(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_SUPV_MASK) >> FLEXCAN_MCR_SUPV_SHIFT);
}

/*! \brief Set FlexCAN access mode
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] accMode : access mode
 *              -0b : FlexCAN is in user mode, affected registers allow both
 *                    supervisor and unrestricted access
 *              -1b : FlexCAN is in supervisor mode. Affected registers allow
 *                    only supervisor access. Unrestricted access behaves as
 *                    though the access was done to an unimplemented register
 *                    location.
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetAccessMode(FlexCanRegType *obj, uint8_t accMode)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_SUPV_MASK);
    tempReg |= (((uint32_t)accMode) << FLEXCAN_MCR_SUPV_SHIFT) & FLEXCAN_MCR_SUPV_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get self wakeup enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return self wakeup enable
 *              -0b : Disable FlexCAN self wakeup feature
 *              -1b : Enable FlexCAN self wakeup feature
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetSelfWakeupEnable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_SLFWAK_MASK) >> FLEXCAN_MCR_SLFWAK_SHIFT);
}

/*! \brief Get self wakeup enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : self wakeup enable
 *              -0b : Disable FlexCAN self wakeup feature
 *              -1b : Enable FlexCAN self wakeup feature
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetSelfWakeupEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_SLFWAK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_SLFWAK_SHIFT) & FLEXCAN_MCR_SLFWAK_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get self warning interrupt enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return warning interrupt enable
 *              -0b : warning interrupt not enable
 *              -1b : warning interrupt enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetWarningIntEnable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_WRNEN_MASK) >> FLEXCAN_MCR_WRNEN_SHIFT);
}

/*! \brief Set self warning interrupt enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : warning interrupt enable
 *              -0b : warning interrupt not enable
 *              -1b : warning interrupt enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetWarningIntEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_WRNEN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_WRNEN_SHIFT) & FLEXCAN_MCR_WRNEN_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get low power mode acknowledge
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return low power mode acknowledge
 *              -0b : FlexCAN is not in a low power mode
 *              -1b : FlexCAN is in a low power mode
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetLowPowerAck(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_LPMACK_MASK) >> FLEXCAN_MCR_LPMACK_SHIFT);
}

/*! \brief Get wake up source
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return wake up source
 *              -0b : FlexCAN uses the unfiltered Rx input to detect recessive-to-dominant edges on the CAN bus
 *              -1b : FlexCAN uses the filtered Rx input to detect recessive-to-dominant edges on the CAN bus
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetWakeupSource(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_WAKSRC_MASK) >> FLEXCAN_MCR_WAKSRC_SHIFT);
}

/*! \brief Set wake up source
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : wake up source
 *              -0b : FlexCAN uses the unfiltered Rx input to detect recessive-to-dominant edges on the CAN bus
 *              -1b : FlexCAN uses the filtered Rx input to detect recessive-to-dominant edges on the CAN bus
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetWakeupSource(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_WAKSRC_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_WAKSRC_SHIFT) & FLEXCAN_MCR_WAKSRC_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get doze mode enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return doze mode enable
 *              -0b : FlexCAN is not enabled to enter low-power mode when Doze mode is request
 *              -1b : FlexCAN is enabled to enter low-power mode when Doze mode is request
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetDozeMode(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_DOZE_MASK) >> FLEXCAN_MCR_DOZE_SHIFT);
}

/*! \brief Set doze mode enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : doze mode enable
 *              -0b : FlexCAN is not enabled to enter low-power mode when Doze mode is request
 *              -1b : FlexCAN is enabled to enter low-power mode when Doze mode is request
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetDozeMode(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_DOZE_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_DOZE_SHIFT) & FLEXCAN_MCR_DOZE_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get self reception
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return self reception enable
 *              -0b : self reception enable
 *              -1b : self reception disable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetSelfReceptionDisable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_SRXDIS_MASK) >> FLEXCAN_MCR_SRXDIS_SHIFT);
}

/*! \brief Set self reception
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] isDisable : self reception enable
 *              -0b : self reception enable
 *              -1b : self reception disable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetSelfReceptionDisable(FlexCanRegType *obj, uint8_t isDisable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_SRXDIS_MASK);
    tempReg |= (((uint32_t)isDisable) << FLEXCAN_MCR_SRXDIS_SHIFT) & FLEXCAN_MCR_SRXDIS_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get rx individual mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return individual mask enable
 *              -0b : individual mask disable
 *              -1b : individual mask enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetIndividualMaskEnable(const FlexCanRegType *obj)
{
    return ((obj->MCR & FLEXCAN_MCR_IRQM_MASK) >> FLEXCAN_MCR_IRQM_SHIFT);
}

/*! \brief Set rx individual mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : individual mask enable
 *              -0b : individual mask disable
 *              -1b : individual mask enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetIndividualMaskEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_IRQM_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_IRQM_SHIFT) & FLEXCAN_MCR_IRQM_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get rx fifo dma enable or disable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return rx fifo dma enable
 *          -0b : rx fifo dma disable
 *          -1b : rx fifo dma enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxFIFODmaEnable(const FlexCanRegType *obj)
{
    return ((obj->MCR & FLEXCAN_MCR_DMA_MASK) >> FLEXCAN_MCR_DMA_SHIFT);
}

/*! \brief Set rx fifo dma enable or disable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : rx fifo dma enable
 *              -0b : rx fifo dma disable
 *              -1b : rx fifo dma enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxFIFODmaEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_DMA_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_DMA_SHIFT) & FLEXCAN_MCR_DMA_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get local priority enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return local priority enable
 *          -0b : local priority disable
 *          -1b : local priority enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMcrLprioen(const FlexCanRegType *obj)
{
    return ((obj->MCR & FLEXCAN_MCR_LPRIOEN_MASK) >> FLEXCAN_MCR_LPRIOEN_SHIFT);
}

/*! \brief Set local priority enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : local priority enable
 *              -0b : local priority disable
 *              -1b : local priority enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMcrLprioen(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MCR;

    tmp &= ~FLEXCAN_MCR_LPRIOEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK);
    obj->MCR = tmp;
}

/*! \brief Get Tx message pending abort mechanism enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return Tx message pending abort mechanism enable
 *              -0b： disable abort
 *              -1b： enable abort
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTxAbortEnable(FlexCanRegType *obj)
{
    return (uint8_t)((obj->MCR & FLEXCAN_MCR_AEN_MASK) >> FLEXCAN_MCR_AEN_SHIFT);
}

/*! \brief Set Tx message pending abort mechanism enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : Tx message pending abort mechanism enable
 *              -0b： disable abort
 *              -1b： enable abort
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetTxAbortEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_AEN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_AEN_SHIFT) & FLEXCAN_MCR_AEN_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get CAN FD operation enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \return CAN FD operation enable
 *              -0b： CAN FD operation enable
 *              -1b： CAN FD operation disable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdEnable(const FlexCanRegType *obj)
{
    return ((obj->MCR & FLEXCAN_MCR_FDEN_MASK) >> FLEXCAN_MCR_FDEN_SHIFT);
}

/*! \brief Set CAN FD operation enable
 *
 * \param[in] obj : pointer to flexCAN register instance
 * \param[in] enable : CAN FD operation enable
 *              -0b： CAN FD operation enable
 *              -1b： CAN FD operation disable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_FDEN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_MCR_FDEN_SHIFT) & FLEXCAN_MCR_FDEN_MASK;

    obj->MCR = tempReg;
}

/*! \brief Set Rx FIFO ID filter acceptance mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : Rx FIFO ID filter acceptance mode
 *              -0h : Format A One full ID (standard and extended) per
 *                    ID filter table element
 *              -1h : Format B Two full standard IDs or two partial 14-bit
 *                    (standard and extended) IDs per ID filter table element
 *              -2h : Format C Four partial 8-bit standard IDs per ID filter
 *                    table element
 *              -3h : Format D All frames rejected
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxFifoFiltMode(FlexCanRegType *obj, uint8_t val)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_IDAM_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_MCR_IDAM_SHIFT) & FLEXCAN_MCR_IDAM_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get Rx FIFO ID filter acceptance mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Rx FIFO ID filter acceptance mode
 *              -0h : Format A One full ID (standard and extended) per
 *                    ID filter table element
 *              -1h : Format B Two full standard IDs or two partial 14-bit
 *                    (standard and extended) IDs per ID filter table element
 *              -2h : Format C Four partial 8-bit standard IDs per ID filter
 *                    table element
 *              -3h : Format D All frames rejected
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxFifoFiltMode(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->MCR) & FLEXCAN_MCR_IDAM_MASK) >> FLEXCAN_MCR_IDAM_SHIFT);
}

/*! \brief Get number of the last message buffer
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: number of the last message buffer
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMcrMaxmb(const FlexCanRegType *obj)
{
    return ((obj->MCR & FLEXCAN_MCR_MAXMB_MASK) >> FLEXCAN_MCR_MAXMB_SHIFT);
}

/*! \brief Set number of the last message buffer
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] maxNum : number of the last message buffer
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMaxMsgBufferNum(FlexCanRegType *obj, uint8_t maxNum)
{
    uint32_t tempReg;
    tempReg = obj->MCR;
    tempReg &= (~FLEXCAN_MCR_MAXMB_MASK);
    tempReg |= (((uint32_t)maxNum) << FLEXCAN_MCR_MAXMB_SHIFT) & FLEXCAN_MCR_MAXMB_MASK;

    obj->MCR = tempReg;
}

/*! \brief Get prescaler division factor
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: prescaler division factor
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Presdiv(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_PRESDIV_MASK) >> FLEXCAN_CTRL1_PRESDIV_SHIFT);
}

/*! \brief Set prescaler division factor
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : prescaler division factor
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Presdiv(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL1;

    tmp &= ~FLEXCAN_CTRL1_PRESDIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK);
    obj->CTRL1 = tmp;
}

/*! \brief Get resync jump width
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: resync jump width
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Rjw(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_RJW_MASK) >> FLEXCAN_CTRL1_RJW_SHIFT);
}

/*! \brief Set resync jump width
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : resync jump width
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Rjw(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL1;

    tmp &= ~FLEXCAN_CTRL1_RJW_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK);
    obj->CTRL1 = tmp;
}

/*! \brief Get phase segment 1
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: phase segment 1
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Pseg1(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_PSEG1_MASK) >> FLEXCAN_CTRL1_PSEG1_SHIFT);
}

/*! \brief Set phase segment 1
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : phase segment 1
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Pseg1(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL1;

    tmp &= ~FLEXCAN_CTRL1_PSEG1_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK);
    obj->CTRL1 = tmp;
}

/*! \brief Get phase segment 2
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: phase segment 2
 */
__attribute__((always_inline)) static inline uint8_t CanReg_GetCtrl1Pseg2(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_PSEG2_MASK) >> FLEXCAN_CTRL1_PSEG2_SHIFT);
}

/*! \brief Set phase segment 2
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : phase segment 2
 */
__attribute__((always_inline)) static inline void CanReg_SetCtrl1Pseg2(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL1;

    tmp &= ~FLEXCAN_CTRL1_PSEG2_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK);
    obj->CTRL1 = tmp;
}

/*! \brief Set bus off interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : bus off interrupt enable
 *              -0b : bus off interrupt disabled
 *              -1b : bus off interrupt enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetBusOffIntEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_BOFFMSK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_BOFFMSK_SHIFT) & FLEXCAN_CTRL1_BOFFMSK_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get bus off interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bus off interrupt enable
 *              -0b : bus off interrupt disabled
 *              -1b : bus off interrupt enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBusOffIntEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_BOFFMSK_MASK) >> FLEXCAN_CTRL1_BOFFMSK_SHIFT);
}

/*! \brief Set error interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : error interrupt enable
 *              -0b : error interrupt disabled
 *              -1b : error interrupt enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetErrorIntEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_ERRMSK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_ERRMSK_SHIFT) & FLEXCAN_CTRL1_ERRMSK_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get error interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error interrupt enable
 *              -0b : error interrupt disabled
 *              -1b : error interrupt enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetErrorIntEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_ERRMSK_MASK) >> FLEXCAN_CTRL1_ERRMSK_SHIFT);
}

/*! \brief Get module clock source
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: module clock source
 *              -0b : The PE clock source is the oscillator clock.
 *              -1b : The PE clock source is the peripheral clock.
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetClockSource(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_CLKSRC_MASK) >> FLEXCAN_CTRL1_CLKSRC_SHIFT);
}

/*! \brief Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] clkSrc :
 *              0b - The PE clock source is the oscillator clock.
 *              1b - The PE clock source is the peripheral clock.
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetClockSource(FlexCanRegType *obj, uint8_t clkSrc)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_CLKSRC_MASK);
    tempReg |= (((uint32_t)clkSrc) << FLEXCAN_CTRL1_CLKSRC_SHIFT) & FLEXCAN_CTRL1_CLKSRC_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get can loop back mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: can loop back mode
 *              0b - disable
 *              1b - enable
 */
__attribute__((always_inline)) static inline uint8_t CanReg_GetLoopbackMode(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_LPB_MASK) >> FLEXCAN_CTRL1_LPB_SHIFT);
}

/*! \brief Set can loop back mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : loop back mode feature select
 *              0b - disable
 *              1b - enable
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetLoopbackMode(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_LPB_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_LPB_SHIFT) & FLEXCAN_CTRL1_LPB_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Set tx warning interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : tx warning interrupt enable
 *              -0b : tx warning interrupt disabled
 *              -1b : tx warning interrupt enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetTxWarnIntEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_TWRNMSK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_TWRNMSK_SHIFT) & FLEXCAN_CTRL1_TWRNMSK_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get tx warning interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: tx warning interrupt enable
 *              -0b : tx warning interrupt disabled
 *              -1b : tx warning interrupt enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTxWarnIntEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_TWRNMSK_MASK) >> FLEXCAN_CTRL1_TWRNMSK_SHIFT);
}

/*! \brief Set rx warning interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : rx warning interrupt enable
 *              -0b : rx warning interrupt disabled
 *              -1b : rx warning interrupt enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxWarnIntEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_RWRNMSK_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_RWRNMSK_SHIFT) & FLEXCAN_CTRL1_RWRNMSK_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get rx warning interrupt enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: rx warning interrupt enable
 *              -0b : rx warning interrupt disabled
 *              -1b : rx warning interrupt enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxWarnIntEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_RWRNMSK_MASK) >> FLEXCAN_CTRL1_RWRNMSK_SHIFT);
}

/*! \brief Get CAN bit sampling mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: CAN bit sampling mode
 *              -0b : one sample is used to determine the bit value
 *              -1b : three samples are used to determine the value of the received bit
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBitSamplingType(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_SMP_MASK) >> FLEXCAN_CTRL1_SMP_SHIFT);
}

/*! \brief Set CAN bit sampling mode
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] threeSamplingEn : can bit sampling
 *              -0b : one sample is used to determine the bit value
 *              -1b : three samples are used to determine the value of the received bit
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetBitSamplingType(FlexCanRegType *obj, uint8_t threeSamplingEn)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_SMP_MASK);
    tempReg |= (((uint32_t)threeSamplingEn) << FLEXCAN_CTRL1_SMP_SHIFT) & FLEXCAN_CTRL1_SMP_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Set bus off automatic recovering enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : bus off automatic recovering enable
 *              -1b : bus off automatic recovering disabled
 *              -0b : bus off automatic recovering enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetBusOffRecEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_BOFFREC_MASK);
    if(enable == true)
    {
        tempReg |= (((uint32_t)0) << FLEXCAN_CTRL1_BOFFREC_SHIFT) & FLEXCAN_CTRL1_BOFFREC_MASK;
    }
    else
    {
        tempReg |= (((uint32_t)1) << FLEXCAN_CTRL1_BOFFREC_SHIFT) & FLEXCAN_CTRL1_BOFFREC_MASK;
    }

    obj->CTRL1 = tempReg;
}

/*! \brief Get bus off automatic recovering enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bus off automatic recovering enable
 *              -0b : bus off automatic recovering disabled
 *              -1b : bus off automatic recovering enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBusOffRecEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_BOFFREC_MASK) >> FLEXCAN_CTRL1_BOFFREC_SHIFT);
}

/*! \brief Set timer synchronze feature enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : timer synchronze feature enable
 *              -0b : timer sync feature disabled
 *              -1b : timer sync feature enabled
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetTimerSyncEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_TSYN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_TSYN_SHIFT) & FLEXCAN_CTRL1_TSYN_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get timer synchronze feature enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: timer synchronze feature enable
 *              -0b : timer sync feature disabled
 *              -1b : timer sync feature enabled
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTimerSyncEnable(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_TSYN_MASK) >> FLEXCAN_CTRL1_TSYN_SHIFT);
}

/*! \brief Set lowest buffer transmit first enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : timer synchronze feature enable
 *              -0b : lowest buffer transmit first disable
 *              -1b : lowest buffer transmit first enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetLowestBufTxFirstEna(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_LBUF_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_LBUF_SHIFT) & FLEXCAN_CTRL1_LBUF_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get lowest buffer transmit first enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: lowest buffer transmit first enable
 *              -0b : lowest buffer transmit first disable
 *              -1b : lowest buffer transmit first enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetLowestBufTxFirstEna(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_LBUF_MASK) >> FLEXCAN_CTRL1_LBUF_SHIFT);
}

/*! \brief Set listen only mode enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : listen only mode enable
 *              -0b : listen only mode disable
 *              -1b : listen only mode enable
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetListenOnlyModeEna(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL1;
    tempReg &= (~FLEXCAN_CTRL1_LOM_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL1_LOM_SHIFT) & FLEXCAN_CTRL1_LOM_MASK;

    obj->CTRL1 = tempReg;
}

/*! \brief Get listen only mode enable
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: listen only mode enable
 *              -0b : listen only mode disable
 *              -1b : listen only mode enable
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetListenOnlyModeEna(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_LOM_MASK) >> FLEXCAN_CTRL1_LOM_SHIFT);
}

/*! \brief Get propagation segment
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: propagation segment length
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Propseg(const FlexCanRegType *obj)
{
    return ((obj->CTRL1 & FLEXCAN_CTRL1_PROPSEG_MASK) >> FLEXCAN_CTRL1_PROPSEG_SHIFT);
}

/*! \brief Set propagation segment
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : propagation segment length
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Propseg(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL1;

    tmp &= ~FLEXCAN_CTRL1_PROPSEG_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK);
    obj->CTRL1 = tmp;
}

/*! \brief Get free running timer
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: free running timer counter
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetFreeRunningTimer(FlexCanRegType *obj)
{
    return obj->TIMER;
}

/*! \brief Get Rx mailboxes global mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Rx mailboxes global mask
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxMailboxGlobalMask(FlexCanRegType *obj)
{
    return obj->RXMGMASK;
}

/*! \brief Set Rx mailboxes global mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] mask : Rx mailboxes global mask
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxMailboxGlobalMask(FlexCanRegType *obj, uint32_t mask)
{
    obj->RXMGMASK = mask;
}


/*! \brief Set Rx mailbox 14 mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] mask : mask for Rx mailbox 14
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxMailbox14Mask(FlexCanRegType *obj, uint32_t mask)
{
    obj->RX14MASK = mask;
}

/*! \brief Get Rx mailbox 14 mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: mask for Rx mailbox 14
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxMailbox14Mask(FlexCanRegType *obj)
{
    return (obj->RX14MASK);
}

/*! \brief Set Rx mailbox 15 mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] mask : mask for Rx mailbox 15
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxMailbox15Mask(FlexCanRegType *obj, uint32_t mask)
{
    obj->RX15MASK = mask;
}

/*! \brief Get Rx mailbox 15 mask
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: mask for Rx mailbox 15
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxMailbox15Mask(FlexCanRegType *obj)
{
    return (obj->RX15MASK);
}

/*! \brief Get receive error counter for fast bits
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: receive error counter for fast bits
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrRxerrcntfast(const FlexCanRegType *obj)
{
    return ((obj->ECR & FLEXCAN_ECR_RXERRCNTFAST_MASK) >> FLEXCAN_ECR_RXERRCNTFAST_SHIFT);
}

/*! \brief Set receive error counter for fast bits
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : receive error counter for fast bits
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetEcrRxerrcntfast(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ECR;

    tmp &= ~FLEXCAN_ECR_RXERRCNTFAST_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_RXERRCNTFAST_SHIFT)) & FLEXCAN_ECR_RXERRCNTFAST_MASK);
    obj->ECR = tmp;
}

/*! \brief Get transmit error counter for fast bits
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: transmit error counter for fast bits
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrTxerrcntfast(const FlexCanRegType *obj)
{
    return ((obj->ECR & FLEXCAN_ECR_TXERRCNTFAST_MASK) >> FLEXCAN_ECR_TXERRCNTFAST_SHIFT);
}

/*! \brief Set transmit error counter for fast bits
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : transmit error counter for fast bits
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetEcrTxerrcntfast(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ECR;

    tmp &= ~FLEXCAN_ECR_TXERRCNTFAST_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_TXERRCNTFAST_SHIFT)) & FLEXCAN_ECR_TXERRCNTFAST_MASK);
    obj->ECR = tmp;
}

/*! \brief Get receive error counter
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: receive error counter
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrRxerrcnt(const FlexCanRegType *obj)
{
    return ((obj->ECR & FLEXCAN_ECR_RXERRCNT_MASK) >> FLEXCAN_ECR_RXERRCNT_SHIFT);
}

/*! \brief Set receive error counter
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : receive error counter
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetEcrRxerrcnt(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ECR;

    tmp &= ~FLEXCAN_ECR_RXERRCNT_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK);
    obj->ECR = tmp;
}

/*! \brief Get transmit error counter
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: transmit error counter
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrTxerrcnt(const FlexCanRegType *obj)
{
    return ((obj->ECR & FLEXCAN_ECR_TXERRCNT_MASK) >> FLEXCAN_ECR_TXERRCNT_SHIFT);
}

/*! \brief Set transmit error counter
 *
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : transmit error counter
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetEcrTxerrcnt(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ECR;

    tmp &= ~FLEXCAN_ECR_TXERRCNT_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK);
    obj->ECR = tmp;
}


/*! \brief Get bit 1 error in FD frame data phase
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bit 1 error in FD frame data phase
 *              - 0 : no such error occurrence
 *              - 1 : at least one bit sent as recessive is received as dominant
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBit1FastError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_BIT1ERR_FAST_MASK) >> FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT);
}

/*! \brief Get bit 0 error in FD frame data phase
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bit 0 error in FD frame data phase
 *              - 0 : no such error occurrence
 *              - 1 : at least one bit sent as dominant is received as recessive
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBit0FastError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_BIT0ERR_FAST_MASK) >> FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT);
}

/*! \brief Get CRC error in FD frame data phase
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: CRC error in FD frame data phase
 *              - 0 : no such error occurrence
 *              - 1 : a CRC error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCrcFastError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_CRCERR_FAST_MASK) >> FLEXCAN_ESR1_CRCERR_FAST_SHIFT);
}

/*! \brief Get form error in FD frame data phase
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: form error in FD frame data phase
 *              - 0 : no such error occurrence
 *              - 1 : a form error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFormFastError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_FRMERR_FAST_MASK) >> FLEXCAN_ESR1_FRMERR_FAST_SHIFT);
}

/*! \brief Get stuff error in FD frame data phase
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: stuff error in FD frame data phase
 *              - 0 : no such error occurrence
 *              - 1 : a stuff error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetStuffFastError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_STFERR_FAST_MASK) >> FLEXCAN_ESR1_STFERR_FAST_SHIFT);
}

/*! \brief Get error overrun
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error overrun
 *              - 0 : overrun has occurred
 *              - 1 : overrun has not occurred
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Errovr(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_ERROVR_MASK) >> FLEXCAN_ESR1_ERROVR_SHIFT);
}

/*! \brief Clear error overrun
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEsr1Errovr(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_ERROVR_MASK;
}

/*! \brief Get error interrupt for errors detected in the data phase of CAN FD frames with the
 * BRS Bit set
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error interrupt for errors detected in the data phase
 *              - 0 : no error
 *              - 1 : error has detected in CAN FD frame data phase
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Errintfast(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_ERRINT_FAST_MASK) >> FLEXCAN_ESR1_ERRINT_FAST_SHIFT);
}

/*! \brief Clear error interrupt for errors detected in the data phase of CAN FD frames with the
 * BRS Bit set
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEsr1Errintfast(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_ERRINT_FAST_MASK;
}

/*! \brief Get bus off done interrupt
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bus off done interrupt
 *              - 0 : no such occurrence
 *              - 1 : module has completed bus off process
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Boffdoneint(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_BOFFDONEINT_MASK) >> FLEXCAN_ESR1_BOFFDONEINT_SHIFT);
}

/*! \brief Clear bus off done interrupt
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEsr1Boffdoneint(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_BOFFDONEINT_MASK;
}

/*! \brief Get CAN synchronization status
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: CAN synchronization status
 *              - 0 : not synchronized to the can bus
 *              - 1 : synchronized to the can bus
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Synch(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_SYNCH_MASK) >> FLEXCAN_ESR1_SYNCH_SHIFT);
}

/*! \brief Get Tx warning interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Tx warning interrupt flag
 *              - 0 : no such occurrence
 *              - 1 : tx error counter transitioned from less than 96 to greater than or equal to 96
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Twrnint(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_TWRNINT_MASK) >> FLEXCAN_ESR1_TWRNINT_SHIFT);
}

/*! \brief Clear Tx warning interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEsr1Twrnint(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_TWRNINT_MASK;
}

/*! \brief Get Rx warning interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Rx warning interrupt flag
 *              - 0 : no such occurrence
 *              - 1 : Rx error counter transitioned from less than 96 to greater than or equal to 96
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr1Rwrnint(const FlexCanRegType *obj)
{
    return ((obj->ESR1 & FLEXCAN_ESR1_RWRNINT_MASK) >> FLEXCAN_ESR1_RWRNINT_SHIFT);
}

/*! \brief Clear Rx warning interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEsr1Rwrnint(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_RWRNINT_MASK;
}

/*! \brief Get bit 1 error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bit 1 error
 *              - 0 : no such error occurrence
 *              - 1 : at least one bit sent as recessive is received as dominant
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBit1Error(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_BIT1ERR_MASK) >> FLEXCAN_ESR1_BIT1ERR_SHIFT);
}

/*! \brief Get bit 0 error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bit 0 error
 *              - 0 : no such error occurrence
 *              - 1 : at least one bit sent as dominant is received as recessive
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBit0Error(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_BIT0ERR_MASK) >> FLEXCAN_ESR1_BIT0ERR_SHIFT);
}

/*! \brief Get ACK error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: ACK error
 *              - 0 : no such error occurrence
 *              - 1 : an ACK error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetAckError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_ACKERR_MASK) >> FLEXCAN_ESR1_ACKERR_SHIFT);
}

/*! \brief Get CRC error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: CRC error
 *              - 0 : no such error occurrence
 *              - 1 : an CRC error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCrcError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_CRCERR_MASK) >> FLEXCAN_ESR1_CRCERR_SHIFT);
}

/*! \brief Get form error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: form error
 *              - 0 : no such error occurrence
 *              - 1 : an form error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFormError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_FRMERR_MASK) >> FLEXCAN_ESR1_FRMERR_SHIFT);
}

/*! \brief Get stuff error
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: stuff error
 *              - 0 : no such error occurrence
 *              - 1 : an stuff error occurred since last read of this register
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetStuffError(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_STFERR_MASK) >> FLEXCAN_ESR1_STFERR_SHIFT);
}

/*! \brief Get Tx error warning
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Tx error warning
 *              - 0 : no such error occurrence
 *              - 1 : TXERRCNT is greater than or equal to 96
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTxErrWarning(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_TXWRN_MASK) >> FLEXCAN_ESR1_TXWRN_SHIFT);
}

/*! \brief Get Rx error warning
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Rx error warning
 *              - 0 : no such error occurrence
 *              - 1 : RXERRCNT is greater than or equal to 96
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxErrWarning(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_RXWRN_MASK) >> FLEXCAN_ESR1_RXWRN_SHIFT);
}

/*! \brief Get idle state
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: idle state
 *              - 0 : no such occurrence
 *              - 1 : CAN bus is now idle
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetIdleState(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_IDLE_MASK) >> FLEXCAN_ESR1_IDLE_SHIFT);
}

/*! \brief Get Tx state
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Tx state
 *              - 0 : FlexCan is not transmitting a message
 *              - 1 : FlexCan is transmitting a message
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTxState(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_TX_MASK) >> FLEXCAN_ESR1_TX_SHIFT);
}

/*! \brief Get fault confinement state
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: fault confinement state
 *              - 0b00 : error passive
 *              - 0b01 : error active
 *              - 0b1x : bus off
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFltConfinementState(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_FLTCONF_MASK) >> FLEXCAN_ESR1_FLTCONF_SHIFT);
}

/*! \brief Get FlexCan Rx state
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: FlexCan Rx state
 *              - 0 : FlexCan is not receiving a message
 *              - 1 : FlexCan is receiving a message
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxState(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_RX_MASK) >> FLEXCAN_ESR1_RX_SHIFT);
}

/*! \brief Get bus off interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bus off interrupt flag
 *              - 0 : bus off interrupt assert
 *              - 1 : bus off interrupt deassert
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBusoffIntFlag(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_BOFFINT_MASK) >> FLEXCAN_ESR1_BOFFINT_SHIFT);
}

/*! \brief Clear bus off interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearBusoffIntFlag(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_BOFFINT_MASK;
}

/*! \brief Get error interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error interrupt flag
 *              - 0 : error interrupt assert
 *              - 1 : error interrupt deassert
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetErrIntFlag(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_ERRINT_MASK) >> FLEXCAN_ESR1_ERRINT_SHIFT);
}

/*! \brief Clear error interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearErrIntFlag(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_ERRINT_MASK;
}

/*! \brief Get edge wakeup interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: edge wakeup interrupt flag
 *              - 0 : wakeup interrupt assert
 *              - 1 : wakeup interrupt deassert
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEdgeWakeIntFlag(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->ESR1) & FLEXCAN_ESR1_WAKINT_MASK) >> FLEXCAN_ESR1_WAKINT_SHIFT);
}

/*! \brief Clear edge wakeup interrupt flag
 *
 * \param[in] obj : pointer to FlexCAN register instance
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearEdgeWakeIntFlag(FlexCanRegType *obj)
{
    obj->ESR1 = FLEXCAN_ESR1_WAKINT_MASK;
}

/*! \brief Set FlexCan message buffer interrupt enable mask
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] regId : register index
 * \param[in] val   : message buffer interrupt enable mask
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMsgBufInterruptEnable(FlexCanRegType *obj, uint32_t regId, uint32_t val)
{
    switch(regId)
    {
    case 0:
        obj->IMASK1 |= val;
        break;
    case 1:
        obj->IMASK2 |= val;
        break;
    case 2:
        obj->IMASK3 |= val;
        break;
    case 3:
        obj->IMASK4 |= val;
        break;
    default:
        break;
    }
}

/*! \brief Set FlexCan message buffer interrupt disable mask
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] regId : register index
 * \param[in] val   : message buffer interrupt disable mask
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMsgBufInterruptDisable(FlexCanRegType *obj, uint32_t regId, uint32_t val)
{
    switch(regId)
    {
    case 0:
        obj->IMASK1 &= val;
        break;
    case 1:
        obj->IMASK2 &= val;
        break;
    case 2:
        obj->IMASK3 &= val;
        break;
    case 3:
        obj->IMASK4 &= val;
        break;
    default:
        break;
    }
}

/*! \brief Get FlexCan message buffer interrupt flag register mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] regId : register index
 * \return: FlexCan message buffer interrupt flag register[n] mask
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetMsgBufInterruptFlagReg(FlexCanRegType *obj, uint32_t regId)
{
    uint32_t retVal = 0;

    switch(regId)
    {
    case 0:
        retVal = obj->IFLAG1;
        break;
    case 1:
        retVal = obj->IFLAG2;
        break;
    case 2:
        retVal = obj->IFLAG3;
        break;
    case 3:
        retVal = obj->IFLAG4;
        break;
    default:
        break;
    }

    return retVal;
}

/*! \brief Set FlexCan message buffer interrupt flag
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] regId : register index
 * \param[in] val   : message buffer interrupt flag
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMsgBufInterruptFlagReg(FlexCanRegType *obj, uint32_t regId, uint32_t val)
{
    switch(regId)
    {
    case 0:
        obj->IFLAG1 = val;
        break;
    case 1:
        obj->IFLAG2 = val;
        break;
    case 2:
        obj->IFLAG3 = val;
        break;
    case 3:
        obj->IFLAG4 = val;
        break;
    default:
        break;
    }
}

/*! \brief Get error interrupt mask in the data phase of CAN FD frame
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error interrupt mask in the data phase of CAN FD frame
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Errmskfast(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_ERRMSKFAST_MASK) >> FLEXCAN_CTRL2_ERRMSKFAST_SHIFT);
}

/*! \brief Set error interrupt mask in the data phase of CAN FD frame
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] value : error interrupt mask in the data phase of CAN FD frame
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Errmskfast(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_ERRMSKFAST_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_ERRMSKFAST_SHIFT)) & FLEXCAN_CTRL2_ERRMSKFAST_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get bus off done interrupt mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: bus off done interrupt mask
 *              0: bus off done interrupt disable
 *              1: bus off done interrupt enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Boffdonemsk(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_BOFFDONEMSK_MASK) >> FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT);
}

/*! \brief Set bus off done interrupt mask
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] value : bus off done interrupt mask
 *              0: bus off done interrupt disable
 *              1: bus off done interrupt enable
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Boffdonemsk(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_BOFFDONEMSK_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get error correction configuration register write enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: error correction configuration register write enable
 *              0: error correction configuration register write disable
 *              1: error correction configuration register write enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMemErrCtrlRegWriteEnable(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_ECRWRE_MASK) >> FLEXCAN_CTRL2_ECRWRE_SHIFT);
}

/*! \brief Set error correction configuration register write enable
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] value : error correction configuration register write enable
 *              0: error correction configuration register write disable
 *              1: error correction configuration register write enable
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetMemErrCtrlRegWriteEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL2;
    tempReg &= (~FLEXCAN_CTRL2_ECRWRE_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ECRWRE_SHIFT) & FLEXCAN_CTRL2_ECRWRE_MASK;

    obj->CTRL2 = tempReg;
}

/*! \brief Get write access to memory in freeze mode enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: write access to memory in freeze mode enable
 *              0: write access to memory in freeze mode disable
 *              1: write access to memory in freeze mode enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFreezeModeWriteAcc(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_WRMFRZ_MASK) >> FLEXCAN_CTRL2_WRMFRZ_SHIFT);
}

/*! \brief Set write access to memory in freeze mode enable
 *
 * \param[in] obj   : pointer to FlexCAN register instance
 * \param[in] enable : write access to memory in freeze mode enable
 *              0: write access to memory in freeze mode disable
 *              1: write access to memory in freeze mode enable
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFreezeModeWriteAcc(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL2;
    tempReg &= (~FLEXCAN_CTRL2_WRMFRZ_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_WRMFRZ_SHIFT) & FLEXCAN_CTRL2_WRMFRZ_MASK;

    obj->CTRL2 = tempReg;
}

/*! \brief Set number of legacy Rx FIFO filters
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : number of legacy Rx FIFO filters
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxFifoFilterNum(FlexCanRegType *obj, uint8_t val)
{
    uint32_t tempReg;
    tempReg = obj->CTRL2;
    tempReg &= (~FLEXCAN_CTRL2_RFFN_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CTRL2_RFFN_SHIFT) & FLEXCAN_CTRL2_RFFN_MASK;

    obj->CTRL2 = tempReg;
}

/*! \brief Get number of legacy Rx FIFO filters
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: number of Rx FIFO filters
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxFifoFilterNum(FlexCanRegType *obj)
{
    return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_RFFN_MASK) >> FLEXCAN_CTRL2_RFFN_SHIFT);
}

/*! \brief Get Tx arbitration start delay
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Tx arbitration start delay
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Tasd(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_TASD_MASK) >> FLEXCAN_CTRL2_TASD_SHIFT);
}

/*! \brief Set Tx arbitration start delay
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : Tx arbitration start delay
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Tasd(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_TASD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get mailboxes reception priority
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: mailboxes reception priority
 *              0: matching starts from Rx FIFO and continues on mailboxes
 *              1: matching starts from mailboxes and continues on Rx FIFO
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Mrp(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_MRP_MASK) >> FLEXCAN_CTRL2_MRP_SHIFT);
}

/*! \brief Set mailboxes reception priority
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : mailboxes reception priority
 *              0: matching starts from Rx FIFO and continues on mailboxes
 *              1: matching starts from mailboxes and continues on Rx FIFO
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Mrp(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_MRP_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get remote request storing
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: remote request storing
 *              0: remote response frame is generated
 *              1: remote request frame is stored
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Rrs(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_RRS_MASK) >> FLEXCAN_CTRL2_RRS_SHIFT);
}

/*! \brief Set remote request storing
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : remote request storing
 *              0: remote response frame is generated
 *              1: remote request frame is stored
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Rrs(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_RRS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get entire frame arbitration field comparison enable for rx mailboxes
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: entire frame arbitration field comparison enable for rx mailboxes
 *              0: rx mailbox filter's IDE bit is always compared and RTR is never
 *                 compared, regardless of mask bits
 *              1: enable the comparison of both the IDE and RTR bits of an
 *                 Rx mailbox filter with the corresponding bits of the incoming
 *                 frame. Mask bits do apply
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Eacen(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_EACEN_MASK) >> FLEXCAN_CTRL2_EACEN_SHIFT);
}

/*! \brief Set entire frame arbitration field comparison enable for rx mailboxes
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : entire frame arbitration field comparison enable for rx mailboxes
 *              0: rx mailbox filter's IDE bit is always compared and RTR is never
 *                 compared, regardless of mask bits
 *              1: enable the comparison of both the IDE and RTR bits of an
 *                 Rx mailbox filter with the corresponding bits of the incoming
 *                 frame. Mask bits do apply
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Eacen(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_EACEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get free running timer source
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: free running timer source
 *              0: clocked by CAN bit clock
 *              1: clocked by an external time tick, the period can be either adjusted
 *                 to be equal to the baud rate on the CAN bus or a different value as
 *                 required
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Timersrc(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_TIMERSRC_MASK) >> FLEXCAN_CTRL2_TIMERSRC_SHIFT);
}

/*! \brief Set free running timer source
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : free running timer source
 *              0: clocked by CAN bit clock
 *              1: clocked by an external time tick, the period can be either adjusted
 *                 to be equal to the baud rate on the CAN bus or a different value as
 *                 required
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Timersrc(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_TIMERSRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_TIMERSRC_SHIFT)) & FLEXCAN_CTRL2_TIMERSRC_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get protocol exception enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: protocol exception enable
 *              0: protocol exception disable
 *              1: protocol exception enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Prexcen(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_PREXCEN_MASK) >> FLEXCAN_CTRL2_PREXCEN_SHIFT);
}

/*! \brief Set protocol exception enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : protocol exception enable
 *              0: protocol exception disable
 *              1: protocol exception enable
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Prexcen(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_PREXCEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_PREXCEN_SHIFT)) & FLEXCAN_CTRL2_PREXCEN_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get ISO CAN FD enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: ISO CAN FD enable
 *              0: ISO CAN FD disable
 *              1: ISO CAN FD enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetIsoFdEnalbe(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_ISOCANFDEN_MASK) >> FLEXCAN_CTRL2_ISOCANFDEN_SHIFT);
}

/*! \brief Set ISO CAN FD enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : ISO CAN FD enable
 *              0: ISO CAN FD disable
 *              1: ISO CAN FD enable
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetIsoFdEnalbe(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CTRL2;
    tempReg &= (~FLEXCAN_CTRL2_ISOCANFDEN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT) & FLEXCAN_CTRL2_ISOCANFDEN_MASK;

    obj->CTRL2 = tempReg;
}

/*! \brief Get edge filter enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: edge filter enable
 *              0: edge filter enable
 *              1: edge filter disable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Edfltdis(const FlexCanRegType *obj)
{
    return ((obj->CTRL2 & FLEXCAN_CTRL2_EDFLTDIS_MASK) >> FLEXCAN_CTRL2_EDFLTDIS_SHIFT);
}

/*! \brief Set edge filter enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] value : edge filter enable
 *              0: edge filter enable
 *              1: edge filter disable
 * 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Edfltdis(FlexCanRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CTRL2;

    tmp &= ~FLEXCAN_CTRL2_EDFLTDIS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK);
    obj->CTRL2 = tmp;
}

/*! \brief Get lowest priority Tx mailbox 
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: lowest priority Tx mailbox 
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Lptm(const FlexCanRegType *obj)
{
    return ((obj->ESR2 & FLEXCAN_ESR2_LPTM_MASK) >> FLEXCAN_ESR2_LPTM_SHIFT);
}

/*! \brief Get valid priority status
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: valid priority status
 *              0: contents of IMB and LPTM are invalid
 *              1: contents of IMB and LPTM are valid
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Vps(const FlexCanRegType *obj)
{
    return ((obj->ESR2 & FLEXCAN_ESR2_VPS_MASK) >> FLEXCAN_ESR2_VPS_SHIFT);
}

/*! \brief Get Inactive mailbox
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Inactive mailbox
 *              0: if CAN_ESR2.VPS is asserted, CAN_ESR2.LPTM is not an inactive mailbox
 *              1: if CAN_ESR2.VPS is asserted, there is at least one inactive maibox.
 *                 CAN_ESR2.LPTM content is the number of the first one
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Imb(const FlexCanRegType *obj)
{
    return ((obj->ESR2 & FLEXCAN_ESR2_IMB_MASK) >> FLEXCAN_ESR2_IMB_SHIFT);
}

/*! \brief Get CRC mailbox
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: CRC mailbox, indicats the number of the mailbox corresponding to the value
 *          in the CAN_CRCR.TXCRC field
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCrcrMbcrc(const FlexCanRegType *obj)
{
    return ((obj->CRCR & FLEXCAN_CRCR_MBCRC_MASK) >> FLEXCAN_CRCR_MBCRC_SHIFT);
}

/*! \brief Get transmitted CRC mailbox
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: transmitted CRC mailbox, indicats the CRC value of the last transmitted
 *          message for non-FD frames
 *
 */
__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetCrcrTxcrc(const FlexCanRegType *obj)
{
    return ((obj->CRCR & FLEXCAN_CRCR_TXCRC_MASK) >> FLEXCAN_CRCR_TXCRC_SHIFT);
}

/*! \brief Get Rx FIFO global mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: Rx FIFO global mask
 *
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxFifoGlobalMask(FlexCanRegType *obj)
{
    return (obj->RXFGMASK);
}

/*! \brief Set Rx FIFO global mask
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : Rx FIFO global mask
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxFifoGlobalMask(FlexCanRegType *obj, uint32_t val)
{
    obj->RXFGMASK = val;
}

/*! \brief Get identifier acceptance filter hit indicator
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: identifier acceptance filter hit indicator
 *
 */
__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetRxfirIdhit(const FlexCanRegType *obj)
{
    return ((obj->RXFIR & FLEXCAN_RXFIR_IDHIT_MASK) >> FLEXCAN_RXFIR_IDHIT_SHIFT);
}

/*! \brief Get extended bit timing format enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended bit timing format enable
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtendedBitTimingEnable(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_BTF_MASK) >> FLEXCAN_CBT_BTF_SHIFT);
}

/*! \brief Set extended bit timing format enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended bit timing format enable
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtendedBitTimingEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_BTF_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_CBT_BTF_SHIFT) & FLEXCAN_CBT_BTF_MASK;

    obj->CBT = tempReg;
}

/*! \brief Get extended prescaler division factor
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended prescaler division factor
 *
 */
__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetExtPresalerDivision(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_EPRESDIV_MASK) >> FLEXCAN_CBT_EPRESDIV_SHIFT);
}

/*! \brief Set extended prescaler division factor
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended prescaler division factor
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtPresalerDivision(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_EPRESDIV_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CBT_EPRESDIV_SHIFT) & FLEXCAN_CBT_EPRESDIV_MASK;

    obj->CBT = tempReg;
}

/*! \brief Get extended resync jump width
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended resync jump width
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtResyncJumpWidth(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_ERJW_MASK) >> FLEXCAN_CBT_ERJW_SHIFT);
}

/*! \brief Set extended resync jump width
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended resync jump width
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtResyncJumpWidth(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_ERJW_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CBT_ERJW_SHIFT) & FLEXCAN_CBT_ERJW_MASK;

    obj->CBT = tempReg;
}

/*! \brief Get extended propagation segment
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended propagation segment
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPorpSeg(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_EPROPSEG_MASK) >> FLEXCAN_CBT_EPROPSEG_SHIFT);
}

/*! \brief Set extended propagation segment
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended propagation segment
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtPorpSeg(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_EPROPSEG_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CBT_EPROPSEG_SHIFT) & FLEXCAN_CBT_EPROPSEG_MASK;

    obj->CBT = tempReg;
}

/*! \brief Get extended phase segment 1
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended phase segment 1
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPhaseSeg1(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_EPSEG1_MASK) >> FLEXCAN_CBT_EPSEG1_SHIFT);
}

/*! \brief Set extended phase segment 1
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended phase segment 1
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtPhaseSeg1(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_EPSEG1_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CBT_EPSEG1_SHIFT) & FLEXCAN_CBT_EPSEG1_MASK;

    obj->CBT = tempReg;
}

/*! \brief Get extended phase segment 2
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return: extended phase segment 2
 *
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPhaseSeg2(const FlexCanRegType *obj)
{
    return ((obj->CBT & FLEXCAN_CBT_EPSEG2_MASK) >> FLEXCAN_CBT_EPSEG2_SHIFT);
}

/*! \brief Set extended phase segment 2
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : extended phase segment 2
 *
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetExtPhaseSeg2(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->CBT;
    tempReg &= (~FLEXCAN_CBT_EPSEG2_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_CBT_EPSEG2_SHIFT) & FLEXCAN_CBT_EPSEG2_MASK;

    obj->CBT = tempReg;
}

/*! \brief Set Rx individual mask n
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] num : number of Rx individual mask
 * \param[in] mask: mask
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRxIndividualMask(FlexCanRegType *obj, uint8_t num, uint32_t mask)
{
    obj->RXIMR[num] = mask;
}

/*! \brief Get Rx individual mask n
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] num : number of Rx individual mask
 * \return : mask value
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxIndividualMask(FlexCanRegType *obj, uint8_t num)
{
    return (obj->RXIMR[num]);
}

/*! \brief Get bit rate switch enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : bit rate switch enable
 *               0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect
 *               1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is
 *                  recessive
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdRateSwitch(const FlexCanRegType *obj)
{
    return ((obj->FDCTRL & FLEXCAN_FDCTRL_FDRATE_MASK) >> FLEXCAN_FDCTRL_FDRATE_SHIFT);
}

/*! \brief Set bit rate switch enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : bit rate switch enable
 *               0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect
 *               1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is
 *                  recessive 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdRateSwitch(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->FDCTRL;
    tempReg &= (~FLEXCAN_FDCTRL_FDRATE_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_FDCTRL_FDRATE_SHIFT) & FLEXCAN_FDCTRL_FDRATE_MASK;

    obj->FDCTRL = tempReg;
}

/*! \brief Set message buffer data size for region n
 *
 * \param[in] obj     : pointer to FlexCAN register instance
 * \param[in] region  : region number
 * \param[in] sizeSel : message buffer data size for region n
 *               00: selects 8 bytes per message buffer
 *               01: selects 16 bytes per message buffer
 *               10: selects 32 bytes per message buffer
 *               11: selects 64 bytes per message buffer
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetRegionDataSizeSel(FlexCanRegType *obj, uint8_t region, uint8_t sizeSel)
{
    uint32_t tempReg;
    tempReg = obj->FDCTRL;

    switch(region)
    {
    case 0:
        tempReg &= (~FLEXCAN_FDCTRL_MBDSR0_MASK);
        tempReg |= (((uint32_t)sizeSel) << FLEXCAN_FDCTRL_MBDSR0_SHIFT) & FLEXCAN_FDCTRL_MBDSR0_MASK;
        break;
    case 1:
        tempReg &= (~FLEXCAN_FDCTRL_MBDSR1_MASK);
        tempReg |= (((uint32_t)sizeSel) << FLEXCAN_FDCTRL_MBDSR1_SHIFT) & FLEXCAN_FDCTRL_MBDSR1_MASK;
        break;
    case 2:
        tempReg &= (~FLEXCAN_FDCTRL_MBDSR2_MASK);
        tempReg |= (((uint32_t)sizeSel) << FLEXCAN_FDCTRL_MBDSR2_SHIFT) & FLEXCAN_FDCTRL_MBDSR2_MASK;
        break;
    case 3:
        tempReg &= (~FLEXCAN_FDCTRL_MBDSR3_MASK);
        tempReg |= (((uint32_t)sizeSel) << FLEXCAN_FDCTRL_MBDSR3_SHIFT) & FLEXCAN_FDCTRL_MBDSR3_MASK;
        break;
    default:
        /* size select wrong, do something */
        break;
    }

    obj->FDCTRL = tempReg;
}

/*! \brief Get message buffer data size for region n
 *
 * \param[in] obj     : pointer to FlexCAN register instance
 * \param[in] region  : region number
 * \return            : message buffer data size for region n
 *                        00: selects 8 bytes per message buffer
 *                        01: selects 16 bytes per message buffer
 *                        10: selects 32 bytes per message buffer
 *                        11: selects 64 bytes per message buffer
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRegionDataSizeSel(FlexCanRegType *obj, uint8_t region)
{
    uint8_t retVal = 0;

    switch(region)
    {
    case 0:
        retVal = (uint8_t)((obj->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_MASK) >> FLEXCAN_FDCTRL_MBDSR0_SHIFT);
        break;
    case 1:
        retVal = (uint8_t)((obj->FDCTRL & FLEXCAN_FDCTRL_MBDSR1_MASK) >> FLEXCAN_FDCTRL_MBDSR1_SHIFT);
        break;
    case 2:
        retVal = (uint8_t)((obj->FDCTRL & FLEXCAN_FDCTRL_MBDSR2_MASK) >> FLEXCAN_FDCTRL_MBDSR2_SHIFT);
        break;
    case 3:
        retVal = (uint8_t)((obj->FDCTRL & FLEXCAN_FDCTRL_MBDSR3_MASK) >> FLEXCAN_FDCTRL_MBDSR3_SHIFT);
        break;
    default:
        /* size select wrong, do something */
        break;
    }

    return retVal;
}

/*! \brief Get bit rate switch enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : bit rate switch enable
 *               0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect
 *               1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is
 *                  recessive
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTdcEnable(const FlexCanRegType *obj)
{
    return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCEN_MASK) >> FLEXCAN_FDCTRL_TDCEN_SHIFT);
}

/*! \brief Set bit rate switch enable
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] enable : bit rate switch enable
 *               0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect
 *               1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is
 *                  recessive 
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetTdcEnable(FlexCanRegType *obj, uint8_t enable)
{
    uint32_t tempReg;
    tempReg = obj->FDCTRL;
    tempReg &= (~FLEXCAN_FDCTRL_TDCEN_MASK);
    tempReg |= (((uint32_t)enable) << FLEXCAN_FDCTRL_TDCEN_SHIFT) & FLEXCAN_FDCTRL_TDCEN_MASK;

    obj->FDCTRL = tempReg;
}

/*! \brief Get transceiver delay compensation fail
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : transceiver delay compensation fail
 *               0: measured loop delay is in range
 *               1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is
 *                  recessive
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcfail(const FlexCanRegType *obj)
{
    return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCFAIL_MASK) >> FLEXCAN_FDCTRL_TDCFAIL_SHIFT);
}

/*! \brief Clear transceiver delay compensation fail
 *
 * \param[in] obj : pointer to FlexCAN register instance
 */
__attribute__((always_inline)) static inline void FlexCanReg_ClearFdctrlTdcfail(FlexCanRegType *obj)
{
    uint32_t tmp = obj->FDCTRL;

    tmp |= (((uint32_t)(((uint32_t)(1)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK);
    obj->FDCTRL = tmp;
}

/*! \brief Get transceiver delay compensation offset
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : transceiver delay compensation offset
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcoff(const FlexCanRegType *obj)
{
    return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCOFF_MASK) >> FLEXCAN_FDCTRL_TDCOFF_SHIFT);
}

/*! \brief Set transceiver delay compensation offset
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] offset : transceiver delay compensation offset
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetTdcOffset(FlexCanRegType *obj, uint8_t offset)
{
    uint32_t tempReg;
    tempReg = obj->FDCTRL;
    tempReg &= (~FLEXCAN_FDCTRL_TDCOFF_MASK);
    tempReg |= (((uint32_t)offset) << FLEXCAN_FDCTRL_TDCOFF_SHIFT) & FLEXCAN_FDCTRL_TDCOFF_MASK;

    obj->FDCTRL = tempReg;
}

/*! \brief Get transceiver delay compensation value
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : transceiver delay compensation value
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcval(const FlexCanRegType *obj)
{
    return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCVAL_MASK) >> FLEXCAN_FDCTRL_TDCVAL_SHIFT);
}

/*! \brief Get fast prescaler division factor
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : fast prescaler division factor
 */
__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetFdPrescalerDivision(const FlexCanRegType *obj)
{
    return ((obj->FDCBT & FLEXCAN_FDCBT_FPRESDIV_MASK) >> FLEXCAN_FDCBT_FPRESDIV_SHIFT);
}

/*! \brief Set fast prescaler division factor
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : fast prescaler division factor
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdPrescalerDivision(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->FDCBT;
    tempReg &= (~FLEXCAN_FDCBT_FPRESDIV_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_FDCBT_FPRESDIV_SHIFT) & FLEXCAN_FDCBT_FPRESDIV_MASK;

    obj->FDCBT = tempReg;
}

/*! \brief Get fast resync jump width
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : fast resync jump width
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdResyncJumpWidth(const FlexCanRegType *obj)
{
    return ((obj->FDCBT & FLEXCAN_FDCBT_FRJW_MASK) >> FLEXCAN_FDCBT_FRJW_SHIFT);
}

/*! \brief Set fast resync jump width
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : fast resync jump width
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdResyncJumpWidth(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->FDCBT;
    tempReg &= (~FLEXCAN_FDCBT_FRJW_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_FDCBT_FRJW_SHIFT) & FLEXCAN_FDCBT_FRJW_MASK;

    obj->FDCBT = tempReg;
}

/*! \brief Get fast propagation segment
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : fast propagation segment
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPorpSeg(const FlexCanRegType *obj)
{
    return ((obj->FDCBT & FLEXCAN_FDCBT_FPROPSEG_MASK) >> FLEXCAN_FDCBT_FPROPSEG_SHIFT);
}

/*! \brief Set fast propagation segment
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : fast propagation segment
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdPorpSeg(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->FDCBT;
    tempReg &= (~FLEXCAN_FDCBT_FPROPSEG_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_FDCBT_FPROPSEG_SHIFT) & FLEXCAN_FDCBT_FPROPSEG_MASK;

    obj->FDCBT = tempReg;
}

/*! \brief Get fast phase segment 1
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : fast phase segment 1
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPhaseSeg1(const FlexCanRegType *obj)
{
    return ((obj->FDCBT & FLEXCAN_FDCBT_FPSEG1_MASK) >> FLEXCAN_FDCBT_FPSEG1_SHIFT);
}

/*! \brief Set fast phase segment 1
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : fast phase segment 1
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdPhaseSeg1(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->FDCBT;
    tempReg &= (~FLEXCAN_FDCBT_FPSEG1_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_FDCBT_FPSEG1_SHIFT) & FLEXCAN_FDCBT_FPSEG1_MASK;

    obj->FDCBT = tempReg;
}

/*! \brief Get fast phase segment 2
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : fast phase segment 2
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPhaseSeg2(const FlexCanRegType *obj)
{
    return ((obj->FDCBT & FLEXCAN_FDCBT_FPSEG2_MASK) >> FLEXCAN_FDCBT_FPSEG2_SHIFT);
}

/*! \brief Set fast phase segment 2
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \param[in] val : fast phase segment 2
 */
__attribute__((always_inline)) static inline void FlexCanReg_SetFdPhaseSeg2(FlexCanRegType *obj, uint16_t val)
{
    uint32_t tempReg;
    tempReg = obj->FDCBT;
    tempReg &= (~FLEXCAN_FDCBT_FPSEG2_MASK);
    tempReg |= (((uint32_t)val) << FLEXCAN_FDCBT_FPSEG2_SHIFT) & FLEXCAN_FDCBT_FPSEG2_MASK;

    obj->FDCBT = tempReg;
}

/*! \brief Get crc mailbox number for FD_TXCRC
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : crc mailbox number for FD_TXCRC
 */
__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdcrcFdmbcrc(const FlexCanRegType *obj)
{
    return ((obj->FDCRC & CAN_FDCRC_FDMBCRC_MASK) >> CAN_FDCRC_FDMBCRC_SHIFT);
}

/*! \brief Get extended transmitted CRC value
 *
 * \param[in] obj : pointer to FlexCAN register instance
 * \return : extended transmitted CRC value
 */
__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetFdcrcFdtxcrc(const FlexCanRegType *obj)
{
    return ((obj->FDCRC & CAN_FDCRC_FDTXCRC_MASK) >> CAN_FDCRC_FDTXCRC_SHIFT);
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _FLEXCAN_REG_H_ */
