/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _SCG0_REG_H_
#define _SCG0_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the SCG0 Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* TRIM Bit Fields */
#define SCG0_TRIM_AUTO_GC_EN_MASK          (0x100000u)
#define SCG0_TRIM_AUTO_GC_EN_SHIFT         (20u)
#define SCG0_TRIM_AUTO_GC_EN_WIDTH         (1u)

/* OSC_CTRL Bit Fields */
#define SCG0_OSC_CTRL_EN_EXT_CLK_MASK      (0x10u)
#define SCG0_OSC_CTRL_EN_EXT_CLK_SHIFT     (4u)
#define SCG0_OSC_CTRL_EN_EXT_CLK_WIDTH     (1u)
#define SCG0_OSC_CTRL_RANGE_MASK           (0x0Cu)
#define SCG0_OSC_CTRL_RANGE_SHIFT          (2u)
#define SCG0_OSC_CTRL_RANGE_WIDTH          (2u)
#define SCG0_OSC_CTRL_EN_SOSC_MASK         (0x01u)
#define SCG0_OSC_CTRL_EN_SOSC_SHIFT        (0u)
#define SCG0_OSC_CTRL_EN_SOSC_WIDTH        (1u)

/* PLL_CTRL0 Bit Fields */
#define SCG0_PLL_CTRL0_PLL_OUTDIV_MASK     (0x4000000u)
#define SCG0_PLL_CTRL0_PLL_OUTDIV_SHIFT    (26u)
#define SCG0_PLL_CTRL0_PLL_OUTDIV_WIDTH    (1u)
#define SCG0_PLL_CTRL0_PLL_POSDIV_MASK     (0x3800u)
#define SCG0_PLL_CTRL0_PLL_POSDIV_SHIFT    (11u)
#define SCG0_PLL_CTRL0_PLL_POSDIV_WIDTH    (3u)
#define SCG0_PLL_CTRL0_PLL_PREDIV_MASK     (0x300u)
#define SCG0_PLL_CTRL0_PLL_PREDIV_SHIFT    (8u)
#define SCG0_PLL_CTRL0_PLL_PREDIV_WIDTH    (2u)
#define SCG0_PLL_CTRL0_PLL_M_MASK          (0xFEu)
#define SCG0_PLL_CTRL0_PLL_M_SHIFT         (1u)
#define SCG0_PLL_CTRL0_PLL_M_WIDTH         (7u)
#define SCG0_PLL_CTRL0_PLL_EN_MASK         (0x01u)
#define SCG0_PLL_CTRL0_PLL_EN_SHIFT        (0u)
#define SCG0_PLL_CTRL0_PLL_EN_WIDTH        (1u)

/* PLL_CTRL1 Bit Fields */
#define SCG0_PLL_CTRL1_PLL_CLKIN_SEL_MASK  (0x10u)
#define SCG0_PLL_CTRL1_PLL_CLKIN_SEL_SHIFT (4u)
#define SCG0_PLL_CTRL1_PLL_CLKIN_SEL_WIDTH (1u)

/* STATUS Bit Fields */
#define SCG0_STATUS_SCG0_LOCK_MASK         (0x08u)
#define SCG0_STATUS_SCG0_LOCK_SHIFT        (3u)
#define SCG0_STATUS_SCG0_LOCK_WIDTH        (1u)
#define SCG0_STATUS_SOSC_RDY_MASK          (0x04u)
#define SCG0_STATUS_SOSC_RDY_SHIFT         (2u)
#define SCG0_STATUS_SOSC_RDY_WIDTH         (1u)
#define SCG0_STATUS_SIRC_8M_RDY_MASK       (0x02u)
#define SCG0_STATUS_SIRC_8M_RDY_SHIFT      (1u)
#define SCG0_STATUS_SIRC_8M_RDY_WIDTH      (1u)
#define SCG0_STATUS_PLL_LOCK_MASK          (0x01u)
#define SCG0_STATUS_PLL_LOCK_SHIFT         (0u)
#define SCG0_STATUS_PLL_LOCK_WIDTH         (1u)

/* ADC Bit Fields */
#define SCG0_ADC_TRG_SRC_MASK              (0x20u)
#define SCG0_ADC_TRG_SRC_SHIFT             (5u)
#define SCG0_ADC_TRG_SRC_WIDTH             (1u)
#define SCG0_ADC_PRETRG_SW_SRC_MASK        (0x1Cu)
#define SCG0_ADC_PRETRG_SW_SRC_SHIFT       (2u)
#define SCG0_ADC_PRETRG_SW_SRC_WIDTH       (3u)
#define SCG0_ADC_PRETRG_SRC_MASK           (0x03u)
#define SCG0_ADC_PRETRG_SRC_SHIFT          (0u)
#define SCG0_ADC_PRETRG_SRC_WIDTH          (2u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of SCG0 registers
 */
typedef struct _Scg0RegType_
{
    volatile uint32_t TRIM;          /*!< Trimming code register, offset: 0x0 */
    uint32_t          RESERVED0[2];  /*!< Reserverd block, offset: 0x4 */
    volatile uint32_t OSC_CTRL;      /*!< oscillator control register, offset: 0xC */
    uint32_t          RESERVED1[1];  /*!< Reserverd block, offset: 0x10 */
    volatile uint32_t PLL_CTRL0;     /*!< phase lock loop control0 register, offset: 0x14 */
    volatile uint32_t PLL_CTRL1;     /*!< MISC phase lock loop control1 register, offset: 0x18 */
    uint32_t          RESERVED2[1];  /*!< Reserverd block, offset: 0x1C */
    volatile uint32_t STATUS;        /*!< status register, offset: 0x20 */
    uint32_t          RESERVED3[3];  /*!< Reserverd block, offset: 0x24 */
    volatile uint32_t ADC;           /*!< system ADC register, offset: 0x30 */
    uint32_t          RESERVED4[11]; /*!< Reserverd block, offset: 0x34 */
    volatile uint32_t KEY;           /*!< key register, offset: 0x60 */
} Scg0RegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the EEE auto garbage collection enable
 *
 * This function gets the current EEE auto garbage collection enable.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return EEE auto garbage collection enable
 *         - 1 : enable auto eee garbage collection;
 *         - 0 : disable auto eee garbage collection;
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetTrimAutoGcEn(const Scg0RegType *obj)
{
    return ((obj->TRIM & SCG0_TRIM_AUTO_GC_EN_MASK) >> SCG0_TRIM_AUTO_GC_EN_SHIFT);
}

/*! \brief Sets the EEE auto garbage collection enable
 *
 * This function sets the EEE auto garbage collection enable.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of EEE auto garbage collection enable
 *                    - 1 : enable auto eee garbage collection;
 *                    - 0 : disable auto eee garbage collection;
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetTrimAutoGcEn(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TRIM;

    tmp &= ~SCG0_TRIM_AUTO_GC_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_TRIM_AUTO_GC_EN_SHIFT)) & SCG0_TRIM_AUTO_GC_EN_MASK);
    obj->TRIM = tmp;
}

/*! \brief Gets the External clock input through XIN pin enable
 *
 * This function gets the current External clock input through XIN pin enable.
 * Enable external clock input through XIN pin. When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return External clock input through XIN pin enable
 *         - 0b : disable.
 *         - 1b : enable.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetOscCtrlEnExtClk(const Scg0RegType *obj)
{
    return ((obj->OSC_CTRL & SCG0_OSC_CTRL_EN_EXT_CLK_MASK) >> SCG0_OSC_CTRL_EN_EXT_CLK_SHIFT);
}

/*! \brief Sets the External clock input through XIN pin enable
 *
 * This function sets the External clock input through XIN pin enable.
 * Enable external clock input through XIN pin. When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of External clock input through XIN pin enable
 *                    - 0b : disable.
 *                    - 1b : enable.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetOscCtrlEnExtClk(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->OSC_CTRL;

    tmp &= ~SCG0_OSC_CTRL_EN_EXT_CLK_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_OSC_CTRL_EN_EXT_CLK_SHIFT)) & SCG0_OSC_CTRL_EN_EXT_CLK_MASK);
    obj->OSC_CTRL = tmp;
}

/*! \brief Gets the SOSC frequency range
 *
 * This function gets the current SOSC frequency range.
 * SOSC frequency range select, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return SOSC frequency range
 *         - 00b : Low frequency range selected for the crystal oscillator(4M);
 *         - 01b : Medium frequency range selected for the crytstal oscillator(4M~8M)
 *         - 10b : Medium frequency range selected for the crytstal oscillator(8M~24M)
 *         - 11b : High frequency range selected for the crystal oscillator(24M~40M)
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetOscCtrlRange(const Scg0RegType *obj)
{
    return ((obj->OSC_CTRL & SCG0_OSC_CTRL_RANGE_MASK) >> SCG0_OSC_CTRL_RANGE_SHIFT);
}

/*! \brief Sets the SOSC frequency range
 *
 * This function sets the SOSC frequency range.
 * SOSC frequency range select, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of SOSC frequency range
 *                    - 00b : Low frequency range selected for the crystal oscillator(4M);
 *                    - 01b : Medium frequency range selected for the crytstal oscillator(4M~8M)
 *                    - 10b : Medium frequency range selected for the crytstal oscillator(8M~24M)
 *                    - 11b : High frequency range selected for the crystal oscillator(24M~40M)
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetOscCtrlRange(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->OSC_CTRL;

    tmp &= ~SCG0_OSC_CTRL_RANGE_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_OSC_CTRL_RANGE_SHIFT)) & SCG0_OSC_CTRL_RANGE_MASK);
    obj->OSC_CTRL = tmp;
}

/*! \brief Gets the System oscillator (crystal osc) enable
 *
 * This function gets the current System oscillator (crystal osc) enable.
 * System oscillator (crystal osc) enable control, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return System oscillator (crystal osc) enable
 *         - 0b : SOSC disable.
 *         - 1b : SOSC enable.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetOscCtrlEnSosc(const Scg0RegType *obj)
{
    return ((obj->OSC_CTRL & SCG0_OSC_CTRL_EN_SOSC_MASK) >> SCG0_OSC_CTRL_EN_SOSC_SHIFT);
}

/*! \brief Sets the System oscillator (crystal osc) enable
 *
 * This function sets the System oscillator (crystal osc) enable.
 * System oscillator (crystal osc) enable control, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of System oscillator (crystal osc) enable
 *                    - 0b : SOSC disable.
 *                    - 1b : SOSC enable.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetOscCtrlEnSosc(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->OSC_CTRL;

    tmp &= ~SCG0_OSC_CTRL_EN_SOSC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_OSC_CTRL_EN_SOSC_SHIFT)) & SCG0_OSC_CTRL_EN_SOSC_MASK);
    obj->OSC_CTRL = tmp;
}

/*! \brief Gets the PLL OUT DIV Setting
 *
 * This function gets the current PLL OUT DIV Setting.
 * 1 stand for div2, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL OUT DIV Setting
 *         - 0b : divider 1.
 *         - 1b : divider 2.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl0PllOutDiv(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL0 & SCG0_PLL_CTRL0_PLL_OUTDIV_MASK) >> SCG0_PLL_CTRL0_PLL_OUTDIV_SHIFT);
}

/*! \brief Sets the PLL OUT DIV Setting
 *
 * This function sets the PLL OUT DIV Setting.
 * 1 stand for div2, When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL OUT DIV Setting
 *                    - 0b : divider 1.
 *                    - 1b : divider 2.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl0PllOutDiv(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL0;

    tmp &= ~SCG0_PLL_CTRL0_PLL_OUTDIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL0_PLL_OUTDIV_SHIFT)) & SCG0_PLL_CTRL0_PLL_OUTDIV_MASK);
    obj->PLL_CTRL0 = tmp;
}

/*! \brief Gets the PLL post-divide
 *
 * This function gets the current PLL post-divide.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL post-divide
 *         - 000b : 8
 *         - 001b : 1
 *         - 010b : 2
 *         - 011b : 3
 *             .
 *             .
 *             .
 *         - 111b : 7
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl0PllPosDiv(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL0 & SCG0_PLL_CTRL0_PLL_POSDIV_MASK) >> SCG0_PLL_CTRL0_PLL_POSDIV_SHIFT);
}

/*! \brief Sets the PLL post-divide
 *
 * This function sets the PLL post-divide.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL post-divide
 *                    - 000b : 8
 *                    - 001b : 1
 *                    - 010b : 2
 *                    - 011b : 3
 *                        .
 *                        .
 *                        .
 *                    - 111b : 7
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl0PllPosDiv(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL0;

    tmp &= ~SCG0_PLL_CTRL0_PLL_POSDIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL0_PLL_POSDIV_SHIFT)) & SCG0_PLL_CTRL0_PLL_POSDIV_MASK);
    obj->PLL_CTRL0 = tmp;
}

/*! \brief Gets the PLL pre-divider setting
 *
 * This function gets the current PLL pre-divider setting.
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL pre-divider setting
 *         - 00b : 1.
 *         - 01b : 2.
 *         - 10b : 4.
 *         - 11b : 8.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl0PllPreDiv(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL0 & SCG0_PLL_CTRL0_PLL_PREDIV_MASK) >> SCG0_PLL_CTRL0_PLL_PREDIV_SHIFT);
}

/*! \brief Sets the PLL pre-divider setting
 *
 * This function sets the PLL pre-divider setting.
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL pre-divider setting
 *                    - 00b : 1.
 *                    - 01b : 2.
 *                    - 10b : 4.
 *                    - 11b : 8.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl0PllPreDiv(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL0;

    tmp &= ~SCG0_PLL_CTRL0_PLL_PREDIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL0_PLL_PREDIV_SHIFT)) & SCG0_PLL_CTRL0_PLL_PREDIV_MASK);
    obj->PLL_CTRL0 = tmp;
}

/*! \brief Gets the PLL feedback divider setting
 *
 * This function gets the current PLL feedback divider setting.
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL feedback divider setting
 *         - 0000001b : 1.
 *         - 0000010b : 2.
 *              .
 *              .
 *              .
 *         - 1111111b : 127.
 *         - 0000000b : 128.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl0PllM(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL0 & SCG0_PLL_CTRL0_PLL_M_MASK) >> SCG0_PLL_CTRL0_PLL_M_SHIFT);
}

/*! \brief Sets the PLL feedback divider setting
 *
 * This function sets the PLL feedback divider setting.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL feedback divider setting
 *                    - 0000001b : 1.
 *                    - 0000010b : 2.
 *                         .
 *                         .
 *                         .
 *                    - 1111111b : 127.
 *                    - 0000000b : 128.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl0PllM(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL0;

    tmp &= ~SCG0_PLL_CTRL0_PLL_M_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL0_PLL_M_SHIFT)) & SCG0_PLL_CTRL0_PLL_M_MASK);
    obj->PLL_CTRL0 = tmp;
}

/*! \brief Gets the PLL enable
 *
 * This function gets the current PLL enable.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL enable
 *         - 0 : disable.
 *         - 1 : enable.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl0PllEn(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL0 & SCG0_PLL_CTRL0_PLL_EN_MASK) >> SCG0_PLL_CTRL0_PLL_EN_SHIFT);
}

/*! \brief Sets the PLL enable
 *
 * This function sets the PLL enable.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL enable
 *                    - 0 : disable.
 *                    - 1 : enable.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl0PllEn(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL0;

    tmp &= ~SCG0_PLL_CTRL0_PLL_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL0_PLL_EN_SHIFT)) & SCG0_PLL_CTRL0_PLL_EN_MASK);
    obj->PLL_CTRL0 = tmp;
}

/*! \brief Gets the PLL input clock source select
 *
 * This function gets the current PLL input clock source select.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL input clock source select
 *         - 0 : SOSC.
 *         - 1 : SIRC.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetPllCtrl1PllClkinSel(const Scg0RegType *obj)
{
    return ((obj->PLL_CTRL1 & SCG0_PLL_CTRL1_PLL_CLKIN_SEL_MASK) >> SCG0_PLL_CTRL1_PLL_CLKIN_SEL_SHIFT);
}

/*! \brief Sets the PLL input clock source select
 *
 * This function sets the PLL input clock source select.
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of PLL input clock source select
 *                    - 0 : SOSC.
 *                    - 1 : SIRC.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetPllCtrl1PllClkinSel(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PLL_CTRL1;

    tmp &= ~SCG0_PLL_CTRL1_PLL_CLKIN_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_PLL_CTRL1_PLL_CLKIN_SEL_SHIFT)) & SCG0_PLL_CTRL1_PLL_CLKIN_SEL_MASK);
    obj->PLL_CTRL1 = tmp;
}

/*! \brief Gets the scg0 lock enable status
 *
 * This function gets the current scg0 lock enable status.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return scg0 lock enable status
 *         - 0b : disalbe.
 *         - 1b : enable.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetStatusKeyLock(const Scg0RegType *obj)
{
    return ((obj->STATUS & SCG0_STATUS_SCG0_LOCK_MASK) >> SCG0_STATUS_SCG0_LOCK_SHIFT);
}

/*! \brief Gets the Sytem oscillator clock ready flag
 *
 * This function gets the current Sytem oscillator clock ready flag.
 * if use external, this flag is not used
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return Sytem oscillator clock ready flag
 *         - 1b : SOSC ready.
 *         - 0b : SOSC not ready.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetStatusSoscRdy(const Scg0RegType *obj)
{
    return ((obj->STATUS & SCG0_STATUS_SOSC_RDY_MASK) >> SCG0_STATUS_SOSC_RDY_SHIFT);
}

/*! \brief Gets the SIRC clock ready flag
 *
 * This function gets the current SIRC clock ready flag.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return SIRC clock ready flag
 *         - 1b : ready;
 *         - 0b : not ready
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetStatusSircRdy(const Scg0RegType *obj)
{
    return ((obj->STATUS & SCG0_STATUS_SIRC_8M_RDY_MASK) >> SCG0_STATUS_SIRC_8M_RDY_SHIFT);
}

/*! \brief Gets the PLL lock state
 *
 * This function gets the current PLL lock state.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return PLL lock state
 *         - 1b : Lock state;
 *         - 0b : Not lock state
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetStatusPllLock(const Scg0RegType *obj)
{
    return ((obj->STATUS & SCG0_STATUS_PLL_LOCK_MASK) >> SCG0_STATUS_PLL_LOCK_SHIFT);
}

/*! \brief Gets the adc trigger source
 *
 * This function gets the adc trigger source.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return adc trigger source
 *         - 0 : PDB trigger out.
 *         - 1 : TRGMUX output.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetAdcTrgSrc(const Scg0RegType *obj)
{
    return ((obj->ADC & SCG0_ADC_TRG_SRC_MASK) >> SCG0_ADC_TRG_SRC_SHIFT);
}

/*! \brief Sets the adc trigger source
 *
 * This function sets the adc trigger source
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of the adc trigger source
 *                    - 0 : PDB trigger out.
 *                    - 1 : TRGMUX output.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetAdcTrgSrc(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SCG0_ADC_TRG_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_ADC_TRG_SRC_SHIFT)) & SCG0_ADC_TRG_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Gets adc software pre trigger source
 *
 * This function gets adc software pre trigger source.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return adc software pre trigger source
 *         - 0 : pre trigger 0.
 *         - 1 : pre trigger 1.
 *         - 2 : pre trigger 2.
 *         - 3 : pre trigger 3.
 *         - others : reserved.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetAdcPreTrgSwSrc(const Scg0RegType *obj)
{
    return ((obj->ADC & SCG0_ADC_PRETRG_SW_SRC_MASK) >> SCG0_ADC_PRETRG_SW_SRC_SHIFT);
}

/*! \brief Sets adc software pre trigger source
 *
 * This function sets adc software pre trigger source
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of the adc software pre trigger source
 *         - 0 : pre trigger 0.
 *         - 1 : pre trigger 1.
 *         - 2 : pre trigger 2.
 *         - 3 : pre trigger 3.
 *         - others : reserved.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetAdcPreTrgSwSrc(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SCG0_ADC_PRETRG_SW_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_ADC_PRETRG_SW_SRC_SHIFT)) & SCG0_ADC_PRETRG_SW_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Gets adc pre trigger source
 *
 * This function gets adc pre trigger source.
 * When write-lock disabled, this register can be written..
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \return adc pre trigger source
 *         - 0 : PDB trigger out.
 *         - 1 : TRGMUX output.
 *         - 2 : software configure PRETRG_SW_SRC.
 *         - 3 : no hardware trigger.
 */
__attribute__((always_inline)) static inline uint8_t Scg0Reg_GetAdcPreTrgSrc(const Scg0RegType *obj)
{
    return ((obj->ADC & SCG0_ADC_PRETRG_SRC_MASK) >> SCG0_ADC_PRETRG_SRC_SHIFT);
}

/*! \brief Sets adc pre trigger source
 *
 * This function sets adc pre trigger source
 * When write-lock disabled, this register can be written.
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of the adc pre trigger source
 *         - 0 : PDB trigger out.
 *         - 1 : TRGMUX output.
 *         - 2 : software configure PRETRG_SW_SRC.
 *         - 3 : no hardware trigger.
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetAdcPreTrgSrc(Scg0RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ADC;

    tmp &= ~SCG0_ADC_PRETRG_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << SCG0_ADC_PRETRG_SRC_SHIFT)) & SCG0_ADC_PRETRG_SRC_MASK);
    obj->ADC = tmp;
}

/*! \brief Sets the SCG0 public write key register
 *
 * This function sets the SCG0 public write key register.
 * SCG0 public write hit key, the initial confirm key is 0x1996_2020,
 * when cpu write data is 0x19962020. SCG0 function lock is invalid,
 * CPU can write the SCG0 function register.
 * When cpu write data is not equal 0x1996_2020, SCG0 function lock is valid,
 * CPU can not write the SCG0 function register
 *
 * \param[in] obj : pointer to SCG0 register instance
 * \param[in] value : the value of SCG0 public write key register
 */
__attribute__((always_inline)) static inline void Scg0Reg_SetKey(Scg0RegType *obj, uint32_t value)
{
    obj->KEY = value;
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _SCG0_REG_H_ */
