初版 LIN OK
This commit is contained in:
commit
c0e71a183b
1
.gitignore
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.gitignore
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||||
/LIN Slave/EWARM/Example
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||||
18
LIN Slave/.vscode/c_cpp_properties.json
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LIN Slave/.vscode/c_cpp_properties.json
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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24
LIN Slave/.vscode/launch.json
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LIN Slave/.vscode/launch.json
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77
LIN Slave/.vscode/settings.json
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77
LIN Slave/.vscode/settings.json
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||||
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||||
1000
LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cm0plus.h
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LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cm0plus.h
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Load Diff
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LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cmFunc.h
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LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cmFunc.h
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/**************************************************************************//**
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||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
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||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority with condition
|
||||
|
||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority with condition
|
||||
|
||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
916
LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cmInstr.h
Normal file
916
LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/core_cmInstr.h
Normal file
@ -0,0 +1,916 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
#else
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
#endif
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __builtin_clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
992
LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/fm33lg0xx.h
Normal file
992
LIN Slave/Drivers/CMSIS/Device/FM/FM33xx/Include/fm33lg0xx.h
Normal file
@ -0,0 +1,992 @@
|
||||
/**************************************************************************************************** * @file FM33LG0XX.h
|
||||
*
|
||||
* @brief CMSIS CORTEX-M0 Peripheral Access Layer Header File for
|
||||
* FM33LG0XX from Keil.
|
||||
*
|
||||
* @version V0.0.1
|
||||
* @date 14 july 2020
|
||||
*
|
||||
* @note Generated with SVDConv V2.87e
|
||||
* from CMSIS SVD File 'FM33LG0XX.SVD' Version 1.0,
|
||||
*
|
||||
* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontroller, but can be equally used for other
|
||||
* suitable processor architectures. This file can be freely distributed.
|
||||
* Modifications to this file shall be clearly marked.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*******************************************************************************************************/
|
||||
|
||||
|
||||
/** @addtogroup Keil
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FM33LG0XX
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __FM33LG0XX_H
|
||||
#define __FM33LG0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define __RCHF_INITIAL_CLOCK (8000000) /* Value of the Internal RC HIGH oscillator in Hz */
|
||||
#define __RCLP_CLOCK (32000) /* Value of the Internal RC LOW oscillator in Hz */
|
||||
#define __XTHF_CLOCK (8000000) /* Value of the EXTERNAL oscillator in Hz */
|
||||
#define __XTLF_CLOCK (32768) /* Value of the EXTERNAL oscillator in Hz */
|
||||
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */
|
||||
#define __MPU_PRESENT 1U /*!< MPU present or not */
|
||||
#define __VTOR_PRESENT 1U /*!< VTOR present or not */
|
||||
#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
||||
|
||||
/**
|
||||
* @brief FM33LG0XX Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
|
||||
Reset_IRQn = -15, /*!< 1 复位向量 */
|
||||
NMI_IRQn = -14, /*!< 2 WKUPx中断、低功耗模式错误中断 */
|
||||
HardFault_IRQn = -13, /*!< 3 HardFault中断向量 */
|
||||
SVC_IRQn = -5, /*!< 11 SVCall系统服务请求 */
|
||||
PendSV_IRQn = -2, /*!< 14 可挂起系统服务请求 */
|
||||
SysTick_IRQn = -1, /*!< 15 内部定时器中断向量 */
|
||||
|
||||
/* -------------------- FM33LG0XX specific Interrupt Numbers --------------------*/
|
||||
WWDT_IRQn = 0, /*!< 0 窗口看门狗或独立看门狗中断 */
|
||||
SVD_IRQn = 1, /*!< 1 电源监测报警中断 */
|
||||
RTCx_IRQn = 2, /*!< 2 实时时钟中断 */
|
||||
FLASH_IRQn = 3, /*!< 3 NVMIF中断 */
|
||||
FDET_IRQn = 4, /*!< 4 XTLF或XTHF停振检测中断、系统时钟选择错误中断 */
|
||||
ADC_IRQn = 5, /*!< 5 ADC转换完成中断 */
|
||||
DAC_IRQn = 6, /*!< 6 DAC中断 */
|
||||
SPI0_IRQn = 7, /*!< 7 SPI0中断 */
|
||||
SPI1_IRQn = 8, /*!< 8 SPI1中断 */
|
||||
SPI2_IRQn = 9, /*!< 9 SPI2中断 */
|
||||
UART0_IRQn = 10, /*!< 10 UART0中断 */
|
||||
UART1_IRQn = 11, /*!< 11 UART1中断 */
|
||||
UART3_IRQn = 12, /*!< 12 UART3中断 */
|
||||
UART4_IRQn = 13, /*!< 13 UART4中断 */
|
||||
UART5_IRQn = 14, /*!< 14 UART5中断 */
|
||||
LPUARTx_IRQn = 16, /*!< 16 LPUART0/1/2中断 */
|
||||
I2C_IRQn = 17, /*!< 17 I2C中断 */
|
||||
CCL_IRQn = 18, /*!< 18 时钟校准中断 */
|
||||
AES_IRQn = 19, /*!< 19 AES中断 */
|
||||
LPTIMx_IRQn = 20, /*!< 20 LPTIM16或LPTIM32中断 */
|
||||
DMA_IRQn = 21, /*!< 21 DMA中断 */
|
||||
WKUPx_IRQn = 22, /*!< 22 WKUP引脚中断 */
|
||||
LUT_IRQn = 23, /*!< 23 LUT中断 */
|
||||
BSTIM_IRQn = 24, /*!< 24 BSTIM16或BSTIM32中断 */
|
||||
COMPx_IRQn = 25, /*!< 25 COMPx中断 */
|
||||
GPTIM01_IRQn = 26, /*!< 26 通用定时器0,1中断 */
|
||||
GPTIM2_IRQn = 27, /*!< 27 通用定时器2中断 */
|
||||
ATIM_IRQn = 28, /*!< 28 高级定时器中断 */
|
||||
VREF_IRQn = 29, /*!< 29 1.2V内部基准电压建立中断、VREF_VREG中断 */
|
||||
GPIO_IRQn = 30, /*!< 30 外部引脚中断 */
|
||||
CAN_IRQn = 31, /*!< 31 CAN2.0中断 */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/** @addtogroup Configuration_of_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */
|
||||
#include "system_fm33lg0xx.h" /*!< FM33LG0XX System */
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Device Specific Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/** @addtogroup Device_Peripheral_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ FLS ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t RDCR; /*!< Flash Read Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t PFCR; /*!< Flash Prefetch Control Register, Address offset: 0x04 */
|
||||
__I uint32_t OPTBR; /*!< Flash Option Bytes Register, Address offset: 0x08 */
|
||||
__IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register1, Address offset: 0x0C */
|
||||
__IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register2, Address offset: 0x10 */
|
||||
__IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */
|
||||
__O uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */
|
||||
__IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */
|
||||
__IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */
|
||||
}FLASH_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ PMU ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< Power Management Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t WKTR; /*!< Wakeup Time Register, Address offset: 0x04 */
|
||||
__IO uint32_t WKFR; /*!< Wakeup Source Flags Register, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< PMU Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< PMU Interrupt and Status Register, Address offset: 0x10 */
|
||||
__IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x14 */
|
||||
__IO uint32_t ULPB_TR; /*!< ULPBG trim Register, Address offset: 0x38 */
|
||||
}PMU_Type;
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ VREFP ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< VREFP Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR; /*!< VREFP Config Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< VREFP Interrupt Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t TR; /*!< VREFP Trim Register, Address offset: 0x0C */
|
||||
}VREFP_Type;
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ VREF ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< VREF Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR; /*!< VREF Config Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< VREF Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< VREF Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t BUFCR; /*!< Buffer Control Register, Address offset: 0x10 */
|
||||
}VREF_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ VAO ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t RSV1[512]; /*!< RESERVED REGISTER, Address offset: 0x00 */
|
||||
__IO uint32_t RSTCR; /*!< VBAT Reset Control Register, Address offset: 0x800 */
|
||||
__IO uint32_t XTLFCR; /*!< XTLF Control Register, Address offset: 0x804 */
|
||||
__IO uint32_t XTLFPR; /*!< XTLF Power Register, Address offset: 0x808 */
|
||||
__IO uint32_t FDIER; /*!< XTLF Oscillation Fail Detection Interrupt Enable Register,Address offset: 0x80C */
|
||||
__IO uint32_t FDISR; /*!< XTLF Oscillation Fail Detection Interrupt Status Register,Address offset: 0x810 */
|
||||
__IO uint32_t RSV2[251]; /*!< RESERVED REGISTER, Address offset: 0x814 */
|
||||
__IO uint32_t INEN; /*!< VAO IO Input Enable Register, Address offset: 0xC00 */
|
||||
__IO uint32_t PUEN; /*!< VAO IO Pull-up Enable Register, Address offset: 0xC04 */
|
||||
__IO uint32_t ODEN; /*!< VAO IO Open Drain Enable Register, Address offset: 0xC08 */
|
||||
__IO uint32_t FCR; /*!< VAO IO Function Control Register, Address offset: 0xC0C */
|
||||
__IO uint32_t DOR; /*!< VAO IO Data Output Register, Address offset: 0xC10 */
|
||||
__I uint32_t DIR; /*!< VAO IO Data Input Register, Address offset: 0xC14 */
|
||||
__IO uint32_t VILR; /*!< VAO IO Voltage Input Low Register, Address offset: 0xC18 */
|
||||
}VAO_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CDIF ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< , Address offset: 0x00 */
|
||||
__IO uint32_t PRSC; /*!< , Address offset: 0x04 */
|
||||
}CDIF_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ RMU ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PDRCR; /*!< PDR Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t BORCR; /*!< BOR Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t LKPCR; /*!< Reset Config Register, Address offset: 0x08 */
|
||||
__O uint32_t SOFTRST; /*!< Software Reset Register, Address offset: 0x0C */
|
||||
__IO uint32_t RSTFR; /*!< Reset Flag Register, Address offset: 0x10 */
|
||||
__O uint32_t PRSTEN; /*!< Peripheral Reset Enable Register, Address offset: 0x14 */
|
||||
__IO uint32_t AHBRSTCR; /*!< AHB Peripherals Reset Register, Address offset: 0x18 */
|
||||
__IO uint32_t APBRSTCR1; /*!< APB Peripherals Reset Register1, Address offset: 0x1C */
|
||||
__IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Register2, Address offset: 0x20 */
|
||||
}RMU_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ IWDT ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t SERV; /*!< IWDT Service Register, Address offset: 0x00 */
|
||||
__IO uint32_t CR; /*!< IWDT Config Register, Address offset: 0x04 */
|
||||
__I uint32_t CNT; /*!< IWDT Counter Register, Address offset: 0x08 */
|
||||
__IO uint32_t WIN; /*!< IWDT Window Register, Address offset: 0x0C */
|
||||
__IO uint32_t IER; /*!< IWDT Interrupt Enable Register, Address offset: 0x10 */
|
||||
__IO uint32_t ISR; /*!< IWDT Interrupt Status Register, Address offset: 0x14 */
|
||||
}IWDT_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ WWDT ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t CR; /*!< WWDT Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR; /*!< WWDT Config Register, Address offset: 0x04 */
|
||||
__I uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */
|
||||
__I uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */
|
||||
}WWDT_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CMU ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SYSCLKCR; /*!< System Clock Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t RCHFCR; /*!< RCHF Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t RCHFTR; /*!< RCHF Trim Register, Address offset: 0x08 */
|
||||
__IO uint32_t PLLCR; /*!< PLL Control Register, Address offset: 0x0C */
|
||||
__IO uint32_t RCLPCR; /*!< RCLP Control Register, Address offset: 0x10 */
|
||||
__IO uint32_t RCLPTR; /*!< RCLP Trim Register, Address offset: 0x14 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x18 */
|
||||
__IO uint32_t LSCLKSEL; /*!< LSCLK Select Register, Address offset: 0x1C */
|
||||
__IO uint32_t XTHFCR; /*!< XTHF Control Register, Address offset: 0x20 */
|
||||
__IO uint32_t RCLFCR; /*!< RCLF Control Register, Address offset: 0x24 */
|
||||
__IO uint32_t RCLFTR; /*!< RCLF Trim Register, Address offset: 0x28 */
|
||||
__IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x2C */
|
||||
__IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x30 */
|
||||
__IO uint32_t PCLKCR1; /*!< Peripheral bus Clock Control Register1, Address offset: 0x34 */
|
||||
__IO uint32_t PCLKCR2; /*!< Peripheral bus Clock Control Register2, Address offset: 0x38 */
|
||||
__IO uint32_t PCLKCR3; /*!< Peripheral bus Clock Control Register3, Address offset: 0x3C */
|
||||
__IO uint32_t PCLKCR4; /*!< Peripheral bus Clock Control Register4, Address offset: 0x40 */
|
||||
__IO uint32_t OPCCR1; /*!< Peripheral Clock Config Register1, Address offset: 0x44 */
|
||||
__IO uint32_t OPCCR2; /*!< Peripheral Clock Config Register 2, Address offset: 0x48 */
|
||||
__IO uint32_t OPCCR3; /*!< Peripheral Clock Config Register 3, Address offset: 0x4C */
|
||||
__IO uint32_t AHBMCR; /*!< AHB Master Control Register, Address offset: 0x50 */
|
||||
__IO uint32_t CCCR; /*!< Clock Calibration Control Register, Address offset: 0x54 */
|
||||
__IO uint32_t CCFR; /*!< Clock Calibration Config Register, Address offset: 0x58 */
|
||||
__I uint32_t CCNR; /*!< Clock Calibration Counter Register, Address offset: 0x5C */
|
||||
__IO uint32_t CCISR; /*!< Clock Calibration Interrupt Status Register, Address offset: 0x60 */
|
||||
}CMU_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ SVD ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR; /*!< SVD Config Register, Address offset: 0x00 */
|
||||
__IO uint32_t CR; /*!< SVD Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t IER; /*!< SVD Interrupt Enable Register, Address offset: 0x08 */
|
||||
__IO uint32_t ISR; /*!< SVD Interrupt Status Register, Address offset: 0x0C */
|
||||
__IO uint32_t VSR; /*!< SVD reference Voltage Select Register, Address offset: 0x10 */
|
||||
}SVD_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ AES ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< AES Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t DIR; /*!< AES Data Input Register, Address offset: 0x0C */
|
||||
__I uint32_t DOR; /*!< AES Data Output Register, Address offset: 0x10 */
|
||||
__IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */
|
||||
__IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */
|
||||
__IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */
|
||||
__IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */
|
||||
__IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */
|
||||
__IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */
|
||||
__IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */
|
||||
__IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */
|
||||
__IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */
|
||||
__IO uint32_t IVR1; /*!< AES Initial Vector Register 1, Address offset: 0x38 */
|
||||
__IO uint32_t IVR2; /*!< AES Initial Vector Register 2, Address offset: 0x3C */
|
||||
__IO uint32_t IVR3; /*!< AES Initial Vector Register 3, Address offset: 0x40 */
|
||||
__IO uint32_t H0; /*!< AES MultH parameter Register 0, Address offset: 0x44 */
|
||||
__IO uint32_t H1; /*!< AES MultH parameter Register 1, Address offset: 0x48 */
|
||||
__IO uint32_t H2; /*!< AES MultH parameter Register 2, Address offset: 0x4C */
|
||||
__IO uint32_t H3; /*!< AES MultH parameter Register 3, Address offset: 0x50 */
|
||||
}AES_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ RNG ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< Random Number Generator Control Register, Address offset: 0x00 */
|
||||
__I uint32_t DOR; /*!< Random Number Generator Data Output Register, Address offset: 0x04 */
|
||||
__IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x08 */
|
||||
__IO uint32_t SR; /*!< Random Number Generator Status Register, Address offset: 0x10 */
|
||||
__IO uint32_t CRCCR; /*!< CRC Control Register, Address offset: 0x14 */
|
||||
__IO uint32_t CRCDIR; /*!< CRC Data input Register, Address offset: 0x18 */
|
||||
__IO uint32_t CRCSR; /*!< CRC Status Register, Address offset: 0x1C */
|
||||
}RNG_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ COMP ================ */
|
||||
/* ================================================================================ */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< ComparatorControl Register 1, Address offset: 0x00 */
|
||||
|
||||
} COMP_Type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICR; /*!< Comparator Interrupt Config Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< Comparator Interrupt Status Register, Address offset: 0x10 */
|
||||
__IO uint32_t BUFCR; /*!< Comparator Buffer Control Register, Address offset: 0x14 */
|
||||
}COMP_COMMON_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CALC ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t OPRD; /*!< Operand Register, Address offset: 0x00 */
|
||||
__IO uint32_t DIVSOR; /*!< Divisor Regsiter, Address offset: 0x04 */
|
||||
__I uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */
|
||||
__I uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */
|
||||
__I uint32_t ROOT; /*!< Root Register, Address offset: 0x10 */
|
||||
__I uint32_t SR; /*!< Status Register, Address offset: 0x14 */
|
||||
__IO uint32_t CR; /*!< Control Register, Address offset: 0x18 */
|
||||
}DIVAS_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ I2C ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MSPCFGR; /*!< I2C Master Config Register, Address offset: 0x00 */
|
||||
__IO uint32_t MSPCR; /*!< I2C Master Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t MSPIER; /*!< I2C Master Intterupt Enable Register, Address offset: 0x08 */
|
||||
__IO uint32_t MSPISR; /*!< I2C Master Interrupt Status Register, Address offset: 0x0C */
|
||||
__IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */
|
||||
__IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */
|
||||
__IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */
|
||||
__IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */
|
||||
__IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */
|
||||
__IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */
|
||||
__IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */
|
||||
__IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */
|
||||
__I uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */
|
||||
__IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */
|
||||
__IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */
|
||||
}I2C_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ UART_COMMON ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IRCR; /*!< Infrared modulation Control Register, Address offset: 0x00 */
|
||||
}UART_COMMON_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ UARTx ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CSR; /*!< UARTx Control Status Register, Address offset: 0x00 */
|
||||
__IO uint32_t IER; /*!< UARTx Interrupt Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< UARTx Interrupt Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t TODR; /*!< UARTx Time-Out and Delay Register, Address offset: 0x0C */
|
||||
__I uint32_t RXBUF; /*!< UARTx Receive Buffer, Address offset: 0x10 */
|
||||
__O uint32_t TXBUF; /*!< UARTx Transmit Buffer, Address offset: 0x14 */
|
||||
__IO uint32_t BGR; /*!< UARTx Baud rate Generator Register, Address offset: 0x18 */
|
||||
}UART_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ LPUARTx ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CSR; /*!< LPUARTx Control Status Register, Address offset: 0x00 */
|
||||
__IO uint32_t IER; /*!< LPUARTx Interrupt Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< LPUARTx Interrupt Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t BMR; /*!< LPUARTx Baud rate Modulation Register, Address offset: 0x0C */
|
||||
__I uint32_t RXBUF; /*!< LPUARTx Receive Buffer Register, Address offset: 0x10 */
|
||||
__IO uint32_t TXBUF; /*!< LPUARTx Transmit Buffer Register, Address offset: 0x14 */
|
||||
__IO uint32_t DMR; /*!< LPUARTx data Matching Register, Address offset: 0x18 */
|
||||
}LPUART_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ SPIx ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPIxControl Register1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPIxControl Register2, Address offset: 0x04 */
|
||||
__IO uint32_t CR3; /*!< Control Register3, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< SPIxInterrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< SPIxStatus Register, Address offset: 0x10 */
|
||||
__O uint32_t TXBUF; /*!< SPIxTransmit Buffer, Address offset: 0x14 */
|
||||
__I uint32_t RXBUF; /*!< SPIxReceive Buffer, Address offset: 0x18 */
|
||||
}SPI_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CAN ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< CAN Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t MSR; /*!< CAN mode select register, Address offset: 0x04 */
|
||||
__IO uint32_t BRPR; /*!< CAN Baud rate Prescaler Register, Address offset: 0x08 */
|
||||
__IO uint32_t BTR; /*!< CAN Bit Timing Register, Address offset: 0x0C */
|
||||
__I uint32_t ECR; /*!< CAN Error Counter Register, Address offset: 0x10 */
|
||||
__IO uint32_t ESR; /*!< CAN Error Status Register, Address offset: 0x14 */
|
||||
__I uint32_t SR; /*!< CAN Status Register, Address offset: 0x18 */
|
||||
__I uint32_t ISR; /*!< CAN Interrupt Status Register, Address offset: 0x1C */
|
||||
__IO uint32_t IER; /*!< CAN Interrupt Enable Register, Address offset: 0x20 */
|
||||
__IO uint32_t ICR; /*!< CAN Interrupt Clear Register, Address offset: 0x24 */
|
||||
__IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x28 */
|
||||
__O uint32_t TXFIDR; /*!< CAN TX FIFO ID Register, Address offset: 0x30 */
|
||||
__O uint32_t TXFDLCR; /*!< CAN TX FIFO DLC Register, Address offset: 0x34 */
|
||||
__O uint32_t TXFDW1R; /*!< CAN TX FIFO Data Word1 Register, Address offset: 0x38 */
|
||||
__O uint32_t TXFDW2R; /*!< CAN TX FIFO Data Word2 Register, Address offset: 0x3C */
|
||||
__O uint32_t HPBIDR; /*!< CAN TX HPB ID Register, Address offset: 0x40 */
|
||||
__O uint32_t HPBDLCR; /*!< CAN TX HPB DLC Register, Address offset: 0x44 */
|
||||
__O uint32_t HPBDW1R; /*!< CAN TX HPB Data Word1 Register, Address offset: 0x48 */
|
||||
__O uint32_t HPBDW2R; /*!< CAN TX HPB Data Word2 Register, Address offset: 0x4C */
|
||||
__O uint32_t RXFIDR; /*!< CAN RX FIFO ID Register, Address offset: 0x50 */
|
||||
__O uint32_t RXFDLCR; /*!< CAN RX FIFO DLC Register, Address offset: 0x54 */
|
||||
__O uint32_t RXFDW1R; /*!< CAN RX FIFO Data Word1 Register, Address offset: 0x58 */
|
||||
__O uint32_t RXFDW2R; /*!< CAN RX FIFO Data Word2 Register, Address offset: 0x5C */
|
||||
__IO uint32_t AFR; /*!< Acceptance Filter Register, Address offset: 0x60 */
|
||||
__IO uint32_t AFMR0; /*!< Acceptance Filter Mask Register0, Address offset: 0x64 */
|
||||
__IO uint32_t AFIR0; /*!< Acceptance Filter ID Register0, Address offset: 0x68 */
|
||||
__IO uint32_t AFMR1; /*!< Acceptance Filter Mask Register1, Address offset: 0x6C */
|
||||
__IO uint32_t AFIR1; /*!< Acceptance Filter ID Register1, Address offset: 0x70 */
|
||||
__IO uint32_t AFMR2; /*!< Acceptance Filter Mask Register2, Address offset: 0x74 */
|
||||
__IO uint32_t AFIR2; /*!< Acceptance Filter ID Register2, Address offset: 0x78 */
|
||||
__IO uint32_t AFMR3; /*!< Acceptance Filter Mask Register3, Address offset: 0x7C */
|
||||
__IO uint32_t AFIR3; /*!< Acceptance Filter ID Register3, Address offset: 0x80 */
|
||||
}CAN_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ DMA ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t GCR; /*!< DMA Global Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t CH0CR; /*!< Channel 0 Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t CH0MAD; /*!< Channel 0 Memory Address Register, Address offset: 0x08 */
|
||||
__IO uint32_t CH1CR; /*!< Channel 1 Control Register, Address offset: 0x0C */
|
||||
__IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register, Address offset: 0x10 */
|
||||
__IO uint32_t CH2CR; /*!< Channel 2 Control Register, Address offset: 0x14 */
|
||||
__IO uint32_t CH2MAD; /*!< Channel 2 Memory Address Register, Address offset: 0x18 */
|
||||
__IO uint32_t CH3CR; /*!< Channel 3 Control Register, Address offset: 0x1C */
|
||||
__IO uint32_t CH3MAD; /*!< Channel 3 Memory Address Register, Address offset: 0x20 */
|
||||
__IO uint32_t CH4CR; /*!< Channel 4 Control Register, Address offset: 0x24 */
|
||||
__IO uint32_t CH4MAD; /*!< Channel 4 Memory Address Register, Address offset: 0x28 */
|
||||
__IO uint32_t CH5CR; /*!< Channel 5 Control Register, Address offset: 0x2C */
|
||||
__IO uint32_t CH5MAD; /*!< Channel 5 Memory Address Register, Address offset: 0x30 */
|
||||
__IO uint32_t CH6CR; /*!< Channel 6 Control Register, Address offset: 0x34 */
|
||||
__IO uint32_t CH6MAD; /*!< Channel 6 Memory Address Register, Address offset: 0x38 */
|
||||
__IO uint32_t CH7CR; /*!< Channel 11 Control Register, Address offset: 0x3C */
|
||||
__IO uint32_t CH7FLSAD; /*!< Channel 11 Flash Address Register, Address offset: 0x40 */
|
||||
__IO uint32_t CH7RAMAD; /*!< Channel 11 RAM Address Register, Address offset: 0x44 */
|
||||
__IO uint32_t ISR; /*!< DMA Interrupt Status Register, Address offset: 0x48 */
|
||||
}DMA_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CRC ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DR; /*!< CRC Data Register, Address offset: 0x00 */
|
||||
__IO uint32_t CR; /*!< Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t LFSR; /*!< CRC Linear Feedback Shift Register, Address offset: 0x08 */
|
||||
__IO uint32_t XOR; /*!< CRC output XOR Register, Address offset: 0x0C */
|
||||
__IO uint32_t RSV1[3]; /*!< RESERVED REGISTER, Address offset: 0x10 */
|
||||
__IO uint32_t POLY; /*!< CRC Polynominal Register, Address offset: 0x1C */
|
||||
}CRC_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ ATIM ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< ATIM Control Register1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< ATIM Control Register2, Address offset: 0x04 */
|
||||
__IO uint32_t SMCR; /*!< ATIM Slave Mode Control Register, Address offset: 0x08 */
|
||||
__IO uint32_t DIER; /*!< ATIM DMA and Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< ATIM Interrupt Status Register, Address offset: 0x10 */
|
||||
__O uint32_t EGR; /*!< ATIM Event Generation Register, Address offset: 0x14 */
|
||||
__IO uint32_t CCMR1; /*!< ATIM Capture/Compare Mode Register1, Address offset: 0x18 */
|
||||
__IO uint32_t CCMR2; /*!< ATIM Capture/Compare Mode Register2, Address offset: 0x1C */
|
||||
__IO uint32_t CCER; /*!< ATIM Capture/Compare Enable Register, Address offset: 0x20 */
|
||||
__IO uint32_t CNT; /*!< ATIM Counter Register, Address offset: 0x24 */
|
||||
__IO uint32_t PSC; /*!< ATIM Prescaler Register, Address offset: 0x28 */
|
||||
__IO uint32_t ARR; /*!< ATIM Auto-Reload Register, Address offset: 0x2C */
|
||||
__IO uint32_t RCR; /*!< ATIM Repetition Counter Register, Address offset: 0x30 */
|
||||
__IO uint32_t CCR1; /*!< ATIM Capture/Compare Register1, Address offset: 0x34 */
|
||||
__IO uint32_t CCR2; /*!< ATIM Capture/Compare Register2, Address offset: 0x38 */
|
||||
__IO uint32_t CCR3; /*!< ATIM Capture/Compare Register3, Address offset: 0x3C */
|
||||
__IO uint32_t CCR4; /*!< ATIM Capture/Compare Register4, Address offset: 0x40 */
|
||||
__IO uint32_t BDTR; /*!< ATIM Break and Deadtime Register, Address offset: 0x44 */
|
||||
__IO uint32_t DCR; /*!< ATIM DMA Control Register, Address offset: 0x48 */
|
||||
__IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address offset: 0x4C */
|
||||
__IO uint32_t RSV1[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */
|
||||
__IO uint32_t BKCR; /*!< ATIM Break Control Register, Address offset: 0x60 */
|
||||
}ATIM_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ GPTIMx ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< GPTIMx Control Register1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< GPTIMx Control Register2, Address offset: 0x04 */
|
||||
__IO uint32_t SMCR; /*!< GPTIMx Slave Mode Control Register, Address offset: 0x08 */
|
||||
__IO uint32_t DIER; /*!< GPTIMx DMA and Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x10 */
|
||||
__O uint32_t EGR; /*!< GPTIMx Event Generation Register, Address offset: 0x14 */
|
||||
__IO uint32_t CCMR1; /*!< GPTIMx Capture/Compare Mode Register1, Address offset: 0x18 */
|
||||
__IO uint32_t CCMR2; /*!< GPTIMx Capture/Compare Mode Register2, Address offset: 0x1C */
|
||||
__IO uint32_t CCER; /*!< GPTIMx Capture/Compare Enable Register, Address offset: 0x20 */
|
||||
__IO uint32_t CNT; /*!< GPTIMx Counter Register, Address offset: 0x24 */
|
||||
__IO uint32_t PSC; /*!< GPTIMx Prescaler Register, Address offset: 0x28 */
|
||||
__IO uint32_t ARR; /*!< GPTIMx Auto-Reload Register, Address offset: 0x2C */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x30 */
|
||||
__IO uint32_t CCR1; /*!< GPTIMx Capture/Compare Register1, Address offset: 0x34 */
|
||||
__IO uint32_t CCR2; /*!< GPTIMx Capture/Compare Register2, Address offset: 0x38 */
|
||||
__IO uint32_t CCR3; /*!< GPTIMx Capture/Compare Register3, Address offset: 0x3C */
|
||||
__IO uint32_t CCR4; /*!< GPTIMx Capture/Compare Register4, Address offset: 0x40 */
|
||||
__IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x44 */
|
||||
__IO uint32_t DCR; /*!< GPTIMx DMA Control Register, Address offset: 0x48 */
|
||||
__IO uint32_t DMAR; /*!< GPTIMx DMA access Register, Address offset: 0x4C */
|
||||
__IO uint32_t RSV3[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */
|
||||
__IO uint32_t ITRSEL; /*!< GPTIMx Internal Trigger Select Register, Address offset: 0x60 */
|
||||
}GPTIM_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ BSTIM32 ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */
|
||||
__O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */
|
||||
__IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */
|
||||
__IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */
|
||||
__IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */
|
||||
__IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */
|
||||
}BSTIM32_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ BSTIM16 ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */
|
||||
__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */
|
||||
__IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */
|
||||
__O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */
|
||||
__IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */
|
||||
__IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */
|
||||
__IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */
|
||||
__IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */
|
||||
}BSTIM16_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ LPTIM32 ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR; /*!< LPTIM32 Config Register, Address offset: 0x00 */
|
||||
__I uint32_t CNT; /*!< LPTIM32 Counter Register, Address offset: 0x04 */
|
||||
__IO uint32_t CCSR; /*!< LPTIM32 Capture/Compare Control and Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t ARR; /*!< LPTIM32 Auto-Reload Register, Address offset: 0x0C */
|
||||
__IO uint32_t IER; /*!< LPTIM32 Interrupt Enable Register, Address offset: 0x10 */
|
||||
__IO uint32_t ISR; /*!< LPTIM32 Interrupt Status Register, Address offset: 0x14 */
|
||||
__IO uint32_t CR; /*!< LPTIM32 Control Register, Address offset: 0x18 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */
|
||||
__IO uint32_t CCR1; /*!< LPTIM32 Capture/Compare Register1, Address offset: 0x20 */
|
||||
__IO uint32_t CCR2; /*!< LPTIM32 Capture/Compare Register2, Address offset: 0x24 */
|
||||
__IO uint32_t CCR3; /*!< LPTIM32 Capture/Compare Register3, Address offset: 0x28 */
|
||||
__IO uint32_t CCR4; /*!< LPTIM32 Capture/Compare Register4, Address offset: 0x2C */
|
||||
}LPTIM32_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ LPTIM16 ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR; /*!< LPTIM Config Register, Address offset: 0x00 */
|
||||
__I uint32_t CNT; /*!< LPTIM Counter Register, Address offset: 0x04 */
|
||||
__IO uint32_t CCSR; /*!< LPTIM Capture/Compare Control and Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */
|
||||
__IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */
|
||||
__IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */
|
||||
__IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */
|
||||
__IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */
|
||||
__IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */
|
||||
}LPTIM16_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ RTCA ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t WER; /*!< RTC Write Enable Register, Address offset: 0x00 */
|
||||
__IO uint32_t IER; /*!< RTC Interrupt Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< RTC Interrupt Status Register, Address offset: 0x08 */
|
||||
__IO uint32_t BCDSEC; /*!< BCD format time second registers, Address offset: 0x0C */
|
||||
__IO uint32_t BCDMIN; /*!< BCD format time minute registers, Address offset: 0x10 */
|
||||
__IO uint32_t BCDHOUR; /*!< BCD format time hour registers, Address offset: 0x14 */
|
||||
__IO uint32_t BCDDAY; /*!< BCD format time day registers, Address offset: 0x18 */
|
||||
__IO uint32_t BCDWEEK; /*!< BCD format time week registers, Address offset: 0x1C */
|
||||
__IO uint32_t BCDMONTH; /*!< BCD format time month registers, Address offset: 0x20 */
|
||||
__IO uint32_t BCDYEAR; /*!< BCD format time year registers, Address offset: 0x24 */
|
||||
__IO uint32_t ALARM; /*!< RTCA Alarm Register, Address offset: 0x28 */
|
||||
__IO uint32_t TMSEL; /*!< RTCA Time Mark Select, Address offset: 0x2C */
|
||||
__IO uint32_t ADJUST; /*!< RTCA time Adjust Register, Address offset: 0x30 */
|
||||
__IO uint32_t ADSIGN; /*!< RTCA time Adjust Sign Register, Address offset: 0x34 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */
|
||||
__IO uint32_t SBSCNT; /*!< RTCA Sub-Second Counter, Address offset: 0x3C */
|
||||
__IO uint32_t CR; /*!< RTCA Control Register, Address offset: 0x40 */
|
||||
}RTCA_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ LCD ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */
|
||||
__IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */
|
||||
__IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x10 */
|
||||
__IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */
|
||||
__IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */
|
||||
__IO uint32_t RSV2[2]; /*!< RESERVED REGISTER, Address offset: 0x1C */
|
||||
__IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */
|
||||
__IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */
|
||||
__IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */
|
||||
__IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */
|
||||
__IO uint32_t DATA4; /*!< LCD data buffer registers 4, Address offset: 0x34 */
|
||||
__IO uint32_t DATA5; /*!< LCD data buffer registers 5, Address offset: 0x38 */
|
||||
__IO uint32_t DATA6; /*!< LCD data buffer registers 6, Address offset: 0x3C */
|
||||
__IO uint32_t DATA7; /*!< LCD data buffer registers 7, Address offset: 0x40 */
|
||||
__IO uint32_t DATA8; /*!< LCD data buffer registers 8, Address offset: 0x44 */
|
||||
__IO uint32_t DATA9; /*!< LCD data buffer registers 9, Address offset: 0x48 */
|
||||
__IO uint32_t RSV3; /*!< RESERVED REGISTER, Address offset: 0x4C */
|
||||
__IO uint32_t COMEN; /*!< LCD COM Enable Register, Address offset: 0x50 */
|
||||
__IO uint32_t SEGEN0; /*!< LCD SEG Enable Register0, Address offset: 0x54 */
|
||||
__IO uint32_t SEGEN1; /*!< LCD SEG Enable Register 1, Address offset: 0x58 */
|
||||
}LCD_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ ADC ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
|
||||
__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t CR1; /*!< ADC Control Register, Address offset: 0x08 */
|
||||
__IO uint32_t CR2; /*!< ADC Control Register, Address offset: 0x0C */
|
||||
__IO uint32_t CALR; /*!< ADC Calibration Register, Address offset: 0x10 */
|
||||
__IO uint32_t CFGR1; /*!< ADC Config Register1, Address offset: 0x14 */
|
||||
__IO uint32_t CFGR2; /*!< ADC Config Register2, Address offset: 0x18 */
|
||||
__IO uint32_t SMTR; /*!< ADC Sampling Time Register, Address offset: 0x1C */
|
||||
__IO uint32_t CHER; /*!< ADC Channel Enable Register, Address offset: 0x20 */
|
||||
__IO uint32_t DCR; /*!< ADC Differential Channel Control Register, Address offset: 0x24 */
|
||||
__I uint32_t DR; /*!< ADC Data Register, Address offset: 0x28 */
|
||||
__IO uint32_t HLTR; /*!< ADC analog watchdog Threshold Register, Address offset: 0x2C */
|
||||
}ADC_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ DAC ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< DAC Control Register, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< DAC Control Register, Address offset: 0x04 */
|
||||
__IO uint32_t CFGR; /*!< DAC Config Register, Address offset: 0x08 */
|
||||
__O uint32_t SWTRGR; /*!< DAC Software Trigger Register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR; /*!< DAC Data Holding Register, Address offset: 0x10 */
|
||||
__IO uint32_t ISR; /*!< DAC Interrupt Status Register, Address offset: 0x14 */
|
||||
__IO uint32_t IER; /*!< DAC Interrupt Enable Register, Address offset: 0x18 */
|
||||
__IO uint32_t SHTR; /*!< DAC Sample Hold Time Register, Address offset: 0x1C */
|
||||
}DAC_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ GPIO ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t INEN; /*!< GPIOx Input Enable Register, Address offset: 0x00 */
|
||||
__IO uint32_t PUEN; /*!< GPIOx Pull-Up Enable Register, Address offset: 0x04 */
|
||||
__IO uint32_t ODEN; /*!< GPIOx Open-Drain Enable Register, Address offset: 0x08 */
|
||||
__IO uint32_t FCR; /*!< GPIOx Function Control Register, Address offset: 0x0C */
|
||||
__IO uint32_t DO; /*!< GPIOx Data Output Register, Address offset: 0x10 */
|
||||
__O uint32_t DSET; /*!< GPIOx Data Set Register, Address offset: 0x14 */
|
||||
__O uint32_t DRST; /*!< GPIOx Data Reset Register, Address offset: 0x18 */
|
||||
__I uint32_t DIN; /*!< GPIOx Data Input Register, Address offset: 0x1C */
|
||||
__IO uint32_t DFS; /*!< GPIOx Digital Function Select, Address offset: 0x20 */
|
||||
__IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x24 */
|
||||
__IO uint32_t ANEN; /*!< GPIOx Analog channel Enable Register, Address offset: 0x28 */
|
||||
__IO uint32_t VILR; /*!< GPIOx Voltage Input Low Register, Address offset: 0x2C */
|
||||
}GPIO_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ GPIO_COMMON ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t EXTISEL0; /*!< External Interrupt Input Select Register0, Address offset: 0x00 */
|
||||
__IO uint32_t EXTISEL1; /*!< External Interrupt Input Select Register1, Address offset: 0x04 */
|
||||
__IO uint32_t EXTIEDS0; /*!< External Interrupt Edge Select and Enable Register0, Address offset: 0x08 */
|
||||
__IO uint32_t EXTIEDS1; /*!< External Interrupt Edge Select and Enable Register1, Address offset: 0x0C */
|
||||
__IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register, Address offset: 0x10 */
|
||||
__IO uint32_t EXTIISR; /*!< External Interrupt and Status Register, Address offset: 0x14 */
|
||||
__I uint32_t EXTIDI; /*!< External Interrupt Data Input Register, Address offset: 0x18 */
|
||||
__IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x1C */
|
||||
__IO uint32_t FOUTSEL; /*!< Frequency Output Select Register, Address offset: 0x100 */
|
||||
__IO uint32_t RSV2[63]; /*!< RESERVED REGISTER, Address offset: 0x104 */
|
||||
__IO uint32_t PINWKEN; /*!< Wakeup Enable Register, Address offset: 0x200 */
|
||||
}GPIO_COMMON_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ DBG ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t SYSCFG; /*!< , Address offset: 0x00 */
|
||||
__IO uint32_t CR; /*!< , Address offset: 0x04 */
|
||||
__IO uint32_t HDFR; /*!< , Address offset: 0x08 */
|
||||
}DBG_Type;
|
||||
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ CPU memory map ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
|
||||
/* Peripheral and SRAM base address */
|
||||
|
||||
#define FLASH_BASE (( uint32_t)0x00000000)
|
||||
#define SRAM_BASE (( uint32_t)0x20000000)
|
||||
#define PERIPH_BASE (( uint32_t)0x40000000)
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral memory map ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* Peripheral memory map */
|
||||
|
||||
#define FLASH_R_BASE (PERIPH_BASE +0x00001000)
|
||||
#define PMU_BASE (PERIPH_BASE +0x00002000)
|
||||
#define VREFP_BASE (PERIPH_BASE +0x0000203C)
|
||||
#define VREF_BASE (PERIPH_BASE +0x0001A400)
|
||||
#define VAO_BASE (PERIPH_BASE +0x0001F000)
|
||||
#define CDIF_BASE (PERIPH_BASE +0x0001E000)
|
||||
#define RMU_BASE (PERIPH_BASE +0x00002800)
|
||||
#define IWDT_BASE (PERIPH_BASE +0x00011400)
|
||||
#define WWDT_BASE (PERIPH_BASE +0x00011800)
|
||||
#define CMU_BASE (PERIPH_BASE +0x00002400)
|
||||
#define SVD_BASE (PERIPH_BASE +0x00012800)
|
||||
#define AES_BASE (PERIPH_BASE +0x00013800)
|
||||
#define RNG_BASE (PERIPH_BASE +0x00013C00)
|
||||
#define COMP1_BASE (PERIPH_BASE +0x00015400)
|
||||
#define COMP2_BASE (PERIPH_BASE +0x00015404)
|
||||
#define COMP3_BASE (PERIPH_BASE +0x00015408)
|
||||
#define COMP_COMMON_BASE (PERIPH_BASE +0x0001540C)
|
||||
#define DIVAS_BASE (PERIPH_BASE +0x00019C00)
|
||||
#define I2C_BASE (PERIPH_BASE +0x00012400)
|
||||
#define UART_COMMON_BASE (PERIPH_BASE +0x00017C00)
|
||||
#define UART0_BASE (PERIPH_BASE +0x00012000)
|
||||
#define UART1_BASE (PERIPH_BASE +0x00016800)
|
||||
#define UART3_BASE (PERIPH_BASE +0x00017000)
|
||||
#define UART4_BASE (PERIPH_BASE +0x00017400)
|
||||
#define UART5_BASE (PERIPH_BASE +0x00017800)
|
||||
#define LPUART0_BASE (PERIPH_BASE +0x00014000)
|
||||
#define LPUART1_BASE (PERIPH_BASE +0x00014400)
|
||||
#define LPUART2_BASE (PERIPH_BASE +0x00015000)
|
||||
#define SPI0_BASE (PERIPH_BASE +0x00010400)
|
||||
#define SPI1_BASE (PERIPH_BASE +0x00010800)
|
||||
#define SPI2_BASE (PERIPH_BASE +0x00014800)
|
||||
#define CAN_BASE (PERIPH_BASE +0x00019400)
|
||||
#define DMA_BASE (PERIPH_BASE +0x00000400)
|
||||
#define CRC_BASE (PERIPH_BASE +0x00010000)
|
||||
#define ATIM_BASE (PERIPH_BASE +0x00013000)
|
||||
#define GPTIM0_BASE (PERIPH_BASE +0x00014C00)
|
||||
#define GPTIM1_BASE (PERIPH_BASE +0x00016400)
|
||||
#define GPTIM2_BASE (PERIPH_BASE +0x00018000)
|
||||
#define BSTIM32_BASE (PERIPH_BASE +0x00016000)
|
||||
#define BSTIM16_BASE (PERIPH_BASE +0x00018C00)
|
||||
#define LPTIM32_BASE (PERIPH_BASE +0x00013400)
|
||||
#define LPTIM16_BASE (PERIPH_BASE +0x00018800)
|
||||
#define RTCA_BASE (PERIPH_BASE +0x00011000)
|
||||
#define LCD_BASE (PERIPH_BASE +0x00010C00)
|
||||
#define ADC_BASE (PERIPH_BASE +0x00015C00)
|
||||
#define DAC_BASE (PERIPH_BASE +0x00019800)
|
||||
#define GPIOA_BASE (PERIPH_BASE +0x00000C00)
|
||||
#define GPIOB_BASE (PERIPH_BASE +0x00000C40)
|
||||
#define GPIOC_BASE (PERIPH_BASE +0x00000C80)
|
||||
#define GPIOD_BASE (PERIPH_BASE +0x00000CC0)
|
||||
#define GPIOE_BASE (PERIPH_BASE +0x00000D00)
|
||||
#define GPIO_COMMON_BASE (PERIPH_BASE +0x00000DC0)
|
||||
#define DBG_BASE (PERIPH_BASE +0x00000000)
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#define FLASH ((FLASH_Type *) FLASH_R_BASE )
|
||||
#define PMU ((PMU_Type *) PMU_BASE )
|
||||
#define VREFP ((VREFP_Type *) VREFP_BASE )
|
||||
#define VREF ((VREF_Type *) VREF_BASE )
|
||||
#define VAO ((VAO_Type *) VAO_BASE )
|
||||
#define CDIF ((CDIF_Type *) CDIF_BASE )
|
||||
#define RMU ((RMU_Type *) RMU_BASE )
|
||||
#define IWDT ((IWDT_Type *) IWDT_BASE )
|
||||
#define WWDT ((WWDT_Type *) WWDT_BASE )
|
||||
#define CMU ((CMU_Type *) CMU_BASE )
|
||||
#define SVD ((SVD_Type *) SVD_BASE )
|
||||
#define AES ((AES_Type *) AES_BASE )
|
||||
#define RNG ((RNG_Type *) RNG_BASE )
|
||||
#define COMP1 ((COMP_Type *) COMP1_BASE )
|
||||
#define COMP2 ((COMP_Type *) COMP2_BASE )
|
||||
#define COMP3 ((COMP_Type *) COMP3_BASE )
|
||||
#define COMP ((COMP_COMMON_Type *)COMP_COMMON_BASE )
|
||||
#define DIVAS ((DIVAS_Type *) DIVAS_BASE )
|
||||
#define I2C ((I2C_Type *) I2C_BASE )
|
||||
#define UART ((UART_COMMON_Type *) UART_COMMON_BASE )
|
||||
#define UART0 ((UART_Type *) UART0_BASE )
|
||||
#define UART1 ((UART_Type *) UART1_BASE )
|
||||
#define UART3 ((UART_Type *) UART3_BASE )
|
||||
#define UART4 ((UART_Type *) UART4_BASE )
|
||||
#define UART5 ((UART_Type *) UART5_BASE )
|
||||
#define LPUART0 ((LPUART_Type *) LPUART0_BASE )
|
||||
#define LPUART1 ((LPUART_Type *) LPUART1_BASE )
|
||||
#define LPUART2 ((LPUART_Type *) LPUART2_BASE )
|
||||
#define SPI0 ((SPI_Type *) SPI0_BASE )
|
||||
#define SPI1 ((SPI_Type *) SPI1_BASE )
|
||||
#define SPI2 ((SPI_Type *) SPI2_BASE )
|
||||
#define CAN ((CAN_Type *) CAN_BASE )
|
||||
#define DMA ((DMA_Type *) DMA_BASE )
|
||||
#define CRC ((CRC_Type *) CRC_BASE )
|
||||
#define ATIM ((ATIM_Type *) ATIM_BASE )
|
||||
#define GPTIM0 ((GPTIM_Type *) GPTIM0_BASE )
|
||||
#define GPTIM1 ((GPTIM_Type *) GPTIM1_BASE )
|
||||
#define GPTIM2 ((GPTIM_Type *) GPTIM2_BASE )
|
||||
#define BSTIM32 ((BSTIM32_Type *) BSTIM32_BASE )
|
||||
#define BSTIM16 ((BSTIM16_Type *) BSTIM16_BASE )
|
||||
#define LPTIM32 ((LPTIM32_Type *) LPTIM32_BASE )
|
||||
#define LPTIM16 ((LPTIM16_Type *) LPTIM16_BASE )
|
||||
#define RTCA ((RTCA_Type *) RTCA_BASE )
|
||||
#define LCD ((LCD_Type *) LCD_BASE )
|
||||
#define ADC ((ADC_Type *) ADC_BASE )
|
||||
#define DAC ((DAC_Type *) DAC_BASE )
|
||||
#define GPIOA ((GPIO_Type *) GPIOA_BASE )
|
||||
#define GPIOB ((GPIO_Type *) GPIOB_BASE )
|
||||
#define GPIOC ((GPIO_Type *) GPIOC_BASE )
|
||||
#define GPIOD ((GPIO_Type *) GPIOD_BASE )
|
||||
#define GPIOE ((GPIO_Type *) GPIOE_BASE )
|
||||
#define GPIO ((GPIO_COMMON_Type *) GPIO_COMMON_BASE )
|
||||
#define DBG ((DBG_Type *) DBG_BASE )
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral include ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_Registers */
|
||||
/** @} */ /* End of group FM33LG0XX */
|
||||
/** @} */ /* End of group Keil */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FM33LG0XX_H */
|
||||
|
||||
@ -0,0 +1,177 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_fm33lg0xx.h
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
|
||||
* Device FM33LG0XX
|
||||
* @version V2.0.0
|
||||
* @date 15. Mar 2021
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef SYSTEM_FM33LC0XX_H
|
||||
#define SYSTEM_FM33LC0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number
|
||||
*/
|
||||
#define __FM33LG0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __FM33LG0xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __FM33LG0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:0] sub2 version */
|
||||
#define __FM33LG0xx_CMSIS_VERSION ((__FM33LG0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__FM33LG0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__FM33LG0xx_CMSIS_VERSION_SUB2))
|
||||
|
||||
/* Configurations ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief LSCLK auto switch
|
||||
* @note Comment the following line to enable LSCLK auto switch function.
|
||||
*/
|
||||
#define USE_LSCLK_AUTO_SWITCH
|
||||
|
||||
|
||||
/**
|
||||
* @brief Keep debug connection under sleep mode
|
||||
* @note Uncomment the following line to debug under sleep mode
|
||||
*/
|
||||
/* #define USE_DEBUG_UNDER_SLEEP */
|
||||
|
||||
/**
|
||||
* @brief Open IWDT on program startup
|
||||
* @note Uncomment the following line to use IWDT on startup. User can modify
|
||||
* the IWDT_OVERFLOW_PERIOD to change the IDWT overflow period.
|
||||
*/
|
||||
/* #define USE_IWDT_ON_STARTUP */
|
||||
|
||||
#ifdef USE_IWDT_ON_STARTUP
|
||||
|
||||
/*
|
||||
Valid value of IWDT_OVERFLOW_PERIOD:
|
||||
- 0x0: 125ms
|
||||
- 0x1: 250ms
|
||||
- 0x2: 500ms
|
||||
- 0x3: 1s
|
||||
- 0x4: 2s
|
||||
- 0x5: 4s
|
||||
- 0x6: 8s
|
||||
- 0x7: 16s
|
||||
*/
|
||||
#define IWDT_OVERFLOW_PERIOD 0x7
|
||||
|
||||
#endif /* USE_IWDT_ON_STARTUP */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/* Device Includes -----------------------------------------------------------*/
|
||||
#include "fm33lg0xx.h"
|
||||
|
||||
/* Trim Values ---------------------------------------------------------------*/
|
||||
/* Validate Function */
|
||||
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
|
||||
((((_N_VALUE_ >> 16) & 0xFFFFU) == \
|
||||
(~(_N_VALUE_) & 0xFFFFU)) ? (_N_VALUE_) : (_T_VALUE_))
|
||||
|
||||
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40U) /* RC8M 常温校准值 */
|
||||
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3CU) /* RC16M 常温校准值 */
|
||||
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38U) /* RC24M 常温校准值 */
|
||||
#define RCHF32M_LDT_TRIM (*(uint32_t *)0x1FFFFB34U) /* RC32M 常温校准值 */
|
||||
#define RCLF_LDT_TRIM (*(uint32_t *)0x1FFFFB44U) /* RCLF 常温校准值 */
|
||||
#define RCLP_LDT_TRIM (*(uint32_t *)0x1FFFFB20U) /* RCLP 常温校准值 */
|
||||
|
||||
|
||||
#define RCHF8M_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBC2U) /* RC8M 常温校准值备份 */
|
||||
#define RCHF16M_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBC4U) /* RC16M 常温校准值备份 */
|
||||
#define RCHF24M_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBC6U) /* RC24M 常温校准值备份 */
|
||||
#define RCHF32M_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBC8U) /* RC32M 常温校准值备份 */
|
||||
#define RCLF_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBC0U) /* RCLF 常温校准值备份 */
|
||||
#define RCLP_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBCEU) /* RCLP 常温校准值备份 */
|
||||
|
||||
|
||||
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, RCHF8M_LDT_TRIM_BKP) & 0xffU)
|
||||
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, RCHF16M_LDT_TRIM_BKP) & 0xffU)
|
||||
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, RCHF24M_LDT_TRIM_BKP) & 0xffU)
|
||||
#define RCHF32M_TRIM (LDT_CHECK(RCHF32M_LDT_TRIM, RCHF32M_LDT_TRIM_BKP) & 0xffU)
|
||||
#define RCLF_TRIM (LDT_CHECK(RCLF_LDT_TRIM, RCLF_LDT_TRIM_BKP) & 0xffU)
|
||||
#define RCLP_TRIM (LDT_CHECK(RCLP_LDT_TRIM, RCLP_LDT_TRIM_BKP) & 0xffU)
|
||||
|
||||
|
||||
#define ULPBG_LDT_TRIM (*(uint32_t *)0x1FFFFA98U)
|
||||
|
||||
#define ULPBG_LDT_TRIM_BKP (*(uint16_t *)0x1FFFFBAAU) /* 备份值 */
|
||||
|
||||
#define ULPBG_TRIM (LDT_CHECK(ULPBG_LDT_TRIM, ULPBG_LDT_TRIM_BKP) & 0x1fU)
|
||||
|
||||
/* Default Clock Frequency Values --------------------------------------------*/
|
||||
|
||||
#define XTHF_DEFAULT_VALUE ((uint32_t)8000000U) /*!< Default value of XTHF in Hz */
|
||||
#define XTLF_DEFAULT_VALUE ((uint32_t)32768U) /*!< Default value of XTLF in Hz */
|
||||
|
||||
/* Default system core clock value */
|
||||
#define HCLK_DEFAULT_VALUE ((uint32_t)8000000U)
|
||||
|
||||
/* Exported Clock Frequency Variables --------------------------------------- */
|
||||
/*
|
||||
- [SystemCoreClock] holds the value of CPU operation clock freqency, and is initialized
|
||||
to HCLK_DEFAULT_VALUE;
|
||||
- [XTLFClock] holds the value of external low-frequency oscillator(XTLF),
|
||||
and is initialized to XTLF_DEFAULT_VALUE;
|
||||
- [XTHFClock] holds the value of external high_frequency oscillator(XTHF),
|
||||
and is initialized to XTHF_DEFAULT_VALUE;
|
||||
|
||||
NOTE: If users are using these two external oscillators, they should modify the
|
||||
value of XTLFClock and XTHFClock to the correct value, and call the SystemCoreClockUpdate()
|
||||
to update the SystemCoreClock variable, otherwise those codes which rely on
|
||||
the SystemCoreClock variable will fail to run.
|
||||
*/
|
||||
extern uint32_t XTLFClock; /*!< External Low-freq Osc Clock Frequency (XTLF) */
|
||||
extern uint32_t XTHFClock; /*!< External High-freq Osc Clock Frequency (XTHF) */
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_FM33LG0XX_H */
|
||||
@ -0,0 +1,231 @@
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000800
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD FDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD DAC_IRQHandler ; 6: DAC
|
||||
DCD SPI0_IRQHandler ; 7: SPI0
|
||||
DCD SPI1_IRQHandler ; 8: SPI1
|
||||
DCD SPI2_IRQHandler ; 9: SPI2
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART3_IRQHandler ; 12: UART3
|
||||
DCD UART4_IRQHandler ; 13: UART4
|
||||
DCD UART5_IRQHandler ; 14: UART5
|
||||
DCD 0 ; 15:
|
||||
DCD LPUARTx_IRQHandler ; 16: LPUART
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD CCL_IRQHandler ; 18: CCL
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUPx_IRQHandler ; 22: WKUP
|
||||
DCD LUT_IRQHandler ; 23: LUT
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1
|
||||
DCD GPTIM2_IRQHandler ; 27: GPTIM2
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD CAN_IRQHandler ; 31: CAN
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT GPIO_IRQHandler [WEAK]
|
||||
EXPORT VREF_IRQHandler [WEAK]
|
||||
EXPORT ATIM_IRQHandler [WEAK]
|
||||
EXPORT GPTIM2_IRQHandler [WEAK]
|
||||
EXPORT GPTIM0_1_IRQHandler [WEAK]
|
||||
EXPORT COMPx_IRQHandler [WEAK]
|
||||
EXPORT BSTIM_IRQHandler [WEAK]
|
||||
EXPORT LUT_IRQHandler [WEAK]
|
||||
EXPORT WKUPx_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT LPTIM_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT CCL_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT LPUARTx_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT FDET_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT SVD_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
|
||||
CAN_IRQHandler
|
||||
GPIO_IRQHandler
|
||||
VREF_IRQHandler
|
||||
ATIM_IRQHandler
|
||||
GPTIM2_IRQHandler
|
||||
GPTIM0_1_IRQHandler
|
||||
COMPx_IRQHandler
|
||||
BSTIM_IRQHandler
|
||||
LUT_IRQHandler
|
||||
WKUPx_IRQHandler
|
||||
DMA_IRQHandler
|
||||
LPTIM_IRQHandler
|
||||
AES_IRQHandler
|
||||
CCL_IRQHandler
|
||||
I2C_IRQHandler
|
||||
LPUARTx_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
DAC_IRQHandler
|
||||
ADC_IRQHandler
|
||||
FDET_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RTC_IRQHandler
|
||||
SVD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
*****END OF FILE*****
|
||||
@ -0,0 +1,139 @@
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Stack_Size = 0x400; /* amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
|
||||
/* system stack */
|
||||
PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/
|
||||
ASSERT ((_stack_base > end), "Error: No room left for the stack")
|
||||
/* _estack is top of stack*/
|
||||
|
||||
/* left ram for heap */
|
||||
PROVIDE (heap_start = _end);
|
||||
PROVIDE (heap_end = _stack_base);
|
||||
PROVIDE (heap_len = heap_end - heap_start);
|
||||
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@ -0,0 +1,131 @@
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Stack_Size = 0x400; /* amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
|
||||
/* system stack */
|
||||
PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/
|
||||
ASSERT ((_stack_base > end), "Error: No room left for the stack")
|
||||
/* _estack is top of stack*/
|
||||
|
||||
/* left ram for heap */
|
||||
PROVIDE (heap_start = _end);
|
||||
PROVIDE (heap_end = _stack_base);
|
||||
PROVIDE (heap_len = heap_end - heap_start);
|
||||
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@ -0,0 +1,250 @@
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
// bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.global g_pfnVectors
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word WWDT_IRQHandler /* 0: WWDT */
|
||||
.word SVD_IRQHandler /* 1: SVD */
|
||||
.word RTC_IRQHandler /* 2: RTC */
|
||||
.word FLASH_IRQHandler /* 3: FLASH */
|
||||
.word FDET_IRQHandler /* 4: FDET */
|
||||
.word ADC_IRQHandler /* 5: ADC */
|
||||
.word DAC_IRQHandler /* 6: DAC */
|
||||
.word SPI0_IRQHandler /* 7: SPI0 */
|
||||
.word SPI1_IRQHandler /* 8: SPI1 */
|
||||
.word SPI2_IRQHandler /* 9: SPI2 */
|
||||
.word UART0_IRQHandler /* 10: UART0 */
|
||||
.word UART1_IRQHandler /* 11: UART1 */
|
||||
.word UART3_IRQHandler /* 12: UART3 */
|
||||
.word UART4_IRQHandler /* 13: UART4 */
|
||||
.word UART5_IRQHandler /* 14: UART5 */
|
||||
.word U7816_IRQHandler /* 15: U7816 */
|
||||
.word LPUARTx_IRQHandler /* 16: LPUARTx */
|
||||
.word I2C_IRQHandler /* 17: I2C */
|
||||
.word CCL_IRQHandler /* 18: CCL */
|
||||
.word AES_IRQHandler /* 19: AES */
|
||||
.word LPTIM_IRQHandler /* 20: LPTIM */
|
||||
.word DMA_IRQHandler /* 21: DMA */
|
||||
.word WKUPx_IRQHandler /* 22: WKUP */
|
||||
.word LUT_IRQHandler /* 23: LUT */
|
||||
.word BSTIM_IRQHandler /* 24: BSTIM */
|
||||
.word COMPx_IRQHandler /* 25: COMPx */
|
||||
.word GPTIM0_1_IRQHandler /* 26: GPTIM0(1) */
|
||||
.word GPTIM2_IRQHandler /* 27: GPTIM2 */
|
||||
.word ATIM_IRQHandler /* 28: ATIM */
|
||||
.word VREF_IRQHandler /* 39: VREF */
|
||||
.word GPIO_IRQHandler /* 30: GPIO */
|
||||
.word CAN_IRQHandler /* 31: CAN */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDT_IRQHandler
|
||||
.thumb_set WWDT_IRQHandler,Default_Handler
|
||||
|
||||
.weak SVD_IRQHandler
|
||||
.thumb_set SVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDET_IRQHandler
|
||||
.thumb_set FDET_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART0_IRQHandler
|
||||
.thumb_set UART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART1_IRQHandler
|
||||
.thumb_set UART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak U7816_IRQHandler
|
||||
.thumb_set U7816_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUARTx_IRQHandler
|
||||
.thumb_set LPUARTx_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C_IRQHandler
|
||||
.thumb_set I2C_IRQHandler,Default_Handler
|
||||
|
||||
.weak CCL_IRQHandler
|
||||
.thumb_set CCL_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM_IRQHandler
|
||||
.thumb_set LPTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_IRQHandler
|
||||
.thumb_set DMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak WKUPx_IRQHandler
|
||||
.thumb_set WKUPx_IRQHandler,Default_Handler
|
||||
|
||||
.weak LUT_IRQHandler
|
||||
.thumb_set LUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak BSTIM_IRQHandler
|
||||
.thumb_set BSTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMPx_IRQHandler
|
||||
.thumb_set COMPx_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPTIM0_1_IRQHandler
|
||||
.thumb_set GPTIM0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPTIM2_IRQHandler
|
||||
.thumb_set GPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak ATIM_IRQHandler
|
||||
.thumb_set ATIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak VREF_IRQHandler
|
||||
.thumb_set VREF_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPIO_IRQHandler
|
||||
.thumb_set GPIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN_IRQHandler
|
||||
.thumb_set CAN_IRQHandler,Default_Handler
|
||||
|
||||
@ -0,0 +1,299 @@
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD FDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD DAC_IRQHandler ; 6: DAC
|
||||
DCD SPI0_IRQHandler ; 7: SPI0
|
||||
DCD SPI1_IRQHandler ; 8: SPI1
|
||||
DCD SPI2_IRQHandler ; 9: SPI2
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART3_IRQHandler ; 12: UART3
|
||||
DCD UART4_IRQHandler ; 13: UART4
|
||||
DCD UART5_IRQHandler ; 14: UART5
|
||||
DCD U7816_IRQHandler ; 15: U7816
|
||||
DCD LPUARTx_IRQHandler ; 16: LPUART
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD CCL_IRQHandler ; 18: CCL
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUPx_IRQHandler ; 22: WKUP
|
||||
DCD LUT_IRQHandler ; 23: LUT
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1
|
||||
DCD GPTIM2_IRQHandler ; 27: GPTIM2
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD CAN_IRQHandler ; 31: CAN
|
||||
__Vectors_End
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WDT_IRQHandler
|
||||
B WDT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVD_IRQHandler
|
||||
B SVD_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK FDET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDET_IRQHandler
|
||||
B FDET_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK U7816_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
U7816_IRQHandler
|
||||
B U7816_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPUARTx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUARTx_IRQHandler
|
||||
B LPUARTx_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK I2C_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C_IRQHandler
|
||||
B I2C_IRQHandler
|
||||
|
||||
PUBWEAK CCL_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CCL_IRQHandler
|
||||
B CCL_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM_IRQHandler
|
||||
B LPTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK WKUPx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WKUPx_IRQHandler
|
||||
B WKUPx_IRQHandler
|
||||
|
||||
PUBWEAK LUT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LUT_IRQHandler
|
||||
B LUT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK BSTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BSTIM_IRQHandler
|
||||
B BSTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK COMPx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMPx_IRQHandler
|
||||
B COMPx_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM0_1_IRQHandler
|
||||
B GPTIM0_1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM2_IRQHandler
|
||||
B GPTIM2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ATIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ATIM_IRQHandler
|
||||
B ATIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK VREF_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
VREF_IRQHandler
|
||||
B VREF_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
END
|
||||
@ -0,0 +1,300 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_fm33lg0xx.c
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
|
||||
* Device FM33LG0XX
|
||||
* @version V2.0.0
|
||||
* @date 15. Mar 2021
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#include "system_fm33lg0xx.h"
|
||||
|
||||
/* Clock Variable definitions ------------------------------------------------*/
|
||||
uint32_t XTLFClock = XTLF_DEFAULT_VALUE; /*!< External Low-freq Osc Clock Frequency (XTLF) */
|
||||
uint32_t XTHFClock = XTHF_DEFAULT_VALUE; /*!< External High-freq Osc Clock Frequency (XTHF) */
|
||||
uint32_t SystemCoreClock = HCLK_DEFAULT_VALUE; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/* Clock functions -----------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Retrieve the PLL clock frequency
|
||||
*
|
||||
* @retval PLL clock frequency
|
||||
*/
|
||||
static uint32_t SystemPLLClockUpdate(void)
|
||||
{
|
||||
uint32_t clock = 0;
|
||||
|
||||
/* Acquire PLL clock source */
|
||||
switch ((CMU->PLLCR >> 1) & 0x1)
|
||||
{
|
||||
case 0:
|
||||
switch ((CMU->RCHFCR >> 16) & 0xFU)
|
||||
{
|
||||
case 1: /* 16MHz */
|
||||
clock = 16000000;
|
||||
break;
|
||||
|
||||
case 2: /* 24MHz */
|
||||
clock = 24000000;
|
||||
break;
|
||||
|
||||
case 3: /* 32MHz */
|
||||
clock = 32000000;
|
||||
break;
|
||||
|
||||
case 0: /* 8MHz */
|
||||
default:
|
||||
clock = 8000000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
clock = XTHFClock;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Acquire PLL prescaler */
|
||||
switch ((CMU->PLLCR >> 0x4) & 0x7)
|
||||
{
|
||||
case 0: /* input divided by 1 */
|
||||
clock /= 1;
|
||||
break;
|
||||
|
||||
case 1: /* input divided by 2 */
|
||||
clock /= 2;
|
||||
break;
|
||||
|
||||
case 2: /* input divided by 4 */
|
||||
clock /= 4;
|
||||
break;
|
||||
|
||||
case 3: /* input divided by 8 */
|
||||
clock /= 8;
|
||||
break;
|
||||
|
||||
case 4: /* input divided by 12 */
|
||||
clock /= 12;
|
||||
break;
|
||||
|
||||
case 5: /* input divided by 16 */
|
||||
clock /= 16;
|
||||
break;
|
||||
|
||||
case 6: /* input divided by 24 */
|
||||
clock /= 24;
|
||||
break;
|
||||
|
||||
case 7: /* input divided by 32 */
|
||||
clock /= 32;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Acquire PLL multiplier and calculate PLL frequency */
|
||||
clock = clock * (((CMU->PLLCR >> 16) & 0x7F) + 1);
|
||||
|
||||
/* Acquire PLL output channel(PLLx1 or PLLx2) */
|
||||
if ((CMU->PLLCR >> 3) & 0x1)
|
||||
{
|
||||
clock *= 2;
|
||||
}
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update the core clock frequency variable: SystemCoreClock
|
||||
*
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
switch ((CMU->SYSCLKCR >> 0) & 0x7)
|
||||
{
|
||||
case 1: /* XTHF */
|
||||
SystemCoreClock = XTHFClock;
|
||||
break;
|
||||
|
||||
case 2: /* PLL */
|
||||
SystemCoreClock = SystemPLLClockUpdate();
|
||||
break;
|
||||
|
||||
case 4: /* RCLF */
|
||||
switch ((CMU->RCLFCR >> 16) & 0x3)
|
||||
{
|
||||
case 0: /* output divided by 1 */
|
||||
SystemCoreClock = 614400;
|
||||
break;
|
||||
|
||||
case 1: /* output divided by 4 */
|
||||
SystemCoreClock = 153600;
|
||||
break;
|
||||
|
||||
case 2: /* output divided by 8 */
|
||||
SystemCoreClock = 76800;
|
||||
break;
|
||||
|
||||
case 3: /* output divided by 16 */
|
||||
SystemCoreClock = 38400;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 5: /* XTLF */
|
||||
SystemCoreClock = XTLFClock;
|
||||
break;
|
||||
|
||||
case 6: /* RCLP */
|
||||
SystemCoreClock = 32000;
|
||||
break;
|
||||
|
||||
default:
|
||||
switch ((CMU->RCHFCR >> 16) & 0xf)
|
||||
{
|
||||
case 1: /* 16MHz */
|
||||
SystemCoreClock = 16000000;
|
||||
break;
|
||||
|
||||
case 2: /* 24MHz */
|
||||
SystemCoreClock = 24000000;
|
||||
break;
|
||||
|
||||
case 3: /* 32MHz */
|
||||
SystemCoreClock = 32000000;
|
||||
break;
|
||||
|
||||
case 0: /* 8MHz */
|
||||
default:
|
||||
SystemCoreClock = 8000000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* AHB Prescaler */
|
||||
switch((CMU->SYSCLKCR >> 8) & 0x7)
|
||||
{
|
||||
case 4: /* divide by 2 */
|
||||
SystemCoreClock /= 2;
|
||||
break;
|
||||
|
||||
case 5: /* divide by 4 */
|
||||
SystemCoreClock /= 4;
|
||||
break;
|
||||
|
||||
case 6: /* divide by 8 */
|
||||
SystemCoreClock /= 8;
|
||||
break;
|
||||
|
||||
case 7: /* divide by 16 */
|
||||
SystemCoreClock /= 16;
|
||||
break;
|
||||
|
||||
default: /* no division */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
||||
#if defined(USE_IWDT_ON_STARTUP)
|
||||
CMU->PCLKCR1 |= 0x20U; /* Enable IWDT Operation Clock */
|
||||
IWDT->CR = IWDT_OVERFLOW_PERIOD; /* Configure IWDT overflow period */
|
||||
IWDT->SERV = 0x12345A5AU; /* Enable IWDT */
|
||||
#endif
|
||||
|
||||
/* Enable VREF Operation Clock */
|
||||
CMU->PCLKCR1 |= 0x1U << 12;
|
||||
|
||||
/* Enable PAD Operation Clock */
|
||||
CMU->PCLKCR1 |= 0x1U << 7;
|
||||
|
||||
#ifdef USE_LSCLK_AUTO_SWITCH
|
||||
|
||||
/* Enable LSCLK auto switch */
|
||||
CMU->SYSCLKCR |= 0x8000000U;
|
||||
CMU->LSCLKSEL = 0x55U;
|
||||
|
||||
#else
|
||||
|
||||
/* Disable LSCLK auto switch */
|
||||
CMU->SYSCLKCR &= 0x7FFFFFFU;
|
||||
CMU->LSCLKSEL = 0x55U;
|
||||
|
||||
#endif /* USE_LSCLK_AUTO_SWITCH */
|
||||
|
||||
/* Keep timers running and disable IWDT && WWDT under debug mode */
|
||||
DBG->CR = 0x3U;
|
||||
|
||||
#ifdef USE_DEBUG_UNDER_SLEEP
|
||||
/* Keep debug connnection under sleep mode */
|
||||
DBG->CR |= 0x1U << 16;
|
||||
#endif
|
||||
|
||||
/* Load power trim value */
|
||||
PMU->ULPB_TR = ULPBG_TRIM;
|
||||
|
||||
/* Load default clock trim value */
|
||||
CMU->RCHFTR = RCHF8M_TRIM;
|
||||
CMU->RCLFTR = RCLF_TRIM;
|
||||
CMU->RCLPTR = RCLP_TRIM;
|
||||
|
||||
/* Enable SWD port pull up */
|
||||
GPIOD->PUEN |= 0x3U << 7;
|
||||
|
||||
/*
|
||||
If BOR is disabled, power down will be monitored by PDR. This means VDD can
|
||||
be below the minimum operating voltage(1.65V) to V_PDR threshold without
|
||||
power down reset. To solve this, user should use SVD to monitor VDD voltage.
|
||||
When the VDD voltage drop below 1.65V, program can enter sleep.
|
||||
*/
|
||||
|
||||
/* PDR Config enable 1.5v */
|
||||
RMU->PDRCR = 0x5;
|
||||
|
||||
/* Disable BOR power down */
|
||||
RMU->BORCR = 0x01;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined(USE_IWDT_ON_STARTUP)
|
||||
IWDT->SERV = 0x12345A5AU; /* Feed IWDT */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
40
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33_assert.h
Normal file
40
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33_assert.h
Normal file
@ -0,0 +1,40 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33_assert.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Assert function define
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
#ifndef __FM33_ASSERT_H
|
||||
#define __FM33_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
117
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl.h
Normal file
117
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl.h
Normal file
@ -0,0 +1,117 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Driver Library
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_H
|
||||
#define __FM33LG0XX_FL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_conf.h"
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
|
||||
/* Macros ---------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_Private_Macros FL Driver Library Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FM33LG0xx FL Driver Library version number
|
||||
*/
|
||||
#define __FM33LG0xx_FL_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __FM33LG0xx_FL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __FM33LG0xx_FL_VERSION_SUB2 (0x01) /*!< [15:0] sub2 version */
|
||||
#define __FM33LG0xx_FL_VERSION ((__FM33LG0xx_FL_VERSION_MAIN << 24)\
|
||||
|(__FM33LG0xx_FL_VERSION_SUB1 << 16)\
|
||||
|(__FM33LG0xx_FL_VERSION_SUB2))
|
||||
|
||||
/**
|
||||
* @brief Macros used by delay support functions
|
||||
*/
|
||||
#define FL_DELAY_US (SystemCoreClock/1000000)
|
||||
#define FL_DELAY_MS (SystemCoreClock/1000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Struct Defines -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_ET_NVIC FL Driver Library NVIC Init Sturcture Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/** 中断抢占优先级 */
|
||||
uint32_t preemptPriority;
|
||||
|
||||
} FL_NVIC_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported Functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_EF_DELAY Exported FL Driver Library Delay Support Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FL_DelayInit(void);
|
||||
void FL_DelayUs(uint32_t count);
|
||||
void FL_DelayMs(uint32_t count);
|
||||
void FL_DelayUsStart(uint32_t count);
|
||||
void FL_DelayMsStart(uint32_t count);
|
||||
bool FL_DelayEnd(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FL_EF_INIT FL Driver Library Exported Init Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FL_Init(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FL_EF_NVIC FL Driver Library Exported NVIC Configuration Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FL_NVIC_Init(FL_NVIC_ConfigTypeDef *configStruct, IRQn_Type irq);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_H */
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
2080
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_adc.h
Normal file
2080
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
760
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_aes.h
Normal file
760
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_aes.h
Normal file
@ -0,0 +1,760 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_aes.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of AES FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_AES_H
|
||||
#define __FM33LG0XX_FL_AES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES AES
|
||||
* @brief AES FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup AES_FL_ES_INIT AES Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL AES Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 秘钥长度 */
|
||||
uint32_t keyLength;
|
||||
/* 数据流处理模式 */
|
||||
uint32_t cipherMode;
|
||||
/* AES工作模式 */
|
||||
uint32_t operationMode;
|
||||
/* 输入数据类型 */
|
||||
uint32_t dataType;
|
||||
|
||||
} FL_AES_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup AES_FL_Exported_Constants AES Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AES_CR_KEYLEN_Pos (13U)
|
||||
#define AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos)
|
||||
#define AES_CR_KEYLEN AES_CR_KEYLEN_Msk
|
||||
|
||||
#define AES_CR_DMAOEN_Pos (12U)
|
||||
#define AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos)
|
||||
#define AES_CR_DMAOEN AES_CR_DMAOEN_Msk
|
||||
|
||||
#define AES_CR_DMAIEN_Pos (11U)
|
||||
#define AES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos)
|
||||
#define AES_CR_DMAIEN AES_CR_DMAIEN_Msk
|
||||
|
||||
#define AES_CR_IVRSWAP_Pos (9U)
|
||||
#define AES_CR_IVRSWAP_Msk (0x3U << AES_CR_IVRSWAP_Pos)
|
||||
#define AES_CR_IVRSWAP AES_CR_IVRSWAP_Msk
|
||||
|
||||
#define AES_CR_CHMOD_Pos (5U)
|
||||
#define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos)
|
||||
#define AES_CR_CHMOD AES_CR_CHMOD_Msk
|
||||
|
||||
#define AES_CR_MODE_Pos (3U)
|
||||
#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos)
|
||||
#define AES_CR_MODE AES_CR_MODE_Msk
|
||||
|
||||
#define AES_CR_DATATYP_Pos (1U)
|
||||
#define AES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos)
|
||||
#define AES_CR_DATATYP AES_CR_DATATYP_Msk
|
||||
|
||||
#define AES_CR_EN_Pos (0U)
|
||||
#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos)
|
||||
#define AES_CR_EN AES_CR_EN_Msk
|
||||
|
||||
#define AES_IER_WRERR_IE_Pos (2U)
|
||||
#define AES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos)
|
||||
#define AES_IER_WRERR_IE AES_IER_WRERR_IE_Msk
|
||||
|
||||
#define AES_IER_RDERR_IE_Pos (1U)
|
||||
#define AES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos)
|
||||
#define AES_IER_RDERR_IE AES_IER_RDERR_IE_Msk
|
||||
|
||||
#define AES_IER_CCF_IE_Pos (0U)
|
||||
#define AES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos)
|
||||
#define AES_IER_CCF_IE AES_IER_CCF_IE_Msk
|
||||
|
||||
#define AES_ISR_WRERR_Pos (2U)
|
||||
#define AES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos)
|
||||
#define AES_ISR_WRERR AES_ISR_WRERR_Msk
|
||||
|
||||
#define AES_ISR_RDERR_Pos (1U)
|
||||
#define AES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos)
|
||||
#define AES_ISR_RDERR AES_ISR_RDERR_Msk
|
||||
|
||||
#define AES_ISR_CCF_Pos (0U)
|
||||
#define AES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos)
|
||||
#define AES_ISR_CCF AES_ISR_CCF_Msk
|
||||
|
||||
|
||||
|
||||
#define FL_AES_KEY0_OFFSET (0x0U << 0U)
|
||||
#define FL_AES_KEY1_OFFSET (0x1U << 0U)
|
||||
#define FL_AES_KEY2_OFFSET (0x2U << 0U)
|
||||
#define FL_AES_KEY3_OFFSET (0x3U << 0U)
|
||||
#define FL_AES_KEY4_OFFSET (0x4U << 0U)
|
||||
#define FL_AES_KEY5_OFFSET (0x5U << 0U)
|
||||
#define FL_AES_KEY6_OFFSET (0x6U << 0U)
|
||||
#define FL_AES_KEY7_OFFSET (0x7U << 0U)
|
||||
#define FL_AES_IVR0_OFFSET (0x0U << 0U)
|
||||
#define FL_AES_IVR1_OFFSET (0x1U << 0U)
|
||||
#define FL_AES_IVR2_OFFSET (0x2U << 0U)
|
||||
#define FL_AES_IVR3_OFFSET (0x3U << 0U)
|
||||
#define FL_AES_H0_OFFSET (0x0U << 0U)
|
||||
#define FL_AES_H1_OFFSET (0x1U << 0U)
|
||||
#define FL_AES_H2_OFFSET (0x2U << 0U)
|
||||
#define FL_AES_H3_OFFSET (0x3U << 0U)
|
||||
|
||||
|
||||
|
||||
#define FL_AES_KEY_LENGTH_128B (0x0U << AES_CR_KEYLEN_Pos)
|
||||
#define FL_AES_KEY_LENGTH_192B (0x1U << AES_CR_KEYLEN_Pos)
|
||||
#define FL_AES_KEY_LENGTH_256B (0x2U << AES_CR_KEYLEN_Pos)
|
||||
|
||||
|
||||
#define FL_AES_IVR_SWAP_32B (0x0U << AES_CR_IVRSWAP_Pos)
|
||||
#define FL_AES_IVR_SWAP_16B (0x1U << AES_CR_IVRSWAP_Pos)
|
||||
#define FL_AES_IVR_SWAP_8B (0x2U << AES_CR_IVRSWAP_Pos)
|
||||
#define FL_AES_IVR_SWAP_1B (0x3U << AES_CR_IVRSWAP_Pos)
|
||||
|
||||
|
||||
#define FL_AES_CIPHER_ECB (0x0U << AES_CR_CHMOD_Pos)
|
||||
#define FL_AES_CIPHER_CBC (0x1U << AES_CR_CHMOD_Pos)
|
||||
#define FL_AES_CIPHER_CTR (0x2U << AES_CR_CHMOD_Pos)
|
||||
#define FL_AES_CIPHER_MULTH (0x3U << AES_CR_CHMOD_Pos)
|
||||
|
||||
|
||||
#define FL_AES_OPERATION_MODE_ENCRYPTION (0x0U << AES_CR_MODE_Pos)
|
||||
#define FL_AES_OPERATION_MODE_KEYDERIVATION (0x1U << AES_CR_MODE_Pos)
|
||||
#define FL_AES_OPERATION_MODE_DECRYPTION (0x2U << AES_CR_MODE_Pos)
|
||||
#define FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION (0x3U << AES_CR_MODE_Pos)
|
||||
|
||||
|
||||
#define FL_AES_DATA_TYPE_32B (0x0U << AES_CR_DATATYP_Pos)
|
||||
#define FL_AES_DATA_TYPE_16B (0x1U << AES_CR_DATATYP_Pos)
|
||||
#define FL_AES_DATA_TYPE_8B (0x2U << AES_CR_DATATYP_Pos)
|
||||
#define FL_AES_DATA_TYPE_1B (0x3U << AES_CR_DATATYP_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup AES_FL_Exported_Functions AES Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set key size selection
|
||||
* @rmtoll CR KEYLEN FL_AES_SetKeySize
|
||||
* @param AESx AES instance
|
||||
* @param keySize This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_KEY_LENGTH_128B
|
||||
* @arg @ref FL_AES_KEY_LENGTH_192B
|
||||
* @arg @ref FL_AES_KEY_LENGTH_256B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_SetKeySize(AES_Type *AESx, uint32_t keySize)
|
||||
{
|
||||
MODIFY_REG(AESx->CR, AES_CR_KEYLEN_Msk, keySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get key size selection
|
||||
* @rmtoll CR KEYLEN FL_AES_GetKeySize
|
||||
* @param AESx AES instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_AES_KEY_LENGTH_128B
|
||||
* @arg @ref FL_AES_KEY_LENGTH_192B
|
||||
* @arg @ref FL_AES_KEY_LENGTH_256B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_GetKeySize(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_KEYLEN_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA output enable
|
||||
* @rmtoll CR DMAOEN FL_AES_EnableDMAReq_Output
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_EnableDMAReq_Output(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->CR, AES_CR_DMAOEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA output enable status
|
||||
* @rmtoll CR DMAOEN FL_AES_IsEnabledDMAReq_Output
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabledDMAReq_Output(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_DMAOEN_Msk) == AES_CR_DMAOEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA output disable
|
||||
* @rmtoll CR DMAOEN FL_AES_DisableDMAReq_Output
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_DisableDMAReq_Output(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->CR, AES_CR_DMAOEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA input enable
|
||||
* @rmtoll CR DMAIEN FL_AES_EnableDMAReq_Input
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_EnableDMAReq_Input(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->CR, AES_CR_DMAIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA input enable status
|
||||
* @rmtoll CR DMAIEN FL_AES_IsEnabledDMAReq_Input
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabledDMAReq_Input(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_DMAIEN_Msk) == AES_CR_DMAIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA input disable
|
||||
* @rmtoll CR DMAIEN FL_AES_DisableDMAReq_Input
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_DisableDMAReq_Input(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->CR, AES_CR_DMAIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set IVR register read out swapping
|
||||
* @rmtoll CR IVRSWAP FL_AES_SetIVRSwapType
|
||||
* @param AESx AES instance
|
||||
* @param type This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_IVR_SWAP_32B
|
||||
* @arg @ref FL_AES_IVR_SWAP_16B
|
||||
* @arg @ref FL_AES_IVR_SWAP_8B
|
||||
* @arg @ref FL_AES_IVR_SWAP_1B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_SetIVRSwapType(AES_Type *AESx, uint32_t type)
|
||||
{
|
||||
MODIFY_REG(AESx->CR, AES_CR_IVRSWAP_Msk, type);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IVR register read out swapping
|
||||
* @rmtoll CR IVRSWAP FL_AES_GetIVRSwapType
|
||||
* @param AESx AES instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_AES_IVR_SWAP_32B
|
||||
* @arg @ref FL_AES_IVR_SWAP_16B
|
||||
* @arg @ref FL_AES_IVR_SWAP_8B
|
||||
* @arg @ref FL_AES_IVR_SWAP_1B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_GetIVRSwapType(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_IVRSWAP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set cipher mode
|
||||
* @rmtoll CR CHMOD FL_AES_SetCipherMode
|
||||
* @param AESx AES instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_CIPHER_ECB
|
||||
* @arg @ref FL_AES_CIPHER_CBC
|
||||
* @arg @ref FL_AES_CIPHER_CTR
|
||||
* @arg @ref FL_AES_CIPHER_MULTH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_SetCipherMode(AES_Type *AESx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(AESx->CR, AES_CR_CHMOD_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cipher mode
|
||||
* @rmtoll CR CHMOD FL_AES_GetCipherMode
|
||||
* @param AESx AES instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_AES_CIPHER_ECB
|
||||
* @arg @ref FL_AES_CIPHER_CBC
|
||||
* @arg @ref FL_AES_CIPHER_CTR
|
||||
* @arg @ref FL_AES_CIPHER_MULTH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_GetCipherMode(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_CHMOD_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set operation mode
|
||||
* @rmtoll CR MODE FL_AES_SetOperationMode
|
||||
* @param AESx AES instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_OPERATION_MODE_ENCRYPTION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_DECRYPTION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_SetOperationMode(AES_Type *AESx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(AESx->CR, AES_CR_MODE_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get operation mode
|
||||
* @rmtoll CR MODE FL_AES_GetOperationMode
|
||||
* @param AESx AES instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_AES_OPERATION_MODE_ENCRYPTION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_DECRYPTION
|
||||
* @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_GetOperationMode(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_MODE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set data type selection
|
||||
* @rmtoll CR DATATYP FL_AES_SetDataType
|
||||
* @param AESx AES instance
|
||||
* @param rule This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_DATA_TYPE_32B
|
||||
* @arg @ref FL_AES_DATA_TYPE_16B
|
||||
* @arg @ref FL_AES_DATA_TYPE_8B
|
||||
* @arg @ref FL_AES_DATA_TYPE_1B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_SetDataType(AES_Type *AESx, uint32_t rule)
|
||||
{
|
||||
MODIFY_REG(AESx->CR, AES_CR_DATATYP_Msk, rule);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get data type selection
|
||||
* @rmtoll CR DATATYP FL_AES_GetDataType
|
||||
* @param AESx AES instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_AES_DATA_TYPE_32B
|
||||
* @arg @ref FL_AES_DATA_TYPE_16B
|
||||
* @arg @ref FL_AES_DATA_TYPE_8B
|
||||
* @arg @ref FL_AES_DATA_TYPE_1B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_GetDataType(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_DATATYP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AES enable
|
||||
* @rmtoll CR EN FL_AES_Enable
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_Enable(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->CR, AES_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AES enable status
|
||||
* @rmtoll CR EN FL_AES_IsEnabled
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabled(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->CR, AES_CR_EN_Msk) == AES_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AES disable
|
||||
* @rmtoll CR EN FL_AES_Disable
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_Disable(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->CR, AES_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write error interrupt enable
|
||||
* @rmtoll IER WRERR_IE FL_AES_EnableIT_WriteError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_EnableIT_WriteError(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->IER, AES_IER_WRERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get write error interrupt enable status
|
||||
* @rmtoll IER WRERR_IE FL_AES_IsEnabledIT_WriteError
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_WriteError(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->IER, AES_IER_WRERR_IE_Msk) == AES_IER_WRERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write error interrupt disable
|
||||
* @rmtoll IER WRERR_IE FL_AES_DisableIT_WriteError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_DisableIT_WriteError(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->IER, AES_IER_WRERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read error interrupt enable
|
||||
* @rmtoll IER RDERR_IE FL_AES_EnableIT_ReadError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_EnableIT_ReadError(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->IER, AES_IER_RDERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get read Error interrupt enable status
|
||||
* @rmtoll IER RDERR_IE FL_AES_IsEnabledIT_ReadError
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_ReadError(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->IER, AES_IER_RDERR_IE_Msk) == AES_IER_RDERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read error interrupt disable
|
||||
* @rmtoll IER RDERR_IE FL_AES_DisableIT_ReadError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_DisableIT_ReadError(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->IER, AES_IER_RDERR_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Cipher complete interrupt enable
|
||||
* @rmtoll IER CCF_IE FL_AES_EnableIT_Complete
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_EnableIT_Complete(AES_Type *AESx)
|
||||
{
|
||||
SET_BIT(AESx->IER, AES_IER_CCF_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cipher complete interrupt enable status
|
||||
* @rmtoll IER CCF_IE FL_AES_IsEnabledIT_Complete
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_Complete(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->IER, AES_IER_CCF_IE_Msk) == AES_IER_CCF_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Cipher complete interrupt disable
|
||||
* @rmtoll IER CCF_IE FL_AES_DisableIT_Complete
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_DisableIT_Complete(AES_Type *AESx)
|
||||
{
|
||||
CLEAR_BIT(AESx->IER, AES_IER_CCF_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get write error flag
|
||||
* @rmtoll ISR WRERR FL_AES_IsActiveFlag_WriteError
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_WriteError(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_WRERR_Msk) == (AES_ISR_WRERR_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear write error flag
|
||||
* @rmtoll ISR WRERR FL_AES_ClearFlag_WriteError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_ClearFlag_WriteError(AES_Type *AESx)
|
||||
{
|
||||
WRITE_REG(AESx->ISR, AES_ISR_WRERR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get read error flag
|
||||
* @rmtoll ISR RDERR FL_AES_IsActiveFlag_ReadError
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_ReadError(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_RDERR_Msk) == (AES_ISR_RDERR_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear read error flag
|
||||
* @rmtoll ISR RDERR FL_AES_ClearFlag_ReadError
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_ClearFlag_ReadError(AES_Type *AESx)
|
||||
{
|
||||
WRITE_REG(AESx->ISR, AES_ISR_RDERR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cipher complete flag
|
||||
* @rmtoll ISR CCF FL_AES_IsActiveFlag_Complete
|
||||
* @param AESx AES instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_Complete(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_CCF_Msk) == (AES_ISR_CCF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear cipher complete flag
|
||||
* @rmtoll ISR CCF FL_AES_ClearFlag_Complete
|
||||
* @param AESx AES instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_ClearFlag_Complete(AES_Type *AESx)
|
||||
{
|
||||
WRITE_REG(AESx->ISR, AES_ISR_CCF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write AES data input register
|
||||
* @rmtoll DIR FL_AES_WriteInputData
|
||||
* @param AESx AES instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_WriteInputData(AES_Type *AESx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(AESx->DIR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read AES data output register
|
||||
* @rmtoll DOR FL_AES_ReadOutputData
|
||||
* @param AESx AES instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_ReadOutputData(AES_Type *AESx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(AESx->DOR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set key registers
|
||||
* @rmtoll KEY0 FL_AES_WriteKeys
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_KEY0_OFFSET
|
||||
* @arg @ref FL_AES_KEY1_OFFSET
|
||||
* @arg @ref FL_AES_KEY2_OFFSET
|
||||
* @arg @ref FL_AES_KEY3_OFFSET
|
||||
* @arg @ref FL_AES_KEY4_OFFSET
|
||||
* @arg @ref FL_AES_KEY5_OFFSET
|
||||
* @arg @ref FL_AES_KEY6_OFFSET
|
||||
* @arg @ref FL_AES_KEY7_OFFSET
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_WriteKeys(AES_Type *AESx, uint32_t offset, uint32_t data)
|
||||
{
|
||||
WRITE_REG(*((&AESx->KEY0) + offset), data);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get key registers
|
||||
* @rmtoll KEY0 FL_AES_ReadKeys
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_KEY0_OFFSET
|
||||
* @arg @ref FL_AES_KEY1_OFFSET
|
||||
* @arg @ref FL_AES_KEY2_OFFSET
|
||||
* @arg @ref FL_AES_KEY3_OFFSET
|
||||
* @arg @ref FL_AES_KEY4_OFFSET
|
||||
* @arg @ref FL_AES_KEY5_OFFSET
|
||||
* @arg @ref FL_AES_KEY6_OFFSET
|
||||
* @arg @ref FL_AES_KEY7_OFFSET
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_ReadKeys(AES_Type *AESx, uint32_t offset)
|
||||
{
|
||||
return (uint32_t)READ_REG(*((&AESx->KEY0) + offset));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write initialization vector registers
|
||||
* @rmtoll DIR FL_AES_WriteIVR
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_IVR0_OFFSET
|
||||
* @arg @ref FL_AES_IVR1_OFFSET
|
||||
* @arg @ref FL_AES_IVR2_OFFSET
|
||||
* @arg @ref FL_AES_IVR3_OFFSET
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_WriteIVR(AES_Type *AESx, uint32_t offset, uint32_t data)
|
||||
{
|
||||
WRITE_REG(*((&AESx->IVR0) + offset), data);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read initialization vector registers
|
||||
* @rmtoll DOR FL_AES_ReadIVR
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_IVR0_OFFSET
|
||||
* @arg @ref FL_AES_IVR1_OFFSET
|
||||
* @arg @ref FL_AES_IVR2_OFFSET
|
||||
* @arg @ref FL_AES_IVR3_OFFSET
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_ReadIVR(AES_Type *AESx, uint32_t offset)
|
||||
{
|
||||
return (uint32_t)READ_REG(*((&AESx->IVR0) + offset));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AES MultH parameter Register
|
||||
* @rmtoll H0 FL_AES_WriteHParams
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_H0_OFFSET
|
||||
* @arg @ref FL_AES_H1_OFFSET
|
||||
* @arg @ref FL_AES_H2_OFFSET
|
||||
* @arg @ref FL_AES_H3_OFFSET
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_AES_WriteHParams(AES_Type *AESx, uint32_t offset, uint32_t data)
|
||||
{
|
||||
WRITE_REG(*((&AESx->H0) + offset), data);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AES MultH parameter Register
|
||||
* @rmtoll H0 FL_AES_ReadHParams
|
||||
* @param AESx AES instance
|
||||
* @param offset This parameter can be one of the following values:
|
||||
* @arg @ref FL_AES_H0_OFFSET
|
||||
* @arg @ref FL_AES_H1_OFFSET
|
||||
* @arg @ref FL_AES_H2_OFFSET
|
||||
* @arg @ref FL_AES_H3_OFFSET
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_AES_ReadHParams(AES_Type *AESx, uint32_t offset)
|
||||
{
|
||||
return (uint32_t)READ_REG(*((&AESx->H0) + offset));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_AES_DeInit(void);
|
||||
void FL_AES_StructInit(FL_AES_InitTypeDef *AES_InitStructer);
|
||||
FL_ErrorStatus FL_AES_Init(AES_Type *AESx, FL_AES_InitTypeDef *AES_InitStructer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_AES_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
3749
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_atim.h
Normal file
3749
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_atim.h
Normal file
File diff suppressed because it is too large
Load Diff
481
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_bstim16.h
Normal file
481
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_bstim16.h
Normal file
@ -0,0 +1,481 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_bstim16.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of BSTIM16 FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_BSTIM16_H
|
||||
#define __FM33LG0XX_FL_BSTIM16_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM16 BSTIM16
|
||||
* @brief BSTIM16 FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM16_FL_ES_INIT BSTIM16 Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL BSTIM16 Init Sturcture definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* 预分频系数 */
|
||||
uint32_t prescaler;
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReload;
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReloadState;
|
||||
|
||||
uint32_t clockSource;
|
||||
|
||||
} FL_BSTIM16_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM16_FL_Exported_Constants BSTIM16 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BSTIM16_CR1_ARPE_Pos (7U)
|
||||
#define BSTIM16_CR1_ARPE_Msk (0x1U << BSTIM16_CR1_ARPE_Pos)
|
||||
#define BSTIM16_CR1_ARPE BSTIM16_CR1_ARPE_Msk
|
||||
|
||||
#define BSTIM16_CR1_OPM_Pos (3U)
|
||||
#define BSTIM16_CR1_OPM_Msk (0x1U << BSTIM16_CR1_OPM_Pos)
|
||||
#define BSTIM16_CR1_OPM BSTIM16_CR1_OPM_Msk
|
||||
|
||||
#define BSTIM16_CR1_URS_Pos (2U)
|
||||
#define BSTIM16_CR1_URS_Msk (0x1U << BSTIM16_CR1_URS_Pos)
|
||||
#define BSTIM16_CR1_URS BSTIM16_CR1_URS_Msk
|
||||
|
||||
#define BSTIM16_CR1_UDIS_Pos (1U)
|
||||
#define BSTIM16_CR1_UDIS_Msk (0x1U << BSTIM16_CR1_UDIS_Pos)
|
||||
#define BSTIM16_CR1_UDIS BSTIM16_CR1_UDIS_Msk
|
||||
|
||||
#define BSTIM16_CR1_CEN_Pos (0U)
|
||||
#define BSTIM16_CR1_CEN_Msk (0x1U << BSTIM16_CR1_CEN_Pos)
|
||||
#define BSTIM16_CR1_CEN BSTIM16_CR1_CEN_Msk
|
||||
|
||||
#define BSTIM16_CR2_MMS_Pos (4U)
|
||||
#define BSTIM16_CR2_MMS_Msk (0x7U << BSTIM16_CR2_MMS_Pos)
|
||||
#define BSTIM16_CR2_MMS BSTIM16_CR2_MMS_Msk
|
||||
|
||||
#define BSTIM16_IER_UIE_Pos (0U)
|
||||
#define BSTIM16_IER_UIE_Msk (0x1U << BSTIM16_IER_UIE_Pos)
|
||||
#define BSTIM16_IER_UIE BSTIM16_IER_UIE_Msk
|
||||
|
||||
#define BSTIM16_ISR_UIF_Pos (0U)
|
||||
#define BSTIM16_ISR_UIF_Msk (0x1U << BSTIM16_ISR_UIF_Pos)
|
||||
#define BSTIM16_ISR_UIF BSTIM16_ISR_UIF_Msk
|
||||
|
||||
#define BSTIM16_EGR_UG_Pos (0U)
|
||||
#define BSTIM16_EGR_UG_Msk (0x1U << BSTIM16_EGR_UG_Pos)
|
||||
#define BSTIM16_EGR_UG BSTIM16_EGR_UG_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_BSTIM16_ONE_PULSE_MODE_CONTINUOUS (0x0U << BSTIM16_CR1_OPM_Pos)
|
||||
#define FL_BSTIM16_ONE_PULSE_MODE_SINGLE (0x1U << BSTIM16_CR1_OPM_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM16_UPDATE_SOURCE_REGULAR (0x0U << BSTIM16_CR1_URS_Pos)
|
||||
#define FL_BSTIM16_UPDATE_SOURCE_COUNTER (0x1U << BSTIM16_CR1_URS_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM16_TRGO_UG (0x0U << BSTIM16_CR2_MMS_Pos)
|
||||
#define FL_BSTIM16_TRGO_ENABLE (0x1U << BSTIM16_CR2_MMS_Pos)
|
||||
#define FL_BSTIM16_TRGO_UPDATE (0x2U << BSTIM16_CR2_MMS_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM16_FL_Exported_Functions BSTIM16 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload enable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM16_EnableARRPreload
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_EnableARRPreload(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
SET_BIT(BSTIM16x->CR1, BSTIM16_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload preload enable status
|
||||
* @rmtoll CR1 ARPE FL_BSTIM16_IsEnabledARRPreload
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_IsEnabledARRPreload(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CR1, BSTIM16_CR1_ARPE_Msk) == BSTIM16_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload disable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM16_DisableARRPreload
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_DisableARRPreload(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM16x->CR1, BSTIM16_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM16_SetOnePulseMode
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM16_ONE_PULSE_MODE_SINGLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_SetOnePulseMode(BSTIM16_Type *BSTIM16x, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->CR1, BSTIM16_CR1_OPM_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM16_GetOnePulseMode
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM16_ONE_PULSE_MODE_SINGLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_GetOnePulseMode(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CR1, BSTIM16_CR1_OPM_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set update request
|
||||
* @rmtoll CR1 URS FL_BSTIM16_SetUpdateSource
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param source This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM16_UPDATE_SOURCE_COUNTER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_SetUpdateSource(BSTIM16_Type *BSTIM16x, uint32_t source)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->CR1, BSTIM16_CR1_URS_Msk, source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update request status
|
||||
* @rmtoll CR1 URS FL_BSTIM16_GetUpdateSource
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM16_UPDATE_SOURCE_COUNTER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_GetUpdateSource(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CR1, BSTIM16_CR1_URS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event enable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM16_EnableUpdateEvent
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_EnableUpdateEvent(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM16x->CR1, BSTIM16_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event disable status
|
||||
* @rmtoll CR1 UDIS FL_BSTIM16_IsEnabledUpdateEvent
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_IsEnabledUpdateEvent(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)!(READ_BIT(BSTIM16x->CR1, BSTIM16_CR1_UDIS_Msk) == BSTIM16_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event disable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM16_DisableUpdateEvent
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_DisableUpdateEvent(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
SET_BIT(BSTIM16x->CR1, BSTIM16_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter enable
|
||||
* @rmtoll CR1 CEN FL_BSTIM16_Enable
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_Enable(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
SET_BIT(BSTIM16x->CR1, BSTIM16_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter enable status
|
||||
* @rmtoll CR1 CEN FL_BSTIM16_IsEnabled
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_IsEnabled(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CR1, BSTIM16_CR1_CEN_Msk) == BSTIM16_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter disable
|
||||
* @rmtoll CR1 CEN FL_BSTIM16_Disable
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_Disable(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM16x->CR1, BSTIM16_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set master Trigger Output mode
|
||||
* @rmtoll CR2 MMS FL_BSTIM16_SetTriggerOutput
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param triggerOutput This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_TRGO_UG
|
||||
* @arg @ref FL_BSTIM16_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM16_TRGO_UPDATE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_SetTriggerOutput(BSTIM16_Type *BSTIM16x, uint32_t triggerOutput)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->CR2, BSTIM16_CR2_MMS_Msk, triggerOutput);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get master Trigger Output mode
|
||||
* @rmtoll CR2 MMS FL_BSTIM16_GetTriggerOutput
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM16_TRGO_UG
|
||||
* @arg @ref FL_BSTIM16_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM16_TRGO_UPDATE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_GetTriggerOutput(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CR2, BSTIM16_CR2_MMS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt disable
|
||||
* @rmtoll IER UIE FL_BSTIM16_DisableIT_Update
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_DisableIT_Update(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM16x->IER, BSTIM16_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt enable
|
||||
* @rmtoll IER UIE FL_BSTIM16_EnableIT_Update
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_EnableIT_Update(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
SET_BIT(BSTIM16x->IER, BSTIM16_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt enable status
|
||||
* @rmtoll IER UIE FL_BSTIM16_IsEnabledIT_Update
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_IsEnabledIT_Update(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->IER, BSTIM16_IER_UIE_Msk) == BSTIM16_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM16_IsActiveFlag_Update
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_IsActiveFlag_Update(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->ISR, BSTIM16_ISR_UIF_Msk) == (BSTIM16_ISR_UIF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM16_ClearFlag_Update
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_ClearFlag_Update(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
WRITE_REG(BSTIM16x->ISR, BSTIM16_ISR_UIF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software update event enable
|
||||
* @rmtoll EGR UG FL_BSTIM16_GenerateUpdateEvent
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_GenerateUpdateEvent(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
SET_BIT(BSTIM16x->EGR, BSTIM16_EGR_UG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter value
|
||||
* @rmtoll CNT FL_BSTIM16_WriteCounter
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param count
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_WriteCounter(BSTIM16_Type *BSTIM16x, uint32_t count)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->CNT, (0xffffU << 0U), (count << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter value
|
||||
* @rmtoll CNT FL_BSTIM16_ReadCounter
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_ReadCounter(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->CNT, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM16_WritePrescaler
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param psc
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_WritePrescaler(BSTIM16_Type *BSTIM16x, uint32_t psc)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->PSC, (0xffffU << 0U), (psc << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM16_ReadPrescaler
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_ReadPrescaler(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->PSC, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM16_WriteAutoReload
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @param value
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM16_WriteAutoReload(BSTIM16_Type *BSTIM16x, uint32_t value)
|
||||
{
|
||||
MODIFY_REG(BSTIM16x->ARR, (0xffffU << 0U), (value << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM16_ReadAutoReload
|
||||
* @param BSTIM16x BSTIM16 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM16_ReadAutoReload(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM16x->ARR, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM16_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_BSTIM16_DeInit(BSTIM16_Type *BSTIM16x);
|
||||
FL_ErrorStatus FL_BSTIM16_Init(BSTIM16_Type *BSTIM16x, FL_BSTIM16_InitTypeDef *init);
|
||||
void FL_BSTIM16_StructInit(FL_BSTIM16_InitTypeDef *init);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_BSTIM16_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
484
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_bstim32.h
Normal file
484
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_bstim32.h
Normal file
@ -0,0 +1,484 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_bstim32.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of BSTIM32 FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_BSTIM32_H
|
||||
#define __FM33LG0XX_FL_BSTIM32_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM32 BSTIM32
|
||||
* @brief BSTIM32 FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_ES_INIT BSTIM32 Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL BSTIM32 Init Sturcture definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* 时钟源 */
|
||||
uint32_t clockSource;
|
||||
|
||||
/* 预分频系数 */
|
||||
uint32_t prescaler;
|
||||
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReload;
|
||||
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReloadState;
|
||||
|
||||
} FL_BSTIM32_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_Exported_Constants BSTIM32 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BSTIM32_CR1_ARPE_Pos (7U)
|
||||
#define BSTIM32_CR1_ARPE_Msk (0x1U << BSTIM32_CR1_ARPE_Pos)
|
||||
#define BSTIM32_CR1_ARPE BSTIM32_CR1_ARPE_Msk
|
||||
|
||||
#define BSTIM32_CR1_OPM_Pos (3U)
|
||||
#define BSTIM32_CR1_OPM_Msk (0x1U << BSTIM32_CR1_OPM_Pos)
|
||||
#define BSTIM32_CR1_OPM BSTIM32_CR1_OPM_Msk
|
||||
|
||||
#define BSTIM32_CR1_URS_Pos (2U)
|
||||
#define BSTIM32_CR1_URS_Msk (0x1U << BSTIM32_CR1_URS_Pos)
|
||||
#define BSTIM32_CR1_URS BSTIM32_CR1_URS_Msk
|
||||
|
||||
#define BSTIM32_CR1_UDIS_Pos (1U)
|
||||
#define BSTIM32_CR1_UDIS_Msk (0x1U << BSTIM32_CR1_UDIS_Pos)
|
||||
#define BSTIM32_CR1_UDIS BSTIM32_CR1_UDIS_Msk
|
||||
|
||||
#define BSTIM32_CR1_CEN_Pos (0U)
|
||||
#define BSTIM32_CR1_CEN_Msk (0x1U << BSTIM32_CR1_CEN_Pos)
|
||||
#define BSTIM32_CR1_CEN BSTIM32_CR1_CEN_Msk
|
||||
|
||||
#define BSTIM32_CR2_MMS_Pos (4U)
|
||||
#define BSTIM32_CR2_MMS_Msk (0x7U << BSTIM32_CR2_MMS_Pos)
|
||||
#define BSTIM32_CR2_MMS BSTIM32_CR2_MMS_Msk
|
||||
|
||||
#define BSTIM32_IER_UIE_Pos (0U)
|
||||
#define BSTIM32_IER_UIE_Msk (0x1U << BSTIM32_IER_UIE_Pos)
|
||||
#define BSTIM32_IER_UIE BSTIM32_IER_UIE_Msk
|
||||
|
||||
#define BSTIM32_ISR_UIF_Pos (0U)
|
||||
#define BSTIM32_ISR_UIF_Msk (0x1U << BSTIM32_ISR_UIF_Pos)
|
||||
#define BSTIM32_ISR_UIF BSTIM32_ISR_UIF_Msk
|
||||
|
||||
#define BSTIM32_EGR_UG_Pos (0U)
|
||||
#define BSTIM32_EGR_UG_Msk (0x1U << BSTIM32_EGR_UG_Pos)
|
||||
#define BSTIM32_EGR_UG BSTIM32_EGR_UG_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS (0x0U << BSTIM32_CR1_OPM_Pos)
|
||||
#define FL_BSTIM32_ONE_PULSE_MODE_SINGLE (0x1U << BSTIM32_CR1_OPM_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM32_UPDATE_SOURCE_REGULAR (0x0U << BSTIM32_CR1_URS_Pos)
|
||||
#define FL_BSTIM32_UPDATE_SOURCE_COUNTER (0x1U << BSTIM32_CR1_URS_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM32_TRGO_UG (0x0U << BSTIM32_CR2_MMS_Pos)
|
||||
#define FL_BSTIM32_TRGO_ENABLE (0x1U << BSTIM32_CR2_MMS_Pos)
|
||||
#define FL_BSTIM32_TRGO_UPDATE (0x2U << BSTIM32_CR2_MMS_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_Exported_Functions BSTIM32 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload enable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_EnableARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload preload enable status
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_IsEnabledARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk) == BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload disable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_DisableARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM32_SetOnePulseMode
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetOnePulseMode(BSTIM32_Type *BSTIM32x, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM32_GetOnePulseMode
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetOnePulseMode(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set update request
|
||||
* @rmtoll CR1 URS FL_BSTIM32_SetUpdateSource
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param source This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetUpdateSource(BSTIM32_Type *BSTIM32x, uint32_t source)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk, source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update request status
|
||||
* @rmtoll CR1 URS FL_BSTIM32_GetUpdateSource
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetUpdateSource(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event enable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_EnableUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event disable status
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_IsEnabledUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)!(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk) == BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event disable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_DisableUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter enable
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_Enable
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_Enable(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter enable status
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_IsEnabled
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabled(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk) == BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter disable
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_Disable
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_Disable(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set master trigger mode
|
||||
* @rmtoll CR2 MMS FL_BSTIM32_SetTriggerOutput
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param triggerOutput This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_TRGO_UG
|
||||
* @arg @ref FL_BSTIM32_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM32_TRGO_UPDATE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetTriggerOutput(BSTIM32_Type *BSTIM32x, uint32_t triggerOutput)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk, triggerOutput);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get master trigger mode status
|
||||
* @rmtoll CR2 MMS FL_BSTIM32_GetTriggerOutput
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_TRGO_UG
|
||||
* @arg @ref FL_BSTIM32_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM32_TRGO_UPDATE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetTriggerOutput(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt disable
|
||||
* @rmtoll IER UIE FL_BSTIM32_DisableIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt enable
|
||||
* @rmtoll IER UIE FL_BSTIM32_EnableIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt enable status
|
||||
* @rmtoll IER UIE FL_BSTIM32_IsEnabledIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk) == BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM32_IsActiveFlag_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsActiveFlag_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk) == (BSTIM32_ISR_UIF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM32_ClearFlag_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_ClearFlag_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
WRITE_REG(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software update event enable
|
||||
* @rmtoll EGR UG FL_BSTIM32_GenerateUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_GenerateUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->EGR, BSTIM32_EGR_UG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter value
|
||||
* @rmtoll CNT FL_BSTIM32_WriteCounter
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param count
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WriteCounter(BSTIM32_Type *BSTIM32x, uint32_t count)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CNT, (0xffffffffU << 0U), (count << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter value
|
||||
* @rmtoll CNT FL_BSTIM32_ReadCounter
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadCounter(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CNT, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM32_WritePrescaler
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param psc
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WritePrescaler(BSTIM32_Type *BSTIM32x, uint32_t psc)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->PSC, (0xffffffffU << 0U), (psc << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM32_ReadPrescaler
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadPrescaler(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->PSC, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM32_WriteAutoReload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param value
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WriteAutoReload(BSTIM32_Type *BSTIM32x, uint32_t value)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->ARR, (0xffffffffU << 0U), (value << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM32_ReadAutoReload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadAutoReload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->ARR, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM32_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_BSTIM32_DeInit(BSTIM32_Type *BSTIM32x);
|
||||
FL_ErrorStatus FL_BSTIM32_Init(BSTIM32_Type *BSTIM32x, FL_BSTIM32_InitTypeDef *init);
|
||||
void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *init);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_BSTIM32_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
2215
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_can.h
Normal file
2215
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_can.h
Normal file
File diff suppressed because it is too large
Load Diff
222
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_cdif.h
Normal file
222
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_cdif.h
Normal file
@ -0,0 +1,222 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_cdif.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of CDIF FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_CDIF_H
|
||||
#define __FM33LG0XX_FL_CDIF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CDIF CDIF
|
||||
* @brief CDIF FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup CDIF_FL_ES_INIT CDIF Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL CDIF Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CDIF_FL_Exported_Constants CDIF Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CDIF_CR_INTF_IEN_Pos (1U)
|
||||
#define CDIF_CR_INTF_IEN_Msk (0x1U << CDIF_CR_INTF_IEN_Pos)
|
||||
#define CDIF_CR_INTF_IEN CDIF_CR_INTF_IEN_Msk
|
||||
|
||||
#define CDIF_CR_INTF_OEN_Pos (0U)
|
||||
#define CDIF_CR_INTF_OEN_Msk (0x1U << CDIF_CR_INTF_OEN_Pos)
|
||||
#define CDIF_CR_INTF_OEN CDIF_CR_INTF_OEN_Msk
|
||||
|
||||
#define CDIF_PRSC_PRSC_Pos (0U)
|
||||
#define CDIF_PRSC_PRSC_Msk (0x7U << CDIF_PRSC_PRSC_Pos)
|
||||
#define CDIF_PRSC_PRSC CDIF_PRSC_PRSC_Msk
|
||||
|
||||
|
||||
|
||||
#define FL_CDIF_PSC_DIV1 (0x0U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV2 (0x1U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV4 (0x2U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV8 (0x3U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV16 (0x4U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV32 (0x5U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV64 (0x6U << CDIF_PRSC_PRSC_Pos)
|
||||
#define FL_CDIF_PSC_DIV128 (0x7U << CDIF_PRSC_PRSC_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CDIF_FL_Exported_Functions CDIF Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief VAO To CPU input enable
|
||||
* @rmtoll CR INTF_IEN FL_CDIF_EnableVAOToCPU
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CDIF_EnableVAOToCPU(CDIF_Type *CDIFx)
|
||||
{
|
||||
SET_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VAO To CPU input enable status
|
||||
* @rmtoll CR INTF_IEN FL_CDIF_IsEnabledVAOToCPU
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CDIF_IsEnabledVAOToCPU(CDIF_Type *CDIFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk) == CDIF_CR_INTF_IEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VAO To CPU input disable
|
||||
* @rmtoll CR INTF_IEN FL_CDIF_DisableVAOToCPU
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CDIF_DisableVAOToCPU(CDIF_Type *CDIFx)
|
||||
{
|
||||
CLEAR_BIT(CDIFx->CR, CDIF_CR_INTF_IEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CPU To VAO enable
|
||||
* @rmtoll CR INTF_OEN FL_CDIF_EnableCPUToVAO
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CDIF_EnableCPUToVAO(CDIF_Type *CDIFx)
|
||||
{
|
||||
SET_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CPU To VAO output enable status
|
||||
* @rmtoll CR INTF_OEN FL_CDIF_IsEnabledCPUToVAO
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CDIF_IsEnabledCPUToVAO(CDIF_Type *CDIFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk) == CDIF_CR_INTF_OEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CPU To VAO output disable
|
||||
* @rmtoll CR INTF_OEN FL_CDIF_DisableCPUToVAO
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CDIF_DisableCPUToVAO(CDIF_Type *CDIFx)
|
||||
{
|
||||
CLEAR_BIT(CDIFx->CR, CDIF_CR_INTF_OEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CDIF prescaler
|
||||
* @rmtoll PRSC PRSC FL_CDIF_SetPrescaler
|
||||
* @param CDIFx CDIF instance
|
||||
* @param psc This parameter can be one of the following values:
|
||||
* @arg @ref FL_CDIF_PSC_DIV1
|
||||
* @arg @ref FL_CDIF_PSC_DIV2
|
||||
* @arg @ref FL_CDIF_PSC_DIV4
|
||||
* @arg @ref FL_CDIF_PSC_DIV8
|
||||
* @arg @ref FL_CDIF_PSC_DIV16
|
||||
* @arg @ref FL_CDIF_PSC_DIV32
|
||||
* @arg @ref FL_CDIF_PSC_DIV64
|
||||
* @arg @ref FL_CDIF_PSC_DIV128
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CDIF_SetPrescaler(CDIF_Type *CDIFx, uint32_t psc)
|
||||
{
|
||||
MODIFY_REG(CDIFx->PRSC, CDIF_PRSC_PRSC_Msk, psc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CDIF prescaler
|
||||
* @rmtoll PRSC PRSC FL_CDIF_GetPrescaler
|
||||
* @param CDIFx CDIF instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CDIF_PSC_DIV1
|
||||
* @arg @ref FL_CDIF_PSC_DIV2
|
||||
* @arg @ref FL_CDIF_PSC_DIV4
|
||||
* @arg @ref FL_CDIF_PSC_DIV8
|
||||
* @arg @ref FL_CDIF_PSC_DIV16
|
||||
* @arg @ref FL_CDIF_PSC_DIV32
|
||||
* @arg @ref FL_CDIF_PSC_DIV64
|
||||
* @arg @ref FL_CDIF_PSC_DIV128
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CDIF_GetPrescaler(CDIF_Type *CDIFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CDIFx->PRSC, CDIF_PRSC_PRSC_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CDIF_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_CDIF_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-11*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
2285
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_cmu.h
Normal file
2285
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_cmu.h
Normal file
File diff suppressed because it is too large
Load Diff
1110
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_comp.h
Normal file
1110
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_comp.h
Normal file
File diff suppressed because it is too large
Load Diff
221
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_conf.h
Normal file
221
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_conf.h
Normal file
@ -0,0 +1,221 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_conf.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Driver Library Configurations
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion --------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_CONF_H
|
||||
#define __FM33LG0XX_FL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Defines -------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief List of drivers to be used.
|
||||
*
|
||||
* @note Uncomment following lines to disable specified driver.
|
||||
*/
|
||||
#define FL_ADC_DRIVER_ENABLED
|
||||
#define FL_AES_DRIVER_ENABLED
|
||||
#define FL_ATIM_DRIVER_ENABLED
|
||||
#define FL_BSTIM16_DRIVER_ENABLED
|
||||
#define FL_BSTIM32_DRIVER_ENABLED
|
||||
#define FL_CAN_DRIVER_ENABLED
|
||||
#define FL_CDIF_DRIVER_ENABLED
|
||||
#define FL_CMU_DRIVER_ENABLED
|
||||
#define FL_COMP_DRIVER_ENABLED
|
||||
#define FL_CRC_DRIVER_ENABLED
|
||||
#define FL_DAC_DRIVER_ENABLED
|
||||
#define FL_DIVAS_DRIVER_ENABLED
|
||||
#define FL_DMA_DRIVER_ENABLED
|
||||
#define FL_EXTI_DRIVER_ENABLED
|
||||
#define FL_FLASH_DRIVER_ENABLED
|
||||
#define FL_GPIO_DRIVER_ENABLED
|
||||
#define FL_GPTIM_DRIVER_ENABLED
|
||||
#define FL_I2C_DRIVER_ENABLED
|
||||
#define FL_IWDT_DRIVER_ENABLED
|
||||
#define FL_LCD_DRIVER_ENABLED
|
||||
#define FL_LPTIM16_DRIVER_ENABLED
|
||||
#define FL_LPTIM32_DRIVER_ENABLED
|
||||
#define FL_LPUART_DRIVER_ENABLED
|
||||
#define FL_PMU_DRIVER_ENABLED
|
||||
#define FL_RMU_DRIVER_ENABLED
|
||||
#define FL_RNG_DRIVER_ENABLED
|
||||
#define FL_RTCA_DRIVER_ENABLED
|
||||
#define FL_SPI_DRIVER_ENABLED
|
||||
#define FL_SVD_DRIVER_ENABLED
|
||||
#define FL_UART_DRIVER_ENABLED
|
||||
#define FL_VAO_DRIVER_ENABLED
|
||||
#define FL_VREF_DRIVER_ENABLED
|
||||
#define FL_VREFP_DRIVER_ENABLED
|
||||
#define FL_WWDT_DRIVER_ENABLED
|
||||
|
||||
/* Device Includes ------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include peripheral's header file
|
||||
*/
|
||||
|
||||
#if defined(FL_ADC_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_adc.h"
|
||||
#endif /* FL_ADC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_AES_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_aes.h"
|
||||
#endif /* FL_AES_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_ATIM_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_atim.h"
|
||||
#endif /* FL_ATIM_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_BSTIM16_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_bstim16.h"
|
||||
#endif /* FL_BSTIM16_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_BSTIM32_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_bstim32.h"
|
||||
#endif /* FL_BSTIM32_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_CAN_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_can.h"
|
||||
#endif /* FL_CAN_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_CDIF_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_cdif.h"
|
||||
#endif /* FL_CDIF_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_CMU_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_cmu.h"
|
||||
#endif /* FL_CMU_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_COMP_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_comp.h"
|
||||
#endif /* FL_COMP_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_CRC_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_crc.h"
|
||||
#endif /* FL_CRC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_DAC_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_dac.h"
|
||||
#endif /* FL_DAC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_DIVAS_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_divas.h"
|
||||
#endif /* FL_DIVAS_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_DMA_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_dma.h"
|
||||
#endif /* FL_DMA_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_EXTI_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_exti.h"
|
||||
#endif /* FL_EXTI_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_FLASH_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_flash.h"
|
||||
#endif /* FL_FLASH_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_GPIO_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_gpio.h"
|
||||
#endif /* FL_GPIO_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_GPTIM_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_gptim.h"
|
||||
#endif /* FL_GPTIM_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_I2C_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_i2c.h"
|
||||
#endif /* FL_I2C_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_IWDT_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_iwdt.h"
|
||||
#endif /* FL_IWDT_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LCD_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_lcd.h"
|
||||
#endif /* FL_LCD_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LPTIM16_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_lptim16.h"
|
||||
#endif /* FL_LPTIM16_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LPTIM32_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_lptim32.h"
|
||||
#endif /* FL_LPTIM32_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LPUART_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_lpuart.h"
|
||||
#endif /* FL_LPUART_DRIVER_ENABLED */
|
||||
|
||||
|
||||
#if defined(FL_PMU_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_pmu.h"
|
||||
#endif /* FL_PMU_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RMU_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_rmu.h"
|
||||
#endif /* FL_RMU_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RNG_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_rng.h"
|
||||
#endif /* FL_RNG_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RTCA_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_rtca.h"
|
||||
#endif /* FL_RTCA_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_SPI_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_spi.h"
|
||||
#endif /* FL_SPI_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_SVD_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_svd.h"
|
||||
#endif /* FL_SVD_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_UART_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_uart.h"
|
||||
#endif /* FL_UART_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_VAO_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_vao.h"
|
||||
#endif /* FL_VAO_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_VREF_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_vref.h"
|
||||
#endif /* FL_VREF_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_VREFP_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_vrefp.h"
|
||||
#endif /* FL_VREFP_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_WWDT_DRIVER_ENABLED)
|
||||
#include "fm33lg0xx_fl_wwdt.h"
|
||||
#endif /* FL_WWDT_DRIVER_ENABLED */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_CONF_H */
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
469
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_crc.h
Normal file
469
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_crc.h
Normal file
@ -0,0 +1,469 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_crc.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of CRC FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_CRC_H
|
||||
#define __FM33LG0XX_FL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_ES_INIT CRC Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL CRC Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! CRC初值 */
|
||||
uint32_t initVal;
|
||||
/*! 计算数据宽度 */
|
||||
uint32_t dataWidth;
|
||||
/*! 输入数据翻转 */
|
||||
uint32_t reflectIn;
|
||||
/*! 输出数据翻转 */
|
||||
uint32_t reflectOut;
|
||||
/*! 输出结果异或寄存器 */
|
||||
uint32_t xorReg;
|
||||
/*! 输出结果异或使能 */
|
||||
uint32_t xorRegState;
|
||||
/*! CRC多项式宽 */
|
||||
uint32_t polynomialWidth;
|
||||
/*! CRC多项式 */
|
||||
uint32_t polynomial;
|
||||
/*! 计算模式 串行或并行 */
|
||||
uint32_t calculatMode;
|
||||
|
||||
} FL_CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRC_CR_OPWD_Pos (9U)
|
||||
#define CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos)
|
||||
#define CRC_CR_OPWD CRC_CR_OPWD_Msk
|
||||
|
||||
#define CRC_CR_PARA_Pos (8U)
|
||||
#define CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos)
|
||||
#define CRC_CR_PARA CRC_CR_PARA_Msk
|
||||
|
||||
#define CRC_CR_RFLTIN_Pos (6U)
|
||||
#define CRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos)
|
||||
#define CRC_CR_RFLTIN CRC_CR_RFLTIN_Msk
|
||||
|
||||
#define CRC_CR_RFLTO_Pos (5U)
|
||||
#define CRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos)
|
||||
#define CRC_CR_RFLTO CRC_CR_RFLTO_Msk
|
||||
|
||||
#define CRC_CR_RES_Pos (4U)
|
||||
#define CRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos)
|
||||
#define CRC_CR_RES CRC_CR_RES_Msk
|
||||
|
||||
#define CRC_CR_BUSY_Pos (3U)
|
||||
#define CRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos)
|
||||
#define CRC_CR_BUSY CRC_CR_BUSY_Msk
|
||||
|
||||
#define CRC_CR_XOR_Pos (2U)
|
||||
#define CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos)
|
||||
#define CRC_CR_XOR CRC_CR_XOR_Msk
|
||||
|
||||
#define CRC_CR_SEL_Pos (0U)
|
||||
#define CRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos)
|
||||
#define CRC_CR_SEL CRC_CR_SEL_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_CRC_DATA_WIDTH_8B (0x0U << CRC_CR_OPWD_Pos)
|
||||
#define FL_CRC_DATA_WIDTH_32B (0x1U << CRC_CR_OPWD_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_CALCULATE_SERIAL (0x0U << CRC_CR_PARA_Pos)
|
||||
#define FL_CRC_CALCULATE_PARALLEL (0x1U << CRC_CR_PARA_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_INPUT_INVERT_NONE (0x0U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_HALF_WORD (0x2U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_WORD (0x3U << CRC_CR_RFLTIN_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_OUPUT_INVERT_NONE (0x0U << CRC_CR_RFLTO_Pos)
|
||||
#define FL_CRC_OUPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTO_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_POLYNOMIAL_32B (0x0U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_16B (0x1U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_8B (0x2U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_7B (0x3U << CRC_CR_SEL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC data register
|
||||
* @rmtoll DR FL_CRC_WriteData
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteData(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->DR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC data register value
|
||||
* @rmtoll DR FL_CRC_ReadData
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadData(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->DR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC calculate operation width
|
||||
* @rmtoll CR OPWD FL_CRC_SetDataWidth
|
||||
* @param CRCx CRC instance
|
||||
* @param dataWidth This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_8B
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_32B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetDataWidth(CRC_Type *CRCx, uint32_t dataWidth)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_OPWD_Msk, dataWidth);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC calculate operation width
|
||||
* @rmtoll CR OPWD FL_CRC_GetDataWidth
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_8B
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_32B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetDataWidth(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_OPWD_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC parallel calculation mode
|
||||
* @rmtoll CR PARA FL_CRC_SetCalculateMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_CALCULATE_SERIAL
|
||||
* @arg @ref FL_CRC_CALCULATE_PARALLEL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetCalculateMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_PARA_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC parallel calculation mode
|
||||
* @rmtoll CR PARA FL_CRC_GetCalculateMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_CALCULATE_SERIAL
|
||||
* @arg @ref FL_CRC_CALCULATE_PARALLEL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetCalculateMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_PARA_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC reflected input
|
||||
* @rmtoll CR RFLTIN FL_CRC_SetInputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_BYTE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_WORD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetInputInvertMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_RFLTIN_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC reflected input status
|
||||
* @rmtoll CR RFLTIN FL_CRC_GetInputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_BYTE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetInputInvertMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTIN_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC reflected output
|
||||
* @rmtoll CR RFLTO FL_CRC_SetOutputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_BYTE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetOutputInvertMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_RFLTO_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC feflected output status
|
||||
* @rmtoll CR RFLTO FL_CRC_GetOutputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_BYTE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetOutputInvertMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTO_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result flag
|
||||
* @rmtoll CR RES FL_CRC_IsActiveFlag_Zero
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Zero(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RES_Msk) == (CRC_CR_RES_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC operational flag
|
||||
* @rmtoll CR BUSY FL_CRC_IsActiveFlag_Busy
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Busy(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_BUSY_Msk) == (CRC_CR_BUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Output XORed with CRC_XOR register enable
|
||||
* @rmtoll CR XOR FL_CRC_EnableOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_EnableOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get output XORed with CRC_XOR register enable status
|
||||
* @rmtoll CR XOR FL_CRC_IsEnabledOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsEnabledOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_XOR_Msk) == CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Output XORed with CRC_XOR register disable
|
||||
* @rmtoll CR XOR FL_CRC_DisableOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_DisableOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
CLEAR_BIT(CRCx->CR, CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polynomial width selection
|
||||
* @rmtoll CR SEL FL_CRC_SetPolynomialWidth
|
||||
* @param CRCx CRC instance
|
||||
* @param width This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_32B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_16B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_8B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_7B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetPolynomialWidth(CRC_Type *CRCx, uint32_t width)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_SEL_Msk, width);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Polynomial width Selection status
|
||||
* @rmtoll CR SEL FL_CRC_GetPolynomialWidth
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_32B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_16B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_8B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetPolynomialWidth(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_SEL_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set linear feedback shift register
|
||||
* @rmtoll LFSR FL_CRC_WriteInitialValue
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteInitialValue(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->LFSR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get linear feedback shift register value
|
||||
* @rmtoll LFSR FL_CRC_ReadInitialValue
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadInitialValue(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->LFSR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set eXclusive XOR register
|
||||
* @rmtoll XOR FL_CRC_WriteXORValue
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteXORValue(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->XOR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get eXclusive XOR register value
|
||||
* @rmtoll XOR FL_CRC_ReadXORValue
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadXORValue(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->XOR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC Polynominals
|
||||
* @rmtoll POLY FL_CRC_WritePolynominalParam
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WritePolynominalParam(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->POLY, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC Polynominals
|
||||
* @rmtoll POLY FL_CRC_ReadPolynominalParam
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadPolynominalParam(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->POLY, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_CRC_DeInit(CRC_Type *CRCx);
|
||||
void FL_CRC_StructInit(FL_CRC_InitTypeDef *CRC_InitStruct);
|
||||
FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_CRC_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
752
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_dac.h
Normal file
752
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_dac.h
Normal file
@ -0,0 +1,752 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_dac.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of DAC FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_DAC_H
|
||||
#define __FM33LG0XX_FL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC DAC
|
||||
* @brief DAC FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DAC_FL_ES_INIT DAC Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL DAC Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*DAC触发模式使能配置*/
|
||||
uint32_t triggerMode;
|
||||
/*DAC触发源配置*/
|
||||
uint32_t triggerSource;
|
||||
/*DAC采样保持模式配置*/
|
||||
uint32_t sampleHoldMode;
|
||||
/*DAC保持时间配置*/
|
||||
uint32_t holdTime;
|
||||
/*DAC采样时间配置*/
|
||||
uint32_t sampleTime;
|
||||
/*DAC_Buffer模式配置*/
|
||||
uint32_t bufferMode;
|
||||
/*DAC反馈开关配置*/
|
||||
uint32_t switchMode;
|
||||
|
||||
|
||||
} FL_DAC_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DAC_FL_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_CR1_EN_Pos (0U)
|
||||
#define DAC_CR1_EN_Msk (0x1U << DAC_CR1_EN_Pos)
|
||||
#define DAC_CR1_EN DAC_CR1_EN_Msk
|
||||
|
||||
#define DAC_CR2_DMAEN_Pos (1U)
|
||||
#define DAC_CR2_DMAEN_Msk (0x1U << DAC_CR2_DMAEN_Pos)
|
||||
#define DAC_CR2_DMAEN DAC_CR2_DMAEN_Msk
|
||||
|
||||
#define DAC_CR2_TRGEN_Pos (0U)
|
||||
#define DAC_CR2_TRGEN_Msk (0x1U << DAC_CR2_TRGEN_Pos)
|
||||
#define DAC_CR2_TRGEN DAC_CR2_TRGEN_Msk
|
||||
|
||||
#define DAC_CFGR_SHEN_Pos (8U)
|
||||
#define DAC_CFGR_SHEN_Msk (0x1U << DAC_CFGR_SHEN_Pos)
|
||||
#define DAC_CFGR_SHEN DAC_CFGR_SHEN_Msk
|
||||
|
||||
#define DAC_CFGR_BUFEN_Pos (7U)
|
||||
#define DAC_CFGR_BUFEN_Msk (0x1U << DAC_CFGR_BUFEN_Pos)
|
||||
#define DAC_CFGR_BUFEN DAC_CFGR_BUFEN_Msk
|
||||
|
||||
#define DAC_CFGR_TRGSEL_Pos (2U)
|
||||
#define DAC_CFGR_TRGSEL_Msk (0xfU << DAC_CFGR_TRGSEL_Pos)
|
||||
#define DAC_CFGR_TRGSEL DAC_CFGR_TRGSEL_Msk
|
||||
|
||||
#define DAC_CFGR_SWIEN_Pos (0U)
|
||||
#define DAC_CFGR_SWIEN_Msk (0x1U << DAC_CFGR_SWIEN_Pos)
|
||||
#define DAC_CFGR_SWIEN DAC_CFGR_SWIEN_Msk
|
||||
|
||||
#define DAC_SWTRGR_SWTRIG_Pos (0U)
|
||||
#define DAC_SWTRGR_SWTRIG_Msk (0x1U << DAC_SWTRGR_SWTRIG_Pos)
|
||||
#define DAC_SWTRGR_SWTRIG DAC_SWTRGR_SWTRIG_Msk
|
||||
|
||||
#define DAC_DHR_DHR_Pos (0U)
|
||||
#define DAC_DHR_DHR_Msk (0xfffU << DAC_DHR_DHR_Pos)
|
||||
#define DAC_DHR_DHR DAC_DHR_DHR_Msk
|
||||
|
||||
#define DAC_IER_DMAE_IE_Pos (3U)
|
||||
#define DAC_IER_DMAE_IE_Msk (0x1U << DAC_IER_DMAE_IE_Pos)
|
||||
#define DAC_IER_DMAE_IE DAC_IER_DMAE_IE_Msk
|
||||
|
||||
#define DAC_IER_EOH_IE_Pos (2U)
|
||||
#define DAC_IER_EOH_IE_Msk (0x1U << DAC_IER_EOH_IE_Pos)
|
||||
#define DAC_IER_EOH_IE DAC_IER_EOH_IE_Msk
|
||||
|
||||
#define DAC_IER_EOS_IE_Pos (1U)
|
||||
#define DAC_IER_EOS_IE_Msk (0x1U << DAC_IER_EOS_IE_Pos)
|
||||
#define DAC_IER_EOS_IE DAC_IER_EOS_IE_Msk
|
||||
|
||||
#define DAC_IER_DOU_IE_Pos (0U)
|
||||
#define DAC_IER_DOU_IE_Msk (0x1U << DAC_IER_DOU_IE_Pos)
|
||||
#define DAC_IER_DOU_IE DAC_IER_DOU_IE_Msk
|
||||
|
||||
#define DAC_ISR_DMAERR_Pos (3U)
|
||||
#define DAC_ISR_DMAERR_Msk (0x1U << DAC_ISR_DMAERR_Pos)
|
||||
#define DAC_ISR_DMAERR DAC_ISR_DMAERR_Msk
|
||||
|
||||
#define DAC_ISR_EOH_Pos (2U)
|
||||
#define DAC_ISR_EOH_Msk (0x1U << DAC_ISR_EOH_Pos)
|
||||
#define DAC_ISR_EOH DAC_ISR_EOH_Msk
|
||||
|
||||
#define DAC_ISR_EOS_Pos (1U)
|
||||
#define DAC_ISR_EOS_Msk (0x1U << DAC_ISR_EOS_Pos)
|
||||
#define DAC_ISR_EOS DAC_ISR_EOS_Msk
|
||||
|
||||
#define DAC_ISR_DOU_Pos (0U)
|
||||
#define DAC_ISR_DOU_Msk (0x1U << DAC_ISR_DOU_Pos)
|
||||
#define DAC_ISR_DOU DAC_ISR_DOU_Msk
|
||||
|
||||
#define DAC_SHTR_THLD_Pos (8U)
|
||||
#define DAC_SHTR_THLD_Msk (0xffffU << DAC_SHTR_THLD_Pos)
|
||||
#define DAC_SHTR_THLD DAC_SHTR_THLD_Msk
|
||||
|
||||
#define DAC_SHTR_TSMPL_Pos (0U)
|
||||
#define DAC_SHTR_TSMPL_Msk (0xffU << DAC_SHTR_TSMPL_Pos)
|
||||
#define DAC_SHTR_TSMPL DAC_SHTR_TSMPL_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_DAC_TRGI_SOFTWARE (0x0U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_ATIM (0x1U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_GPTIM1 (0x2U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_GPTIM2 (0x3U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_BSTIM16 (0x4U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_LPTIM16 (0x5U << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_EXTI0 (0xcU << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_EXTI4 (0xdU << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_EXTI8 (0xeU << DAC_CFGR_TRGSEL_Pos)
|
||||
#define FL_DAC_TRGI_EXTI12 (0xfU << DAC_CFGR_TRGSEL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DAC_FL_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable DAC
|
||||
* @rmtoll CR1 EN FL_DAC_Enable
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_Enable(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CR1, DAC_CR1_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC
|
||||
* @rmtoll CR1 EN FL_DAC_Disable
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_Disable(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CR1, DAC_CR1_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Enable Status
|
||||
* @rmtoll CR1 EN FL_DAC_IsEnabled
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabled(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR1, DAC_CR1_EN_Msk) == DAC_CR1_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC DMA
|
||||
* @rmtoll CR2 DMAEN FL_DAC_EnableDMAReq
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableDMAReq(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CR2, DAC_CR2_DMAEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC DMA
|
||||
* @rmtoll CR2 DMAEN FL_DAC_DisableDMAReq
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableDMAReq(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CR2, DAC_CR2_DMAEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC DMA Enable Status
|
||||
* @rmtoll CR2 DMAEN FL_DAC_IsEnabledDMAReq
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledDMAReq(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR2, DAC_CR2_DMAEN_Msk) == DAC_CR2_DMAEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC Trigger
|
||||
* @rmtoll CR2 TRGEN FL_DAC_EnableTriggerMode
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableTriggerMode(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CR2, DAC_CR2_TRGEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC Trigger
|
||||
* @rmtoll CR2 TRGEN FL_DAC_DisableTriggerMode
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableTriggerMode(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CR2, DAC_CR2_TRGEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Trigger Enable Status
|
||||
* @rmtoll CR2 TRGEN FL_DAC_IsEnabledTriggerMode
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledTriggerMode(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR2, DAC_CR2_TRGEN_Msk) == DAC_CR2_TRGEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC Sample Hold
|
||||
* @rmtoll CFGR SHEN FL_DAC_EnableSampleHoldMode
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableSampleHoldMode(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CFGR, DAC_CFGR_SHEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC Sample Hold
|
||||
* @rmtoll CFGR SHEN FL_DAC_DisableSampleHoldMode
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableSampleHoldMode(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CFGR, DAC_CFGR_SHEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Sample Hold Enable Status
|
||||
* @rmtoll CFGR SHEN FL_DAC_IsEnabledSampleHoldMode
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledSampleHoldMode(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CFGR, DAC_CFGR_SHEN_Msk) == DAC_CFGR_SHEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC Output Buffer
|
||||
* @rmtoll CFGR BUFEN FL_DAC_EnableOutputBuffer
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableOutputBuffer(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CFGR, DAC_CFGR_BUFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC Output Buffer
|
||||
* @rmtoll CFGR BUFEN FL_DAC_DisableOutputBuffer
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableOutputBuffer(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CFGR, DAC_CFGR_BUFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Output Buffer Status
|
||||
* @rmtoll CFGR BUFEN FL_DAC_IsEnabledOutputBuffer
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledOutputBuffer(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CFGR, DAC_CFGR_BUFEN_Msk) == DAC_CFGR_BUFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set DAC Trigger Source
|
||||
* @note Can Only Be Modified When TRGEN=0
|
||||
* @rmtoll CFGR TRGSEL FL_DAC_SetTriggerSource
|
||||
* @param DACx DAC instance
|
||||
* @param source This parameter can be one of the following values:
|
||||
* @arg @ref FL_DAC_TRGI_SOFTWARE
|
||||
* @arg @ref FL_DAC_TRGI_ATIM
|
||||
* @arg @ref FL_DAC_TRGI_GPTIM1
|
||||
* @arg @ref FL_DAC_TRGI_GPTIM2
|
||||
* @arg @ref FL_DAC_TRGI_BSTIM16
|
||||
* @arg @ref FL_DAC_TRGI_LPTIM16
|
||||
* @arg @ref FL_DAC_TRGI_EXTI0
|
||||
* @arg @ref FL_DAC_TRGI_EXTI4
|
||||
* @arg @ref FL_DAC_TRGI_EXTI8
|
||||
* @arg @ref FL_DAC_TRGI_EXTI12
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_SetTriggerSource(DAC_Type *DACx, uint32_t source)
|
||||
{
|
||||
MODIFY_REG(DACx->CFGR, DAC_CFGR_TRGSEL_Msk, source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Trigger Source
|
||||
* @rmtoll CFGR TRGSEL FL_DAC_GetTriggerSource
|
||||
* @param DACx DAC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_DAC_TRGI_SOFTWARE
|
||||
* @arg @ref FL_DAC_TRGI_ATIM
|
||||
* @arg @ref FL_DAC_TRGI_GPTIM1
|
||||
* @arg @ref FL_DAC_TRGI_GPTIM2
|
||||
* @arg @ref FL_DAC_TRGI_BSTIM16
|
||||
* @arg @ref FL_DAC_TRGI_LPTIM16
|
||||
* @arg @ref FL_DAC_TRGI_EXTI0
|
||||
* @arg @ref FL_DAC_TRGI_EXTI4
|
||||
* @arg @ref FL_DAC_TRGI_EXTI8
|
||||
* @arg @ref FL_DAC_TRGI_EXTI12
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_GetTriggerSource(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CFGR, DAC_CFGR_TRGSEL_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC DAC Feedback Switch
|
||||
* @rmtoll CFGR SWIEN FL_DAC_EnableFeedbackSwitch
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableFeedbackSwitch(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->CFGR, DAC_CFGR_SWIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC DAC Feedback Switch
|
||||
* @rmtoll CFGR SWIEN FL_DAC_DisableFeedbackSwitch
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableFeedbackSwitch(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->CFGR, DAC_CFGR_SWIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Feedback Switch
|
||||
* @rmtoll CFGR SWIEN FL_DAC_IsEnabledFeedbackSwitch
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledFeedbackSwitch(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CFGR, DAC_CFGR_SWIEN_Msk) == DAC_CFGR_SWIEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trigger DAC
|
||||
* @rmtoll SWTRGR SWTRIG FL_DAC_EnableSoftwareTrigger
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableSoftwareTrigger(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->SWTRGR, DAC_SWTRGR_SWTRIG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write DAC Data
|
||||
* @rmtoll DHR DHR FL_DAC_WriteData
|
||||
* @param DACx DAC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_WriteData(DAC_Type *DACx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(DACx->DHR, (0xfffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read DAC Data
|
||||
* @rmtoll DHR DHR FL_DAC_ReadData
|
||||
* @param DACx DAC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_ReadData(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->DHR, 0xfffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC DMA Error interrupt
|
||||
* @rmtoll IER DMAE_IE FL_DAC_EnableIT_DMAError
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableIT_DMAError(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->IER, DAC_IER_DMAE_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC DMA Error interrupt
|
||||
* @rmtoll IER DMAE_IE FL_DAC_DisableIT_DMAError
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableIT_DMAError(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->IER, DAC_IER_DMAE_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC DMA Error interrupt Enable Status
|
||||
* @rmtoll IER DMAE_IE FL_DAC_IsEnabledIT_DMAError
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledIT_DMAError(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->IER, DAC_IER_DMAE_IE_Msk) == DAC_IER_DMAE_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC End Of Holding Phase Interrupt
|
||||
* @rmtoll IER EOH_IE FL_DAC_EnableIT_EndOfHolding
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableIT_EndOfHolding(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->IER, DAC_IER_EOH_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC End Of Holding Phase Interrupt
|
||||
* @rmtoll IER EOH_IE FL_DAC_DisableIT_EndOfHolding
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableIT_EndOfHolding(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->IER, DAC_IER_EOH_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC End Of Holding Phase Interrupt Enable Status
|
||||
* @rmtoll IER EOH_IE FL_DAC_IsEnabledIT_EndOfHolding
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledIT_EndOfHolding(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->IER, DAC_IER_EOH_IE_Msk) == DAC_IER_EOH_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC End Of Sampling Phase Interrupt
|
||||
* @rmtoll IER EOS_IE FL_DAC_EnableIT_EndOfSampling
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableIT_EndOfSampling(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->IER, DAC_IER_EOS_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC End Of Sampling Phase Interrupt
|
||||
* @rmtoll IER EOS_IE FL_DAC_DisableIT_EndOfSampling
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableIT_EndOfSampling(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->IER, DAC_IER_EOS_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC End Of Sampling Phase Interrupt Enable Status
|
||||
* @rmtoll IER EOS_IE FL_DAC_IsEnabledIT_EndOfSampling
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledIT_EndOfSampling(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->IER, DAC_IER_EOS_IE_Msk) == DAC_IER_EOS_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DAC Data Output Updated Interrupt
|
||||
* @rmtoll IER DOU_IE FL_DAC_EnableIT_DataOutputUpdate
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_EnableIT_DataOutputUpdate(DAC_Type *DACx)
|
||||
{
|
||||
SET_BIT(DACx->IER, DAC_IER_DOU_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DAC Data Output Updated Interrupt
|
||||
* @rmtoll IER DOU_IE FL_DAC_DisableIT_DataOutputUpdate
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_DisableIT_DataOutputUpdate(DAC_Type *DACx)
|
||||
{
|
||||
CLEAR_BIT(DACx->IER, DAC_IER_DOU_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Data Output Updated Interrupt Enable Status
|
||||
* @rmtoll IER DOU_IE FL_DAC_IsEnabledIT_DataOutputUpdate
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsEnabledIT_DataOutputUpdate(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->IER, DAC_IER_DOU_IE_Msk) == DAC_IER_DOU_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC DMA Error Flag
|
||||
* @rmtoll ISR DMAERR FL_DAC_IsActiveFlag_DMAError
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsActiveFlag_DMAError(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->ISR, DAC_ISR_DMAERR_Msk) == (DAC_ISR_DMAERR_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DAC DMA Error Flag
|
||||
* @rmtoll ISR DMAERR FL_DAC_ClearFlag_DMAError
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_ClearFlag_DMAError(DAC_Type *DACx)
|
||||
{
|
||||
WRITE_REG(DACx->ISR, DAC_ISR_DMAERR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC End Of Holding Phase Flag
|
||||
* @rmtoll ISR EOH FL_DAC_IsActiveFlag_EndOfHolding
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsActiveFlag_EndOfHolding(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->ISR, DAC_ISR_EOH_Msk) == (DAC_ISR_EOH_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DAC End Of Holding Phase Flag
|
||||
* @rmtoll ISR EOH FL_DAC_ClearFlag_EndOfHolding
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_ClearFlag_EndOfHolding(DAC_Type *DACx)
|
||||
{
|
||||
WRITE_REG(DACx->ISR, DAC_ISR_EOH_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC End Of Sampling Phase Flag
|
||||
* @rmtoll ISR EOS FL_DAC_IsActiveFlag_EndOfSampling
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsActiveFlag_EndOfSampling(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->ISR, DAC_ISR_EOS_Msk) == (DAC_ISR_EOS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DAC End Of Sampling Phase Flag
|
||||
* @rmtoll ISR EOS FL_DAC_ClearFlag_EndOfSampling
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_ClearFlag_EndOfSampling(DAC_Type *DACx)
|
||||
{
|
||||
WRITE_REG(DACx->ISR, DAC_ISR_EOS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DAC Data Output Updated Flag
|
||||
* @rmtoll ISR DOU FL_DAC_IsActiveFlag_DataOutputUpdate
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_IsActiveFlag_DataOutputUpdate(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->ISR, DAC_ISR_DOU_Msk) == (DAC_ISR_DOU_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DAC Data Output Updated Flag
|
||||
* @rmtoll ISR DOU FL_DAC_ClearFlag_DataOutputUpdate
|
||||
* @param DACx DAC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_ClearFlag_DataOutputUpdate(DAC_Type *DACx)
|
||||
{
|
||||
WRITE_REG(DACx->ISR, DAC_ISR_DOU_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set DAC Holding Time
|
||||
* @note Modification IS NOT ALLOWED When SHEN=1
|
||||
* @rmtoll SHTR THLD FL_DAC_WriteHoldingTime
|
||||
* @param DACx DAC instance
|
||||
* @param time
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_WriteHoldingTime(DAC_Type *DACx, uint32_t time)
|
||||
{
|
||||
MODIFY_REG(DACx->SHTR, (0xffffU << 8U), (time << 8U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read DAC Holding Time
|
||||
* @rmtoll SHTR THLD FL_DAC_ReadHoldingTime
|
||||
* @param DACx DAC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_ReadHoldingTime(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->SHTR, 0xffffU) >> 8U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set DAC Sampling Time Under Sample&Hold Mode
|
||||
* @note Modification IS NOT ALLOWED When SHEN=1
|
||||
* @rmtoll SHTR TSMPL FL_DAC_WriteSamplingTime
|
||||
* @param DACx DAC instance
|
||||
* @param time
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DAC_WriteSamplingTime(DAC_Type *DACx, uint32_t time)
|
||||
{
|
||||
MODIFY_REG(DACx->SHTR, (0xffU << 0U), (time << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read DAC Sampling Time Under Sample&Hold Mode
|
||||
* @rmtoll SHTR TSMPL FL_DAC_ReadSamplingTime
|
||||
* @param DACx DAC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DAC_ReadSamplingTime(DAC_Type *DACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->SHTR, 0xffU) >> 0U);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_DAC_DeInit(DAC_Type *DACx);
|
||||
FL_ErrorStatus FL_DAC_Init(DAC_Type *DACx, FL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
void FL_DAC_StructInit(FL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_DAC_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
92
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_def.h
Normal file
92
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_def.h
Normal file
@ -0,0 +1,92 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_def.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Driver Library Defines
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion --------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_DEF_H
|
||||
#define __FM33LG0XX_FL_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx.h"
|
||||
#include "fm33_assert.h"
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/* Macros ---------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_Exported_Macros FL Driver Library Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Bit-wise operation macros used by FL driver library functions
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
#define READ_REG(REG) ((REG))
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Types ----------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_PT_Return FL Driver Library Private Return Type Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_RESET = 0U,
|
||||
FL_SET = !FL_RESET
|
||||
} FL_FlagStatus, FL_ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_DISABLE = 0U,
|
||||
FL_ENABLE = !FL_DISABLE
|
||||
} FL_FunState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FL_DISABLE) || ((STATE) == FL_ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_FAIL = 0U,
|
||||
FL_PASS = !FL_FAIL
|
||||
} FL_ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_DEF_H */
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
247
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_divas.h
Normal file
247
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_divas.h
Normal file
@ -0,0 +1,247 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_divas.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of DIVAS FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_DIVAS_H
|
||||
#define __FM33LG0XX_FL_DIVAS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DIVAS DIVAS
|
||||
* @brief DIVAS FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_ES_INIT DIVAS Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL DIVAS Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_Exported_Constants DIVAS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define FL_DIVAS_SR_BUSY_TIMEOUT (0xFFFU)
|
||||
|
||||
#define DIVAS_SR_DIV0_Pos (1U)
|
||||
#define DIVAS_SR_DIV0_Msk (0x1U << DIVAS_SR_DIV0_Pos)
|
||||
#define DIVAS_SR_DIV0 DIVAS_SR_DIV0_Msk
|
||||
|
||||
#define DIVAS_SR_BUSY_Pos (0U)
|
||||
#define DIVAS_SR_BUSY_Msk (0x1U << DIVAS_SR_BUSY_Pos)
|
||||
#define DIVAS_SR_BUSY DIVAS_SR_BUSY_Msk
|
||||
|
||||
#define DIVAS_CR_MODE_Pos (0U)
|
||||
#define DIVAS_CR_MODE_Msk (0x1U << DIVAS_CR_MODE_Pos)
|
||||
#define DIVAS_CR_MODE DIVAS_CR_MODE_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_DIVAS_MODE_DIV (0x0U << DIVAS_CR_MODE_Pos)
|
||||
#define FL_DIVAS_MODE_ROOT (0x1U << DIVAS_CR_MODE_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_Exported_Functions DIVAS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write Operator Register
|
||||
* @rmtoll OPRD FL_DIVAS_WriteOperand
|
||||
* @param DIVASx DIVAS instance
|
||||
* @param number
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DIVAS_WriteOperand(DIVAS_Type *DIVASx, uint32_t number)
|
||||
{
|
||||
WRITE_REG(DIVASx->OPRD,(number << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read Operator Register
|
||||
* @rmtoll OPRD FL_DIVAS_ReadOperand
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIVAS_ReadOperand(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (int32_t)(READ_BIT(DIVASx->OPRD, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write 16bit Signed Dividend
|
||||
* @rmtoll DIVSOR FL_DIVAS_WriteDivisor
|
||||
* @param DIVASx DIVAS instance
|
||||
* @param number
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DIVAS_WriteDivisor(DIVAS_Type *DIVASx, uint32_t number)
|
||||
{
|
||||
MODIFY_REG(DIVASx->DIVSOR, (0xffffU << 0U), (number << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 16bit Signed Dividend
|
||||
* @rmtoll DIVSOR FL_DIVAS_ReadDivisor
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIVAS_ReadDivisor(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (int32_t)(READ_BIT(DIVASx->DIVSOR, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 32bit Signed QUTO
|
||||
* @rmtoll QUOT FL_DIVAS_ReadQuotient
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIVAS_ReadQuotient(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (int32_t)(READ_BIT(DIVASx->QUOT, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 16bit Signed Reminder
|
||||
* @rmtoll REMD FL_DIVAS_ReadResidue
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int16_t FL_DIVAS_ReadResidue(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (int16_t)(READ_BIT(DIVASx->REMD, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 16bit Unsigned Square Root
|
||||
* @rmtoll ROOT FL_DIVAS_ReadRoot
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint16_t FL_DIVAS_ReadRoot(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (uint16_t)(READ_BIT(DIVASx->ROOT, 0xffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get divided by 0 flag
|
||||
* @rmtoll SR DIV0 FL_DIVAS_IsActiveFlag_DividedZero
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DIVAS_IsActiveFlag_DividedZero(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVASx->SR, DIVAS_SR_DIV0_Msk) == (DIVAS_SR_DIV0_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Busy flag
|
||||
* @rmtoll SR BUSY FL_DIVAS_IsActiveFlag_Busy
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DIVAS_IsActiveFlag_Busy(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVASx->SR, DIVAS_SR_BUSY_Msk) == (DIVAS_SR_BUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Work Mode
|
||||
* @rmtoll CR MODE FL_DIVAS_SetMode
|
||||
* @param DIVASx DIVAS instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_DIVAS_MODE_DIV
|
||||
* @arg @ref FL_DIVAS_MODE_ROOT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DIVAS_SetMode(DIVAS_Type *DIVASx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(DIVASx->CR, DIVAS_CR_MODE_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Work Mode
|
||||
* @rmtoll CR MODE FL_DIVAS_GetMode
|
||||
* @param DIVASx DIVAS instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_DIVAS_MODE_DIV
|
||||
* @arg @ref FL_DIVAS_MODE_ROOT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DIVAS_GetMode(DIVAS_Type *DIVASx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVASx->CR, DIVAS_CR_MODE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DIVAS_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_DIVAS_DeInit(DIVAS_Type *DIVASx);
|
||||
FL_ErrorStatus FL_DIVAS_Init(DIVAS_Type *DIVASx);
|
||||
uint32_t FL_DIVAS_Hdiv_Calculation(DIVAS_Type *DIVASx, int32_t DivisorEnd, int16_t Divisor, int32_t *Quotient, int16_t *Residue);
|
||||
uint32_t FL_DIVAS_Root_Calculation(DIVAS_Type *DIVASx, uint32_t Root, uint16_t *Result);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_DIVAS_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1257
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_dma.h
Normal file
1257
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_dma.h
Normal file
File diff suppressed because it is too large
Load Diff
132
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_exti.h
Normal file
132
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_exti.h
Normal file
@ -0,0 +1,132 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_exti.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of EXTI FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_EXTI_H
|
||||
#define __FM33LG0XX_FL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_ES_INIT EXTI Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL EXTI Common Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! EXTI时钟源配置 */
|
||||
uint32_t clockSource;
|
||||
|
||||
} FL_EXTI_CommonInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FL EXTI Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! EXTI输入配置 */
|
||||
uint32_t input;
|
||||
|
||||
/*! EXTI触发边沿配置 */
|
||||
uint32_t triggerEdge;
|
||||
|
||||
/*! EXTI数字滤波配置 */
|
||||
uint32_t filter;
|
||||
|
||||
} FL_EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP0 (0x0U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP1 (0x1U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP2 (0x2U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP3 (0x3U << 0U)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_Exported_Functions EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_EXTI_CommonInit(FL_EXTI_CommonInitTypeDef *init);
|
||||
FL_ErrorStatus FL_EXTI_CommonDeinit(void);
|
||||
void FL_EXTI_CommonStructInit(FL_EXTI_CommonInitTypeDef *init);
|
||||
|
||||
FL_ErrorStatus FL_EXTI_Init(uint32_t extiLineX, FL_EXTI_InitTypeDef *init);
|
||||
FL_ErrorStatus FL_EXTI_DeInit(uint32_t extiLineX);
|
||||
void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *init);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_EXTI_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2021-03-16*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1020
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_flash.h
Normal file
1020
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_flash.h
Normal file
File diff suppressed because it is too large
Load Diff
2167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_gpio.h
Normal file
2167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_gpio.h
Normal file
File diff suppressed because it is too large
Load Diff
2963
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_gptim.h
Normal file
2963
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_gptim.h
Normal file
File diff suppressed because it is too large
Load Diff
1861
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_i2c.h
Normal file
1861
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_i2c.h
Normal file
File diff suppressed because it is too large
Load Diff
348
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_iwdt.h
Normal file
348
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_iwdt.h
Normal file
@ -0,0 +1,348 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_iwdt.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of IWDT FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_IWDT_H
|
||||
#define __FM33LG0XX_FL_IWDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDT IWDT
|
||||
* @brief IWDT FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup IWDT_FL_ES_INIT IWDT Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL IWDT Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 看门狗溢出时间 */
|
||||
uint32_t overflowPeriod;
|
||||
/* 清狗窗口 */
|
||||
uint32_t iwdtWindows;
|
||||
|
||||
} FL_IWDT_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup IWDT_FL_Exported_Constants IWDT Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDT_RELOAD_KEY (0x12345A5AUL)
|
||||
|
||||
#define IWDT_CR_FREEZE_Pos (11U)
|
||||
#define IWDT_CR_FREEZE_Msk (0x1U << IWDT_CR_FREEZE_Pos)
|
||||
#define IWDT_CR_FREEZE IWDT_CR_FREEZE_Msk
|
||||
|
||||
#define IWDT_CR_CFG_Pos (0U)
|
||||
#define IWDT_CR_CFG_Msk (0x7U << IWDT_CR_CFG_Pos)
|
||||
#define IWDT_CR_CFG IWDT_CR_CFG_Msk
|
||||
|
||||
#define IWDT_IER_IE_Pos (0U)
|
||||
#define IWDT_IER_IE_Msk (0x1U << IWDT_IER_IE_Pos)
|
||||
#define IWDT_IER_IE IWDT_IER_IE_Msk
|
||||
|
||||
#define IWDT_ISR_WINF_Pos (0U)
|
||||
#define IWDT_ISR_WINF_Msk (0x1U << IWDT_ISR_WINF_Pos)
|
||||
#define IWDT_ISR_WINF IWDT_ISR_WINF_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_IWDT_PERIOD_125MS (0x0U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_250MS (0x1U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_500MS (0x2U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_1000MS (0x3U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_2000MS (0x4U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_4000MS (0x5U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_8000MS (0x6U << IWDT_CR_CFG_Pos)
|
||||
#define FL_IWDT_PERIOD_16000MS (0x7U << IWDT_CR_CFG_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup IWDT_FL_Exported_Functions IWDT Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set IWDT service register
|
||||
* @rmtoll SERV FL_IWDT_ReloadCounter
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_ReloadCounter(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
IWDTx->SERV = IWDT_RELOAD_KEY;
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set freeze in sleep enable
|
||||
* @rmtoll CR FREEZE FL_IWDT_EnableFreezeWhileSleep
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_EnableFreezeWhileSleep(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
SET_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set freeze in sleep disable
|
||||
* @rmtoll CR FREEZE FL_IWDT_DisableFreezeWhileSleep
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_DisableFreezeWhileSleep(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
CLEAR_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get freeze in sleep enable status
|
||||
* @rmtoll CR FREEZE FL_IWDT_IsEnabledFreezeWhileSleep
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_IsEnabledFreezeWhileSleep(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk) == IWDT_CR_FREEZE_Msk);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set IWDT overflow period
|
||||
* @rmtoll CR CFG FL_IWDT_SetPeriod
|
||||
* @param IWDTx IWDT instance
|
||||
* @param period This parameter can be one of the following values:
|
||||
* @arg @ref FL_IWDT_PERIOD_125MS
|
||||
* @arg @ref FL_IWDT_PERIOD_250MS
|
||||
* @arg @ref FL_IWDT_PERIOD_500MS
|
||||
* @arg @ref FL_IWDT_PERIOD_1000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_2000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_4000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_8000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_16000MS
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_SetPeriod(IWDT_Type *IWDTx, uint32_t period)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
MODIFY_REG(IWDTx->CR, IWDT_CR_CFG_Msk, period);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT overflow period
|
||||
* @rmtoll CR CFG FL_IWDT_GetPeriod
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_IWDT_PERIOD_125MS
|
||||
* @arg @ref FL_IWDT_PERIOD_250MS
|
||||
* @arg @ref FL_IWDT_PERIOD_500MS
|
||||
* @arg @ref FL_IWDT_PERIOD_1000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_2000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_4000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_8000MS
|
||||
* @arg @ref FL_IWDT_PERIOD_16000MS
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_GetPeriod(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->CR, IWDT_CR_CFG_Msk));
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT current counter value
|
||||
* @rmtoll CNT FL_IWDT_ReadCounter
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_ReadCounter(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->CNT, (0xfffU << 0U)) >> 0U);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set IWDT window register
|
||||
* @rmtoll WIN FL_IWDT_WriteWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @param value
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_WriteWindow(IWDT_Type *IWDTx, uint32_t value)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
IWDTx->WIN = (value & 0xFFF);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT window register
|
||||
* @rmtoll WIN FL_IWDT_ReadWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_ReadWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->WIN, (0xfffU << 0U)) >> 0U);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief IWDT interrupt enable
|
||||
* @rmtoll IER IE FL_IWDT_EnableIT_EnterWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_EnableIT_EnterWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
IWDTx->IER = FL_ENABLE;
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief IWDT interrupt disable
|
||||
* @rmtoll IER IE FL_IWDT_DisableIT_EnterWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_DisableIT_EnterWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
IWDTx->IER = FL_DISABLE;
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT interrupt enable status
|
||||
* @rmtoll IER IE FL_IWDT_IsEnabledIT_EnterWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_IsEnabledIT_EnterWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->IER, IWDT_IER_IE_Msk) == IWDT_IER_IE_Msk);
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT window interrupt flag
|
||||
* @rmtoll ISR WINF FL_IWDT_IsActiveFlag_EnterWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_IWDT_IsActiveFlag_EnterWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
uint32_t temp;
|
||||
temp = (uint32_t)(READ_BIT(IWDTx->ISR, IWDT_ISR_WINF_Msk));
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear IWDT window interrupt flag
|
||||
* @rmtoll ISR WINF FL_IWDT_ClearFlag_EnterWindow
|
||||
* @param IWDTx IWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_IWDT_ClearFlag_EnterWindow(IWDT_Type *IWDTx)
|
||||
{
|
||||
volatile uint32_t val = 0;
|
||||
IWDTx->ISR = IWDT_ISR_WINF_Msk;
|
||||
val = READ_REG(IWDTx->SERV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDT_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_IWDT_DeInit(IWDT_Type *IWDTx);
|
||||
void FL_IWDT_StructInit(FL_IWDT_InitTypeDef *IWDT_InitStruct);
|
||||
FL_ErrorStatus FL_IWDT_Init(IWDT_Type *IWDTx, FL_IWDT_InitTypeDef *IWDT_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_IWDT_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1192
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lcd.h
Normal file
1192
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lcd.h
Normal file
File diff suppressed because it is too large
Load Diff
1319
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lptim16.h
Normal file
1319
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lptim16.h
Normal file
File diff suppressed because it is too large
Load Diff
1296
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lptim32.h
Normal file
1296
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lptim32.h
Normal file
File diff suppressed because it is too large
Load Diff
1128
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lpuart.h
Normal file
1128
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_lpuart.h
Normal file
File diff suppressed because it is too large
Load Diff
1017
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_pmu.h
Normal file
1017
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_pmu.h
Normal file
File diff suppressed because it is too large
Load Diff
758
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rmu.h
Normal file
758
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rmu.h
Normal file
@ -0,0 +1,758 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_rmu.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of RMU FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_RMU_H
|
||||
#define __FM33LG0XX_FL_RMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RMU RMU
|
||||
* @brief RMU FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup RMU_FL_ES_INIT RMU Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL RMU Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup RMU_FL_Exported_Constants RMU Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RMU_PDRCR_CFG_Pos (1U)
|
||||
#define RMU_PDRCR_CFG_Msk (0x3U << RMU_PDRCR_CFG_Pos)
|
||||
#define RMU_PDRCR_CFG RMU_PDRCR_CFG_Msk
|
||||
|
||||
#define RMU_PDRCR_EN_Pos (0U)
|
||||
#define RMU_PDRCR_EN_Msk (0x1U << RMU_PDRCR_EN_Pos)
|
||||
#define RMU_PDRCR_EN RMU_PDRCR_EN_Msk
|
||||
|
||||
#define RMU_BORCR_CFG_Pos (2U)
|
||||
#define RMU_BORCR_CFG_Msk (0x3U << RMU_BORCR_CFG_Pos)
|
||||
#define RMU_BORCR_CFG RMU_BORCR_CFG_Msk
|
||||
|
||||
#define RMU_BORCR_ENB_Pos (0U)
|
||||
#define RMU_BORCR_ENB_Msk (0x1U << RMU_BORCR_ENB_Pos)
|
||||
#define RMU_BORCR_ENB RMU_BORCR_ENB_Msk
|
||||
|
||||
#define RMU_LKPCR_EN_Pos (1U)
|
||||
#define RMU_LKPCR_EN_Msk (0x1U << RMU_LKPCR_EN_Pos)
|
||||
#define RMU_LKPCR_EN RMU_LKPCR_EN_Msk
|
||||
|
||||
#define RMU_RSTFR_MDFN_FLAG_Pos (12U)
|
||||
#define RMU_RSTFR_MDFN_FLAG_Msk (0x1U << RMU_RSTFR_MDFN_FLAG_Pos)
|
||||
#define RMU_RSTFR_MDFN_FLAG RMU_RSTFR_MDFN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_NRSTN_FLAG_Pos (11U)
|
||||
#define RMU_RSTFR_NRSTN_FLAG_Msk (0x1U << RMU_RSTFR_NRSTN_FLAG_Pos)
|
||||
#define RMU_RSTFR_NRSTN_FLAG RMU_RSTFR_NRSTN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_PRC_FLAG_Pos (10U)
|
||||
#define RMU_RSTFR_PRC_FLAG_Msk (0x1U << RMU_RSTFR_PRC_FLAG_Pos)
|
||||
#define RMU_RSTFR_PRC_FLAG RMU_RSTFR_PRC_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_PORN_FLAG_Pos (9U)
|
||||
#define RMU_RSTFR_PORN_FLAG_Msk (0x1U << RMU_RSTFR_PORN_FLAG_Pos)
|
||||
#define RMU_RSTFR_PORN_FLAG RMU_RSTFR_PORN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_PDRN_FLAG_Pos (8U)
|
||||
#define RMU_RSTFR_PDRN_FLAG_Msk (0x1U << RMU_RSTFR_PDRN_FLAG_Pos)
|
||||
#define RMU_RSTFR_PDRN_FLAG RMU_RSTFR_PDRN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_SOFTN_FLAG_Pos (5U)
|
||||
#define RMU_RSTFR_SOFTN_FLAG_Msk (0x1U << RMU_RSTFR_SOFTN_FLAG_Pos)
|
||||
#define RMU_RSTFR_SOFTN_FLAG RMU_RSTFR_SOFTN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_IWDTN_FLAG_Pos (4U)
|
||||
#define RMU_RSTFR_IWDTN_FLAG_Msk (0x1U << RMU_RSTFR_IWDTN_FLAG_Pos)
|
||||
#define RMU_RSTFR_IWDTN_FLAG RMU_RSTFR_IWDTN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_WWDTN_FLAG_Pos (2U)
|
||||
#define RMU_RSTFR_WWDTN_FLAG_Msk (0x1U << RMU_RSTFR_WWDTN_FLAG_Pos)
|
||||
#define RMU_RSTFR_WWDTN_FLAG RMU_RSTFR_WWDTN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_LKUPN_FLAG_Pos (1U)
|
||||
#define RMU_RSTFR_LKUPN_FLAG_Msk (0x1U << RMU_RSTFR_LKUPN_FLAG_Pos)
|
||||
#define RMU_RSTFR_LKUPN_FLAG RMU_RSTFR_LKUPN_FLAG_Msk
|
||||
|
||||
#define RMU_RSTFR_NVICN_FLAG_Pos (0U)
|
||||
#define RMU_RSTFR_NVICN_FLAG_Msk (0x1U << RMU_RSTFR_NVICN_FLAG_Pos)
|
||||
#define RMU_RSTFR_NVICN_FLAG RMU_RSTFR_NVICN_FLAG_Msk
|
||||
|
||||
#define PERHRSTEN_KEY (0x13579BDFUL)
|
||||
#define SOFTWARERESET_KEY (0x5C5CAABBUL)
|
||||
|
||||
#define FL_RMU_RSTAHB_DMA (0x1U << 0U)
|
||||
#define FL_RMU_RSTAPB_UART5 (0x1fU << 0U)
|
||||
#define FL_RMU_RSTAPB_UART4 (0x1eU << 0U)
|
||||
#define FL_RMU_RSTAPB_UART3 (0x1dU << 0U)
|
||||
#define FL_RMU_RSTAPB_UART1 (0x1bU << 0U)
|
||||
#define FL_RMU_RSTAPB_UART0 (0x1aU << 0U)
|
||||
#define FL_RMU_RSTAPB_UCIR (0x19U << 0U)
|
||||
#define FL_RMU_RSTAPB_U7816 (0x18U << 0U)
|
||||
#define FL_RMU_RSTAPB_GPTIM2 (0x17U << 0U)
|
||||
#define FL_RMU_RSTAPB_GPTIM1 (0x16U << 0U)
|
||||
#define FL_RMU_RSTAPB_GPTIM0 (0x15U << 0U)
|
||||
#define FL_RMU_RSTAPB_ATIM (0x14U << 0U)
|
||||
#define FL_RMU_RSTAPB_BSTIM32 (0x13U << 0U)
|
||||
#define FL_RMU_RSTAPB_BSTIM16 (0x12U << 0U)
|
||||
#define FL_RMU_RSTAPB_SPI2 (0xfU << 0U)
|
||||
#define FL_RMU_RSTAPB_SPI1 (0xeU << 0U)
|
||||
#define FL_RMU_RSTAPB_SPI0 (0xdU << 0U)
|
||||
#define FL_RMU_RSTAPB_I2C (0xbU << 0U)
|
||||
#define FL_RMU_RSTAPB_LPUART2 (0xaU << 0U)
|
||||
#define FL_RMU_RSTAPB_LPUART1 (0x9U << 0U)
|
||||
#define FL_RMU_RSTAPB_LPUART0 (0x8U << 0U)
|
||||
#define FL_RMU_RSTAPB_VREF (0x6U << 0U)
|
||||
#define FL_RMU_RSTAPB_PGL (0x5U << 0U)
|
||||
#define FL_RMU_RSTAPB_LCD (0x4U << 0U)
|
||||
#define FL_RMU_RSTAPB_DAC (0x3U << 0U)
|
||||
#define FL_RMU_RSTAPB_OPA (0x2U << 0U)
|
||||
#define FL_RMU_RSTAPB_LPTIM16 (0x1U << 0U)
|
||||
#define FL_RMU_RSTAPB_LPTIM32 (0x0U << 0U)
|
||||
#define FL_RMU_RSTAPB_ADCCR (0x38U << 0U)
|
||||
#define FL_RMU_RSTAPB_ADC (0x37U << 0U)
|
||||
#define FL_RMU_RSTAPB_AES (0x32U << 0U)
|
||||
#define FL_RMU_RSTAPB_CRC (0x31U << 0U)
|
||||
#define FL_RMU_RSTAPB_RNG (0x30U << 0U)
|
||||
#define FL_RMU_RSTAPB_DIVAS (0x23U << 0U)
|
||||
#define FL_RMU_RSTAPB_CAN (0x22U << 0U)
|
||||
#define FL_RMU_RSTAPB_SVD (0x21U << 0U)
|
||||
#define FL_RMU_RSTAPB_COMP (0x20U << 0U)
|
||||
|
||||
|
||||
|
||||
#define FL_RMU_PDR_THRESHOLD_1P40V (0x0U << RMU_PDRCR_CFG_Pos)
|
||||
#define FL_RMU_PDR_THRESHOLD_1P45V (0x1U << RMU_PDRCR_CFG_Pos)
|
||||
#define FL_RMU_PDR_THRESHOLD_1P50V (0x2U << RMU_PDRCR_CFG_Pos)
|
||||
#define FL_RMU_PDR_THRESHOLD_1P55V (0x3U << RMU_PDRCR_CFG_Pos)
|
||||
|
||||
|
||||
#define FL_RMU_BOR_THRESHOLD_1P80V (0x0U << RMU_BORCR_CFG_Pos)
|
||||
#define FL_RMU_BOR_THRESHOLD_2P00V (0x1U << RMU_BORCR_CFG_Pos)
|
||||
#define FL_RMU_BOR_THRESHOLD_2P20V (0x2U << RMU_BORCR_CFG_Pos)
|
||||
#define FL_RMU_BOR_THRESHOLD_2P40V (0x3U << RMU_BORCR_CFG_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup RMU_FL_Exported_Functions RMU Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set Power Down Reset Voltage
|
||||
* @rmtoll PDRCR CFG FL_RMU_PDR_SetThreshold
|
||||
* @param RMUx RMU instance
|
||||
* @param threshold This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P40V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P45V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P50V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P55V
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_PDR_SetThreshold(RMU_Type *RMUx, uint32_t threshold)
|
||||
{
|
||||
MODIFY_REG(RMUx->PDRCR, RMU_PDRCR_CFG_Msk, threshold);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down Reset Voltage Setting
|
||||
* @rmtoll PDRCR CFG FL_RMU_PDR_GetThreshold
|
||||
* @param RMUx RMU instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P40V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P45V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P50V
|
||||
* @arg @ref FL_RMU_PDR_THRESHOLD_1P55V
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_PDR_GetThreshold(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->PDRCR, RMU_PDRCR_CFG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down Reset Enable Status
|
||||
* @rmtoll PDRCR EN FL_RMU_PDR_IsEnabled
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_PDR_IsEnabled(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk) == RMU_PDRCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Down Reset
|
||||
* @rmtoll PDRCR EN FL_RMU_PDR_Disable
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_PDR_Disable(RMU_Type *RMUx)
|
||||
{
|
||||
CLEAR_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Down Reset
|
||||
* @rmtoll PDRCR EN FL_RMU_PDR_Enable
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_PDR_Enable(RMU_Type *RMUx)
|
||||
{
|
||||
SET_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Brown Out Reset Voltage
|
||||
* @rmtoll BORCR CFG FL_RMU_BOR_SetThreshold
|
||||
* @param RMUx RMU instance
|
||||
* @param threshold This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_1P80V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P00V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P20V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P40V
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_BOR_SetThreshold(RMU_Type *RMUx, uint32_t threshold)
|
||||
{
|
||||
MODIFY_REG(RMUx->BORCR, RMU_BORCR_CFG_Msk, threshold);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Brown Out Reset Setting
|
||||
* @rmtoll BORCR CFG FL_RMU_BOR_GetThreshold
|
||||
* @param RMUx RMU instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_1P80V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P00V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P20V
|
||||
* @arg @ref FL_RMU_BOR_THRESHOLD_2P40V
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_BOR_GetThreshold(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->BORCR, RMU_BORCR_CFG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Brown Out Reset Enable Status
|
||||
* @rmtoll BORCR ENB FL_RMU_BOR_IsEnabled
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_BOR_IsEnabled(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)!(READ_BIT(RMUx->BORCR, RMU_BORCR_ENB_Msk) == RMU_BORCR_ENB_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Brown Out Reset
|
||||
* @rmtoll BORCR ENB FL_RMU_BOR_Disable
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_BOR_Disable(RMU_Type *RMUx)
|
||||
{
|
||||
SET_BIT(RMUx->BORCR, RMU_BORCR_ENB_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Brown Out Reset
|
||||
* @rmtoll BORCR ENB FL_RMU_BOR_Enable
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_BOR_Enable(RMU_Type *RMUx)
|
||||
{
|
||||
CLEAR_BIT(RMUx->BORCR, RMU_BORCR_ENB_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LockUp Reset Enable Status
|
||||
* @rmtoll LKPCR EN FL_RMU_IsEnabledLockUpReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsEnabledLockUpReset(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->LKPCR, RMU_LKPCR_EN_Msk) == RMU_LKPCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LockUp Reset
|
||||
* @rmtoll LKPCR EN FL_RMU_DisableLockUpReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_DisableLockUpReset(RMU_Type *RMUx)
|
||||
{
|
||||
CLEAR_BIT(RMUx->LKPCR, RMU_LKPCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LockUp Reset
|
||||
* @rmtoll LKPCR EN FL_RMU_EnableLockUpReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_EnableLockUpReset(RMU_Type *RMUx)
|
||||
{
|
||||
SET_BIT(RMUx->LKPCR, RMU_LKPCR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Soft Reset Chip
|
||||
* @rmtoll SOFTRST FL_RMU_SetSoftReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_SetSoftReset(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->SOFTRST, SOFTWARERESET_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MDF Reset Flag
|
||||
* @rmtoll RSTFR MDFN_FLAG FL_RMU_IsActiveFlag_MDF
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_MDF(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_MDFN_FLAG_Msk) == (RMU_RSTFR_MDFN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear MDF Reset Flag
|
||||
* @rmtoll RSTFR MDFN_FLAG FL_RMU_ClearFlag_MDF
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_MDF(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_MDFN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get NRST Reset Flag
|
||||
* @rmtoll RSTFR NRSTN_FLAG FL_RMU_IsActiveFlag_NRSTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_NRSTN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_NRSTN_FLAG_Msk) == (RMU_RSTFR_NRSTN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear NRST Reset Flag
|
||||
* @rmtoll RSTFR NRSTN_FLAG FL_RMU_ClearFlag_NRSTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_NRSTN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_NRSTN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PRC Reset Flag
|
||||
* @rmtoll RSTFR PRC_FLAG FL_RMU_IsActiveFlag_PRCN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_PRCN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_PRC_FLAG_Msk) == (RMU_RSTFR_PRC_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear PRC Reset Flag
|
||||
* @rmtoll RSTFR PRC_FLAG FL_RMU_ClearFlag_PRCN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_PRCN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_PRC_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power On Reset Flag
|
||||
* @rmtoll RSTFR PORN_FLAG FL_RMU_IsActiveFlag_PORN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_PORN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_PORN_FLAG_Msk) == (RMU_RSTFR_PORN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Power On Reset Flag
|
||||
* @rmtoll RSTFR PORN_FLAG FL_RMU_ClearFlag_PORN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_PORN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_PORN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down Reset Flag
|
||||
* @rmtoll RSTFR PDRN_FLAG FL_RMU_IsActiveFlag_PDRN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_PDRN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_PDRN_FLAG_Msk) == (RMU_RSTFR_PDRN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Power Down Reset Flag
|
||||
* @rmtoll RSTFR PDRN_FLAG FL_RMU_ClearFlag_PDRN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_PDRN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_PDRN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Software Reset Flag
|
||||
* @rmtoll RSTFR SOFTN_FLAG FL_RMU_IsActiveFlag_SOFTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_SOFTN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_SOFTN_FLAG_Msk) == (RMU_RSTFR_SOFTN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Software Reset Flag
|
||||
* @rmtoll RSTFR SOFTN_FLAG FL_RMU_ClearFlag_SOFTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_SOFTN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_SOFTN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IWDT Reset Flag
|
||||
* @rmtoll RSTFR IWDTN_FLAG FL_RMU_IsActiveFlag_IWDTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_IWDTN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_IWDTN_FLAG_Msk) == (RMU_RSTFR_IWDTN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear IWDT Reset Flag
|
||||
* @rmtoll RSTFR IWDTN_FLAG FL_RMU_ClearFlag_IWDTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_IWDTN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_IWDTN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Reset Flag
|
||||
* @rmtoll RSTFR WWDTN_FLAG FL_RMU_IsActiveFlag_WWDTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_WWDTN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_WWDTN_FLAG_Msk) == (RMU_RSTFR_WWDTN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT Reset Flag
|
||||
* @rmtoll RSTFR WWDTN_FLAG FL_RMU_ClearFlag_WWDTN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_WWDTN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_WWDTN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LockUp Reset Flag
|
||||
* @rmtoll RSTFR LKUPN_FLAG FL_RMU_IsActiveFlag_LKUPN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_LKUPN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_LKUPN_FLAG_Msk) == (RMU_RSTFR_LKUPN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear LockUp Reset Flag
|
||||
* @rmtoll RSTFR LKUPN_FLAG FL_RMU_ClearFlag_LKUPN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_LKUPN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_LKUPN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get NVIC Reset Flag
|
||||
* @rmtoll RSTFR NVICN_FLAG FL_RMU_IsActiveFlag_NVICN
|
||||
* @param RMUx RMU instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RMU_IsActiveFlag_NVICN(RMU_Type *RMUx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RMUx->RSTFR, RMU_RSTFR_NVICN_FLAG_Msk) == (RMU_RSTFR_NVICN_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear NVIC Reset Flag
|
||||
* @rmtoll RSTFR NVICN_FLAG FL_RMU_ClearFlag_NVICN
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_ClearFlag_NVICN(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->RSTFR, RMU_RSTFR_NVICN_FLAG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Peripheral Reset
|
||||
* @rmtoll PRSTEN FL_RMU_DisablePeripheralReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_DisablePeripheralReset(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->PRSTEN, (~PERHRSTEN_KEY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Peripheral Reset
|
||||
* @rmtoll PRSTEN FL_RMU_EnablePeripheralReset
|
||||
* @param RMUx RMU instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_EnablePeripheralReset(RMU_Type *RMUx)
|
||||
{
|
||||
WRITE_REG(RMUx->PRSTEN, PERHRSTEN_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable AHB Peripheral Reset
|
||||
* @rmtoll AHBRSTCR FL_RMU_EnableResetAHBPeripheral
|
||||
* @param RMUx RMU instance
|
||||
* @param peripheral This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_RSTAHB_DMA
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_EnableResetAHBPeripheral(RMU_Type *RMUx, uint32_t peripheral)
|
||||
{
|
||||
SET_BIT(RMUx->AHBRSTCR, ((peripheral & 0xffffffff) << 0x0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable APB Peripheral Reset1
|
||||
* @rmtoll APBRSTCR FL_RMU_EnableResetAPBPeripheral
|
||||
* @param RMUx RMU instance
|
||||
* @param peripheral This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_RSTAPB_UART5
|
||||
* @arg @ref FL_RMU_RSTAPB_UART4
|
||||
* @arg @ref FL_RMU_RSTAPB_UART3
|
||||
* @arg @ref FL_RMU_RSTAPB_UART1
|
||||
* @arg @ref FL_RMU_RSTAPB_UART0
|
||||
* @arg @ref FL_RMU_RSTAPB_UCIR
|
||||
* @arg @ref FL_RMU_RSTAPB_U7816
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM2
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM1
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM0
|
||||
* @arg @ref FL_RMU_RSTAPB_ATIM
|
||||
* @arg @ref FL_RMU_RSTAPB_BSTIM32
|
||||
* @arg @ref FL_RMU_RSTAPB_BSTIM16
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI2
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI1
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI0
|
||||
* @arg @ref FL_RMU_RSTAPB_I2C
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART2
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART1
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART0
|
||||
* @arg @ref FL_RMU_RSTAPB_VREF
|
||||
* @arg @ref FL_RMU_RSTAPB_PGL
|
||||
* @arg @ref FL_RMU_RSTAPB_LCD
|
||||
* @arg @ref FL_RMU_RSTAPB_DAC
|
||||
* @arg @ref FL_RMU_RSTAPB_OPA
|
||||
* @arg @ref FL_RMU_RSTAPB_LPTIM16
|
||||
* @arg @ref FL_RMU_RSTAPB_LPTIM32
|
||||
* @arg @ref FL_RMU_RSTAPB_ADCCR
|
||||
* @arg @ref FL_RMU_RSTAPB_ADC
|
||||
* @arg @ref FL_RMU_RSTAPB_AES
|
||||
* @arg @ref FL_RMU_RSTAPB_CRC
|
||||
* @arg @ref FL_RMU_RSTAPB_RNG
|
||||
* @arg @ref FL_RMU_RSTAPB_DIVAS
|
||||
* @arg @ref FL_RMU_RSTAPB_CAN
|
||||
* @arg @ref FL_RMU_RSTAPB_SVD
|
||||
* @arg @ref FL_RMU_RSTAPB_COMP
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_EnableResetAPBPeripheral(RMU_Type *RMUx, uint32_t peripheral)
|
||||
{
|
||||
if(peripheral < FL_RMU_RSTAPB_COMP)
|
||||
{
|
||||
SET_BIT(RMUx->APBRSTCR1, (0x1U << peripheral));
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_BIT(RMUx->APBRSTCR2, (0x1U << (peripheral - 32)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable AHB Peripheral Reset
|
||||
* @rmtoll AHBRSTCR FL_RMU_DisableResetAHBPeripheral
|
||||
* @param RMUx RMU instance
|
||||
* @param peripheral This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_RSTAHB_DMA
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_DisableResetAHBPeripheral(RMU_Type *RMUx, uint32_t peripheral)
|
||||
{
|
||||
CLEAR_BIT(RMUx->AHBRSTCR, ((peripheral & 0xffffffff) << 0x0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable APB Peripheral Reset1
|
||||
* @rmtoll APBRSTCR FL_RMU_DisableResetAPBPeripheral
|
||||
* @param RMUx RMU instance
|
||||
* @param peripheral This parameter can be one of the following values:
|
||||
* @arg @ref FL_RMU_RSTAPB_UART5
|
||||
* @arg @ref FL_RMU_RSTAPB_UART4
|
||||
* @arg @ref FL_RMU_RSTAPB_UART3
|
||||
* @arg @ref FL_RMU_RSTAPB_UART1
|
||||
* @arg @ref FL_RMU_RSTAPB_UART0
|
||||
* @arg @ref FL_RMU_RSTAPB_UCIR
|
||||
* @arg @ref FL_RMU_RSTAPB_U7816
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM2
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM1
|
||||
* @arg @ref FL_RMU_RSTAPB_GPTIM0
|
||||
* @arg @ref FL_RMU_RSTAPB_ATIM
|
||||
* @arg @ref FL_RMU_RSTAPB_BSTIM32
|
||||
* @arg @ref FL_RMU_RSTAPB_BSTIM16
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI2
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI1
|
||||
* @arg @ref FL_RMU_RSTAPB_SPI0
|
||||
* @arg @ref FL_RMU_RSTAPB_I2C
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART2
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART1
|
||||
* @arg @ref FL_RMU_RSTAPB_LPUART0
|
||||
* @arg @ref FL_RMU_RSTAPB_VREF
|
||||
* @arg @ref FL_RMU_RSTAPB_PGL
|
||||
* @arg @ref FL_RMU_RSTAPB_LCD
|
||||
* @arg @ref FL_RMU_RSTAPB_DAC
|
||||
* @arg @ref FL_RMU_RSTAPB_OPA
|
||||
* @arg @ref FL_RMU_RSTAPB_LPTIM16
|
||||
* @arg @ref FL_RMU_RSTAPB_LPTIM32
|
||||
* @arg @ref FL_RMU_RSTAPB_ADCCR
|
||||
* @arg @ref FL_RMU_RSTAPB_ADC
|
||||
* @arg @ref FL_RMU_RSTAPB_AES
|
||||
* @arg @ref FL_RMU_RSTAPB_CRC
|
||||
* @arg @ref FL_RMU_RSTAPB_RNG
|
||||
* @arg @ref FL_RMU_RSTAPB_DIVAS
|
||||
* @arg @ref FL_RMU_RSTAPB_CAN
|
||||
* @arg @ref FL_RMU_RSTAPB_SVD
|
||||
* @arg @ref FL_RMU_RSTAPB_COMP
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RMU_DisableResetAPBPeripheral(RMU_Type *RMUx, uint32_t peripheral)
|
||||
{
|
||||
if(peripheral < FL_RMU_RSTAPB_COMP)
|
||||
{
|
||||
CLEAR_BIT(RMUx->APBRSTCR1, (0x1U << peripheral));
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(RMUx->APBRSTCR2, (0x1U << (peripheral - 32)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RMU_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_RMU_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.14-0.1 @ 2020-10-20*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
255
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rng.h
Normal file
255
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rng.h
Normal file
@ -0,0 +1,255 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_rng.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of RNG FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_RNG_H
|
||||
#define __FM33LG0XX_FL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup RNG_FL_ES_INIT RNG Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL RNG Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup RNG_FL_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RNG_CR_EN_Pos (0U)
|
||||
#define RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos)
|
||||
#define RNG_CR_EN RNG_CR_EN_Msk
|
||||
|
||||
#define RNG_SR_RBUSY_Pos (1U)
|
||||
#define RNG_SR_RBUSY_Msk (0x1U << RNG_SR_RBUSY_Pos)
|
||||
#define RNG_SR_RBUSY RNG_SR_RBUSY_Msk
|
||||
|
||||
#define RNG_SR_RNF_Pos (0U)
|
||||
#define RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos)
|
||||
#define RNG_SR_RNF RNG_SR_RNF_Msk
|
||||
|
||||
#define RNG_CRCCR_CRCEN_Pos (0U)
|
||||
#define RNG_CRCCR_CRCEN_Msk (0x1U << RNG_CRCCR_CRCEN_Pos)
|
||||
#define RNG_CRCCR_CRCEN RNG_CRCCR_CRCEN_Msk
|
||||
|
||||
#define RNG_CRCSR_CRCDONE_Pos (0U)
|
||||
#define RNG_CRCSR_CRCDONE_Msk (0x1U << RNG_CRCSR_CRCDONE_Pos)
|
||||
#define RNG_CRCSR_CRCDONE RNG_CRCSR_CRCDONE_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup RNG_FL_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RNG enable
|
||||
* @rmtoll CR EN FL_RNG_Enable
|
||||
* @param RNGx RNG instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_Enable(RNG_Type *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RNG enable status
|
||||
* @rmtoll CR EN FL_RNG_IsEnabled
|
||||
* @param RNGx RNG instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_IsEnabled(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_EN_Msk) == RNG_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RNG disable
|
||||
* @rmtoll CR EN FL_RNG_Disable
|
||||
* @param RNGx RNG instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_Disable(RNG_Type *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read RNG output data register
|
||||
* @rmtoll DOR FL_RNG_ReadData
|
||||
* @param RNGx RNG instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_ReadData(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->DOR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LFSR Flag
|
||||
* @rmtoll SR RBUSY FL_RNG_IsActiveFlag_Busy
|
||||
* @param RNGx RNG instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_Busy(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->SR, RNG_SR_RBUSY_Msk) == (RNG_SR_RBUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get random number fail flag
|
||||
* @rmtoll SR RNF FL_RNG_IsActiveFlag_RandomFail
|
||||
* @param RNGx RNG instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_RandomFail(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->SR, RNG_SR_RNF_Msk) == (RNG_SR_RNF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear random number fail flag
|
||||
* @rmtoll SR RNF FL_RNG_ClearFlag_RandomFail
|
||||
* @param RNGx RNG instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_ClearFlag_RandomFail(RNG_Type *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, RNG_SR_RNF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CRC enable
|
||||
* @rmtoll CRCCR CRCEN FL_RNG_CRC_Enable
|
||||
* @param RNGx RNG instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_CRC_Enable(RNG_Type *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CRCCR, RNG_CRCCR_CRCEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC enable status
|
||||
* @rmtoll CRCCR CRCEN FL_RNG_CRC_IsEnabled
|
||||
* @param RNGx RNG instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_CRC_IsEnabled(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CRCCR, RNG_CRCCR_CRCEN_Msk) == RNG_CRCCR_CRCEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write CRC data input
|
||||
* @rmtoll CRCDIR FL_RNG_CRC_WriteData
|
||||
* @param RNGx RNG instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_CRC_WriteData(RNG_Type *RNGx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(RNGx->CRCDIR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC calculation done Flag
|
||||
* @rmtoll CRCSR CRCDONE FL_RNG_IsActiveFlag_CRCComplete
|
||||
* @param RNGx RNG instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_CRCComplete(RNG_Type *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CRCSR, RNG_CRCSR_CRCDONE_Msk) == (RNG_CRCSR_CRCDONE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear CRC calculation done Flag
|
||||
* @rmtoll CRCSR CRCDONE FL_RNG_ClearFlag_CRCComplete
|
||||
* @param RNGx RNG instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_RNG_ClearFlag_CRCComplete(RNG_Type *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CRCSR, RNG_CRCSR_CRCDONE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_RNG_DeInit(RNG_Type *RNGx);
|
||||
FL_ErrorStatus FL_RNG_Init(RNG_Type *RNGx);
|
||||
uint32_t GetRandomNumber(void);
|
||||
uint32_t GetCrc32(uint32_t dataIn);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_RNG_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1374
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rtca.h
Normal file
1374
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_rtca.h
Normal file
File diff suppressed because it is too large
Load Diff
1251
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_spi.h
Normal file
1251
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_spi.h
Normal file
File diff suppressed because it is too large
Load Diff
606
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_svd.h
Normal file
606
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_svd.h
Normal file
@ -0,0 +1,606 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_svd.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of SVD FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_SVD_H
|
||||
#define __FM33LG0XX_FL_SVD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SVD SVD
|
||||
* @brief SVD FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup SVD_FL_ES_INIT SVD Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL SVD Init Sturcture definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* 参考电压 */
|
||||
uint32_t referenceVoltage;
|
||||
|
||||
/* 报警阈值 */
|
||||
uint32_t warningThreshold;
|
||||
|
||||
/* 数字滤波 */
|
||||
uint32_t digitalFilter;
|
||||
|
||||
/* 工作模式 */
|
||||
uint32_t workMode;
|
||||
|
||||
/* 间歇使能间隔 */
|
||||
uint32_t enablePeriod;
|
||||
|
||||
/* SVS通道选择 */
|
||||
uint32_t SVSChannel;
|
||||
|
||||
} FL_SVD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup SVD_FL_Exported_Constants SVD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SVD_CFGR_LVL_Pos (4U)
|
||||
#define SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos)
|
||||
#define SVD_CFGR_LVL SVD_CFGR_LVL_Msk
|
||||
|
||||
#define SVD_CFGR_DFEN_Pos (3U)
|
||||
#define SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos)
|
||||
#define SVD_CFGR_DFEN SVD_CFGR_DFEN_Msk
|
||||
|
||||
#define SVD_CFGR_MOD_Pos (2U)
|
||||
#define SVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos)
|
||||
#define SVD_CFGR_MOD SVD_CFGR_MOD_Msk
|
||||
|
||||
#define SVD_CFGR_ITVL_Pos (0U)
|
||||
#define SVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos)
|
||||
#define SVD_CFGR_ITVL SVD_CFGR_ITVL_Msk
|
||||
|
||||
#define SVD_CR_SVS0EN_Pos (1U)
|
||||
#define SVD_CR_SVS0EN_Msk (0x1U << SVD_CR_SVS0EN_Pos)
|
||||
#define SVD_CR_SVS0EN SVD_CR_SVS0EN_Msk
|
||||
|
||||
#define SVD_CR_EN_Pos (0U)
|
||||
#define SVD_CR_EN_Msk (0x1U << SVD_CR_EN_Pos)
|
||||
#define SVD_CR_EN SVD_CR_EN_Msk
|
||||
|
||||
#define SVD_IER_PFIE_Pos (1U)
|
||||
#define SVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos)
|
||||
#define SVD_IER_PFIE SVD_IER_PFIE_Msk
|
||||
|
||||
#define SVD_IER_PRIE_Pos (0U)
|
||||
#define SVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos)
|
||||
#define SVD_IER_PRIE SVD_IER_PRIE_Msk
|
||||
|
||||
#define SVD_ISR_SVDO_Pos (8U)
|
||||
#define SVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos)
|
||||
#define SVD_ISR_SVDO SVD_ISR_SVDO_Msk
|
||||
|
||||
#define SVD_ISR_SVDR_Pos (7U)
|
||||
#define SVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos)
|
||||
#define SVD_ISR_SVDR SVD_ISR_SVDR_Msk
|
||||
|
||||
#define SVD_ISR_PFF_Pos (1U)
|
||||
#define SVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos)
|
||||
#define SVD_ISR_PFF SVD_ISR_PFF_Msk
|
||||
|
||||
#define SVD_ISR_PRF_Pos (0U)
|
||||
#define SVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos)
|
||||
#define SVD_ISR_PRF SVD_ISR_PRF_Msk
|
||||
|
||||
#define SVD_VSR_EN_Pos (0U)
|
||||
#define SVD_VSR_EN_Msk (0x7U << SVD_VSR_EN_Pos)
|
||||
#define SVD_VSR_EN SVD_VSR_EN_Msk
|
||||
|
||||
|
||||
|
||||
#define FL_SVD_REFERENCE_1P0V (0x1U << 2U)
|
||||
#define FL_SVD_REFERENCE_0P95V (0x1U << 1U)
|
||||
#define FL_SVD_REFERENCE_0P9V (0x1U << 0U)
|
||||
|
||||
|
||||
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP0 (0x0U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP1 (0x1U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP2 (0x2U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP3 (0x3U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP4 (0x4U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP5 (0x5U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP6 (0x6U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP7 (0x7U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP8 (0x8U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP9 (0x9U << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP10 (0xaU << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP11 (0xbU << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP12 (0xcU << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP13 (0xdU << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP14 (0xeU << SVD_CFGR_LVL_Pos)
|
||||
#define FL_SVD_WARNING_THRESHOLD_GROUP15 (0xfU << SVD_CFGR_LVL_Pos)
|
||||
|
||||
|
||||
#define FL_SVD_WORK_MODE_CONTINUOUS (0x0U << SVD_CFGR_MOD_Pos)
|
||||
#define FL_SVD_WORK_MODE_PERIODIC (0x1U << SVD_CFGR_MOD_Pos)
|
||||
|
||||
|
||||
#define FL_SVD_ENABLE_PERIOD_62P5MS (0x0U << SVD_CFGR_ITVL_Pos)
|
||||
#define FL_SVD_ENABLE_PERIOD_256MS (0x1U << SVD_CFGR_ITVL_Pos)
|
||||
#define FL_SVD_ENABLE_PERIOD_1000MS (0x2U << SVD_CFGR_ITVL_Pos)
|
||||
#define FL_SVD_ENABLE_PERIOD_4000MS (0x3U << SVD_CFGR_ITVL_Pos)
|
||||
|
||||
|
||||
#define FL_SVD_POWER_STATUS_FALLING (0x0U << SVD_ISR_SVDO_Pos)
|
||||
#define FL_SVD_POWER_STATUS_RISING (0x1U << SVD_ISR_SVDO_Pos)
|
||||
|
||||
#define FL_SVD_LATCHED_POWER_STATUS_FALLING (0x0U << SVD_ISR_SVDR_Pos)
|
||||
#define FL_SVD_LATCHED_POWER_STATUS_RISING (0x1U << SVD_ISR_SVDR_Pos)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup SVD_FL_Exported_Functions SVD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set SVD Threshold Warning Level
|
||||
* @rmtoll CFGR LVL FL_SVD_SetWarningThreshold
|
||||
* @param SVDx SVD instance
|
||||
* @param level This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP0
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP1
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP2
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP3
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP4
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP5
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP6
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP7
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP8
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP9
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP10
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP11
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP12
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP13
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP14
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP15
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_SetWarningThreshold(SVD_Type *SVDx, uint32_t level)
|
||||
{
|
||||
MODIFY_REG(SVDx->CFGR, SVD_CFGR_LVL_Msk, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Warning Threshold Level
|
||||
* @rmtoll CFGR LVL FL_SVD_GetWarningThreshold
|
||||
* @param SVDx SVD instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP0
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP1
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP2
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP3
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP4
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP5
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP6
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP7
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP8
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP9
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP10
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP11
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP12
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP13
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP14
|
||||
* @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP15
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_GetWarningThreshold(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_LVL_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SVD Digital Filter
|
||||
* @rmtoll CFGR DFEN FL_SVD_EnableDigitalFilter
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_EnableDigitalFilter(SVD_Type *SVDx)
|
||||
{
|
||||
SET_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Digital Filter Enable Status
|
||||
* @rmtoll CFGR DFEN FL_SVD_IsEnabledDigitalFilter
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabledDigitalFilter(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk) == SVD_CFGR_DFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SVD Digital Filter
|
||||
* @rmtoll CFGR DFEN FL_SVD_DisableDigitalFilter
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_DisableDigitalFilter(SVD_Type *SVDx)
|
||||
{
|
||||
CLEAR_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SVD Work Mode
|
||||
* @rmtoll CFGR MOD FL_SVD_SetWorkMode
|
||||
* @param SVDx SVD instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_WORK_MODE_CONTINUOUS
|
||||
* @arg @ref FL_SVD_WORK_MODE_PERIODIC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_SetWorkMode(SVD_Type *SVDx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(SVDx->CFGR, SVD_CFGR_MOD_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Work Mode
|
||||
* @rmtoll CFGR MOD FL_SVD_GetWorkMode
|
||||
* @param SVDx SVD instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_SVD_WORK_MODE_CONTINUOUS
|
||||
* @arg @ref FL_SVD_WORK_MODE_PERIODIC
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_GetWorkMode(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_MOD_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SVD Enable Period
|
||||
* @rmtoll CFGR ITVL FL_SVD_SetEnablePeriod
|
||||
* @param SVDx SVD instance
|
||||
* @param period This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_62P5MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_256MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_1000MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_4000MS
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_SetEnablePeriod(SVD_Type *SVDx, uint32_t period)
|
||||
{
|
||||
MODIFY_REG(SVDx->CFGR, SVD_CFGR_ITVL_Msk, period);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Work Interval
|
||||
* @rmtoll CFGR ITVL FL_SVD_GetEnablePeriod
|
||||
* @param SVDx SVD instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_62P5MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_256MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_1000MS
|
||||
* @arg @ref FL_SVD_ENABLE_PERIOD_4000MS
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_GetEnablePeriod(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_ITVL_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable External SVS Channel
|
||||
* @rmtoll CR SVS0EN FL_SVD_EnableSVSChannel
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_EnableSVSChannel(SVD_Type *SVDx)
|
||||
{
|
||||
SET_BIT(SVDx->CR, SVD_CR_SVS0EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get External SVS Channel Enable Status
|
||||
* @rmtoll CR SVS0EN FL_SVD_IsEnabledSVSChannel
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabledSVSChannel(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CR, SVD_CR_SVS0EN_Msk) == SVD_CR_SVS0EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable External SVS Channel
|
||||
* @rmtoll CR SVS0EN FL_SVD_DisableSVSChannel
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_DisableSVSChannel(SVD_Type *SVDx)
|
||||
{
|
||||
CLEAR_BIT(SVDx->CR, SVD_CR_SVS0EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SVD
|
||||
* @rmtoll CR EN FL_SVD_Enable
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_Enable(SVD_Type *SVDx)
|
||||
{
|
||||
SET_BIT(SVDx->CR, SVD_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Enable Status
|
||||
* @rmtoll CR EN FL_SVD_IsEnabled
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabled(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->CR, SVD_CR_EN_Msk) == SVD_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SVD
|
||||
* @rmtoll CR EN FL_SVD_Disable
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_Disable(SVD_Type *SVDx)
|
||||
{
|
||||
CLEAR_BIT(SVDx->CR, SVD_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Fall Interrupt
|
||||
* @rmtoll IER PFIE FL_SVD_EnableIT_PowerFall
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_EnableIT_PowerFall(SVD_Type *SVDx)
|
||||
{
|
||||
SET_BIT(SVDx->IER, SVD_IER_PFIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Fall Interrupt Status
|
||||
* @rmtoll IER PFIE FL_SVD_IsEnabledIT_PowerFall
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabledIT_PowerFall(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->IER, SVD_IER_PFIE_Msk) == SVD_IER_PFIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Fall Interrupt
|
||||
* @rmtoll IER PFIE FL_SVD_DisableIT_PowerFall
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_DisableIT_PowerFall(SVD_Type *SVDx)
|
||||
{
|
||||
CLEAR_BIT(SVDx->IER, SVD_IER_PFIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Rise Interrupt
|
||||
* @rmtoll IER PRIE FL_SVD_EnableIT_PowerRise
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_EnableIT_PowerRise(SVD_Type *SVDx)
|
||||
{
|
||||
SET_BIT(SVDx->IER, SVD_IER_PRIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Rise Interrupt Status
|
||||
* @rmtoll IER PRIE FL_SVD_IsEnabledIT_PowerRise
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabledIT_PowerRise(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->IER, SVD_IER_PRIE_Msk) == SVD_IER_PRIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Rise Interrupt
|
||||
* @rmtoll IER PRIE FL_SVD_DisableIT_PowerRise
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_DisableIT_PowerRise(SVD_Type *SVDx)
|
||||
{
|
||||
CLEAR_BIT(SVDx->IER, SVD_IER_PRIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Current Power Status
|
||||
* @rmtoll ISR SVDO FL_SVD_GetCurrentPowerStatus
|
||||
* @param SVDx SVD instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_SVD_POWER_STATUS_FALLING
|
||||
* @arg @ref FL_SVD_POWER_STATUS_RISING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_GetCurrentPowerStatus(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_SVDO_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Latched Power Status
|
||||
* @rmtoll ISR SVDR FL_SVD_GetLatchedPowerStatus
|
||||
* @param SVDx SVD instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_SVD_LATCHED_POWER_STATUS_FALLING
|
||||
* @arg @ref FL_SVD_LATCHED_POWER_STATUS_RISING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_GetLatchedPowerStatus(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_SVDR_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Power Fall Flag
|
||||
* @rmtoll ISR PFF FL_SVD_IsActiveFlag_PowerFall
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsActiveFlag_PowerFall(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_PFF_Msk) == (SVD_ISR_PFF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear SVD Power Fall Flag
|
||||
* @rmtoll ISR PFF FL_SVD_ClearFlag_PowerFall
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_ClearFlag_PowerFall(SVD_Type *SVDx)
|
||||
{
|
||||
WRITE_REG(SVDx->ISR, SVD_ISR_PFF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Power Rise Flag
|
||||
* @rmtoll ISR PRF FL_SVD_IsActiveFlag_PowerRise
|
||||
* @param SVDx SVD instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsActiveFlag_PowerRise(SVD_Type *SVDx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_PRF_Msk) == (SVD_ISR_PRF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear SVD Power Rise Flag
|
||||
* @rmtoll ISR PRF FL_SVD_ClearFlag_PowerRise
|
||||
* @param SVDx SVD instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_ClearFlag_PowerRise(SVD_Type *SVDx)
|
||||
{
|
||||
WRITE_REG(SVDx->ISR, SVD_ISR_PRF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SVD Reference
|
||||
* @rmtoll VSR EN FL_SVD_EnableReference
|
||||
* @param SVDx SVD instance
|
||||
* @param ref This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_REFERENCE_1P0V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P95V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P9V
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_EnableReference(SVD_Type *SVDx, uint32_t ref)
|
||||
{
|
||||
WRITE_REG(SVDx->VSR, ((ref & 0x7) << 0x0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SVD Reference Enable Status
|
||||
* @rmtoll VSR EN FL_SVD_IsEnabledReference
|
||||
* @param SVDx SVD instance
|
||||
* @param ref This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_REFERENCE_1P0V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P95V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P9V
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_SVD_IsEnabledReference(SVD_Type *SVDx, uint32_t ref)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SVDx->VSR, ((ref & 0x7) << 0x0U)) == ((ref & 0x7) << 0x0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SVD Reference
|
||||
* @rmtoll VSR EN FL_SVD_DisableReference
|
||||
* @param SVDx SVD instance
|
||||
* @param ref This parameter can be one of the following values:
|
||||
* @arg @ref FL_SVD_REFERENCE_1P0V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P95V
|
||||
* @arg @ref FL_SVD_REFERENCE_0P9V
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_SVD_DisableReference(SVD_Type *SVDx, uint32_t ref)
|
||||
{
|
||||
CLEAR_BIT(SVDx->VSR, ((ref & 0x7) << 0x0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SVD_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_SVD_DeInit(SVD_Type *SVDx);
|
||||
FL_ErrorStatus FL_SVD_Init(SVD_Type *SVDx, FL_SVD_InitTypeDef *init);
|
||||
void FL_SVD_StructInit(FL_SVD_InitTypeDef *init);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_SVD_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1291
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_uart.h
Normal file
1291
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_uart.h
Normal file
File diff suppressed because it is too large
Load Diff
645
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vao.h
Normal file
645
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vao.h
Normal file
@ -0,0 +1,645 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_vao.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of VAO FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_VAO_H
|
||||
#define __FM33LG0XX_FL_VAO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup VAO VAO
|
||||
* @brief VAO FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup VAO_FL_ES_INIT VAO Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL VAO Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL VAO Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! PH15输入使能 */
|
||||
uint32_t input;
|
||||
/*! PH15上拉使能 */
|
||||
uint32_t pullup;
|
||||
/*! PH15开漏输出使能 */
|
||||
uint32_t opendrainOutput;
|
||||
/*! PH15功能选择 */
|
||||
uint32_t mode;
|
||||
|
||||
} FL_VAO_IO_InitTypeDef;
|
||||
typedef struct
|
||||
{
|
||||
/*! 驱动能力配置 */
|
||||
uint32_t driveMode;
|
||||
/*! 工作电流大小*/
|
||||
uint32_t workingCurrentMode;
|
||||
|
||||
} FL_VAO_XTLF_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VAO_FL_Exported_Constants VAO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VAO_RSTCR_VBAT_RST_Pos (0U)
|
||||
#define VAO_RSTCR_VBAT_RST_Msk (0x1U << VAO_RSTCR_VBAT_RST_Pos)
|
||||
#define VAO_RSTCR_VBAT_RST VAO_RSTCR_VBAT_RST_Msk
|
||||
|
||||
#define VAO_XTLFCR_XTLFEN_Pos (0U)
|
||||
#define VAO_XTLFCR_XTLFEN_Msk (0xfU << VAO_XTLFCR_XTLFEN_Pos)
|
||||
#define VAO_XTLFCR_XTLFEN VAO_XTLFCR_XTLFEN_Msk
|
||||
|
||||
#define VAO_XTLFPR_DRVCFG_Pos (4U)
|
||||
#define VAO_XTLFPR_DRVCFG_Msk (0x7U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define VAO_XTLFPR_DRVCFG VAO_XTLFPR_DRVCFG_Msk
|
||||
|
||||
#define VAO_XTLFPR_XTLFIPW_Pos (0U)
|
||||
#define VAO_XTLFPR_XTLFIPW_Msk (0xfU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define VAO_XTLFPR_XTLFIPW VAO_XTLFPR_XTLFIPW_Msk
|
||||
|
||||
#define VAO_FDIER_LFDET_IE_Pos (0U)
|
||||
#define VAO_FDIER_LFDET_IE_Msk (0x1U << VAO_FDIER_LFDET_IE_Pos)
|
||||
#define VAO_FDIER_LFDET_IE VAO_FDIER_LFDET_IE_Msk
|
||||
|
||||
#define VAO_FDISR_LFDETO_Pos (1U)
|
||||
#define VAO_FDISR_LFDETO_Msk (0x1U << VAO_FDISR_LFDETO_Pos)
|
||||
#define VAO_FDISR_LFDETO VAO_FDISR_LFDETO_Msk
|
||||
|
||||
#define VAO_FDISR_LFDETIF_Pos (0U)
|
||||
#define VAO_FDISR_LFDETIF_Msk (0x1U << VAO_FDISR_LFDETIF_Pos)
|
||||
#define VAO_FDISR_LFDETIF VAO_FDISR_LFDETIF_Msk
|
||||
|
||||
#define VAO_INEN_PHINEN_Pos (15U)
|
||||
#define VAO_INEN_PHINEN_Msk (0x1U << VAO_INEN_PHINEN_Pos)
|
||||
#define VAO_INEN_PHINEN VAO_INEN_PHINEN_Msk
|
||||
|
||||
#define VAO_PUEN_PHPUEN_Pos (15U)
|
||||
#define VAO_PUEN_PHPUEN_Msk (0x1U << VAO_PUEN_PHPUEN_Pos)
|
||||
#define VAO_PUEN_PHPUEN VAO_PUEN_PHPUEN_Msk
|
||||
|
||||
#define VAO_ODEN_PHODEN_Pos (15U)
|
||||
#define VAO_ODEN_PHODEN_Msk (0x1U << VAO_ODEN_PHODEN_Pos)
|
||||
#define VAO_ODEN_PHODEN VAO_ODEN_PHODEN_Msk
|
||||
|
||||
#define VAO_FCR_PH15FCR_Pos (30U)
|
||||
#define VAO_FCR_PH15FCR_Msk (0x3U << VAO_FCR_PH15FCR_Pos)
|
||||
#define VAO_FCR_PH15FCR VAO_FCR_PH15FCR_Msk
|
||||
|
||||
#define VAO_DOR_PHDO_Pos (15U)
|
||||
#define VAO_DOR_PHDO_Msk (0x1U << VAO_DOR_PHDO_Pos)
|
||||
#define VAO_DOR_PHDO VAO_DOR_PHDO_Msk
|
||||
|
||||
#define VAO_DIR_PHDIN_Pos (15U)
|
||||
#define VAO_DIR_PHDIN_Msk (0x1U << VAO_DIR_PHDIN_Pos)
|
||||
#define VAO_DIR_PHDIN VAO_DIR_PHDIN_Msk
|
||||
|
||||
#define VAO_VILR_PHVIL15_Pos (15U)
|
||||
#define VAO_VILR_PHVIL15_Msk (0x1U << VAO_VILR_PHVIL15_Pos)
|
||||
#define VAO_VILR_PHVIL15 VAO_VILR_PHVIL15_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_VAO_XTLF_ENABLE (0x5U << VAO_XTLFCR_XTLFEN_Pos)
|
||||
#define FL_VAO_XTLF_DISABLE (0xaU << VAO_XTLFCR_XTLFEN_Pos)
|
||||
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_NONE (0x0U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_1 (0x1U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_2 (0x2U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_3 (0x3U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_4 (0x4U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_5 (0x5U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_6 (0x6U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_DRIVE_LEVEL_7 (0x7U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_NONE (0x0U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_1 (0x1U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_2 (0x2U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_3 (0x3U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_4 (0x4U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_5 (0x5U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_6 (0x6U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
#define FL_VAO_XTLF_OUTPUT_LEVEL_7 (0x7U << VAO_XTLFPR_DRVCFG_Pos)
|
||||
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_850NA (0x0U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_800NA (0x1U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_750NA (0x2U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_700NA (0x3U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_650NA (0x4U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_600NA (0x5U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_550NA (0x6U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_500NA (0x7U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_450NA (0x8U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_400NA (0x9U << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_350NA (0xaU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_300NA (0xbU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_250NA (0xcU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_200NA (0xdU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_150NA (0xeU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
#define FL_VAO_XTLF_WORK_CURRENT_100NA (0xfU << VAO_XTLFPR_XTLFIPW_Pos)
|
||||
|
||||
|
||||
#define FL_VAO_PH15_MODE_INPUT (0x0U << VAO_FCR_PH15FCR_Pos)
|
||||
#define FL_VAO_PH15_MODE_OUTPUT (0x1U << VAO_FCR_PH15FCR_Pos)
|
||||
#define FL_VAO_PH15_MODE_RTCOUT (0x2U << VAO_FCR_PH15FCR_Pos)
|
||||
|
||||
|
||||
#define FL_VAO_PH15_THRESHOLD_NORMAL (0x0U << VAO_VILR_PHVIL15_Pos)
|
||||
#define FL_VAO_PH15_THRESHOLD_LOW (0x1U << VAO_VILR_PHVIL15_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VAO_FL_Exported_Functions VAO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief VBAT电源域寄存器复位使能
|
||||
* @rmtoll RSTCR VBAT_RST FL_VAO_EnableReset
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_EnableReset(VAO_Type *VAOx)
|
||||
{
|
||||
SET_BIT(VAOx->RSTCR, VAO_RSTCR_VBAT_RST_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取VBAT电源域寄存器复位控制状态
|
||||
* @rmtoll RSTCR VBAT_RST FL_VAO_IsEnabledReset
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_IsEnabledReset(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->RSTCR, VAO_RSTCR_VBAT_RST_Msk) == VAO_RSTCR_VBAT_RST_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VBAT电源域寄存器复位撤销
|
||||
* @rmtoll RSTCR VBAT_RST FL_VAO_DisableReset
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_DisableReset(VAO_Type *VAOx)
|
||||
{
|
||||
CLEAR_BIT(VAOx->RSTCR, VAO_RSTCR_VBAT_RST_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 使能XTLF
|
||||
* @rmtoll XTLFCR XTLFEN FL_VAO_XTLF_Enable
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_XTLF_Enable(VAO_Type *VAOx)
|
||||
{
|
||||
WRITE_REG(VAOx->XTLFCR, FL_VAO_XTLF_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取XTLF状态
|
||||
* @rmtoll XTLFCR XTLFEN FL_VAO_XTLF_IsEnabled
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_XTLF_IsEnabled(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(VAOx->XTLFCR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 禁止XTLF
|
||||
* @rmtoll XTLFCR XTLFEN FL_VAO_XTLF_Disable
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_XTLF_Disable(VAO_Type *VAOx)
|
||||
{
|
||||
WRITE_REG(VAOx->XTLFCR, FL_VAO_XTLF_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置输出级驱动等级
|
||||
* @rmtoll XTLFPR DRVCFG FL_VAO_XTLF_SetDriveLevel
|
||||
* @param VAOx VAO instance
|
||||
* @param level This parameter can be one of the following values:
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_NONE
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_1
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_2
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_3
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_4
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_5
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_6
|
||||
* @arg @ref FL_VAO_XTLF_DRIVE_LEVEL_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_XTLF_SetDriveLevel(VAO_Type *VAOx, uint32_t level)
|
||||
{
|
||||
MODIFY_REG(VAOx->XTLFPR, VAO_XTLFPR_DRVCFG_Msk, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get output drive Level
|
||||
* @rmtoll XTLFPR DRVCFG FL_VAO_XTLF_GetDriveLevel
|
||||
* @param VAOx VAO instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_NONE
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_1
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_2
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_3
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_4
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_5
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_6
|
||||
* @arg @ref FL_VAO_XTLF_OUTPUT_LEVEL_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_XTLF_GetDriveLevel(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->XTLFPR, VAO_XTLFPR_DRVCFG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set XTLF working current
|
||||
* @rmtoll XTLFPR XTLFIPW FL_VAO_XTLF_SetWorkCurrent
|
||||
* @param VAOx VAO instance
|
||||
* @param current This parameter can be one of the following values:
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_850NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_800NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_750NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_700NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_650NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_600NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_550NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_500NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_450NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_400NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_350NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_300NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_250NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_200NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_150NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_100NA
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_XTLF_SetWorkCurrent(VAO_Type *VAOx, uint32_t current)
|
||||
{
|
||||
MODIFY_REG(VAOx->XTLFPR, VAO_XTLFPR_XTLFIPW_Msk, current);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XTLF working current
|
||||
* @rmtoll XTLFPR XTLFIPW FL_VAO_XTLF_GetWorkCurrent
|
||||
* @param VAOx VAO instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_850NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_800NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_750NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_700NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_650NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_600NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_550NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_500NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_450NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_400NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_350NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_300NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_250NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_200NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_150NA
|
||||
* @arg @ref FL_VAO_XTLF_WORK_CURRENT_100NA
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_XTLF_GetWorkCurrent(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->XTLFPR, VAO_XTLFPR_XTLFIPW_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief XTLF detect interrupt enable
|
||||
* @rmtoll FDIER LFDET_IE FL_VAO_EnableIT_XTLFFail
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_EnableIT_XTLFFail(VAO_Type *VAOx)
|
||||
{
|
||||
SET_BIT(VAOx->FDIER, VAO_FDIER_LFDET_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XTLF detect interrupt enable status
|
||||
* @rmtoll FDIER LFDET_IE FL_VAO_IsEnabledIT_XTLFFail
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_IsEnabledIT_XTLFFail(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->FDIER, VAO_FDIER_LFDET_IE_Msk) == VAO_FDIER_LFDET_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief XTLF detect interrupt disable
|
||||
* @rmtoll FDIER LFDET_IE FL_VAO_DisableIT_XTLFFail
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_DisableIT_XTLFFail(VAO_Type *VAOx)
|
||||
{
|
||||
CLEAR_BIT(VAOx->FDIER, VAO_FDIER_LFDET_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XTLF detect output
|
||||
* @rmtoll FDISR LFDETO FL_VAO_GetXTLFFailOutput
|
||||
* @param VAOx VAO instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GetXTLFFailOutput(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->FDISR, VAO_FDISR_LFDETO_Msk) >> VAO_FDISR_LFDETO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XTLF detect interrupt flag
|
||||
* @rmtoll FDISR LFDETIF FL_VAO_IsActiveFlag_XTLFFail
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_IsActiveFlag_XTLFFail(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->FDISR, VAO_FDISR_LFDETIF_Msk) == (VAO_FDISR_LFDETIF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear XTLF detect interrupt flag
|
||||
* @rmtoll FDISR LFDETIF FL_VAO_ClearFlag_XTLFFail
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_ClearFlag_XTLFFail(VAO_Type *VAOx)
|
||||
{
|
||||
WRITE_REG(VAOx->FDISR, VAO_FDISR_LFDETIF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 input enable
|
||||
* @rmtoll INEN PHINEN FL_VAO_GPIO_EnablePH15Input
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_EnablePH15Input(VAO_Type *VAOx)
|
||||
{
|
||||
SET_BIT(VAOx->INEN, VAO_INEN_PHINEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 input enable status
|
||||
* @rmtoll INEN PHINEN FL_VAO_GPIO_IsEnabledPH15Input
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_IsEnabledPH15Input(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->INEN, VAO_INEN_PHINEN_Msk) == VAO_INEN_PHINEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 input disable
|
||||
* @rmtoll INEN PHINEN FL_VAO_GPIO_DisablePH15Input
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_DisablePH15Input(VAO_Type *VAOx)
|
||||
{
|
||||
CLEAR_BIT(VAOx->INEN, VAO_INEN_PHINEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 pullup enable
|
||||
* @rmtoll PUEN PHPUEN FL_VAO_GPIO_EnablePH15Pullup
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_EnablePH15Pullup(VAO_Type *VAOx)
|
||||
{
|
||||
SET_BIT(VAOx->PUEN, VAO_PUEN_PHPUEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 pullup enable status
|
||||
* @rmtoll PUEN PHPUEN FL_VAO_GPIO_IsEnabledPH15Pullup
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_IsEnabledPH15Pullup(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->PUEN, VAO_PUEN_PHPUEN_Msk) == VAO_PUEN_PHPUEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 pullup disable
|
||||
* @rmtoll PUEN PHPUEN FL_VAO_GPIO_DisablePH15Pullup
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_DisablePH15Pullup(VAO_Type *VAOx)
|
||||
{
|
||||
CLEAR_BIT(VAOx->PUEN, VAO_PUEN_PHPUEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 pullup enable
|
||||
* @rmtoll ODEN PHODEN FL_VAO_GPIO_EnablePH15OpenDrain
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_EnablePH15OpenDrain(VAO_Type *VAOx)
|
||||
{
|
||||
SET_BIT(VAOx->ODEN, VAO_ODEN_PHODEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 pullup enable status
|
||||
* @rmtoll ODEN PHODEN FL_VAO_GPIO_IsEnabledPH15OpenDrain
|
||||
* @param VAOx VAO instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_IsEnabledPH15OpenDrain(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->ODEN, VAO_ODEN_PHODEN_Msk) == VAO_ODEN_PHODEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PH15 pullup disable
|
||||
* @rmtoll ODEN PHODEN FL_VAO_GPIO_DisablePH15OpenDrain
|
||||
* @param VAOx VAO instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_DisablePH15OpenDrain(VAO_Type *VAOx)
|
||||
{
|
||||
CLEAR_BIT(VAOx->ODEN, VAO_ODEN_PHODEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PH15 mode
|
||||
* @rmtoll FCR PH15FCR FL_VAO_GPIO_SetPH15Mode
|
||||
* @param VAOx VAO instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_VAO_PH15_MODE_INPUT
|
||||
* @arg @ref FL_VAO_PH15_MODE_OUTPUT
|
||||
* @arg @ref FL_VAO_PH15_MODE_RTCOUT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_SetPH15Mode(VAO_Type *VAOx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(VAOx->FCR, VAO_FCR_PH15FCR_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 mode
|
||||
* @rmtoll FCR PH15FCR FL_VAO_GPIO_GetPH15Mode
|
||||
* @param VAOx VAO instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VAO_PH15_MODE_INPUT
|
||||
* @arg @ref FL_VAO_PH15_MODE_OUTPUT
|
||||
* @arg @ref FL_VAO_PH15_MODE_RTCOUT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_GetPH15Mode(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->FCR, VAO_FCR_PH15FCR_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PH15 output data register
|
||||
* @rmtoll DOR PHDO FL_VAO_GPIO_WritePH15Output
|
||||
* @param VAOx VAO instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_WritePH15Output(VAO_Type *VAOx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(VAOx->DOR, (0x1U << 15U), (data << 15U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 output data
|
||||
* @rmtoll DOR PHDO FL_VAO_GPIO_ReadPH15Output
|
||||
* @param VAOx VAO instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_ReadPH15Output(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->DOR, (0x1U << 15U)) >> 15U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 input data
|
||||
* @rmtoll DIR PHDIN FL_VAO_GPIO_ReadPH15Input
|
||||
* @param VAOx VAO instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_ReadPH15Input(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->DIR, (0x1U << 15U)) >> 15U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PH15 input low threshold value
|
||||
* @rmtoll VILR PHVIL15 FL_VAO_GPIO_SetPH15Threshold
|
||||
* @param VAOx VAO instance
|
||||
* @param value This parameter can be one of the following values:
|
||||
* @arg @ref FL_VAO_PH15_THRESHOLD_NORMAL
|
||||
* @arg @ref FL_VAO_PH15_THRESHOLD_LOW
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VAO_GPIO_SetPH15Threshold(VAO_Type *VAOx, uint32_t value)
|
||||
{
|
||||
MODIFY_REG(VAOx->VILR, VAO_VILR_PHVIL15_Msk, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PH15 input low threshold value
|
||||
* @rmtoll VILR PHVIL15 FL_VAO_GPIO_GetPH15Threshold
|
||||
* @param VAOx VAO instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VAO_PH15_THRESHOLD_NORMAL
|
||||
* @arg @ref FL_VAO_PH15_THRESHOLD_LOW
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VAO_GPIO_GetPH15Threshold(VAO_Type *VAOx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VAOx->VILR, VAO_VILR_PHVIL15_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup VAO_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
//#warning "PLEASE ANNOUCE THE INIT AND DEINIT FUNCTIONS HERE!!!"
|
||||
FL_ErrorStatus FL_VAO_DeInit(VAO_Type *VAOx);
|
||||
FL_ErrorStatus FL_VAO_IO_Init(VAO_Type *VAOx, FL_VAO_IO_InitTypeDef *VAO_InitStruct);
|
||||
FL_ErrorStatus FL_VAO_XTLF_Init(VAO_Type *VAOx, FL_VAO_XTLF_InitTypeDef *VAO_XTLF_InitStruct);
|
||||
void FL_VAO_IO_StructInit(FL_VAO_IO_InitTypeDef *VAO_InitStruct);
|
||||
void FL_VAO_XTLF_StructInit(FL_VAO_XTLF_InitTypeDef *VAO_XTLF_InitStruct);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_VAO_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
488
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vref.h
Normal file
488
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vref.h
Normal file
@ -0,0 +1,488 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_vref.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of VREF FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_VREF_H
|
||||
#define __FM33LG0XX_FL_VREF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup VREF VREF
|
||||
* @brief VREF FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREF_FL_ES_INIT VREF Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL VREF Init Sturcture definition
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREF_FL_Exported_Constants VREF Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VREF_CR_VREF_EN_Pos (0U)
|
||||
#define VREF_CR_VREF_EN_Msk (0x1U << VREF_CR_VREF_EN_Pos)
|
||||
#define VREF_CR_VREF_EN VREF_CR_VREF_EN_Msk
|
||||
|
||||
#define VREF_CR_PTAT_EN_Pos (1U)
|
||||
#define VREF_CR_PTAT_EN_Msk (0x1U << VREF_CR_PTAT_EN_Pos)
|
||||
#define VREF_CR_PTAT_EN VREF_CR_PTAT_EN_Msk
|
||||
|
||||
#define VREF_ISR_FLAG_Pos (8U)
|
||||
#define VREF_ISR_FLAG_Msk (0x1U << VREF_ISR_FLAG_Pos)
|
||||
#define VREF_ISR_FLAG VREF_ISR_FLAG_Msk
|
||||
|
||||
#define VREF_ISR_RDY_Pos (1U)
|
||||
#define VREF_ISR_RDY_Msk (0x1U << VREF_ISR_RDY_Pos)
|
||||
#define VREF_ISR_RDY VREF_ISR_RDY_Msk
|
||||
|
||||
#define VREF_ISR_IF_Pos (0U)
|
||||
#define VREF_ISR_IF_Msk (0x1U << VREF_ISR_IF_Pos)
|
||||
#define VREF_ISR_IF VREF_ISR_IF_Msk
|
||||
|
||||
#define VREF_IER_IE_Pos (0U)
|
||||
#define VREF_IER_IE_Msk (0x1U << VREF_IER_IE_Pos)
|
||||
#define VREF_IER_IE VREF_IER_IE_Msk
|
||||
|
||||
#define VREF_BUFCR_AVREFBUF_OUTEN_Pos (5U)
|
||||
#define VREF_BUFCR_AVREFBUF_OUTEN_Msk (0x1U << VREF_BUFCR_AVREFBUF_OUTEN_Pos)
|
||||
#define VREF_BUFCR_AVREFBUF_OUTEN VREF_BUFCR_AVREFBUF_OUTEN_Msk
|
||||
|
||||
#define VREF_BUFCR_AVREFBUF_EN_Pos (4U)
|
||||
#define VREF_BUFCR_AVREFBUF_EN_Msk (0x1U << VREF_BUFCR_AVREFBUF_EN_Pos)
|
||||
#define VREF_BUFCR_AVREFBUF_EN VREF_BUFCR_AVREFBUF_EN_Msk
|
||||
|
||||
#define VREF_BUFCR_VPTATBUFFER_OUTEN_Pos (3U)
|
||||
#define VREF_BUFCR_VPTATBUFFER_OUTEN_Msk (0x1U << VREF_BUFCR_VPTATBUFFER_OUTEN_Pos)
|
||||
#define VREF_BUFCR_VPTATBUFFER_OUTEN VREF_BUFCR_VPTATBUFFER_OUTEN_Msk
|
||||
|
||||
#define VREF_BUFCR_VPTATBUFFER_EN_Pos (2U)
|
||||
#define VREF_BUFCR_VPTATBUFFER_EN_Msk (0x1U << VREF_BUFCR_VPTATBUFFER_EN_Pos)
|
||||
#define VREF_BUFCR_VPTATBUFFER_EN VREF_BUFCR_VPTATBUFFER_EN_Msk
|
||||
|
||||
#define VREF_BUFCR_VREFBUFFER_OUTEN_Pos (1U)
|
||||
#define VREF_BUFCR_VREFBUFFER_OUTEN_Msk (0x1U << VREF_BUFCR_VREFBUFFER_OUTEN_Pos)
|
||||
#define VREF_BUFCR_VREFBUFFER_OUTEN VREF_BUFCR_VREFBUFFER_OUTEN_Msk
|
||||
|
||||
#define VREF_BUFCR_VREFBUFFER_EN_Pos (0U)
|
||||
#define VREF_BUFCR_VREFBUFFER_EN_Msk (0x1U << VREF_BUFCR_VREFBUFFER_EN_Pos)
|
||||
#define VREF_BUFCR_VREFBUFFER_EN VREF_BUFCR_VREFBUFFER_EN_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREF_FL_Exported_Functions VREF Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable VREF
|
||||
* @rmtoll CR VREF_EN FL_VREF_Enable
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_Enable(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Enable Status
|
||||
* @rmtoll CR VREF_EN FL_VREF_IsEnabled
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabled(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk) == VREF_CR_VREF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VREF
|
||||
* @rmtoll CR VREF_EN FL_VREF_Disable
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_Disable(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Temperatue Sensor
|
||||
* @rmtoll CR PTAT_EN FL_VREF_EnableTemperatureSensor
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableTemperatureSensor(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Temperatue Sensor Enable Status
|
||||
* @rmtoll CR PTAT_EN FL_VREF_IsEnabledTemperatureSensor
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledTemperatureSensor(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk) == VREF_CR_PTAT_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Temperatue Sensor
|
||||
* @rmtoll CR PTAT_EN FL_VREF_DisableTemperatureSensor
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableTemperatureSensor(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Setable Flag From Analog
|
||||
* @rmtoll ISR FLAG FL_VREF_IsActiveFlag_AnalogReady
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_AnalogReady(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->ISR, VREF_ISR_FLAG_Msk) == (VREF_ISR_FLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Ready Flag
|
||||
* @rmtoll ISR RDY FL_VREF_IsActiveFlag_DigitalReady
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_DigitalReady(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->ISR, VREF_ISR_RDY_Msk) == (VREF_ISR_RDY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Ready Interrupt Flag
|
||||
* @rmtoll ISR IF FL_VREF_IsActiveFlag_Ready
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_Ready(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->ISR, VREF_ISR_IF_Msk) == (VREF_ISR_IF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear VREF Ready Interrupt Flag
|
||||
* @rmtoll ISR IF FL_VREF_ClearFlag_Ready
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_ClearFlag_Ready(VREF_Type *VREFx)
|
||||
{
|
||||
WRITE_REG(VREFx->ISR, VREF_ISR_IF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable VREF Ready Interrupt
|
||||
* @rmtoll IER IE FL_VREF_EnableIT_Ready
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableIT_Ready(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->IER, VREF_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Ready Interrupt Enable Status
|
||||
* @rmtoll IER IE FL_VREF_IsEnabledIT_Ready
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledIT_Ready(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->IER, VREF_IER_IE_Msk) == VREF_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VREF Ready Interrupt
|
||||
* @rmtoll IER IE FL_VREF_DisableIT_Ready
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableIT_Ready(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->IER, VREF_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable AVREF Buffer Output
|
||||
* @rmtoll BUFCR AVREFBUF_OUTEN FL_VREF_EnableAVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableAVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AVREF Buffer Output Enable Status
|
||||
* @rmtoll BUFCR AVREFBUF_OUTEN FL_VREF_IsEnabledAVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledAVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_OUTEN_Msk) == VREF_BUFCR_AVREFBUF_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable AVREF Buffer Output
|
||||
* @rmtoll BUFCR AVREFBUF_OUTEN FL_VREF_DisableAVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableAVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable AVREF Buffer
|
||||
* @rmtoll BUFCR AVREFBUF_EN FL_VREF_EnableAVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableAVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AVREF Buffer Enable Status
|
||||
* @rmtoll BUFCR AVREFBUF_EN FL_VREF_IsEnabledAVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledAVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_EN_Msk) == VREF_BUFCR_AVREFBUF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable AVREF Buffer
|
||||
* @rmtoll BUFCR AVREFBUF_EN FL_VREF_DisableAVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableAVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_AVREFBUF_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable VPTAT Buffer Output
|
||||
* @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_EnableVPTATBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableVPTATBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VPTAT Buffer Output Enable Status
|
||||
* @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_IsEnabledVPTATBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledVPTATBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk) == VREF_BUFCR_VPTATBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VPTAT Buffer Output
|
||||
* @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_DisableVPTATBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableVPTATBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable VPTAT Buffer
|
||||
* @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_EnableVPTATBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableVPTATBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VPTAT Buffer Enable Status
|
||||
* @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_IsEnabledVPTATBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledVPTATBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk) == VREF_BUFCR_VPTATBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VPTAT Buffer
|
||||
* @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_DisableVPTATBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableVPTATBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable VREF Buffer Output
|
||||
* @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_EnableVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Buffer Output Enable Status
|
||||
* @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_IsEnabledVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk) == VREF_BUFCR_VREFBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VREF Buffer Output
|
||||
* @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_DisableVREFBufferOutput
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableVREFBufferOutput(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable VREF Buffer
|
||||
* @rmtoll BUFCR VREFBUFFER_EN FL_VREF_EnableVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_EnableVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
SET_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREF Buffer Enable Status
|
||||
* @rmtoll BUFCR VREFBUFFER_EN FL_VREF_IsEnabledVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREF_IsEnabledVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk) == VREF_BUFCR_VREFBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VREF Buffer
|
||||
* @rmtoll BUFCR VREFBUFFER_EN FL_VREF_DisableVREFBuffer
|
||||
* @param VREFx VREF instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREF_DisableVREFBuffer(VREF_Type *VREFx)
|
||||
{
|
||||
CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup VREF_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_VREF_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
521
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vrefp.h
Normal file
521
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_vrefp.h
Normal file
@ -0,0 +1,521 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_vrefp.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of VREFP FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_VREFP_H
|
||||
#define __FM33LG0XX_FL_VREFP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup VREFP VREFP
|
||||
* @brief VREFP FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREFP_FL_ES_INIT VREFP Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL VREFP Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 输出电压的TRIM值 */
|
||||
uint32_t voltageTrim;
|
||||
/* 输出电压值 */
|
||||
uint32_t outputVoltage;
|
||||
/* VREFP输出模式 */
|
||||
uint32_t mode;
|
||||
/* 间歇模式下单次驱动时间 */
|
||||
uint32_t timeOfDriving;
|
||||
/* 间歇模式下使能周期 */
|
||||
uint32_t timeOfPeriod;
|
||||
|
||||
} FL_VREFP_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREFP_FL_Exported_Constants VREFP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VREFP_CR_DENDIE_Pos (2U)
|
||||
#define VREFP_CR_DENDIE_Msk (0x1U << VREFP_CR_DENDIE_Pos)
|
||||
#define VREFP_CR_DENDIE VREFP_CR_DENDIE_Msk
|
||||
|
||||
#define VREFP_CR_POVIE_Pos (1U)
|
||||
#define VREFP_CR_POVIE_Msk (0x1U << VREFP_CR_POVIE_Pos)
|
||||
#define VREFP_CR_POVIE VREFP_CR_POVIE_Msk
|
||||
|
||||
#define VREFP_CR_EN_Pos (0U)
|
||||
#define VREFP_CR_EN_Msk (0x1U << VREFP_CR_EN_Pos)
|
||||
#define VREFP_CR_EN VREFP_CR_EN_Msk
|
||||
|
||||
#define VREFP_CFGR_VRS_Pos (8U)
|
||||
#define VREFP_CFGR_VRS_Msk (0x7U << VREFP_CFGR_VRS_Pos)
|
||||
#define VREFP_CFGR_VRS VREFP_CFGR_VRS_Msk
|
||||
|
||||
#define VREFP_CFGR_TPERIOD_Pos (5U)
|
||||
#define VREFP_CFGR_TPERIOD_Msk (0x7U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define VREFP_CFGR_TPERIOD VREFP_CFGR_TPERIOD_Msk
|
||||
|
||||
#define VREFP_CFGR_TDRV_Pos (2U)
|
||||
#define VREFP_CFGR_TDRV_Msk (0x7U << VREFP_CFGR_TDRV_Pos)
|
||||
#define VREFP_CFGR_TDRV VREFP_CFGR_TDRV_Msk
|
||||
|
||||
#define VREFP_CFGR_LPM_Pos (1U)
|
||||
#define VREFP_CFGR_LPM_Msk (0x1U << VREFP_CFGR_LPM_Pos)
|
||||
#define VREFP_CFGR_LPM VREFP_CFGR_LPM_Msk
|
||||
|
||||
#define VREFP_ISR_BUSY_Pos (2U)
|
||||
#define VREFP_ISR_BUSY_Msk (0x1U << VREFP_ISR_BUSY_Pos)
|
||||
#define VREFP_ISR_BUSY VREFP_ISR_BUSY_Msk
|
||||
|
||||
#define VREFP_ISR_DEND_Pos (1U)
|
||||
#define VREFP_ISR_DEND_Msk (0x1U << VREFP_ISR_DEND_Pos)
|
||||
#define VREFP_ISR_DEND VREFP_ISR_DEND_Msk
|
||||
|
||||
#define VREFP_ISR_POV_Pos (0U)
|
||||
#define VREFP_ISR_POV_Msk (0x1U << VREFP_ISR_POV_Pos)
|
||||
#define VREFP_ISR_POV VREFP_ISR_POV_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_2P0V (0x0U << VREFP_CFGR_VRS_Pos)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_2P5V (0x1U << VREFP_CFGR_VRS_Pos)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_3P0V (0x2U << VREFP_CFGR_VRS_Pos)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_4P5V (0x3U << VREFP_CFGR_VRS_Pos)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_1P5V (0x4U << VREFP_CFGR_VRS_Pos)
|
||||
|
||||
|
||||
#define FL_VREFP_ENABLE_PERIOD_1MS (0x0U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_4MS (0x1U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_16MS (0x2U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_32MS (0x3U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_64MS (0x4U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_256MS (0x5U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_1000MS (0x6U << VREFP_CFGR_TPERIOD_Pos)
|
||||
#define FL_VREFP_ENABLE_PERIOD_4000MS (0x7U << VREFP_CFGR_TPERIOD_Pos)
|
||||
|
||||
|
||||
#define FL_VREFP_DRIVING_TIME_4LSCLK (0x0U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_8LSCLK (0x1U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_16LSCLK (0x2U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_32LSCLK (0x3U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_64LSCLK (0x4U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_128LSCLK (0x5U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_256LSCLK (0x6U << VREFP_CFGR_TDRV_Pos)
|
||||
#define FL_VREFP_DRIVING_TIME_512LSCLK (0x7U << VREFP_CFGR_TDRV_Pos)
|
||||
|
||||
|
||||
#define FL_VREFP_WORK_MODE_CONTINUOUS (0x0U << VREFP_CFGR_LPM_Pos)
|
||||
#define FL_VREFP_WORK_MODE_PERIODIC (0x1U << VREFP_CFGR_LPM_Pos)
|
||||
|
||||
|
||||
/* 原始值 */
|
||||
#define VREFP_OUTPUT_VOLTAGE_2P0V_TRIM (*(uint32_t*)0x1FFFFA90)
|
||||
#define VREFP_OUTPUT_VOLTAGE_2P5V_TRIM (*(uint32_t*)0x1FFFFA8C)
|
||||
#define VREFP_OUTPUT_VOLTAGE_3P0V_TRIM (*(uint32_t*)0x1FFFFA88)
|
||||
#define VREFP_OUTPUT_VOLTAGE_4P5V_TRIM (*(uint32_t*)0x1FFFFA84)
|
||||
#define VREFP_OUTPUT_VOLTAGE_1P5V_TRIM (*(uint32_t*)0x1FFFFA94)
|
||||
|
||||
/* 备份值 */
|
||||
#define VREFP_OUTPUT_VOLTAGE_2P0V_TRIM_BKP (*(uint16_t*)0x1FFFFBA6)
|
||||
#define VREFP_OUTPUT_VOLTAGE_2P5V_TRIM_BKP (*(uint16_t*)0x1FFFFBA4)
|
||||
#define VREFP_OUTPUT_VOLTAGE_3P0V_TRIM_BKP (*(uint16_t*)0x1FFFFBA2)
|
||||
#define VREFP_OUTPUT_VOLTAGE_4P5V_TRIM_BKP (*(uint16_t*)0x1FFFFBA0)
|
||||
#define VREFP_OUTPUT_VOLTAGE_1P5V_TRIM_BKP (*(uint16_t*)0x1FFFFBA8)
|
||||
|
||||
/* 最终值 */
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_2P0V_TRIM (LDT_CHECK(VREFP_OUTPUT_VOLTAGE_2P0V_TRIM, VREFP_OUTPUT_VOLTAGE_2P0V_TRIM_BKP) & 0xff)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_2P5V_TRIM (LDT_CHECK(VREFP_OUTPUT_VOLTAGE_2P5V_TRIM, VREFP_OUTPUT_VOLTAGE_2P5V_TRIM_BKP) & 0xff)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_3P0V_TRIM (LDT_CHECK(VREFP_OUTPUT_VOLTAGE_3P0V_TRIM, VREFP_OUTPUT_VOLTAGE_3P0V_TRIM_BKP) & 0xff)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_4P5V_TRIM (LDT_CHECK(VREFP_OUTPUT_VOLTAGE_4P5V_TRIM, VREFP_OUTPUT_VOLTAGE_4P5V_TRIM_BKP) & 0xff)
|
||||
#define FL_VREFP_OUTPUT_VOLTAGE_1P5V_TRIM (LDT_CHECK(VREFP_OUTPUT_VOLTAGE_1P5V_TRIM, VREFP_OUTPUT_VOLTAGE_1P5V_TRIM_BKP) & 0xff)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup VREFP_FL_Exported_Functions VREFP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Driving end interrupt enable
|
||||
* @rmtoll CR DENDIE FL_VREFP_EnableIT_DrivingEnd
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_EnableIT_DrivingEnd(VREFP_Type *VREFPx)
|
||||
{
|
||||
SET_BIT(VREFPx->CR, VREFP_CR_DENDIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Driving end interrupt enable status
|
||||
* @rmtoll CR DENDIE FL_VREFP_IsEnabledIT_DrivingEnd
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsEnabledIT_DrivingEnd(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CR, VREFP_CR_DENDIE_Msk) == VREFP_CR_DENDIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Driving end interrupt disable
|
||||
* @rmtoll CR DENDIE FL_VREFP_DisableIT_DrivingEnd
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_DisableIT_DrivingEnd(VREFP_Type *VREFPx)
|
||||
{
|
||||
CLEAR_BIT(VREFPx->CR, VREFP_CR_DENDIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Periodic overflow interrupt enable
|
||||
* @rmtoll CR POVIE FL_VREFP_EnableIT_EndOfPeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_EnableIT_EndOfPeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
SET_BIT(VREFPx->CR, VREFP_CR_POVIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Periodic overflow interrupt enable status
|
||||
* @rmtoll CR POVIE FL_VREFP_IsEnabledIT_EndOfPeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsEnabledIT_EndOfPeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CR, VREFP_CR_POVIE_Msk) == VREFP_CR_POVIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Periodic overflow interrupt disable
|
||||
* @rmtoll CR POVIE FL_VREFP_DisableIT_EndOfPeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_DisableIT_EndOfPeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
CLEAR_BIT(VREFPx->CR, VREFP_CR_POVIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VREFP_VREG enable
|
||||
* @rmtoll CR EN FL_VREFP_Enable
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_Enable(VREFP_Type *VREFPx)
|
||||
{
|
||||
SET_BIT(VREFPx->CR, VREFP_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREFP_VREG enable status
|
||||
* @rmtoll CR EN FL_VREFP_IsEnabled
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsEnabled(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CR, VREFP_CR_EN_Msk) == VREFP_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VREFP_VREG disable
|
||||
* @rmtoll CR EN FL_VREFP_Disable
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_Disable(VREFP_Type *VREFPx)
|
||||
{
|
||||
CLEAR_BIT(VREFPx->CR, VREFP_CR_EN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set output voltage
|
||||
* @rmtoll CFGR VRS FL_VREFP_SetOutputVoltage
|
||||
* @param VREFPx VREFP instance
|
||||
* @param voltage This parameter can be one of the following values:
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_2P0V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_2P5V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_3P0V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_4P5V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_1P5V
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_SetOutputVoltage(VREFP_Type *VREFPx, uint32_t voltage)
|
||||
{
|
||||
MODIFY_REG(VREFPx->CFGR, VREFP_CFGR_VRS_Msk, voltage);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get output voltage
|
||||
* @rmtoll CFGR VRS FL_VREFP_GetOutputVoltage
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_2P0V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_2P5V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_3P0V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_4P5V
|
||||
* @arg @ref FL_VREFP_OUTPUT_VOLTAGE_1P5V
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_GetOutputVoltage(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CFGR, VREFP_CFGR_VRS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set period time on low power mode
|
||||
* @rmtoll CFGR TPERIOD FL_VREFP_SetEnablePeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @param period This parameter can be one of the following values:
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_1MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_4MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_16MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_32MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_64MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_256MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_1000MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_4000MS
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_SetEnablePeriod(VREFP_Type *VREFPx, uint32_t period)
|
||||
{
|
||||
MODIFY_REG(VREFPx->CFGR, VREFP_CFGR_TPERIOD_Msk, period);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get period time on low power mode
|
||||
* @rmtoll CFGR TPERIOD FL_VREFP_GetEnablePeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_1MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_4MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_16MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_32MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_64MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_256MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_1000MS
|
||||
* @arg @ref FL_VREFP_ENABLE_PERIOD_4000MS
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_GetEnablePeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CFGR, VREFP_CFGR_TPERIOD_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set driving time on low power mode
|
||||
* @rmtoll CFGR TDRV FL_VREFP_SetDrivingTime
|
||||
* @param VREFPx VREFP instance
|
||||
* @param time This parameter can be one of the following values:
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_4LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_8LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_16LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_32LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_64LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_128LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_256LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_512LSCLK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_SetDrivingTime(VREFP_Type *VREFPx, uint32_t time)
|
||||
{
|
||||
MODIFY_REG(VREFPx->CFGR, VREFP_CFGR_TDRV_Msk, time);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get driving time on low power mode
|
||||
* @rmtoll CFGR TDRV FL_VREFP_GetDrivingTime
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_4LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_8LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_16LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_32LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_64LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_128LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_256LSCLK
|
||||
* @arg @ref FL_VREFP_DRIVING_TIME_512LSCLK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_GetDrivingTime(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CFGR, VREFP_CFGR_TDRV_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Low power mode enable
|
||||
* @rmtoll CFGR LPM FL_VREFP_SetWorkMode
|
||||
* @param VREFPx VREFP instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_VREFP_WORK_MODE_CONTINUOUS
|
||||
* @arg @ref FL_VREFP_WORK_MODE_PERIODIC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_SetWorkMode(VREFP_Type *VREFPx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(VREFPx->CFGR, VREFP_CFGR_LPM_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get low power mode enablestatus
|
||||
* @rmtoll CFGR LPM FL_VREFP_GetWorkMode
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_VREFP_WORK_MODE_CONTINUOUS
|
||||
* @arg @ref FL_VREFP_WORK_MODE_PERIODIC
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_GetWorkMode(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->CFGR, VREFP_CFGR_LPM_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Driving busy flag
|
||||
* @rmtoll ISR BUSY FL_VREFP_IsActiveFlag_DrivingBusy
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsActiveFlag_DrivingBusy(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->ISR, VREFP_ISR_BUSY_Msk) == (VREFP_ISR_BUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Driving end flag
|
||||
* @rmtoll ISR DEND FL_VREFP_IsActiveFlag_DrivingEnd
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsActiveFlag_DrivingEnd(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->ISR, VREFP_ISR_DEND_Msk) == (VREFP_ISR_DEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Driving end flag
|
||||
* @rmtoll ISR DEND FL_VREFP_ClearFlag_DrivingEnd
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_ClearFlag_DrivingEnd(VREFP_Type *VREFPx)
|
||||
{
|
||||
WRITE_REG(VREFPx->ISR, VREFP_ISR_DEND_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get periodic overflow flag
|
||||
* @rmtoll ISR POV FL_VREFP_IsActiveFlag_EndOfPeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_IsActiveFlag_EndOfPeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->ISR, VREFP_ISR_POV_Msk) == (VREFP_ISR_POV_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear periodic overflow flag
|
||||
* @rmtoll ISR POV FL_VREFP_ClearFlag_EndOfPeriod
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_ClearFlag_EndOfPeriod(VREFP_Type *VREFPx)
|
||||
{
|
||||
WRITE_REG(VREFPx->ISR, VREFP_ISR_POV_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set VREFP output voltage
|
||||
* @rmtoll TR FL_VREFP_WriteOutputVoltageTrim
|
||||
* @param VREFPx VREFP instance
|
||||
* @param voltage
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_VREFP_WriteOutputVoltageTrim(VREFP_Type *VREFPx, uint32_t voltage)
|
||||
{
|
||||
MODIFY_REG(VREFPx->TR, (0xffU << 0U), (voltage << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VREFP output voltage
|
||||
* @rmtoll TR FL_VREFP_ReadOutputVoltageTrim
|
||||
* @param VREFPx VREFP instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_VREFP_ReadOutputVoltageTrim(VREFP_Type *VREFPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(VREFPx->TR, (0xffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup VREFP_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_VREFP_Init(VREFP_Type *VREFPx, FL_VREFP_InitTypeDef *VREFP_InitStruct);
|
||||
void FL_VREFP_StructInit(FL_VREFP_InitTypeDef *VREFP_InitStruct);
|
||||
FL_ErrorStatus FL_VREFP_DeInit(VREFP_Type *VREFPx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_VREFP_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.14-0.1 @ 2021-06-25*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
263
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_wwdt.h
Normal file
263
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Inc/fm33lg0xx_fl_wwdt.h
Normal file
@ -0,0 +1,263 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_wwdt.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of WWDT FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LG0XX_FL_WWDT_H
|
||||
#define __FM33LG0XX_FL_WWDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl_def.h"
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT WWDT
|
||||
* @brief WWDT FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup WWDT_FL_ES_INIT WWDT Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL WWDT Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 看门狗溢出周期 */
|
||||
uint32_t overflowPeriod;
|
||||
|
||||
} FL_WWDT_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup WWDT_FL_Exported_Constants WWDT Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDT_CR_CON_Pos (0U)
|
||||
#define WWDT_CR_CON_Msk (0xffU << WWDT_CR_CON_Pos)
|
||||
#define WWDT_CR_CON WWDT_CR_CON_Msk
|
||||
|
||||
#define WWDT_CFGR_CFG_Pos (0U)
|
||||
#define WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos)
|
||||
#define WWDT_CFGR_CFG WWDT_CFGR_CFG_Msk
|
||||
|
||||
#define WWDT_IER_IE_Pos (0U)
|
||||
#define WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos)
|
||||
#define WWDT_IER_IE WWDT_IER_IE_Msk
|
||||
|
||||
#define WWDT_ISR_IF_Pos (0U)
|
||||
#define WWDT_ISR_IF_Msk (0x1U << WWDT_ISR_IF_Pos)
|
||||
#define WWDT_ISR_IF WWDT_ISR_IF_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_WWDT_KEY_ENABLE (0x5AU << WWDT_CR_CON_Pos)
|
||||
|
||||
#define FL_WWDT_RELOAD_ENABLE (0xACU << WWDT_CR_CON_Pos)
|
||||
|
||||
#define FL_WWDT_PERIOD_1CNT (0x0U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_4CNT (0x1U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_16CNT (0x2U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_64CNT (0x3U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_128CNT (0x4U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_256CNT (0x5U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_512CNT (0x6U << WWDT_CFGR_CFG_Pos)
|
||||
#define FL_WWDT_PERIOD_1024CNT (0x7U << WWDT_CFGR_CFG_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup WWDT_FL_Exported_Functions WWDT Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief WWDT enable counter
|
||||
* @rmtoll CR CON FL_WWDT_Enable
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_Enable(WWDT_Type *WWDTx)
|
||||
{
|
||||
WRITE_REG(WWDTx->CR, FL_WWDT_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief WWDT reset counter
|
||||
* @rmtoll CR CON FL_WWDT_ReloadCounter
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_ReloadCounter(WWDT_Type *WWDTx)
|
||||
{
|
||||
WRITE_REG(WWDTx->CR, FL_WWDT_RELOAD_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set WWDT overflow period
|
||||
* @rmtoll CFGR CFG FL_WWDT_SetPeriod
|
||||
* @param WWDTx WWDT instance
|
||||
* @param period This parameter can be one of the following values:
|
||||
* @arg @ref FL_WWDT_PERIOD_1CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_4CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_16CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_64CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_128CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_256CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_512CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_1024CNT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_SetPeriod(WWDT_Type *WWDTx, uint32_t period)
|
||||
{
|
||||
MODIFY_REG(WWDTx->CFGR, WWDT_CFGR_CFG_Msk, period);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get WWDT overflow period
|
||||
* @rmtoll CFGR CFG FL_WWDT_GetPeriod
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_WWDT_PERIOD_1CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_4CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_16CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_64CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_128CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_256CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_512CNT
|
||||
* @arg @ref FL_WWDT_PERIOD_1024CNT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_WWDT_GetPeriod(WWDT_Type *WWDTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDTx->CFGR, WWDT_CFGR_CFG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Counter value
|
||||
* @rmtoll CNT FL_WWDT_ReadCounter
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_WWDT_ReadCounter(WWDT_Type *WWDTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDTx->CNT, (0x3ffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief WWDT interrupt enable
|
||||
* @rmtoll IER IE FL_WWDT_EnableIT_NearOverflow
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_EnableIT_NearOverflow(WWDT_Type *WWDTx)
|
||||
{
|
||||
SET_BIT(WWDTx->IER, WWDT_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief WWDT interrupt enable status
|
||||
* @rmtoll IER IE FL_WWDT_IsEnabledIT_NearOverflow
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_WWDT_IsEnabledIT_NearOverflow(WWDT_Type *WWDTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDTx->IER, WWDT_IER_IE_Msk) == WWDT_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief WWDT interrupt disable
|
||||
* @rmtoll IER IE FL_WWDT_DisableIT_NearOverflow
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_DisableIT_NearOverflow(WWDT_Type *WWDTx)
|
||||
{
|
||||
CLEAR_BIT(WWDTx->IER, WWDT_IER_IE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get WWDT 75% overflow flag
|
||||
* @rmtoll ISR IF FL_WWDT_IsActiveFlag_NearOverflow
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_WWDT_IsActiveFlag_NearOverflow(WWDT_Type *WWDTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDTx->ISR, WWDT_ISR_IF_Msk) == (WWDT_ISR_IF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT 75% overflow flag
|
||||
* @rmtoll ISR IF FL_WWDT_ClearFlag_NearOverflow
|
||||
* @param WWDTx WWDT instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_WWDT_ClearFlag_NearOverflow(WWDT_Type *WWDTx)
|
||||
{
|
||||
WRITE_REG(WWDTx->ISR, WWDT_ISR_IF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_WWDT_DeInit(WWDT_Type *WWDTx);
|
||||
FL_ErrorStatus FL_WWDT_Init(WWDT_Type *WWDTx, FL_WWDT_InitTypeDef *WWDT_InitStruct);
|
||||
void FL_WWDT_StructInit(FL_WWDT_InitTypeDef *WWDT_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LG0XX_FL_WWDT_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-14*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
163
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl.c
Normal file
163
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl.c
Normal file
@ -0,0 +1,163 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Source file of FL Driver Library
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FL_EF_DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the timer(default is Systick) used as delay timer.
|
||||
* @note The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__WEAK void FL_DelayInit(void)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide block delay in microseconds.
|
||||
* @note The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param count specifies the delay count in microseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__WEAK void FL_DelayUs(uint32_t count)
|
||||
{
|
||||
count = FL_DELAY_US * count;
|
||||
count = count > 16777216 ? 16777216 : count;
|
||||
SysTick->LOAD = count - 1;
|
||||
SysTick->VAL = 0;
|
||||
while(!((SysTick->CTRL >> 16) & 0x1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide blocking delay in milliseconds.
|
||||
* @note The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param count specifies the delay count in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__WEAK void FL_DelayMs(uint32_t count)
|
||||
{
|
||||
while(count--)
|
||||
{
|
||||
FL_DelayUs(1000);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide no-blocking delay initialization in microseconds.
|
||||
* @note Should be follow By while(!FL_DelayEnd()){ ** user code ** } immediately.
|
||||
The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param count specifies the delay count in microseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__WEAK void FL_DelayUsStart(uint32_t count)
|
||||
{
|
||||
count = FL_DELAY_US * count;
|
||||
count = count > 16777216 ? 16777216 : count;
|
||||
SysTick->LOAD = count - 1;
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide no-blocking delay initialization in milliseconds.
|
||||
* @note Should be followed By while(!FL_DelayEnd()){ ** user code ** }.
|
||||
* The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param count specifies the delay count in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__WEAK void FL_DelayMsStart(uint32_t count)
|
||||
{
|
||||
FL_DelayUsStart(1000 * count);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Showing if the no-blocking delay has ended.
|
||||
* @note Should be used with FL_DelayMs/UsStart() function.
|
||||
The function is declared as __WEAK to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param count specifies the delay count in milliseconds.
|
||||
* @retval true - delay has ended
|
||||
* false - delay is in progress
|
||||
*/
|
||||
__WEAK bool FL_DelayEnd(void)
|
||||
{
|
||||
return (((SysTick->CTRL >> 16) & 0x1) == 0x1);
|
||||
}
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/** @addtogroup FL_EF_DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FL_Init(void)
|
||||
{
|
||||
/* Init delay support function */
|
||||
FL_DelayInit();
|
||||
}
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/** @addtogroup FL_EF_NVIC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure NVIC for specified Interrupt.
|
||||
* @param configStruct NVIC configuration.
|
||||
* @param irq Interrupt number.
|
||||
* @retval None
|
||||
*/
|
||||
void FL_NVIC_Init(FL_NVIC_ConfigTypeDef *configStruct, IRQn_Type irq)
|
||||
{
|
||||
/* Check parameter */
|
||||
if(configStruct->preemptPriority > 3)
|
||||
{
|
||||
configStruct->preemptPriority = 3;
|
||||
}
|
||||
NVIC_DisableIRQ(irq);
|
||||
NVIC_SetPriority(irq, configStruct->preemptPriority);
|
||||
NVIC_EnableIRQ(irq);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
|
||||
|
||||
432
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_adc.c
Normal file
432
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_adc.c
Normal file
@ -0,0 +1,432 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_adc.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of ADC FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0xx_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_ADC_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup ADC_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FL_ADC_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
|
||||
|
||||
#define IS_FL_ADC_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_CMU_ADC_CLK_SOURCE_RCLF)||\
|
||||
((__VALUE__) == FL_CMU_ADC_CLK_SOURCE_RCHF)||\
|
||||
((__VALUE__) == FL_CMU_ADC_CLK_SOURCE_XTHF)||\
|
||||
((__VALUE__) == FL_CMU_ADC_CLK_SOURCE_PLL)||\
|
||||
((__VALUE__) == FL_ADC_CLK_SOURCE_APBCLK))
|
||||
|
||||
#define IS_FL_ADC_CMUCLK_PRESCALER(__VALUE__) (((__VALUE__) == FL_ADC_CLK_PSC_DIV1)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV2)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV4)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV8)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV16)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV32))
|
||||
|
||||
#define IS_FL_ADC_APBCLK_PRESCALER(__VALUE__) (((__VALUE__) == FL_ADC_CLK_PSC_DIV1)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV2)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV4)||\
|
||||
((__VALUE__) == FL_ADC_CLK_PSC_DIV8))
|
||||
|
||||
#define IS_FL_ADC_REFERENCE_SOURCE(__VALUE__) (((__VALUE__) == FL_ADC_REF_SOURCE_VDDA)||\
|
||||
((__VALUE__) == FL_ADC_REF_SOURCE_VREFP))
|
||||
|
||||
#define IS_FL_ADC_BITWIDTH(__VALUE__) (((__VALUE__) == FL_ADC_BIT_WIDTH_12B)||\
|
||||
((__VALUE__) == FL_ADC_BIT_WIDTH_10B)||\
|
||||
((__VALUE__) == FL_ADC_BIT_WIDTH_8B)||\
|
||||
((__VALUE__) == FL_ADC_BIT_WIDTH_6B))
|
||||
|
||||
#define IS_FL_ADC_CONTINUOUSCONVMODE(__VALUE__) (((__VALUE__) == FL_ADC_CONV_MODE_SINGLE)||\
|
||||
((__VALUE__) == FL_ADC_CONV_MODE_CONTINUOUS))
|
||||
|
||||
#define IS_FL_ADC_AUTO_MODE(__VALUE__) (((__VALUE__) == FL_ADC_SINGLE_CONV_MODE_AUTO)||\
|
||||
((__VALUE__) == FL_ADC_SINGLE_CONV_MODE_SEMIAUTO))
|
||||
|
||||
|
||||
#define IS_FL_ADC_SCANDIRECTION(__VALUE__) (((__VALUE__) == FL_ADC_SEQ_SCAN_DIR_FORWARD)||\
|
||||
((__VALUE__) == FL_ADC_SEQ_SCAN_DIR_BACKWARD))
|
||||
|
||||
|
||||
#define IS_FL_ADC_EXTERNALTRIGCONV(__VALUE__) (((__VALUE__) == FL_ADC_TRIGGER_EDGE_NONE)||\
|
||||
((__VALUE__) == FL_ADC_TRIGGER_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_ADC_TRIGGER_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_ADC_TRIGGER_EDGE_BOTH))
|
||||
|
||||
#define IS_FL_ADC_EXTERNALTRIGSOURCE(__VALUE__) (((__VALUE__) == FL_ADC_TRGI_LUT0)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_LUT1)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_LUT2)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_ATIM)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_GPTIM1)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_GPTIM2)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_BSTIM16)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_LPTIM12)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_COMP1)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_COMP2)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_RTCA)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_LUT3)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_GPTIM0)||\
|
||||
((__VALUE__) == FL_ADC_TRGI_COMP3))
|
||||
|
||||
#define IS_FL_ADC_CHANNEL_FAST_TIME(__VALUE__) (((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_2_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_8_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_16_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_32_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_64_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_80_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_96_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_128_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_160_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_192_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_256_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_320_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_384_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_512_ADCCLK))
|
||||
|
||||
#define IS_FL_ADC_CHANNEL_SLOW_TIME(__VALUE__) (((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_2_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_4_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_8_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_16_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_32_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_64_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_80_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_96_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_128_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_160_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_256_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_320_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_384_ADCCLK)||\
|
||||
((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_512_ADCCLK))
|
||||
|
||||
#define IS_FL_ADC_OVERSAMPCOFIG(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_ADC_OVERSAMPINGRATIO(__VALUE__) (((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_2X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_4X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_8X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_16X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_32X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_64X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_128X)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_256X))
|
||||
|
||||
#define IS_FL_ADC_OVERSAMPINGSHIFT(__VALUE__) (((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_0B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_1B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_2B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_3B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_4B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_5B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_6B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_7B)||\
|
||||
((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_8B))
|
||||
|
||||
#define ADC_CALIBRATIN_TIME_OUT (500000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC外设寄存器值为复位值
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_ADC_CommonDeInit(void)
|
||||
{
|
||||
/* 关闭总线时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_ADC);
|
||||
/* 关闭操作时钟 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ADC);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief ADC共用寄存器设置以配置外设工作时钟
|
||||
*
|
||||
* @note 其中FL_LPTIM_OPERATION_MODE_EXTERNAL_ASYN_PAUSE_CNT 模式需要外部脉冲提供给LPTIM模块作为工作时钟，此时
|
||||
* LPTIM完全工作在异步模式下。
|
||||
* @param LPTIM 外设入口地址
|
||||
* @param LPTIM_InitStruct指向FL_LPTIM_TimeInitTypeDef类的结构体，它包含指定LPTIM外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS ADC配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ADC_CommonInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FL_ADC_CLK_SOURCE(ADC_CommonInitStruct->clockSource));
|
||||
assert_param(IS_FL_ADC_REFERENCE_SOURCE(ADC_CommonInitStruct->referenceSource));
|
||||
assert_param(IS_FL_ADC_BITWIDTH(ADC_CommonInitStruct->bitWidth));
|
||||
if(ADC_CommonInitStruct->clockSource == FL_ADC_CLK_SOURCE_APBCLK)
|
||||
{
|
||||
assert_param(IS_FL_ADC_APBCLK_PRESCALER(ADC_CommonInitStruct->clockPrescaler));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_FL_ADC_CMUCLK_PRESCALER(ADC_CommonInitStruct->clockPrescaler));
|
||||
}
|
||||
|
||||
/* 开启总线时钟 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_ADC);
|
||||
/* 配置ADC时钟 */
|
||||
if(ADC_CommonInitStruct->clockSource == FL_ADC_CLK_SOURCE_APBCLK)
|
||||
{
|
||||
/* 设置ADC时钟来源于APBCLK */
|
||||
FL_ADC_SetClockSource(ADC, FL_ADC_CLK_SOURCE_APBCLK);
|
||||
|
||||
/* 配置APBCLOCK时钟预分频 */
|
||||
FL_ADC_SetAPBPrescaler(ADC, ADC_CommonInitStruct->clockPrescaler << ADC_CFGR1_APBCLK_PSC_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 设置ADC时钟来源于ADCCLK */
|
||||
FL_ADC_SetClockSource(ADC, FL_ADC_CLK_SOURCE_ADCCLK);
|
||||
|
||||
/* 设置ADCCLK时钟源 */
|
||||
FL_CMU_SetADCClockSource(ADC_CommonInitStruct->clockSource);
|
||||
|
||||
/* 配置ADCCLK时钟预分频 */
|
||||
FL_CMU_SetADCPrescaler(ADC_CommonInitStruct->clockPrescaler << CMU_OPCCR2_ADCPRSC_Pos);
|
||||
|
||||
/* 开启操作时钟 */
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ADC);
|
||||
}
|
||||
/* 配置ADC基准电压*/
|
||||
FL_ADC_SetReferenceSource(ADC, ADC_CommonInitStruct->referenceSource);
|
||||
/* 配置ADC输出位数*/
|
||||
FL_ADC_SetBitWidth(ADC, ADC_CommonInitStruct->bitWidth);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 ADC_CommonInitStruct 为默认配置
|
||||
* @param ADC_CommonInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ADC_CommonInitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ADC_CommonStructInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||
{
|
||||
/* 默认使用RCHF作为ADC时钟模块时钟源，预分频系数16 */
|
||||
ADC_CommonInitStruct->clockSource = FL_CMU_ADC_CLK_SOURCE_RCHF;
|
||||
ADC_CommonInitStruct->clockPrescaler = FL_CMU_ADC_PSC_DIV16;
|
||||
ADC_CommonInitStruct->referenceSource = FL_ADC_REF_SOURCE_VDDA;
|
||||
ADC_CommonInitStruct->bitWidth = FL_ADC_BIT_WIDTH_12B;
|
||||
}
|
||||
/**
|
||||
* @brief 恢复对应的ADC入口地址寄存器为默认值
|
||||
*
|
||||
* @param ADCx 外设入口地址
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS ADC配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ADC_DeInit(ADC_Type *ADCx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口合法性检查 */
|
||||
assert_param(IS_FL_ADC_INSTANCE(ADCx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ADC);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ADC);
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ADCCR);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ADCCR);
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 初始化ADCx指定的入口地址的外设寄存器
|
||||
*
|
||||
* @note 用户必须检查此函数的返回值，以确保自校准完成，否则转换结果精度无法保证，除此之外ADC使能过采样实际不会增加ADC的
|
||||
* 转换精度只会提高转换结果的稳定性（同时配置移位寄存器的情况下），同时过采样会降低转换速度。
|
||||
* @param ADCx 外设入口地址
|
||||
* @param ADC_InitStruct 指向一 @ref FL_ADC_InitTypeDef 结构体，它包含指定ADC外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS ADC配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ADC_Init(ADC_Type *ADCx, FL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
uint32_t i = 0,Calibration_Flag;
|
||||
/* 入口合法性检查 */
|
||||
assert_param(IS_FL_ADC_INSTANCE(ADCx));
|
||||
assert_param(IS_FL_ADC_CONTINUOUSCONVMODE(ADC_InitStruct->conversionMode));
|
||||
assert_param(IS_FL_ADC_AUTO_MODE(ADC_InitStruct->autoMode));
|
||||
assert_param(IS_FL_ADC_SCANDIRECTION(ADC_InitStruct->scanDirection));
|
||||
assert_param(IS_FL_ADC_EXTERNALTRIGCONV(ADC_InitStruct->externalTrigConv));
|
||||
assert_param(IS_FL_ADC_OVERSAMPCOFIG(ADC_InitStruct->oversamplingMode));
|
||||
assert_param(IS_FL_ADC_OVERSAMPINGRATIO(ADC_InitStruct->overSampingMultiplier));
|
||||
assert_param(IS_FL_ADC_OVERSAMPINGSHIFT(ADC_InitStruct->oversamplingShift));
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_VREF1P2);
|
||||
if(!FL_VREF_IsEnabled(VREF))
|
||||
{
|
||||
FL_VREF_ClearFlag_Ready(VREF);
|
||||
FL_VREF_Enable(VREF);//置位VREF_EN寄存器，使能VREF1p2模块
|
||||
}
|
||||
FL_VREF_EnableTemperatureSensor(VREF);//置位PTAT_EN寄存器
|
||||
while(FL_VREF_IsActiveFlag_Ready(VREF) == 0) /* 等待VREF建立 */
|
||||
{
|
||||
if(i >= 128000)
|
||||
{
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
FL_ADC_Disable(ADCx);
|
||||
FL_ADC_DisableOverSampling(ADCx);
|
||||
FL_ADC_Enable(ADCx);
|
||||
FL_ADC_EnableCalibration(ADC);
|
||||
|
||||
i = 0;
|
||||
do
|
||||
{
|
||||
Calibration_Flag = FL_ADC_IsActiveFlag_EndOfCalibration(ADC);
|
||||
i++;
|
||||
}while((i != 0xFFFFFFFFU) && (Calibration_Flag == 0U)); //等待转换完成
|
||||
|
||||
if(Calibration_Flag == 0x01)
|
||||
{
|
||||
FL_ADC_ClearFlag_EndOfCalibration(ADC);
|
||||
/* 关闭ADC，关闭后ADC自校准值依然保持 */
|
||||
FL_ADC_Disable(ADCx);
|
||||
if(FL_ADC_IsEnabled(ADCx) == 0U)
|
||||
{
|
||||
/* 连续转换模式 */
|
||||
FL_ADC_SetConversionMode(ADCx, ADC_InitStruct->conversionMode);
|
||||
/* 自动转换模式 */
|
||||
FL_ADC_SetSingleConversionAutoMode(ADCx, ADC_InitStruct->autoMode);
|
||||
/* 通道等待使能 */
|
||||
if(ADC_InitStruct->waitMode)
|
||||
{
|
||||
FL_ADC_EnableWaitMode(ADCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ADC_DisableWaitMode(ADCx);
|
||||
}
|
||||
/*数据冲突模式设置*/
|
||||
if(ADC_InitStruct->overrunMode)
|
||||
{
|
||||
FL_ADC_EnableOverrunMode(ADCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ADC_DisableOverrunMode(ADCx);
|
||||
}
|
||||
/* 多通道扫描方向 */
|
||||
FL_ADC_SetSequenceScanDirection(ADCx, ADC_InitStruct->scanDirection);
|
||||
/* 外部引脚触发 */
|
||||
FL_ADC_DisableExternalConversion(ADCx);
|
||||
/* 触发模式 */
|
||||
FL_ADC_SetTriggerEdge(ADCx, ADC_InitStruct->externalTrigConv);
|
||||
/* 触发源 */
|
||||
FL_ADC_SetTriggerSource(ADCx, ADC_InitStruct->triggerSource);
|
||||
/*通道采样时间设置*/
|
||||
FL_ADC_SetFastChannelSamplingTime(ADCx, ADC_InitStruct->fastChannelTime);
|
||||
FL_ADC_SetSlowChannelSamplingTime(ADCx, ADC_InitStruct->lowChannelTime);
|
||||
if(ADC_InitStruct->oversamplingMode)
|
||||
{
|
||||
/*使能过采样倍数后，需要配置移位寄存器进行移位，这一过程是硬件自动完成的最终最大
|
||||
可输出16位的结果值（即256被采样得到的结果是20bit的，右移4bit结果就是16bit的）*/
|
||||
FL_ADC_SetOverSamplingMultiplier(ADCx, ADC_InitStruct->overSampingMultiplier);
|
||||
FL_ADC_SetOverSamplingShift(ADCx, ADC_InitStruct->oversamplingShift);
|
||||
/* 过采样使能 */
|
||||
FL_ADC_EnableOverSampling(ADCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 关闭过采样 */
|
||||
FL_ADC_DisableOverSampling(ADCx);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = FL_FAIL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = FL_FAIL;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 ADC_InitStruct 为默认配置
|
||||
* @param ADC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ADC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ADC_StructInit(FL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
{
|
||||
ADC_InitStruct->conversionMode = FL_ADC_CONV_MODE_SINGLE;
|
||||
ADC_InitStruct->autoMode = FL_ADC_SINGLE_CONV_MODE_AUTO;
|
||||
ADC_InitStruct->scanDirection = FL_ADC_SEQ_SCAN_DIR_FORWARD;
|
||||
ADC_InitStruct->externalTrigConv = FL_ADC_TRIGGER_EDGE_NONE;
|
||||
ADC_InitStruct->overrunMode = FL_ENABLE;
|
||||
ADC_InitStruct->waitMode = FL_ENABLE;
|
||||
ADC_InitStruct->fastChannelTime = FL_ADC_FAST_CH_SAMPLING_TIME_2_ADCCLK;
|
||||
ADC_InitStruct->lowChannelTime = FL_ADC_SLOW_CH_SAMPLING_TIME_512_ADCCLK;
|
||||
ADC_InitStruct->oversamplingMode = FL_ENABLE;
|
||||
ADC_InitStruct->overSampingMultiplier = FL_ADC_OVERSAMPLING_MUL_16X;
|
||||
ADC_InitStruct->oversamplingShift = FL_ADC_OVERSAMPLING_SHIFT_4B;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_ADC_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
|
||||
|
||||
155
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_aes.c
Normal file
155
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_aes.c
Normal file
@ -0,0 +1,155 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_aes.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of AES FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0xx_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_AES_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup AES_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_AES_INSTANCE(INSTANCE) (((INSTANCE) == AES))
|
||||
|
||||
#define IS_FL_AES_KEYLENTH(__VALUE__) (((__VALUE__) == FL_AES_KEY_LENGTH_128B)||\
|
||||
((__VALUE__) == FL_AES_KEY_LENGTH_192B)||\
|
||||
((__VALUE__) == FL_AES_KEY_LENGTH_256B))
|
||||
|
||||
#define IS_FL_AES_CIPHERMODE(__VALUE__) (((__VALUE__) == FL_AES_CIPHER_ECB)||\
|
||||
((__VALUE__) == FL_AES_CIPHER_CBC)||\
|
||||
((__VALUE__) == FL_AES_CIPHER_CTR)||\
|
||||
((__VALUE__) == FL_AES_CIPHER_MULTH))
|
||||
|
||||
#define IS_FL_AES_OPERATIONMODE(__VALUE__) (((__VALUE__) == FL_AES_OPERATION_MODE_ENCRYPTION)||\
|
||||
((__VALUE__) == FL_AES_OPERATION_MODE_KEYDERIVATION)||\
|
||||
((__VALUE__) == FL_AES_OPERATION_MODE_DECRYPTION)||\
|
||||
((__VALUE__) == FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION))
|
||||
|
||||
#define IS_FL_AES_DATATYPE(__VALUE__) (((__VALUE__) == FL_AES_DATA_TYPE_32B)||\
|
||||
((__VALUE__) == FL_AES_DATA_TYPE_16B)||\
|
||||
((__VALUE__) == FL_AES_DATA_TYPE_8B)||\
|
||||
((__VALUE__) == FL_AES_DATA_TYPE_1B))
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup AES_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位AES 外设寄存器值为复位值
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_AES_DeInit(void)
|
||||
{
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位AES */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_AES);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_AES);
|
||||
/* 关闭总线时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_AES);
|
||||
/* 锁定外设复位功能 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 AES_InitStructer初始化对应外设入口地址的寄存器值.
|
||||
*
|
||||
* @param AESx 外设入口地址
|
||||
* @param AES_InitStructer 指向 @ref FL_AES_InitTypeDef 结构体的指针
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_AES_Init(AES_Type *AESx, FL_AES_InitTypeDef *AES_InitStructer)
|
||||
{
|
||||
/* 入口合法性检查 */
|
||||
assert_param(IS_FL_AES_INSTANCE(AESx));
|
||||
assert_param(IS_FL_AES_KEYLENTH(AES_InitStructer->keyLength));
|
||||
assert_param(IS_FL_AES_CIPHERMODE(AES_InitStructer->cipherMode));
|
||||
assert_param(IS_FL_AES_OPERATIONMODE(AES_InitStructer->operationMode));
|
||||
assert_param(IS_FL_AES_DATATYPE(AES_InitStructer->dataType));
|
||||
if(FL_AES_IsEnabled(AESx) == 0)
|
||||
{
|
||||
/* 开启总线时钟 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_AES);
|
||||
/* key长度 */
|
||||
FL_AES_SetKeySize(AESx, AES_InitStructer->keyLength);
|
||||
/* 数据流处理模式 */
|
||||
FL_AES_SetCipherMode(AESx, AES_InitStructer->cipherMode);
|
||||
/* 操作模式 */
|
||||
FL_AES_SetOperationMode(AESx, AES_InitStructer->operationMode);
|
||||
/* 数据类型 */
|
||||
FL_AES_SetDataType(AESx, AES_InitStructer->dataType);
|
||||
}
|
||||
else
|
||||
{
|
||||
return FL_FAIL;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 AES_InitStruct 为默认配置
|
||||
*
|
||||
* @param AES_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_AES_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_AES_StructInit(FL_AES_InitTypeDef *AES_InitStructer)
|
||||
{
|
||||
AES_InitStructer->keyLength = FL_AES_KEY_LENGTH_128B;
|
||||
AES_InitStructer->cipherMode = FL_AES_CIPHER_ECB;
|
||||
AES_InitStructer->operationMode = FL_AES_OPERATION_MODE_ENCRYPTION;
|
||||
AES_InitStructer->dataType = FL_AES_DATA_TYPE_32B;
|
||||
}
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
#endif /* FL_AES_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/*********************** (C) COPYRIGHT Fudan Microelectronics *****END OF FILE************************/
|
||||
760
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_atim.c
Normal file
760
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_atim.c
Normal file
@ -0,0 +1,760 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_atim.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of ATIM FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ATIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_ATIM_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup ATIM_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define IS_ATIM_INSTANCE(TIMx) ((TIMx) == ATIM)
|
||||
|
||||
#define IS_ATIM_CLKSRC(__VALUE__) (((__VALUE__) == FL_CMU_ATIM_CLK_SOURCE_APBCLK) \
|
||||
|| ((__VALUE__) == FL_CMU_ATIM_CLK_SOURCE_PLL_X2))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_COUNTERMODE(__VALUE__) (((__VALUE__) == FL_ATIM_COUNTER_DIR_UP) \
|
||||
|| ((__VALUE__) == FL_ATIM_COUNTER_DIR_DOWN) \
|
||||
|| ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN ) \
|
||||
|| ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_UP ) \
|
||||
|| ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN))
|
||||
|
||||
#define IS_FL_ATIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV1) \
|
||||
|| ((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV2) \
|
||||
|| ((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV4))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_CC_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_MODE_OUTPUT) \
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER) \
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_TRC))
|
||||
|
||||
#define IS_FL_ATIM_IC_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_IC_FILTER_DIV1 ) \
|
||||
|| ((__VALUE__) ==FL_ATIM_IC_FILTER_DIV1_N2) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV1_N4) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV1_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV2_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV2_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV4_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV4_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV8_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV8_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N8))
|
||||
|
||||
#define IS_FL_ATIM_CHANNEL(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_1)\
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_2)\
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_3)\
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_4))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_SLAVE_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_SLAVE_MODE_PROHIBITED)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X2_TI1)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X2_TI2)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X4_TI1TI2)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_RISE_RST)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_HIGH_RUN)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_RISE_RUN)\
|
||||
|| ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_CLK))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_TRIGGER_SRC(__VALUE__) (((__VALUE__) == FL_ATIM_TRGI_ITR0 )\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_ITR1 )\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_ITR2)\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_ITR3)\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_TI1F_EDGE)\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_TI1FP1)\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_TI2FP2)\
|
||||
||((__VALUE__) ==FL_ATIM_TRGI_ETRF))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_ETP_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N2) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N4) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV2_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV2_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV4_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV4_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV8_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV8_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N8))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_ETR_PSC(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_PSC_DIV1) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_PSC_DIV2) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_PSC_DIV4) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_PSC_DIV8))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_ETR_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_ETR_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_IC_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_IC_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_IC_ACTIVEINPUT(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER) \
|
||||
|| ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_TRC))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_IC_PRESCALER(__VALUE__) (((__VALUE__) == FL_ATIM_IC_PSC_DIV1) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_PSC_DIV2) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_PSC_DIV4) \
|
||||
|| ((__VALUE__) == FL_ATIM_IC_PSC_DIV8))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_OC_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_OC_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_OC_MODE_FROZEN) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_ACTIVE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_INACTIVE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_TOGGLE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_FORCED_INACTIVE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_FORCED_ACTIVE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_PWM1) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_MODE_PWM2))
|
||||
|
||||
#define IS_FL_ATIM_AUTORELOAB_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OC_FASTMODE(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OC_PRELOAD(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OC_ETR_CLEARN(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OCN_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE)\
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OC_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE)\
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_ATIM_OC_IDLESTATE(__VALUE__) (((__VALUE__) == FL_ATIM_OC_IDLE_STATE_LOW) \
|
||||
|| ((__VALUE__) == FL_ATIM_OC_IDLE_STATE_HIGH))
|
||||
|
||||
#define IS_FL_ATIM_OC_NIDLESTATE(__VALUE__) (((__VALUE__) == FL_ATIM_OCN_IDLE_STATE_LOW) \
|
||||
|| ((__VALUE__) == FL_ATIM_OCN_IDLE_STATE_HIGH))
|
||||
|
||||
|
||||
#define IS_FL_ATIM_OC_NPOLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_OCN_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_ATIM_OCN_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_ATIM_BDTR_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N2) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N4) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV2_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV2_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV4_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV4_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV8_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV8_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N8) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N5) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N6) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N8))
|
||||
|
||||
#define IS_FL_ATIM_OSSR_STATE(__VALUE__) (((__VALUE__) == FL_ATIM_OSSR_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OSSR_ENABLE))
|
||||
|
||||
#define IS_FL_ATIM_OSSI_STATE(__VALUE__) (((__VALUE__) == FL_ATIM_OSSI_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ATIM_OSSI_ENABLE))
|
||||
|
||||
#define IS_FL_ATIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == FL_ATIM_LOCK_LEVEL_OFF) \
|
||||
|| ((__VALUE__) == FL_ATIM_LOCK_LEVEL_1) \
|
||||
|| ((__VALUE__) == FL_ATIM_LOCK_LEVEL_2) \
|
||||
|| ((__VALUE__) == FL_ATIM_LOCK_LEVEL_3))
|
||||
|
||||
#define IS_FL_ATIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_BREAK_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == FL_ATIM_BREAK_POLARITY_HIGH))
|
||||
|
||||
#define IS_FL_ATIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_ATIM_TRIGGER_DELAY(__VALUE__) (((__VALUE__) == FL_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_ATIM_IC_CAPTURE_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup TIM_FL_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
static FL_ErrorStatus OCConfig(ATIM_Type *TIMx, uint32_t Channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIM_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应ATIMx寄存器.
|
||||
* @param ATIMx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_DeInit(ATIM_Type *TIMx)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ATIM_INSTANCE(TIMx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位ATIM外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ATIM);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_ATIM);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_ATIM);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ATIM);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 配置基本定时器时基单元（内部时钟源）.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_InitStruct 指向一个 @ref FL_ATIM_InitTypeDef(时基配置结构体)
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_ATIM_Init(ATIM_Type *TIMx, FL_ATIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
uint32_t i = 5;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_ATIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_ATIM_COUNTERMODE(TIM_InitStruct->counterMode));
|
||||
assert_param(IS_FL_ATIM_CLOCKDIVISION(TIM_InitStruct->clockDivision));
|
||||
assert_param(IS_FL_ATIM_AUTORELOAB_STATE(TIM_InitStruct->autoReloadState));
|
||||
assert_param(IS_ATIM_CLKSRC(TIM_InitStruct->clockSource));
|
||||
/* 时钟总线使能配置 */
|
||||
FL_CMU_SetATIMClockSource(TIM_InitStruct->clockSource);
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_ATIM);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ATIM);
|
||||
/* 设置重复计数值 */
|
||||
FL_ATIM_WriteRepetitionCounter(TIMx, TIM_InitStruct->repetitionCounter);
|
||||
/* 计数器计数模式配置 */
|
||||
switch(TIM_InitStruct->counterMode)
|
||||
{
|
||||
/* 中心对称模式 */
|
||||
case FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN :
|
||||
case FL_ATIM_COUNTER_ALIGNED_CENTER_UP :
|
||||
case FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN:
|
||||
FL_ATIM_SetCounterDirection(TIMx,FL_ATIM_COUNTER_DIR_UP);
|
||||
FL_ATIM_SetCounterAlignedMode(TIMx, TIM_InitStruct->counterMode);
|
||||
break;
|
||||
default:
|
||||
/* 边沿模式 */
|
||||
FL_ATIM_SetCounterDirection(TIMx, TIM_InitStruct->counterMode);
|
||||
FL_ATIM_SetCounterAlignedMode(TIMx, FL_ATIM_COUNTER_ALIGNED_EDGE);
|
||||
break;
|
||||
}
|
||||
/* 自动重装载值 */
|
||||
FL_ATIM_WriteAutoReload(TIMx, TIM_InitStruct->autoReload);
|
||||
/* 定时器分频系数与数字滤波器所使用的采样时钟分频比 */
|
||||
FL_ATIM_SetClockDivision(TIMx, TIM_InitStruct->clockDivision);
|
||||
/* 时钟分频 */
|
||||
FL_ATIM_WritePrescaler(TIMx, TIM_InitStruct->prescaler);
|
||||
/* 预装载配置 */
|
||||
if(TIM_InitStruct->autoReloadState == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_EnableARRPreload(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_DisableARRPreload(TIMx);
|
||||
}
|
||||
/* 手动触发更新事件，将配置值写入 */
|
||||
FL_ATIM_GenerateUpdateEvent(TIMx);
|
||||
while((!FL_ATIM_IsActiveFlag_Update(ATIM))&&i)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
/*清除UIF标志，防止产生UG事件中断*/
|
||||
FL_ATIM_ClearFlag_Update(ATIM);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 FL_ATIM_InitTypeDef 为默认配置
|
||||
* @param TIM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ATIM_StructInit(FL_ATIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_InitStruct->clockSource = FL_CMU_ATIM_CLK_SOURCE_APBCLK;
|
||||
TIM_InitStruct->prescaler = (uint16_t)0x0000;
|
||||
TIM_InitStruct->counterMode = FL_ATIM_COUNTER_DIR_UP;
|
||||
TIM_InitStruct->autoReload = 0xFFFFU;
|
||||
TIM_InitStruct->clockDivision = FL_ATIM_CLK_DIVISION_DIV1;
|
||||
TIM_InitStruct->repetitionCounter = 0;
|
||||
TIM_InitStruct->autoReloadState = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置基本定时器从模式，包括编码器模式.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_InitStruct 指向一个 @ref FL_ATIM_SlaveInitTypeDef 结构体
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_SlaveMode_Init(ATIM_Type *TIMx, FL_ATIM_SlaveInitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_ATIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_ATIM_TRIGGER_DELAY(TIM_InitStruct->triggerDelay));
|
||||
assert_param(IS_FL_ATIM_TRIGGER_SRC(TIM_InitStruct->triggerSrc));
|
||||
assert_param(IS_FL_ATIM_SLAVE_MODE(TIM_InitStruct->slaveMode));
|
||||
/* 时钟总线使能配置 */
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_ATIM);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ATIM);
|
||||
/* 触发延迟默认关闭 */
|
||||
FL_ATIM_DisableMasterSlaveMode(TIMx);
|
||||
/* 关闭从模式以能写入TS */
|
||||
FL_ATIM_SetSlaveMode(TIMx, 0);
|
||||
/* 从模式输入源选择 */
|
||||
FL_ATIM_SetTriggerInput(TIMx, TIM_InitStruct->triggerSrc);
|
||||
/* 从模式选择 */
|
||||
FL_ATIM_SetSlaveMode(TIMx, TIM_InitStruct->slaveMode);
|
||||
/* 触发延迟默认关闭 */
|
||||
if(TIM_InitStruct->triggerDelay == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_EnableMasterSlaveMode(TIMx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 FL_ATIM_SlaveInitTypeDef 为默认配置
|
||||
* @param TIM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_SlaveInitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ATIM_SlaveModeStructInit(FL_ATIM_SlaveInitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
TIM_InitStruct->slaveMode = FL_ATIM_SLAVE_MODE_PROHIBITED;
|
||||
TIM_InitStruct->triggerSrc = FL_ATIM_TRGI_TI1FP1;
|
||||
TIM_InitStruct->triggerDelay = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置TIM的输入捕获通道.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_ATIM_CHANNEL_0
|
||||
* @arg @ref FL_ATIM_CHANNEL_1
|
||||
* @arg @ref FL_ATIM_CHANNEL_2
|
||||
* @arg @ref FL_ATIM_CHANNEL_3
|
||||
* @param TIM_IC_InitStruct 指向一个 @ref FL_ATIM_IC_InitTypeDef 结构体
|
||||
* @retval TIM_OC_InitStruct pointer to a @ref FL_ATIM_OC_InitTypeDef structure
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_IC_Init(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_IC_InitTypeDef *IC_InitStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_ATIM_CHANNEL(channel));
|
||||
assert_param(IS_FL_ATIM_IC_CAPTURE_STATE(IC_InitStruct->captureState));
|
||||
assert_param(IS_FL_ATIM_IC_POLARITY(IC_InitStruct->ICPolarity));
|
||||
assert_param(IS_FL_ATIM_IC_ACTIVEINPUT(IC_InitStruct->ICActiveInput));
|
||||
assert_param(IS_FL_ATIM_IC_PRESCALER(IC_InitStruct->ICPrescaler));
|
||||
assert_param(IS_FL_ATIM_IC_FILTER(IC_InitStruct->ICFilter));
|
||||
/* 时钟总线使能配置 */
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_ATIM);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ATIM);
|
||||
/* 通道关闭 */
|
||||
FL_ATIM_OC_DisableChannel(TIMx, channel);
|
||||
/*捕获极性 */
|
||||
FL_ATIM_IC_SetChannelPolarity(TIMx, IC_InitStruct->ICPolarity, channel);
|
||||
/* 捕获映射通道 */
|
||||
FL_ATIM_CC_SetChannelMode(TIMx, IC_InitStruct->ICActiveInput, channel);
|
||||
/* 捕获预分频 */
|
||||
FL_ATIM_IC_SetPrescaler(TIMx, IC_InitStruct->ICPrescaler, channel);
|
||||
/* 捕获滤波器 */
|
||||
FL_ATIM_IC_SetFilter(TIMx, IC_InitStruct->ICFilter, channel);
|
||||
if(IC_InitStruct->captureState == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_IC_EnableChannel(TIMx, channel);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 FL_ATIM_IC_InitTypeDef 为默认配置
|
||||
* @param TIM_ICInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_IC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ATIM_IC_StructInit(FL_ATIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* 默认配置 */
|
||||
TIM_ICInitStruct->ICPolarity = FL_ATIM_IC_POLARITY_NORMAL;
|
||||
TIM_ICInitStruct->ICActiveInput = FL_ATIM_CHANNEL_MODE_INPUT_NORMAL;
|
||||
TIM_ICInitStruct->ICPrescaler = FL_ATIM_IC_PSC_DIV1;
|
||||
TIM_ICInitStruct->ICFilter = FL_ATIM_IC_FILTER_DIV1;
|
||||
TIM_ICInitStruct->captureState = FL_DISABLE;
|
||||
}
|
||||
/**
|
||||
* @brief 配置TIM触发输入捕获通道ETR.
|
||||
* @param TIMx Timer Instance
|
||||
* @param ETPolarity 极性
|
||||
* @param ETPrescaler 分频
|
||||
* @param ETR_Filter 滤波
|
||||
* @param TIM_IC_InitStruct 指向一个 @ref FL_ATIM_IC_InitTypeDef 结构体
|
||||
* @retval TIM_OC_InitStruct pointer to a @ref FL_ATIM_OC_InitTypeDef structure
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_ETR_Init(ATIM_Type *TIMx, FL_ATIM_ETR_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
assert_param(IS_FL_ATIM_ETP_FILTER(TIM_InitStruct->ETRFilter));
|
||||
assert_param(IS_FL_ATIM_ETR_PSC(TIM_InitStruct->ETRClockDivision));
|
||||
assert_param(IS_FL_ATIM_ETR_POLARITY(TIM_InitStruct->ETRPolarity));
|
||||
/* 时钟总线使能配置 */
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_ATIM);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_ATIM);
|
||||
/* 外部时钟极性 */
|
||||
FL_ATIM_SetETRPolarity(TIMx, TIM_InitStruct->ETRPolarity);
|
||||
/* 外部时钟滤波 */
|
||||
FL_ATIM_SetETRFilter(TIMx, TIM_InitStruct->ETRFilter);
|
||||
/* 外部时钟分频 */
|
||||
FL_ATIM_SetETRPrescaler(TIMx, TIM_InitStruct->ETRClockDivision);
|
||||
if(TIM_InitStruct->useExternalTrigger == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_EnableExternalClock(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_DisableExternalClock(TIMx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
void FL_ATIM_ETRStructInit(FL_ATIM_ETR_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
TIM_InitStruct->useExternalTrigger = FL_DISABLE;
|
||||
TIM_InitStruct->ETRFilter = FL_ATIM_ETR_FILTER_DIV1;
|
||||
TIM_InitStruct->ETRPolarity = FL_ATIM_ETR_POLARITY_NORMAL;
|
||||
TIM_InitStruct->ETRClockDivision = FL_ATIM_ETR_PSC_DIV1;
|
||||
}
|
||||
/**
|
||||
* @brief 配置
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_ATIM_CHANNEL_1
|
||||
* @arg @ref FL_ATIM_CHANNEL_2
|
||||
* @arg @ref FL_ATIM_CHANNEL_3
|
||||
* @arg @ref FL_ATIM_CHANNEL_4
|
||||
* @param TIM_ICInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_IC_InitTypeDef 结构体包含配置参数.
|
||||
* @retval None
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
static FL_ErrorStatus OCConfig(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 配置比较输出通道模式 */
|
||||
FL_ATIM_OC_SetMode(TIMx, TIM_OC_InitStruct->OCMode, channel);
|
||||
/* 配置TRF清零使能 */
|
||||
if(TIM_OC_InitStruct->OCETRFStatus == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_OC_EnableClear(TIMx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_OC_DisableClear(TIMx, channel);
|
||||
}
|
||||
/* 比较输出通道快速模式 */
|
||||
if(TIM_OC_InitStruct->OCFastMode == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_OC_EnableFastMode(TIMx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_OC_DisableFastMode(TIMx, channel);
|
||||
}
|
||||
/* 比较输出通道缓冲模式 */
|
||||
if(TIM_OC_InitStruct->OCPreload == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_OC_EnablePreload(TIMx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_OC_DisablePreload(TIMx, channel);
|
||||
}
|
||||
if(TIM_OC_InitStruct->OCNState == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_OC_EnableReverseChannel(TIMx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_OC_DisableReverseChannel(TIMx, channel);
|
||||
}
|
||||
if(TIM_OC_InitStruct->OCState == FL_ENABLE)
|
||||
{
|
||||
/* 通道使能 */
|
||||
FL_ATIM_OC_EnableChannel(TIMx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_OC_DisableChannel(TIMx, channel);
|
||||
}
|
||||
/* 设置比较值 */
|
||||
switch(channel)
|
||||
{
|
||||
case FL_ATIM_CHANNEL_1:
|
||||
FL_ATIM_WriteCompareCH1(TIMx, TIM_OC_InitStruct->compareValue);
|
||||
break;
|
||||
case FL_ATIM_CHANNEL_2:
|
||||
FL_ATIM_WriteCompareCH2(TIMx, TIM_OC_InitStruct->compareValue);
|
||||
break;
|
||||
case FL_ATIM_CHANNEL_3:
|
||||
FL_ATIM_WriteCompareCH3(TIMx, TIM_OC_InitStruct->compareValue);
|
||||
break;
|
||||
case FL_ATIM_CHANNEL_4:
|
||||
FL_ATIM_WriteCompareCH4(TIMx, TIM_OC_InitStruct->compareValue);
|
||||
break;
|
||||
default :
|
||||
result = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 配置TIM的比较输出通道.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_ATIM_CHANNEL_1
|
||||
* @arg @ref FL_ATIM_CHANNEL_2
|
||||
* @arg @ref FL_ATIM_CHANNEL_3
|
||||
* @arg @ref FL_ATIM_CHANNEL_4
|
||||
* @retval TIM_OC_InitStruct pointer to a @ref FL_ATIM_OC_InitTypeDef structure
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_OC_Init(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
{
|
||||
uint32_t i = 5;
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_ATIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_ATIM_OC_MODE(TIM_OC_InitStruct->OCMode));
|
||||
assert_param(IS_FL_ATIM_OC_PRELOAD(TIM_OC_InitStruct->OCPreload));
|
||||
assert_param(IS_FL_ATIM_OC_POLARITY(TIM_OC_InitStruct->OCPolarity));
|
||||
assert_param(IS_FL_ATIM_OC_FASTMODE(TIM_OC_InitStruct->OCFastMode));
|
||||
assert_param(IS_FL_ATIM_OC_ETR_CLEARN(TIM_OC_InitStruct->OCETRFStatus));
|
||||
assert_param(IS_FL_ATIM_OCN_STATE(TIM_OC_InitStruct->OCNState));
|
||||
assert_param(IS_FL_ATIM_OC_STATE(TIM_OC_InitStruct->OCState));
|
||||
assert_param(IS_FL_ATIM_OC_IDLESTATE(TIM_OC_InitStruct->OCIdleState));
|
||||
assert_param(IS_FL_ATIM_OC_NIDLESTATE(TIM_OC_InitStruct->OCNIdleState));
|
||||
assert_param(IS_FL_ATIM_OC_NPOLARITY(TIM_OC_InitStruct->OCNPolarity));
|
||||
/* 通道关闭 */
|
||||
FL_ATIM_OC_DisableChannel(TIMx, channel);
|
||||
FL_ATIM_OC_DisableReverseChannel(TIMx, channel);
|
||||
/* 通道极性 */
|
||||
FL_ATIM_OC_SetChannelPolarity(TIMx, TIM_OC_InitStruct->OCPolarity, channel);
|
||||
/* 通道空闲电平 */
|
||||
FL_ATIM_OC_SetChannelIdleState(TIMx, TIM_OC_InitStruct->OCIdleState, channel);
|
||||
/* 互补通道空闲电平 */
|
||||
FL_ATIM_OC_SetReverseChannelIdleState(TIMx, TIM_OC_InitStruct->OCNIdleState, channel);
|
||||
/* 互补通道极性 */
|
||||
FL_ATIM_OC_SetReverseChannelPolarity(TIMx, TIM_OC_InitStruct->OCNPolarity, channel);
|
||||
/* 捕获映射到输出通道 */
|
||||
FL_ATIM_CC_SetChannelMode(TIMx, FL_ATIM_CHANNEL_MODE_OUTPUT, channel);
|
||||
/* 输出比较模式寄存器配置 */
|
||||
OCConfig(TIMx, channel, TIM_OC_InitStruct);
|
||||
/* 手动触发更新事件，将配置值写入 */
|
||||
FL_ATIM_GenerateUpdateEvent(TIMx);
|
||||
while((!FL_ATIM_IsActiveFlag_Update(ATIM))&&i)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
/*清除UIF标志，防止产生UG事件中断*/
|
||||
FL_ATIM_ClearFlag_Update(ATIM);
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 FL_ATIM_OC_InitTypeDef 为默认配置
|
||||
* @param TIM_OC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_OC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ATIM_OC_StructInit(FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_OC_InitStruct->OCMode = FL_ATIM_OC_MODE_FROZEN;
|
||||
TIM_OC_InitStruct->OCETRFStatus = FL_DISABLE;
|
||||
TIM_OC_InitStruct->OCFastMode = FL_DISABLE;
|
||||
TIM_OC_InitStruct->compareValue = 0x00000000U;
|
||||
TIM_OC_InitStruct->OCPolarity = FL_ATIM_OC_POLARITY_NORMAL;
|
||||
TIM_OC_InitStruct->OCPreload = FL_DISABLE;
|
||||
TIM_OC_InitStruct->OCIdleState = FL_ATIM_OC_IDLE_STATE_LOW;
|
||||
TIM_OC_InitStruct->OCNIdleState = FL_ATIM_OCN_IDLE_STATE_LOW;
|
||||
TIM_OC_InitStruct->OCNPolarity = FL_ATIM_OCN_POLARITY_NORMAL;
|
||||
TIM_OC_InitStruct->OCNState = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置TIM的输入捕获通道.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_IC_InitStruct 指向一个 @ref FL_ATIM_IC_InitTypeDef 结构体
|
||||
* @retval TIM_OC_InitStruct pointer to a @ref FL_ATIM_OC_InitTypeDef structure
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_ATIM_BDTR_Init(ATIM_Type *TIMx, FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_ATIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_ATIM_OSSR_STATE(TIM_BDTR_InitStruct->OSSRState));
|
||||
assert_param(IS_FL_ATIM_OSSI_STATE(TIM_BDTR_InitStruct->OSSIState));
|
||||
assert_param(IS_FL_ATIM_LOCK_LEVEL(TIM_BDTR_InitStruct->lockLevel));
|
||||
assert_param(IS_FL_ATIM_BREAK_POLARITY(TIM_BDTR_InitStruct->breakPolarity));
|
||||
assert_param(IS_FL_ATIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTR_InitStruct->automaticOutput));
|
||||
assert_param(IS_FL_ATIM_BDTR_FILTER(TIM_BDTR_InitStruct->breakFilter));
|
||||
/* 关闭所有输出 */
|
||||
FL_ATIM_DisableALLOutput(TIMx);
|
||||
/* 设置死区时间 */
|
||||
FL_ATIM_WriteDeadTime(TIMx, TIM_BDTR_InitStruct->deadTime);
|
||||
/* 设置寄存器锁定等级 */
|
||||
FL_ATIM_SetLockLevel(TIMx, TIM_BDTR_InitStruct->lockLevel);
|
||||
/* Idle状态下关闭状态 */
|
||||
FL_ATIM_SetOffStateIdle(TIMx, TIM_BDTR_InitStruct->OSSIState);
|
||||
/* run状态下关闭状态 */
|
||||
FL_ATIM_SetOffStateRun(TIMx, TIM_BDTR_InitStruct->OSSRState);
|
||||
/* 门控1刹车信号 */
|
||||
FL_ATIM_SetBreak1GateState(TIMx, TIM_BDTR_InitStruct->gatedBrakeSignal_1);
|
||||
/* 门控2刹车信号 */
|
||||
FL_ATIM_SetBreak2GateState(TIMx, TIM_BDTR_InitStruct->gatedBrakeSignal_2);
|
||||
/* 门控刹车信号组合方式设置 */
|
||||
FL_ATIM_SetBreakSignalCombination(TIMx, TIM_BDTR_InitStruct->brakeSignalCombined);
|
||||
/* 刹车极性设置 */
|
||||
FL_ATIM_SetBreakPolarity(TIMx, TIM_BDTR_InitStruct->breakPolarity);
|
||||
/* 更新时间自动设置输出配置，如果刹车事件发生过并且当前功能使能，则下一个更新事件将重新自动输出 */
|
||||
if(TIM_BDTR_InitStruct->automaticOutput == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_EnableAutomaticOutput(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_DisableAutomaticOutput(TIMx);
|
||||
}
|
||||
/* 刹车功能开关配置 */
|
||||
if(TIM_BDTR_InitStruct->breakState == FL_ENABLE)
|
||||
{
|
||||
FL_ATIM_EnableBreak(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_ATIM_DisableBreak(TIMx);
|
||||
}
|
||||
/* 使能全部输出 */
|
||||
FL_ATIM_EnableALLOutput(TIMx);
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 FL_ATIM_IC_InitTypeDef 为默认配置
|
||||
* @param TIM_ICInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ATIM_IC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_ATIM_BDTR_StructInit(FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct)
|
||||
{
|
||||
TIM_BDTR_InitStruct->deadTime = 0x00;
|
||||
TIM_BDTR_InitStruct->lockLevel = FL_ATIM_LOCK_LEVEL_OFF;
|
||||
TIM_BDTR_InitStruct->OSSRState = FL_ATIM_OSSR_DISABLE;
|
||||
TIM_BDTR_InitStruct->OSSIState = FL_ATIM_OSSI_DISABLE;
|
||||
TIM_BDTR_InitStruct->breakFilter = FL_ATIM_BREAK_FILTER_DIV1;
|
||||
TIM_BDTR_InitStruct->breakPolarity = FL_ATIM_BREAK_POLARITY_LOW;
|
||||
TIM_BDTR_InitStruct->automaticOutput = FL_DISABLE;
|
||||
TIM_BDTR_InitStruct->gatedBrakeSignal_1 = FL_ATIM_BREAK1_GATE_AUTO;
|
||||
TIM_BDTR_InitStruct->gatedBrakeSignal_2 = FL_ATIM_BREAK2_GATE_AUTO;
|
||||
TIM_BDTR_InitStruct->breakState = FL_DISABLE;
|
||||
TIM_BDTR_InitStruct->brakeSignalCombined = FL_ATIM_BREAK_COMBINATION_OR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_ATIM_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
157
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_bstim16.c
Normal file
157
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_bstim16.c
Normal file
@ -0,0 +1,157 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_bstim16.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of BSTIM FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BSTIM16
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_BSTIM16_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup BSTIM16_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_BSTIM16_INSTANCE(INTANCE) ((INTANCE) == BSTIM16)
|
||||
|
||||
#define IS_FL_BSTIM16_PSC(__VALUE__) ((__VALUE__) <= 0x0000FFFF)
|
||||
|
||||
#define IS_FL_BSTIM16_AUTORELOAD(__VALUE__) ((__VALUE__) <= 0x0000FFFF)
|
||||
|
||||
|
||||
#define IS_FL_BSTIM16_AUTORELOAD_MODE(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_BSTIM16_CLOCK_SRC(__VALUE__) (((__VALUE__) == FL_CMU_BSTIM16_CLK_SOURCE_APBCLK)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM16_CLK_SOURCE_RCLP)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM16_CLK_SOURCE_RCLF)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM16_CLK_SOURCE_LSCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup BSTIM16_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应BSTIM16寄存器.
|
||||
* @param BSTIMx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_BSTIM16_DeInit(BSTIM16_Type *BSTIM16x)
|
||||
{
|
||||
assert_param(IS_FL_BSTIM16_INSTANCE(BSTIM16x));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位IIC外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_BSTIM16);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_BSTIM16);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_BSTIM16);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_BSTIM16);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 BSTIM16_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param BSTIMx BSTIMx
|
||||
* @param BSTIM16_InitStruct 指向一个 @ref FL_BSTIM16_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_BSTIM16_Init(BSTIM16_Type *BSTIM16x, FL_BSTIM16_InitTypeDef *init)
|
||||
{
|
||||
uint32_t i = 5;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_BSTIM16_INSTANCE(BSTIM16x));
|
||||
assert_param(IS_FL_BSTIM16_CLOCK_SRC(init->clockSource));
|
||||
assert_param(IS_FL_BSTIM16_PSC(init->prescaler));
|
||||
assert_param(IS_FL_BSTIM16_AUTORELOAD(init->autoReload));
|
||||
assert_param(IS_FL_BSTIM16_AUTORELOAD_MODE(init->autoReloadState));
|
||||
/* 时钟使能 */
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_BSTIM16);
|
||||
/* 选择时钟源 */
|
||||
FL_CMU_SetBSTIM16ClockSource(init->clockSource);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_BSTIM16);
|
||||
/* 分频系数 */
|
||||
FL_BSTIM16_WritePrescaler(BSTIM16x, init->prescaler);
|
||||
/* 自动重装载值 */
|
||||
FL_BSTIM16_EnableUpdateEvent(BSTIM16x);
|
||||
FL_BSTIM16_WriteAutoReload(BSTIM16x, init->autoReload);
|
||||
if(init->autoReloadState == FL_ENABLE)
|
||||
{
|
||||
FL_BSTIM16_EnableARRPreload(BSTIM16x);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_BSTIM16_DisableARRPreload(BSTIM16x);
|
||||
}
|
||||
FL_BSTIM16_GenerateUpdateEvent(BSTIM16x);
|
||||
while((!FL_BSTIM16_IsActiveFlag_Update(BSTIM16x))&&i)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 BSTIM16_InitStruct 为默认配置
|
||||
* @param BSTIM16_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_BSTIM16_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_BSTIM16_StructInit(FL_BSTIM16_InitTypeDef *init)
|
||||
{
|
||||
init->prescaler = 0;
|
||||
init->autoReload = 0xFFFFFFFF;
|
||||
init->autoReloadState = FL_ENABLE;
|
||||
init->clockSource = FL_CMU_BSTIM16_CLK_SOURCE_APBCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_BSTIM16_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
151
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_bstim32.c
Normal file
151
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_bstim32.c
Normal file
@ -0,0 +1,151 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_bstim32.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of BSTIM FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BSTIM32
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_BSTIM32_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup BSTIM32_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_BSTIM32_INSTANCE(INTANCE) ((INTANCE) == BSTIM32)
|
||||
|
||||
|
||||
#define IS_FL_BSTIM32_AUTORELOAD_MODE(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_BSTIM32_CLOCK_SRC(__VALUE__) (((__VALUE__) == FL_CMU_BSTIM32_CLK_SOURCE_APBCLK)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM32_CLK_SOURCE_RCLP)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM32_CLK_SOURCE_RCLF)||\
|
||||
((__VALUE__) == FL_CMU_BSTIM32_CLK_SOURCE_LSCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup BSTIM_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应BSTIM寄存器.
|
||||
* @param BSTIMx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_BSTIM32_DeInit(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
assert_param(IS_FL_BSTIM32_INSTANCE(BSTIM32x));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_BSTIM32);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_BSTIM32);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_BSTIM32);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_BSTIM32);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 BSTIM32_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param BSTIMx BSTIMx
|
||||
* @param BSTIM32_InitStruct 指向一个 @ref FL_BSTIM32_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_BSTIM32_Init(BSTIM32_Type *BSTIM32x, FL_BSTIM32_InitTypeDef *init)
|
||||
{
|
||||
uint32_t i = 5;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_BSTIM32_INSTANCE(BSTIM32x));
|
||||
assert_param(IS_FL_BSTIM32_CLOCK_SRC(init->clockSource));
|
||||
assert_param(IS_FL_BSTIM32_AUTORELOAD_MODE(init->autoReloadState));
|
||||
/* 时钟使能 */
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_BSTIM32);
|
||||
/* 选择时钟源 */
|
||||
FL_CMU_SetBSTIM32ClockSource(init->clockSource);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_BSTIM32);
|
||||
/* 分频系数 */
|
||||
FL_BSTIM32_WritePrescaler(BSTIM32x, init->prescaler);
|
||||
/* 自动重装载值 */
|
||||
FL_BSTIM32_EnableUpdateEvent(BSTIM32x);
|
||||
FL_BSTIM32_WriteAutoReload(BSTIM32x, init->autoReload);
|
||||
if(init->autoReloadState == FL_ENABLE)
|
||||
{
|
||||
FL_BSTIM32_EnableARRPreload(BSTIM32x);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_BSTIM32_DisableARRPreload(BSTIM32x);
|
||||
}
|
||||
FL_BSTIM32_GenerateUpdateEvent(BSTIM32x);
|
||||
while((!FL_BSTIM32_IsActiveFlag_Update(BSTIM32x))&&i)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 BSTIM32_InitStruct 为默认配置
|
||||
* @param BSTIM32_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_BSTIM_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *init)
|
||||
{
|
||||
init->prescaler = 0;
|
||||
init->autoReload = 0xFFFFFFFF;
|
||||
init->autoReloadState = FL_ENABLE;
|
||||
init->clockSource = FL_CMU_BSTIM32_CLK_SOURCE_APBCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_BSTIM32_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
301
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_can.c
Normal file
301
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_can.c
Normal file
@ -0,0 +1,301 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_can.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of VAN fL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_CAN_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup CAN_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_SJW(__VALUE__) (((__VALUE__) == FL_CAN_SJW_1Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_SJW_2Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_SJW_3Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_SJW_4Tq))
|
||||
|
||||
|
||||
#define IS_CAN_TS1(__VALUE__) (((__VALUE__) == FL_CAN_TS1_1Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_2Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_3Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_4Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_5Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_6Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_7Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_8Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_9Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_10Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_11Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_12Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_13Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_14Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_15Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS1_16Tq))
|
||||
|
||||
|
||||
|
||||
#define IS_CAN_TS2(__VALUE__) (((__VALUE__) == FL_CAN_TS2_1Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_2Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_3Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_4Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_5Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_6Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_7Tq) \
|
||||
|| ((__VALUE__) == FL_CAN_TS2_8Tq))
|
||||
|
||||
|
||||
#define IS_CAN_FILTER_EN(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
|
||||
#define IS_CAN_AFx(__VALUE__) (((__VALUE__) == FL_CAN_FILTER1) \
|
||||
|| ((__VALUE__) == FL_CAN_FILTER2) \
|
||||
|| ((__VALUE__) == FL_CAN_FILTER3) \
|
||||
|| ((__VALUE__) == FL_CAN_FILTER4))
|
||||
|
||||
|
||||
#define IS_CAN_MODE(__VALUE__) (((__VALUE__) == FL_CAN_MODE_NORMAL) \
|
||||
|| ((__VALUE__) == FL_CAN_MODE_LOOPBACK) \
|
||||
|| ((__VALUE__) == FL_CAN_MODE_CONFIG))
|
||||
|
||||
|
||||
#define IS_CAN_CLK(__VALUE__) (((__VALUE__) == FL_CMU_CAN_CLK_SOURCE_RCHF) \
|
||||
|| ((__VALUE__) == FL_CMU_CAN_CLK_SOURCE_XTHF) \
|
||||
|| ((__VALUE__) == FL_CMU_CAN_CLK_SOURCE_PLL) \
|
||||
|| ((__VALUE__) == FL_CMU_CAN_CLK_SOURCE_APBCLK))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define IS_CAN_SRR(__VALUE__) (((__VALUE__)==FL_CAN_SRR_BIT_LOW) ||((__VALUE__)==FL_CAN_SRR_BIT_HIGH))
|
||||
#define IS_CAN_IDE(__VALUE__) (((__VALUE__)==FL_CAN_IDE_BIT_LOW) ||((__VALUE__)==FL_CAN_IDE_BIT_HIGH))
|
||||
#define IS_CAN_RTR(__VALUE__) (((__VALUE__)==FL_CAN_RTR_BIT_LOW) ||((__VALUE__)==FL_CAN_RTR_BIT_HIGH))
|
||||
|
||||
#define IS_CAN_ID18_MASK(__VALUE__) (__VALUE__<=262143U)
|
||||
#define IS_CAN_ID11_MASK(__VALUE__) (__VALUE__<=2047U)
|
||||
|
||||
#define IS_CAN_SRR_MASK(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_CAN_IDE_MASK(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_CAN_RTR_MASK(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CAN初始化
|
||||
* @param CANx外设入口地址
|
||||
* @param CAN_InitStruct 指向一个@ref FL_CAN_InitTypeDef 结构体的指针
|
||||
* @retval 错误状态可能值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_CAN_Init(CAN_Type *CANx, FL_CAN_InitTypeDef *CAN_InitStruct)
|
||||
{
|
||||
/*参数检查*/
|
||||
assert_param(IS_CAN_SJW(CAN_InitStruct->SJW));
|
||||
assert_param(IS_CAN_TS1(CAN_InitStruct->TS1));
|
||||
assert_param(IS_CAN_TS2(CAN_InitStruct->TS2));
|
||||
assert_param(IS_CAN_CLK(CAN_InitStruct->clockSource));
|
||||
/*时钟总线配置*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_CAN);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_CAN);
|
||||
/*CAN时钟源选择*/
|
||||
FL_CMU_SetCANClockSource(CAN_InitStruct->clockSource);
|
||||
/*复位CAN模块*/
|
||||
FL_CAN_SetSoftwareReset(CANx, FL_CAN_SOFTWARE_RESET);
|
||||
/*设置同步段*/
|
||||
FL_CAN_WriteSyncJumpWidth(CANx, CAN_InitStruct->SJW);
|
||||
/*设置时间段1*/
|
||||
FL_CAN_WriteTimeSegment1Length(CANx, CAN_InitStruct->TS1);
|
||||
/*设置时间段2*/
|
||||
FL_CAN_WriteTimeSegment2Length(CANx, CAN_InitStruct->TS2);
|
||||
/*设置波特率*/
|
||||
FL_CAN_WriteBaudRatePrescaler(CANx, CAN_InitStruct->BRP);
|
||||
if(CAN_InitStruct->mode == FL_CAN_MODE_NORMAL)
|
||||
{
|
||||
FL_CAN_DisableLoopBackMode(CANx); /* Normal模式 */
|
||||
FL_CAN_Enable(CANx);
|
||||
}
|
||||
else
|
||||
if(CAN_InitStruct->mode == FL_CAN_MODE_LOOPBACK)
|
||||
{
|
||||
FL_CAN_EnableLoopBackMode(CANx); /* Loop Back模式 */
|
||||
FL_CAN_Enable(CANx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Disable(CANx); /* Configuration模式 */
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 CAN_InitStruct 为默认配置
|
||||
* @param CAN_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_CAN_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_CAN_StructInit(FL_CAN_InitTypeDef *CAN_InitStruct)
|
||||
{
|
||||
CAN_InitStruct->mode = FL_CAN_MODE_NORMAL;
|
||||
CAN_InitStruct->BRP = 0;
|
||||
CAN_InitStruct->clockSource = FL_CMU_CAN_CLK_SOURCE_RCHF;
|
||||
CAN_InitStruct->SJW = FL_CAN_SJW_1Tq;
|
||||
CAN_InitStruct->TS1 = FL_CAN_TS1_5Tq;
|
||||
CAN_InitStruct->TS2 = FL_CAN_TS2_4Tq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CAN滤波器初始化
|
||||
* @param CANx外设入口地址
|
||||
* @param filterX This parameter can be one of the following values:
|
||||
* @arg @ref FL_CAN_FILTER1
|
||||
* @arg @ref FL_CAN_FILTER2
|
||||
* @arg @ref FL_CAN_FILTER3
|
||||
* @arg @ref FL_CAN_FILTER4
|
||||
* @param CAN_InitFilterStruct 指向一个@ref FL_CAN_FilterInitTypeDef 结构体的指针
|
||||
* @retval 错误状态可能值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_CAN_FilterInit(CAN_Type *CANx, FL_CAN_FilterInitTypeDef *CAN_FilterInitStruct, uint32_t filterX)
|
||||
{
|
||||
uint32_t counter =0;
|
||||
uint32_t filterstatus;
|
||||
assert_param(IS_CAN_SRR(CAN_FilterInitStruct->filterIdSRR));
|
||||
assert_param(IS_CAN_IDE(CAN_FilterInitStruct->filterIdIDE));
|
||||
assert_param(IS_CAN_RTR(CAN_FilterInitStruct->filterIdRTR));
|
||||
assert_param(IS_CAN_FILTER_EN(CAN_FilterInitStruct->filterEn));
|
||||
assert_param(IS_CAN_ID18_MASK(CAN_FilterInitStruct->filterMaskIdLow));
|
||||
assert_param(IS_CAN_ID11_MASK(CAN_FilterInitStruct->filterMaskIdHigh));
|
||||
assert_param(IS_CAN_SRR_MASK(CAN_FilterInitStruct->filterMaskIdSRR));
|
||||
assert_param(IS_CAN_IDE_MASK(CAN_FilterInitStruct->filterMaskIdIDE));
|
||||
assert_param(IS_CAN_RTR_MASK(CAN_FilterInitStruct->filterMaskIdRTR));
|
||||
assert_param(IS_CAN_AFx(filterX));
|
||||
do
|
||||
{
|
||||
filterstatus = FL_CAN_IsActiveFlag_FilterBusy(CANx);
|
||||
counter++;
|
||||
}while((filterstatus != 0U) && (counter != CAN_TIMEOUT));
|
||||
if(CAN_FilterInitStruct->filterIdIDE == FL_CAN_IDE_BIT_HIGH)
|
||||
{
|
||||
FL_CAN_Filter_WriteIDCompare(CANx, filterX, ((CAN_FilterInitStruct->filterIdExtend) >> 18) & 0X7FF);
|
||||
FL_CAN_Filter_WriteEXTIDCompare(CANx, filterX, (CAN_FilterInitStruct->filterIdExtend) & 0X3FFFF);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Filter_WriteIDCompare(CANx, filterX, (CAN_FilterInitStruct->filterIdStandard) & 0X7FF);
|
||||
}
|
||||
if((CAN_FilterInitStruct->filterMaskIdSRR) == FL_ENABLE) /* SRR参与滤波器比较 */
|
||||
{
|
||||
FL_CAN_Filter_EnableSRRCompare(CANx, filterX);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Filter_DisableSRRCompare(CANx, filterX);
|
||||
}
|
||||
if((CAN_FilterInitStruct->filterMaskIdIDE) == FL_ENABLE) /* IDE位参与滤波器比较 */
|
||||
{
|
||||
FL_CAN_Filter_EnableIDECompare(CANx, filterX);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Filter_DisableIDECompare(CANx, filterX);
|
||||
}
|
||||
if((CAN_FilterInitStruct->filterMaskIdRTR) == FL_ENABLE) /* RTR位参与滤波器比较 */
|
||||
{
|
||||
FL_CAN_Filter_EnableRTRCompare(CANx, filterX);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Filter_DisableRTRCompare(CANx, filterX);
|
||||
}
|
||||
FL_CAN_Filter_WriteIDCompareMask(CANx, filterX, CAN_FilterInitStruct->filterMaskIdHigh); /* 滤波器掩码配置 */
|
||||
FL_CAN_Filter_WriteEXTIDCompareMask(CANx, filterX, CAN_FilterInitStruct->filterMaskIdLow);
|
||||
FL_CAN_Filter_SetSRRCompare(CANx, filterX, CAN_FilterInitStruct->filterIdSRR);
|
||||
FL_CAN_Filter_SetIDECompare(CANx, filterX, CAN_FilterInitStruct->filterIdIDE); /* 滤波器ID配置 */
|
||||
FL_CAN_Filter_SetRTRCompare(CANx, filterX, CAN_FilterInitStruct->filterIdRTR);
|
||||
if((CAN_FilterInitStruct->filterEn) == FL_ENABLE) /* 滤波器使能 */
|
||||
{
|
||||
FL_CAN_Filter_Enable(CANx, filterX);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CAN_Filter_Disable(CANx, filterX);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 CAN_FilterInitStruct 为默认配置
|
||||
* @param CAN_FilterInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_CAN_FilterInitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_CAN_StructFilterInit(FL_CAN_FilterInitTypeDef *CAN_FilterInitStruct)
|
||||
{
|
||||
CAN_FilterInitStruct->filterEn = FL_DISABLE;
|
||||
CAN_FilterInitStruct->filterIdExtend = 0;
|
||||
CAN_FilterInitStruct->filterMaskIdHigh = 0x7FF;
|
||||
CAN_FilterInitStruct->filterIdIDE = FL_CAN_IDE_BIT_LOW;
|
||||
CAN_FilterInitStruct->filterMaskIdIDE = FL_DISABLE;
|
||||
CAN_FilterInitStruct->filterMaskIdLow = 0X3FFFF;
|
||||
CAN_FilterInitStruct->filterIdRTR = FL_CAN_RTR_BIT_LOW;
|
||||
CAN_FilterInitStruct->filterMaskIdRTR = FL_DISABLE;
|
||||
CAN_FilterInitStruct->filterIdSRR = FL_CAN_SRR_BIT_LOW;
|
||||
CAN_FilterInitStruct->filterMaskIdSRR = FL_DISABLE;
|
||||
CAN_FilterInitStruct->filterIdStandard = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_CAN_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
289
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_cmu.c
Normal file
289
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_cmu.c
Normal file
@ -0,0 +1,289 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_cmu.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of CMU FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CMU
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_CMU_DRIVER_ENABLED
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CMU_FL_EF_QUERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 获取系统当前工作时钟SYSCLK。
|
||||
* @param None
|
||||
* @note 函数中用到了XTHF_VALUE 宏，这个宏应该被定义为外部晶振的输入频率值。
|
||||
*
|
||||
* @retval 系统时钟频率 (Hz)。
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetSystemClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
/* 获取系统时钟源 */
|
||||
switch(FL_CMU_GetSystemClockSource())
|
||||
{
|
||||
/* 系统时钟源为内部RCHF */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_RCHF:
|
||||
/* 内部RCHF默认为8MHz ,可以配置为16或24M */
|
||||
frequency = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
/* 系统时钟源为XTHF */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_XTHF:
|
||||
frequency = XTHFClock;
|
||||
break;
|
||||
/* 系统时钟源为PLL */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_PLL:
|
||||
frequency = FL_CMU_GetPLLClockFreq();
|
||||
break;
|
||||
/* 系统时钟源为内部RCLF */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_RCLF:
|
||||
/* 根据RC4M的分频配置得出系统时钟 */
|
||||
frequency = FL_CMU_GetRCLFClockFreq();
|
||||
break;
|
||||
/* 系统时钟源为XTLF */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_XTLF:
|
||||
/* 根据外部晶振的频率得出系统时钟 */
|
||||
frequency = XTLFClock;
|
||||
break;
|
||||
/* 系统时钟源为RCLP */
|
||||
case FL_CMU_SYSTEM_CLK_SOURCE_RCLP:
|
||||
frequency = 32768;
|
||||
break;
|
||||
default:
|
||||
frequency = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
}
|
||||
return frequency;
|
||||
}
|
||||
/**
|
||||
* @brief 获取 AHB 总线时钟频率。
|
||||
*
|
||||
* @param SYSCLK_Frequency 系统主时钟频率SYSCLK
|
||||
*
|
||||
* @retval AHB 总线时钟频率(Hz)
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetAHBClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
/* 获取AHB分频系数，AHB源自系统主时钟 */
|
||||
switch(FL_CMU_GetAHBPrescaler())
|
||||
{
|
||||
case FL_CMU_AHBCLK_PSC_DIV1:
|
||||
frequency = FL_CMU_GetSystemClockFreq();
|
||||
break;
|
||||
case FL_CMU_AHBCLK_PSC_DIV2:
|
||||
frequency = FL_CMU_GetSystemClockFreq() / 2;
|
||||
break;
|
||||
case FL_CMU_AHBCLK_PSC_DIV4:
|
||||
frequency = FL_CMU_GetSystemClockFreq() / 4;
|
||||
break;
|
||||
case FL_CMU_AHBCLK_PSC_DIV8:
|
||||
frequency = FL_CMU_GetSystemClockFreq() / 8;
|
||||
break;
|
||||
case FL_CMU_AHBCLK_PSC_DIV16:
|
||||
frequency = FL_CMU_GetSystemClockFreq() / 16;
|
||||
break;
|
||||
default:
|
||||
frequency = FL_CMU_GetSystemClockFreq();
|
||||
break;
|
||||
}
|
||||
return frequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取当前系统的APB总线时钟
|
||||
* @param APB_Frequency APB总线的时钟频率
|
||||
*
|
||||
* @retval APB clock frequency (in Hz)
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetAPBClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
/* 获取APB1分频系数，APB源自AHB */
|
||||
switch(FL_CMU_GetAPBPrescaler())
|
||||
{
|
||||
case FL_CMU_APBCLK_PSC_DIV1:
|
||||
frequency = FL_CMU_GetAHBClockFreq();
|
||||
break;
|
||||
case FL_CMU_APBCLK_PSC_DIV2:
|
||||
frequency = FL_CMU_GetAHBClockFreq() / 2;
|
||||
break;
|
||||
case FL_CMU_APBCLK_PSC_DIV4:
|
||||
frequency = FL_CMU_GetAHBClockFreq() / 4;
|
||||
break;
|
||||
case FL_CMU_APBCLK_PSC_DIV8:
|
||||
frequency = FL_CMU_GetAHBClockFreq() / 8;
|
||||
break;
|
||||
case FL_CMU_APBCLK_PSC_DIV16:
|
||||
frequency = FL_CMU_GetAHBClockFreq() / 16;
|
||||
break;
|
||||
default:
|
||||
frequency = FL_CMU_GetAHBClockFreq();
|
||||
break;
|
||||
}
|
||||
return frequency;
|
||||
}
|
||||
/**
|
||||
* @brief 获取RCLF输出时钟频率
|
||||
* @param None
|
||||
*
|
||||
* @retval 返回RCLF输出时钟频率(Hz)
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetRCLFClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
switch(FL_CMU_RCLF_GetPrescaler())
|
||||
{
|
||||
case FL_CMU_RCLF_PSC_DIV1:
|
||||
frequency = 614400;
|
||||
break;
|
||||
case FL_CMU_RCLF_PSC_DIV4:
|
||||
frequency = 153600;
|
||||
break;
|
||||
case FL_CMU_RCLF_PSC_DIV8:
|
||||
frequency = 76800;
|
||||
break;
|
||||
case FL_CMU_RCLF_PSC_DIV16:
|
||||
frequency = 38400;
|
||||
break;
|
||||
default:
|
||||
frequency = 614400;
|
||||
break;
|
||||
}
|
||||
return frequency;
|
||||
}
|
||||
/**
|
||||
* @brief 获取RCHF输出时钟频率
|
||||
* @param None
|
||||
*
|
||||
* @retval 返回RCHF输出时钟频率(Hz)
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetRCHFClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
switch(FL_CMU_RCHF_GetFrequency())
|
||||
{
|
||||
case FL_CMU_RCHF_FREQUENCY_8MHZ:
|
||||
frequency = 8000000;
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_16MHZ:
|
||||
frequency = 16000000;
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_24MHZ:
|
||||
frequency = 24000000;
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_32MHZ:
|
||||
frequency = 32000000;
|
||||
break;
|
||||
default:
|
||||
frequency = 8000000;
|
||||
break;
|
||||
}
|
||||
return frequency;
|
||||
}
|
||||
/**
|
||||
* @brief 获取PLL输出时钟频率
|
||||
* @param None
|
||||
*
|
||||
* @retval 返回PLL输出时钟频率(Hz)
|
||||
*
|
||||
*/
|
||||
uint32_t FL_CMU_GetPLLClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
uint32_t multiplier = 0;
|
||||
/* 获取PLL时钟源 */
|
||||
switch(FL_CMU_PLL_GetClockSource())
|
||||
{
|
||||
case FL_CMU_PLL_CLK_SOURCE_RCHF:
|
||||
/* 获取RCHF配置主频 */
|
||||
frequency = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
case FL_CMU_PLL_CLK_SOURCE_XTHF:
|
||||
frequency = XTHFClock;
|
||||
break;
|
||||
default:
|
||||
frequency = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
}
|
||||
/* 获取PLL时钟分频系数 */
|
||||
switch(FL_CMU_PLL_GetPrescaler())
|
||||
{
|
||||
case FL_CMU_PLL_PSC_DIV1:
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV2:
|
||||
frequency /= 2;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV4:
|
||||
frequency /= 4;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV8:
|
||||
frequency /= 8;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV12:
|
||||
frequency /= 12;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV16:
|
||||
frequency /= 16;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV24:
|
||||
frequency /= 24;
|
||||
break;
|
||||
case FL_CMU_PLL_PSC_DIV32:
|
||||
frequency /= 32;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
multiplier = FL_CMU_PLL_ReadMultiplier() + 1;
|
||||
frequency *= multiplier;
|
||||
return frequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_CMU_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
219
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_comp.c
Normal file
219
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_comp.c
Normal file
@ -0,0 +1,219 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_comp.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of COMP FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_COMP_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup COMP_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_ALL_INSTANCE(INTENCE) (((INTENCE) == COMP1)||\
|
||||
((INTENCE) == COMP2)||\
|
||||
((INTENCE) == COMP3))
|
||||
|
||||
#define IS_FL_COMP_POSITIVEINPUT(__VALUE__) (((__VALUE__) == FL_COMP_INP_SOURCE_INP1)||\
|
||||
((__VALUE__) == FL_COMP_INP_SOURCE_INP2)||\
|
||||
((__VALUE__) == FL_COMP_INP_SOURCE_AVREF)||\
|
||||
((__VALUE__) == FL_COMP_INP_SOURCE_ULPBG_REF)||\
|
||||
((__VALUE__) == FL_COMP_INP_SOURCE_VDD15)||\
|
||||
((__VALUE__) == FL_COMP_INP_SOURCE_VREFP))
|
||||
|
||||
#define IS_FL_COMP_NEGATIVEINPUT(__VALUE__) (((__VALUE__) == FL_COMP_INN_SOURCE_INN1)||\
|
||||
((__VALUE__) == FL_COMP_INN_SOURCE_INN2)||\
|
||||
((__VALUE__) == FL_COMP_INN_SOURCE_VREF)||\
|
||||
((__VALUE__) == FL_COMP_INN_SOURCE_VREF_DIV_2)||\
|
||||
((__VALUE__) == FL_COMP_INN_SOURCE_VREFP)||\
|
||||
((__VALUE__) == FL_COMP_INN_SOURCE_DAC))
|
||||
|
||||
#define IS_FL_COMP_POLARITY(__VALUE__) (((__VALUE__) == FL_COMP_OUTPUT_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_COMP_EDGE(__VALUE__) (((__VALUE__) == FL_COMP_INTERRUPT_EDGE_BOTH)||\
|
||||
((__VALUE__) == FL_COMP_INTERRUPT_EDGE_RISING )||\
|
||||
((__VALUE__) == FL_COMP_INTERRUPT_EDGE_FALLING))
|
||||
|
||||
#define IS_FL_COMP_DIGITAL_FILTER(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_COMP_DIGITAL_FILTER_LEN(__VALUE__) (((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_3APBCLK)||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_4APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_5APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_6APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_7APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_8APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_9APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_10APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_11APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_12APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_13APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_14APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_15APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_16APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_17APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_18APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_19APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_20APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_21APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_22APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_23APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_24APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_25APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_26APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_27APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_28APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_29APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_30APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_31APBCLK )||\
|
||||
((__VALUE__) == FL_COMP_OUTPUT_FILTER_WINDOW_32APBCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应COMP控制寄存器.
|
||||
* @param COMPx COMP Port
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_COMP_DeInit(COMP_Type *COMPx)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(COMPx));
|
||||
/* 恢复寄存器值为默认值 */
|
||||
COMPx->CR = 0x00000000U;
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 COMP_InitStruct的配置信息初始化对应外设.
|
||||
* @param COMPx COMP Port
|
||||
* @param initStruct 指向一个 @ref FL_COMP_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @param Serial 比较器序号可取值：
|
||||
* 1 配置比较器1
|
||||
* 2 配置比较器2
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS COMP配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_COMP_Init(COMP_Type *COMPx, FL_COMP_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(COMPx));
|
||||
assert_param(IS_FL_COMP_EDGE(initStruct->edge));
|
||||
assert_param(IS_FL_COMP_POLARITY(initStruct->polarity));
|
||||
assert_param(IS_FL_COMP_POSITIVEINPUT(initStruct->positiveInput));
|
||||
assert_param(IS_FL_COMP_NEGATIVEINPUT(initStruct->negativeInput));
|
||||
assert_param(IS_FL_COMP_DIGITAL_FILTER(initStruct->digitalFilter));
|
||||
assert_param(IS_FL_COMP_DIGITAL_FILTER_LEN(initStruct->digitalFilterLen));
|
||||
/* 使能时钟总线 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_COMP);
|
||||
/* 比较器输出极性选择 */
|
||||
FL_COMP_SetOutputPolarity(COMPx, initStruct->polarity);
|
||||
/* 比较器正向输入选择 */
|
||||
FL_COMP_SetINPSource(COMPx, initStruct->positiveInput);
|
||||
/* 比较器反向输入选择 */
|
||||
FL_COMP_SetINNSource(COMPx, initStruct->negativeInput);
|
||||
/* 比较器使用1/2(internal reference) 打开buffer */
|
||||
if(initStruct->negativeInput == FL_COMP_INN_SOURCE_VREF_DIV_2)
|
||||
{
|
||||
FL_COMP_EnableBuffer(COMP); /* buffer使能 */
|
||||
FL_COMP_DisableBufferBypass(COMP); /* 不bypass buffer */
|
||||
}
|
||||
/* 比较器数字滤波 */
|
||||
if(COMPx == COMP1)
|
||||
{
|
||||
/* 比较器中断边沿选择 */
|
||||
FL_COMP_SetComparator1InterruptEdge(COMP, ((initStruct->edge)<<COMP_ICR_CMP1SEL_Pos));
|
||||
}
|
||||
else
|
||||
if(COMPx == COMP2)
|
||||
{
|
||||
/* 比较器中断边沿选择 */
|
||||
FL_COMP_SetComparator2InterruptEdge(COMP, ((initStruct->edge)<<COMP_ICR_CMP2SEL_Pos));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 比较器中断边沿选择 */
|
||||
FL_COMP_SetComparator3InterruptEdge(COMP, ((initStruct->edge)<<COMP_ICR_CMP3SEL_Pos));
|
||||
}
|
||||
/* 滤波 */
|
||||
if(initStruct->digitalFilter)
|
||||
{
|
||||
FL_COMP_EnableOutputFilter(COMPx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_COMP_DisableOutputFilter(COMPx);
|
||||
}
|
||||
/* 滤波长度 */
|
||||
FL_COMP_SetOutputFilterWindow(COMPx, initStruct->digitalFilterLen);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 initStruct 为默认配置
|
||||
* @param initStruct 指向需要将值设置为默认配置的结构体 @ref FL_COMP_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_COMP_StructInit(FL_COMP_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 复位配置信息 */
|
||||
initStruct->edge = FL_COMP_INTERRUPT_EDGE_BOTH;
|
||||
initStruct->polarity = FL_COMP_OUTPUT_POLARITY_NORMAL;
|
||||
initStruct->negativeInput = FL_COMP_INN_SOURCE_INN1;
|
||||
initStruct->positiveInput = FL_COMP_INP_SOURCE_INP1;
|
||||
initStruct->digitalFilter = FL_ENABLE;
|
||||
initStruct->digitalFilterLen = FL_COMP_OUTPUT_FILTER_WINDOW_3APBCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_COMP_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_crc.c
Normal file
167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_crc.c
Normal file
@ -0,0 +1,167 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_crc.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of CRC FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_CRC_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup CRC_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_CRC_INSTANCE(INTANCE) ((INTANCE) == CRC)
|
||||
|
||||
#define IS_FL_CRC_POLYNOMIAL_WIDTH(__VALUE__) (((__VALUE__) == FL_CRC_POLYNOMIAL_16B)||\
|
||||
((__VALUE__) == FL_CRC_POLYNOMIAL_32B)||\
|
||||
((__VALUE__) == FL_CRC_POLYNOMIAL_8B)||\
|
||||
((__VALUE__) == FL_CRC_POLYNOMIAL_7B))
|
||||
|
||||
#define IS_FL_CRC_DR_WIDTH(__VALUE__) (((__VALUE__) == FL_CRC_DATA_WIDTH_8B)||\
|
||||
((__VALUE__) == FL_CRC_DATA_WIDTH_32B))
|
||||
|
||||
|
||||
#define IS_FL_CRC_OUPUT_REFLECTE_MODE(__VALUE__) (((__VALUE__) == FL_CRC_OUPUT_INVERT_NONE)||\
|
||||
((__VALUE__) == FL_CRC_OUPUT_INVERT_BYTE))
|
||||
|
||||
#define IS_FL_CRC_INPUT_REFLECTE_MODE(__VALUE__) (((__VALUE__) == FL_CRC_INPUT_INVERT_NONE)||\
|
||||
((__VALUE__) == FL_CRC_INPUT_INVERT_BYTE)||\
|
||||
((__VALUE__) == FL_CRC_INPUT_INVERT_HALF_WORD)||\
|
||||
((__VALUE__) == FL_CRC_INPUT_INVERT_WORD))
|
||||
|
||||
#define IS_FL_CRC_CALCULA_MODE(__VALUE__) (((__VALUE__) == FL_CRC_CALCULATE_SERIAL)||\
|
||||
((__VALUE__) == FL_CRC_CALCULATE_PARALLEL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CRC_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应CRC寄存器.
|
||||
*
|
||||
* @param CRCx 外设入口地址
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_CRC_DeInit(CRC_Type *CRCx)
|
||||
{
|
||||
assert_param(IS_FL_CRC_INSTANCE(CRCx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_CRC);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_CRC);
|
||||
/* 关闭总线时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_CRC);
|
||||
/* 锁定外设复位功能 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 CRC_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
*
|
||||
* @param CRCx 外设入口地址
|
||||
* @param CRC_InitStruct 指向一个 @ref FL_CRC_InitTypeDef 结构体其中包含了外设的相关配置信息.
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_CRC_INSTANCE(CRCx));
|
||||
assert_param(IS_FL_CRC_DR_WIDTH(CRC_InitStruct->dataWidth));
|
||||
assert_param(IS_FL_CRC_CALCULA_MODE(CRC_InitStruct->calculatMode));
|
||||
assert_param(IS_FL_CRC_POLYNOMIAL_WIDTH(CRC_InitStruct->polynomialWidth));
|
||||
assert_param(IS_FL_CRC_INPUT_REFLECTE_MODE(CRC_InitStruct->reflectIn));
|
||||
assert_param(IS_FL_CRC_OUPUT_REFLECTE_MODE(CRC_InitStruct->reflectOut));
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_CRC);
|
||||
FL_CRC_SetCalculateMode(CRCx, CRC_InitStruct->calculatMode);
|
||||
FL_CRC_SetInputInvertMode(CRCx, CRC_InitStruct->reflectIn);
|
||||
FL_CRC_SetOutputInvertMode(CRCx, CRC_InitStruct->reflectOut);
|
||||
FL_CRC_SetPolynomialWidth(CRCx, CRC_InitStruct->polynomialWidth);
|
||||
FL_CRC_WriteXORValue(CRCx, CRC_InitStruct->xorReg);
|
||||
FL_CRC_WritePolynominalParam(CRCx, CRC_InitStruct->polynomial);
|
||||
FL_CRC_WriteInitialValue(CRCx, CRC_InitStruct->initVal);
|
||||
FL_CRC_SetDataWidth(CRCx, CRC_InitStruct->dataWidth);
|
||||
if(CRC_InitStruct->xorRegState == FL_ENABLE)
|
||||
{
|
||||
FL_CRC_EnableOutputXOR(CRCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CRC_DisableOutputXOR(CRCx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief 设置 CRC_InitStruct 为默认配置
|
||||
*
|
||||
* @param CRC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_CRC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_CRC_StructInit(FL_CRC_InitTypeDef *CRC_InitStruct)
|
||||
{
|
||||
CRC_InitStruct->polynomial = 0x00000000;
|
||||
CRC_InitStruct->polynomialWidth = FL_CRC_POLYNOMIAL_16B;
|
||||
CRC_InitStruct->dataWidth = FL_CRC_DATA_WIDTH_8B;
|
||||
CRC_InitStruct->calculatMode = FL_CRC_CALCULATE_SERIAL;
|
||||
CRC_InitStruct->reflectIn = FL_CRC_INPUT_INVERT_NONE;
|
||||
CRC_InitStruct->reflectOut = FL_CRC_OUPUT_INVERT_NONE;
|
||||
CRC_InitStruct->xorReg = 0x00000000;
|
||||
CRC_InitStruct->xorRegState = FL_DISABLE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_CRC_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
199
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_dac.c
Normal file
199
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_dac.c
Normal file
@ -0,0 +1,199 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_dac.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of DAC FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_DAC_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup DAC_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FL_DAC_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
|
||||
|
||||
#define IS_FL_DAC_TRIGGERMODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_DAC_TRIGGE_SOURCE(__VALUE__) (((__VALUE__) == FL_DAC_TRGI_SOFTWARE)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_ATIM)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_GPTIM1)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_GPTIM2)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_BSTIM16)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_LPTIM16)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_EXTI0)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_EXTI4)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_EXTI8)||\
|
||||
((__VALUE__) == FL_DAC_TRGI_EXTI12))
|
||||
|
||||
#define IS_FL_DAC_SAMPLEHOLDMODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_DAC_HOLD_TIME(__VALUE__) (((__VALUE__) <= 0XFFFF))
|
||||
|
||||
#define IS_FL_DAC_SAMPLE_TIME(__VALUE__) (((__VALUE__) <= 0XFF))
|
||||
|
||||
#define IS_FL_DAC_BUFFERMODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_DAC_SWITCHMODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_DAC_DMAMODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CRC_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 恢复对应的DAC入口地址寄存器为默认值
|
||||
*
|
||||
* @param DACx 外设入口地址
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS DAC配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_DAC_DeInit(DAC_Type *DACx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口合法性检查 */
|
||||
assert_param(IS_FL_DAC_INSTANCE(DACx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DAC);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DAC);
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 初始化DACx指定的入口地址的外设寄存器
|
||||
* @param DACx 外设入口地址
|
||||
* @param DAC_InitStruct 向一FL_DAC_InitTypeDef结构体，它包含指定DAC外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS DAC配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_DAC_Init(DAC_Type *DACx, FL_DAC_InitTypeDef *DAC_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口合法性检查 */
|
||||
assert_param(IS_FL_DAC_INSTANCE(DACx));
|
||||
assert_param(IS_FL_DAC_TRIGGERMODE(DAC_InitStruct->triggerMode));
|
||||
assert_param(IS_FL_DAC_TRIGGE_SOURCE(DAC_InitStruct->triggerSource));
|
||||
assert_param(IS_FL_DAC_SAMPLEHOLDMODE(DAC_InitStruct->sampleHoldMode));
|
||||
assert_param(IS_FL_DAC_HOLD_TIME(DAC_InitStruct->holdTime));
|
||||
assert_param(IS_FL_DAC_SAMPLE_TIME(DAC_InitStruct->sampleTime));
|
||||
assert_param(IS_FL_DAC_BUFFERMODE(DAC_InitStruct->bufferMode));
|
||||
assert_param(IS_FL_DAC_SWITCHMODE(DAC_InitStruct->switchMode));
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DAC);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DAC);
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_DAC);
|
||||
FL_DAC_Disable(DACx);
|
||||
if(FL_DAC_IsEnabled(DACx) == 0U)
|
||||
{
|
||||
/* 采样保持使能配置 */
|
||||
if(DAC_InitStruct->sampleHoldMode)
|
||||
{
|
||||
FL_DAC_WriteSamplingTime(DACx, DAC_InitStruct->sampleTime);
|
||||
FL_DAC_WriteHoldingTime(DACx, DAC_InitStruct->holdTime);
|
||||
FL_DAC_EnableSampleHoldMode(DACx);
|
||||
}
|
||||
else
|
||||
{ FL_DAC_DisableSampleHoldMode(DACx); }
|
||||
/* 触发模式使能配置 */
|
||||
if(DAC_InitStruct->triggerMode)
|
||||
{
|
||||
FL_DAC_SetTriggerSource(DACx, DAC_InitStruct->triggerSource);
|
||||
FL_DAC_EnableTriggerMode(DACx);
|
||||
}
|
||||
else
|
||||
{ FL_DAC_DisableTriggerMode(DACx); }
|
||||
/* buffer使能配置 */
|
||||
if(DAC_InitStruct->bufferMode)
|
||||
{ FL_DAC_EnableOutputBuffer(DACx); }
|
||||
else
|
||||
{ FL_DAC_DisableOutputBuffer(DACx); }
|
||||
/* SWITCH使能配置 */
|
||||
if(DAC_InitStruct->switchMode)
|
||||
{ FL_DAC_EnableFeedbackSwitch(DACx); }
|
||||
else
|
||||
{ FL_DAC_DisableFeedbackSwitch(DACx); }
|
||||
}
|
||||
else
|
||||
{
|
||||
status = FL_FAIL;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief 设置 DAC_InitStruct 为默认配置
|
||||
* @param DAC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_DAC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_DAC_StructInit(FL_DAC_InitTypeDef *DAC_InitStruct)
|
||||
{
|
||||
DAC_InitStruct->bufferMode = FL_ENABLE;
|
||||
DAC_InitStruct->switchMode = FL_ENABLE;
|
||||
DAC_InitStruct->triggerMode = FL_DISABLE;
|
||||
DAC_InitStruct->triggerSource = FL_DAC_TRGI_SOFTWARE;
|
||||
DAC_InitStruct->sampleHoldMode = FL_DISABLE;
|
||||
DAC_InitStruct->sampleTime = 0xFF;
|
||||
DAC_InitStruct->holdTime = 0X0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_DAC_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
|
||||
|
||||
182
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_divas.c
Normal file
182
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_divas.c
Normal file
@ -0,0 +1,182 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_divas.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of DIVAS FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DIVAS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_DIVAS_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup DIVAS_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DIVAS_ALL_INSTANCE(INTENCE) ((INTENCE) == DIVAS)
|
||||
|
||||
#define IS_FL_DIVAS_DIVISOR(__VALUE__) (((__VALUE__) != 0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DIVAS_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应HDIV控制寄存器.
|
||||
*
|
||||
* @param DIVASx 外设入口地址
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_DIVAS_DeInit(DIVAS_Type *DIVASx)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_DIVAS_ALL_INSTANCE(DIVASx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 恢复寄存器值为默认值 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DIVAS);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_DIVAS);
|
||||
/* 关闭总线时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_DIVAS);
|
||||
/* 锁定外设复位功能 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 初始化对应外设DIVAS.
|
||||
*
|
||||
* @param DIVASx 外设入口地址
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_DIVAS_Init(DIVAS_Type *DIVASx)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_DIVAS_ALL_INSTANCE(DIVASx));
|
||||
/* 使能时钟总线 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_DIVAS);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 硬件除法器计算函数
|
||||
*
|
||||
* @param DIVASx 外设入口地址
|
||||
* @param DivisorEnd 32位有符号被除数
|
||||
* @param Divisor 16位有符号除数，注意不能为0
|
||||
* @param Quotient 指向 @ref int32_t 指针 保存商的地址
|
||||
* @param Residue 指向 @ref int16_t 指针 保存余数的地址
|
||||
*
|
||||
* @retval 计算正确性与否
|
||||
* -0 计算结果正确
|
||||
* -非0 计算过程发生错误
|
||||
*/
|
||||
uint32_t FL_DIVAS_Hdiv_Calculation(DIVAS_Type *DIVASx, int32_t DivisorEnd, int16_t Divisor, int32_t *Quotient, int16_t *Residue)
|
||||
{
|
||||
uint32_t TimeOut ;
|
||||
FL_DIVAS_SetMode(DIVASx, FL_DIVAS_MODE_DIV);
|
||||
FL_DIVAS_WriteOperand(DIVASx, (uint32_t)DivisorEnd);
|
||||
FL_DIVAS_WriteDivisor(DIVASx, (uint32_t)Divisor);
|
||||
if(FL_DIVAS_IsActiveFlag_DividedZero(DIVASx))
|
||||
{
|
||||
/*除数为0 */
|
||||
*Quotient = 0;
|
||||
*Residue = 0;
|
||||
return 1;
|
||||
}
|
||||
TimeOut = FL_DIVAS_SR_BUSY_TIMEOUT;
|
||||
while(FL_DIVAS_IsActiveFlag_Busy(DIVASx))
|
||||
{
|
||||
TimeOut--;
|
||||
if(TimeOut == 0)
|
||||
{
|
||||
/* 计算超时*/
|
||||
*Quotient = 0;
|
||||
*Residue = 0;
|
||||
return 3;
|
||||
}
|
||||
}
|
||||
*Quotient = FL_DIVAS_ReadQuotient(DIVASx);
|
||||
*Residue = FL_DIVAS_ReadResidue(DIVASx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 硬件开方计算函数
|
||||
*
|
||||
* @param DIVASx 外设入口地址
|
||||
* @param Root 32bit被开方数
|
||||
* @param Result 指向 @ref int16_t 指针 保存结果开方根
|
||||
*
|
||||
* @retval 计算正确性与否
|
||||
* -0 计算结果正确
|
||||
* -非0 计算过程发生错误
|
||||
*/
|
||||
uint32_t FL_DIVAS_Root_Calculation(DIVAS_Type *DIVASx, uint32_t Root, uint16_t *Result)
|
||||
{
|
||||
uint32_t TimeOut ;
|
||||
FL_DIVAS_SetMode(DIVASx, FL_DIVAS_MODE_ROOT);
|
||||
FL_DIVAS_WriteOperand(DIVASx, Root);
|
||||
TimeOut = FL_DIVAS_SR_BUSY_TIMEOUT;
|
||||
while(FL_DIVAS_IsActiveFlag_Busy(DIVASx))
|
||||
{
|
||||
TimeOut --;
|
||||
if(TimeOut == 0)
|
||||
{
|
||||
/* 计算超时*/
|
||||
*Result = 0;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
*Result = FL_DIVAS_ReadRoot(DIVASx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_DIVAS_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
|
||||
229
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_dma.c
Normal file
229
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_dma.c
Normal file
@ -0,0 +1,229 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_dma.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of DMA FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_DMA_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup DMA_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_DMA_INSTANCE(INTANCE) ((INTANCE) == DMA)
|
||||
|
||||
#define IS_FL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == FL_DMA_PRIORITY_LOW)||\
|
||||
((__VALUE__) == FL_DMA_PRIORITY_MEDIUM)||\
|
||||
((__VALUE__) == FL_DMA_PRIORITY_HIGH)||\
|
||||
((__VALUE__) == FL_DMA_PRIORITY_VERYHIGH))
|
||||
|
||||
#define IS_FL_DMA_CIRC_MODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
|
||||
#define IS_FL_DMA_DIRECION(__VALUE__) (((__VALUE__) == FL_DMA_DIR_PERIPHERAL_TO_RAM)||\
|
||||
((__VALUE__) == FL_DMA_DIR_RAM_TO_PERIPHERAL)||\
|
||||
((__VALUE__) == FL_DMA_DIR_FLASH_TO_RAM)||\
|
||||
((__VALUE__) == FL_DMA_DIR_RAM_TO_FLASH))
|
||||
|
||||
|
||||
#define IS_FL_DMA_DATA_SIZE(__VALUE__) (((__VALUE__) == FL_DMA_BANDWIDTH_8B)||\
|
||||
((__VALUE__) == FL_DMA_BANDWIDTH_16B)||\
|
||||
((__VALUE__) == FL_DMA_BANDWIDTH_32B))
|
||||
|
||||
#define IS_FL_DMA_INCMODE(__VALUE__) (((__VALUE__) == FL_DMA_MEMORY_INC_MODE_INCREASE)||\
|
||||
((__VALUE__) == FL_DMA_MEMORY_INC_MODE_DECREASE) ||\
|
||||
((__VALUE__) == FL_DMA_CH7_RAM_INC_MODE_INCREASE)||\
|
||||
((__VALUE__) == FL_DMA_CH7_RAM_INC_MODE_DECREASE)||\
|
||||
((__VALUE__) == FL_DMA_CH7_FLASH_INC_MODE_INCREASE)||\
|
||||
((__VALUE__) == FL_DMA_CH7_FLASH_INC_MODE_DECREASE))
|
||||
|
||||
#define IS_FL_DMA_PERIPH(__VALUE__) (((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION1)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION2)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION3)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION4)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION5)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION6)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION7)||\
|
||||
((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应DMA寄存器.
|
||||
* @param DMAx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_DMA_DeInit(DMA_Type *DMAx)
|
||||
{
|
||||
assert_param(IS_FL_DMA_INSTANCE(DMAx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAHBPeripheral(RMU, FL_RMU_RSTAHB_DMA);
|
||||
FL_RMU_DisableResetAHBPeripheral(RMU, FL_RMU_RSTAHB_DMA);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_DMA);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 DMA_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param DMAx DMAx
|
||||
* @param DMA_InitStruct 指向一个 @ref FL_DMA_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_DMA_CHANNEL_0
|
||||
* @arg @ref FL_DMA_CHANNEL_1
|
||||
* @arg @ref FL_DMA_CHANNEL_2
|
||||
* @arg @ref FL_DMA_CHANNEL_3
|
||||
* @arg @ref FL_DMA_CHANNEL_4
|
||||
* @arg @ref FL_DMA_CHANNEL_5
|
||||
* @arg @ref FL_DMA_CHANNEL_6
|
||||
* @arg @ref FL_DMA_CHANNEL_7
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_DMA_Init(DMA_Type *DMAx, FL_DMA_InitTypeDef *initStruct, uint32_t channel)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_DMA_INSTANCE(DMAx));
|
||||
assert_param(IS_FL_DMA_PRIORITY(initStruct->priority));
|
||||
assert_param(IS_FL_DMA_CIRC_MODE(initStruct->circMode));
|
||||
assert_param(IS_FL_DMA_DIRECION(initStruct->direction));
|
||||
assert_param(IS_FL_DMA_DATA_SIZE(initStruct->dataSize));
|
||||
assert_param(IS_FL_DMA_INCMODE(initStruct->memoryAddressIncMode));
|
||||
/* 开启时钟 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_DMA);
|
||||
/* 配置通道优先级 */
|
||||
FL_DMA_SetPriority(DMAx, initStruct->priority, channel);
|
||||
/* RAM地址方向 */
|
||||
FL_DMA_SetMemoryIncrementMode(DMAx, initStruct->memoryAddressIncMode, channel);
|
||||
/* 传输方向 */
|
||||
FL_DMA_SetTransmissionDirection(DMAx, initStruct->direction, channel);
|
||||
/* 数据宽度 */
|
||||
FL_DMA_SetBandwidth(DMAx, initStruct->dataSize, channel);
|
||||
/* 循环模式 */
|
||||
if(initStruct->circMode == FL_ENABLE)
|
||||
{
|
||||
if(channel == FL_DMA_CHANNEL_7)
|
||||
{
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_DMA_EnableCircularMode(DMAx, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_DMA_DisableCircularMode(DMAx, channel);
|
||||
}
|
||||
/* 如果是通道7 外设地址实际就是FLASH地址，因此这里针对通道7做了单独处理 */
|
||||
if(channel != FL_DMA_CHANNEL_7)
|
||||
{
|
||||
assert_param(IS_FL_DMA_PERIPH(initStruct->periphAddress));
|
||||
FL_DMA_SetPeripheralMap(DMAx, initStruct->periphAddress, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_DMA_SetFlashAddrIncremental(DMAx, initStruct->flashAddressIncMode);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 CRC_InitStruct 为默认配置
|
||||
* @param CRC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_CRC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_DMA_StructInit(FL_DMA_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->circMode = FL_DISABLE;
|
||||
initStruct->dataSize = FL_DMA_BANDWIDTH_8B;
|
||||
initStruct->direction = FL_DMA_DIR_PERIPHERAL_TO_RAM;
|
||||
initStruct->periphAddress = FL_DMA_PERIPHERAL_FUNCTION1;
|
||||
initStruct->priority = FL_DMA_PRIORITY_LOW;
|
||||
initStruct->memoryAddressIncMode = FL_DMA_MEMORY_INC_MODE_INCREASE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 启动一次DMA传输.
|
||||
* @param DMAx DMAx
|
||||
* @param configStruct 指向一个 @ref FL_DMA_ConfigTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_DMA_CHANNEL_0
|
||||
* @arg @ref FL_DMA_CHANNEL_1
|
||||
* @arg @ref FL_DMA_CHANNEL_2
|
||||
* @arg @ref FL_DMA_CHANNEL_3
|
||||
* @arg @ref FL_DMA_CHANNEL_4
|
||||
* @arg @ref FL_DMA_CHANNEL_5
|
||||
* @arg @ref FL_DMA_CHANNEL_6
|
||||
* @arg @ref FL_DMA_CHANNEL_7
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 过程发生错误可能是超时也可能是地址非法
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_DMA_StartTransmission(DMA_Type *DMAx, FL_DMA_ConfigTypeDef *configStruct, uint32_t channel)
|
||||
{
|
||||
/* 配置传输个数 */
|
||||
FL_DMA_WriteTransmissionSize(DMAx, configStruct->transmissionCount, channel);
|
||||
/* 配置Memory地址 */
|
||||
FL_DMA_WriteMemoryAddress(DMAx, configStruct->memoryAddress, channel);
|
||||
/* 清除通道中断标志位 */
|
||||
FL_DMA_ClearFlag_TransferHalfComplete(DMAx, channel);
|
||||
FL_DMA_ClearFlag_TransferComplete(DMAx, channel);
|
||||
/* 使能DMA通道使能开关 */
|
||||
FL_DMA_EnableChannel(DMAx, channel);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_DIVAS_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
263
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_exti.c
Normal file
263
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_exti.c
Normal file
@ -0,0 +1,263 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_exti.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of EXTI FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_EXTI_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_EXTI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FL_GPIO_EXTI_LINE_0)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_1)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_2)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_3)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_4)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_5)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_6)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_7)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_8)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_9)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_10)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_11)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_12)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_13)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_14)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_15)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_16)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_17)||\
|
||||
((INSTANCE) == FL_GPIO_EXTI_LINE_18))
|
||||
|
||||
#define IS_EXTI_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_CMU_EXTI_CLK_SOURCE_HCLK)||\
|
||||
((__VALUE__) == FL_CMU_EXTI_CLK_SOURCE_LSCLK))
|
||||
|
||||
#define IS_EXTI_INPUT_GROUP(__VALUE__) (((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP0)||\
|
||||
((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP1)||\
|
||||
((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP2)||\
|
||||
((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP3))
|
||||
|
||||
#define IS_EXTI_TRIG_EDGE(__VALUE__) (((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_BOTH))
|
||||
|
||||
#define IS_EXTI_FILTER(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private consts ------------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_FL_Private_Consts
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pSetExtiLineFunc)(GPIO_COMMON_Type *, uint32_t);
|
||||
static const pSetExtiLineFunc setExtiLineFuncs[] =
|
||||
{
|
||||
FL_GPIO_SetExtiLine0,
|
||||
FL_GPIO_SetExtiLine1,
|
||||
FL_GPIO_SetExtiLine2,
|
||||
FL_GPIO_SetExtiLine3,
|
||||
FL_GPIO_SetExtiLine4,
|
||||
FL_GPIO_SetExtiLine5,
|
||||
FL_GPIO_SetExtiLine6,
|
||||
FL_GPIO_SetExtiLine7,
|
||||
FL_GPIO_SetExtiLine8,
|
||||
FL_GPIO_SetExtiLine9,
|
||||
FL_GPIO_SetExtiLine10,
|
||||
FL_GPIO_SetExtiLine11,
|
||||
FL_GPIO_SetExtiLine12,
|
||||
FL_GPIO_SetExtiLine13,
|
||||
FL_GPIO_SetExtiLine14,
|
||||
FL_GPIO_SetExtiLine15,
|
||||
FL_GPIO_SetExtiLine16,
|
||||
FL_GPIO_SetExtiLine17,
|
||||
FL_GPIO_SetExtiLine18,
|
||||
};
|
||||
|
||||
typedef void (*pSetTrigEdgeFunc)(GPIO_COMMON_Type *, uint32_t, uint32_t);
|
||||
static const pSetTrigEdgeFunc setTrigEdgeFuncs[] =
|
||||
{
|
||||
FL_GPIO_SetTriggerEdge0,
|
||||
FL_GPIO_SetTriggerEdge1,
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI通用配置设置
|
||||
*
|
||||
* @param EXTI_CommonInitStruct 指向 @ref FL_EXTI_CommonInitTypeDef 类型的结构体，它包含EXTI外设通用配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS EXTI配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_EXTI_CommonInit(FL_EXTI_CommonInitTypeDef *EXTI_CommonInitStruct)
|
||||
{
|
||||
assert_param(IS_EXTI_CLK_SOURCE(EXTI_CommonInitStruct->clockSource));
|
||||
/* 使能IO时钟寄存器总线时钟 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_PAD);
|
||||
/* 使能并配置外部中断时钟源 */
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_EXTI);
|
||||
FL_CMU_SetEXTIClockSource(EXTI_CommonInitStruct->clockSource);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 复位EXTI通用配置设置
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 发生错误
|
||||
* -FL_PASS EXTI通用设置复位成功
|
||||
*/
|
||||
FL_ErrorStatus FL_EXTI_CommonDeinit(void)
|
||||
{
|
||||
/* 关闭外部中断时钟源 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_EXTI);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 EXTI_CommonInitStruct 为默认配置
|
||||
* @param EXTI_CommonInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_EXTI_CommonInitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_EXTI_CommonStructInit(FL_EXTI_CommonInitTypeDef *EXTI_CommonInitStruct)
|
||||
{
|
||||
EXTI_CommonInitStruct->clockSource = FL_CMU_EXTI_CLK_SOURCE_LSCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI配置设置
|
||||
*
|
||||
* @param extiLineX 外设入口地址
|
||||
* @param EXTI_InitStruct 指向 @ref FL_EXTI_InitTypeDef 类型的结构体，它包含EXTI外设配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS EXTI配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_EXTI_Init(uint32_t extiLineX, FL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
uint8_t extiLineId;
|
||||
uint32_t tmpExtiLineX;
|
||||
uint32_t i = 0;
|
||||
/* 通过内核时钟计算200us延时的计数个数 */
|
||||
uint32_t temp = SystemCoreClock*2/10000 ;
|
||||
/* 检查参数合法性 */
|
||||
assert_param(IS_EXTI_ALL_INSTANCE(extiLineX));
|
||||
assert_param(IS_EXTI_INPUT_GROUP(EXTI_InitStruct->input));
|
||||
assert_param(IS_EXTI_TRIG_EDGE(EXTI_InitStruct->triggerEdge));
|
||||
assert_param(IS_EXTI_FILTER(EXTI_InitStruct->filter));
|
||||
/* 获取EXTI中断线对应id号 */
|
||||
tmpExtiLineX = extiLineX;
|
||||
for(extiLineId = 0; tmpExtiLineX != FL_GPIO_EXTI_LINE_0; tmpExtiLineX >>= 1, extiLineId++);
|
||||
/* 设置中断线连接的IO */
|
||||
setExtiLineFuncs[extiLineId](GPIO, EXTI_InitStruct->input << (2 * (extiLineId % 16)));
|
||||
/* 设置数字滤波 */
|
||||
EXTI_InitStruct->filter == FL_ENABLE ? FL_GPIO_EnableDigitalFilter(GPIO, extiLineX) : FL_GPIO_DisableDigitalFilter(GPIO, extiLineX);
|
||||
/* 设置中断线触发边沿 */
|
||||
setTrigEdgeFuncs[extiLineId / 16](GPIO, extiLineX, EXTI_InitStruct->triggerEdge);
|
||||
/* 等待至少周期6个LSCLK周期，约200us */
|
||||
for(i=0;i<temp;i++)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
/* 清除外部中断标志 */
|
||||
FL_GPIO_ClearFlag_EXTI(GPIO, extiLineX);
|
||||
/* 清除中断挂起 */
|
||||
NVIC_ClearPendingIRQ(GPIO_IRQn);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 复位EXTI配置设置
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 发生错误
|
||||
* -FL_PASS EXTI设置复位成功
|
||||
*/
|
||||
FL_ErrorStatus FL_EXTI_DeInit(uint32_t extiLineX)
|
||||
{
|
||||
uint8_t extiLineId;
|
||||
uint32_t tmpExtiLineX;
|
||||
/* 检查参数合法性 */
|
||||
assert_param(IS_EXTI_ALL_INSTANCE(extiLineX));
|
||||
/* 获取EXTI中断线对应id号 */
|
||||
tmpExtiLineX = extiLineX;
|
||||
for(extiLineId = 0; tmpExtiLineX != FL_GPIO_EXTI_LINE_0; tmpExtiLineX >>= 1, extiLineId++);
|
||||
/* 清除外部中断标志 */
|
||||
FL_GPIO_ClearFlag_EXTI(GPIO, extiLineX);
|
||||
/* 中断线触发边沿禁止 */
|
||||
setTrigEdgeFuncs[extiLineId / 16](GPIO, extiLineX, FL_GPIO_EXTI_TRIGGER_EDGE_DISABLE);
|
||||
/* 禁止数字滤波 */
|
||||
FL_GPIO_DisableDigitalFilter(GPIO, extiLineX);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 EXTI_InitStruct 为默认配置
|
||||
* @param EXTI_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_EXTI_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->filter = FL_DISABLE;
|
||||
EXTI_InitStruct->input = FL_GPIO_EXTI_INPUT_GROUP0;
|
||||
EXTI_InitStruct->triggerEdge = FL_GPIO_EXTI_TRIGGER_EDGE_RISING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_EXTI_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
568
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_flash.c
Normal file
568
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_flash.c
Normal file
@ -0,0 +1,568 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_flash.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of FLASH FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_FLASH_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_ALL_INSTANCE(INTENCE) (((INTENCE) == FLASH))
|
||||
|
||||
#define IS_FL_FLASH_PAGE_NUM(__VALUE__) ((uint32_t)(__VALUE__) < FL_FLASH_MAX_PAGE_NUM)
|
||||
|
||||
#define IS_FL_FLASH_SECTOR_NUM(__VALUE__) ((uint32_t)(__VALUE__) < FL_FLASH_MAX_SECTOR_NUM)
|
||||
|
||||
#define IS_FL_FLASH_MAX_ADDR(__VALUE__) ((uint32_t)(__VALUE__) <= FL_FLASH_ADDR_MAXPROGRAM)
|
||||
|
||||
#define IS_FL_FLASH_MAX_PAGE(__VALUE__) ((uint32_t)(__VALUE__) < FL_FLASH_MAX_PAGE_NUM)
|
||||
|
||||
#define IS_FL_FLASH_MAX_SECTOR(__VALUE__) ((uint32_t)(__VALUE__) < FL_FLASH_MAX_SECTOR_NUM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Flash 页擦除函数，一个页为512byte.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param address 为需要擦除的页内任意地址，推荐使用页开始的首地址（字对齐）
|
||||
* .
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_PageErase(FLASH_Type *FLASHx, uint32_t address)
|
||||
{
|
||||
uint32_t timeout = 0;
|
||||
uint32_t primask;
|
||||
FL_ErrorStatus ret = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address));
|
||||
/*时钟使能*/
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
if((address % FL_FLASH_ADDRS_ALIGN) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR)
|
||||
{
|
||||
/*Flash 已经锁定，复位前无法操作*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
/*配置擦写类型*/
|
||||
FL_FLASH_SetFlashEraseType(FLASHx, FL_FLASH_ERASE_TYPE_PAGE);
|
||||
/* 开始擦除页*/
|
||||
FL_FLASH_EnableErase(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_ERASE_KEY);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PGAE_ERASE_KEY);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_ClearFlag_EraseComplete(FLASHx);
|
||||
FL_FLASH_ClearFlag_ClockError(FLASHx);
|
||||
FL_FLASH_ClearFlag_AuthenticationError(FLASHx);
|
||||
/* 擦请求 */
|
||||
*((uint32_t *)address) = FL_FLASH_ERASE_REQUEST;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if((timeout > FL_FLASH_ERASE_TIMEOUT)\
|
||||
|| (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx)))
|
||||
{
|
||||
/* 超时或出现错误 */
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
else
|
||||
if(FL_FLASH_IsActiveFlag_EraseComplete(FLASHx))
|
||||
{
|
||||
/*编程成功*/
|
||||
FL_FLASH_ClearFlag_EraseComplete(FLASHx);
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Flash 扇区擦除函数，一个扇区为2k byte.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param address 为需要擦除的扇区内任意地址，推荐使用扇区开始的首地址（字对齐）
|
||||
* .
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_SectorErase(FLASH_Type *FLASHx, uint32_t address)
|
||||
{
|
||||
uint32_t timeout = 0;
|
||||
uint32_t primask;
|
||||
FL_ErrorStatus ret = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address));
|
||||
/*时钟使能*/
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
if((address % FL_FLASH_ADDRS_ALIGN) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR)
|
||||
{
|
||||
/*Flash 已经锁定，复位前无法操作*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
/*配置擦写类型*/
|
||||
FL_FLASH_SetFlashEraseType(FLASHx, FL_FLASH_ERASE_TYPE_SECTOR);
|
||||
/* 开始擦除扇区*/
|
||||
FL_FLASH_EnableErase(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_ERASE_KEY);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_SECTOR_ERASE_KEY);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_ClearFlag_EraseComplete(FLASHx);
|
||||
FL_FLASH_ClearFlag_ClockError(FLASHx);
|
||||
FL_FLASH_ClearFlag_AuthenticationError(FLASHx);
|
||||
/* 擦请求 */
|
||||
*((uint32_t *)address) = FL_FLASH_ERASE_REQUEST;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if((timeout > FL_FLASH_ERASE_TIMEOUT)\
|
||||
|| (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx)))
|
||||
{
|
||||
/* 超时或出现错误 */
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
else
|
||||
if(FL_FLASH_IsActiveFlag_EraseComplete(FLASHx))
|
||||
{
|
||||
/*编程成功*/
|
||||
FL_FLASH_ClearFlag_EraseComplete(FLASHx);
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 单次编程函数，编程地址必须对齐到Word边界.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param address 为需要编程的已经擦除过的扇区内任意地址，非对齐地址编程将触发fault。
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_Program_Word(FLASH_Type *FLASHx, uint32_t address, uint32_t data)
|
||||
{
|
||||
uint32_t timeout = 0;
|
||||
uint32_t primask;
|
||||
FL_ErrorStatus ret = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address));
|
||||
/*时钟使能*/
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
if((address % FL_FLASH_ADDRS_ALIGN) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR)
|
||||
{
|
||||
/*Flash 已经锁定，复位前无法操作*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
/* 开始编程*/
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_ClearFlag_ClockError(FLASHx);
|
||||
FL_FLASH_ClearFlag_AuthenticationError(FLASHx);
|
||||
*((uint32_t *)address) = data;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if((timeout > FL_FLASH_ERASE_TIMEOUT)\
|
||||
|| (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx)))
|
||||
{
|
||||
/* 超时或出现错误 */
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
else
|
||||
if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx))
|
||||
{
|
||||
/*编程成功*/
|
||||
FL_FLASH_ClearFlag_ProgramComplete(FLASHx);
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 页编程函数，编程地址必须对齐到Page边界.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param PageNum 为需要编程的已经擦除过的扇区号，FM33LG04最大为256，非对齐地址编程将触发fault。
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_Program_Page(FLASH_Type *FLASHx, uint32_t pageNum, uint32_t *data)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t primask;
|
||||
uint32_t address;
|
||||
uint32_t timeout;
|
||||
FL_ErrorStatus ret=FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_PAGE((uint32_t)pageNum));
|
||||
address = pageNum * FL_FLASH_PGAE_SIZE_BYTE;
|
||||
/* 页对齐*/
|
||||
if((address % FL_FLASH_PGAE_SIZE_BYTE) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_ClearFlag_ClockError(FLASHx);
|
||||
FL_FLASH_ClearFlag_AuthenticationError(FLASHx);
|
||||
for(count = 0; count < FL_FLASH_PGAE_SIZE_BYTE; count += 4)
|
||||
{
|
||||
timeout = 0;
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
*((uint32_t *)address) = *data;
|
||||
address += 4;
|
||||
data++;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if((timeout > FL_FLASH_ERASE_TIMEOUT)\
|
||||
|| (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx)))
|
||||
{
|
||||
/* 超时或出现错误 */
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx))
|
||||
{
|
||||
/*编程成功*/
|
||||
FL_FLASH_ClearFlag_ProgramComplete(FLASHx);
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(ret == FL_FAIL)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 扇区编程函数，编程地址必须对齐到Sector边界.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param sectorNum 为需要编程的已经擦除过的扇区号，最大为128，非对齐地址编程将触发fault。
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_Program_Sector(FLASH_Type *FLASHx, uint32_t sectorNum, uint32_t *data)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t primask;
|
||||
uint32_t address;
|
||||
uint32_t timeout;
|
||||
FL_ErrorStatus ret=FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_SECTOR((uint32_t)sectorNum));
|
||||
address = sectorNum * FL_FLASH_SECTOR_SIZE_BYTE;
|
||||
/* Sector对齐*/
|
||||
if((address % FL_FLASH_SECTOR_SIZE_BYTE) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_ClearFlag_ClockError(FLASHx);
|
||||
FL_FLASH_ClearFlag_AuthenticationError(FLASHx);
|
||||
for(count = 0; count < FL_FLASH_SECTOR_SIZE_BYTE; count += 4)
|
||||
{
|
||||
timeout = 0;
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
*((uint32_t *)address) = *data;
|
||||
address += 4;
|
||||
data++;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if((timeout > FL_FLASH_ERASE_TIMEOUT)\
|
||||
|| (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\
|
||||
|| (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx)))
|
||||
{
|
||||
/* 超时或出现错误 */
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx))
|
||||
{
|
||||
/*编程成功*/
|
||||
FL_FLASH_ClearFlag_ProgramComplete(FLASHx);
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(ret == FL_FAIL)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA编程函数，编程地址必须对齐到half-page，长度固定为64字.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param address 待编程Flash地址
|
||||
* @param *data 待写入Flash数据
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_Write_Dma(FLASH_Type *FLASHx, uint32_t address, uint32_t *data)
|
||||
{
|
||||
FL_ErrorStatus ret=FL_PASS;
|
||||
uint32_t primask;
|
||||
uint32_t timeout;
|
||||
FL_DMA_InitTypeDef DMA_InitStruct = {0};
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_ADDR(address));
|
||||
/* 半页对齐*/
|
||||
if((address % (FL_FLASH_PGAE_SIZE_BYTE / 2)) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
/* Key 序列*/
|
||||
primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1);
|
||||
FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2);
|
||||
__set_PRIMASK(primask);
|
||||
FL_FLASH_EnableProgram(FLASHx);
|
||||
DMA_InitStruct.circMode = FL_DISABLE;
|
||||
DMA_InitStruct.direction = FL_DMA_DIR_RAM_TO_FLASH;
|
||||
DMA_InitStruct.memoryAddressIncMode = FL_DMA_CH7_RAM_INC_MODE_INCREASE;
|
||||
DMA_InitStruct.flashAddressIncMode = FL_DMA_CH7_FLASH_INC_MODE_INCREASE;
|
||||
DMA_InitStruct.priority = FL_DMA_PRIORITY_HIGH;
|
||||
FL_DMA_Init(DMA, &DMA_InitStruct, FL_DMA_CHANNEL_7);
|
||||
/* Channel7 Flash 指针地址为（word 地址） */
|
||||
FL_DMA_WriteFlashAddress(DMA, address >> 2);
|
||||
/* Channel7 RAM 指针地址为（word 地址）*/
|
||||
FL_DMA_WriteMemoryAddress(DMA, (uint32_t)data >> 2, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_WriteTransmissionSize(DMA, 64 - 1, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_ClearFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_EnableChannel(DMA, FL_DMA_CHANNEL_7);
|
||||
timeout = 0;
|
||||
while(1)
|
||||
{
|
||||
timeout++;
|
||||
if(timeout > FL_FLASH_ERASE_TIMEOUT)
|
||||
{
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
if(FL_DMA_IsActiveFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7) == FL_SET)
|
||||
{
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
FL_FLASH_LockFlash(FLASHx);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_FLASH);
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_FLASH);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA读取函数，编程地址必须对齐到Word边界.
|
||||
* @param FLASHx FLASH Port
|
||||
* @param address 读取数据Flash地址
|
||||
* @param *data 读出数据存储区
|
||||
* @param length 读出数据的字长度
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 擦写发生错误
|
||||
* -FL_PASS 擦写成功
|
||||
*/
|
||||
FL_ErrorStatus FL_FLASH_Read_Dma(FLASH_Type *FLASHx, uint32_t address, uint32_t *data, uint16_t length)
|
||||
{
|
||||
FL_ErrorStatus ret=FL_PASS;
|
||||
uint32_t Timeout;
|
||||
FL_DMA_InitTypeDef DMA_InitStruct = {0};
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FLASH_ALL_INSTANCE(FLASHx));
|
||||
assert_param(IS_FL_FLASH_MAX_ADDR(address));
|
||||
/* 字对齐*/
|
||||
if((address % FL_FLASH_ADDRS_ALIGN) != 0)
|
||||
{
|
||||
/*地址未对齐*/
|
||||
return FL_FAIL;
|
||||
}
|
||||
DMA_InitStruct.circMode = FL_DISABLE;
|
||||
DMA_InitStruct.direction = FL_DMA_DIR_FLASH_TO_RAM;
|
||||
DMA_InitStruct.memoryAddressIncMode = FL_DMA_CH7_RAM_INC_MODE_INCREASE;
|
||||
DMA_InitStruct.flashAddressIncMode = FL_DMA_CH7_FLASH_INC_MODE_INCREASE;
|
||||
DMA_InitStruct.priority = FL_DMA_PRIORITY_HIGH;
|
||||
FL_DMA_Init(DMA, &DMA_InitStruct, FL_DMA_CHANNEL_7);
|
||||
/* Channel7 Flash 指针地址为（word 地址） */
|
||||
FL_DMA_WriteFlashAddress(DMA, address >> 2);
|
||||
/* Channel7 RAM 指针地址为（word 地址）*/
|
||||
FL_DMA_WriteMemoryAddress(DMA, (uint32_t)data >> 2, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_WriteTransmissionSize(DMA, length - 1, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_ClearFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7);
|
||||
FL_DMA_EnableChannel(DMA, FL_DMA_CHANNEL_7);
|
||||
Timeout = 0;
|
||||
while(1)
|
||||
{
|
||||
Timeout++;
|
||||
if(Timeout > FL_FLASH_ERASE_TIMEOUT)
|
||||
{
|
||||
ret = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
if(FL_DMA_IsActiveFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7) == FL_SET)
|
||||
{
|
||||
ret = FL_PASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_FLASH_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
405
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_gpio.c
Normal file
405
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_gpio.c
Normal file
@ -0,0 +1,405 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_gpio.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of GPIO FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_GPIO_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPIO_ALL_INSTANCE(INTENCE) (((INTENCE) == GPIOA)||\
|
||||
((INTENCE) == GPIOB)||\
|
||||
((INTENCE) == GPIOC)||\
|
||||
((INTENCE) == GPIOD)||\
|
||||
((INTENCE) == GPIOE))
|
||||
|
||||
#define IS_FL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\
|
||||
((__VALUE__) <= (FL_GPIO_PIN_ALL)))
|
||||
|
||||
#define IS_FL_GPIO_MODE(__VALUE__) (((__VALUE__) == FL_GPIO_MODE_ANALOG)||\
|
||||
((__VALUE__) == FL_GPIO_MODE_INPUT)||\
|
||||
((__VALUE__) == FL_GPIO_MODE_OUTPUT)||\
|
||||
((__VALUE__) == FL_GPIO_MODE_DIGITAL))
|
||||
|
||||
#define IS_FL_GPIO_OPENDRAIN(__VALUE__) (((__VALUE__) == FL_GPIO_OUTPUT_OPENDRAIN)||\
|
||||
((__VALUE__) == FL_GPIO_OUTPUT_PUSHPULL))
|
||||
|
||||
#define IS_FL_GPIO_PULL_UP(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_GPIO_ANALOG_SWITCH(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_GPIO_WKUP_ENTRY(__VALUE__) (((__VALUE__) == FL_GPIO_WKUP_INT_ENTRY_NMI)||\
|
||||
((__VALUE__) == FL_GPIO_WKUP_INT_ENTRY_NUM_38))
|
||||
|
||||
#define IS_FL_GPIO_WKUP_EDGE(__VALUE__) (((__VALUE__) == FL_GPIO_WAKEUP_TRIGGER_RISING)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_TRIGGER_FALLING)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_TRIGGER_BOTH))
|
||||
|
||||
|
||||
#define IS_FL_GPIO_WKUP_NUM(__VALUE__) (((__VALUE__) == FL_GPIO_WAKEUP_0)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_1)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_2)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_3)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_4)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_5)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_6)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_7)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_8)||\
|
||||
((__VALUE__) == FL_GPIO_WAKEUP_9))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应GPIO控制寄存器.
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_GPIO_DeInit(GPIO_Type *GPIOx, uint32_t pin)
|
||||
{
|
||||
uint32_t pinPos = 0x00000000U;
|
||||
uint32_t currentPin = 0x00000000U;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_FL_GPIO_PIN(pin));
|
||||
/* 恢复寄存器值为默认值 */
|
||||
while(((pin) >> pinPos) != 0x00000000U)
|
||||
{
|
||||
/* 获取当前遍历到的Pin脚 */
|
||||
currentPin = (pin) & (0x00000001U << pinPos);
|
||||
if(currentPin)
|
||||
{
|
||||
FL_GPIO_SetPinMode(GPIOx, currentPin, FL_GPIO_MODE_INPUT);
|
||||
FL_GPIO_DisablePinInput(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinPullup(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinAnalogSwitch(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinRemap(GPIOx, currentPin);
|
||||
}
|
||||
pinPos++;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
#if defined (FM33LG0x3A) /* 仅针对32pin芯片处理 */
|
||||
/**
|
||||
* @brief 复用GPIO数据类型,单个元素为一组复用的GPIO
|
||||
*/
|
||||
static const struct MultiplexGpioType
|
||||
{
|
||||
/* 成员元素 */
|
||||
const struct
|
||||
{
|
||||
GPIO_Type *GPIox; /* 元素信息: GPIO的Port索引 */
|
||||
uint32_t Pin; /* 元素信息: GPIO的Pin索引 */
|
||||
} MultiplexGpioElement[2]; /* 一组复用关系，无先后顺序 */
|
||||
|
||||
} MultiplexGpioTable[] = /* 复用GPIO的表格清单 */
|
||||
{
|
||||
{ {{GPIOA, (uint32_t)FL_GPIO_PIN_9 }/*PA9 */, {GPIOA, (uint32_t)FL_GPIO_PIN_11}/*PA11*/} },/* 此为一组复用关系 */
|
||||
{ {{GPIOB, (uint32_t)FL_GPIO_PIN_0 }/*PB0 */, {GPIOA, (uint32_t)FL_GPIO_PIN_12}/*PA12*/} },
|
||||
{ {{GPIOB, (uint32_t)FL_GPIO_PIN_7 }/*PB7 */, {GPIOB, (uint32_t)FL_GPIO_PIN_8 }/*PB8 */} },
|
||||
{ {{GPIOB, (uint32_t)FL_GPIO_PIN_12}/*PB12*/, {GPIOE, (uint32_t)FL_GPIO_PIN_1 }/*PE1 */} },
|
||||
{ {{GPIOC, (uint32_t)FL_GPIO_PIN_2 }/*PC2 */, {GPIOD, (uint32_t)FL_GPIO_PIN_12}/*PD12*/} },
|
||||
{ {{GPIOD, (uint32_t)FL_GPIO_PIN_11}/*PD11*/, {GPIOD, (uint32_t)FL_GPIO_PIN_0 }/*PD0 */} },
|
||||
{ {{GPIOD, (uint32_t)FL_GPIO_PIN_6 }/*PD6 */, {GPIOD, (uint32_t)FL_GPIO_PIN_1 }/*PD1 */} }
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 复用GPIO的组数
|
||||
*/
|
||||
static const uint32_t u32MultiplexGpioCount =\
|
||||
(uint32_t)((sizeof(MultiplexGpioTable)) / (sizeof(MultiplexGpioTable[0])));
|
||||
|
||||
/**
|
||||
* @brief 针对复用GPIO，如有一个GPIO使用，则将另一个GPIO配置为高阻抗，避免相互影响
|
||||
* @param GPIOx 当前使用的GPIO Port索引
|
||||
* @param pin 当前使用的GPIO Pin索引
|
||||
* @retval 无
|
||||
*/
|
||||
static void FL_GPIO_Multiplex_DeInit(GPIO_Type *GPIOx, uint32_t pin)
|
||||
{
|
||||
/* 指向复用GPIO表格的指针 */
|
||||
const struct MultiplexGpioType *pMultiplexGpio = MultiplexGpioTable;
|
||||
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_FL_GPIO_PIN(pin));
|
||||
|
||||
for( ; pMultiplexGpio < (MultiplexGpioTable + u32MultiplexGpioCount); pMultiplexGpio++)
|
||||
{
|
||||
if( (pMultiplexGpio->MultiplexGpioElement[0].Pin == pin)\
|
||||
&& (pMultiplexGpio->MultiplexGpioElement[0].GPIox == GPIOx))
|
||||
{
|
||||
/* 未使用的GPIO执行高阻抗初始化 */
|
||||
FL_GPIO_DeInit(pMultiplexGpio->MultiplexGpioElement[1].GPIox,\
|
||||
pMultiplexGpio->MultiplexGpioElement[1].Pin );
|
||||
break;
|
||||
}
|
||||
else if( (pMultiplexGpio->MultiplexGpioElement[1].Pin == pin)\
|
||||
&& (pMultiplexGpio->MultiplexGpioElement[1].GPIox == GPIOx))
|
||||
{
|
||||
/* 未使用的GPIO执行高阻抗初始化 */
|
||||
FL_GPIO_DeInit(pMultiplexGpio->MultiplexGpioElement[0].GPIox,\
|
||||
pMultiplexGpio->MultiplexGpioElement[0].Pin );
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* #if defined (FM33LG0x3A) */
|
||||
|
||||
/**
|
||||
* @brief 根据 GPIO_InitStruct的配置信息初始化对应外设.
|
||||
* @param GPIOx GPIO Port
|
||||
* @param GPIO_InitStruct 指向一个 @ref FL_GPIO_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPIO_Init(GPIO_Type *GPIOx, FL_GPIO_InitTypeDef *initStruct)
|
||||
{
|
||||
uint32_t pinPos = 0x00000000U;
|
||||
uint32_t currentPin = 0x00000000U;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_FL_GPIO_PIN(initStruct->pin));
|
||||
assert_param(IS_FL_GPIO_MODE(initStruct->mode));
|
||||
assert_param(IS_FL_GPIO_OPENDRAIN(initStruct->outputType));
|
||||
assert_param(IS_FL_GPIO_PULL_UP(initStruct->pull));
|
||||
assert_param(IS_FL_GPIO_ANALOG_SWITCH(initStruct->analogSwitch));
|
||||
/* 使能时钟总线 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_PAD);
|
||||
/* 这里考虑到PIN有可能不止一个因此需要遍历 */
|
||||
while(((initStruct->pin) >> pinPos) != 0x00000000U)
|
||||
{
|
||||
/* 获取当前遍历到的Pin脚 */
|
||||
currentPin = (initStruct->pin) & (0x00000001U << pinPos);
|
||||
if(currentPin)
|
||||
{
|
||||
#if defined (FM33LG0x3A) /* 仅针对32pin芯片处理 */
|
||||
/* 检查复用引脚，并做处理 */
|
||||
FL_GPIO_Multiplex_DeInit(GPIOx, currentPin);
|
||||
#endif /* #if defined (FM33LG0x3A) */
|
||||
/* Pin脚模拟模式设置 */
|
||||
if(initStruct->mode == FL_GPIO_MODE_ANALOG)
|
||||
{
|
||||
FL_GPIO_DisablePinInput(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinPullup(GPIOx, currentPin);
|
||||
FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin);
|
||||
if(initStruct->analogSwitch == FL_ENABLE)
|
||||
{
|
||||
FL_GPIO_EnablePinAnalogSwitch(GPIOx, currentPin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_DisablePinAnalogSwitch(GPIOx, currentPin);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_DisablePinAnalogSwitch(GPIOx, currentPin);
|
||||
/* Pin脚输入使能控制 */
|
||||
if(initStruct->mode == FL_GPIO_MODE_INPUT)
|
||||
{
|
||||
FL_GPIO_EnablePinInput(GPIOx, currentPin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_DisablePinInput(GPIOx, currentPin);
|
||||
}
|
||||
/* Pin脚输出模式设置 */
|
||||
if(initStruct->outputType == FL_GPIO_OUTPUT_PUSHPULL)
|
||||
{
|
||||
FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_EnablePinOpenDrain(GPIOx, currentPin);
|
||||
}
|
||||
/* Pin脚上拉模式设置 */
|
||||
if(initStruct->pull)
|
||||
{
|
||||
FL_GPIO_EnablePinPullup(GPIOx, currentPin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_DisablePinPullup(GPIOx, currentPin);
|
||||
}
|
||||
}
|
||||
/* 数字模式复用功能选择 */
|
||||
if(initStruct->mode == FL_GPIO_MODE_DIGITAL)
|
||||
{
|
||||
/*重定向*/
|
||||
if(initStruct->remapPin == FL_ENABLE)
|
||||
{
|
||||
FL_GPIO_EnablePinRemap(GPIOx, currentPin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPIO_DisablePinRemap(GPIOx, currentPin);
|
||||
}
|
||||
}
|
||||
/* Pin脚工作模式设置 */
|
||||
FL_GPIO_SetPinMode(GPIOx, currentPin, initStruct->mode);
|
||||
}
|
||||
pinPos++;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 GPIO_InitStruct 为默认配置
|
||||
* @param GPIO_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_GPIO_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPIO_StructInit(FL_GPIO_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 复位配置信息 */
|
||||
initStruct->pin = FL_GPIO_PIN_ALL;
|
||||
initStruct->mode = FL_GPIO_MODE_INPUT;
|
||||
initStruct->outputType = FL_GPIO_OUTPUT_OPENDRAIN;
|
||||
initStruct->pull = FL_DISABLE;
|
||||
initStruct->remapPin = FL_DISABLE;
|
||||
initStruct->analogSwitch = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 WKUP_InitTypeDef的配置信息初始化对应外设.
|
||||
* @param WKUP_InitTypeDef 指向一个 @ref FL_WKUP_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @param Wkupx 唤醒入口
|
||||
* FL_GPIO_WKUP_0
|
||||
* FL_GPIO_WKUP_1
|
||||
* FL_GPIO_WKUP_2
|
||||
* FL_GPIO_WKUP_3
|
||||
* FL_GPIO_WKUP_4
|
||||
* FL_GPIO_WKUP_5
|
||||
* FL_GPIO_WKUP_6
|
||||
* FL_GPIO_WKUP_7
|
||||
* FL_GPIO_WKUP_8
|
||||
* FL_GPIO_WKUP_9
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_WKUP_Init(FL_WKUP_InitTypeDef *initStruct, uint32_t wakeup)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FL_GPIO_WKUP_NUM(wakeup));
|
||||
assert_param(IS_FL_GPIO_WKUP_EDGE(initStruct->polarity));
|
||||
FL_GPIO_EnableWakeup(GPIO, wakeup);
|
||||
FL_GPIO_SetWakeupEdge(GPIO, wakeup, initStruct->polarity);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 去初始化Wakeup设置.
|
||||
* @param Wkupx 唤醒入口
|
||||
* FL_GPIO_WKUP_0
|
||||
* FL_GPIO_WKUP_1
|
||||
* FL_GPIO_WKUP_2
|
||||
* FL_GPIO_WKUP_3
|
||||
* FL_GPIO_WKUP_4
|
||||
* FL_GPIO_WKUP_5
|
||||
* FL_GPIO_WKUP_6
|
||||
* FL_GPIO_WKUP_7
|
||||
* FL_GPIO_WKUP_8
|
||||
* FL_GPIO_WKUP_9
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_WKUP_DeInit(uint32_t wakeup)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FL_GPIO_WKUP_NUM(wakeup));
|
||||
FL_GPIO_DisableWakeup(GPIO, wakeup);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 GPIO_InitStruct 为默认配置
|
||||
* @param GPIO_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_GPIO_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_WKUP_StructInit(FL_WKUP_InitTypeDef *initStruct_Wakeup)
|
||||
{
|
||||
/* 复位配置信息 */
|
||||
initStruct_Wakeup->polarity = FL_GPIO_WAKEUP_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置所有IO口为输入模式、输入使能关闭（高阻态），SWD接口除外。
|
||||
* @note PD7和PD8为调试接口
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPIO_ALLPIN_LPM_MODE(void)
|
||||
{
|
||||
FL_GPIO_DeInit(GPIOA, FL_GPIO_PIN_ALL);
|
||||
FL_GPIO_DeInit(GPIOB, FL_GPIO_PIN_ALL);
|
||||
FL_GPIO_DeInit(GPIOC, FL_GPIO_PIN_ALL);
|
||||
FL_GPIO_DeInit(GPIOD, FL_GPIO_PIN_ALL &
|
||||
(~FL_GPIO_PIN_7) & (~FL_GPIO_PIN_8));
|
||||
FL_GPIO_DeInit(GPIOE, FL_GPIO_PIN_ALL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_GPIO_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
641
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_gptim.c
Normal file
641
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_gptim.c
Normal file
@ -0,0 +1,641 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_gptim.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of GPTIM FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_GPTIM_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPTIM_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPTIM_INSTANCE(TIMx) (((TIMx) == GPTIM0) || \
|
||||
((TIMx) == GPTIM1) || \
|
||||
((TIMx) == GPTIM2))
|
||||
|
||||
#define IS_FL_GPTIM_COUNTERMODE(__VALUE__) (((__VALUE__) == FL_GPTIM_COUNTER_DIR_UP) || \
|
||||
((__VALUE__) == FL_GPTIM_COUNTER_DIR_DOWN) || \
|
||||
((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_EDGE) || \
|
||||
((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_UP) || \
|
||||
((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN) || \
|
||||
((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN))
|
||||
|
||||
#define IS_FL_GPTIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV1) || \
|
||||
((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV2) || \
|
||||
((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV4))
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_CHANNEL_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_CHANNEL_MODE_OUTPUT) || \
|
||||
((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL) || \
|
||||
((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_CROSSOVER) || \
|
||||
((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_TRC))
|
||||
|
||||
#define IS_FL_GPTIM_IC_FILTER(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N2) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N4) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV2_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV2_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV4_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV4_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV8_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV8_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N5) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N5) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N8))
|
||||
|
||||
#define IS_FL_GPTIM_CHANNEL(__VALUE__) (((__VALUE__) == FL_GPTIM_CHANNEL_1)\
|
||||
|| ((__VALUE__) == FL_GPTIM_CHANNEL_2)\
|
||||
|| ((__VALUE__) == FL_GPTIM_CHANNEL_3)\
|
||||
|| ((__VALUE__) == FL_GPTIM_CHANNEL_4))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_SLAVE_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_SLAVE_MODE_PROHIBITED)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI1)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI2)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X4_TI1TI2)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_RISE_RST)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_HIGH_RUN)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_RISE_RUN)\
|
||||
|| ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_CLK))
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_TRIGGER_SRC(__VALUE__) (((__VALUE__) ==FL_GPTIM_TIM_TS_ITR0 )\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR1 )\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR2)\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR3)\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_TI1F_ED)\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_TI1FP1)\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_TI2FP2)\
|
||||
||((__VALUE__) ==FL_GPTIM_TIM_TS_ETRF))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_ETR_FILTER(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N2) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N4) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV2_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV2_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV4_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV4_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV8_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV8_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N5) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N8) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N5) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N6) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N8))
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_ETR_PSC(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_PSC_DIV1) ||\
|
||||
((__VALUE__) == FL_GPTIM_ETR_PSC_DIV2) ||\
|
||||
((__VALUE__) == FL_GPTIM_ETR_PSC_DIV4) ||\
|
||||
((__VALUE__) == FL_GPTIM_ETR_PSC_DIV8))
|
||||
|
||||
#define IS_FL_GPTIM_ETR_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_POLARITY_NORMAL) || \
|
||||
((__VALUE__) == FL_GPTIM_ETR_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_IC_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_GPTIM_IC_POLARITY_INVERT))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_IC_PSC(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_PSC_DIV1) \
|
||||
|| ((__VALUE__) == FL_GPTIM_IC_PSC_DIV2) \
|
||||
|| ((__VALUE__) == FL_GPTIM_IC_PSC_DIV4) \
|
||||
|| ((__VALUE__) == FL_GPTIM_IC_PSC_DIV8))
|
||||
|
||||
#define IS_FL_GPTIM_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_OC_POLARITY_NORMAL) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_GPTIM_OC_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_OC_MODE_FROZEN) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_ACTIVE) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_INACTIVE) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_TOGGLE) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_FORCED_INACTIVE) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_FORCED_ACTIVE) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_PWM1) \
|
||||
|| ((__VALUE__) == FL_GPTIM_OC_MODE_PWM2))
|
||||
|
||||
#define IS_FL_GPTIM_OC_FASTMODE(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_GPTIM_OC_PRELOAD(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_GPTIM_OC_ETR_CLEARN(__VALUE__) (((__VALUE__) == FL_ENABLE) \
|
||||
|| ((__VALUE__) == FL_DISABLE))
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_TRIGGER_DELAY(__VALUE__) (((__VALUE__) == FL_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ENABLE))
|
||||
|
||||
|
||||
#define IS_FL_GPTIM_IC_CAPTURE_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \
|
||||
|| ((__VALUE__) == FL_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup TIM_FL_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
static FL_ErrorStatus OCConfig(GPTIM_Type *TIMx, uint32_t Channel, FL_GPTIM_OC_InitTypeDef *TIM_OC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIM_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应GPTIMx寄存器.
|
||||
* @param GPTIMx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_DeInit(GPTIM_Type *TIMx)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPTIM_INSTANCE(TIMx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
if(TIMx == GPTIM0)
|
||||
{
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM0);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM0);
|
||||
/* 关闭外设时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM0);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM1)
|
||||
{
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM1);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM1);
|
||||
/* 关闭外设时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM1);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM2)
|
||||
{
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM2);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_GPTIM2);
|
||||
/* 关闭外设时钟 */
|
||||
FL_CMU_DisableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM2);
|
||||
}
|
||||
else
|
||||
{
|
||||
result = FL_FAIL;
|
||||
}
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 配置基本定时器时基单元（内部时钟源）.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_InitStruct 指向一个 @ref FL_GPTIM_InitTypeDef(时基配置结构体)
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_Init(GPTIM_Type *TIMx, FL_GPTIM_InitTypeDef *init)
|
||||
{
|
||||
uint32_t i = 5;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_GPTIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_GPTIM_COUNTERMODE(init->counterMode));
|
||||
assert_param(IS_FL_GPTIM_CLOCKDIVISION(init->clockDivision));
|
||||
/* 时钟总线使能配置 */
|
||||
if(TIMx == GPTIM0)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM0);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM1)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM1);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM2);
|
||||
}
|
||||
/* 计数器计数模式配置 */
|
||||
switch(init->counterMode)
|
||||
{
|
||||
/* 中心对称模式 */
|
||||
case FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN :
|
||||
case FL_GPTIM_COUNTER_ALIGNED_CENTER_UP :
|
||||
case FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN:
|
||||
FL_GPTIM_SetCounterAlignedMode(TIMx, init->counterMode);
|
||||
break;
|
||||
default:
|
||||
/* 边沿模式 */
|
||||
FL_GPTIM_SetCounterDirection(TIMx, init->counterMode);
|
||||
FL_GPTIM_SetCounterAlignedMode(TIMx, FL_GPTIM_COUNTER_ALIGNED_EDGE);
|
||||
break;
|
||||
}
|
||||
/* 自动重装载值 */
|
||||
FL_GPTIM_WriteAutoReload(TIMx, init->autoReload);
|
||||
/* 定时器分频系数与数字滤波器所使用的采样时钟分频比 */
|
||||
FL_GPTIM_SetClockDivision(TIMx, init->clockDivision);
|
||||
/* 时钟分频 */
|
||||
FL_GPTIM_WritePrescaler(TIMx, init->prescaler);
|
||||
/* 预装载配置 */
|
||||
if(init->autoReloadState == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_EnableARRPreload(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPTIM_DisableARRPreload(TIMx);
|
||||
}
|
||||
/* 手动触发更新事件，将配置值写入 */
|
||||
FL_GPTIM_GenerateUpdateEvent(TIMx);
|
||||
while((!FL_GPTIM_IsActiveFlag_Update(TIMx))&&i)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
FL_GPTIM_ClearFlag_Update(TIMx);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 FL_GPTIM_InitTypeDef 为默认配置
|
||||
* @param TIM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPTIM_StructInit(FL_GPTIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_InitStruct->prescaler = (uint16_t)0x0000;
|
||||
TIM_InitStruct->autoReloadState = FL_DISABLE;
|
||||
TIM_InitStruct->counterMode = FL_GPTIM_COUNTER_DIR_UP;
|
||||
TIM_InitStruct->autoReload = 0xFFFFU;
|
||||
TIM_InitStruct->clockDivision = FL_GPTIM_CLK_DIVISION_DIV1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置基本定时器外部时钟源模式，包括编码器模式.
|
||||
* @param TIMx Timer Instance
|
||||
* @param slave_init 指向一个 @ref FL_GPTIM_SlaveInitTypeDef 结构体
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_SlaveMode_Init(GPTIM_Type *TIMx, FL_GPTIM_SlaveInitTypeDef *slave_init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_GPTIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_GPTIM_SLAVE_MODE(slave_init->slaveMode));
|
||||
assert_param(IS_FL_GPTIM_TRIGGER_SRC(slave_init->triggerSrc));
|
||||
assert_param(IS_FL_GPTIM_TRIGGER_DELAY(slave_init->triggerDelay));
|
||||
/* 时钟总线使能配置 */
|
||||
if(TIMx == GPTIM0)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM0);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM1)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM1);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM2);
|
||||
}
|
||||
/* 触发延迟默认关闭 */
|
||||
FL_GPTIM_DisableMasterSlaveMode(TIMx);
|
||||
/* 关闭从模式以能写入TS */
|
||||
FL_GPTIM_SetSlaveMode(TIMx, 0);
|
||||
/* 从模式输入源选择 */
|
||||
FL_GPTIM_SetTriggerInput(TIMx, slave_init->triggerSrc);
|
||||
/* ITRx 输入源选择 */
|
||||
if(slave_init->triggerSrc <= FL_GPTIM_TIM_TS_ITR3)
|
||||
{
|
||||
/* 内部触发ITRx源选择 */
|
||||
FL_GPTIM_SetITRInput(TIMx, (1U << (slave_init->triggerSrc >> GPTIM_SMCR_TS_Pos)), slave_init->ITRSourceGroup);
|
||||
}
|
||||
/* 从模式选择 */
|
||||
FL_GPTIM_SetSlaveMode(TIMx, slave_init->slaveMode);
|
||||
/* 触发延迟默认关闭 */
|
||||
if(slave_init->triggerDelay == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_EnableMasterSlaveMode(TIMx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 FL_GPTIM_SlaveInitTypeDef 为默认配置
|
||||
* @param TIM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_SlaveInitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPTIM_SlaveMode_StructInit(FL_GPTIM_SlaveInitTypeDef *slave_init)
|
||||
{
|
||||
slave_init->ITRSourceGroup = 0;
|
||||
slave_init->slaveMode = FL_GPTIM_SLAVE_MODE_PROHIBITED;
|
||||
slave_init->triggerSrc = FL_GPTIM_TIM_TS_TI1FP1;
|
||||
slave_init->triggerDelay = FL_DISABLE;
|
||||
}
|
||||
/**
|
||||
* @brief 配置TIM触发输入捕获通道ETR.
|
||||
* @param TIMx Timer Instance
|
||||
* @param ETPolarity 极性
|
||||
* @param ETPrescaler 分频
|
||||
* @param ETR_Filter 滤波
|
||||
* @param etr_init 指向一个 @ref FL_GPTIM_ETR_InitTypeDef 结构体
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_ETR_Init(GPTIM_Type *TIMx, FL_GPTIM_ETR_InitTypeDef *etr_init)
|
||||
{
|
||||
assert_param(IS_FL_GPTIM_ETR_FILTER(etr_init->ETRFilter));
|
||||
assert_param(IS_FL_GPTIM_ETR_PSC(etr_init->ETRClockDivision));
|
||||
assert_param(IS_FL_GPTIM_ETR_POLARITY(etr_init->ETRPolarity));
|
||||
/* 时钟总线使能配置 */
|
||||
if(TIMx == GPTIM0)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM0);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM1)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM1);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM2);
|
||||
}
|
||||
/* 外部时钟极性 */
|
||||
FL_GPTIM_SetETRPolarity(TIMx, etr_init->ETRPolarity);
|
||||
/* 外部时钟滤波 */
|
||||
FL_GPTIM_SetETRFilter(TIMx, etr_init->ETRFilter);
|
||||
/* 外部时钟分频 */
|
||||
FL_GPTIM_SetETRPrescaler(TIMx, etr_init->ETRClockDivision);
|
||||
if(etr_init->useExternalTrigger == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_EnableExternalClock(TIMx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_GPTIM_DisableExternalClock(TIMx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 FL_GPTIM_ETRInitTypeDef 为默认配置
|
||||
* @param etr_init 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_ETR_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPTIM_ETR_StructInit(FL_GPTIM_ETR_InitTypeDef *etr_init)
|
||||
{
|
||||
etr_init->useExternalTrigger = FL_DISABLE;
|
||||
etr_init->ETRFilter = FL_GPTIM_ETR_FILTER_DIV1;
|
||||
etr_init->ETRPolarity = FL_GPTIM_ETR_POLARITY_NORMAL;
|
||||
etr_init->ETRClockDivision = FL_GPTIM_ETR_PSC_DIV1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置TIM的比较输出通道.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_GPTIM_CHANNEL_0
|
||||
* @arg @ref FL_GPTIM_CHANNEL_1
|
||||
* @arg @ref FL_GPTIM_CHANNEL_2
|
||||
* @arg @ref FL_GPTIM_CHANNEL_3
|
||||
* @param oc_init 指向一个 @ref FL_GPTIM_OC_InitTypeDef 结构体
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_OC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_GPTIM_INSTANCE(TIMx));
|
||||
assert_param(IS_FL_GPTIM_OC_MODE(oc_init->OCMode));
|
||||
assert_param(IS_FL_GPTIM_OC_PRELOAD(oc_init->OCPreload));
|
||||
assert_param(IS_FL_GPTIM_OC_POLARITY(oc_init->OCPolarity));
|
||||
assert_param(IS_FL_GPTIM_OC_FASTMODE(oc_init->OCFastMode));
|
||||
assert_param(IS_FL_GPTIM_OC_ETR_CLEARN(oc_init->OCETRFStatus));
|
||||
/* 通道关闭 */
|
||||
FL_GPTIM_OC_DisableChannel(TIMx, channel);
|
||||
/* 通道极性 */
|
||||
FL_GPTIM_OC_SetChannelPolarity(TIMx, oc_init->OCPolarity, channel);
|
||||
/* 捕获映射到输出通道 */
|
||||
FL_GPTIM_CC_SetChannelMode(TIMx, FL_GPTIM_CHANNEL_MODE_OUTPUT, channel);
|
||||
/* 输出比较模式寄存器配置 */
|
||||
OCConfig(TIMx, channel, oc_init);
|
||||
/* 通道使能 */
|
||||
FL_GPTIM_OC_EnableChannel(TIMx, channel);
|
||||
/* 手动触发更新事件，将配置值写入 */
|
||||
FL_GPTIM_GenerateUpdateEvent(TIMx);
|
||||
FL_GPTIM_ClearFlag_Update(TIMx);
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 配置
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_GPTIM_CHANNEL_0
|
||||
* @arg @ref FL_GPTIM_CHANNEL_1
|
||||
* @arg @ref FL_GPTIM_CHANNEL_2
|
||||
* @arg @ref FL_GPTIM_CHANNEL_3
|
||||
* @param oc_init 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_OC_InitTypeDef 结构体包含配置参数.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
static FL_ErrorStatus OCConfig(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 配置比较输出通道模式 */
|
||||
FL_GPTIM_OC_SetMode(TIMx, oc_init->OCMode, channel);
|
||||
/* 配置ETRF清零使能 */
|
||||
if(oc_init->OCETRFStatus == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_OC_EnableClear(TIMx, channel);
|
||||
}
|
||||
/* 比较输出通道快速模式 */
|
||||
if(oc_init->OCFastMode == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_OC_EnableFastMode(TIMx, channel);
|
||||
}
|
||||
/* 比较输出通道缓冲模式 */
|
||||
if(oc_init->OCPreload == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_OC_EnablePreload(TIMx, channel);
|
||||
}
|
||||
/* 设置比较值 */
|
||||
switch(channel)
|
||||
{
|
||||
case FL_GPTIM_CHANNEL_1:
|
||||
FL_GPTIM_WriteCompareCH1(TIMx, oc_init->compareValue);
|
||||
break;
|
||||
case FL_GPTIM_CHANNEL_2:
|
||||
FL_GPTIM_WriteCompareCH2(TIMx, oc_init->compareValue);
|
||||
break;
|
||||
case FL_GPTIM_CHANNEL_3:
|
||||
FL_GPTIM_WriteCompareCH3(TIMx, oc_init->compareValue);
|
||||
break;
|
||||
case FL_GPTIM_CHANNEL_4:
|
||||
FL_GPTIM_WriteCompareCH4(TIMx, oc_init->compareValue);
|
||||
break;
|
||||
default :
|
||||
result = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 FL_GPTIM_OC_InitTypeDef 为默认配置
|
||||
* @param oc_init 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_OC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPTIM_OC_StructInit(FL_GPTIM_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
oc_init->OCMode = FL_GPTIM_OC_MODE_FROZEN;
|
||||
oc_init->OCETRFStatus = FL_DISABLE;
|
||||
oc_init->OCFastMode = FL_DISABLE;
|
||||
oc_init->compareValue = 0x00000000U;
|
||||
oc_init->OCPolarity = FL_GPTIM_OC_POLARITY_NORMAL;
|
||||
oc_init->OCPreload = FL_DISABLE;
|
||||
}
|
||||
/**
|
||||
* @brief 配置TIM的输入捕获通道.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref FL_GPTIM_CHANNEL_0
|
||||
* @arg @ref FL_GPTIM_CHANNEL_1
|
||||
* @arg @ref FL_GPTIM_CHANNEL_2
|
||||
* @arg @ref FL_GPTIM_CHANNEL_3
|
||||
* @param ic_init 指向一个 @ref FL_GPTIM_IC_InitTypeDef 结构体
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_GPTIM_IC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_GPTIM_CHANNEL(channel));
|
||||
assert_param(IS_FL_GPTIM_IC_CAPTURE_STATE(ic_init->captureState));
|
||||
assert_param(IS_FL_GPTIM_IC_POLARITY(ic_init->ICPolarity));
|
||||
assert_param(IS_FL_GPTIM_CHANNEL_MODE(ic_init->ICActiveInput));
|
||||
assert_param(IS_FL_GPTIM_IC_PSC(ic_init->ICPrescaler));
|
||||
assert_param(IS_FL_GPTIM_IC_FILTER(ic_init->ICFilter));
|
||||
/* 时钟总线使能配置 */
|
||||
if(TIMx == GPTIM0)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM0);
|
||||
}
|
||||
else
|
||||
if(TIMx == GPTIM1)
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM1);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_CMU_EnableGroup4BusClock(FL_CMU_GROUP4_BUSCLK_GPTIM2);
|
||||
}
|
||||
/* 通道关闭 */
|
||||
FL_GPTIM_IC_DisableChannel(TIMx, channel);
|
||||
/*捕获极性 */
|
||||
FL_GPTIM_IC_SetChannelPolarity(TIMx, ic_init->ICPolarity, channel);
|
||||
/* 捕获映射通道 */
|
||||
FL_GPTIM_CC_SetChannelMode(TIMx, ic_init->ICActiveInput, channel);
|
||||
/* 捕获预分频 */
|
||||
FL_GPTIM_IC_SetPrescaler(TIMx, ic_init->ICPrescaler, channel);
|
||||
/* 捕获滤波器 */
|
||||
FL_GPTIM_IC_SetFilter(TIMx, ic_init->ICFilter, channel);
|
||||
if(ic_init->captureState == FL_ENABLE)
|
||||
{
|
||||
FL_GPTIM_IC_EnableChannel(TIMx, channel);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 FL_GPTIM_IC_InitTypeDef 为默认配置
|
||||
* @param ic_init 指向需要将值设置为默认配置的结构体 @ref FL_GPTIM_IC_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_GPTIM_IC_StructInit(FL_GPTIM_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
ic_init->ICPolarity = FL_GPTIM_IC_POLARITY_NORMAL;
|
||||
ic_init->ICActiveInput = FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL;
|
||||
ic_init->ICPrescaler = FL_GPTIM_IC_PSC_DIV1;
|
||||
ic_init->ICFilter = FL_GPTIM_IC_FILTER_DIV1;
|
||||
ic_init->captureState = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_GPTIM_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
249
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_i2c.c
Normal file
249
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_i2c.c
Normal file
@ -0,0 +1,249 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_i2c.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of I2C FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_I2C_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup I2C_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FL_I2C_INSTANCE(INSTANCE) ((INSTANCE) == I2C)
|
||||
|
||||
#define IS_FL_I2C_BAUDRATE(__VALUE__) (((__VALUE__) > 0 )&&((__VALUE__) <= 1000000))
|
||||
|
||||
#define IS_FL_I2C_CLOCKSRC(__VALUE__) (((__VALUE__) == FL_CMU_I2C_CLK_SOURCE_APBCLK )||\
|
||||
((__VALUE__) == FL_CMU_I2C_CLK_SOURCE_RCHF)||\
|
||||
((__VALUE__) == FL_CMU_I2C_CLK_SOURCE_SYSCLK)||\
|
||||
((__VALUE__) == FL_CMU_I2C_CLK_SOURCE_RCLF))
|
||||
|
||||
#define IS_FL_I2C_MSATER_TIMEOUT(__VALUE__) (((__VALUE__) == FL_IWDT_PERIOD_125MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_16000MS))
|
||||
|
||||
|
||||
#define IS_FL_I2C_SLAVE_ACK(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
|
||||
|
||||
#define IS_FL_I2C_ANGLOGFILTER(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_I2C_ADDRSIZE10BIT(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
#define IS_FL_I2C_SLAVE_SCLSEN(__VALUE__) (((__VALUE__) == FL_ENABLE)||\
|
||||
((__VALUE__) == FL_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位I2C外设.
|
||||
* @param I2Cx 外设入口地址
|
||||
* @retval 错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_I2C_DeInit(I2C_Type *I2Cx)
|
||||
{
|
||||
assert_param(IS_FL_I2C_INSTANCE(I2Cx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位I2C外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_I2C);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_I2C);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_I2C);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_I2C);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置I2C主机模式.
|
||||
* @param I2Cx 外设入口地址
|
||||
* @param I2C_InitStruct 指向 @ref FL_I2C_MasterMode_InitTypeDef 结构体的指针
|
||||
* @retval 错误状态，可能值：
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_I2C_MasterMode_Init(I2C_Type *I2Cx, FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
uint32_t I2C_Clk_Freq = 0, BRG = 0;
|
||||
assert_param(IS_FL_I2C_INSTANCE(I2Cx));
|
||||
assert_param(IS_FL_I2C_CLOCKSRC(I2C_InitStruct->clockSource));
|
||||
assert_param(IS_FL_I2C_BAUDRATE(I2C_InitStruct->baudRate));
|
||||
/* 外设总线时钟和工作时钟开启 */
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_I2C);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_I2C);
|
||||
/* 选择I2C工作时钟源 */
|
||||
FL_CMU_SetI2CClockSource(I2C_InitStruct->clockSource);
|
||||
/* 获取时钟源速度 */
|
||||
switch(I2C_InitStruct->clockSource)
|
||||
{
|
||||
case FL_CMU_I2C_CLK_SOURCE_APBCLK:
|
||||
I2C_Clk_Freq = FL_CMU_GetAPBClockFreq();
|
||||
break;
|
||||
case FL_CMU_I2C_CLK_SOURCE_RCHF:
|
||||
I2C_Clk_Freq = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
case FL_CMU_I2C_CLK_SOURCE_SYSCLK:
|
||||
I2C_Clk_Freq = FL_CMU_GetSystemClockFreq();
|
||||
break;
|
||||
case FL_CMU_I2C_CLK_SOURCE_RCLF:
|
||||
I2C_Clk_Freq = FL_CMU_GetRCLFClockFreq();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* 根据不同的时钟源速度计算出配置速率需要的寄存器值并配置相关寄存器 */
|
||||
BRG = (uint32_t)(I2C_Clk_Freq / (2 * I2C_InitStruct->baudRate)) - 1;
|
||||
FL_I2C_Master_WriteSCLHighWidth(I2Cx, BRG);
|
||||
FL_I2C_Master_WriteSCLLowWidth(I2Cx, BRG);
|
||||
FL_I2C_Master_WriteSDAHoldTime(I2Cx, (uint32_t)(BRG / 2.0 + 0.5));
|
||||
/* 使能外设 */
|
||||
FL_I2C_Master_Enable(I2C);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief 将 @ref FL_I2C_MasterMode_InitTypeDef 结构体初始化为默认配置
|
||||
* @param I2C_InitStruct 指向 @ref FL_I2C_MasterMode_InitTypeDef 结构体的指针
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_I2C_MasterMode_StructInit(FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
I2C_InitStruct->clockSource = FL_CMU_I2C_CLK_SOURCE_RCHF;
|
||||
I2C_InitStruct->baudRate = 40000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置I2C从机模式.
|
||||
* @param I2Cx 外设入口地址
|
||||
* @param I2C_InitStruct 指向 @ref FL_I2C_SlaveMode_InitTypeDef 结构体的指针.
|
||||
* @note 作为从机时的从机地址应参考手册推荐具体设置
|
||||
* @retval 错误状态，可能值：
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_I2C_SlaveMode_Init(I2C_Type *I2Cx, FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
assert_param(IS_FL_I2C_INSTANCE(I2Cx));
|
||||
assert_param(IS_FL_I2C_SLAVE_ACK(I2C_InitStruct->ACK));
|
||||
assert_param(IS_FL_I2C_ADDRSIZE10BIT(I2C_InitStruct->ownAddrSize10bit));
|
||||
assert_param(IS_FL_I2C_SLAVE_SCLSEN(I2C_InitStruct->SCLSEN));
|
||||
/* 外设总线时钟开启 注：不需要工作时钟*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_I2C);
|
||||
/* 使能SDA输出延迟 注：推荐开启*/
|
||||
FL_I2C_Slave_EnableSDAStretching(I2Cx);
|
||||
/* 使能SCL模拟滤波使能 注：推荐开启*/
|
||||
FL_I2C_Slave_EnableSCLAnalogFilter(I2Cx);
|
||||
/* 从机ACK */
|
||||
if(I2C_InitStruct->ACK == FL_ENABLE)
|
||||
{
|
||||
FL_I2C_Slave_EnableACK(I2Cx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_I2C_Slave_DisableACK(I2Cx);
|
||||
}
|
||||
/* 从机地址宽度 和地址配置 */
|
||||
if(I2C_InitStruct->ownAddrSize10bit == FL_ENABLE)
|
||||
{
|
||||
FL_I2C_Slave_Enable10BitAddress(I2Cx);
|
||||
FL_I2C_Slave_WriteSlaveAddress(I2Cx, I2C_InitStruct->ownAddr);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_I2C_Slave_Disable10BitAddress(I2Cx);
|
||||
FL_I2C_Slave_WriteSlaveAddress(I2Cx, I2C_InitStruct->ownAddr & 0x7F);
|
||||
}
|
||||
/* 从机时钟延展使能 */
|
||||
if(I2C_InitStruct->SCLSEN == FL_ENABLE)
|
||||
{
|
||||
FL_I2C_Slave_EnableSCLStretching(I2Cx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_I2C_Slave_DisableSCLStretching(I2Cx);
|
||||
}
|
||||
/* 外设开启 */
|
||||
FL_I2C_Slave_Enable(I2Cx);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 将 @ref FL_I2C_SlaveMode_InitTypeDef 结构体初始化为默认配置
|
||||
* @param I2C_InitStruct 指向 @ref FL_I2C_SlaveMode_InitTypeDef 结构体的指针
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_I2C_SlaveMode_StructInit(FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
I2C_InitStruct->ACK = FL_ENABLE;
|
||||
I2C_InitStruct->ownAddr = 0x55;
|
||||
I2C_InitStruct->ownAddrSize10bit = FL_DISABLE;
|
||||
I2C_InitStruct->SCLSEN = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_I2C_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
|
||||
|
||||
|
||||
133
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_iwdt.c
Normal file
133
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_iwdt.c
Normal file
@ -0,0 +1,133 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_iwdt.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of IWDT FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_IWDT_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup IWDT_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDT_INSTANCE(INTANCE) ((INTANCE) == IWDT)
|
||||
|
||||
#define IS_FL_IWDT_WINDOWSVEL(__VALUE__) ((__VALUE__) < 0xFFF)
|
||||
|
||||
#define IS_FL_IWDT_OVERFLOWPERIOD(__VALUE__) (((__VALUE__) == FL_IWDT_PERIOD_125MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_250MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_500MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_1000MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_2000MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_4000MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_8000MS)||\
|
||||
((__VALUE__) == FL_IWDT_PERIOD_16000MS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IWDT_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位IWDT外设
|
||||
*
|
||||
* @note 此函数只能用于配制前复位外设，因为IWDT开启后不可以关闭
|
||||
*
|
||||
* @param IWDTx 外设入口地址
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_IWDT_DeInit(IWDT_Type *IWDTx)
|
||||
{
|
||||
assert_param(IS_IWDT_INSTANCE(IWDTx));
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 IWDT_InitStruct 初始化对应外设的寄存器值.
|
||||
*
|
||||
* @note IWTD使能后将无法关闭，直到下一次芯片复位
|
||||
*
|
||||
* @param IWDTx 外设入口地址
|
||||
* @param IWDT_InitStruct 是 @ref FL_IWDT_InitTypeDef结构体，它包含指定IWDT外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_IWDT_Init(IWDT_Type *IWDTx, FL_IWDT_InitTypeDef *IWDT_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_IWDT_INSTANCE(IWDTx));
|
||||
assert_param(IS_FL_IWDT_WINDOWSVEL(IWDT_InitStruct->iwdtWindows));
|
||||
assert_param(IS_FL_IWDT_OVERFLOWPERIOD(IWDT_InitStruct->overflowPeriod));
|
||||
/* 开启总线时钟 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_IWDT);
|
||||
/* 配置独立看门狗溢出周期 */
|
||||
FL_IWDT_SetPeriod(IWDTx, IWDT_InitStruct->overflowPeriod);
|
||||
/* 配置独立看门狗清狗窗口*/
|
||||
FL_IWDT_WriteWindow(IWDTx, IWDT_InitStruct->iwdtWindows);
|
||||
/* 启动看门狗 */
|
||||
FL_IWDT_ReloadCounter(IWDTx);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 IWDT_InitStruct 为默认配置
|
||||
*
|
||||
* @param IWDT_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_IWDT_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_IWDT_StructInit(FL_IWDT_InitTypeDef *IWDT_InitStruct)
|
||||
{
|
||||
/* 默认不使用窗口 */
|
||||
IWDT_InitStruct->iwdtWindows = 0;
|
||||
/*最长溢出时间*/
|
||||
IWDT_InitStruct->overflowPeriod = FL_IWDT_PERIOD_500MS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_IWDT_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
341
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lcd.c
Normal file
341
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lcd.c
Normal file
@ -0,0 +1,341 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_lcd.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of LCD FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_LCD_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup LCD_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FL_LCD_INSTANCE(INTENCE) ((INTENCE) == LCD)
|
||||
|
||||
#define IS_FL_LCD_BIASCURRENT(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_CURRENT_VERYHIGH))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_CURRENT_HIGH))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_CURRENT_MEDIUM))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_CURRENT_LOW)))
|
||||
|
||||
#define IS_FL_LCD_ENMODE(__VALUE__) ((__VALUE__) == (FL_LCD_DRIVER_MODE_INNER_RESISTER)||\
|
||||
((__VALUE__) == (FL_LCD_DRIVER_MODE_OUTER_CAPACITY)))
|
||||
|
||||
#define IS_FL_LCD_BIASVOLTAGE(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL0))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL1))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL2))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL3))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL4))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL5))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL6))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL7))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL8))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL9))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL10))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL11))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL12))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL13))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL14))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL15)))
|
||||
|
||||
#define IS_FL_LCD_BIASMD(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_MODE_4BIAS))||\
|
||||
((__VALUE__) == (FL_LCD_BIAS_MODE_3BIAS)))
|
||||
|
||||
#define IS_FL_LCD_BWFT(__VALUE__) (((__VALUE__) == (FL_LCD_WAVEFORM_TYPEA))||\
|
||||
((__VALUE__) == (FL_LCD_WAVEFORM_TYPEB)))
|
||||
|
||||
#define IS_FL_LCD_LMUX(__VALUE__) (((__VALUE__) == (FL_LCD_COM_NUM_4COM))||\
|
||||
((__VALUE__) == (FL_LCD_COM_NUM_6COM))||\
|
||||
((__VALUE__) == (FL_LCD_COM_NUM_8COM)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LCD_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 获取LCD工作频率寄存器.
|
||||
* @param wavetype 波形
|
||||
* @param freq 工作频率
|
||||
* @retval 工作频率寄存器值
|
||||
*/
|
||||
static uint32_t FL_LCD_DisplayFreq(uint32_t wavetype,uint32_t freq)
|
||||
{
|
||||
uint32_t displayFreq = 32u;
|
||||
if((freq > 0) && (freq <= 100))
|
||||
{
|
||||
if(wavetype == FL_LCD_WAVEFORM_TYPEA)
|
||||
{
|
||||
switch(FL_LCD_GetCOMNumber(LCD))
|
||||
{
|
||||
case FL_LCD_COM_NUM_4COM:
|
||||
displayFreq = (32768 / (4 * freq * 2) );
|
||||
break;
|
||||
case FL_LCD_COM_NUM_6COM:
|
||||
displayFreq = (32768 / (6 * freq * 2) );
|
||||
break;
|
||||
case FL_LCD_COM_NUM_8COM:
|
||||
displayFreq = (32768 / (8 * freq * 2) );
|
||||
break;
|
||||
default:
|
||||
displayFreq = (32768/ (4 * freq * 2) );
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch(FL_LCD_GetCOMNumber(LCD))
|
||||
{
|
||||
case FL_LCD_COM_NUM_4COM:
|
||||
displayFreq = (32768 / (4 * freq * 4) );
|
||||
break;
|
||||
case FL_LCD_COM_NUM_6COM:
|
||||
displayFreq = (32768 / (6 * freq * 4) );
|
||||
break;
|
||||
case FL_LCD_COM_NUM_8COM:
|
||||
displayFreq = (32768 / (8 * freq * 4) );
|
||||
break;
|
||||
default:
|
||||
displayFreq = (32768/ (4 * freq * 4) );
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
displayFreq = displayFreq & 0x000000ffu;
|
||||
return displayFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取LCD闪烁时间寄存器值
|
||||
* @param timevalue 闪烁时间
|
||||
* @retval 闪烁时间寄存器
|
||||
*/
|
||||
static uint32_t FL_LCD_FlickTime(uint32_t timevalue)
|
||||
{
|
||||
uint32_t stepTime;
|
||||
uint32_t TimeResult = 0u;
|
||||
switch(FL_LCD_GetCOMNumber(LCD))
|
||||
{
|
||||
case FL_LCD_COM_NUM_4COM:
|
||||
stepTime = (4 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768;
|
||||
break;
|
||||
case FL_LCD_COM_NUM_6COM:
|
||||
stepTime = (6 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768;
|
||||
break;
|
||||
case FL_LCD_COM_NUM_8COM:
|
||||
stepTime = (8 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768;
|
||||
break;
|
||||
default:
|
||||
stepTime = (4 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768;
|
||||
break;
|
||||
}
|
||||
TimeResult = timevalue / stepTime;
|
||||
return TimeResult;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 复位对应LCD寄存器.
|
||||
|
||||
* @param LCDx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_LCD_DeInit(LCD_Type *LCDx)
|
||||
{
|
||||
assert_param(IS_FL_LCD_INSTANCE(LCDx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位LCD外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LCD);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LCD);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_LCD);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 LCD_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param LCDx LCDx
|
||||
* @param LCD_InitStruct 指向一个 @ref FL_LCD_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LCD配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LCD_Init(LCD_Type *LCDx, FL_LCD_InitTypeDef *initStruct)
|
||||
{
|
||||
assert_param(IS_FL_LCD_INSTANCE(LCDx));
|
||||
assert_param(IS_FL_LCD_BIASCURRENT(initStruct->biasCurrent));
|
||||
assert_param(IS_FL_LCD_ENMODE(initStruct->mode));
|
||||
assert_param(IS_FL_LCD_BIASVOLTAGE(initStruct->biasVoltage));
|
||||
assert_param(IS_FL_LCD_BIASMD(initStruct->biasMode));
|
||||
assert_param(IS_FL_LCD_BWFT(initStruct->waveform));
|
||||
assert_param(IS_FL_LCD_LMUX(initStruct->COMxNum));
|
||||
/* 外设总线始时钟 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_LCD);
|
||||
/* 电流源电流控制 */
|
||||
FL_LCD_SetBiasCurrent(LCD, initStruct->biasCurrent);
|
||||
/* LCD驱动模式 */
|
||||
FL_LCD_SetDriverMode(LCD, initStruct->mode);
|
||||
/* 偏执电压设置 */
|
||||
FL_LCD_SetBiasVoltage(LCD, initStruct->biasVoltage);
|
||||
/* 偏执模式选择 */
|
||||
FL_LCD_SetBiasMode(LCD, initStruct->biasMode);
|
||||
/* 驱动波形设置 */
|
||||
FL_LCD_SetWaveform(LCD, initStruct->waveform);
|
||||
/* COMx口选择 */
|
||||
FL_LCD_SetCOMNumber(LCD, initStruct->COMxNum);
|
||||
/* 设置工作频率 */
|
||||
FL_LCD_WriteDisplayFrequency(LCD, FL_LCD_DisplayFreq(initStruct->waveform,initStruct->displayFreq));
|
||||
/* 设置闪烁频率 */
|
||||
FL_LCD_WriteDisplayOnTime(LCD, FL_LCD_FlickTime(initStruct->flickOnTime));
|
||||
FL_LCD_WriteDisplayOffTime(LCD, FL_LCD_FlickTime(initStruct->flickOffTime));
|
||||
/* 使能外设 */
|
||||
FL_LCD_Enable(LCD);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LCD_InitStruct 为默认配置
|
||||
* @param LCD_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_LCD_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LCD_StructInit(FL_LCD_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->biasCurrent = FL_LCD_BIAS_CURRENT_HIGH;
|
||||
initStruct->mode = FL_LCD_DRIVER_MODE_INNER_RESISTER;
|
||||
initStruct->biasVoltage = FL_LCD_BIAS_VOLTAGE_LEVEL10;
|
||||
initStruct->biasMode = FL_LCD_BIAS_MODE_3BIAS;
|
||||
initStruct->waveform = FL_LCD_WAVEFORM_TYPEA;
|
||||
initStruct->COMxNum = FL_LCD_COM_NUM_6COM;
|
||||
initStruct->displayFreq = 42;
|
||||
initStruct->flickOnTime = 0;
|
||||
initStruct->flickOffTime = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LCD 4COM显示字端
|
||||
* @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。
|
||||
* @param com 待显示字段所在COM。范围0-4。
|
||||
* @param seg 待显示字段所在SEG。范围0-43。
|
||||
* @param state 待显示字段状态。0，熄灭；否则，点亮。
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LCD_4COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state)
|
||||
{
|
||||
uint8_t temp;
|
||||
if(state != 0)
|
||||
{
|
||||
state = 1;
|
||||
}
|
||||
if(seg > 31)
|
||||
{
|
||||
temp = (seg - 32) + com * 12;
|
||||
com = 4 + temp / 32;
|
||||
seg = temp % 32;
|
||||
}
|
||||
MODIFY_REG(display[com], (uint32_t)(0x1U << seg), (uint32_t)(state << seg));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LCD 6COM显示字端
|
||||
* @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。
|
||||
* @param com 待显示字段所在COM。范围0-6。
|
||||
* @param seg 待显示字段所在SEG。范围0-41。
|
||||
* @param state 待显示字段状态。0，熄灭；否则，点亮。
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LCD_6COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state)
|
||||
{
|
||||
uint8_t temp;
|
||||
if(state != 0)
|
||||
{
|
||||
state = 1;
|
||||
}
|
||||
if(seg > 31)
|
||||
{
|
||||
temp = (seg - 32) + com * 10;
|
||||
com = 6 + temp / 32;
|
||||
seg = temp % 32;
|
||||
}
|
||||
MODIFY_REG(display[com], (uint32_t)(0x1 << seg), (uint32_t)(state << seg));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LCD 8COM显示字端
|
||||
* @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。
|
||||
* @param com 待显示字段所在COM。范围0-8。
|
||||
* @param seg 待显示字段所在SEG。范围0-39。
|
||||
* @param state 待显示字段状态。0，熄灭；否则，点亮。
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LCD_8COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state)
|
||||
{
|
||||
uint8_t temp;
|
||||
if(state != 0)
|
||||
{
|
||||
state = 1;
|
||||
}
|
||||
if(seg > 31)
|
||||
{
|
||||
temp = (seg - 32) + com * 8;
|
||||
com = 8 + temp / 32;
|
||||
seg = temp % 32;
|
||||
}
|
||||
MODIFY_REG(display[com], (uint32_t)(0x1 << seg), (uint32_t)(state << seg));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_LCD_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
374
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lptim16.c
Normal file
374
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lptim16.c
Normal file
@ -0,0 +1,374 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_lptim16.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of LPTIM16 FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM16
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_LPTIM16_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup LPTIM16_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM16_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM16))
|
||||
|
||||
#define IS_FL_LPTIM16_CHANNEL(__VALUE__) (((__VALUE__) == FL_LPTIM16_CHANNEL_1)||\
|
||||
((__VALUE__) == FL_LPTIM16_CHANNEL_2))
|
||||
|
||||
#define IS_FL_LPTIM16_CMU_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_CMU_LPTIM16_CLK_SOURCE_RCLF)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM16_CLK_SOURCE_RCLP)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM16_CLK_SOURCE_LSCLK)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM16_CLK_SOURCE_APBCLK))
|
||||
|
||||
#define IS_FL_LPTIM16_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM16_CLK_SOURCE_INTERNAL)||\
|
||||
((__VALUE__) == FL_LPTIM16_CLK_SOURCE_EXTERNAL))
|
||||
|
||||
#define IS_FL_LPTIM16_PSC(__VALUE__) (((__VALUE__) == FL_LPTIM16_PSC_DIV1)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV2)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV4)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV8)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV16)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV32)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV64)||\
|
||||
((__VALUE__) == FL_LPTIM16_PSC_DIV128))
|
||||
|
||||
#define IS_FL_LPTIM16_OPERATION_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM16_OPERATION_MODE_NORMAL)||\
|
||||
((__VALUE__) == FL_LPTIM16_OPERATION_MODE_EXTERNAL_TRIGGER_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM16_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM16_OPERATION_MODE_TIMEOUT))
|
||||
|
||||
#define IS_FL_LPTIM16_ENCODER_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM16_ENCODER_MODE_DISABLE)||\
|
||||
((__VALUE__) == FL_LPTIM16_ENCODER_MODE_TI1FP1_TI2FP2_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM16_ENCODER_MODE_TI2FP2_TI1FP1_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM16_ENCODER_MODE_TI2FP2_CNT_TI1FP1_CNT))
|
||||
|
||||
#define IS_FL_LPTIM16_ETR_TRIGGER_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM16_ETR_TRIGGER_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM16_ETR_TRIGGER_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_LPTIM16_ETR_TRIGGER_EDGE_BOTH))
|
||||
|
||||
#define IS_FL_LPTIM16_ETR_COUNT_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM16_ETR_COUNT_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM16_ETR_COUNT_EDGE_FALLING))
|
||||
|
||||
#define IS_FL_LPTIM16_ONE_PULSE_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM16_ONE_PULSE_MODE_CONTINUOUS)||\
|
||||
((__VALUE__) == FL_LPTIM16_ONE_PULSE_MODE_SINGLE))
|
||||
|
||||
#define IS_FL_LPTIM16_IC_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM16_IC_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC_EDGE_BOTH))
|
||||
|
||||
#define IS_FL_LPTIM16_IC_POLARITY(__VALUE__) (((__VALUE__) == FL_LPTIM16_IC_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_LPTIM16_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_LPTIM16_OC_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_LPTIM16_OC_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_LPTIM16_IC1_CAPTURE_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM16_IC1_CAPTURE_SOURCE_GROUP0)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC1_CAPTURE_SOURCE_GROUP1)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC1_CAPTURE_SOURCE_GROUP2)||\
|
||||
((__VALUE__) == FL_LPTIM16_IC1_CAPTURE_SOURCE_GROUP3))
|
||||
|
||||
#define IS_FL_LPTIM16_TRGO_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM16_TRGO_ENABLE)||\
|
||||
((__VALUE__) == FL_LPTIM16_TRGO_UPDATE)||\
|
||||
((__VALUE__) == FL_LPTIM16_TRGO_OC1_CMP_PULSE)||\
|
||||
((__VALUE__) == FL_LPTIM16_TRGO_IC1_EVENT)||\
|
||||
((__VALUE__) == FL_LPTIM16_TRGO_IC2_EVENT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LPTIM16_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位LPTIM16 外设
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM16_DeInit(LPTIM16_Type *LPTIM16x)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM16_INSTANCE(LPTIM16x));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPTIM16);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPTIM16);
|
||||
/* 关闭外设总线时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_LPTIM16);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPTIM16);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置LPTIM16寄存器使之工作在定时器功能模式下
|
||||
*
|
||||
* @note 需要使用ETR作为计数源时，建议根据需求配置为异步脉冲计数模式
|
||||
* @ref FL_LPTIM16_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT 或外部触发计数模式
|
||||
* @ref FL_LPTIM16_OPERATION_MODE_EXTERNAL_TRIGGER_CNT
|
||||
*
|
||||
* @param LPTIM16x 外设入口地址
|
||||
* @param init 为 @ref FL_LPTIM16_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM16配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM16_Init(LPTIM16_Type *LPTIM16x, FL_LPTIM16_InitTypeDef *init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM16_INSTANCE(LPTIM16x));
|
||||
assert_param(IS_FL_LPTIM16_CMU_CLK_SOURCE(init->clockSource));
|
||||
assert_param(IS_FL_LPTIM16_CLK_SOURCE(init->prescalerClockSource));
|
||||
assert_param(IS_FL_LPTIM16_PSC(init->prescaler));
|
||||
assert_param(IS_FL_LPTIM16_OPERATION_MODE(init->mode));
|
||||
assert_param(IS_FL_LPTIM16_ENCODER_MODE(init->encoderMode));
|
||||
assert_param(IS_FL_LPTIM16_ONE_PULSE_MODE(init->onePulseMode));
|
||||
assert_param(IS_FL_LPTIM16_ETR_TRIGGER_EDGE(init->triggerEdge));
|
||||
assert_param(IS_FL_LPTIM16_ETR_COUNT_EDGE(init->countEdge));
|
||||
/* 时钟配置 */
|
||||
if(LPTIM16x == LPTIM16)
|
||||
{
|
||||
/* 使能总线时钟 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_LPTIM16);
|
||||
/* 除了异步计数模式，其他模式都需要使能工作时钟 */
|
||||
if(init->prescalerClockSource == FL_LPTIM16_CLK_SOURCE_EXTERNAL)
|
||||
{
|
||||
/* 使能工作时钟 */
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPTIM16);
|
||||
/* 设置工作时钟时钟源 */
|
||||
FL_CMU_SetLPTIM16ClockSource(init->clockSource);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return FL_FAIL;
|
||||
}
|
||||
/* 配置分频器的时钟源 */
|
||||
FL_LPTIM16_SetClockSource(LPTIM16x, init->prescalerClockSource);
|
||||
/* 配置时钟分频 */
|
||||
FL_LPTIM16_SetPrescaler(LPTIM16x, init->prescaler);
|
||||
/* 配置重装载值 */
|
||||
FL_LPTIM16_WriteAutoReload(LPTIM16x, init->autoReload);
|
||||
/* 配置定时器工作模式 */
|
||||
FL_LPTIM16_SetOperationMode(LPTIM16x, init->mode);
|
||||
/* 配置编码器模式 */
|
||||
if(init->mode == FL_LPTIM16_OPERATION_MODE_NORMAL)
|
||||
{
|
||||
FL_LPTIM16_SetEncoderMode(LPTIM16x, init->encoderMode);
|
||||
}
|
||||
/* 单次计数模式 */
|
||||
FL_LPTIM16_SetOnePulseMode(LPTIM16x, init->onePulseMode);
|
||||
/* 配置定时器不同模式下的特殊寄存器 */
|
||||
switch(init->mode)
|
||||
{
|
||||
case FL_LPTIM16_OPERATION_MODE_NORMAL:
|
||||
{
|
||||
/* ETR作为时钟时和异步脉冲计数模式信号路径一样，需要使能模拟滤波，并配置边沿 */
|
||||
if(init->prescalerClockSource == FL_LPTIM16_CLK_SOURCE_EXTERNAL)
|
||||
{
|
||||
/* 配置异步计数边沿 */
|
||||
FL_LPTIM16_SetETRCountEdge(LPTIM16x, init->countEdge);
|
||||
/* 开启外部输入滤波 */
|
||||
FL_LPTIM16_EnableETRFilter(LPTIM16x);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM16_OPERATION_MODE_EXTERNAL_TRIGGER_CNT:
|
||||
{
|
||||
/* 配置外部输入有效边沿 */
|
||||
FL_LPTIM16_SetETRTriggerEdge(LPTIM16x, init->triggerEdge);
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM16_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT:
|
||||
{
|
||||
/* 配置异步计数边沿 */
|
||||
FL_LPTIM16_SetETRCountEdge(LPTIM16x, init->countEdge);
|
||||
/* 开启外部输入滤波 */
|
||||
FL_LPTIM16_EnableETRFilter(LPTIM16x);
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM16_OPERATION_MODE_TIMEOUT:
|
||||
{
|
||||
/* 配置外部输入有效边沿 */
|
||||
FL_LPTIM16_SetETRTriggerEdge(LPTIM16x, init->triggerEdge);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return FL_FAIL;
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM16_InitStruct 为默认配置
|
||||
* @param init 为 @ref FL_LPTIM16_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM16_StructInit(FL_LPTIM16_InitTypeDef *init)
|
||||
{
|
||||
init->clockSource = FL_CMU_LPTIM16_CLK_SOURCE_APBCLK;
|
||||
init->prescalerClockSource = FL_LPTIM16_CLK_SOURCE_INTERNAL;
|
||||
init->prescaler = FL_LPTIM16_PSC_DIV1;
|
||||
init->autoReload = 0;
|
||||
init->mode = FL_LPTIM16_OPERATION_MODE_NORMAL;
|
||||
init->countEdge = FL_LPTIM16_ETR_COUNT_EDGE_RISING;
|
||||
init->triggerEdge = FL_LPTIM16_ETR_TRIGGER_EDGE_RISING;
|
||||
init->encoderMode = FL_LPTIM16_ENCODER_MODE_DISABLE;
|
||||
init->onePulseMode = FL_LPTIM16_ONE_PULSE_MODE_CONTINUOUS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置LPTIM16工作在输入捕获模式
|
||||
*
|
||||
* @param LPTIM16x 外设入口地址
|
||||
* @param ic_init 为 @ref FL_LPTIM16_IC_InitTypeDef类型的结构体
|
||||
* @param Channel LPTIM16输入通道
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM16配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM16_IC_Init(LPTIM16_Type *LPTIM16x, uint32_t Channel, FL_LPTIM16_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM16_INSTANCE(LPTIM16x));
|
||||
assert_param(IS_FL_LPTIM16_CHANNEL(Channel));
|
||||
assert_param(IS_FL_LPTIM16_IC_EDGE(ic_init->ICEdge));
|
||||
assert_param(IS_FL_LPTIM16_IC_POLARITY(ic_init->ICInputPolarity));
|
||||
assert_param(IS_FL_LPTIM16_IC1_CAPTURE_SOURCE(ic_init->channel1CaptureSource));
|
||||
/* 通道1捕获源 & 预分频 */
|
||||
if(Channel == FL_LPTIM16_CHANNEL_1)
|
||||
{
|
||||
FL_LPTIM16_IC_WriteChannel1Prescaler(LPTIM16x, ic_init->channel1Prescaler);
|
||||
FL_LPTIM16_IC_SetChannel1CaptureSource(LPTIM16x, ic_init->channel1CaptureSource);
|
||||
}
|
||||
if(ic_init->ICInputDigitalFilter == FL_DISABLE)
|
||||
{
|
||||
FL_LPTIM16_DisableDigitalFilter(LPTIM16, Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_LPTIM16_EnableDigitalFilter(LPTIM16, Channel);
|
||||
}
|
||||
/* 捕获通道极性 */
|
||||
FL_LPTIM16_IC_SetInputPolarity(LPTIM16x, ic_init->ICInputPolarity, Channel);
|
||||
/* 配置捕获边沿 */
|
||||
FL_LPTIM16_IC_SetCaptureEdge(LPTIM16x, ic_init->ICEdge, Channel);
|
||||
/* 通道输入捕获使能 */
|
||||
FL_LPTIM16_SetChannelMode(LPTIM16x, FL_LPTIM16_CHANNEL_MODE_INPUT, Channel);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM16_IC_InitStruct 为默认配置
|
||||
* @param ic_init 为 @ref FL_LPTIM16_IC_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM16_IC_StructInit(FL_LPTIM16_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
ic_init->ICInputPolarity = FL_LPTIM16_IC_POLARITY_NORMAL;
|
||||
ic_init->ICInputDigitalFilter = FL_DISABLE;
|
||||
ic_init->ICEdge = FL_LPTIM16_IC_EDGE_RISING;
|
||||
ic_init->channel1Prescaler = 1 - 1;
|
||||
ic_init->channel1CaptureSource = FL_LPTIM16_IC1_CAPTURE_SOURCE_GROUP0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置LPTIM16寄存器工作在输出比较模式
|
||||
*
|
||||
* @param LPTIM16x 外设入口地址
|
||||
* @param oc_init 为 @ref FL_LPTIM16_OC_InitTypeDef类型的结构体
|
||||
* @param Channel LPTIM16输出通道
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM16配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM16_OC_Init(LPTIM16_Type *LPTIM16x, uint32_t Channel, FL_LPTIM16_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM16_INSTANCE(LPTIM16x));
|
||||
assert_param(IS_FL_LPTIM16_CHANNEL(Channel));
|
||||
assert_param(IS_FL_LPTIM16_OC_POLARITY(oc_init->OCPolarity));
|
||||
/* 比较通道极性 */
|
||||
FL_LPTIM16_OC_SetPolarity(LPTIM16x, oc_init->OCPolarity, Channel);
|
||||
/* 设置比较值 */
|
||||
switch(Channel)
|
||||
{
|
||||
case FL_LPTIM16_CHANNEL_1:
|
||||
FL_LPTIM16_WriteCompareCH1(LPTIM16x, oc_init->compareValue);
|
||||
break;
|
||||
case FL_LPTIM16_CHANNEL_2:
|
||||
FL_LPTIM16_WriteCompareCH2(LPTIM16x, oc_init->compareValue);
|
||||
break;
|
||||
default :
|
||||
return FL_FAIL;
|
||||
}
|
||||
/* 通道输出比较使能 */
|
||||
FL_LPTIM16_SetChannelMode(LPTIM16x, FL_LPTIM16_CHANNEL_MODE_OUTPUT, Channel);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM16_OC_InitStruct 为默认配置
|
||||
* @param oc_init 为 @ref FL_LPTIM16_OC_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM16_OC_StructInit(FL_LPTIM16_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
oc_init->compareValue = 0;
|
||||
oc_init->OCPolarity = FL_LPTIM16_OC_POLARITY_NORMAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_LPTIM16_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
348
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lptim32.c
Normal file
348
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lptim32.c
Normal file
@ -0,0 +1,348 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_lptim32.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of LPTIM32 FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM32
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_LPTIM32_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup LPTIM32_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM32_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM32)
|
||||
|
||||
#define IS_FL_LPTIM32_CHANNEL(__VALUE__) (((__VALUE__) == FL_LPTIM32_CHANNEL_1)||\
|
||||
((__VALUE__) == FL_LPTIM32_CHANNEL_2)||\
|
||||
((__VALUE__) == FL_LPTIM32_CHANNEL_3)||\
|
||||
((__VALUE__) == FL_LPTIM32_CHANNEL_4))
|
||||
|
||||
#define IS_FL_LPTIM32_CMU_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_CMU_LPTIM32_CLK_SOURCE_RCLF)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM32_CLK_SOURCE_RCLP)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM32_CLK_SOURCE_LSCLK)||\
|
||||
((__VALUE__) == FL_CMU_LPTIM32_CLK_SOURCE_APBCLK))
|
||||
|
||||
#define IS_FL_LPTIM32_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM32_CLK_SOURCE_INTERNAL)||\
|
||||
((__VALUE__) == FL_LPTIM32_CLK_SOURCE_EXTERNAL))
|
||||
|
||||
#define IS_FL_LPTIM32_PSC(__VALUE__) (((__VALUE__) == FL_LPTIM32_PSC_DIV1)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV2)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV4)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV8)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV16)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV32)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV64)||\
|
||||
((__VALUE__) == FL_LPTIM32_PSC_DIV128))
|
||||
|
||||
#define IS_FL_LPTIM32_OPERATION_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM32_OPERATION_MODE_NORMAL)||\
|
||||
((__VALUE__) == FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT)||\
|
||||
((__VALUE__) == FL_LPTIM32_OPERATION_MODE_TIMEOUT))
|
||||
|
||||
#define IS_FL_LPTIM32_ETR_TRIGGER_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_BOTH))
|
||||
|
||||
#define IS_FL_LPTIM32_ETR_COUNT_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ETR_COUNT_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM32_ETR_COUNT_EDGE_FALLING))
|
||||
|
||||
#define IS_FL_LPTIM32_ONE_PULSE_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS)||\
|
||||
((__VALUE__) == FL_LPTIM32_ONE_PULSE_MODE_SINGLE))
|
||||
|
||||
#define IS_FL_LPTIM32_IC_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_IC_EDGE_RISING)||\
|
||||
((__VALUE__) == FL_LPTIM32_IC_EDGE_FALLING)||\
|
||||
((__VALUE__) == FL_LPTIM32_IC_EDGE_BOTH))
|
||||
|
||||
#define IS_FL_LPTIM32_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_LPTIM32_OC_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_LPTIM32_OC_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_LPTIM32_IC1_CAPTURE_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM32_IC1_CAPTURE_SOURCE_GROUP0)||\
|
||||
((__VALUE__) == FL_LPTIM32_IC1_CAPTURE_SOURCE_GROUP1)||\
|
||||
((__VALUE__) == FL_LPTIM32_IC1_CAPTURE_SOURCE_GROUP2)||\
|
||||
((__VALUE__) == FL_LPTIM32_IC1_CAPTURE_SOURCE_GROUP3))
|
||||
|
||||
#define IS_FL_LPTIM32_TRGO_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM32_TRGO_ENABLE)||\
|
||||
((__VALUE__) == FL_LPTIM32_TRGO_UPDATE)||\
|
||||
((__VALUE__) == FL_LPTIM32_TRGO_OC1_CMP_PULSE)||\
|
||||
((__VALUE__) == FL_LPTIM32_TRGO_IC1_EVENT)||\
|
||||
((__VALUE__) == FL_LPTIM32_TRGO_IC2_EVENT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LPTIM32_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位LPTIM32 外设
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM32_DeInit(LPTIM32_Type *LPTIM32x)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM32_INSTANCE(LPTIM32x));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPTIM32);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPTIM32);
|
||||
/* 关闭外设总线时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_LPTIM32);
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPTIM32);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置LPTIM32寄存器使之工作在定时器功能模式下
|
||||
*
|
||||
* @note 需要使用ETR作为计数源时，建议根据需求配置为异步脉冲计数模式
|
||||
* @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT 或外部触发计数模式
|
||||
* @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT
|
||||
*
|
||||
* @param LPTIM32x 外设入口地址
|
||||
* @param init 为 @ref FL_LPTIM32_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM32配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM32_Init(LPTIM32_Type *LPTIM32x, FL_LPTIM32_InitTypeDef *init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM32_INSTANCE(LPTIM32x));
|
||||
assert_param(IS_FL_LPTIM32_CMU_CLK_SOURCE(init->clockSource));
|
||||
assert_param(IS_FL_LPTIM32_CLK_SOURCE(init->prescalerClockSource));
|
||||
assert_param(IS_FL_LPTIM32_PSC(init->prescaler));
|
||||
assert_param(IS_FL_LPTIM32_OPERATION_MODE(init->mode));
|
||||
assert_param(IS_FL_LPTIM32_ONE_PULSE_MODE(init->onePulseMode));
|
||||
assert_param(IS_FL_LPTIM32_ETR_TRIGGER_EDGE(init->triggerEdge));
|
||||
assert_param(IS_FL_LPTIM32_ETR_COUNT_EDGE(init->countEdge));
|
||||
/* 时钟配置 */
|
||||
if(LPTIM32x == LPTIM32)
|
||||
{
|
||||
/* 使能总线时钟 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_LPTIM32);
|
||||
/* 除了异步计数模式，其他模式都需要使能工作时钟 */
|
||||
if(init->mode != FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT)
|
||||
{
|
||||
/* 使能工作时钟 */
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPTIM32);
|
||||
/* 设置工作时钟时钟源 */
|
||||
FL_CMU_SetLPTIM32ClockSource(init->clockSource);
|
||||
}
|
||||
}
|
||||
/* 配置分频器的时钟源 */
|
||||
FL_LPTIM32_SetClockSource(LPTIM32x, init->prescalerClockSource);
|
||||
/* 配置时钟分频 */
|
||||
FL_LPTIM32_SetPrescaler(LPTIM32x, init->prescaler);
|
||||
/* 配置定时器工作模式 */
|
||||
FL_LPTIM32_SetOperationMode(LPTIM32x, init->mode);
|
||||
/* 配置定时器不同模式下的特殊寄存器 */
|
||||
switch(init->mode)
|
||||
{
|
||||
case FL_LPTIM32_OPERATION_MODE_NORMAL:
|
||||
{
|
||||
if(init->prescalerClockSource == FL_LPTIM32_CLK_SOURCE_EXTERNAL)
|
||||
{
|
||||
/* 配置外部计数边沿 */
|
||||
FL_LPTIM32_SetETRCountEdge(LPTIM32x, init->countEdge);
|
||||
/* 开启外部输入滤波 */
|
||||
FL_LPTIM32_EnableETRFilter(LPTIM32x);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT:
|
||||
{
|
||||
/* 配置外部输入有效边沿 */
|
||||
FL_LPTIM32_SetETRTriggerEdge(LPTIM32x, init->triggerEdge);
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT:
|
||||
{
|
||||
/* 配置外部计数边沿 */
|
||||
FL_LPTIM32_SetETRCountEdge(LPTIM32x, init->countEdge);
|
||||
/* 开启外部输入滤波 */
|
||||
FL_LPTIM32_EnableETRFilter(LPTIM32x);
|
||||
}
|
||||
break;
|
||||
case FL_LPTIM32_OPERATION_MODE_TIMEOUT:
|
||||
{
|
||||
/* 配置外部输入有效边沿 */
|
||||
FL_LPTIM32_SetETRTriggerEdge(LPTIM32x, init->triggerEdge);
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* 单次计数模式 */
|
||||
FL_LPTIM32_SetOnePulseMode(LPTIM32x, init->onePulseMode);
|
||||
/* 设置重装载值 */
|
||||
FL_LPTIM32_WriteAutoReload(LPTIM32x, init->autoReload);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM32_InitStruct 为默认配置
|
||||
* @param init 为 @ref FL_LPTIM32_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM32_StructInit(FL_LPTIM32_InitTypeDef *init)
|
||||
{
|
||||
init->clockSource = FL_CMU_LPTIM32_CLK_SOURCE_APBCLK;
|
||||
init->prescalerClockSource = FL_LPTIM32_CLK_SOURCE_INTERNAL;
|
||||
init->prescaler = FL_LPTIM32_PSC_DIV1;
|
||||
init->autoReload = 0;
|
||||
init->mode = FL_LPTIM32_OPERATION_MODE_NORMAL;
|
||||
init->countEdge = FL_LPTIM32_ETR_COUNT_EDGE_RISING;
|
||||
init->triggerEdge = FL_LPTIM32_ETR_TRIGGER_EDGE_RISING;
|
||||
init->onePulseMode = FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置LPTIM32工作在输入捕获模式
|
||||
*
|
||||
* @param LPTIM32x 外设入口地址
|
||||
* @param ic_init 为 @ref FL_LPTIM32_IC_InitTypeDef类型的结构体
|
||||
* @param Channel LPTIM32输入通道
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM32配置成功
|
||||
*/
|
||||
//输入捕获配置
|
||||
FL_ErrorStatus FL_LPTIM32_IC_Init(LPTIM32_Type *LPTIM32x, uint32_t Channel, FL_LPTIM32_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM32_INSTANCE(LPTIM32x));
|
||||
assert_param(IS_FL_LPTIM32_CHANNEL(Channel));
|
||||
assert_param(IS_FL_LPTIM32_IC_EDGE(ic_init->ICEdge));
|
||||
assert_param(IS_FL_LPTIM32_IC1_CAPTURE_SOURCE(ic_init->ICSource));
|
||||
/* 通道1捕获源 */
|
||||
if(Channel == FL_LPTIM32_CHANNEL_1)
|
||||
{
|
||||
FL_LPTIM32_IC_SetChannel1CaptureSource(LPTIM32, ic_init->ICSource);
|
||||
}
|
||||
/* 捕获通道边沿 */
|
||||
FL_LPTIM32_IC_SetCaptureEdge(LPTIM32, ic_init->ICEdge, Channel);
|
||||
/* 通道输入捕获使能 */
|
||||
FL_LPTIM32_SetChannelMode(LPTIM32, FL_LPTIM32_CHANNEL_MODE_INPUT, Channel);
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM32_IC_InitStruct 为默认配置
|
||||
* @param ic_init为 @ref FL_LPTIM32_IC_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM32_IC_StructInit(FL_LPTIM32_IC_InitTypeDef *ic_init)
|
||||
{
|
||||
ic_init->ICEdge = FL_LPTIM32_IC_EDGE_RISING;
|
||||
ic_init->ICSource = FL_LPTIM32_IC1_CAPTURE_SOURCE_GROUP0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置LPTIM32寄存器工作在输出比较模式
|
||||
*
|
||||
* @param LPTIM32x 外设入口地址
|
||||
* @param oc_init 为 @ref FL_LPTIM32_OC_InitTypeDef类型的结构体
|
||||
* @param Channel LPTIM32输出通道
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPTIM32配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPTIM32_OC_Init(LPTIM32_Type *LPTIM32x, uint32_t Channel, FL_LPTIM32_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* 参数检查 */
|
||||
assert_param(IS_LPTIM32_INSTANCE(LPTIM32x));
|
||||
assert_param(IS_FL_LPTIM32_CHANNEL(Channel));
|
||||
assert_param(IS_FL_LPTIM32_OC_POLARITY(oc_init->OCPolarity));
|
||||
/* 比较通道极性 */
|
||||
FL_LPTIM32_OC_SetPolarity(LPTIM32x, oc_init->OCPolarity, Channel);
|
||||
/* 设置比较值 */
|
||||
switch(Channel)
|
||||
{
|
||||
case FL_LPTIM32_CHANNEL_1:
|
||||
FL_LPTIM32_WriteCompareCH1(LPTIM32x, oc_init->compareValue);
|
||||
break;
|
||||
case FL_LPTIM32_CHANNEL_2:
|
||||
FL_LPTIM32_WriteCompareCH2(LPTIM32x, oc_init->compareValue);
|
||||
break;
|
||||
case FL_LPTIM32_CHANNEL_3:
|
||||
FL_LPTIM32_WriteCompareCH3(LPTIM32x, oc_init->compareValue);
|
||||
break;
|
||||
case FL_LPTIM32_CHANNEL_4:
|
||||
FL_LPTIM32_WriteCompareCH4(LPTIM32x, oc_init->compareValue);
|
||||
break;
|
||||
default :
|
||||
result = FL_FAIL;
|
||||
break;
|
||||
}
|
||||
/* 通道输出比较使能 */
|
||||
FL_LPTIM32_SetChannelMode(LPTIM32x, FL_LPTIM32_CHANNEL_MODE_OUTPUT, Channel);
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 LPTIM32_OC_InitStruct 为默认配置
|
||||
* @param oc_init为 @ref FL_LPTIM32_OC_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_LPTIM32_OC_StructInit(FL_LPTIM32_OC_InitTypeDef *oc_init)
|
||||
{
|
||||
oc_init->compareValue = 0;
|
||||
oc_init->OCPolarity = FL_LPTIM32_OC_POLARITY_NORMAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_LPTIM32_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
281
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lpuart.c
Normal file
281
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_lpuart.c
Normal file
@ -0,0 +1,281 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_lpuart.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of LPUART FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPUART
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_LPUART_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup LPUART_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART0)||\
|
||||
((INSTANCE) == LPUART1)||\
|
||||
((INSTANCE) == LPUART2))
|
||||
|
||||
#define IS_FL_LPUART_CLKSRC(__VALUE__) (((__VALUE__) == FL_CMU_LPUART_CLK_SOURCE_LSCLK)||\
|
||||
((__VALUE__) == FL_CMU_LPUART_CLK_SOURCE_RCHF)||\
|
||||
((__VALUE__) == FL_CMU_LPUART_CLK_SOURCE_RCLF))
|
||||
|
||||
#define IS_FL_LPUART_BAUDRATE(__VALUE__) (((__VALUE__) == FL_LPUART_BAUDRATE_300)||\
|
||||
((__VALUE__) == FL_LPUART_BAUDRATE_600)||\
|
||||
((__VALUE__) == FL_LPUART_BAUDRATE_1200)||\
|
||||
((__VALUE__) == FL_LPUART_BAUDRATE_2400)||\
|
||||
((__VALUE__) == FL_LPUART_BAUDRATE_4800)||\
|
||||
((__VALUE__) == FL_LPUART_BAUDRATE_9600))
|
||||
|
||||
#define IS_FL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == FL_LPUART_DATA_WIDTH_6B)||\
|
||||
((__VALUE__) == FL_LPUART_DATA_WIDTH_7B)||\
|
||||
((__VALUE__) == FL_LPUART_DATA_WIDTH_8B)||\
|
||||
((__VALUE__) == FL_LPUART_DATA_WIDTH_9B))
|
||||
|
||||
#define IS_FL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == FL_LPUART_STOP_BIT_WIDTH_1B)||\
|
||||
((__VALUE__) == FL_LPUART_STOP_BIT_WIDTH_2B))
|
||||
|
||||
#define IS_FL_LPUART_PARITY(__VALUE__) (((__VALUE__) == FL_LPUART_PARITY_NONE)||\
|
||||
((__VALUE__) == FL_LPUART_PARITY_EVEN)||\
|
||||
((__VALUE__) == FL_LPUART_PARITY_ODD))
|
||||
|
||||
#define IS_FL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == FL_LPUART_DIRECTION_NONE)||\
|
||||
((__VALUE__) == FL_LPUART_DIRECTION_RX)||\
|
||||
((__VALUE__) == FL_LPUART_DIRECTION_TX)||\
|
||||
((__VALUE__) == FL_LPUART_DIRECTION_TX_RX))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LPUART_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位LPUART 外设
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_LPUART_DeInit(LPUART_Type *LPUARTx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口参数合法性断言 */
|
||||
assert_param(IS_LPUART_INSTANCE(LPUARTx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
if(LPUARTx == LPUART0)
|
||||
{
|
||||
/*复位LPUART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART0);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART0);
|
||||
/* 外设总线时钟关闭 */
|
||||
FL_CMU_IsEnabledGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART0);
|
||||
/* 外设工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART0);
|
||||
}
|
||||
else
|
||||
if(LPUARTx == LPUART1)
|
||||
{
|
||||
/*复位LPUART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART1);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART1);
|
||||
/* 外设总线时钟关闭 */
|
||||
FL_CMU_IsEnabledGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART1);
|
||||
/* 外设工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART1);
|
||||
}
|
||||
else
|
||||
if(LPUARTx == LPUART2)
|
||||
{
|
||||
/*复位LPUART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART2);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_LPUART2);
|
||||
/* 外设总线时钟关闭 */
|
||||
FL_CMU_IsEnabledGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART2);
|
||||
/* 外设工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART2);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = FL_FAIL;
|
||||
}
|
||||
/* 锁定外设复位功能 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置LPUART寄存器
|
||||
*
|
||||
* @note 波特率调制寄存器中的MCTL值，默认为工作时钟为32768Hz的频率下的调制值，用户如果外设工作时钟不是此前
|
||||
* 提则可能需要手动调整这个寄存器的值，以达到更好的通信效果。
|
||||
* @param LPUARTx 外设入口地址
|
||||
* @param initStruct 指向一个 @ref FL_LPUART_InitTypeDef类型的结构体，它包含指定LPUART外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS LPUART配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_LPUART_Init(LPUART_Type *LPUARTx, FL_LPUART_InitTypeDef *initStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
uint16_t MCTLVel;
|
||||
/* 参数合法性检查 */
|
||||
assert_param(IS_LPUART_INSTANCE(LPUARTx));
|
||||
assert_param(IS_FL_LPUART_CLKSRC(initStruct->clockSrc));
|
||||
assert_param(IS_FL_LPUART_BAUDRATE(initStruct->baudRate));
|
||||
assert_param(IS_FL_LPUART_DATAWIDTH(initStruct->dataWidth));
|
||||
assert_param(IS_FL_LPUART_STOPBITS(initStruct->stopBits));
|
||||
assert_param(IS_FL_LPUART_PARITY(initStruct->parity));
|
||||
assert_param(IS_FL_LPUART_DIRECTION(initStruct->transferDirection));
|
||||
if(LPUARTx == LPUART0)
|
||||
{
|
||||
/*总线时钟使能*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART0);
|
||||
/*操作时钟使能*/
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART0);
|
||||
/*时钟源选择*/
|
||||
FL_CMU_SetLPUART0ClockSource(initStruct->clockSrc << CMU_OPCCR1_LPUART0CKS_Pos);
|
||||
}
|
||||
else
|
||||
if(LPUARTx == LPUART1)
|
||||
{
|
||||
/*总线时钟使能*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART1);
|
||||
/*操作时钟使能*/
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART1);
|
||||
/*时钟源选择*/
|
||||
FL_CMU_SetLPUART1ClockSource(initStruct->clockSrc << CMU_OPCCR1_LPUART1CKS_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*总线时钟使能*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_LPUART2);
|
||||
/*操作时钟使能*/
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_LPUART2);
|
||||
/*时钟源选择*/
|
||||
FL_CMU_SetLPUART2ClockSource(initStruct->clockSrc << CMU_OPCCR1_LPUART2CKS_Pos);
|
||||
}
|
||||
if(initStruct->clockSrc == FL_CMU_LPUART_CLK_SOURCE_RCLF)//RCLF时钟
|
||||
{
|
||||
FL_CMU_RCLF_SetPrescaler(FL_CMU_RCLF_PSC_DIV16);
|
||||
FL_CMU_RCLF_Enable();
|
||||
FL_LPUART_DisableBaudRateModulation(LPUARTx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_LPUART_EnableBaudRateModulation(LPUARTx);
|
||||
}
|
||||
/*发送接收配置*/
|
||||
if(initStruct->transferDirection & FL_LPUART_DIRECTION_TX)
|
||||
{
|
||||
do
|
||||
{
|
||||
FL_LPUART_EnableTX(LPUARTx);
|
||||
} while(FL_LPUART_IsEnabledTX(LPUARTx) != FL_SET);
|
||||
}
|
||||
if(initStruct->transferDirection & FL_LPUART_DIRECTION_RX)
|
||||
{
|
||||
do
|
||||
{
|
||||
FL_LPUART_EnableRX(LPUARTx);
|
||||
} while(FL_LPUART_IsEnabledRX(LPUARTx) != FL_SET);
|
||||
}
|
||||
/*配置波特率*/
|
||||
FL_LPUART_SetBaudRate(LPUARTx, initStruct->baudRate);
|
||||
/*配置停止位*/
|
||||
FL_LPUART_SetStopBitsWidth(LPUARTx, initStruct->stopBits);
|
||||
/*配置数据位宽*/
|
||||
FL_LPUART_SetDataWidth(LPUARTx, initStruct->dataWidth);
|
||||
/*配置波特率*/
|
||||
FL_LPUART_SetParity(LPUARTx, initStruct->parity);
|
||||
/*根据波特率配置MCTL值*/
|
||||
switch(initStruct->baudRate)
|
||||
{
|
||||
case FL_LPUART_BAUDRATE_9600:
|
||||
MCTLVel = 0x0552;
|
||||
break;
|
||||
case FL_LPUART_BAUDRATE_4800:
|
||||
MCTLVel = 0x1EFB;
|
||||
break;
|
||||
case FL_LPUART_BAUDRATE_2400:
|
||||
MCTLVel = 0x16DB;
|
||||
break;
|
||||
case FL_LPUART_BAUDRATE_1200:
|
||||
MCTLVel = 0x0492;
|
||||
break;
|
||||
case FL_LPUART_BAUDRATE_600:
|
||||
MCTLVel = 0x16D6;
|
||||
break;
|
||||
case FL_LPUART_BAUDRATE_300:
|
||||
MCTLVel = 0x0842;
|
||||
break;
|
||||
default:
|
||||
MCTLVel = 0x0552;
|
||||
break;
|
||||
}
|
||||
FL_LPUART_WriteBitModulation(LPUARTx, MCTLVel);
|
||||
status = FL_PASS;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initStruct 为默认配置
|
||||
* @param initStruct 指向需要将值设置为默认配置的结构体 @ref FL_LPUART_InitTypeDef structure
|
||||
* 结构体
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_LPUART_StructInit(FL_LPUART_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->baudRate = FL_LPUART_BAUDRATE_9600;
|
||||
initStruct->dataWidth = FL_LPUART_DATA_WIDTH_8B;
|
||||
initStruct->stopBits = FL_LPUART_STOP_BIT_WIDTH_1B;
|
||||
initStruct->parity = FL_LPUART_PARITY_NONE ;
|
||||
initStruct->transferDirection = FL_LPUART_DIRECTION_TX_RX;
|
||||
initStruct->clockSrc = FL_CMU_LPUART_CLK_SOURCE_LSCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_LPUART_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
174
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_pmu.c
Normal file
174
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_pmu.c
Normal file
@ -0,0 +1,174 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_pmu.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of PMU FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PMU
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_PMU_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup UART_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define IS_FL_PMU_INSTANCE(INSTANCE) (((INSTANCE) == PMU))
|
||||
|
||||
#define IS_FL_PMU_MODE(__VALUE__) (((__VALUE__) == FL_PMU_POWER_MODE_ACTIVE_OR_LPACTIVE)||\
|
||||
((__VALUE__) == FL_PMU_POWER_MODE_LPRUN_ONLY)||\
|
||||
((__VALUE__) == FL_PMU_POWER_MODE_SLEEP_OR_DEEPSLEEP))
|
||||
|
||||
#define IS_FL_PMU_COREVOLTAGESCALING(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_PMU_DEEPSLEEP(__VALUE__) (((__VALUE__) == FL_PMU_SLEEP_MODE_DEEP)||\
|
||||
((__VALUE__) == FL_PMU_SLEEP_MODE_NORMAL))
|
||||
|
||||
#define IS_FL_PMU_WAKEUPFREQUENCY(__VALUE__) (((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_8MHZ)||\
|
||||
((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_16MHZ)||\
|
||||
((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_24MHZ))
|
||||
|
||||
#define IS_FL_PMU_LDOLOWMODE(__VALUE__) (((__VALUE__) == FL_PMU_LDO_LPM_DISABLE)||\
|
||||
((__VALUE__) == FL_PMU_LDO_LPM_ENABLE))
|
||||
|
||||
#define IS_FL_PMU_WAKEUPDELAY(__VALUE__) (((__VALUE__) == FL_PMU_WAKEUP_DELAY_0US)||\
|
||||
((__VALUE__) == FL_PMU_WAKEUP_DELAY_2US)||\
|
||||
((__VALUE__) == FL_PMU_WAKEUP_DELAY_4US)||\
|
||||
((__VALUE__) == FL_PMU_WAKEUP_DELAY_8US))
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PMU_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位pmu外设
|
||||
*
|
||||
* @param 外设入口地址
|
||||
*
|
||||
* @retval 返回错误状态，可能值:
|
||||
* -FL_PASS 外设寄存器值回复复位值
|
||||
* -FL_FAIL 位成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_PMU_Sleep_DeInit(PMU_Type *PMUx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
/* 参数合法性检测 */
|
||||
assert_param(IS_FL_PMU_INSTANCE(PMUx));
|
||||
PMUx->CR = 0x00060000U;
|
||||
PMUx->WKTR = 0xC0000001U;
|
||||
PMUx->IER = 0x00000000U;
|
||||
status = FL_PASS;
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief 根据lpm_initstruct结构体包含的配置信息配置pmu寄存器
|
||||
*
|
||||
* @note 为更好的睡眠功耗用户可能需要根据实际应用，调用 @ref fm33lg0xx_fl_pmu.h中的其他接口
|
||||
* 来完成睡眠前的模式配置，包括睡眠行为和唤醒后的行为(注：此函数会关闭BOR)
|
||||
* @param PMUx 外设入口地址
|
||||
* @param LPM_InitStruct 指向一个 @ref FL_PMU_SleepInitTypeDef 类型的结构体，它包含指定PMU外设的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS PMU配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_PMU_Sleep_Init(PMU_Type *PMUx, FL_PMU_SleepInitTypeDef *LPM_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
/* 参数合法性检查 */
|
||||
assert_param(IS_FL_PMU_INSTANCE(PMUx));
|
||||
assert_param(IS_FL_PMU_MODE(LPM_InitStruct->powerMode));
|
||||
assert_param(IS_FL_PMU_COREVOLTAGESCALING(LPM_InitStruct->coreVoltageScaling));
|
||||
assert_param(IS_FL_PMU_LDOLOWMODE(LPM_InitStruct->LDOLowPowerMode));
|
||||
assert_param(IS_FL_PMU_DEEPSLEEP(LPM_InitStruct->deepSleep));
|
||||
assert_param(IS_FL_PMU_WAKEUPFREQUENCY(LPM_InitStruct->wakeupFrequency));
|
||||
assert_param(IS_FL_PMU_WAKEUPDELAY(LPM_InitStruct->wakeupDelay));
|
||||
/* 唤醒时间 */
|
||||
FL_PMU_SetWakeupDelay(PMUx, LPM_InitStruct->wakeupDelay);
|
||||
/* 唤醒后RCHF的频率 */
|
||||
FL_PMU_SetRCHFWakeupFrequency(PMUx, LPM_InitStruct->wakeupFrequency);
|
||||
/* 睡眠下内核电压配置 */
|
||||
if(LPM_InitStruct->coreVoltageScaling == FL_ENABLE)
|
||||
{
|
||||
FL_PMU_EnableCoreVoltageScaling(PMUx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_PMU_DisableCoreVoltageScaling(PMUx);
|
||||
}
|
||||
/* LDO低功耗配置 */
|
||||
FL_PMU_SetLDOLowPowerMode(PMUx,LPM_InitStruct->LDOLowPowerMode);
|
||||
/* M0系统控制器，一般配置为0即可*/
|
||||
SCB->SCR = 0;
|
||||
/* 睡眠模式 */
|
||||
FL_PMU_SetSleepMode(PMUx, LPM_InitStruct->deepSleep);
|
||||
|
||||
status = FL_PASS;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LPM_InitStruct 为默认配置
|
||||
* @param LPM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_PMU_SleepInitTypeDef structure
|
||||
* 结构体
|
||||
* @retval None
|
||||
*/
|
||||
void FL_PMU_StructInit(FL_PMU_SleepInitTypeDef *LPM_InitStruct)
|
||||
{
|
||||
LPM_InitStruct->powerMode = FL_PMU_POWER_MODE_SLEEP_OR_DEEPSLEEP;
|
||||
LPM_InitStruct->deepSleep = FL_PMU_SLEEP_MODE_NORMAL;
|
||||
LPM_InitStruct->LDOLowPowerMode = FL_PMU_LDO_LPM_DISABLE;
|
||||
LPM_InitStruct->wakeupFrequency = FL_PMU_RCHF_WAKEUP_FREQ_8MHZ;
|
||||
LPM_InitStruct->wakeupDelay = FL_PMU_WAKEUP_DELAY_2US;
|
||||
LPM_InitStruct->coreVoltageScaling = FL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_PMU_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
201
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_rng.c
Normal file
201
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_rng.c
Normal file
@ -0,0 +1,201 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_rng.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of RNG FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_RNG_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RNG_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_RNG_INSTANCE(INTANCE) ((INTANCE) == RNG)
|
||||
|
||||
#define IS_FL_RNG_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == FL_CMU_RNG_PSC_DIV1)||\
|
||||
((__VALUE__) == FL_CMU_RNG_PSC_DIV2)||\
|
||||
((__VALUE__) == FL_CMU_RNG_PSC_DIV4)||\
|
||||
((__VALUE__) == FL_CMU_RNG_PSC_DIV8)||\
|
||||
((__VALUE__) == FL_CMU_RNG_PSC_DIV16)||\
|
||||
((__VALUE__) == FL_CMU_RNG_PSC_DIV32))
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RNG_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief 复位对应RNG寄存器.
|
||||
*
|
||||
* @param RNGx 外设入口地址
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_RNG_DeInit(RNG_Type *RNGx)
|
||||
{
|
||||
assert_param(IS_FL_RNG_INSTANCE(RNGx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_RNG);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_RNG);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_RNG);
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param RNGx 外设入口地址
|
||||
*
|
||||
* @param initStruct 指向一个 @ref FL_RNG_InitTypeDef 结构体 其中包含了外设的相关配置信息.
|
||||
*
|
||||
* @note RNG使用RCHF默认的8M作为时钟输入，经2分频后4M提供给RNG
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_RNG_Init(RNG_Type *RNGx)
|
||||
{
|
||||
assert_param(IS_FL_RNG_INSTANCE(RNGx));
|
||||
/* RNG 使用RCHF作为工作时钟因此必须确认RCHF使能*/
|
||||
if(FL_CMU_RCHF_IsEnabled() != FL_SET)
|
||||
{
|
||||
FL_CMU_RCHF_Enable();
|
||||
}
|
||||
/* RNG 总线时钟使能 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_RNG);
|
||||
/* RNG 工作时钟预分频*/
|
||||
switch(FL_CMU_GetRCHFClockFreq())
|
||||
{
|
||||
case FL_CMU_RCHF_FREQUENCY_8MHZ:
|
||||
FL_CMU_SetRNGPrescaler(FL_CMU_RNG_PSC_DIV2);
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_16MHZ:
|
||||
FL_CMU_SetRNGPrescaler(FL_CMU_RNG_PSC_DIV4);
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_24MHZ:
|
||||
FL_CMU_SetRNGPrescaler(FL_CMU_RNG_PSC_DIV8);
|
||||
break;
|
||||
case FL_CMU_RCHF_FREQUENCY_32MHZ:
|
||||
FL_CMU_SetRNGPrescaler(FL_CMU_RNG_PSC_DIV8);
|
||||
break;
|
||||
default:
|
||||
FL_CMU_SetRNGPrescaler(FL_CMU_RNG_PSC_DIV2);
|
||||
break;
|
||||
}
|
||||
/* RNG 工作时钟使能*/
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_RNG);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取一次随机数
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @note 如果返回值为0xFFFFFFFF 则说明随机数生成失败，请用户检查此函数的返回值，失败时重新生成
|
||||
*
|
||||
* @retval 成功返回随机数，失败返回0xFFFFFFFF
|
||||
*
|
||||
*/
|
||||
uint32_t GetRandomNumber(void)
|
||||
{
|
||||
uint32_t rn32;
|
||||
FL_RNG_ClearFlag_RandomFail(RNG);
|
||||
FL_RNG_Enable(RNG);
|
||||
/* 由于LFSR循环移位周期是32cycle，为保证随机数质量，应用应保证两次读取RNGOUT之间的间隔大于32个TRNG_CLK周期 */
|
||||
FL_DelayUs(12);
|
||||
FL_RNG_Disable(RNG);
|
||||
rn32 = FL_RNG_ReadData(RNG);
|
||||
if(FL_RNG_IsActiveFlag_RandomFail(RNG))
|
||||
{
|
||||
FL_RNG_ClearFlag_RandomFail(RNG);
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
return rn32;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取CRC32
|
||||
*
|
||||
* @param dataIn 待计算的数据
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
* @retval 成功返回CRC32，失败返回0xFFFFFFFF
|
||||
*
|
||||
*/
|
||||
uint32_t GetCrc32(uint32_t dataIn)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
uint32_t crc32 = 0;
|
||||
FL_RNG_CRC_WriteData(RNG, dataIn);
|
||||
FL_RNG_ClearFlag_CRCComplete(RNG);
|
||||
FL_RNG_CRC_Enable(RNG);
|
||||
while(0 == FL_RNG_IsActiveFlag_CRCComplete(RNG))
|
||||
{
|
||||
i++;
|
||||
if(i > 600)
|
||||
{ break; }
|
||||
}
|
||||
if(i >= 600)
|
||||
{
|
||||
FL_RNG_ClearFlag_CRCComplete(RNG);
|
||||
FL_RNG_Disable(RNG);
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
FL_RNG_ClearFlag_CRCComplete(RNG);
|
||||
crc32 = FL_RNG_ReadData(RNG);
|
||||
FL_RNG_Disable(RNG);
|
||||
return crc32;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_RNG_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
187
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_rtca.c
Normal file
187
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_rtca.c
Normal file
@ -0,0 +1,187 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_rtca.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of RTCA FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_RTCA_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RTCA_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTCA_INSTANCE(RTCAx) ((RTCAx) == RTCA)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTCA_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief 复位对应RTCAx寄存器.
|
||||
* @param RTCAx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_RTCA_DeInit(RTCA_Type *RTCAx)
|
||||
{
|
||||
FL_ErrorStatus result = FL_PASS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTCA_INSTANCE(RTCAx));
|
||||
RTCAx->IER = 0x00000000U;
|
||||
RTCAx->WER = 0xACACACACU;
|
||||
RTCAx->ADJUST = 0x00000000U;
|
||||
RTCAx->ADSIGN = 0x00000000U;
|
||||
RTCAx->ALARM = 0x00000000U;
|
||||
RTCAx->BCDDAY = 0x00000000U;
|
||||
RTCAx->BCDHOUR = 0x00000000U;
|
||||
RTCAx->BCDMIN = 0x00000000U;
|
||||
RTCAx->BCDMONTH = 0x00000000U;
|
||||
RTCAx->BCDSEC = 0x00000000U;
|
||||
RTCAx->BCDWEEK = 0x00000000U;
|
||||
RTCAx->BCDYEAR = 0x00000000U;
|
||||
RTCAx->SBSCNT = 0x00000000U;
|
||||
RTCAx->TMSEL = 0x00000000U;
|
||||
RTCAx->CR = 0x00000000U;
|
||||
RTCAx->WER = 0x00000000U;
|
||||
return result;
|
||||
}
|
||||
/**
|
||||
* @brief 配置实时时钟相关.
|
||||
* @param RTCAx Timer Instance
|
||||
* @param initStruct 指向一个 @ref FL_RTCA_InitTypeDef(时基配置结构体)
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_RTCA_Init(RTCA_Type *RTCAx, FL_RTCA_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_RTCA_INSTANCE(RTCAx));
|
||||
/* 时钟总线使能配置 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_RTCA);
|
||||
/* 配置时间 */
|
||||
FL_RTCA_ConfigTime(RTCAx, initStruct);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置实时时钟
|
||||
* @param RTCAx Timer Instance
|
||||
* @param initStruct 指向一个 @ref FL_RTCA_InitTypeDef(时基配置结构体)
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_RTCA_ConfigTime(RTCA_Type *RTCAx, FL_RTCA_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 使能时间配置 */
|
||||
FL_RTCA_WriteEnable(RTCAx);
|
||||
/* 配置秒 */
|
||||
FL_RTCA_WriteSecond(RTCAx, initStruct->second);
|
||||
/* 配置分钟 */
|
||||
FL_RTCA_WriteMinute(RTCAx, initStruct->minute);
|
||||
/* 配置小时 */
|
||||
FL_RTCA_WriteHour(RTCAx, initStruct->hour);
|
||||
/* 配置日期 */
|
||||
FL_RTCA_WriteDay(RTCAx, initStruct->day);
|
||||
/* 配置周 */
|
||||
FL_RTCA_WriteWeek(RTCAx, initStruct->week);
|
||||
/* 配置月 */
|
||||
FL_RTCA_WriteMonth(RTCAx, initStruct->month);
|
||||
/* 配置年 */
|
||||
FL_RTCA_WriteYear(RTCAx, initStruct->year);
|
||||
/* 锁定时间配置 */
|
||||
FL_RTCA_WriteDisable(RTCAx);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 获取实时时间并保存到指定结构体中
|
||||
* @param RTCAx Timer Instance
|
||||
* @param initStruct 指向一个 @ref FL_RTCA_InitTypeDef(时基配置结构体)
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 成功
|
||||
*/
|
||||
FL_ErrorStatus FL_RTCA_GetTime(RTCA_Type *RTCAx, FL_RTCA_InitTypeDef *initStruct)
|
||||
{
|
||||
/* 配置秒 */
|
||||
initStruct->second = FL_RTCA_ReadSecond(RTCAx);
|
||||
/* 配置分钟 */
|
||||
initStruct->minute = FL_RTCA_ReadMinute(RTCAx);
|
||||
/* 配置小时 */
|
||||
initStruct->hour = FL_RTCA_ReadHour(RTCAx);
|
||||
/* 配置日期 */
|
||||
initStruct->day = FL_RTCA_ReadDay(RTCAx);
|
||||
/* 配置周 */
|
||||
initStruct->week = FL_RTCA_ReadWeek(RTCAx);
|
||||
/* 配置月 */
|
||||
initStruct->month = FL_RTCA_ReadMonth(RTCAx);
|
||||
/* 配置年 */
|
||||
initStruct->year = FL_RTCA_ReadYear(RTCAx);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 initStruct 为默认配置
|
||||
* @param initStruct 指向需要将值设置为默认配置的结构体 @ref FL_RTCA_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_RTCA_StructInit(FL_RTCA_InitTypeDef *initStruct)
|
||||
{
|
||||
/* */
|
||||
initStruct->year = 0x00;
|
||||
initStruct->month = 0x00;
|
||||
initStruct->day = 0x00;
|
||||
initStruct->week = 0x00;
|
||||
initStruct->hour = 0x00;
|
||||
initStruct->minute = 0x00;
|
||||
initStruct->second = 0x00;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_RTCA_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
229
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_spi.c
Normal file
229
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_spi.c
Normal file
@ -0,0 +1,229 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_spi.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of SPI FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_SPI_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup SPI_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_SPI_INSTANCE(INTANCE) (((INTANCE) == SPI0)||\
|
||||
((INTANCE) == SPI1)||\
|
||||
((INTANCE) == SPI2))
|
||||
|
||||
#define IS_FL_SPI_MODE(__VALUE__) (((__VALUE__) == FL_SPI_WORK_MODE_SLAVE)||\
|
||||
((__VALUE__) == FL_SPI_WORK_MODE_MASTER))
|
||||
|
||||
#define IS_FL_SPI_BITORDER(__VALUE__) (((__VALUE__) == FL_SPI_BIT_ORDER_MSB_FIRST)||\
|
||||
((__VALUE__) == FL_SPI_BIT_ORDER_LSB_FIRST))
|
||||
|
||||
#define IS_FL_SPI_DATAWIDT(__VALUE__) (((__VALUE__) == FL_SPI_DATA_WIDTH_8B)||\
|
||||
((__VALUE__) == FL_SPI_DATA_WIDTH_16B)||\
|
||||
((__VALUE__) == FL_SPI_DATA_WIDTH_24B)||\
|
||||
((__VALUE__) == FL_SPI_DATA_WIDTH_32B))
|
||||
|
||||
#define IS_FL_SPI_CLOCK_PHASE(__VALUE__) (((__VALUE__) == FL_SPI_PHASE_EDGE1)||\
|
||||
((__VALUE__) == FL_SPI_PHASE_EDGE2))
|
||||
|
||||
#define IS_FL_SPI_CLOCK_POLARITY(__VALUE__) (((__VALUE__) == FL_SPI_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_SPI_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == FL_SPI_BAUDRATE_DIV2)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV4)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV8)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV16)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV32)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV64)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV128)||\
|
||||
((__VALUE__) == FL_SPI_BAUDRATE_DIV256))
|
||||
|
||||
|
||||
#define IS_FL_SPI_TANSFERMODE(__VALUE__) (((__VALUE__) == FL_SPI_TRANSFER_MODE_FULL_DUPLEX)||\
|
||||
((__VALUE__) == FL_SPI_TRANSFER_MODE_HALF_DUPLEX))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应SPI寄存器.
|
||||
* @param SPIx
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_SPI_DeInit(SPI_Type *SPIx)
|
||||
{
|
||||
assert_param(IS_FL_SPI_INSTANCE(SPIx));
|
||||
/* 使能外设复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
if(SPIx == SPI0)
|
||||
{
|
||||
/* 复位SPI外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI0);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI0);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI0);
|
||||
}
|
||||
else
|
||||
if(SPIx == SPI1)
|
||||
{
|
||||
/* 复位SPI外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI1);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI1);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI1);
|
||||
}
|
||||
else
|
||||
if(SPIx == SPI2)
|
||||
{
|
||||
/* 复位SPI外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI2);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SPI2);
|
||||
/* 关闭外设总线始时钟和工作时钟 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI2);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_FAIL;
|
||||
}
|
||||
/* 锁定外设复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 SPI_InitStruct 的配置信息初始化对应外设入口地址的寄存器值.
|
||||
* @param SPIx SPIx
|
||||
* @param SPI_InitStruct 指向一个 @ref FL_SPI_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS SPI配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_SPI_Init(SPI_Type *SPIx, FL_SPI_InitTypeDef *initStruct)
|
||||
{
|
||||
assert_param(IS_FL_SPI_INSTANCE(SPIx));
|
||||
assert_param(IS_FL_SPI_MODE(initStruct->mode));
|
||||
assert_param(IS_FL_SPI_BITORDER(initStruct->bitOrder));
|
||||
assert_param(IS_FL_SPI_DATAWIDT(initStruct->dataWidth));
|
||||
assert_param(IS_FL_SPI_BAUDRATE(initStruct->baudRate));
|
||||
assert_param(IS_FL_SPI_CLOCK_PHASE(initStruct->clockPhase));
|
||||
assert_param(IS_FL_SPI_CLOCK_POLARITY(initStruct->clockPolarity));
|
||||
if(SPIx == SPI0)
|
||||
{
|
||||
/* 外设总线始时钟 */
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI0);
|
||||
}
|
||||
else
|
||||
if(SPIx == SPI1)
|
||||
{
|
||||
/* 外设总线始时钟 */
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI1);
|
||||
}
|
||||
else
|
||||
if(SPIx == SPI2)
|
||||
{
|
||||
/* 外设总线始时钟 */
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_SPI2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return FL_FAIL;
|
||||
}
|
||||
/* 选择NSS脚控制模式 */
|
||||
if(initStruct->softControl == FL_ENABLE)
|
||||
{
|
||||
FL_SPI_EnableSSNSoftControl(SPIx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_SPI_DisableSSNSoftControl(SPIx);
|
||||
}
|
||||
/* 外设工作主从模式 */
|
||||
FL_SPI_SetWorkMode(SPIx, initStruct->mode);
|
||||
/* 总线通讯速率 */
|
||||
FL_SPI_SetClockDivision(SPIx, initStruct->baudRate);
|
||||
/* 数据bit方向 */
|
||||
FL_SPI_SetBitOrder(SPIx, initStruct->bitOrder);
|
||||
/* 总线数据位宽 */
|
||||
FL_SPI_SetDataWidth(SPIx, initStruct->dataWidth);
|
||||
/* 时钟相位 */
|
||||
FL_SPI_SetClockPhase(SPIx, initStruct->clockPhase);
|
||||
/* 传输模式 双工半双工 */
|
||||
FL_SPI_SetTransferMode(SPIx, initStruct->transferMode);
|
||||
/* 时钟极性 */
|
||||
FL_SPI_SetClockPolarity(SPIx, initStruct->clockPolarity);
|
||||
/* 使能 外设*/
|
||||
FL_SPI_Enable(SPIx);
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 SPI_InitStruct 为默认配置
|
||||
* @param SPI_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_SPI_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_SPI_StructInit(FL_SPI_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->softControl = FL_DISABLE;
|
||||
initStruct->mode = FL_SPI_WORK_MODE_MASTER;
|
||||
initStruct->baudRate = FL_SPI_CLK_DIV8;
|
||||
initStruct->bitOrder = FL_SPI_BIT_ORDER_MSB_FIRST;
|
||||
initStruct->dataWidth = FL_SPI_DATA_WIDTH_8B;
|
||||
initStruct->clockPolarity = FL_SPI_POLARITY_NORMAL;
|
||||
initStruct->clockPhase = FL_SPI_PHASE_EDGE1;
|
||||
initStruct->transferMode = FL_SPI_TRANSFER_MODE_FULL_DUPLEX;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_SPI_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
191
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_svd.c
Normal file
191
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_svd.c
Normal file
@ -0,0 +1,191 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_svd.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of SVD FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SVD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_SVD_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup SVD_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SVD_INSTANCE(INSTANCE) (((INSTANCE) == SVD))
|
||||
|
||||
#define IS_FL_SVD_REFERENCE_VOLTAGE(__VALUE__) (((__VALUE__) == FL_SVD_REFERENCE_1P0V)||\
|
||||
((__VALUE__) == FL_SVD_REFERENCE_0P95V)||\
|
||||
((__VALUE__) == FL_SVD_REFERENCE_0P9V))
|
||||
|
||||
#define IS_FL_SVD_WARNING_THRESHOLD_LEVEL(__VALUE__) (((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP0)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP1)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP2)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP3)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP4)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP5)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP6)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP7)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP8)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP9)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP10)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP11)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP12)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP13)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP14)||\
|
||||
((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP15))
|
||||
|
||||
#define IS_FL_SVD_WORK_MODE(__VALUE__) (((__VALUE__) == FL_SVD_WORK_MODE_CONTINUOUS)||\
|
||||
((__VALUE__) == FL_SVD_WORK_MODE_PERIODIC))
|
||||
|
||||
#define IS_FL_SVD_ENABLE_PERIOD(__VALUE__) (((__VALUE__) == FL_SVD_ENABLE_PERIOD_62P5MS)||\
|
||||
((__VALUE__) == FL_SVD_ENABLE_PERIOD_256MS)||\
|
||||
((__VALUE__) == FL_SVD_ENABLE_PERIOD_1000MS)||\
|
||||
((__VALUE__) == FL_SVD_ENABLE_PERIOD_4000MS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SVD_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位SVD外设
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值：
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_SVD_DeInit(SVD_Type *SVDx)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_SVD_INSTANCE(SVDx));
|
||||
/* 使能复位 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
/* 复位外设寄存器 */
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SVD);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_SVD);
|
||||
/* 关闭外设总线时钟 */
|
||||
FL_CMU_DisableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_SVD);
|
||||
/* 关闭复位 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要功能配置SVD寄存器
|
||||
*
|
||||
* @param SVDx 外设入口地址
|
||||
* @param init @ref FL_SVD_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS SVD配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_SVD_Init(SVD_Type *SVDx, FL_SVD_InitTypeDef *init)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_SVD_INSTANCE(SVDx));
|
||||
assert_param(IS_FL_SVD_REFERENCE_VOLTAGE(init->referenceVoltage));
|
||||
assert_param(IS_FL_SVD_WARNING_THRESHOLD_LEVEL(init->warningThreshold));
|
||||
assert_param(IS_FL_SVD_WORK_MODE(init->workMode));
|
||||
assert_param(IS_FL_SVD_ENABLE_PERIOD(init->enablePeriod));
|
||||
/* 开启SVD时钟 */
|
||||
if(SVDx == SVD)
|
||||
{
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_SVD);
|
||||
}
|
||||
else
|
||||
{
|
||||
return FL_FAIL;
|
||||
}
|
||||
/* 设置参考基准 */
|
||||
FL_SVD_EnableReference(SVDx, init->referenceVoltage);
|
||||
/* 设置报警阈值 */
|
||||
FL_SVD_SetWarningThreshold(SVDx, init->warningThreshold);
|
||||
/* 数字滤波 */
|
||||
if(init->digitalFilter == FL_ENABLE)
|
||||
{
|
||||
FL_SVD_EnableDigitalFilter(SVDx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_SVD_DisableDigitalFilter(SVDx);
|
||||
}
|
||||
/* 工作模式 */
|
||||
FL_SVD_SetWorkMode(SVDx, init->workMode);
|
||||
if(init->workMode == FL_SVD_WORK_MODE_PERIODIC)
|
||||
{
|
||||
/* 间歇使能间隔 */
|
||||
FL_SVD_SetEnablePeriod(SVDx, init->enablePeriod);
|
||||
}
|
||||
/* SVS通道 */
|
||||
if(init->SVSChannel == FL_ENABLE)
|
||||
{
|
||||
FL_SVD_EnableSVSChannel(SVDx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_SVD_DisableSVSChannel(SVDx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 SVD_InitStruct 为默认配置
|
||||
* @param init @ref FL_SVD_InitTypeDef类型的结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_SVD_StructInit(FL_SVD_InitTypeDef *init)
|
||||
{
|
||||
init->referenceVoltage = FL_SVD_REFERENCE_1P0V;
|
||||
init->SVSChannel = FL_DISABLE;
|
||||
init->digitalFilter = FL_DISABLE;
|
||||
init->workMode = FL_SVD_WORK_MODE_CONTINUOUS;
|
||||
init->enablePeriod = FL_SVD_ENABLE_PERIOD_62P5MS;
|
||||
init->warningThreshold = FL_SVD_WARNING_THRESHOLD_GROUP0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_SVD_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
|
||||
375
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_uart.c
Normal file
375
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_uart.c
Normal file
@ -0,0 +1,375 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_uart.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of UART FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2020] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_UART_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup UART_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == UART0)||\
|
||||
((INSTANCE) == UART1)||\
|
||||
((INSTANCE) == UART3)||\
|
||||
((INSTANCE) == UART4)||\
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
#define IS_FL_UART_CLKSRC(__VALUE__) (((__VALUE__) == FL_CMU_UART0_CLK_SOURCE_APBCLK)||\
|
||||
((__VALUE__) == FL_CMU_UART0_CLK_SOURCE_RCHF)||\
|
||||
((__VALUE__) == FL_CMU_UART0_CLK_SOURCE_SYSCLK)||\
|
||||
((__VALUE__) == FL_CMU_UART0_CLK_SOURCE_XTHF)||\
|
||||
((__VALUE__) == FL_CMU_UART1_CLK_SOURCE_APBCLK)||\
|
||||
((__VALUE__) == FL_CMU_UART1_CLK_SOURCE_RCHF)||\
|
||||
((__VALUE__) == FL_CMU_UART1_CLK_SOURCE_SYSCLK)||\
|
||||
((__VALUE__) == FL_CMU_UART1_CLK_SOURCE_XTHF))
|
||||
|
||||
|
||||
#define IS_FL_UART_DATAWIDTH(__VALUE__) (((__VALUE__) == FL_UART_DATA_WIDTH_6B)||\
|
||||
((__VALUE__) == FL_UART_DATA_WIDTH_7B)||\
|
||||
((__VALUE__) == FL_UART_DATA_WIDTH_8B)||\
|
||||
((__VALUE__) == FL_UART_DATA_WIDTH_9B))
|
||||
|
||||
#define IS_FL_UART_STOPBITS(__VALUE__) (((__VALUE__) == FL_UART_STOP_BIT_WIDTH_1B)||\
|
||||
((__VALUE__) == FL_UART_STOP_BIT_WIDTH_2B))
|
||||
|
||||
#define IS_FL_UART_PARITY(__VALUE__) (((__VALUE__) == FL_UART_PARITY_NONE)||\
|
||||
((__VALUE__) == FL_UART_PARITY_EVEN)||\
|
||||
((__VALUE__) == FL_UART_PARITY_ODD))
|
||||
|
||||
#define IS_FL_UART_DIRECTION(__VALUE__) (((__VALUE__) == FL_UART_DIRECTION_NONE)||\
|
||||
((__VALUE__) == FL_UART_DIRECTION_RX)||\
|
||||
((__VALUE__) == FL_UART_DIRECTION_TX)||\
|
||||
((__VALUE__) == FL_UART_DIRECTION_TX_RX))
|
||||
|
||||
#define IS_FL_UART_INFRA_MODULATION(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
|
||||
#define IS_FL_UART_INFRARED_POLARITY(__VALUE__) (((__VALUE__) == FL_UART_INFRARED_POLARITY_NORMAL)||\
|
||||
((__VALUE__) == FL_UART_INFRARED_POLARITY_INVERT))
|
||||
|
||||
#define IS_FL_UART_INFRARED_MODULATION_DUTY(__VALUE__) (((__VALUE__) <= 100))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UART_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位UART 外设寄存器值为复位值
|
||||
* @param 外设入口地址
|
||||
* @retval 返回错误状态，可能值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 复位未成功
|
||||
*/
|
||||
FL_ErrorStatus FL_UART_DeInit(UART_Type *UARTx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 参数入口合法性 */
|
||||
assert_param(IS_UART_INSTANCE(UARTx));
|
||||
/* 外设复位使能 */
|
||||
FL_RMU_EnablePeripheralReset(RMU);
|
||||
if(UARTx == UART0)
|
||||
{
|
||||
/*复位UART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART0);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART0);
|
||||
/* 外设总线时钟关闭 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART0);
|
||||
/* 外设工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_UART0);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART1)
|
||||
{
|
||||
/*复位UART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART1);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART1);
|
||||
/* 外设总线时钟关闭 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART1);
|
||||
/* 外设工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_UART1);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART3)
|
||||
{
|
||||
/*复位UART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART3);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART3);
|
||||
/* UART3、4、5为单时钟，关闭总线时钟 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART3);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART4)
|
||||
{
|
||||
/*复位UART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART4);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART4);
|
||||
/* 总线、工作时钟关闭 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART4);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART5)
|
||||
{
|
||||
/*复位UART*/
|
||||
FL_RMU_EnableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART5);
|
||||
FL_RMU_DisableResetAPBPeripheral(RMU, FL_RMU_RSTAPB_UART5);
|
||||
/* 总线（工作）时钟关闭 */
|
||||
FL_CMU_DisableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART5);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = FL_FAIL;
|
||||
}
|
||||
/* 锁定外设复位功能 */
|
||||
FL_RMU_DisablePeripheralReset(RMU);
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据需要配置UART
|
||||
*
|
||||
* @param UARTx 外设入口地址
|
||||
* @param UART_InitStruct指向一个FL_UART_InitTypeDef类型的结构体,它包含外设UART的配置信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS UART配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_UART_Init(UART_Type *UARTx, FL_UART_InitTypeDef *initStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
uint32_t Fclk = 0, BaudRate = 0;
|
||||
/* 参数合法性检查 */
|
||||
assert_param(IS_UART_INSTANCE(UARTx));
|
||||
assert_param(IS_FL_UART_CLKSRC(initStruct->clockSrc));
|
||||
assert_param(IS_FL_UART_DATAWIDTH(initStruct->dataWidth));
|
||||
assert_param(IS_FL_UART_PARITY(initStruct->parity));
|
||||
assert_param(IS_FL_UART_STOPBITS(initStruct->stopBits));
|
||||
assert_param(IS_FL_UART_DIRECTION(initStruct->transferDirection));
|
||||
if(UARTx == UART0)
|
||||
{
|
||||
/*时钟源选择*/
|
||||
FL_CMU_SetUART0ClockSource(initStruct->clockSrc);
|
||||
/* 根据不同的时钟源计算baudrate 寄存器值,并配置 */
|
||||
switch(initStruct->clockSrc)
|
||||
{
|
||||
case FL_CMU_UART0_CLK_SOURCE_APBCLK:
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART0_CLK_SOURCE_RCHF:
|
||||
Fclk = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART0_CLK_SOURCE_SYSCLK:
|
||||
Fclk = FL_CMU_GetSystemClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART0_CLK_SOURCE_XTHF:
|
||||
Fclk = XTHFClock;
|
||||
break;
|
||||
default:
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
break;
|
||||
}
|
||||
BaudRate = Fclk / initStruct->baudRate - 1;
|
||||
}
|
||||
if(UARTx == UART1)
|
||||
{
|
||||
/*时钟源选择*/
|
||||
FL_CMU_SetUART1ClockSource(initStruct->clockSrc);
|
||||
/* 根据不同的时钟源计算baudrate 寄存器值,并配置 */
|
||||
switch(initStruct->clockSrc)
|
||||
{
|
||||
case FL_CMU_UART1_CLK_SOURCE_APBCLK:
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART1_CLK_SOURCE_RCHF:
|
||||
Fclk = FL_CMU_GetRCHFClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART1_CLK_SOURCE_SYSCLK :
|
||||
Fclk = FL_CMU_GetSystemClockFreq();
|
||||
break;
|
||||
case FL_CMU_UART1_CLK_SOURCE_XTHF:
|
||||
Fclk = XTHFClock;
|
||||
break;
|
||||
default:
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
break;
|
||||
}
|
||||
BaudRate = Fclk / initStruct->baudRate - 1;
|
||||
}
|
||||
if(UARTx == UART0)
|
||||
{
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART0);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_UART0);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART1)
|
||||
{
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART1);
|
||||
FL_CMU_EnableGroup3OperationClock(FL_CMU_GROUP3_OPCLK_UART1);
|
||||
}
|
||||
else
|
||||
if(UARTx == UART3)
|
||||
{
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART3);
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
BaudRate = Fclk / initStruct->baudRate - 1;
|
||||
}
|
||||
else
|
||||
if(UARTx == UART4)
|
||||
{
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART4);
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
BaudRate = Fclk / initStruct->baudRate - 1;
|
||||
}
|
||||
else
|
||||
if(UARTx == UART5)
|
||||
{
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UART5);
|
||||
Fclk = FL_CMU_GetAPBClockFreq();
|
||||
BaudRate = Fclk / initStruct->baudRate - 1;
|
||||
}
|
||||
/*发送接收控制*/
|
||||
if(initStruct->transferDirection & FL_UART_DIRECTION_TX)
|
||||
{
|
||||
FL_UART_EnableTX(UARTx);
|
||||
}
|
||||
if(initStruct->transferDirection & FL_UART_DIRECTION_RX)
|
||||
{
|
||||
FL_UART_EnableRX(UARTx);
|
||||
}
|
||||
/*配置波特率*/
|
||||
FL_UART_WriteBaudRate(UARTx, BaudRate);
|
||||
/*配置停止位长度*/
|
||||
FL_UART_SetStopBitsWidth(UARTx, initStruct->stopBits);
|
||||
/*数据长度*/
|
||||
FL_UART_SetDataWidth(UARTx, initStruct->dataWidth);
|
||||
/*配置奇偶校验*/
|
||||
FL_UART_SetParity(UARTx, initStruct->parity);
|
||||
status = FL_PASS;
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 根据需要配置红外调制寄存器
|
||||
*
|
||||
* @param UARTx 外设入口地址
|
||||
*
|
||||
* @param initStruct指向FL_UART_InitTypeDef类型的结构体,包含UART外设信息
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程出现错误
|
||||
* -FL_PASS UART配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_UART_InfraRed_Init(UART_Type *UARTx, FL_UART_InfraRed_InitTypeDef *initStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
uint32_t tempTZBRG = 0, tempTH = 0;
|
||||
/* 参数合法性检查 */
|
||||
assert_param(IS_UART_INSTANCE(UARTx));
|
||||
assert_param(IS_FL_UART_INFRARED_POLARITY(initStruct->polarity));
|
||||
assert_param(IS_FL_UART_INFRARED_MODULATION_DUTY(initStruct->modulationDuty));
|
||||
/*红外发送总线时钟使能*/
|
||||
FL_CMU_EnableGroup3BusClock(FL_CMU_GROUP3_BUSCLK_UARTIR);
|
||||
/*红外发送使能*/
|
||||
FL_UART_EnableIRModulation(UARTx);
|
||||
/*红外调制极性*/
|
||||
FL_UART_SetIRPolarity(UART, initStruct->polarity);
|
||||
/*红外调制频率*/
|
||||
tempTZBRG = (uint32_t)((FL_CMU_GetAPBClockFreq() * 1.0) / initStruct->modulationFrequency - 1);
|
||||
/* 调制占空比 */
|
||||
if((tempTZBRG >> 4) != 0)
|
||||
{
|
||||
tempTH = (uint32_t)(((float)initStruct->modulationDuty / 100.0f) * ((float)(tempTZBRG + 1) / (float)(tempTZBRG >> 4)) + 0.5f);
|
||||
}
|
||||
else
|
||||
{
|
||||
tempTH = (uint32_t)(((float)initStruct->modulationDuty / 100.0f) * (float)(tempTZBRG + 1) + 0.5f);
|
||||
}
|
||||
/* 占空比限位到小于95%，否则结果会有问题 */
|
||||
tempTH = ((float)((tempTZBRG >> 4) * tempTH) / (float)(tempTZBRG + 1)) < 0.95f ? tempTH : tempTH - 1;
|
||||
/* 占空比和调制频率配置 */
|
||||
FL_UART_WriteIRModulationDuty(UART, tempTH);
|
||||
FL_UART_WriteIRModulationFrequency(UART, tempTZBRG);
|
||||
status = FL_PASS;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART_InitStruct 为默认配置
|
||||
* @param UART_InitStruct 指向需要将值设置为默认配置 的结构体@ref FL_UART_InitTypeDef structure 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_UART_InfraRed_StructInit(FL_UART_InfraRed_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->polarity = FL_UART_INFRARED_POLARITY_NORMAL;
|
||||
initStruct->modulationDuty = 50;
|
||||
initStruct->modulationFrequency = 38000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART_InitStruct 为默认配置
|
||||
* @param UART_InitStruct 指向需要将值设置为默认配置 的结构体@ref FL_UART_InitTypeDef structure 结构体
|
||||
* 结构体
|
||||
* @retval None
|
||||
*/
|
||||
void FL_UART_StructInit(FL_UART_InitTypeDef *initStruct)
|
||||
{
|
||||
initStruct->baudRate = 115200;
|
||||
initStruct->dataWidth = FL_UART_DATA_WIDTH_8B;
|
||||
initStruct->stopBits = FL_UART_STOP_BIT_WIDTH_1B;
|
||||
initStruct->parity = FL_UART_PARITY_EVEN ;
|
||||
initStruct->transferDirection = FL_UART_DIRECTION_TX_RX;
|
||||
initStruct->clockSrc = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_UART_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
226
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_vao.c
Normal file
226
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_vao.c
Normal file
@ -0,0 +1,226 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lg0xx_fl_vao.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of DMA FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup VAO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FL_VAO_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup VAO_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FL_VAO_INSTANCE(INTANCE) ((INTANCE) == VAO)
|
||||
|
||||
#define IS_FL_VAO_OUTPUT_DRIVE_ABILITY(__VALUE__) (((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_NONE)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_1)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_2)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_3)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_4)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_5)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_6)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_DRIVE_LEVEL_7))
|
||||
|
||||
#define IS_FL_VAO_WORKING_CURRENT(__VALUE__) (((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_850NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_800NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_750NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_700NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_650NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_600NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_550NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_500NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_450NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_400NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_350NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_300NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_250NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_200NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_150NA)||\
|
||||
((__VALUE__) == FL_VAO_XTLF_WORK_CURRENT_100NA))
|
||||
|
||||
#define IS_FL_VAO_PH15_INPUT(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_VAO_PH15_PULL_UP(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
|
||||
#define IS_FL_VAO_PH15_OPENDRAIN_OUTPUT(__VALUE__) (((__VALUE__) == FL_DISABLE)||\
|
||||
((__VALUE__) == FL_ENABLE))
|
||||
|
||||
#define IS_FL_VAO_PH15_MODE(__VALUE__) (((__VALUE__) == FL_VAO_PH15_MODE_INPUT)||\
|
||||
((__VALUE__) == FL_VAO_PH15_MODE_OUTPUT)||\
|
||||
((__VALUE__) == FL_VAO_PH15_MODE_RTCOUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup VAO_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 复位对应VAO寄存器
|
||||
* @param VAOx VAO Port
|
||||
* @retval ErrorStatus枚举值:
|
||||
* -FL_PASS 外设寄存器值恢复复位值
|
||||
* -FL_FAIL 未成功执行
|
||||
*/
|
||||
FL_ErrorStatus FL_VAO_DeInit(VAO_Type *VAOx)
|
||||
{
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_FL_VAO_INSTANCE(VAOx));
|
||||
/* 使能vao复位 */
|
||||
FL_VAO_EnableReset(VAOx);
|
||||
/*失能CDIF*/
|
||||
FL_CDIF_DisableVAOToCPU(CDIF);
|
||||
FL_CDIF_DisableCPUToVAO(CDIF);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 VAO_IO_StructInit 的配置信息初始化对应外设入口地址的寄存器值
|
||||
* @param VAOx VAOx
|
||||
* @param VAO_IO_StructInit 指向一个 @ref FL_VAO_IO_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_VAO_IO_Init(VAO_Type *VAOx, FL_VAO_IO_InitTypeDef *VAO_IO_InitStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_VAO_INSTANCE(VAOx));
|
||||
assert_param(IS_FL_VAO_PH15_INPUT(VAO_IO_InitStruct->input));
|
||||
assert_param(IS_FL_VAO_PH15_PULL_UP(VAO_IO_InitStruct->pullup));
|
||||
assert_param(IS_FL_VAO_PH15_OPENDRAIN_OUTPUT(VAO_IO_InitStruct->opendrainOutput));
|
||||
assert_param(IS_FL_VAO_PH15_MODE(VAO_IO_InitStruct->mode));
|
||||
/*使能CDIF*/
|
||||
FL_CDIF_EnableVAOToCPU(CDIF);
|
||||
FL_CDIF_EnableCPUToVAO(CDIF);
|
||||
/*! PH15功能选择 */
|
||||
FL_VAO_GPIO_SetPH15Mode(VAOx, VAO_IO_InitStruct->mode);
|
||||
/*! PH15输入使能 */
|
||||
if(VAO_IO_InitStruct->input == FL_ENABLE)
|
||||
{
|
||||
FL_VAO_GPIO_EnablePH15Input(VAOx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_VAO_GPIO_DisablePH15Input(VAOx);
|
||||
}
|
||||
/*! PH15上拉使能 */
|
||||
if(VAO_IO_InitStruct->pullup == FL_ENABLE)
|
||||
{
|
||||
FL_VAO_GPIO_EnablePH15Pullup(VAOx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_VAO_GPIO_DisablePH15Pullup(VAOx);
|
||||
}
|
||||
/*! PH15开漏输出使能 */
|
||||
if(VAO_IO_InitStruct->opendrainOutput == FL_ENABLE)
|
||||
{
|
||||
FL_VAO_GPIO_EnablePH15OpenDrain(VAOx);
|
||||
}
|
||||
else
|
||||
{
|
||||
FL_VAO_GPIO_DisablePH15OpenDrain(VAOx);
|
||||
}
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 根据 VAO_XTLF_StructInit 的配置信息初始化对应外设入口地址的寄存器值
|
||||
* @param VAOx VAOx
|
||||
* @param VAO_XTLF_StructInit 指向一个 @ref FL_VAO_XTLF_InitTypeDef 结构体
|
||||
* 其中包含了外设的相关配置信息.
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
* -FL_PASS 配置成功
|
||||
*/
|
||||
FL_ErrorStatus FL_VAO_XTLF_Init(VAO_Type *VAOx, FL_VAO_XTLF_InitTypeDef *VAO_XTLF_InitStruct)
|
||||
{
|
||||
/* 参数检查 */
|
||||
assert_param(IS_FL_VAO_INSTANCE(VAOx));
|
||||
assert_param(IS_FL_VAO_OUTPUT_DRIVE_ABILITY(VAO_XTLF_InitStruct->driveMode));
|
||||
assert_param(IS_FL_VAO_WORKING_CURRENT(VAO_XTLF_InitStruct->workingCurrentMode));
|
||||
/*使能CDIF*/
|
||||
FL_CDIF_EnableVAOToCPU(CDIF);
|
||||
FL_CDIF_EnableCPUToVAO(CDIF);
|
||||
/*! XTLF工作电流选择 */
|
||||
FL_VAO_XTLF_SetWorkCurrent(VAOx, VAO_XTLF_InitStruct->workingCurrentMode);
|
||||
/*! XTLF输出级驱动能力配置 */
|
||||
FL_VAO_XTLF_SetDriveLevel(VAOx, VAO_XTLF_InitStruct->driveMode);
|
||||
return FL_PASS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置 VAO_IO_StructInit 为默认配置
|
||||
* @param VAO_IO_StructInit 指向需要将值设置为默认配置的结构体 @ref FL_VAO_IO_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_VAO_IO_StructInit(FL_VAO_IO_InitTypeDef *VAO_IO_InitStruct)
|
||||
{
|
||||
VAO_IO_InitStruct->mode = FL_VAO_PH15_MODE_INPUT;
|
||||
VAO_IO_InitStruct->input = FL_ENABLE;
|
||||
VAO_IO_InitStruct->pullup = FL_ENABLE;
|
||||
VAO_IO_InitStruct->opendrainOutput = FL_DISABLE;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 VAO_XTLF_StructInit 为默认配置
|
||||
* @param VAO_XTLF_StructInit 指向需要将值设置为默认配置的结构体 @ref FL_VAO_XTLF_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void FL_VAO_XTLF_StructInit(FL_VAO_XTLF_InitTypeDef *VAO_XTLF_InitStruct)
|
||||
{
|
||||
VAO_XTLF_InitStruct->driveMode = FL_VAO_XTLF_DRIVE_LEVEL_1;
|
||||
VAO_XTLF_InitStruct->workingCurrentMode = FL_VAO_XTLF_WORK_CURRENT_450NA;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_VAO_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_vrefp.c
Normal file
167
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_vrefp.c
Normal file
@ -0,0 +1,167 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_vrefp.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of VREFP FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup VREFP
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#ifdef FL_VREFP_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup VREFP_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_VREFP_INSTANCE(INTANCE) ((INTANCE) == VREFP)
|
||||
|
||||
#define IS_FL_VREFP_VOLTAGETRIM(__VALUE__) (((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_2P0V_TRIM)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_2P5V_TRIM)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_3P0V_TRIM)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_4P5V_TRIM)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_1P5V_TRIM))
|
||||
|
||||
#define IS_FL_VREFP_OUTPUTVOLTAGE(__VALUE__) (((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_2P0V)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_2P5V)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_3P0V)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_4P5V)||\
|
||||
((__VALUE__) == FL_VREFP_OUTPUT_VOLTAGE_1P5V))
|
||||
|
||||
#define IS_FL_VREFP_ENABLEPERIOD(__VALUE__) (((__VALUE__) == FL_VREFP_ENABLE_PERIOD_1MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_4MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_16MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_32MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_64MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_256MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_1000MS)||\
|
||||
((__VALUE__) == FL_VREFP_ENABLE_PERIOD_4000MS))
|
||||
|
||||
#define IS_FL_VREFP_DRIVINGTIME(__VALUE__) (((__VALUE__) == FL_VREFP_DRIVING_TIME_4LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_8LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_16LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_32LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_64LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_128LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_256LSCLK)||\
|
||||
((__VALUE__) == FL_VREFP_DRIVING_TIME_512LSCLK))
|
||||
|
||||
#define IS_FL_VREFP_WORKMODE(__VALUE__) (((__VALUE__) == FL_VREFP_WORK_MODE_CONTINUOUS)||\
|
||||
((__VALUE__) == FL_VREFP_WORK_MODE_PERIODIC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup VREFP_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 关闭VREFP外设总线时钟
|
||||
*
|
||||
* @param VREFPx 外设入口地址
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_VREFP_DeInit(VREFP_Type *VREFPx)
|
||||
{
|
||||
assert_param(IS_VREFP_INSTANCE(VREFPx));
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 VREFP_InitStruct初始化对应外设入口地址的寄存器值.
|
||||
*
|
||||
* @note WWTD使能后将无法关闭，直到下一次芯片复位
|
||||
*
|
||||
* @param VREFPx 外设入口地址
|
||||
*
|
||||
* @param VREFP_InitStruct 指向 @ref FL_VREFP_InitTypeDef 结构体的指针
|
||||
*
|
||||
* @retval ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_VREFP_Init(VREFP_Type *VREFPx, FL_VREFP_InitTypeDef *VREFP_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_VREFP_INSTANCE(VREFPx));
|
||||
assert_param(IS_FL_VREFP_VOLTAGETRIM(VREFP_InitStruct->voltageTrim));
|
||||
assert_param(IS_FL_VREFP_OUTPUTVOLTAGE(VREFP_InitStruct->outputVoltage));
|
||||
assert_param(IS_FL_VREFP_ENABLEPERIOD(VREFP_InitStruct->timeOfPeriod));
|
||||
assert_param(IS_FL_VREFP_DRIVINGTIME(VREFP_InitStruct->timeOfDriving));
|
||||
assert_param(IS_FL_VREFP_WORKMODE(VREFP_InitStruct->mode));
|
||||
/* 开启总线时钟 */
|
||||
FL_CMU_EnableGroup1BusClock(FL_CMU_GROUP1_BUSCLK_PMU);
|
||||
/* 配置VREFP输出电压TRIM值 */
|
||||
FL_VREFP_WriteOutputVoltageTrim(VREFPx, VREFP_InitStruct->voltageTrim);
|
||||
/* 配置VREFP输出电压 */
|
||||
FL_VREFP_SetOutputVoltage(VREFPx, VREFP_InitStruct->outputVoltage);
|
||||
/* 配置输出模式 */
|
||||
FL_VREFP_SetWorkMode(VREFPx, VREFP_InitStruct->mode);
|
||||
/* 间歇模式下使能周期 */
|
||||
FL_VREFP_SetEnablePeriod(VREFPx, VREFP_InitStruct->timeOfPeriod);
|
||||
/* 间歇模式下单次驱动时间 */
|
||||
FL_VREFP_SetDrivingTime(VREFPx, VREFP_InitStruct->timeOfDriving);
|
||||
/* 启动VREFP */
|
||||
FL_VREFP_Enable(VREFPx);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 VREFP_InitStruct 为默认配置
|
||||
*
|
||||
* @param VREFP_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_VREFP_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_VREFP_StructInit(FL_VREFP_InitTypeDef *VREFP_InitStruct)
|
||||
{
|
||||
VREFP_InitStruct->voltageTrim = FL_VREFP_OUTPUT_VOLTAGE_3P0V_TRIM;
|
||||
VREFP_InitStruct->outputVoltage = FL_VREFP_OUTPUT_VOLTAGE_3P0V;
|
||||
VREFP_InitStruct->mode = FL_VREFP_WORK_MODE_CONTINUOUS;
|
||||
VREFP_InitStruct->timeOfPeriod = FL_VREFP_ENABLE_PERIOD_1MS;
|
||||
VREFP_InitStruct->timeOfDriving = FL_VREFP_DRIVING_TIME_4LSCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_VREFP_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
|
||||
128
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_wwdt.c
Normal file
128
LIN Slave/Drivers/FM33LG0xx_FL_Driver/Src/fm33lg0xx_fl_wwdt.c
Normal file
@ -0,0 +1,128 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33lg0xx_fl_wwdt.c
|
||||
* @author FMSH Application Team
|
||||
* @brief Src file of WWDT FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2021] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "fm33lg0xx_fl.h"
|
||||
|
||||
/** @addtogroup FM33LG0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#ifdef FL_WWDT_DRIVER_ENABLED
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup WWDT_FL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDT_INSTANCE(INTANCE) ((INTANCE) == WWDT)
|
||||
|
||||
#define IS_FL_WWDT_OVERFLOWPERIOD(__VALUE__) (((__VALUE__) == FL_WWDT_PERIOD_1CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_4CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_16CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_64CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_128CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_256CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_512CNT)||\
|
||||
((__VALUE__) == FL_WWDT_PERIOD_1024CNT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup WWDT_FL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 关闭WWDT外设总线时钟
|
||||
*
|
||||
* @note WWDT开启不能再关闭，直到下一次复位。低功耗休眠模式下 WWDT 停止运行
|
||||
*
|
||||
* @param WWDTx 外设入口地址
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_WWDT_DeInit(WWDT_Type *WWDTx)
|
||||
{
|
||||
assert_param(IS_WWDT_INSTANCE(WWDTx));
|
||||
return FL_PASS;
|
||||
}
|
||||
/**
|
||||
* @brief 根据 WWDT_InitStruct初始化对应外设入口地址的寄存器值.
|
||||
*
|
||||
* @note WWTD使能后将无法关闭，直到下一次芯片复位
|
||||
*
|
||||
* @param WWDTx 外设入口地址
|
||||
*
|
||||
* @param WWDT_InitStruct 指向 @ref FL_WWDT_InitTypeDef 结构体的指针
|
||||
*
|
||||
* @retval FL_ErrorStatus枚举值
|
||||
* -FL_PASS 配置成功
|
||||
* -FL_FAIL 配置过程发生错误
|
||||
*/
|
||||
FL_ErrorStatus FL_WWDT_Init(WWDT_Type *WWDTx, FL_WWDT_InitTypeDef *WWDT_InitStruct)
|
||||
{
|
||||
FL_ErrorStatus status = FL_PASS;
|
||||
/* 入口参数检查 */
|
||||
assert_param(IS_WWDT_INSTANCE(WWDTx));
|
||||
assert_param(IS_FL_WWDT_OVERFLOWPERIOD(WWDT_InitStruct->overflowPeriod));
|
||||
/* 开启总线时钟 */
|
||||
FL_CMU_EnableGroup2BusClock(FL_CMU_GROUP2_BUSCLK_WWDT);
|
||||
/* 配置独立看门狗溢出周期 */
|
||||
FL_WWDT_SetPeriod(WWDTx, WWDT_InitStruct->overflowPeriod);
|
||||
/* 启动看门狗 */
|
||||
FL_WWDT_Enable(WWDTx);
|
||||
return status;
|
||||
}
|
||||
/**
|
||||
* @brief 设置 WWDT_InitStruct 为默认配置
|
||||
*
|
||||
* @param WWDT_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_WWDT_InitTypeDef 结构体
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FL_WWDT_StructInit(FL_WWDT_InitTypeDef *WWDT_InitStruct)
|
||||
{
|
||||
/* 默认最长溢出周期 */
|
||||
WWDT_InitStruct->overflowPeriod = FL_WWDT_PERIOD_1024CNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FL_WWDT_DRIVER_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1374
LIN Slave/EWARM/Backup of Example.ewd
Normal file
1374
LIN Slave/EWARM/Backup of Example.ewd
Normal file
File diff suppressed because it is too large
Load Diff
1095
LIN Slave/EWARM/Backup of Example.ewp
Normal file
1095
LIN Slave/EWARM/Backup of Example.ewp
Normal file
File diff suppressed because it is too large
Load Diff
1196
LIN Slave/EWARM/Backup of Example.ewt
Normal file
1196
LIN Slave/EWARM/Backup of Example.ewt
Normal file
File diff suppressed because it is too large
Load Diff
1142
LIN Slave/EWARM/Example.dep
Normal file
1142
LIN Slave/EWARM/Example.dep
Normal file
File diff suppressed because it is too large
Load Diff
1615
LIN Slave/EWARM/Example.ewd
Normal file
1615
LIN Slave/EWARM/Example.ewd
Normal file
File diff suppressed because it is too large
Load Diff
1234
LIN Slave/EWARM/Example.ewp
Normal file
1234
LIN Slave/EWARM/Example.ewp
Normal file
File diff suppressed because it is too large
Load Diff
1570
LIN Slave/EWARM/Example.ewt
Normal file
1570
LIN Slave/EWARM/Example.ewt
Normal file
File diff suppressed because it is too large
Load Diff
7
LIN Slave/EWARM/Project.eww
Normal file
7
LIN Slave/EWARM/Project.eww
Normal file
@ -0,0 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\Example.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
40
LIN Slave/EWARM/settings/Example.Example.cspy.bat
Normal file
40
LIN Slave/EWARM/settings/Example.Example.cspy.bat
Normal file
@ -0,0 +1,40 @@
|
||||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM
|
||||
@REM Read about available command line parameters in the C-SPY Debugging
|
||||
@REM Guide. Hints about additional command line parameters that may be
|
||||
@REM useful in specific cases:
|
||||
@REM --download_only Downloads a code image without starting a debug
|
||||
@REM session afterwards.
|
||||
@REM --silent Omits the sign-on message.
|
||||
@REM --timeout Limits the maximum allowed execution time.
|
||||
@REM
|
||||
|
||||
|
||||
@echo off
|
||||
|
||||
if not "%~1" == "" goto debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.general.xcl" --backend -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.driver.xcl"
|
||||
|
||||
@echo off
|
||||
goto end
|
||||
|
||||
:debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.general.xcl" "--debug_file=%~1" --backend -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.driver.xcl"
|
||||
|
||||
@echo off
|
||||
:end
|
||||
31
LIN Slave/EWARM/settings/Example.Example.cspy.ps1
Normal file
31
LIN Slave/EWARM/settings/Example.Example.cspy.ps1
Normal file
@ -0,0 +1,31 @@
|
||||
param([String]$debugfile = "");
|
||||
|
||||
# This powershell file has been generated by the IAR Embedded Workbench
|
||||
# C - SPY Debugger, as an aid to preparing a command line for running
|
||||
# the cspybat command line utility using the appropriate settings.
|
||||
#
|
||||
# Note that this file is generated every time a new debug session
|
||||
# is initialized, so you may want to move or rename the file before
|
||||
# making changes.
|
||||
#
|
||||
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
|
||||
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
|
||||
#
|
||||
# Read about available command line parameters in the C - SPY Debugging
|
||||
# Guide. Hints about additional command line parameters that may be
|
||||
# useful in specific cases :
|
||||
# --download_only Downloads a code image without starting a debug
|
||||
# session afterwards.
|
||||
# --silent Omits the sign - on message.
|
||||
# --timeout Limits the maximum allowed execution time.
|
||||
#
|
||||
|
||||
|
||||
if ($debugfile -eq "")
|
||||
{
|
||||
& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.general.xcl" --backend -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.driver.xcl"
|
||||
}
|
||||
else
|
||||
{
|
||||
& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.general.xcl" --debug_file=$debugfile --backend -f "F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\settings\Example.Example.driver.xcl"
|
||||
}
|
||||
29
LIN Slave/EWARM/settings/Example.Example.driver.xcl
Normal file
29
LIN Slave/EWARM/settings/Example.Example.driver.xcl
Normal file
@ -0,0 +1,29 @@
|
||||
"--endian=little"
|
||||
|
||||
"--cpu=SC000"
|
||||
|
||||
"--fpu=None"
|
||||
|
||||
"-p"
|
||||
|
||||
"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\FMSH\FM33LG02x.ddf"
|
||||
|
||||
"--semihosting"
|
||||
|
||||
"--device=FM33LG02x"
|
||||
|
||||
"--drv_communication=USB0"
|
||||
|
||||
"--drv_interface_speed=auto"
|
||||
|
||||
"--jlink_initial_speed=10000"
|
||||
|
||||
"--jlink_reset_strategy=0,2"
|
||||
|
||||
"--drv_interface=SWD"
|
||||
|
||||
"--drv_catch_exceptions=0x000"
|
||||
|
||||
|
||||
|
||||
|
||||
13
LIN Slave/EWARM/settings/Example.Example.general.xcl
Normal file
13
LIN Slave/EWARM/settings/Example.Example.general.xcl
Normal file
@ -0,0 +1,13 @@
|
||||
"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll"
|
||||
|
||||
"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armJLINK.dll"
|
||||
|
||||
"F:\FCB_project\RP-01\anmo\code\LIN Slave\EWARM\Example\Exe\Example.out"
|
||||
|
||||
--plugin="E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armbat.dll"
|
||||
|
||||
--flash_loader="E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\flashloader\FMSH\FM33LG02x.board"
|
||||
|
||||
|
||||
|
||||
|
||||
13
LIN Slave/EWARM/settings/Example.crun
Normal file
13
LIN Slave/EWARM/settings/Example.crun
Normal file
@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<crun>
|
||||
<version>1</version>
|
||||
<filter_entries>
|
||||
<filter index="0" type="default">
|
||||
<type>*</type>
|
||||
<start_file>*</start_file>
|
||||
<end_file>*</end_file>
|
||||
<action_debugger>0</action_debugger>
|
||||
<action_log>1</action_log>
|
||||
</filter>
|
||||
</filter_entries>
|
||||
</crun>
|
||||
930
LIN Slave/EWARM/settings/Example.dbgdt
Normal file
930
LIN Slave/EWARM/settings/Example.dbgdt
Normal file
File diff suppressed because one or more lines are too long
130
LIN Slave/EWARM/settings/Example.dni
Normal file
130
LIN Slave/EWARM/settings/Example.dni
Normal file
@ -0,0 +1,130 @@
|
||||
[Stack]
|
||||
FillEnabled=0
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnLogOnly=1
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[DebugChecksum]
|
||||
Checksum=-214169912
|
||||
[CodeCoverage]
|
||||
Enabled=_ 0
|
||||
[DriverProfiling]
|
||||
Enabled=0
|
||||
Mode=1
|
||||
Graph=0
|
||||
Symbiont=0
|
||||
Exclusions=
|
||||
[Exceptions]
|
||||
StopOnUncaught=_ 0
|
||||
StopOnThrow=_ 0
|
||||
[CallStack]
|
||||
ShowArgs=0
|
||||
[Disassembly]
|
||||
MixedMode=1
|
||||
[Interrupts]
|
||||
Enabled=1
|
||||
[MemConfig]
|
||||
Base=1
|
||||
Manual=0
|
||||
Ddf=1
|
||||
TypeViol=0
|
||||
Stop=1
|
||||
[Trace1]
|
||||
Enabled=0
|
||||
ShowSource=1
|
||||
[Simulator]
|
||||
Freq=10000000
|
||||
MultiCoreRunAll=1
|
||||
[Trace2]
|
||||
Enabled=0
|
||||
ShowSource=0
|
||||
[SWOTraceWindow]
|
||||
PcSampling=0
|
||||
InterruptLogs=0
|
||||
ForcedTimeStamps=0
|
||||
EventCPI=0
|
||||
EventEXC=0
|
||||
EventFOLD=0
|
||||
EventLSU=0
|
||||
EventSLEEP=0
|
||||
[PowerLog]
|
||||
Title_0=I0
|
||||
Symbol_0=0 4 90
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
LiveEnabled=0
|
||||
LiveFile=PowerLogLive.log
|
||||
[DataLog]
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
SumEnabled=0
|
||||
ShowTimeSum=1
|
||||
[EventLog]
|
||||
Title_0=Ch3
|
||||
Symbol_0=0 4 1
|
||||
Title_1=Ch2
|
||||
Symbol_1=0 4 1
|
||||
Title_2=Ch1
|
||||
Symbol_2=0 4 1
|
||||
Title_3=Ch0
|
||||
Symbol_3=0 4 1
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
SumEnabled=0
|
||||
ShowTimeSum=1
|
||||
SumSortOrder=0
|
||||
[InterruptLog]
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
SumEnabled=0
|
||||
ShowTimeSum=1
|
||||
SumSortOrder=0
|
||||
[Log file]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
Category=_ 0
|
||||
[TermIOLog]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
[CallStackLog]
|
||||
Enabled=0
|
||||
[CallStackStripe]
|
||||
ShowTiming=1
|
||||
[JLinkDriver]
|
||||
CStepIntDis=_ 0
|
||||
[SWOTraceHWSettings]
|
||||
OverrideDefaultClocks=0
|
||||
CpuClock=72000000
|
||||
ClockAutoDetect=0
|
||||
ClockWanted=2000000
|
||||
JtagSpeed=2000000
|
||||
Prescaler=36
|
||||
TimeStampPrescIndex=0
|
||||
TimeStampPrescData=0
|
||||
PcSampCYCTAP=1
|
||||
PcSampPOSTCNT=15
|
||||
PcSampIndex=0
|
||||
DataLogMode=0
|
||||
ITMportsEnable=0
|
||||
ITMportsTermIO=0
|
||||
ITMportsLogFile=0
|
||||
ITMlogFile=$PROJ_DIR$\ITM.log
|
||||
[PowerProbe]
|
||||
Frequency=10000
|
||||
Probe0=I0
|
||||
ProbeSetup0=2 1 1 2 0 0
|
||||
[Disassemble mode]
|
||||
mode=0
|
||||
[Breakpoints2]
|
||||
Count=0
|
||||
[Aliases]
|
||||
Count=0
|
||||
SuppressDialog=0
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user